Re: [PATCH v2 2/2] Intel-IOMMU, intr-remap: source-id checking

[ebiederm@xmission.com (Eric W. Biederman)]

"Han, Weidong" <weidong.han@intel.com> writes:

> Ingo Molnar wrote:
>> * Eric W. Biederman <ebiederm@xmission.com> wrote:
>> 
>>> Not finding an upstream pcie_bridge and then concluding we are a
>>> pcie device seems bogus. 
>>> 
>
> If device is pcie, pci_find_upstream_pcie_bridge() will return
> NULL. For root complex integrated device, it won't find upstream
> bridge, and also return NULL. What's more, pcie device and root
> complex integrated device will be handled as the same way to set
> sid, so I mix them here. But it also returns NULL for busted
> hardware. I think no parent bus can be considered Root Complex
> integrated device, right? If so, I think can handle it as follows:

I have problems with pci_find_upstream_pcie_bridge.  The
name is actively misleading about what that function does.
Returning a pci_to_pci bridge is strongly counter intuitive
give that name.

Can we change it to pci_find_upstream_pcie_to_pci_bridge.
Returning NULL in all cases when there is not an upstream
pcie_to_pci bridge.

For the set_sid case that is ideal.  For the other cases in
intel-iommu.c it may be a problem.  Is it even possible to have a
genuine pci device not behind a pcie to pci bridge on an intel
chipset with this iommu?


> 	...
> 	if (dev->is_pcie || !dev->bus->parent) {
> 		set_irte_sid(...);
> 		return 0;
> 	}
>
> 	bridge = pci_find_upstream_pcie_bridge(dev);
> 	if (bridge) {
> 		if (bridge->is_pcie) /* PCIE-to-PCI/PCIx bridge */
> 			set_irte_sid(...);
> 		else /* legacy PCI bridge */
> 			set_irte_sid(..);
> 	}
>
> 	return 0;
>
>>> Why if we do have an upstream pcie bridge do we only want to do a
>>> bus range verification instead of checking just for the bus
>>>> devfn?
>>> 
>>> The legacy PCI case seems even stranger.
>
> Why? If a PCI device isn't connected to a PCIe bridge, it should be a legacy bridge.

I am not deep in the IOV specification at the moment.  I am mostly
wondering why we pick the parts we pick to verify.  I recall
bus and devfn being on the pcie packets so that makes sense.

Why would we ever want to do something different?  Does a pcie to pci
bridge do something different in it's translation?

Eric