* [PATCH v3 0/4] Rework BPI-R2-Pro PCIe clock topology
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
Signed-off-by: David Heidelberg <david@ixit.cz>
---
Changes in v3:
- Added commit extending the clock list with pipe clock for rk3568.
- Updated the clock list in BPI-R2-Pro dts. (Charalampos)
- Link to v2: https://lore.kernel.org/r/20260303-rk3568-bri-r2-pro-fix-pcie-v2-0-04665e55d5a8@ixit.cz
Changes in v2:
- Added patches for solving the topology issues and on top of these
original patch. (Heiko)
- Link to v1: https://lore.kernel.org/r/20260301-rk3568-bri-r2-pro-fix-pcie-v1-1-b9ed318b4a77@ixit.cz
---
David Heidelberg (4):
arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes
arm64: dts: rockchip: Introduce the reference PCIe clk generator for BPI-R2-Pro
arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro
arm64: dts: rockchip: Define PCIe clock pinctrl for BPI-R2-Pro
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 59 +++++++++++++++++-----
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 +++--
2 files changed, 53 insertions(+), 18 deletions(-)
---
base-commit: 3fa5e5702a82d259897bd7e209469bc06368bf31
change-id: 20260222-rk3568-bri-r2-pro-fix-pcie-355b020dd0d2
Best regards,
--
David Heidelberg <david@ixit.cz>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v3 0/4] Rework BPI-R2-Pro PCIe clock topology
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
Signed-off-by: David Heidelberg <david@ixit.cz>
---
Changes in v3:
- Added commit extending the clock list with pipe clock for rk3568.
- Updated the clock list in BPI-R2-Pro dts. (Charalampos)
- Link to v2: https://lore.kernel.org/r/20260303-rk3568-bri-r2-pro-fix-pcie-v2-0-04665e55d5a8@ixit.cz
Changes in v2:
- Added patches for solving the topology issues and on top of these
original patch. (Heiko)
- Link to v1: https://lore.kernel.org/r/20260301-rk3568-bri-r2-pro-fix-pcie-v1-1-b9ed318b4a77@ixit.cz
---
David Heidelberg (4):
arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes
arm64: dts: rockchip: Introduce the reference PCIe clk generator for BPI-R2-Pro
arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro
arm64: dts: rockchip: Define PCIe clock pinctrl for BPI-R2-Pro
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 59 +++++++++++++++++-----
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 +++--
2 files changed, 53 insertions(+), 18 deletions(-)
---
base-commit: 3fa5e5702a82d259897bd7e209469bc06368bf31
change-id: 20260222-rk3568-bri-r2-pro-fix-pcie-355b020dd0d2
Best regards,
--
David Heidelberg <david@ixit.cz>
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v3 1/4] arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes
2026-03-03 19:52 ` David Heidelberg via B4 Relay
(?)
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
-1 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
These clocks are used by PCIe lanes, but we're missing from the
definition.
Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 658097ed69714..3bc653f027f1f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 {
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
- <&cru CLK_PCIE30X1_AUX_NDFT>;
+ <&cru CLK_PCIE30X1_AUX_NDFT>,
+ <&cru CLK_PCIE30X1_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
+ "aclk_dbi", "pclk", "aux",
+ "pipe";
device_type = "pci";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
@@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 {
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
- <&cru CLK_PCIE30X2_AUX_NDFT>;
+ <&cru CLK_PCIE30X2_AUX_NDFT>,
+ <&cru CLK_PCIE30X2_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
+ "aclk_dbi", "pclk", "aux",
+ "pipe";
device_type = "pci";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
--
2.53.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 1/4] arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
These clocks are used by PCIe lanes, but we're missing from the
definition.
Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 658097ed69714..3bc653f027f1f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 {
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
- <&cru CLK_PCIE30X1_AUX_NDFT>;
+ <&cru CLK_PCIE30X1_AUX_NDFT>,
+ <&cru CLK_PCIE30X1_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
+ "aclk_dbi", "pclk", "aux",
+ "pipe";
device_type = "pci";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
@@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 {
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
- <&cru CLK_PCIE30X2_AUX_NDFT>;
+ <&cru CLK_PCIE30X2_AUX_NDFT>,
+ <&cru CLK_PCIE30X2_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
+ "aclk_dbi", "pclk", "aux",
+ "pipe";
device_type = "pci";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
--
2.53.0
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 1/4] arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
These clocks are used by PCIe lanes, but we're missing from the
definition.
Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 658097ed69714..3bc653f027f1f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 {
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
- <&cru CLK_PCIE30X1_AUX_NDFT>;
+ <&cru CLK_PCIE30X1_AUX_NDFT>,
+ <&cru CLK_PCIE30X1_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
+ "aclk_dbi", "pclk", "aux",
+ "pipe";
device_type = "pci";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
@@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 {
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
- <&cru CLK_PCIE30X2_AUX_NDFT>;
+ <&cru CLK_PCIE30X2_AUX_NDFT>,
+ <&cru CLK_PCIE30X2_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
+ "aclk_dbi", "pclk", "aux",
+ "pipe";
device_type = "pci";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
--
2.53.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v3 1/4] arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes
2026-03-03 19:52 ` David Heidelberg via B4 Relay
@ 2026-03-04 0:48 ` Shawn Lin
-1 siblings, 0 replies; 19+ messages in thread
From: Shawn Lin @ 2026-03-04 0:48 UTC (permalink / raw)
To: david, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Frank Wunderlich
Cc: shawn.lin, Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Hi David
在 2026/03/04 星期三 3:52, David Heidelberg via B4 Relay 写道:
> From: David Heidelberg <david@ixit.cz>
>
> These clocks are used by PCIe lanes, but we're missing from the
> definition.
>
Thanks for catching this.
Since you're already working on the PCIe clock definitions, would you
mind taking the opportunity to also add the missing pcie2x1 pipe clock
to the rk356x-base.dtsi in the same patch? This would keep the fixes
complete and consistent.
> Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 658097ed69714..3bc653f027f1f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 {
> bus-range = <0x10 0x1f>;
> clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
> <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
> - <&cru CLK_PCIE30X1_AUX_NDFT>;
> + <&cru CLK_PCIE30X1_AUX_NDFT>,
> + <&cru CLK_PCIE30X1_PIPE_DFT>;
> clock-names = "aclk_mst", "aclk_slv",
> - "aclk_dbi", "pclk", "aux";
> + "aclk_dbi", "pclk", "aux",
> + "pipe";
> device_type = "pci";
> interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> @@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 {
> bus-range = <0x20 0x2f>;
> clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> - <&cru CLK_PCIE30X2_AUX_NDFT>;
> + <&cru CLK_PCIE30X2_AUX_NDFT>,
> + <&cru CLK_PCIE30X2_PIPE_DFT>;
> clock-names = "aclk_mst", "aclk_slv",
> - "aclk_dbi", "pclk", "aux";
> + "aclk_dbi", "pclk", "aux",
> + "pipe";
> device_type = "pci";
> interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 1/4] arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes
@ 2026-03-04 0:48 ` Shawn Lin
0 siblings, 0 replies; 19+ messages in thread
From: Shawn Lin @ 2026-03-04 0:48 UTC (permalink / raw)
To: david, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Frank Wunderlich
Cc: shawn.lin, Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Hi David
在 2026/03/04 星期三 3:52, David Heidelberg via B4 Relay 写道:
> From: David Heidelberg <david@ixit.cz>
>
> These clocks are used by PCIe lanes, but we're missing from the
> definition.
>
Thanks for catching this.
Since you're already working on the PCIe clock definitions, would you
mind taking the opportunity to also add the missing pcie2x1 pipe clock
to the rk356x-base.dtsi in the same patch? This would keep the fixes
complete and consistent.
> Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 658097ed69714..3bc653f027f1f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 {
> bus-range = <0x10 0x1f>;
> clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
> <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
> - <&cru CLK_PCIE30X1_AUX_NDFT>;
> + <&cru CLK_PCIE30X1_AUX_NDFT>,
> + <&cru CLK_PCIE30X1_PIPE_DFT>;
> clock-names = "aclk_mst", "aclk_slv",
> - "aclk_dbi", "pclk", "aux";
> + "aclk_dbi", "pclk", "aux",
> + "pipe";
> device_type = "pci";
> interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> @@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 {
> bus-range = <0x20 0x2f>;
> clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> - <&cru CLK_PCIE30X2_AUX_NDFT>;
> + <&cru CLK_PCIE30X2_AUX_NDFT>,
> + <&cru CLK_PCIE30X2_PIPE_DFT>;
> clock-names = "aclk_mst", "aclk_slv",
> - "aclk_dbi", "pclk", "aux";
> + "aclk_dbi", "pclk", "aux",
> + "pipe";
> device_type = "pci";
> interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] arm64: dts: rockchip: Introduce the reference PCIe clk generator for BPI-R2-Pro
2026-03-03 19:52 ` David Heidelberg via B4 Relay
(?)
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
-1 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
This clocks provides for both PCIe lanes. In following commit will be
utilized by PCIe clock.
Most likely PI6CG33602C or some variant of it.
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index 4d3ebe50b90ba..d02b82c5f979a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -114,6 +114,12 @@ pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
};
/* pi6c pcie clock generator feeds both ports */
+ pcie_refclk_gen: pcie-refclk-gen-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
--
2.53.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 2/4] arm64: dts: rockchip: Introduce the reference PCIe clk generator for BPI-R2-Pro
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
This clocks provides for both PCIe lanes. In following commit will be
utilized by PCIe clock.
Most likely PI6CG33602C or some variant of it.
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index 4d3ebe50b90ba..d02b82c5f979a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -114,6 +114,12 @@ pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
};
/* pi6c pcie clock generator feeds both ports */
+ pcie_refclk_gen: pcie-refclk-gen-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
--
2.53.0
_______________________________________________
Linux-rockchip mailing list
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 2/4] arm64: dts: rockchip: Introduce the reference PCIe clk generator for BPI-R2-Pro
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
This clocks provides for both PCIe lanes. In following commit will be
utilized by PCIe clock.
Most likely PI6CG33602C or some variant of it.
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index 4d3ebe50b90ba..d02b82c5f979a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -114,6 +114,12 @@ pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
};
/* pi6c pcie clock generator feeds both ports */
+ pcie_refclk_gen: pcie-refclk-gen-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
--
2.53.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 3/4] arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro
2026-03-03 19:52 ` David Heidelberg via B4 Relay
(?)
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
-1 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
Describe properly PCIe clock, which allows us correct the
toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as
supply) and adding the clock dependency in the PCIe nodes.
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++-------
1 file changed, 33 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index d02b82c5f979a..3cdea9456a28c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock {
clock-frequency = <100000000>;
};
- vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <200000>;
- vin-supply = <&vcc5v0_sys>;
+ pcie_refclk: pcie-refclk-clock {
+ compatible = "gpio-gate-clock";
+ clocks = <&pcie_refclk_gen>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
};
- /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
vcc3v3_minipcie: regulator-vcc3v3-minipcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_minipcie";
@@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie {
pinctrl-names = "default";
pinctrl-0 = <&minipcie_enable_h>;
startup-delay-us = <50000>;
- vin-supply = <&vcc3v3_pi6c_05>;
+ vin-supply = <&vcc3v3_sys>;
};
- /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
vcc3v3_ngff: regulator-vcc3v3-ngff {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_ngff";
@@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff {
pinctrl-names = "default";
pinctrl-0 = <&ngffpcie_enable_h>;
startup-delay-us = <50000>;
- vin-supply = <&vcc3v3_pi6c_05>;
+ vin-supply = <&vcc3v3_sys>;
};
vcc5v0_usb: regulator-vcc5v0-usb {
@@ -586,12 +580,24 @@ rgmii_phy1: ethernet-phy@0 {
&pcie30phy {
data-lanes = <1 2>;
- phy-supply = <&vcc3v3_pi6c_05>;
+
status = "okay";
};
&pcie3x1 {
/* M.2 slot */
+ /*
+ * The board has a gpio-controlled "pcie_refclk" generator,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
+ <&cru CLK_PCIE30X1_AUX_NDFT>,
+ <&cru CLK_PCIE30X1_PIPE_DFT>,
+ <&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux",
+ "pipe", "ref";
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&ngffpcie_reset_h>;
@@ -602,6 +608,19 @@ &pcie3x1 {
&pcie3x2 {
/* mPCIe slot */
+ /*
+ * The board has a gpio-controlled "pcie_refclk" generator,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ <&cru CLK_PCIE30X2_AUX_NDFT>,
+ <&cru CLK_PCIE30X2_PIPE_DFT>,
+ <&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux",
+ "pipe", "ref";
+
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&minipcie_reset_h>;
--
2.53.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 3/4] arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
Describe properly PCIe clock, which allows us correct the
toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as
supply) and adding the clock dependency in the PCIe nodes.
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++-------
1 file changed, 33 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index d02b82c5f979a..3cdea9456a28c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock {
clock-frequency = <100000000>;
};
- vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <200000>;
- vin-supply = <&vcc5v0_sys>;
+ pcie_refclk: pcie-refclk-clock {
+ compatible = "gpio-gate-clock";
+ clocks = <&pcie_refclk_gen>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
};
- /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
vcc3v3_minipcie: regulator-vcc3v3-minipcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_minipcie";
@@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie {
pinctrl-names = "default";
pinctrl-0 = <&minipcie_enable_h>;
startup-delay-us = <50000>;
- vin-supply = <&vcc3v3_pi6c_05>;
+ vin-supply = <&vcc3v3_sys>;
};
- /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
vcc3v3_ngff: regulator-vcc3v3-ngff {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_ngff";
@@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff {
pinctrl-names = "default";
pinctrl-0 = <&ngffpcie_enable_h>;
startup-delay-us = <50000>;
- vin-supply = <&vcc3v3_pi6c_05>;
+ vin-supply = <&vcc3v3_sys>;
};
vcc5v0_usb: regulator-vcc5v0-usb {
@@ -586,12 +580,24 @@ rgmii_phy1: ethernet-phy@0 {
&pcie30phy {
data-lanes = <1 2>;
- phy-supply = <&vcc3v3_pi6c_05>;
+
status = "okay";
};
&pcie3x1 {
/* M.2 slot */
+ /*
+ * The board has a gpio-controlled "pcie_refclk" generator,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
+ <&cru CLK_PCIE30X1_AUX_NDFT>,
+ <&cru CLK_PCIE30X1_PIPE_DFT>,
+ <&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux",
+ "pipe", "ref";
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&ngffpcie_reset_h>;
@@ -602,6 +608,19 @@ &pcie3x1 {
&pcie3x2 {
/* mPCIe slot */
+ /*
+ * The board has a gpio-controlled "pcie_refclk" generator,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ <&cru CLK_PCIE30X2_AUX_NDFT>,
+ <&cru CLK_PCIE30X2_PIPE_DFT>,
+ <&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux",
+ "pipe", "ref";
+
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&minipcie_reset_h>;
--
2.53.0
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 3/4] arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
Describe properly PCIe clock, which allows us correct the
toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as
supply) and adding the clock dependency in the PCIe nodes.
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++-------
1 file changed, 33 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index d02b82c5f979a..3cdea9456a28c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock {
clock-frequency = <100000000>;
};
- vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <200000>;
- vin-supply = <&vcc5v0_sys>;
+ pcie_refclk: pcie-refclk-clock {
+ compatible = "gpio-gate-clock";
+ clocks = <&pcie_refclk_gen>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
};
- /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
vcc3v3_minipcie: regulator-vcc3v3-minipcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_minipcie";
@@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie {
pinctrl-names = "default";
pinctrl-0 = <&minipcie_enable_h>;
startup-delay-us = <50000>;
- vin-supply = <&vcc3v3_pi6c_05>;
+ vin-supply = <&vcc3v3_sys>;
};
- /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
vcc3v3_ngff: regulator-vcc3v3-ngff {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_ngff";
@@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff {
pinctrl-names = "default";
pinctrl-0 = <&ngffpcie_enable_h>;
startup-delay-us = <50000>;
- vin-supply = <&vcc3v3_pi6c_05>;
+ vin-supply = <&vcc3v3_sys>;
};
vcc5v0_usb: regulator-vcc5v0-usb {
@@ -586,12 +580,24 @@ rgmii_phy1: ethernet-phy@0 {
&pcie30phy {
data-lanes = <1 2>;
- phy-supply = <&vcc3v3_pi6c_05>;
+
status = "okay";
};
&pcie3x1 {
/* M.2 slot */
+ /*
+ * The board has a gpio-controlled "pcie_refclk" generator,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
+ <&cru CLK_PCIE30X1_AUX_NDFT>,
+ <&cru CLK_PCIE30X1_PIPE_DFT>,
+ <&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux",
+ "pipe", "ref";
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&ngffpcie_reset_h>;
@@ -602,6 +608,19 @@ &pcie3x1 {
&pcie3x2 {
/* mPCIe slot */
+ /*
+ * The board has a gpio-controlled "pcie_refclk" generator,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ <&cru CLK_PCIE30X2_AUX_NDFT>,
+ <&cru CLK_PCIE30X2_PIPE_DFT>,
+ <&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux",
+ "pipe", "ref";
+
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&minipcie_reset_h>;
--
2.53.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v3 3/4] arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro
2026-03-03 19:52 ` David Heidelberg via B4 Relay
@ 2026-03-03 20:13 ` Charalampos Mitrodimas
-1 siblings, 0 replies; 19+ messages in thread
From: Charalampos Mitrodimas @ 2026-03-03 20:13 UTC (permalink / raw)
To: David Heidelberg via B4 Relay
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich, david, Martin Filla, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
David Heidelberg via B4 Relay <devnull+david.ixit.cz@kernel.org> writes:
> From: David Heidelberg <david@ixit.cz>
>
> Describe properly PCIe clock, which allows us correct the
^^^^^^ ^^
Typo/missing words?
> toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as
^^^^^^
Typo?
> supply) and adding the clock dependency in the PCIe nodes.
>
> Suggested-by: Heiko Stuebner <heiko@sntech.de>
> Tested-by: Martin Filla <freebsd@sysctl.cz>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++-------
> 1 file changed, 33 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> index d02b82c5f979a..3cdea9456a28c 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> @@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock {
> clock-frequency = <100000000>;
> };
>
> - vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
> - compatible = "regulator-fixed";
> - regulator-name = "vcc3v3_pcie";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - enable-active-high;
> - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> - startup-delay-us = <200000>;
> - vin-supply = <&vcc5v0_sys>;
> + pcie_refclk: pcie-refclk-clock {
> + compatible = "gpio-gate-clock";
> + clocks = <&pcie_refclk_gen>;
> + #clock-cells = <0>;
> + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> };
>
> - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
> vcc3v3_minipcie: regulator-vcc3v3-minipcie {
> compatible = "regulator-fixed";
> regulator-name = "vcc3v3_minipcie";
> @@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie {
> pinctrl-names = "default";
> pinctrl-0 = <&minipcie_enable_h>;
> startup-delay-us = <50000>;
> - vin-supply = <&vcc3v3_pi6c_05>;
> + vin-supply = <&vcc3v3_sys>;
> };
>
> - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
> vcc3v3_ngff: regulator-vcc3v3-ngff {
> compatible = "regulator-fixed";
> regulator-name = "vcc3v3_ngff";
> @@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff {
> pinctrl-names = "default";
> pinctrl-0 = <&ngffpcie_enable_h>;
> startup-delay-us = <50000>;
> - vin-supply = <&vcc3v3_pi6c_05>;
> + vin-supply = <&vcc3v3_sys>;
> };
>
> vcc5v0_usb: regulator-vcc5v0-usb {
> @@ -586,12 +580,24 @@ rgmii_phy1: ethernet-phy@0 {
>
> &pcie30phy {
> data-lanes = <1 2>;
> - phy-supply = <&vcc3v3_pi6c_05>;
> +
> status = "okay";
> };
>
> &pcie3x1 {
> /* M.2 slot */
> + /*
> + * The board has a gpio-controlled "pcie_refclk" generator,
> + * so add it to the list of clocks.
> + */
> + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
> + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
> + <&cru CLK_PCIE30X1_AUX_NDFT>,
> + <&cru CLK_PCIE30X1_PIPE_DFT>,
> + <&pcie_refclk>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk", "aux",
> + "pipe", "ref";
> num-lanes = <1>;
> pinctrl-names = "default";
> pinctrl-0 = <&ngffpcie_reset_h>;
> @@ -602,6 +608,19 @@ &pcie3x1 {
>
> &pcie3x2 {
> /* mPCIe slot */
> + /*
> + * The board has a gpio-controlled "pcie_refclk" generator,
> + * so add it to the list of clocks.
> + */
> + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> + <&cru CLK_PCIE30X2_AUX_NDFT>,
> + <&cru CLK_PCIE30X2_PIPE_DFT>,
> + <&pcie_refclk>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk", "aux",
> + "pipe", "ref";
> +
> num-lanes = <1>;
> pinctrl-names = "default";
> pinctrl-0 = <&minipcie_reset_h>;
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v3 3/4] arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro
@ 2026-03-03 20:13 ` Charalampos Mitrodimas
0 siblings, 0 replies; 19+ messages in thread
From: Charalampos Mitrodimas @ 2026-03-03 20:13 UTC (permalink / raw)
To: David Heidelberg via B4 Relay
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich, david, Martin Filla, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
David Heidelberg via B4 Relay <devnull+david.ixit.cz@kernel.org> writes:
> From: David Heidelberg <david@ixit.cz>
>
> Describe properly PCIe clock, which allows us correct the
^^^^^^ ^^
Typo/missing words?
> toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as
^^^^^^
Typo?
> supply) and adding the clock dependency in the PCIe nodes.
>
> Suggested-by: Heiko Stuebner <heiko@sntech.de>
> Tested-by: Martin Filla <freebsd@sysctl.cz>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++-------
> 1 file changed, 33 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> index d02b82c5f979a..3cdea9456a28c 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> @@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock {
> clock-frequency = <100000000>;
> };
>
> - vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
> - compatible = "regulator-fixed";
> - regulator-name = "vcc3v3_pcie";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - enable-active-high;
> - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> - startup-delay-us = <200000>;
> - vin-supply = <&vcc5v0_sys>;
> + pcie_refclk: pcie-refclk-clock {
> + compatible = "gpio-gate-clock";
> + clocks = <&pcie_refclk_gen>;
> + #clock-cells = <0>;
> + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> };
>
> - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
> vcc3v3_minipcie: regulator-vcc3v3-minipcie {
> compatible = "regulator-fixed";
> regulator-name = "vcc3v3_minipcie";
> @@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie {
> pinctrl-names = "default";
> pinctrl-0 = <&minipcie_enable_h>;
> startup-delay-us = <50000>;
> - vin-supply = <&vcc3v3_pi6c_05>;
> + vin-supply = <&vcc3v3_sys>;
> };
>
> - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
> vcc3v3_ngff: regulator-vcc3v3-ngff {
> compatible = "regulator-fixed";
> regulator-name = "vcc3v3_ngff";
> @@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff {
> pinctrl-names = "default";
> pinctrl-0 = <&ngffpcie_enable_h>;
> startup-delay-us = <50000>;
> - vin-supply = <&vcc3v3_pi6c_05>;
> + vin-supply = <&vcc3v3_sys>;
> };
>
> vcc5v0_usb: regulator-vcc5v0-usb {
> @@ -586,12 +580,24 @@ rgmii_phy1: ethernet-phy@0 {
>
> &pcie30phy {
> data-lanes = <1 2>;
> - phy-supply = <&vcc3v3_pi6c_05>;
> +
> status = "okay";
> };
>
> &pcie3x1 {
> /* M.2 slot */
> + /*
> + * The board has a gpio-controlled "pcie_refclk" generator,
> + * so add it to the list of clocks.
> + */
> + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
> + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
> + <&cru CLK_PCIE30X1_AUX_NDFT>,
> + <&cru CLK_PCIE30X1_PIPE_DFT>,
> + <&pcie_refclk>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk", "aux",
> + "pipe", "ref";
> num-lanes = <1>;
> pinctrl-names = "default";
> pinctrl-0 = <&ngffpcie_reset_h>;
> @@ -602,6 +608,19 @@ &pcie3x1 {
>
> &pcie3x2 {
> /* mPCIe slot */
> + /*
> + * The board has a gpio-controlled "pcie_refclk" generator,
> + * so add it to the list of clocks.
> + */
> + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> + <&cru CLK_PCIE30X2_AUX_NDFT>,
> + <&cru CLK_PCIE30X2_PIPE_DFT>,
> + <&pcie_refclk>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk", "aux",
> + "pipe", "ref";
> +
> num-lanes = <1>;
> pinctrl-names = "default";
> pinctrl-0 = <&minipcie_reset_h>;
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 4/4] arm64: dts: rockchip: Define PCIe clock pinctrl for BPI-R2-Pro
2026-03-03 19:52 ` David Heidelberg via B4 Relay
(?)
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
-1 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
Without configuring the PCIe clock enable pin as an output, it
remains floating in input state. Some operating systems that rely
on correct pin settings may fail to boot as a result.
Fixes: 86973ae0355b ("arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro")
Reported-by: Martin Filla <freebsd@sysctl.cz> # reported by private message
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index 3cdea9456a28c..95cf4a6236048 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -125,6 +125,8 @@ pcie_refclk: pcie-refclk-clock {
clocks = <&pcie_refclk_gen>;
#clock-cells = <0>;
enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pcie_clkreq_h>;
+ pinctrl-names = "default";
};
vcc3v3_minipcie: regulator-vcc3v3-minipcie {
@@ -652,6 +654,10 @@ ir_receiver_pin: ir-receiver-pin {
};
pcie {
+ pcie_clkreq_h: pcie-clkreq-h {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+
minipcie_enable_h: minipcie-enable-h {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
};
--
2.53.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 4/4] arm64: dts: rockchip: Define PCIe clock pinctrl for BPI-R2-Pro
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
Without configuring the PCIe clock enable pin as an output, it
remains floating in input state. Some operating systems that rely
on correct pin settings may fail to boot as a result.
Fixes: 86973ae0355b ("arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro")
Reported-by: Martin Filla <freebsd@sysctl.cz> # reported by private message
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index 3cdea9456a28c..95cf4a6236048 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -125,6 +125,8 @@ pcie_refclk: pcie-refclk-clock {
clocks = <&pcie_refclk_gen>;
#clock-cells = <0>;
enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pcie_clkreq_h>;
+ pinctrl-names = "default";
};
vcc3v3_minipcie: regulator-vcc3v3-minipcie {
@@ -652,6 +654,10 @@ ir_receiver_pin: ir-receiver-pin {
};
pcie {
+ pcie_clkreq_h: pcie-clkreq-h {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+
minipcie_enable_h: minipcie-enable-h {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
};
--
2.53.0
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v3 4/4] arm64: dts: rockchip: Define PCIe clock pinctrl for BPI-R2-Pro
@ 2026-03-03 19:52 ` David Heidelberg via B4 Relay
0 siblings, 0 replies; 19+ messages in thread
From: David Heidelberg via B4 Relay @ 2026-03-03 19:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Frank Wunderlich
Cc: Martin Filla, Charalampos Mitrodimas, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
Without configuring the PCIe clock enable pin as an output, it
remains floating in input state. Some operating systems that rely
on correct pin settings may fail to boot as a result.
Fixes: 86973ae0355b ("arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro")
Reported-by: Martin Filla <freebsd@sysctl.cz> # reported by private message
Tested-by: Martin Filla <freebsd@sysctl.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index 3cdea9456a28c..95cf4a6236048 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -125,6 +125,8 @@ pcie_refclk: pcie-refclk-clock {
clocks = <&pcie_refclk_gen>;
#clock-cells = <0>;
enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pcie_clkreq_h>;
+ pinctrl-names = "default";
};
vcc3v3_minipcie: regulator-vcc3v3-minipcie {
@@ -652,6 +654,10 @@ ir_receiver_pin: ir-receiver-pin {
};
pcie {
+ pcie_clkreq_h: pcie-clkreq-h {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+
minipcie_enable_h: minipcie-enable-h {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
};
--
2.53.0
^ permalink raw reply related [flat|nested] 19+ messages in thread