[PATCH net-next v2 0/2] dpll: expose clock quality level

[PATCH net-next v2 0/2] dpll: expose clock quality level

[Jiri Pirko]

From: Jiri Pirko <jiri@nvidia.com>

Some device driver might know the quality of the clock it is running.
In order to expose the information to the user, introduce new netlink
attribute and dpll device op. Implement the op in mlx5 driver.

Example:
$ ./tools/net/ynl/cli.py --spec Documentation/netlink/specs/dpll.yaml --dump device-get
[{'clock-id': 540663412652420550,
  'clock-quality-level': 'itu-eeec',      <<<<<<<<<<<<<<<<<<<<<<<<<<
  'id': 0,
  'lock-status': 'unlocked',
  'lock-status-error': 'none',
  'mode': 'manual',
  'mode-supported': ['manual'],
  'module-name': 'mlx5_dpll',
  'type': 'eec'}]

---
v1->v2:
- extended quality enum documentation
- added "itu" prefix to the enum values

Jiri Pirko (2):
  dpll: add clock quality level attribute and op
  net/mlx5: DPLL, Add clock quality level op implementation

 Documentation/netlink/specs/dpll.yaml         | 32 ++++++++
 drivers/dpll/dpll_netlink.c                   | 22 +++++
 .../net/ethernet/mellanox/mlx5/core/dpll.c    | 82 +++++++++++++++++++
 include/linux/dpll.h                          |  4 +
 include/uapi/linux/dpll.h                     | 23 ++++++
 5 files changed, 163 insertions(+)

-- 
2.46.1

[PATCH net-next v2 1/2] dpll: add clock quality level attribute and op

[Jiri Pirko]

From: Jiri Pirko <jiri@nvidia.com>

In order to allow driver expose quality level of the clock it is
running, introduce a new netlink attr with enum to carry it to the
userspace. Also, introduce an op the dpll netlink code calls into the
driver to obtain the value.

Signed-off-by: Jiri Pirko <jiri@nvidia.com>
---
v1->v2:
- extended quality enum documentation
- added "itu" prefix to the enum values
---
 Documentation/netlink/specs/dpll.yaml | 32 +++++++++++++++++++++++++++
 drivers/dpll/dpll_netlink.c           | 22 ++++++++++++++++++
 include/linux/dpll.h                  |  4 ++++
 include/uapi/linux/dpll.h             | 23 +++++++++++++++++++
 4 files changed, 81 insertions(+)

diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
index f2894ca35de8..d64a3c4490d3 100644
--- a/Documentation/netlink/specs/dpll.yaml
+++ b/Documentation/netlink/specs/dpll.yaml
@@ -85,6 +85,34 @@ definitions:
           This may happen for example if dpll device was previously
           locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
     render-max: true
+  -
+    type: enum
+    name: clock-quality-level
+    doc: |
+      level of quality of a clock device. The current list is defined
+      according to the table 11-7 contained in ITU-T G.8264/Y.1364
+      document. One may extend this list freely by other ITU-T defined
+      clock qualities, or different ones defined by another
+      standardization body (for those, please use different prefix).
+    entries:
+      -
+        name: itu-prc
+        value: 1
+      -
+        name: itu-ssu-a
+      -
+        name: itu-ssu-b
+      -
+        name: itu-eec1
+      -
+        name: itu-prtc
+      -
+        name: itu-eprtc
+      -
+        name: itu-eeec
+      -
+        name: itu-eprc
+    render-max: true
   -
     type: const
     name: temp-divider
@@ -252,6 +280,10 @@ attribute-sets:
         name: lock-status-error
         type: u32
         enum: lock-status-error
+      -
+        name: clock-quality-level
+        type: u32
+        enum: clock-quality-level
   -
     name: pin
     enum-name: dpll_a_pin
diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
index fc0280dcddd1..689a6d0ff049 100644
--- a/drivers/dpll/dpll_netlink.c
+++ b/drivers/dpll/dpll_netlink.c
@@ -169,6 +169,25 @@ dpll_msg_add_temp(struct sk_buff *msg, struct dpll_device *dpll,
 	return 0;
 }
 
+static int
+dpll_msg_add_clock_quality_level(struct sk_buff *msg, struct dpll_device *dpll,
+				 struct netlink_ext_ack *extack)
+{
+	const struct dpll_device_ops *ops = dpll_device_ops(dpll);
+	enum dpll_clock_quality_level ql;
+	int ret;
+
+	if (!ops->clock_quality_level_get)
+		return 0;
+	ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), &ql, extack);
+	if (ret)
+		return ret;
+	if (nla_put_u32(msg, DPLL_A_CLOCK_QUALITY_LEVEL, ql))
+		return -EMSGSIZE;
+
+	return 0;
+}
+
 static int
 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin,
 		      struct dpll_pin_ref *ref,
@@ -557,6 +576,9 @@ dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg,
 	if (ret)
 		return ret;
 	ret = dpll_msg_add_lock_status(msg, dpll, extack);
+	if (ret)
+		return ret;
+	ret = dpll_msg_add_clock_quality_level(msg, dpll, extack);
 	if (ret)
 		return ret;
 	ret = dpll_msg_add_mode(msg, dpll, extack);
diff --git a/include/linux/dpll.h b/include/linux/dpll.h
index 81f7b623d0ba..e99cdb8ab02c 100644
--- a/include/linux/dpll.h
+++ b/include/linux/dpll.h
@@ -26,6 +26,10 @@ struct dpll_device_ops {
 			       struct netlink_ext_ack *extack);
 	int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
 			s32 *temp, struct netlink_ext_ack *extack);
+	int (*clock_quality_level_get)(const struct dpll_device *dpll,
+				       void *dpll_priv,
+				       enum dpll_clock_quality_level *ql,
+				       struct netlink_ext_ack *extack);
 };
 
 struct dpll_pin_ops {
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index b0654ade7b7e..6b9db2e69f32 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -79,6 +79,28 @@ enum dpll_lock_status_error {
 	DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1)
 };
 
+/**
+ * enum dpll_clock_quality_level - level of quality of a clock device. The
+ *   current list is defined according to the table 11-7 contained in ITU-T
+ *   G.8264/Y.1364 document. One may extend this list freely by other ITU-T
+ *   defined clock qualities, or different ones defined by another
+ *   standardization body (for those, please use different prefix).
+ */
+enum dpll_clock_quality_level {
+	DPLL_CLOCK_QUALITY_LEVEL_ITU_PRC = 1,
+	DPLL_CLOCK_QUALITY_LEVEL_ITU_SSU_A,
+	DPLL_CLOCK_QUALITY_LEVEL_ITU_SSU_B,
+	DPLL_CLOCK_QUALITY_LEVEL_ITU_EEC1,
+	DPLL_CLOCK_QUALITY_LEVEL_ITU_PRTC,
+	DPLL_CLOCK_QUALITY_LEVEL_ITU_EPRTC,
+	DPLL_CLOCK_QUALITY_LEVEL_ITU_EEEC,
+	DPLL_CLOCK_QUALITY_LEVEL_ITU_EPRC,
+
+	/* private: */
+	__DPLL_CLOCK_QUALITY_LEVEL_MAX,
+	DPLL_CLOCK_QUALITY_LEVEL_MAX = (__DPLL_CLOCK_QUALITY_LEVEL_MAX - 1)
+};
+
 #define DPLL_TEMP_DIVIDER	1000
 
 /**
@@ -180,6 +202,7 @@ enum dpll_a {
 	DPLL_A_TEMP,
 	DPLL_A_TYPE,
 	DPLL_A_LOCK_STATUS_ERROR,
+	DPLL_A_CLOCK_QUALITY_LEVEL,
 
 	__DPLL_A_MAX,
 	DPLL_A_MAX = (__DPLL_A_MAX - 1)
-- 
2.46.1

Re: [PATCH net-next v2 1/2] dpll: add clock quality level attribute and op

[Donald Hunter]

Jiri Pirko <jiri@resnulli.us> writes:

> From: Jiri Pirko <jiri@nvidia.com>
>
> In order to allow driver expose quality level of the clock it is
> running, introduce a new netlink attr with enum to carry it to the
> userspace. Also, introduce an op the dpll netlink code calls into the
> driver to obtain the value.
>
> Signed-off-by: Jiri Pirko <jiri@nvidia.com>

Reviewed-by: Donald Hunter <donald.hunter@gmail.com>

Re: [PATCH net-next v2 1/2] dpll: add clock quality level attribute and op

[Vadim Fedorenko]

On 10/10/2024 14:06, Jiri Pirko wrote:
> From: Jiri Pirko <jiri@nvidia.com>
> 
> In order to allow driver expose quality level of the clock it is
> running, introduce a new netlink attr with enum to carry it to the
> userspace. Also, introduce an op the dpll netlink code calls into the
> driver to obtain the value.
> 
> Signed-off-by: Jiri Pirko <jiri@nvidia.com>

Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>

[PATCH net-next v2 2/2] net/mlx5: DPLL, Add clock quality level op implementation

[Jiri Pirko]

From: Jiri Pirko <jiri@nvidia.com>

Use MSECQ register to query clock quality from firmware. Implement the
dpll op and fill-up the quality level value properly.

Signed-off-by: Jiri Pirko <jiri@nvidia.com>
---
v1->v2:
- added "itu" prefix to the enum values
---
 .../net/ethernet/mellanox/mlx5/core/dpll.c    | 82 +++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
index 904e08de852e..ccb7477d77b6 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
@@ -166,9 +166,91 @@ static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll,
 	return 0;
 }
 
+enum {
+	MLX5_DPLL_SSM_CODE_PRC = 0b0010,
+	MLX5_DPLL_SSM_CODE_SSU_A = 0b0100,
+	MLX5_DPLL_SSM_CODE_SSU_B = 0b1000,
+	MLX5_DPLL_SSM_CODE_EEC1 = 0b1011,
+	MLX5_DPLL_SSM_CODE_PRTC = 0b0010,
+	MLX5_DPLL_SSM_CODE_EPRTC = 0b0010,
+	MLX5_DPLL_SSM_CODE_EEEC = 0b1011,
+	MLX5_DPLL_SSM_CODE_EPRC = 0b0010,
+};
+
+enum {
+	MLX5_DPLL_ENHANCED_SSM_CODE_PRC = 0xff,
+	MLX5_DPLL_ENHANCED_SSM_CODE_SSU_A = 0xff,
+	MLX5_DPLL_ENHANCED_SSM_CODE_SSU_B = 0xff,
+	MLX5_DPLL_ENHANCED_SSM_CODE_EEC1 = 0xff,
+	MLX5_DPLL_ENHANCED_SSM_CODE_PRTC = 0x20,
+	MLX5_DPLL_ENHANCED_SSM_CODE_EPRTC = 0x21,
+	MLX5_DPLL_ENHANCED_SSM_CODE_EEEC = 0x22,
+	MLX5_DPLL_ENHANCED_SSM_CODE_EPRC = 0x23,
+};
+
+#define __MLX5_DPLL_SSM_COMBINED_CODE(ssm_code, enhanced_ssm_code)		\
+	((ssm_code) | ((enhanced_ssm_code) << 8))
+
+#define MLX5_DPLL_SSM_COMBINED_CODE(type)					\
+	__MLX5_DPLL_SSM_COMBINED_CODE(MLX5_DPLL_SSM_CODE_##type,		\
+				      MLX5_DPLL_ENHANCED_SSM_CODE_##type)
+
+static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll,
+					     void *priv,
+					     enum dpll_clock_quality_level *ql,
+					     struct netlink_ext_ack *extack)
+{
+	u8 network_option, ssm_code, enhanced_ssm_code;
+	u32 out[MLX5_ST_SZ_DW(msecq_reg)] = {};
+	u32 in[MLX5_ST_SZ_DW(msecq_reg)] = {};
+	struct mlx5_dpll *mdpll = priv;
+	int err;
+
+	err = mlx5_core_access_reg(mdpll->mdev, in, sizeof(in),
+				   out, sizeof(out), MLX5_REG_MSECQ, 0, 0);
+	if (err)
+		return err;
+	network_option = MLX5_GET(msecq_reg, out, network_option);
+	if (network_option != 1)
+		goto errout;
+	ssm_code = MLX5_GET(msecq_reg, out, local_ssm_code);
+	enhanced_ssm_code = MLX5_GET(msecq_reg, out, local_enhanced_ssm_code);
+
+	switch (__MLX5_DPLL_SSM_COMBINED_CODE(ssm_code, enhanced_ssm_code)) {
+	case MLX5_DPLL_SSM_COMBINED_CODE(PRC):
+		*ql = DPLL_CLOCK_QUALITY_LEVEL_ITU_PRC;
+		return 0;
+	case MLX5_DPLL_SSM_COMBINED_CODE(SSU_A):
+		*ql = DPLL_CLOCK_QUALITY_LEVEL_ITU_SSU_A;
+		return 0;
+	case MLX5_DPLL_SSM_COMBINED_CODE(SSU_B):
+		*ql = DPLL_CLOCK_QUALITY_LEVEL_ITU_SSU_B;
+		return 0;
+	case MLX5_DPLL_SSM_COMBINED_CODE(EEC1):
+		*ql = DPLL_CLOCK_QUALITY_LEVEL_ITU_EEC1;
+		return 0;
+	case MLX5_DPLL_SSM_COMBINED_CODE(PRTC):
+		*ql = DPLL_CLOCK_QUALITY_LEVEL_ITU_PRTC;
+		return 0;
+	case MLX5_DPLL_SSM_COMBINED_CODE(EPRTC):
+		*ql = DPLL_CLOCK_QUALITY_LEVEL_ITU_EPRTC;
+		return 0;
+	case MLX5_DPLL_SSM_COMBINED_CODE(EEEC):
+		*ql = DPLL_CLOCK_QUALITY_LEVEL_ITU_EEEC;
+		return 0;
+	case MLX5_DPLL_SSM_COMBINED_CODE(EPRC):
+		*ql = DPLL_CLOCK_QUALITY_LEVEL_ITU_EPRC;
+		return 0;
+	}
+errout:
+	NL_SET_ERR_MSG_MOD(extack, "Invalid clock quality level obtained from firmware\n");
+	return -EINVAL;
+}
+
 static const struct dpll_device_ops mlx5_dpll_device_ops = {
 	.lock_status_get = mlx5_dpll_device_lock_status_get,
 	.mode_get = mlx5_dpll_device_mode_get,
+	.clock_quality_level_get = mlx5_dpll_clock_quality_level_get,
 };
 
 static int mlx5_dpll_pin_direction_get(const struct dpll_pin *pin,
-- 
2.46.1

Re: [PATCH net-next v2 0/2] dpll: expose clock quality level

[Jiri Pirko]

Note that there is still discussion going on in v1. Will let you know
how that ends-up, if v2 is okay or another v will come up.

Thanks!

Thu, Oct 10, 2024 at 03:06:44PM CEST, jiri@resnulli.us wrote:
>From: Jiri Pirko <jiri@nvidia.com>
>
>Some device driver might know the quality of the clock it is running.
>In order to expose the information to the user, introduce new netlink
>attribute and dpll device op. Implement the op in mlx5 driver.
>
>Example:
>$ ./tools/net/ynl/cli.py --spec Documentation/netlink/specs/dpll.yaml --dump device-get
>[{'clock-id': 540663412652420550,
>  'clock-quality-level': 'itu-eeec',      <<<<<<<<<<<<<<<<<<<<<<<<<<
>  'id': 0,
>  'lock-status': 'unlocked',
>  'lock-status-error': 'none',
>  'mode': 'manual',
>  'mode-supported': ['manual'],
>  'module-name': 'mlx5_dpll',
>  'type': 'eec'}]
>
>---
>v1->v2:
>- extended quality enum documentation
>- added "itu" prefix to the enum values
>
>Jiri Pirko (2):
>  dpll: add clock quality level attribute and op
>  net/mlx5: DPLL, Add clock quality level op implementation
>
> Documentation/netlink/specs/dpll.yaml         | 32 ++++++++
> drivers/dpll/dpll_netlink.c                   | 22 +++++
> .../net/ethernet/mellanox/mlx5/core/dpll.c    | 82 +++++++++++++++++++
> include/linux/dpll.h                          |  4 +
> include/uapi/linux/dpll.h                     | 23 ++++++
> 5 files changed, 163 insertions(+)
>
>-- 
>2.46.1
>