From: Alexander Hoogerhuis <alexh@ihatent.com>
To: Dave Jones <davej@codemonkey.org.uk>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>,
linux-kernel@vger.kernel.org, marcelo@conectiva.com.br
Subject: Re: CPU/cache detection wrong
Date: 01 Oct 2002 17:31:07 +0200 [thread overview]
Message-ID: <m3d6qu41ms.fsf@lapper.ihatent.com> (raw)
In-Reply-To: <20021001110628.GA17865@suse.de>
Dave Jones <davej@codemonkey.org.uk> writes:
> On Tue, Oct 01, 2002 at 09:21:26AM +0200, Alexander Hoogerhuis wrote:
> > Here we go:
> >
> > CPU: Trace cache: 12K uops, L1 D cache: 8K
> > CPU: L2 cache: 512K
> >
> > But my BIOS still say I should have 8Kb/8Kb I/D L1 cache... oh
> > well. I'm sure Alan Cox would just write it up as marketing, since
> > thats about how reliable a BIOS is :)
>
> Hmm, can a P4 have a trace cache AND an L1 I cache ?
> I thought they were exclusive, which is why the code
> doesn't take this into account. Easily fixed if so though..
>
I don't know the gory details of it, but my BIOS claims I got 8/8, but
I'm deep enough in it now to start taking the 5th amendment on the
details here :)
ttfn,
A
--
Alexander Hoogerhuis | alexh@ihatent.com
CCNP - CCDP - MCNE - CCSE | +47 908 21 485
"You have zero privacy anyway. Get over it." --Scott McNealy
next prev parent reply other threads:[~2002-10-01 15:26 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-09-28 12:29 CPU/cache detection wrong Alexander Hoogerhuis
2002-09-30 16:34 ` Alan Cox
2002-09-30 17:43 ` Alexander Hoogerhuis
2002-09-30 22:15 ` Dave Jones
2002-10-01 7:21 ` Alexander Hoogerhuis
2002-10-01 11:06 ` Dave Jones
2002-10-01 15:31 ` Alexander Hoogerhuis [this message]
2002-10-01 17:01 ` Vojtech Pavlik
-- strict thread matches above, loose matches on Subject: below --
2002-10-01 1:06 David L. DeGeorge
2002-10-01 11:18 ` Dave Jones
2002-10-01 13:35 ` Maciej W. Rozycki
2002-10-01 15:15 ` Dave Jones
2002-10-01 16:03 ` Maciej W. Rozycki
2002-10-01 16:31 ` Dave Jones
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