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From: Pratyush Yadav <pratyush@kernel.org>
To: Cheng Ming Lin <linchengming884@gmail.com>
Cc: tudor.ambarus@linaro.org,  pratyush@kernel.org,
	 mwalle@kernel.org, miquel.raynal@bootlin.com,  richard@nod.at,
	 vigneshr@ti.com, linux-mtd@lists.infradead.org,
	 linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw,
	 leoyu@mxic.com.tw,  Cheng Ming Lin <chengminglin@mxic.com.tw>
Subject: Re: [PATCH] mtd: spi-nor: core: replace dummy buswidth from addr to data
Date: Thu, 07 Nov 2024 17:00:21 +0000	[thread overview]
Message-ID: <mafs0cyj77zdm.fsf@kernel.org> (raw)
In-Reply-To: <20241107093016.151448-1-linchengming884@gmail.com> (Cheng Ming Lin's message of "Thu, 7 Nov 2024 17:30:16 +0800")

On Thu, Nov 07 2024, Cheng Ming Lin wrote:

> From: Cheng Ming Lin <chengminglin@mxic.com.tw>
>
> The default dummy cycle for Macronix SPI NOR flash in Octal Output
> Read Mode(1-1-8) is 20.
>
> Currently, the dummy buswidth is set according to the address bus width.
> In the 1-1-8 mode, this means the dummy buswidth is 1. When converting
> dummy cycles to bytes, this results in 20 x 1 / 8 = 2 bytes, causing the
> host to read data 4 cycles too early.
>
> Since the protocol data buswidth is always greater than or equal to the
> address buswidth. Setting the dummy buswidth to match the data buswidth
> increases the likelihood that the dummy cycle-to-byte conversion will be
> divisible, preventing the host from reading data prematurely.

Makes sense.

Reviewed-by: Pratyush Yadav <pratyush@kernel.org>

-- 
Regards,
Pratyush Yadav

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Pratyush Yadav <pratyush@kernel.org>
To: Cheng Ming Lin <linchengming884@gmail.com>
Cc: tudor.ambarus@linaro.org,  pratyush@kernel.org,
	 mwalle@kernel.org, miquel.raynal@bootlin.com,  richard@nod.at,
	 vigneshr@ti.com, linux-mtd@lists.infradead.org,
	 linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw,
	 leoyu@mxic.com.tw,  Cheng Ming Lin <chengminglin@mxic.com.tw>
Subject: Re: [PATCH] mtd: spi-nor: core: replace dummy buswidth from addr to data
Date: Thu, 07 Nov 2024 17:00:21 +0000	[thread overview]
Message-ID: <mafs0cyj77zdm.fsf@kernel.org> (raw)
In-Reply-To: <20241107093016.151448-1-linchengming884@gmail.com> (Cheng Ming Lin's message of "Thu, 7 Nov 2024 17:30:16 +0800")

On Thu, Nov 07 2024, Cheng Ming Lin wrote:

> From: Cheng Ming Lin <chengminglin@mxic.com.tw>
>
> The default dummy cycle for Macronix SPI NOR flash in Octal Output
> Read Mode(1-1-8) is 20.
>
> Currently, the dummy buswidth is set according to the address bus width.
> In the 1-1-8 mode, this means the dummy buswidth is 1. When converting
> dummy cycles to bytes, this results in 20 x 1 / 8 = 2 bytes, causing the
> host to read data 4 cycles too early.
>
> Since the protocol data buswidth is always greater than or equal to the
> address buswidth. Setting the dummy buswidth to match the data buswidth
> increases the likelihood that the dummy cycle-to-byte conversion will be
> divisible, preventing the host from reading data prematurely.

Makes sense.

Reviewed-by: Pratyush Yadav <pratyush@kernel.org>

-- 
Regards,
Pratyush Yadav

  reply	other threads:[~2024-11-07 18:16 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-07  9:30 [PATCH] mtd: spi-nor: core: replace dummy buswidth from addr to data Cheng Ming Lin
2024-11-07  9:30 ` Cheng Ming Lin
2024-11-07 17:00 ` Pratyush Yadav [this message]
2024-11-07 17:00   ` Pratyush Yadav
2024-11-11 10:18 ` Tudor Ambarus
2024-11-11 10:18   ` Tudor Ambarus
2024-11-12  2:42   ` Cheng Ming Lin
2024-11-12  2:42     ` Cheng Ming Lin
2024-11-12  6:45     ` Tudor Ambarus
2024-11-12  6:45       ` Tudor Ambarus
2024-11-12  7:06       ` Tudor Ambarus
2024-11-12  7:06         ` Tudor Ambarus
2024-11-12  7:16         ` Cheng Ming Lin
2024-11-12  7:16           ` Cheng Ming Lin

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