From: "Mallick, Asit K" <asit.k.mallick@intel.com>
To: linux-ia64@vger.kernel.org
Subject: RE: [Linux-ia64] CONFIG_IA64_L1_CACHE_SHIFT
Date: Fri, 02 Mar 2001 01:00:44 +0000 [thread overview]
Message-ID: <marc-linux-ia64-105590693005240@msgid-missing> (raw)
In-Reply-To: <marc-linux-ia64-105590693005236@msgid-missing>
Also this is configurable to take care of future processors that may have
higher cache line sizes.
Thanks,
Asit
> -----Original Message-----
> From: David Mosberger [mailto:davidm@hpl.hp.com]
> Sent: Thursday, March 01, 2001 2:35 PM
> To: Jes Sorensen
> Cc: linux-ia64@linuxia64.org
> Subject: Re: [Linux-ia64] CONFIG_IA64_L1_CACHE_SHIFT
>
>
> >>>>> On 01 Mar 2001 20:29:28 +0100, Jes Sorensen
> <jes@linuxcare.com> said:
>
> Jes> Hi Anyone who can explain why there is a
>
> Jes> define_int CONFIG_IA64_L1_CACHE_SHIFT 6
>
> Jes> in the config file? We already have SMP_CACHE_BYTES and
> Jes> L1_CACHE bytes for all architectures, it doesn't make a whole
> Jes> lot of sense to me ot invent yet another alignment rule.
>
> $ fgrep CONFIG_IA64_L1 include/asm-ia64/cache.h
> #define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT
>
> --david
>
> _______________________________________________
> Linux-IA64 mailing list
> Linux-IA64@linuxia64.org
> http://lists.linuxia64.org/lists/listinfo/linux-ia64
>
next prev parent reply other threads:[~2001-03-02 1:00 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-03-01 19:29 [Linux-ia64] CONFIG_IA64_L1_CACHE_SHIFT Jes Sorensen
2001-03-01 22:35 ` David Mosberger
2001-03-01 23:18 ` Jes Sorensen
2001-03-02 1:00 ` Mallick, Asit K [this message]
2001-03-02 15:51 ` David Mosberger
2001-03-02 23:30 ` Grover, Andrew
2001-03-05 19:37 ` David Mosberger
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