From: Jack Steiner <steiner@sgi.com>
To: linux-ia64@vger.kernel.org
Subject: Re: [RFC] Better MCA recovery on IPF
Date: Mon, 03 Nov 2003 19:28:56 +0000 [thread overview]
Message-ID: <marc-linux-ia64-106788827105836@msgid-missing> (raw)
In-Reply-To: <marc-linux-ia64-106724227826901@msgid-missing>
On Mon, Nov 03, 2003 at 10:42:48AM -0800, Alberto Munoz wrote:
>
>
> > > Hi,
> > >
> > > I just wondered if a speculative load hitting a cache or memory
> > > error does cause an exception on IA64 ?
> >
> > I dont think a speculative load should cause a problem - at
> > least until
> > code tries to consume the data by transfering it to a
> > processor register.
>
> If you are doing a read (which is what a speculative load will be
> generating), the error will be generated by whatever part of the logic that
> detects it. You cannot possible send poisoned data through a memory bus and a
> system bus (at least not the Intel system buses I am familiar with) without
> having some of the error checking logic (ECC or parity) complaining about it
> (this means generating an MCA).
As the poisoned data flows thru the BUSes, errors may be reported but these errors
are not reported to the OS as uncorrected/fatal MCA errors. Depending on your
chipset, errors are logged as platform errors.
There is a good paper by Tony Luck (Intel) that describes data poisoning as used
in IA64. You can find it on google or at:
archive.linuxsymposium.org/ols2003/Proceedings/ All-Reprints/Reprint-Luck-OLS2003.pdf
See the section on "data poisoning".
>
> > As I understand the cpu architecture, an error that occurs
> > reading data
> > will result in a poisoned cache line being delivered to the
> > cpu cache.
> > The poisoned cache line can stay in the cache forever. No MCA error is
> > reported until the data is actually consumed by tranfering
> > the data from
> > cache to a cpu register.
>
> The problem is that the cache error checking logic has no way of knowing that
> the data it is about to supply to some register is going to be used for a
> speculative operation. The cache logic is pretty far away (in processor
> terms) from the decoding logic.
>
> Bert Munoz
>
> > This requires some support from the chipset. Some chipsets dont fully
> > support this error model.
> >
> >
> >
> >
--
Thanks
Jack Steiner (steiner@sgi.com) 651-683-5302
Principal Engineer SGI - Silicon Graphics, Inc.
next prev parent reply other threads:[~2003-11-03 19:28 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-10-27 8:07 [RFC] Better MCA recovery on IPF Hidetoshi Seto
2003-10-27 16:58 ` Matthias Fouquet-Lapar
2003-10-31 5:09 ` Hidetoshi Seto
2003-10-31 17:14 ` Grant Grundler
2003-11-01 6:39 ` Matthias Fouquet-Lapar
2003-11-01 8:38 ` Keith Owens
2003-11-02 13:33 ` Matthias Fouquet-Lapar
2003-11-03 17:09 ` Russ Anderson
2003-11-03 17:37 ` Matthias Fouquet-Lapar
2003-11-03 17:51 ` Alberto Munoz
2003-11-03 17:53 ` Alberto Munoz
2003-11-03 18:23 ` Jack Steiner
2003-11-03 18:42 ` Alberto Munoz
2003-11-03 19:28 ` Jack Steiner [this message]
2003-11-03 23:09 ` Alberto Munoz
2003-11-05 4:11 ` Greg Banks
2003-11-05 17:00 ` Luck, Tony
2003-11-05 17:14 ` Alberto Munoz
2003-11-05 17:30 ` Matthew Wilcox
2003-11-05 17:37 ` Alberto Munoz
2003-11-06 12:03 ` Hidetoshi Seto
2003-11-06 14:23 ` Matthias Fouquet-Lapar
2003-11-06 19:09 ` Luck, Tony
2003-11-07 9:58 ` Hidetoshi Seto
2003-11-07 10:52 ` Matthias Fouquet-Lapar
2003-11-08 1:15 ` Luck, Tony
2003-11-08 7:36 ` Matthias Fouquet-Lapar
2003-11-10 10:33 ` Hidetoshi Seto
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