* Re: [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler
2025-07-10 13:32 [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler Andreas Schwab
@ 2025-07-10 19:05 ` Clément Léger
2025-07-11 7:29 ` Alexandre Ghiti
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Clément Léger @ 2025-07-10 19:05 UTC (permalink / raw)
To: Andreas Schwab, linux-riscv; +Cc: damien.lemoal, anup, palmer
On 10/07/2025 15:32, Andreas Schwab wrote:
> Add missing cast to signed long.
>
> Signed-off-by: Andreas Schwab <schwab@suse.de>
> ---
> arch/riscv/kernel/traps_misaligned.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 93043924fe6c..f760e4fcc052 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
> }
>
> if (!fp)
> - SET_RD(insn, regs, val.data_ulong << shift >> shift);
> + SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
> else if (len == 8)
> set_f64_rd(insn, regs, val.data_u64);
> else
Hi Andreas,
After modify my test to catch sign extension problems, I can confirm it
fixes it.
Tested-by: Clément Léger <cleger@rivosinc.com>
Thanks,
Clément
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler
2025-07-10 13:32 [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler Andreas Schwab
2025-07-10 19:05 ` Clément Léger
@ 2025-07-11 7:29 ` Alexandre Ghiti
2025-07-14 6:59 ` Andreas Schwab
2025-07-14 7:38 ` Andreas Schwab
2025-07-16 16:07 ` Palmer Dabbelt
2025-07-16 20:00 ` patchwork-bot+linux-riscv
3 siblings, 2 replies; 7+ messages in thread
From: Alexandre Ghiti @ 2025-07-11 7:29 UTC (permalink / raw)
To: Andreas Schwab, linux-riscv; +Cc: damien.lemoal, anup, palmer
Hi Andreas,
On 7/10/25 15:32, Andreas Schwab wrote:
> Add missing cast to signed long.
>
> Signed-off-by: Andreas Schwab <schwab@suse.de>
> ---
> arch/riscv/kernel/traps_misaligned.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 93043924fe6c..f760e4fcc052 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
> }
>
> if (!fp)
> - SET_RD(insn, regs, val.data_ulong << shift >> shift);
> + SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
> else if (len == 8)
> set_f64_rd(insn, regs, val.data_u64);
> else
Let's add:
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Cc: stable@vger.kernel.org
Does that fix the issue you reported when booting with opensbi 1.7?
Thanks,
Alex
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler
2025-07-11 7:29 ` Alexandre Ghiti
@ 2025-07-14 6:59 ` Andreas Schwab
2025-07-14 7:38 ` Andreas Schwab
1 sibling, 0 replies; 7+ messages in thread
From: Andreas Schwab @ 2025-07-14 6:59 UTC (permalink / raw)
To: Alexandre Ghiti; +Cc: linux-riscv, damien.lemoal, anup, palmer
On Jul 11 2025, Alexandre Ghiti wrote:
> Does that fix the issue you reported when booting with opensbi 1.7?
Yes, it does.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler
2025-07-11 7:29 ` Alexandre Ghiti
2025-07-14 6:59 ` Andreas Schwab
@ 2025-07-14 7:38 ` Andreas Schwab
1 sibling, 0 replies; 7+ messages in thread
From: Andreas Schwab @ 2025-07-14 7:38 UTC (permalink / raw)
To: Alexandre Ghiti; +Cc: linux-riscv, damien.lemoal, anup, palmer
On Jul 11 2025, Alexandre Ghiti wrote:
> Does that fix the issue you reported when booting with opensbi 1.7?
Yes, it does.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler
2025-07-10 13:32 [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler Andreas Schwab
2025-07-10 19:05 ` Clément Léger
2025-07-11 7:29 ` Alexandre Ghiti
@ 2025-07-16 16:07 ` Palmer Dabbelt
2025-07-16 20:00 ` patchwork-bot+linux-riscv
3 siblings, 0 replies; 7+ messages in thread
From: Palmer Dabbelt @ 2025-07-16 16:07 UTC (permalink / raw)
To: schwab; +Cc: linux-riscv, damien.lemoal, anup
On Thu, 10 Jul 2025 06:32:18 PDT (-0700), schwab@suse.de wrote:
> Add missing cast to signed long.
>
> Signed-off-by: Andreas Schwab <schwab@suse.de>
> ---
> arch/riscv/kernel/traps_misaligned.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 93043924fe6c..f760e4fcc052 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
> }
>
> if (!fp)
> - SET_RD(insn, regs, val.data_ulong << shift >> shift);
> + SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
Thanks. I ran into another assembly sign extension issue recently, I
think we need to scrub through the port for these...
> else if (len == 8)
> set_f64_rd(insn, regs, val.data_u64);
> else
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler
2025-07-10 13:32 [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler Andreas Schwab
` (2 preceding siblings ...)
2025-07-16 16:07 ` Palmer Dabbelt
@ 2025-07-16 20:00 ` patchwork-bot+linux-riscv
3 siblings, 0 replies; 7+ messages in thread
From: patchwork-bot+linux-riscv @ 2025-07-16 20:00 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linux-riscv, damien.lemoal, anup, palmer
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@dabbelt.com>:
On Thu, 10 Jul 2025 15:32:18 +0200 you wrote:
> Add missing cast to signed long.
>
> Signed-off-by: Andreas Schwab <schwab@suse.de>
> ---
> arch/riscv/kernel/traps_misaligned.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Here is the summary with links:
- riscv: traps_misaligned: properly sign extend value in misaligned load handler
https://git.kernel.org/riscv/c/b3510183ab7d
You are awesome, thank you!
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^ permalink raw reply [flat|nested] 7+ messages in thread