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From: Andreas Schwab <schwab@suse.de>
To: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
Cc: Tomasz Jeznach <tjeznach@rivosinc.com>,
	 Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	 Robin Murphy <robin.murphy@arm.com>,
	Paul Walmsley <pjw@kernel.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Alexandre Ghiti <alex@ghiti.fr>,
	iommu@lists.linux.dev,  linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,  Xu Lu <luxu.kernel@bytedance.com>,
	cuiyunhui@bytedance.com,  yuanzhu@bytedance.com
Subject: Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses
Date: Mon, 15 Jun 2026 10:21:12 +0200	[thread overview]
Message-ID: <mvmik7kz01z.fsf@suse.de> (raw)
In-Reply-To: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> (Zhanpeng Zhang's message of "Mon, 15 Jun 2026 14:48:55 +0800")

On Jun 15 2026, Zhanpeng Zhang wrote:

> +config RISCV_IOMMU_32BIT_ACCESS
> +	bool "Use 32-bit accesses for RISC-V IOMMU registers"
> +	depends on RISCV_IOMMU
> +	help
> +	  Say Y when the RISC-V IOMMU MMIO window cannot be accessed
> +	  using naturally aligned 64-bit loads and stores.
> +
> +	  When enabled, 64-bit IOMMU registers are accessed as paired
> +	  32-bit MMIO operations. This option does not describe an RV32
> +	  kernel or a 32-bit IOMMU architecture.

What is the expected setting in a generic kernel?

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

WARNING: multiple messages have this Message-ID (diff)
From: Andreas Schwab <schwab@suse.de>
To: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
Cc: Tomasz Jeznach <tjeznach@rivosinc.com>,
	 Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	 Robin Murphy <robin.murphy@arm.com>,
	Paul Walmsley <pjw@kernel.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Alexandre Ghiti <alex@ghiti.fr>,
	iommu@lists.linux.dev,  linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,  Xu Lu <luxu.kernel@bytedance.com>,
	cuiyunhui@bytedance.com,  yuanzhu@bytedance.com
Subject: Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses
Date: Mon, 15 Jun 2026 10:21:12 +0200	[thread overview]
Message-ID: <mvmik7kz01z.fsf@suse.de> (raw)
In-Reply-To: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> (Zhanpeng Zhang's message of "Mon, 15 Jun 2026 14:48:55 +0800")

On Jun 15 2026, Zhanpeng Zhang wrote:

> +config RISCV_IOMMU_32BIT_ACCESS
> +	bool "Use 32-bit accesses for RISC-V IOMMU registers"
> +	depends on RISCV_IOMMU
> +	help
> +	  Say Y when the RISC-V IOMMU MMIO window cannot be accessed
> +	  using naturally aligned 64-bit loads and stores.
> +
> +	  When enabled, 64-bit IOMMU registers are accessed as paired
> +	  32-bit MMIO operations. This option does not describe an RV32
> +	  kernel or a 32-bit IOMMU architecture.

What is the expected setting in a generic kernel?

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-06-15  8:21 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-15  6:48 [PATCH v1] iommu/riscv: Support 32-bit register accesses Zhanpeng Zhang
2026-06-15  6:48 ` Zhanpeng Zhang
2026-06-15  8:21 ` Andreas Schwab [this message]
2026-06-15  8:21   ` Andreas Schwab
2026-06-15  9:51   ` [External] " Zhanpeng Zhang
2026-06-15  9:51     ` Zhanpeng Zhang
2026-06-15  9:59 ` David Laight
2026-06-15  9:59   ` David Laight
2026-06-15 13:21   ` [External] " Zhanpeng Zhang
2026-06-15 13:21     ` Zhanpeng Zhang
2026-06-15 12:38 ` Guo Ren
2026-06-15 12:38   ` Guo Ren
2026-06-15 13:23   ` [External] " Zhanpeng Zhang
2026-06-15 13:23     ` Zhanpeng Zhang

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