* Re: [PATCH] Double x86 initialise fix.
From: Alan Cox @ 2002-10-26 13:57 UTC (permalink / raw)
To: Dave Jones; +Cc: Alan Cox, Linux Kernel Mailing List, alan
In-Reply-To: <20021026134947.GA31349@suse.de>
> Isn't this always the case on x86 ?
> /me waits to hear gory details of some IBM monster.
It isnt. The boot CPU may be any number. In addition you can strap dual
pentium boxes to arbitrate for who is boot cpu (this is used for fault
tolerance).
^ permalink raw reply
* Re: kexec for 2.5.44 (Who do I send this to?)
From: Eric W. Biederman @ 2002-10-26 13:54 UTC (permalink / raw)
To: Pavel Machek
Cc: linux-kernel, Suparna Bhattacharya, Petr Vandrovec, fastboot,
Werner Almesberger
In-Reply-To: <20021020190939.GA913@elf.ucw.cz>
Pavel Machek <pavel@ucw.cz> writes:
> Hi!
>
> > The kexec code has gone through a fairly decent review, and all known bugs
> > are resolved. There are still BIOS's that don't work after you have
> > run a kernel but that is an entirely different problem.
>
> Looks good... Few comments follow.
> Perhaps this should be done using driverfs callbacks?
SMP must be stopped and the APIC shutdown as the very last thing to happen.
The order dependency is a very real, and ugly things happen when it
doesn't happen as the very last thing. Does driverfs have a way to
express that?
Eric
^ permalink raw reply
* Re: The pain with the Net Drivers (ne*, xirc2ps_c, etc)
From: Tomas Szepe @ 2002-10-26 13:53 UTC (permalink / raw)
To: Adrian Pop; +Cc: Adam Kropelin, linux-kernel
In-Reply-To: <Pine.GSO.4.44.0210260712300.11632-100000@mir20.ida.liu.se>
> Both gived the errors under medium load with
> the original timeout: TX_TIMEOUT (20*HZ/100).
> They reported no error and worked perfectly after
> changing TX_TIMEOUT to (100*HZ/100)
Your ethernet is on fire.
Either that, or your machine is somehow not quite healthy.
Considering your "it really doesn't matter the computer",
I'd vote for the former, though.
T.
^ permalink raw reply
* [LARTC] Problem with fw filters
From: Aigars Mahinovs @ 2002-10-26 13:44 UTC (permalink / raw)
To: lartc
[-- Attachment #1: Type: text/plain, Size: 7667 bytes --]
Hi all,
I am trying to priorityse outgoing traffic basing on UID of the sender.
Script follows:
# First mark packets with their respective priority
iptables -t mangle -F OUTPUT
iptables -t mangle -A OUTPUT -m owner --uid-owner root -j MARK
--set-mark 1
iptables -t mangle -A OUTPUT -m owner --uid-owner aigarius -j MARK
--set-mark 2
iptables -t mangle -A OUTPUT -m owner --uid-owner bind -j MARK
--set-mark 3
iptables -t mangle -A OUTPUT -m owner --uid-owner proxy -j MARK
--set-mark 4
iptables -t mangle -A OUTPUT -m owner --uid-owner nobody -j MARK
--set-mark 5
iptables -t mangle -A OUTPUT -m owner --uid-owner www-data -j MARK
--set-mark 6
iptables -t mangle -A OUTPUT -m owner --uid-owner ftp -j MARK --set-mark
7
iptables -t mangle -A OUTPUT -m owner --uid-owner ivarix -j MARK
--set-mark 8
iptables -t mangle -A OUTPUT -m owner --uid-owner blacky -j MARK
--set-mark 9
iptables -t mangle -A OUTPUT -j MARK --set-mark 666
# now make outgoing traffic classes
# clean existing qdiscs, hide errors
/home/aigarius/bin/tc qdisc del dev eth0 root 2> /dev/null >
/dev/null
/home/aigarius/bin/tc qdisc add dev eth0 root handle 1: htb
/home/aigarius/bin/tc class add dev eth0 parent 1: classid 1:1 htb rate
100mbit burst 64k
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:10 htb
rate 100mbit burst 64k prio 1
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:20 htb
rate 100mbit burst 64k prio 2
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:30 htb
rate 100mbit burst 64k prio 3
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:40 htb
rate 100mbit burst 64k prio 4
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:50 htb
rate 100mbit burst 64k prio 5
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:60 htb
rate 100mbit burst 64k prio 6
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:70 htb
rate 100mbit burst 64k prio 7
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:80 htb
rate 100mbit burst 64k prio 8
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:90 htb
rate 100mbit burst 64k prio 9
/home/aigarius/bin/tc class add dev eth0 parent 1:1 classid 1:666 htb
rate 10mbit burst 64k prio 20
# all get Stochastic Fairness:
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:10 handle 10: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:20 handle 20: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:30 handle 30: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:40 handle 40: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:50 handle 50: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:60 handle 60: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:70 handle 70: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:80 handle 80: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:90 handle 90: sfq
perturb 10
/home/aigarius/bin/tc qdisc add dev eth0 parent 1:666 handle 666: sfq
perturb 10
# Filter traffic into classes
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 1 fw flowid 1:10
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 2 fw flowid 1:20
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 3 fw flowid 1:30
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 4 fw flowid 1:40
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 5 fw flowid 1:50
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 6 fw flowid 1:60
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 7 fw flowid 1:70
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 8 fw flowid 1:80
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 9 fw flowid 1:90
/home/aigarius/bin/tc filter add dev eth0 parent 1:0 protocol ip prio 10
handle 666 fw flowid 1:666
--- END OF SCRIPT ---
Problem:
no shaping is done
# tc -s qdisc show
qdisc sfq 666: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 679086470 bytes 985634 pkts (dropped 0, overlimits 0)
qdisc sfq 90: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc sfq 80: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc sfq 70: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc sfq 60: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc sfq 50: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc sfq 40: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc sfq 30: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc sfq 20: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc sfq 10: dev eth0 quantum 1514b limit 128p flows 128/1024 perturb
10sec
Sent 0 bytes 0 pkts (dropped 0, overlimits 0)
qdisc htb 1: dev eth0 r2q 10 default 0 direct_packets_stat 778 ver 3.6
Sent 679175569 bytes 986412 pkts (dropped 0, overlimits 9647)
#iptables -v -t mangle -L OUTPUT
Chain OUTPUT (policy ACCEPT 25M packets, 16G bytes)
pkts bytes target prot opt in out source
destination
6782 802K MARK all -- any any anywhere
anywhere OWNER UID match root MARK set 0x1
7439 393K MARK all -- any any anywhere
anywhere OWNER UID match aigarius MARK set 0x2
7878 2018K MARK all -- any any anywhere
anywhere OWNER UID match bind MARK set 0x3
65687 49M MARK all -- any any anywhere
anywhere OWNER UID match proxy MARK set 0x4
752K 524M MARK all -- any any anywhere
anywhere OWNER UID match nobody MARK set 0x5
24388 35M MARK all -- any any anywhere
anywhere OWNER UID match www-data MARK set 0x6
44401 62M MARK all -- any any anywhere
anywhere OWNER UID match ftp MARK set 0x7
7 600 MARK all -- any any anywhere
anywhere OWNER UID match ivarix MARK set 0x8
0 0 MARK all -- any any anywhere
anywhere OWNER UID match blacky MARK set 0x9
1019K 680M MARK all -- any any anywhere
anywhere MARK set 0x29a
As I see there is no shaping done -- the filters do not work.
I also do routing based on firewall key -> it doesn't work either, but
nothing shows any errors.
Please help. Thanks.
PS. I am using kernel 2.4.19 patched with htb3 and gr-security patch and
htb3 precompiled tc on Debian unstable system.
--
Best regards,
Aigars Mahinovs mailto:aigarius@debian.org
#--------------------------------------------------#
| .''`. |
| : :' : Debian GNU/Linux |
| `. `' http://www.debian.org |
| `- |
#--------------------------------------------------#
[-- Attachment #2: Type: application/pgp-signature, Size: 831 bytes --]
^ permalink raw reply
* Re: KT333, IO-APIC, Promise Fasttrak, Initrd
From: Alan Cox @ 2002-10-26 14:06 UTC (permalink / raw)
To: freaky; +Cc: Linux Kernel Mailing List
In-Reply-To: <001401c27cbc$53ecf810$1400a8c0@Freaky>
On Sat, 2002-10-26 at 07:53, freaky wrote:
> So that would be data on the MBR, or partition table? Perhaps win doesn't
> have probs because it can handle to partitions types properly. MSI told me
No its seperate. The hpt/promise raid "borrows" part of the disk and
hides it.
^ permalink raw reply
* Re: [PATCH] Double x86 initialise fix.
From: Dave Jones @ 2002-10-26 13:49 UTC (permalink / raw)
To: Alan Cox; +Cc: Linux Kernel Mailing List, alan
In-Reply-To: <1035640580.13032.100.camel@irongate.swansea.linux.org.uk>
On Sat, Oct 26, 2002 at 02:56:20PM +0100, Alan Cox wrote:
> > For many moons, we've been executing identify_cpu()
> > on the boot processor twice on SMP kernels.
> > This is harmless, but has a few downsides..
> > - Extra cruft in bootlog/dmesg
> > - Spawns one too many timers for the mcheck handler
> > - possibly other wasteful things..
> >
> > This seems to do the right thing here..
Isn't this always the case on x86 ?
/me waits to hear gory details of some IBM monster.
Dave
--
| Dave Jones. http://www.codemonkey.org.uk
^ permalink raw reply
* Pinging a IP , how to stop it bringing diald live
From: Sean Rima @ 2002-10-26 13:35 UTC (permalink / raw)
To: linux-diald
Originally to: All
Hi Folks,
I am trying to get a BBS package working, it checks that the inet is live by
pinging the net. Is there any way to tell diald not to dial if it receives a
ping for a certain ip?
Sean
Gtx, Sean Rima
^ permalink raw reply
* Re: [PATCH] Double x86 initialise fix.
From: Alan Cox @ 2002-10-26 13:56 UTC (permalink / raw)
To: davej; +Cc: Linux Kernel Mailing List, alan
In-Reply-To: <200210261242.g9QCgSqp030280@noodles.internal>
On Sat, 2002-10-26 at 13:42, davej@codemonkey.org.uk wrote:
> For many moons, we've been executing identify_cpu()
> on the boot processor twice on SMP kernels.
> This is harmless, but has a few downsides..
> - Extra cruft in bootlog/dmesg
> - Spawns one too many timers for the mcheck handler
> - possibly other wasteful things..
>
> This seems to do the right thing here..
How do you know the boot CPU is CPU#0
^ permalink raw reply
* Re: [PATCH] de-cryptify ide-disk host protected area output
From: Erik Andersen @ 2002-10-26 13:24 UTC (permalink / raw)
To: bert hubert, andre, linux-kernel
In-Reply-To: <20021026130701.GA29860@outpost.ds9a.nl>
On Sat Oct 26, 2002 at 03:07:01PM +0200, bert hubert wrote:
> Useless number '1' being printed leading to operator confusion.
>
> --- linux-2.5.44/drivers/ide/ide-disk.c~orig Sat Oct 26 14:59:35 2002
> +++ linux-2.5.44/drivers/ide/ide-disk.c Sat Oct 26 15:00:40 2002
> @@ -1128,7 +1128,7 @@
> {
> int flag = (drive->id->cfs_enable_1 & 0x0400) ? 1 : 0;
> if (flag)
> - printk("%s: host protected area => %d\n", drive->name, flag);
> + printk("%s: supports host protected area", drive->name);
> return flag;
> }
Even better -- kill the prink entirely. If anyone really
cares, they can run 'hdparm -I <drivename>' and get the
exhaustive list of everything the drive supports....
-Erik
--
Erik B. Andersen http://codepoet-consulting.com/
--This message was written using 73% post-consumer electrons--
^ permalink raw reply
* quota support for 2.4.20-pre11
From: Basil A. Evseenko @ 2002-10-26 13:17 UTC (permalink / raw)
To: reiserfs-list
Are there quota patches for 2.4.20-pre11 kernel?
Patches for 2.4.19 doesn't applies correctly.
^ permalink raw reply
* [PATCH] de-cryptify ide-disk host protected area output
From: bert hubert @ 2002-10-26 13:07 UTC (permalink / raw)
To: andre, linux-kernel
Useless number '1' being printed leading to operator confusion.
--- linux-2.5.44/drivers/ide/ide-disk.c~orig Sat Oct 26 14:59:35 2002
+++ linux-2.5.44/drivers/ide/ide-disk.c Sat Oct 26 15:00:40 2002
@@ -1128,7 +1128,7 @@
{
int flag = (drive->id->cfs_enable_1 & 0x0400) ? 1 : 0;
if (flag)
- printk("%s: host protected area => %d\n", drive->name, flag);
+ printk("%s: supports host protected area", drive->name);
return flag;
}
--
http://www.PowerDNS.com Versatile DNS Software & Services
http://lartc.org Linux Advanced Routing & Traffic Control HOWTO
^ permalink raw reply
* [PATCH] x86 machine check architecture cleanup.
From: davej @ 2002-10-26 12:42 UTC (permalink / raw)
To: linux-kernel; +Cc: alan
Splits up into seperate files per implementation, and
moved to the arch/i386/kernel/cpu/mcheck/ directory.
Feedback of this from users of various Pentiums,
Athlon/Durons and IDT Winchips would be useful.
It seems to survive minimal testing here on my P4.
With the cpu/ dir starting to fill up, I'm wondering if
it should be moved out of kernel/ up one dir to
arch/i386/cpu. Any comments ?
Dave
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/config.in linux-2.5/arch/i386/config.in
--- bk-linus/arch/i386/config.in 2002-10-20 20:21:18.000000000 -0100
+++ linux-2.5/arch/i386/config.in 2002-10-25 18:02:30.000000000 -0100
@@ -188,8 +193,12 @@ else
fi
bool 'Machine Check Exception' CONFIG_X86_MCE
-dep_bool 'Check for non-fatal errors on Athlon/Duron' CONFIG_X86_MCE_NONFATAL $CONFIG_X86_MCE
-dep_bool 'check for P4 thermal throttling interrupt.' CONFIG_X86_MCE_P4THERMAL $CONFIG_X86_MCE $CONFIG_X86_UP_APIC
+dep_bool ' Check for non-fatal errors on Athlon/Duron' CONFIG_X86_MCE_NONFATAL $CONFIG_X86_MCE
+if [ "$CONFIG_SMP" = "y" ]; then
+ dep_bool ' Check for P4 thermal throttling interrupt.' CONFIG_X86_MCE_P4THERMAL $CONFIG_X86_MCE
+else
+ dep_bool ' Check for P4 thermal throttling interrupt.' CONFIG_X86_MCE_P4THERMAL $CONFIG_X86_MCE $CONFIG_X86_UP_APIC
+fi
bool 'CPU Frequency scaling' CONFIG_CPU_FREQ
if [ "$CONFIG_CPU_FREQ" = "y" ]; then
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/Makefile linux-2.5/arch/i386/kernel/Makefile
--- bk-linus/arch/i386/kernel/Makefile 2002-10-20 20:21:20.000000000 -0100
+++ linux-2.5/arch/i386/kernel/Makefile 2002-10-25 18:02:30.000000000 -0100
@@ -8,9 +8,8 @@ export-objs := mca.o i386_ksyms.o ti
obj-y := process.o semaphore.o signal.o entry.o traps.o irq.o vm86.o \
ptrace.o i8259.o ioport.o ldt.o setup.o time.o sys_i386.o \
- pci-dma.o i386_ksyms.o i387.o bluesmoke.o dmi_scan.o \
- bootflag.o
+ pci-dma.o i386_ksyms.o i387.o dmi_scan.o bootflag.o
obj-y += cpu/
obj-y += timers/
obj-$(CONFIG_X86_BIOS_REBOOT) += reboot.o
obj-$(CONFIG_MCA) += mca.o
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/bluesmoke.c linux-2.5/arch/i386/kernel/bluesmoke.c
--- bk-linus/arch/i386/kernel/bluesmoke.c 2002-10-20 20:21:20.000000000 -0100
+++ linux-2.5/arch/i386/kernel/bluesmoke.c 1969-12-31 23:00:00.000000000 -0100
@@ -1,504 +0,0 @@
-/*
- * arch/i386/kernel/bluesmoke.c - x86 Machine Check Exception Reporting
- */
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/jiffies.h>
-#include <linux/smp.h>
-#include <linux/config.h>
-#include <linux/irq.h>
-#include <linux/workqueue.h>
-#include <linux/interrupt.h>
-
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/msr.h>
-#include <asm/apic.h>
-#include <asm/pgtable.h>
-#include <asm/tlbflush.h>
-#include <asm/hardirq.h>
-
-#ifdef CONFIG_X86_MCE
-
-/* as supported by the P4/Xeon family */
-struct intel_mce_extended_msrs {
- u32 eax;
- u32 ebx;
- u32 ecx;
- u32 edx;
- u32 esi;
- u32 edi;
- u32 ebp;
- u32 esp;
- u32 eflags;
- u32 eip;
- /* u32 *reserved[]; */
-};
-
-static int mce_disabled __initdata = 0;
-
-static int mce_num_extended_msrs = 0;
-static int banks;
-
-
-#ifdef CONFIG_X86_MCE_P4THERMAL
-/*
- * P4/Xeon Thermal transition interrupt handler
- */
-
-static void intel_thermal_interrupt(struct pt_regs *regs)
-{
- u32 l, h;
- unsigned int cpu = smp_processor_id();
-
- ack_APIC_irq();
-
- rdmsr(MSR_IA32_THERM_STATUS, l, h);
- if (l & 1) {
- printk(KERN_EMERG "CPU#%d: Temperature above threshold\n", cpu);
- printk(KERN_EMERG "CPU#%d: Running in modulated clock mode\n", cpu);
- } else {
- printk(KERN_INFO "CPU#%d: Temperature/speed normal\n", cpu);
- }
-}
-
-static void unexpected_thermal_interrupt(struct pt_regs *regs)
-{
- printk(KERN_ERR "CPU#%d: Unexpected LVT TMR interrupt!\n", smp_processor_id());
-}
-
-/*
- * Thermal interrupt handler for this CPU setup
- */
-
-static void (*vendor_thermal_interrupt)(struct pt_regs *regs) = unexpected_thermal_interrupt;
-
-asmlinkage void smp_thermal_interrupt(struct pt_regs regs)
-{
- irq_enter();
- vendor_thermal_interrupt(®s);
- irq_exit();
-}
-
-/* P4/Xeon Thermal regulation detect and init */
-
-static void __init intel_init_thermal(struct cpuinfo_x86 *c)
-{
- u32 l, h;
- unsigned int cpu = smp_processor_id();
-
- /* Thermal monitoring */
- if (!cpu_has(c, X86_FEATURE_ACPI))
- return; /* -ENODEV */
-
- /* Clock modulation */
- if (!cpu_has(c, X86_FEATURE_ACC))
- return; /* -ENODEV */
-
- /* first check if its enabled already, in which case there might
- * be some SMM goo which handles it, so we can't even put a handler
- * since it might be delivered via SMI already -zwanem.
- */
- rdmsr(MSR_IA32_MISC_ENABLE, l, h);
- h = apic_read(APIC_LVTTHMR);
- if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
- printk(KERN_DEBUG "CPU#%d: Thermal monitoring handled by SMI\n", cpu);
- return; /* -EBUSY */
- }
-
- /* check whether a vector already exists, temporarily masked? */
- if (h & APIC_VECTOR_MASK) {
- printk(KERN_DEBUG "CPU#%d: Thermal LVT vector (%#x) already installed\n",
- cpu, (h & APIC_VECTOR_MASK));
- return; /* -EBUSY */
- }
-
- /* The temperature transition interrupt handler setup */
- h = THERMAL_APIC_VECTOR; /* our delivery vector */
- h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
- apic_write_around(APIC_LVTTHMR, h);
-
- rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
- wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
-
- /* ok we're good to go... */
- vendor_thermal_interrupt = intel_thermal_interrupt;
-
- rdmsr(MSR_IA32_MISC_ENABLE, l, h);
- wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
-
- l = apic_read(APIC_LVTTHMR);
- apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
- printk(KERN_INFO "CPU#%d: Thermal monitoring enabled\n", cpu);
- return;
-}
-#endif /* CONFIG_X86_MCE_P4THERMAL */
-
-
-/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
-
-static int inline intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
-{
- u32 h;
-
- if (mce_num_extended_msrs == 0)
- goto done;
-
- rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
- rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
- rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
- rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
- rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
- rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
- rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
- rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
- rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
- rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
-
- /* can we rely on kmalloc to do a dynamic
- * allocation for the reserved registers?
- */
-done:
- return mce_num_extended_msrs;
-}
-
-/*
- * Machine Check Handler For PII/PIII
- */
-
-static void intel_machine_check(struct pt_regs * regs, long error_code)
-{
- int recover=1;
- u32 alow, ahigh, high, low;
- u32 mcgstl, mcgsth;
- int i;
- struct intel_mce_extended_msrs dbg;
-
- rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
- if(mcgstl&(1<<0)) /* Recoverable ? */
- recover=0;
-
- printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", smp_processor_id(), mcgsth, mcgstl);
-
- if (intel_get_extended_msrs(&dbg)) {
- printk(KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n",
- smp_processor_id(), dbg.eip, dbg.eflags);
- printk(KERN_DEBUG "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n",
- dbg.eax, dbg.ebx, dbg.ecx, dbg.edx);
- printk(KERN_DEBUG "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
- dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
- }
-
- for (i=0;i<banks;i++) {
- rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high);
- if(high&(1<<31)) {
- if(high&(1<<29))
- recover|=1;
- if(high&(1<<25))
- recover|=2;
- printk(KERN_EMERG "Bank %d: %08x%08x", i, high, low);
- high&=~(1<<31);
- if(high&(1<<27)) {
- rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
- printk("[%08x%08x]", ahigh, alow);
- }
- if(high&(1<<26)) {
- rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
- printk(" at %08x%08x", ahigh, alow);
- }
- printk("\n");
- /* Clear it */
- wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
- /* Serialize */
- wmb();
- }
- }
-
- if(recover&2)
- panic("CPU context corrupt");
- if(recover&1)
- panic("Unable to continue");
- printk(KERN_EMERG "Attempting to continue.\n");
- mcgstl&=~(1<<2);
- wrmsr(MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
-}
-
-/*
- * Machine check handler for Pentium class Intel
- */
-
-static void pentium_machine_check(struct pt_regs * regs, long error_code)
-{
- u32 loaddr, hi, lotype;
- rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
- rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
- printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
- if(lotype&(1<<5))
- printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
-}
-
-/*
- * Machine check handler for WinChip C6
- */
-
-static void winchip_machine_check(struct pt_regs * regs, long error_code)
-{
- printk(KERN_EMERG "CPU#%d: Machine Check Exception.\n", smp_processor_id());
-}
-
-/*
- * Handle unconfigured int18 (should never happen)
- */
-
-static void unexpected_machine_check(struct pt_regs * regs, long error_code)
-{
- printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", smp_processor_id());
-}
-
-/*
- * Call the installed machine check handler for this CPU setup.
- */
-
-static void (*machine_check_vector)(struct pt_regs *, long error_code) = unexpected_machine_check;
-
-asmlinkage void do_machine_check(struct pt_regs * regs, long error_code)
-{
- machine_check_vector(regs, error_code);
-}
-
-
-#ifdef CONFIG_X86_MCE_NONFATAL
-static struct timer_list mce_timer;
-static int timerset = 0;
-
-#define MCE_RATE 15*HZ /* timer rate is 15s */
-
-static void mce_checkregs (void *info)
-{
- u32 low, high;
- int i;
-
- preempt_disable();
- for (i=0; i<banks; i++) {
- rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
-
- if ((low | high) != 0) {
- printk (KERN_EMERG "MCE: The hardware reports a non fatal, correctable incident occured on CPU %d.\n", smp_processor_id());
- printk (KERN_EMERG "Bank %d: %08x%08x\n", i, high, low);
-
- /* Scrub the error so we don't pick it up in MCE_RATE seconds time. */
- wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
-
- /* Serialize */
- wmb();
- }
- }
- preempt_enable();
-}
-
-static void do_mce_timer(void *data)
-{
- smp_call_function (mce_checkregs, NULL, 1, 1);
-}
-
-static DECLARE_WORK(mce_work, do_mce_timer, NULL);
-
-static void mce_timerfunc (unsigned long data)
-{
-#ifdef CONFIG_SMP
- if (num_online_cpus() > 1)
- schedule_work(&mce_work);
-#else
- mce_checkregs(NULL);
-#endif
- mce_timer.expires = jiffies + MCE_RATE;
- add_timer (&mce_timer);
-}
-#endif
-
-
-/*
- * Set up machine check reporting for processors with Intel style MCE
- */
-
-static void __init intel_mcheck_init(struct cpuinfo_x86 *c)
-{
- u32 l, h;
- int i;
- static int done;
-
- /*
- * Check for MCE support
- */
-
- if( !cpu_has(c, X86_FEATURE_MCE) )
- return;
-
- /*
- * Pentium machine check
- */
-
- if(c->x86 == 5)
- {
- /* Default P5 to off as its often misconnected */
- if(mce_disabled != -1)
- return;
- machine_check_vector = pentium_machine_check;
- wmb();
- /* Read registers before enabling */
- rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
- rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
- if(done==0)
- printk(KERN_INFO "Intel old style machine check architecture supported.\n");
- /* Enable MCE */
- set_in_cr4(X86_CR4_MCE);
- printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());
- return;
- }
-
-
- /*
- * Check for PPro style MCA
- */
-
- if( !cpu_has(c, X86_FEATURE_MCA) )
- return;
-
- /* Ok machine check is available */
-
- machine_check_vector = intel_machine_check;
- wmb();
-
- if(done==0)
- printk(KERN_INFO "Intel machine check architecture supported.\n");
- rdmsr(MSR_IA32_MCG_CAP, l, h);
- if(l&(1<<8)) /* Control register present ? */
- wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
- banks = l&0xff;
-
- /* Don't enable bank 0 on intel P6 cores, it goes bang quickly. */
- if (c->x86_vendor == X86_VENDOR_INTEL && c->x86 == 6) {
- for(i=1; i<banks; i++)
- wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
- } else {
- for(i=0; i<banks; i++)
- wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
- }
-
- for(i=0; i<banks; i++)
- wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
-
- set_in_cr4(X86_CR4_MCE);
- printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", smp_processor_id());
-
- /*
- * Check for P4/Xeon specific MCE extensions
- */
-
- if (c->x86_vendor == X86_VENDOR_INTEL && c->x86 == 15) {
- /* Check for P4/Xeon extended MCE MSRs */
- rdmsr(MSR_IA32_MCG_CAP, l, h);
- if (l & (1<<9)) {/* MCG_EXT_P */
- mce_num_extended_msrs = (l >> 16) & 0xff;
- printk(KERN_INFO "CPU#%d: Intel P4/Xeon Extended MCE MSRs (%d) available\n",
- smp_processor_id(), mce_num_extended_msrs);
- }
-
-#ifdef CONFIG_X86_MCE_P4THERMAL
- /* Check for P4/Xeon Thermal monitor */
- intel_init_thermal(c);
-#endif
- }
-
- done=1;
-}
-
-/*
- * Set up machine check reporting on the Winchip C6 series
- */
-
-static void __init winchip_mcheck_init(struct cpuinfo_x86 *c)
-{
- u32 lo, hi;
- /* Not supported on C3 */
- if(c->x86 != 5)
- return;
- /* Winchip C6 */
- machine_check_vector = winchip_machine_check;
- wmb();
- rdmsr(MSR_IDT_FCR1, lo, hi);
- lo|= (1<<2); /* Enable EIERRINT (int 18 MCE) */
- lo&= ~(1<<4); /* Enable MCE */
- wrmsr(MSR_IDT_FCR1, lo, hi);
- set_in_cr4(X86_CR4_MCE);
- printk(KERN_INFO "Winchip machine check reporting enabled on CPU#%d.\n", smp_processor_id());
-}
-
-
-/*
- * This has to be run for each processor
- */
-
-void __init mcheck_init(struct cpuinfo_x86 *c)
-{
-
- if(mce_disabled==1)
- return;
-
- switch(c->x86_vendor)
- {
- case X86_VENDOR_AMD:
- /* AMD K7 machine check is Intel like */
- if(c->x86 == 6 || c->x86 == 15) {
- intel_mcheck_init(c);
-#ifdef CONFIG_X86_MCE_NONFATAL
- if (timerset == 0) {
- /* Set the timer to check for non-fatal
- errors every MCE_RATE seconds */
- init_timer (&mce_timer);
- mce_timer.expires = jiffies + MCE_RATE;
- mce_timer.data = 0;
- mce_timer.function = &mce_timerfunc;
- add_timer (&mce_timer);
- timerset = 1;
- printk(KERN_INFO "Machine check exception polling timer started.\n");
- }
-#endif
- }
- break;
-
- case X86_VENDOR_INTEL:
- intel_mcheck_init(c);
- break;
-
- case X86_VENDOR_CENTAUR:
- winchip_mcheck_init(c);
- break;
-
- default:
- break;
- }
-}
-
-static int __init mcheck_disable(char *str)
-{
- mce_disabled = 1;
- return 0;
-}
-
-static int __init mcheck_enable(char *str)
-{
- mce_disabled = -1;
- return 0;
-}
-
-__setup("nomce", mcheck_disable);
-__setup("mce", mcheck_enable);
-
-#else
-asmlinkage void do_machine_check(struct pt_regs * regs, long error_code) {}
-asmlinkage void smp_thermal_interrupt(struct pt_regs regs) {}
-void __init mcheck_init(struct cpuinfo_x86 *c) {}
-#endif
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/Makefile linux-2.5/arch/i386/kernel/cpu/Makefile
--- bk-linus/arch/i386/kernel/cpu/Makefile 2002-10-20 20:21:24.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/Makefile 2002-10-25 18:02:31.000000000 -0100
@@ -13,7 +13,10 @@ obj-y += rise.o
obj-y += nexgen.o
obj-y += umc.o
+obj-y += mcheck/
+
obj-$(CONFIG_MTRR) += mtrr/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
+
include $(TOPDIR)/Rules.make
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mcheck/Makefile linux-2.5/arch/i386/kernel/cpu/mcheck/Makefile
--- bk-linus/arch/i386/kernel/cpu/mcheck/Makefile 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mcheck/Makefile 2002-10-25 18:02:31.000000000 -0100
@@ -0,0 +1,4 @@
+obj-y = mce.o k7.o p4.o p5.o p6.o winchip.o
+
+include $(TOPDIR)/Rules.make
+
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mcheck/k7.c linux-2.5/arch/i386/kernel/cpu/mcheck/k7.c
--- bk-linus/arch/i386/kernel/cpu/mcheck/k7.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mcheck/k7.c 2002-10-25 18:02:31.000000000 -0100
@@ -0,0 +1,159 @@
+/*
+ * Athlon specific Machine Check Exception Reporting
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/jiffies.h>
+#include <linux/config.h>
+#include <linux/irq.h>
+#include <linux/workqueue.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/msr.h>
+
+#include "mce.h"
+
+static int banks;
+
+/* Machine Check Handler For AMD Athlon/Duron */
+static void k7_machine_check(struct pt_regs * regs, long error_code)
+{
+ int recover=1;
+ u32 alow, ahigh, high, low;
+ u32 mcgstl, mcgsth;
+ int i;
+
+ rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
+ if(mcgstl&(1<<0)) /* Recoverable ? */
+ recover=0;
+
+ printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", smp_processor_id(), mcgsth, mcgstl);
+
+ for (i=0;i<banks;i++) {
+ rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high);
+ if(high&(1<<31)) {
+ if(high&(1<<29))
+ recover|=1;
+ if(high&(1<<25))
+ recover|=2;
+ printk(KERN_EMERG "Bank %d: %08x%08x", i, high, low);
+ high&=~(1<<31);
+ if(high&(1<<27)) {
+ rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
+ printk("[%08x%08x]", ahigh, alow);
+ }
+ if(high&(1<<26)) {
+ rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
+ printk(" at %08x%08x", ahigh, alow);
+ }
+ printk("\n");
+ /* Clear it */
+ wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
+ /* Serialize */
+ wmb();
+ }
+ }
+
+ if(recover&2)
+ panic("CPU context corrupt");
+ if(recover&1)
+ panic("Unable to continue");
+ printk(KERN_EMERG "Attempting to continue.\n");
+ mcgstl&=~(1<<2);
+ wrmsr(MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+}
+
+
+#ifdef CONFIG_X86_MCE_NONFATAL
+static struct timer_list mce_timer;
+static int timerset = 0;
+
+#define MCE_RATE 15*HZ /* timer rate is 15s */
+
+static void mce_checkregs (void *info)
+{
+ u32 low, high;
+ int i;
+
+ preempt_disable();
+ for (i=0; i<banks; i++) {
+ rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
+
+ if ((low | high) != 0) {
+ printk (KERN_EMERG "MCE: The hardware reports a non fatal, correctable incident occured on CPU %d.\n", smp_processor_id());
+ printk (KERN_EMERG "Bank %d: %08x%08x\n", i, high, low);
+
+ /* Scrub the error so we don't pick it up in MCE_RATE seconds time. */
+ wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
+
+ /* Serialize */
+ wmb();
+ }
+ }
+ preempt_enable();
+}
+
+static void do_mce_timer(void *data)
+{
+ smp_call_function (mce_checkregs, NULL, 1, 1);
+}
+
+static DECLARE_WORK(mce_work, do_mce_timer, NULL);
+
+static void mce_timerfunc (unsigned long data)
+{
+#ifdef CONFIG_SMP
+ if (num_online_cpus() > 1)
+ schedule_work(&mce_work);
+#else
+ mce_checkregs(NULL);
+#endif /* SMP */
+ mce_timer.expires = jiffies + MCE_RATE;
+ add_timer (&mce_timer);
+}
+#endif /* NON_FATAL */
+
+
+/* AMD K7 machine check is Intel like */
+void __init amd_mcheck_init(struct cpuinfo_x86 *c)
+{
+ u32 l, h;
+ int i;
+
+ machine_check_vector = k7_machine_check;
+ wmb();
+
+ printk(KERN_INFO "Intel machine check architecture supported.\n");
+ rdmsr(MSR_IA32_MCG_CAP, l, h);
+ if(l&(1<<8)) /* Control register present ? */
+ wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+ banks = l&0xff;
+
+ for(i=0; i<banks; i++)
+ wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+
+ for(i=0; i<banks; i++)
+ wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+
+ set_in_cr4(X86_CR4_MCE);
+ printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", smp_processor_id());
+
+#ifdef CONFIG_X86_MCE_NONFATAL
+ if (timerset == 0) {
+ /* Set the timer to check for non-fatal
+ errors every MCE_RATE seconds */
+ init_timer (&mce_timer);
+ mce_timer.expires = jiffies + MCE_RATE;
+ mce_timer.data = 0;
+ mce_timer.function = &mce_timerfunc;
+ add_timer (&mce_timer);
+ timerset = 1;
+ printk(KERN_INFO "Machine check exception polling timer started.\n");
+ }
+#endif
+}
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mcheck/mce.c linux-2.5/arch/i386/kernel/cpu/mcheck/mce.c
--- bk-linus/arch/i386/kernel/cpu/mcheck/mce.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mcheck/mce.c 2002-10-25 18:02:32.000000000 -0100
@@ -0,0 +1,84 @@
+/*
+ * mce.c - x86 Machine Check Exception Reporting
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <linux/smp.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/thread_info.h>
+
+#include "mce.h"
+
+#ifdef CONFIG_X86_MCE
+
+int mce_disabled __initdata = 0;
+
+/* Handle unconfigured int18 (should never happen) */
+static void unexpected_machine_check(struct pt_regs * regs, long error_code)
+{
+ printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", smp_processor_id());
+}
+
+/* Call the installed machine check handler for this CPU setup. */
+void (*machine_check_vector)(struct pt_regs *, long error_code) = unexpected_machine_check;
+
+asmlinkage void do_machine_check(struct pt_regs * regs, long error_code)
+{
+ machine_check_vector(regs, error_code);
+}
+
+/* This has to be run for each processor */
+void __init mcheck_init(struct cpuinfo_x86 *c)
+{
+ if(mce_disabled==1)
+ return;
+
+ switch(c->x86_vendor) {
+ case X86_VENDOR_AMD:
+ if (c->x86==6 || c->x86==15)
+ amd_mcheck_init(c);
+ break;
+
+ case X86_VENDOR_INTEL:
+ if (c->x86==5)
+ intel_p5_mcheck_init(c);
+ if (c->x86==6)
+ intel_p6_mcheck_init(c);
+ if (c->x86==15)
+ intel_p4_mcheck_init(c);
+ break;
+
+ case X86_VENDOR_CENTAUR:
+ if (c->x86==5)
+ winchip_mcheck_init(c);
+ break;
+
+ default:
+ break;
+ }
+}
+
+static int __init mcheck_disable(char *str)
+{
+ mce_disabled = 1;
+ return 0;
+}
+
+static int __init mcheck_enable(char *str)
+{
+ mce_disabled = -1;
+ return 0;
+}
+
+__setup("nomce", mcheck_disable);
+__setup("mce", mcheck_enable);
+
+#else
+asmlinkage void do_machine_check(struct pt_regs * regs, long error_code) {}
+asmlinkage void smp_thermal_interrupt(struct pt_regs regs) {}
+void __init mcheck_init(struct cpuinfo_x86 *c) {}
+#endif
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mcheck/mce.h linux-2.5/arch/i386/kernel/cpu/mcheck/mce.h
--- bk-linus/arch/i386/kernel/cpu/mcheck/mce.h 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mcheck/mce.h 2002-10-25 18:02:32.000000000 -0100
@@ -0,0 +1,12 @@
+#include <linux/init.h>
+
+void amd_mcheck_init(struct cpuinfo_x86 *c);
+void intel_p4_mcheck_init(struct cpuinfo_x86 *c);
+void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
+void intel_p6_mcheck_init(struct cpuinfo_x86 *c);
+void winchip_mcheck_init(struct cpuinfo_x86 *c);
+
+/* Call the installed machine check handler for this CPU setup. */
+extern void (*machine_check_vector)(struct pt_regs *, long error_code);
+
+extern int mce_disabled __initdata;
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mcheck/p4.c linux-2.5/arch/i386/kernel/cpu/mcheck/p4.c
--- bk-linus/arch/i386/kernel/cpu/mcheck/p4.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mcheck/p4.c 2002-10-25 18:02:32.000000000 -0100
@@ -0,0 +1,244 @@
+/*
+ * P4 specific Machine Check Exception Reporting
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/msr.h>
+#include <asm/apic.h>
+
+#include "mce.h"
+
+/* as supported by the P4/Xeon family */
+struct intel_mce_extended_msrs {
+ u32 eax;
+ u32 ebx;
+ u32 ecx;
+ u32 edx;
+ u32 esi;
+ u32 edi;
+ u32 ebp;
+ u32 esp;
+ u32 eflags;
+ u32 eip;
+ /* u32 *reserved[]; */
+};
+
+static int mce_num_extended_msrs = 0;
+static int banks;
+
+
+#ifdef CONFIG_X86_MCE_P4THERMAL
+static void unexpected_thermal_interrupt(struct pt_regs *regs)
+{
+ printk(KERN_ERR "CPU#%d: Unexpected LVT TMR interrupt!\n", smp_processor_id());
+}
+
+/* P4/Xeon Thermal transition interrupt handler */
+static void intel_thermal_interrupt(struct pt_regs *regs)
+{
+ u32 l, h;
+ unsigned int cpu = smp_processor_id();
+
+ ack_APIC_irq();
+
+ rdmsr(MSR_IA32_THERM_STATUS, l, h);
+ if (l & 1) {
+ printk(KERN_EMERG "CPU#%d: Temperature above threshold\n", cpu);
+ printk(KERN_EMERG "CPU#%d: Running in modulated clock mode\n", cpu);
+ } else {
+ printk(KERN_INFO "CPU#%d: Temperature/speed normal\n", cpu);
+ }
+}
+
+/* Thermal interrupt handler for this CPU setup */
+static void (*vendor_thermal_interrupt)(struct pt_regs *regs) = unexpected_thermal_interrupt;
+
+asmlinkage void smp_thermal_interrupt(struct pt_regs regs)
+{
+ irq_enter();
+ vendor_thermal_interrupt(®s);
+ irq_exit();
+}
+
+/* P4/Xeon Thermal regulation detect and init */
+static void __init intel_init_thermal(struct cpuinfo_x86 *c)
+{
+ u32 l, h;
+ unsigned int cpu = smp_processor_id();
+
+ /* Thermal monitoring */
+ if (!cpu_has(c, X86_FEATURE_ACPI))
+ return; /* -ENODEV */
+
+ /* Clock modulation */
+ if (!cpu_has(c, X86_FEATURE_ACC))
+ return; /* -ENODEV */
+
+ /* first check if its enabled already, in which case there might
+ * be some SMM goo which handles it, so we can't even put a handler
+ * since it might be delivered via SMI already -zwanem.
+ */
+ rdmsr(MSR_IA32_MISC_ENABLE, l, h);
+ h = apic_read(APIC_LVTTHMR);
+ if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
+ printk(KERN_DEBUG "CPU#%d: Thermal monitoring handled by SMI\n", cpu);
+ return; /* -EBUSY */
+ }
+
+ /* check whether a vector already exists, temporarily masked? */
+ if (h & APIC_VECTOR_MASK) {
+ printk(KERN_DEBUG "CPU#%d: Thermal LVT vector (%#x) already installed\n",
+ cpu, (h & APIC_VECTOR_MASK));
+ return; /* -EBUSY */
+ }
+
+ /* The temperature transition interrupt handler setup */
+ h = THERMAL_APIC_VECTOR; /* our delivery vector */
+ h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
+ apic_write_around(APIC_LVTTHMR, h);
+
+ rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
+ wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
+
+ /* ok we're good to go... */
+ vendor_thermal_interrupt = intel_thermal_interrupt;
+
+ rdmsr(MSR_IA32_MISC_ENABLE, l, h);
+ wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
+
+ l = apic_read(APIC_LVTTHMR);
+ apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
+ printk(KERN_INFO "CPU#%d: Thermal monitoring enabled\n", cpu);
+ return;
+}
+#endif /* CONFIG_X86_MCE_P4THERMAL */
+
+
+/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
+static int inline intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
+{
+ u32 h;
+
+ if (mce_num_extended_msrs == 0)
+ goto done;
+
+ rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
+ rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
+ rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
+ rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
+ rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
+ rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
+ rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
+ rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
+ rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
+ rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
+
+ /* can we rely on kmalloc to do a dynamic
+ * allocation for the reserved registers?
+ */
+done:
+ return mce_num_extended_msrs;
+}
+
+static void intel_machine_check(struct pt_regs * regs, long error_code)
+{
+ int recover=1;
+ u32 alow, ahigh, high, low;
+ u32 mcgstl, mcgsth;
+ int i;
+ struct intel_mce_extended_msrs dbg;
+
+ rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
+ if(mcgstl&(1<<0)) /* Recoverable ? */
+ recover=0;
+
+ printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", smp_processor_id(), mcgsth, mcgstl);
+
+ if (intel_get_extended_msrs(&dbg)) {
+ printk(KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n",
+ smp_processor_id(), dbg.eip, dbg.eflags);
+ printk(KERN_DEBUG "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n",
+ dbg.eax, dbg.ebx, dbg.ecx, dbg.edx);
+ printk(KERN_DEBUG "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
+ dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
+ }
+
+ for (i=0;i<banks;i++) {
+ rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high);
+ if(high&(1<<31)) {
+ if(high&(1<<29))
+ recover|=1;
+ if(high&(1<<25))
+ recover|=2;
+ printk(KERN_EMERG "Bank %d: %08x%08x", i, high, low);
+ high&=~(1<<31);
+ if(high&(1<<27)) {
+ rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
+ printk("[%08x%08x]", ahigh, alow);
+ }
+ if(high&(1<<26)) {
+ rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
+ printk(" at %08x%08x", ahigh, alow);
+ }
+ printk("\n");
+ /* Clear it */
+ wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
+ /* Serialize */
+ wmb();
+ }
+ }
+
+ if(recover&2)
+ panic("CPU context corrupt");
+ if(recover&1)
+ panic("Unable to continue");
+ printk(KERN_EMERG "Attempting to continue.\n");
+ mcgstl&=~(1<<2);
+ wrmsr(MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+}
+
+void __init intel_p4_mcheck_init(struct cpuinfo_x86 *c)
+{
+ u32 l, h;
+ int i;
+
+ machine_check_vector = intel_machine_check;
+ wmb();
+
+ printk(KERN_INFO "Intel machine check architecture supported.\n");
+ rdmsr(MSR_IA32_MCG_CAP, l, h);
+ if(l&(1<<8)) /* Control register present ? */
+ wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+ banks = l&0xff;
+
+ for(i=1; i<banks; i++)
+ wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+
+ for(i=0; i<banks; i++)
+ wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+
+ set_in_cr4(X86_CR4_MCE);
+ printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", smp_processor_id());
+
+ /* Check for P4/Xeon extended MCE MSRs */
+ rdmsr(MSR_IA32_MCG_CAP, l, h);
+ if (l & (1<<9)) {/* MCG_EXT_P */
+ mce_num_extended_msrs = (l >> 16) & 0xff;
+ printk(KERN_INFO "CPU#%d: Intel P4/Xeon Extended MCE MSRs (%d) available\n",
+ smp_processor_id(), mce_num_extended_msrs);
+
+#ifdef CONFIG_X86_MCE_P4THERMAL
+ /* Check for P4/Xeon Thermal monitor */
+ intel_init_thermal(c);
+#endif
+ }
+}
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mcheck/p5.c linux-2.5/arch/i386/kernel/cpu/mcheck/p5.c
--- bk-linus/arch/i386/kernel/cpu/mcheck/p5.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mcheck/p5.c 2002-10-25 18:02:32.000000000 -0100
@@ -0,0 +1,52 @@
+/*
+ * P5 specific Machine Check Exception Reporting
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/msr.h>
+
+#include "mce.h"
+
+/* Machine check handler for Pentium class Intel */
+static void pentium_machine_check(struct pt_regs * regs, long error_code)
+{
+ u32 loaddr, hi, lotype;
+ rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
+ rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
+ printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
+ if(lotype&(1<<5))
+ printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
+}
+
+/* Set up machine check reporting for processors with Intel style MCE */
+void __init intel_p5_mcheck_init(struct cpuinfo_x86 *c)
+{
+ u32 l, h;
+
+ /*Check for MCE support */
+ if( !cpu_has(c, X86_FEATURE_MCE) )
+ return;
+
+ /* Default P5 to off as its often misconnected */
+ if(mce_disabled != -1)
+ return;
+ machine_check_vector = pentium_machine_check;
+ wmb();
+
+ /* Read registers before enabling */
+ rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
+ rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
+ printk(KERN_INFO "Intel old style machine check architecture supported.\n");
+
+ /* Enable MCE */
+ set_in_cr4(X86_CR4_MCE);
+ printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());
+}
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mcheck/p6.c linux-2.5/arch/i386/kernel/cpu/mcheck/p6.c
--- bk-linus/arch/i386/kernel/cpu/mcheck/p6.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mcheck/p6.c 2002-10-25 18:02:32.000000000 -0100
@@ -0,0 +1,101 @@
+/*
+ * P6 specific Machine Check Exception Reporting
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/msr.h>
+
+#include "mce.h"
+
+static int banks;
+
+/* Machine Check Handler For PII/PIII */
+static void intel_machine_check(struct pt_regs * regs, long error_code)
+{
+ int recover=1;
+ u32 alow, ahigh, high, low;
+ u32 mcgstl, mcgsth;
+ int i;
+
+ rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
+ if(mcgstl&(1<<0)) /* Recoverable ? */
+ recover=0;
+
+ printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", smp_processor_id(), mcgsth, mcgstl);
+
+ for (i=0;i<banks;i++) {
+ rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high);
+ if(high&(1<<31)) {
+ if(high&(1<<29))
+ recover|=1;
+ if(high&(1<<25))
+ recover|=2;
+ printk(KERN_EMERG "Bank %d: %08x%08x", i, high, low);
+ high&=~(1<<31);
+ if(high&(1<<27)) {
+ rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
+ printk("[%08x%08x]", ahigh, alow);
+ }
+ if(high&(1<<26)) {
+ rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
+ printk(" at %08x%08x", ahigh, alow);
+ }
+ printk("\n");
+ /* Clear it */
+ wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
+ /* Serialize */
+ wmb();
+ }
+ }
+
+ if(recover&2)
+ panic("CPU context corrupt");
+ if(recover&1)
+ panic("Unable to continue");
+ printk(KERN_EMERG "Attempting to continue.\n");
+ mcgstl&=~(1<<2);
+ wrmsr(MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+}
+
+/* Set up machine check reporting for processors with Intel style MCE */
+void __init intel_p6_mcheck_init(struct cpuinfo_x86 *c)
+{
+ u32 l, h;
+ int i;
+
+ /* Check for MCE support */
+ if( !cpu_has(c, X86_FEATURE_MCE) )
+ return;
+
+ /* Check for PPro style MCA */
+ if( !cpu_has(c, X86_FEATURE_MCA) )
+ return;
+
+ /* Ok machine check is available */
+ machine_check_vector = intel_machine_check;
+ wmb();
+
+ printk(KERN_INFO "Intel machine check architecture supported.\n");
+ rdmsr(MSR_IA32_MCG_CAP, l, h);
+ if(l&(1<<8)) /* Control register present ? */
+ wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+ banks = l&0xff;
+
+ /* Don't enable bank 0 on intel P6 cores, it goes bang quickly. */
+ for(i=1; i<banks; i++)
+ wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+
+ for(i=0; i<banks; i++)
+ wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+
+ set_in_cr4(X86_CR4_MCE);
+ printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", smp_processor_id());
+}
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mcheck/winchip.c linux-2.5/arch/i386/kernel/cpu/mcheck/winchip.c
--- bk-linus/arch/i386/kernel/cpu/mcheck/winchip.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mcheck/winchip.c 2002-10-25 18:02:32.000000000 -0100
@@ -0,0 +1,35 @@
+/*
+ * IDT Winchip specific Machine Check Exception Reporting
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/msr.h>
+
+#include "mce.h"
+
+/* Machine check handler for WinChip C6 */
+static void winchip_machine_check(struct pt_regs * regs, long error_code)
+{
+ printk(KERN_EMERG "CPU0: Machine Check Exception.\n");
+}
+
+/* Set up machine check reporting on the Winchip C6 series */
+void __init winchip_mcheck_init(struct cpuinfo_x86 *c)
+{
+ u32 lo, hi;
+ machine_check_vector = winchip_machine_check;
+ wmb();
+ rdmsr(MSR_IDT_FCR1, lo, hi);
+ lo|= (1<<2); /* Enable EIERRINT (int 18 MCE) */
+ lo&= ~(1<<4); /* Enable MCE */
+ wrmsr(MSR_IDT_FCR1, lo, hi);
+ set_in_cr4(X86_CR4_MCE);
+ printk(KERN_INFO "Winchip machine check reporting enabled on CPU#0.\n");
+}
^ permalink raw reply
* promise sx6000 success / raid options
From: Mikael Abrahamsson @ 2002-10-26 12:35 UTC (permalink / raw)
To: linux-raid
I had initial problems with a Promise SX6000 controller with the i2o block
driver and I also tried their source pti_st.o code but never got it to
compile. I emailed promise and got a response back quite quickly which
provided me with a new version of the source code version, plus beta
drivers they themselves compiled for redhat 7.3 and redhat 8.0 kernels.
I have today started using the redhat 8.0 kernel driver and it seems to
work very well. Write performance is approx 15 meg/s to a 5 times 120gig
drive stripe (seems a bit on the low side if you ask me but that's ok
anyway, perhaps ext3 is slowing things down). I recommend anyone who have
problems with their SX6000 to do the same.
I made the filesystem with just mke2fs -j and no raid options, is the
"stride" options anything I should use? Does it provide better
performance? (I tried finding some information on this, but the mke2fs man
page is so spread that all the search engines give me are copies of the
man page).
--
Mikael Abrahamsson email: swmike@swm.pp.se
^ permalink raw reply
* [PATCH] silence MTRR debugging.
From: davej @ 2002-10-26 12:42 UTC (permalink / raw)
To: linux-kernel; +Cc: alan
Remove debugging noise.
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/mtrr/generic.c linux-2.5/arch/i386/kernel/cpu/mtrr/generic.c
--- bk-linus/arch/i386/kernel/cpu/mtrr/generic.c 2002-10-20 20:21:25.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mtrr/generic.c 2002-10-25 15:39:27.000000000 -0100
@@ -312,8 +312,6 @@ static void generic_set_mtrr(unsigned in
{
prepare_set();
- printk("MTRR: setting reg %x\n",reg);
-
if (size == 0) {
/* The invalid bit is kept in the mask, so we simply clear the
relevant mask register to disable a range. */
^ permalink raw reply
* [PATCH] max_cpus overflow.
From: davej @ 2002-10-26 12:42 UTC (permalink / raw)
To: linux-kernel; +Cc: alan
Without the below patch, my HT 2-way prints out
"CPUS Done 4294967295" on boot, which whilst amusing
is somewhat exaggerated.
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/init/main.c linux-2.5/init/main.c
--- bk-linus/init/main.c 2002-10-20 20:34:00.000000000 -0100
+++ linux-2.5/init/main.c 2002-10-25 15:43:43.000000000 -0100
@@ -100,7 +100,7 @@ int rows, cols;
char *execute_command;
/* Setup configured maximum number of CPUs to activate */
-static unsigned int max_cpus = UINT_MAX;
+static unsigned int max_cpus = NR_CPUS;
/*
* Setup routine for controlling SMP activation
^ permalink raw reply
* [PATCH] Double x86 initialise fix.
From: davej @ 2002-10-26 12:42 UTC (permalink / raw)
To: linux-kernel; +Cc: alan
For many moons, we've been executing identify_cpu()
on the boot processor twice on SMP kernels.
This is harmless, but has a few downsides..
- Extra cruft in bootlog/dmesg
- Spawns one too many timers for the mcheck handler
- possibly other wasteful things..
This seems to do the right thing here..
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/smpboot.c linux-2.5/arch/i386/kernel/smpboot.c
--- bk-linus/arch/i386/kernel/smpboot.c 2002-10-20 20:21:24.000000000 -0100
+++ linux-2.5/arch/i386/kernel/smpboot.c 2002-10-25 15:39:26.000000000 -0100
@@ -118,7 +118,8 @@ static void __init smp_store_cpu_info(in
struct cpuinfo_x86 *c = cpu_data + id;
*c = boot_cpu_data;
- identify_cpu(c);
+ if (id!=0)
+ identify_cpu(c);
/*
* Mask B, Pentium, but not Pentium MMX
*/
^ permalink raw reply
* [PATCH] Clean up capabilities printing.
From: davej @ 2002-10-26 12:42 UTC (permalink / raw)
To: linux-kernel; +Cc: alan
The machine check initialisation prints some blurb
which makes the capabilities dumping a little untidy.
By initialising it slightly later, we get something that
looks a lot better.
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/common.c linux-2.5/arch/i386/kernel/cpu/common.c
--- bk-linus/arch/i386/kernel/cpu/common.c 2002-10-20 20:21:24.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/common.c 2002-10-25 15:39:26.000000000 -0100
@@ -315,9 +315,6 @@ void __init identify_cpu(struct cpuinfo_
clear_bit(X86_FEATURE_XMM, c->x86_capability);
}
- /* Init Machine Check Exception if available. */
- mcheck_init(c);
-
/* If the model name is still unset, do table lookup. */
if ( !c->x86_model_id[0] ) {
char *p;
@@ -355,6 +352,9 @@ void __init identify_cpu(struct cpuinfo_
boot_cpu_data.x86_capability[1],
boot_cpu_data.x86_capability[2],
boot_cpu_data.x86_capability[3]);
+
+ /* Init Machine Check Exception if available. */
+ mcheck_init(c);
}
/*
* Perform early boot up checks for a valid TSC. See arch/i386/kernel/time.c
^ permalink raw reply
* Console settings.
From: geoff bagley @ 2002-10-26 12:33 UTC (permalink / raw)
To: linux-newbie
I have a dual-boot system with Debian Woody on hda, and SuSE 8.0 on hdb.
They both work well, and share a common hdc.
When I set up the Konsole settings, changing for example, the Schema and
the font size,
and then hit the Save Setting button on Debian, they STAY saved, and are
there next
time I boot up. On SuSE I have to re-set them each time.
Is this a bug, and can I fix it ?
Best regards,
Geoff
G3FHL
-
To unsubscribe from this list: send the line "unsubscribe linux-newbie" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.linux-learn.org/faqs
^ permalink raw reply
* Re: [CFT] faster athlon/duron memory copy implementation
From: Jurjen Oskam @ 2002-10-26 12:11 UTC (permalink / raw)
To: linux-kernel
In-Reply-To: <3DB82ABF.8030706@colorfullife.com>
On Thu, Oct 24, 2002 at 07:15:43PM +0200, Manfred Spraul wrote:
> Attached is a test app that compares several memory copy implementations.
> Could you run it and report the results to me, together with cpu,
> chipset and memory type?
joskam@hobbes:~> gcc -v
Reading specs from /usr/lib/gcc-lib/i486-suse-linux/2.95.3/specs
gcc version 2.95.3 20010315 (SuSE)
joskam@hobbes:~> gcc athlon.c
joskam@hobbes:~> ./a.out
Athlon test program $Id: fast.c,v 1.6 2000/09/23 09:05:45 arjan Exp $
copy_page() tests
copy_page function 'warm up run' took 19425 cycles per page
copy_page function '2.4 non MMX' took 22285 cycles per page
copy_page function '2.4 MMX fallback' took 21698 cycles per page
copy_page function '2.4 MMX version' took 19587 cycles per page
copy_page function 'faster_copy' took 11082 cycles per page
copy_page function 'even_faster' took 11203 cycles per page
copy_page function 'no_prefetch' took 7140 cycles per page
joskam@hobbes:~> ./a.out
Athlon test program $Id: fast.c,v 1.6 2000/09/23 09:05:45 arjan Exp $
copy_page() tests
copy_page function 'warm up run' took 19463 cycles per page
copy_page function '2.4 non MMX' took 22378 cycles per page
copy_page function '2.4 MMX fallback' took 21863 cycles per page
copy_page function '2.4 MMX version' took 19558 cycles per page
copy_page function 'faster_copy' took 11036 cycles per page
copy_page function 'even_faster' took 11292 cycles per page
copy_page function 'no_prefetch' took 7152 cycles per page
joskam@hobbes:~> ./a.out
Athlon test program $Id: fast.c,v 1.6 2000/09/23 09:05:45 arjan Exp $
copy_page() tests
copy_page function 'warm up run' took 21519 cycles per page
copy_page function '2.4 non MMX' took 22224 cycles per page
copy_page function '2.4 MMX fallback' took 21707 cycles per page
copy_page function '2.4 MMX version' took 19399 cycles per page
copy_page function 'faster_copy' took 11002 cycles per page
copy_page function 'even_faster' took 11211 cycles per page
copy_page function 'no_prefetch' took 7147 cycles per page
joskam@hobbes:~> cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 6
model : 6
model name : AMD Athlon(TM) XP1700+
stepping : 2
cpu MHz : 1477.400
cache size : 256 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov
pat pse36 mmx fxsr sse syscall mmxext 3dnowext 3dnow
bogomips : 2949.12
This was run on an Asus A7V266-E motherboard with a KT266A chipset, with
512 MB of DDR SDRAM.
--
Jurjen Oskam
PGP Key available at http://www.stupendous.org/
^ permalink raw reply
* Was: Trying to get GUI'ed
From: John E. Jay Maass @ 2002-10-26 11:01 UTC (permalink / raw)
To: linux-newbie
Bryan Simmons <bsimmo1@gl.umbc.edu> writes:
> Think that was informative? Learn assembly on x86 Linux.
> You have NO idea what a computer goes through just to add
> two numbers, let alone manage network traffic... The most
> shocking part is the idea of virtual memory.
Bryan,
I thought my little RAM thing was informative, yeah. It was
intended as practical, nothing esoteric or high minded. About
assembly language, a friend of mine worked with it and I took
a peek. I would love to know a little assembly. What I read
of it was impossible for me to grasp. Somehow I get by. With
great perseverance I manage to eventually grasp a little of
what others take for granted. Certainly nothing like assembly,
though <grins>.
All best,
Jay
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^ permalink raw reply
* Re: Why cant the firewall machine resolve host names??
From: Antony Stone @ 2002-10-26 10:57 UTC (permalink / raw)
To: Netfilter mailinglist
In-Reply-To: <20021026104016.72923.qmail@web40712.mail.yahoo.com>
On Saturday 26 October 2002 11:40 am, Tasha Smith wrote:
> Hii,
> Sorry to keep bugging you, but i think i am finally getting this whole
> iptables thing. This is my exact script... Averything is working but the
> FIREWALL machine CAN NOT resolve host names? I cant surf the net with the
> firewall machine can you tell me why? I added the DNS rules but they didnt
> work?? All my lan computers can SURF the net?
I've snipped out stuff which seems okay....
> # Remove any existing rules from all chains.
> iptables --flush
> iptables -t nat --flush
> iptables -t mangle --flush
>
> # Unlimited access on the loopback interface.
> iptables -A INPUT -i lo -j ACCEPT
> iptables -A OUTPUT -o lo -j ACCEPT
>
> # Set the default policy to drop.
> iptables --policy INPUT DROP
> iptables --policy FORWARD DROP
> iptables --policy OUTPUT ACCEPT
>
> iptables -t nat --policy PREROUTING ACCEPT
> iptables -t nat --policy OUTPUT DROP ######
> iptables -t nat --policy POSTROUTING DROP
>
> # iptables -t mangle --policy PREROUTING DROP
> # iptables -t mangle --policy OUTPUT DROP
Never, never, never set a default drop policy on nat or mangle tables.
It will stop things working. The filter table is for filtering - do not try
to filter (ie drop or reject) packets in the other two tables.
> # Allow stateful connections
> iptables -A INPUT -m state --state ESTABLISHED,RELATED -j ACCEPT
> iptables -A OUTPUT -m state --state ESTABLISHED,RELATED -j ACCEPT
> iptables -A FORWARD -m state --state ESTABLISHED,RELATED -j ACCEPT
>
> # Allow Access for DNS service.
> if [ "$CONNECTION_TRACKING" = "1" ]; then
> iptables -A OUPUT -o eth0 -p udp \
You might want to spell OUTPUT correctly :-)
> -s $IP_INET --sport 1024:65535 \
Why are you restricting the source port to be above 1024 ? If you are
running a name daemon on the machine it might be using a source port of 53.
> -d 111.53.4.110 --dport 53 \
> -m state --state NEW -j ACCEPT
> fi
>
> iptables -A OUTPUT -o eth0 -p udp \
> -s $IP_INET --sport 1024:65535 \
> -d 111.53.4.110 --dport 53 -j ACCEPT
I don't quite understand why you have this rule as well as the conditional
one above ?
> iptables -A INPUT -i eth0 -p udp \
> -s 111.53.4.110 --sport 53 \
> -d $eth0_address --dport 1024:65535 -j ACCEPT
This should not be necessary because you have an ESTABLISHED,RELATED rule in
your INPUT chain already - that will allow the replies back.
> if [ "$CONNECTION_TRACKING" = "1" ]; then
> iptables -A OUTPUT -o eth0 -p tcp \
> -s $IP_INET --sport 1024:65535 \
> -d 111.53.4.110 --dport 53 \
> -m state --state NEW -j ACCEPT
> fi
>
> iptables -A OUTPUT -o eth0 -p tcp \
> -s $IP_INET --sport 1024:65535 \
> -d 111.53.4.110 --dport 53 \
Are you missing a -j ACCEPT on this rule ? Again, I don't understand why
you have this as well as the one immediately above.
> iptables -A INPUT -i eth0 -p tcp ! --syn \
> -s 111.53.4.110 --sport 53 \
> -d $IP_INET --dport 1024:65535 -j ACCEPT
Not necessary with the ESTABLISHED,RELATED rule.
Antony.
--
Anyone that's normal doesn't really achieve much.
- Mark Blair, Australian rocket engineer
^ permalink raw reply
* Re: Why are XMAS and NULLS scans not filtered with these rules?
From: Maciej Soltysiak @ 2002-10-26 10:46 UTC (permalink / raw)
To: Tasha Smith; +Cc: netfilter
In-Reply-To: <20021026011329.71679.qmail@web40707.mail.yahoo.com>
Hi,
Try -j REJECT --reject-with tcp-reset
This way you'll tell nmap: go away, the port is closed.
normal REJECT will issue an ICMP error message:
destination unreachable/port unreachable.
If you use DROP or simple REJECT nmap will say: filtered
If you use REJECT --reject-with tcp-reset it will say closed.
Note that, if you use any REJECT and not DROP, nmap will get the packets
and will try OS fingerprinting on them.
Also note that it does not really give a scanner anything. I recommend
using DROP and not caring about the nmap results.
NMAP also sends a ping and then a TCP ACK packet with --dport 80, just
before it starts scanning. You may want to track down the UNRELATED TCP
ACKs with -p tcp and -m state --state NEW together.
Regards,
Maciej Soltysiak
^ permalink raw reply
* Re: TCP DELAY
From: Rogier Wolff @ 2002-10-26 10:52 UTC (permalink / raw)
To: bert hubert, Latha B lingaiah, linux-kernel
In-Reply-To: <20021021065839.GA6108@outpost.ds9a.nl>
On Mon, Oct 21, 2002 at 08:58:39AM +0200, bert hubert wrote:
> On Sun, Oct 20, 2002 at 11:56:00PM -0700, Latha B lingaiah wrote:
> > Hi,
> >
> > While transfering a 42MB file, there seem to be a TCP
> > delay between the kernels 2.4.7 and 2.4.18.
>
> Don't do such short measurements, 4.5 seconds is no way to do statistics.
> TCP/IP does not start out at full speed but takes some time to find the
> right speed.
If all you do is repeatedly transfer small files of only 42Mb, the
difference of 18% between 3.7 and 4.4 seconds is quite measureable.
But you should measure the difference more than once, but I suspect
that this was indeed done.....
Roger.
--
** R.E.Wolff@BitWizard.nl ** http://www.BitWizard.nl/ ** +31-15-2600998 **
*-- BitWizard writes Linux device drivers for any device you may have! --*
* The Worlds Ecosystem is a stable system. Stable systems may experience *
* excursions from the stable situation. We are currently in such an *
* excursion: The stable situation does not include humans. ***************
^ permalink raw reply
* Re: loadlin with 2.5.?? kernels
From: robert w hall @ 2002-10-26 10:37 UTC (permalink / raw)
To: linux-kernel
In-Reply-To: <m1vg3plfi7.fsf@frodo.biederman.org>
In article <m1vg3plfi7.fsf@frodo.biederman.org>, Eric W. Biederman
<ebiederm@xmission.com> writes
>Mike Galbraith <efault@gmx.de> writes:
>
>> At 11:20 PM 10/25/2002 -0600, Eric W. Biederman wrote:
>> >Mike Galbraith <efault@gmx.de> writes:
>> >
>> > > I went back and double-checked my loadlin version, and it turned out I was
>> > > actually using 1.6a due to a fat finger. Version 1.6c booted fine (only
>one
>>
>> > > kernel tested) without Eric's help. 1.6a definitely needs Eric's help to
>> > boot.
>> >
>> >Darn. I guess the arguments for my patch may not be quite as good,
>> >but I still think it may be worth while.
>>
>> Well, cleanup is always a pretty fine argument. Since there only seem to be
>two
>>
>> of us loadlin users, you probably didn't loose much argument wise ;-) The
>other
>>
>> loadlin user reported failure at .38, so maybe your patch is needed sometimes
>> even with loadlin-1.6c. (other loadlin user listening?)
>
>Robert thanks for your reply.
(oops this thread is a bit messy now - sorry, I originally intended to
post off-list, [so as not to parade my ignorance in this august forum
:-) ], and made a cockup of withdrawing a post to LK)
>
>I just looked at what the loadlin 1.6c code does, and it's heuristic
>is just slightly more reliable. It assumes %ds is %cs+8....
well that relationship has held for about 9 years, so it was a fairly
safe bet when Hans was trying to fix 1.6a for win4lin :-)
> That
>happens to work but there is nothing in the kernel keeping that from
>being broken. So in practice it looks to be worthwhile to stabilize
>this interface.
agreed -
/ignorant query/
but if you aim for too much generality are you not eventually going to
need Hans Lermen to revisit his loadlin version of the startup code
(which is based in part on old code from head.S & misc.c of course)?
//
> So loadlin, and other bootloaders can work by design
>and not by chance.
might also be worth checking out linlod (which still is only a beta I
think) needs to run
>
>Eric
Bob
--
robert w hall
^ permalink raw reply
* Re: One for the Security Guru's
From: Henning P. Schmiedehausen @ 2002-10-26 10:46 UTC (permalink / raw)
To: linux-kernel
In-Reply-To: <20021026114452.B16359@bitwizard.nl>
Rogier Wolff <R.E.Wolff@BitWizard.nl> writes:
>On Thu, Oct 24, 2002 at 09:38:46AM +0000, Henning P. Schmiedehausen wrote:
>> Get the real thing. Checkpoint. PIX. But that's a little
>> more expensive than "xxx firewall based on Linux".
>PIX? Is that the one that breaks TCP/IP when an ACK is lost on
>the side that the data is coming from?
Depends on your PIX OS. As with any other OS, there are bugs and you
should monitor the vendor mailing lists for updates and fixes.
It did broke SACK once. There was an update and the problem was
solved. Thats what a vendor is for.
Regards
Henning
What did you think? That I fall bait to this troll? :-)
--
Dipl.-Inf. (Univ.) Henning P. Schmiedehausen -- Geschaeftsfuehrer
INTERMETA - Gesellschaft fuer Mehrwertdienste mbH hps@intermeta.de
Am Schwabachgrund 22 Fon.: 09131 / 50654-0 info@intermeta.de
D-91054 Buckenhof Fax.: 09131 / 50654-20
^ permalink raw reply
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