* LE APIs on other platforms
From: Mat Martineau @ 2011-10-23 12:12 UTC (permalink / raw)
To: linux-bluetooth
For those of you asking about iOS LE APIs at the Bluetooth summit,
here is the link to Apple's LE developer documentation:
http://developer.apple.com/library/ios/#documentation/CoreBluetooth/Reference/CoreBluetooth_Framework/_index.html
--
Mat Martineau
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum
^ permalink raw reply
* Re: [PATCH 00/28 v6] m68k: Convert to genirq
From: Geert Uytterhoeven @ 2011-10-23 12:12 UTC (permalink / raw)
To: Greg Ungerer; +Cc: linux-m68k, Thomas Gleixner, linux-kernel, netdev
In-Reply-To: <4EA3FA86.7000905@snapgear.com>
On Sun, Oct 23, 2011 at 13:29, Greg Ungerer <gerg@snapgear.com> wrote:
> On 10/23/2011 07:49 PM, Geert Uytterhoeven wrote:
>> On Thu, Oct 20, 2011 at 14:18, Geert Uytterhoeven<geert@linux-m68k.org>
>> wrote:
>>> On Sun, Sep 11, 2011 at 13:59, Geert Uytterhoeven<geert@linux-m68k.org>
>>> wrote:
>>>> This patch series converts the m68k/mmu (nommu was converted before)
>>>> architecture to the generic hardirq framework.
>>>>
>>>> á- [01/28] genirq: Add missing "else" in irq_shutdown()
>>>> á- [02/28] ide-{cd,floppy,tape}: Do not include<linux/irq.>
>>>> á- [03/28] keyboard: Do not include<linux/irq.>
>>>> á- [04/28] m68k/irq: Rename irq_controller to irq_chip
>>>> á- [05/28] m68k/irq: Kill irq_node_t typedef, always use struct
>>>> irq_node
>>>> á- [06/28] m68k/irq: Rename irq_node to irq_data
>>>> á- [07/28] m68k/irq: Switch irq_chip methods to "struct irq_data *data"
>>>> á- [08/28] m68k/irq: Rename setup_irq() to m68k_setup_irq() and make it
>>>> static
>>>> á- [09/28] m68k/irq: Extract irq_set_chip()
>>>> á- [10/28] m68k/irq: Add m68k_setup_irq_controller()
>>>> á- [11/28] m68k/irq: Rename {,__}m68k_handle_int()
>>>> á- [12/28] m68k/irq: Remove obsolete IRQ_FLG_* definitions and users
>>>> á- [13/28] m68k/irq: Add genirq support
>>>> á- [14/28] m68k/atari: Convert Atari to genirq
>>>> á- [15/28] m68k/atari: Remove code and comments about different irq
>>>> types
>>>> á- [16/28] m68k/amiga: Refactor amiints.c
>>>> á- [17/28] m68k/amiga: Convert Amiga to genirq
>>>> á- [18/28] m68k/amiga: Optimize interrupts using chain handlers
>>>> á- [19/28] m68k/mac: Convert Mac to genirq
>>>> á- [20/28] m68k/mac: Optimize interrupts using chain handlers
>>>> á- [21/28] m68k/hp300: Convert HP9000/300 and HP9000/400 to genirq
>>>> á- [22/28] m68k/vme: Convert VME to genirq
>>>> á- [23/28] m68k/apollo: Convert Apollo to genirq
>>>> á- [24/28] m68k/sun3: Use the kstat_irqs_cpu() wrapper
>>>> á- [25/28] m68k/sun3: Convert Sun3/3x to genirq
>>>> á- [26/28] m68k/q40: Convert Q40/Q60 to genirq
>>>> á- [27/28] m68k/irq: Remove obsolete m68k irq framework
>>>> á- [28/28] m68k/irq: Remove obsolete support for user vector interrupt
>>>> fixups
>>>>
>>>> Overview:
>>>> á- [01] is a fix for the core genirq code,
>>>
>>> This went into v3.1-rc6.
>>>
>>>> á- [02-03] are fixes to avoid compile problems later in the conversion
>>>> á áprocess,
>>>
>>> The keyboard path went into the tty -next tree.
>>> The IDE one is still pending (I've just resent it).
>>
>> The IDE one got acked in the mean time.
>>
>>>> I will update my m68k-genirq branch as soon as master.kernel.org is
>>>> available
>>>> again.
>>>
>>> Updated, on top of m68k master (which is at v3.1-rc10 now).
>>>
>>> http://git.kernel.org/?p=linux/kernel/git/geert/linux-m68k.git;a=shortlog;h=refs/heads/m68k-genirq
>>>
>>> If noone objects, I'd like to add this to the m68k master and for-3.2
>>> branches.
>>
>> I added it to m68k master.
>>
>> As there were several merge conflicts with current -next
>> (arch/m68k/kernel/Makefile_mm
>> due to the mmu/nommu merge, and drivers/net/macsonic.c in [12/28] due
>> to the network
>> driver reshuffling dance), I did not add it to for-3.2 and for-next,
>> but to for-3.3.
>>
>> Depending on Stephen's return during or after the merge window, and
>> the merge timing
>> of the m68knommu and netdev trees, I may stil try to sneak it in 3.2,
>> though.
>
> I can ask Linus to pull the m68knommu tree early in the merge window,
> if that will help.
Thanks, that will help. Then I can rebase on top of that.
And I'll split "[12/28] m68k/irq: Remove obsolete IRQ_FLG_*
definitions and users",
so the net/scsi/tty parts can hit the repective trees separately.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 00/28 v6] m68k: Convert to genirq
From: Geert Uytterhoeven @ 2011-10-23 12:12 UTC (permalink / raw)
To: Greg Ungerer; +Cc: linux-m68k, Thomas Gleixner, linux-kernel, netdev
In-Reply-To: <4EA3FA86.7000905@snapgear.com>
On Sun, Oct 23, 2011 at 13:29, Greg Ungerer <gerg@snapgear.com> wrote:
> On 10/23/2011 07:49 PM, Geert Uytterhoeven wrote:
>> On Thu, Oct 20, 2011 at 14:18, Geert Uytterhoeven<geert@linux-m68k.org>
>> wrote:
>>> On Sun, Sep 11, 2011 at 13:59, Geert Uytterhoeven<geert@linux-m68k.org>
>>> wrote:
>>>> This patch series converts the m68k/mmu (nommu was converted before)
>>>> architecture to the generic hardirq framework.
>>>>
>>>> á- [01/28] genirq: Add missing "else" in irq_shutdown()
>>>> á- [02/28] ide-{cd,floppy,tape}: Do not include<linux/irq.>
>>>> á- [03/28] keyboard: Do not include<linux/irq.>
>>>> á- [04/28] m68k/irq: Rename irq_controller to irq_chip
>>>> á- [05/28] m68k/irq: Kill irq_node_t typedef, always use struct
>>>> irq_node
>>>> á- [06/28] m68k/irq: Rename irq_node to irq_data
>>>> á- [07/28] m68k/irq: Switch irq_chip methods to "struct irq_data *data"
>>>> á- [08/28] m68k/irq: Rename setup_irq() to m68k_setup_irq() and make it
>>>> static
>>>> á- [09/28] m68k/irq: Extract irq_set_chip()
>>>> á- [10/28] m68k/irq: Add m68k_setup_irq_controller()
>>>> á- [11/28] m68k/irq: Rename {,__}m68k_handle_int()
>>>> á- [12/28] m68k/irq: Remove obsolete IRQ_FLG_* definitions and users
>>>> á- [13/28] m68k/irq: Add genirq support
>>>> á- [14/28] m68k/atari: Convert Atari to genirq
>>>> á- [15/28] m68k/atari: Remove code and comments about different irq
>>>> types
>>>> á- [16/28] m68k/amiga: Refactor amiints.c
>>>> á- [17/28] m68k/amiga: Convert Amiga to genirq
>>>> á- [18/28] m68k/amiga: Optimize interrupts using chain handlers
>>>> á- [19/28] m68k/mac: Convert Mac to genirq
>>>> á- [20/28] m68k/mac: Optimize interrupts using chain handlers
>>>> á- [21/28] m68k/hp300: Convert HP9000/300 and HP9000/400 to genirq
>>>> á- [22/28] m68k/vme: Convert VME to genirq
>>>> á- [23/28] m68k/apollo: Convert Apollo to genirq
>>>> á- [24/28] m68k/sun3: Use the kstat_irqs_cpu() wrapper
>>>> á- [25/28] m68k/sun3: Convert Sun3/3x to genirq
>>>> á- [26/28] m68k/q40: Convert Q40/Q60 to genirq
>>>> á- [27/28] m68k/irq: Remove obsolete m68k irq framework
>>>> á- [28/28] m68k/irq: Remove obsolete support for user vector interrupt
>>>> fixups
>>>>
>>>> Overview:
>>>> á- [01] is a fix for the core genirq code,
>>>
>>> This went into v3.1-rc6.
>>>
>>>> á- [02-03] are fixes to avoid compile problems later in the conversion
>>>> á áprocess,
>>>
>>> The keyboard path went into the tty -next tree.
>>> The IDE one is still pending (I've just resent it).
>>
>> The IDE one got acked in the mean time.
>>
>>>> I will update my m68k-genirq branch as soon as master.kernel.org is
>>>> available
>>>> again.
>>>
>>> Updated, on top of m68k master (which is at v3.1-rc10 now).
>>>
>>> http://git.kernel.org/?p=linux/kernel/git/geert/linux-m68k.git;a=shortlog;h=refs/heads/m68k-genirq
>>>
>>> If noone objects, I'd like to add this to the m68k master and for-3.2
>>> branches.
>>
>> I added it to m68k master.
>>
>> As there were several merge conflicts with current -next
>> (arch/m68k/kernel/Makefile_mm
>> due to the mmu/nommu merge, and drivers/net/macsonic.c in [12/28] due
>> to the network
>> driver reshuffling dance), I did not add it to for-3.2 and for-next,
>> but to for-3.3.
>>
>> Depending on Stephen's return during or after the merge window, and
>> the merge timing
>> of the m68knommu and netdev trees, I may stil try to sneak it in 3.2,
>> though.
>
> I can ask Linus to pull the m68knommu tree early in the merge window,
> if that will help.
Thanks, that will help. Then I can rebase on top of that.
And I'll split "[12/28] m68k/irq: Remove obsolete IRQ_FLG_*
definitions and users",
so the net/scsi/tty parts can hit the repective trees separately.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 00/28 v6] m68k: Convert to genirq
From: Geert Uytterhoeven @ 2011-10-23 12:12 UTC (permalink / raw)
To: Greg Ungerer; +Cc: linux-m68k, Thomas Gleixner, linux-kernel, netdev
In-Reply-To: <4EA3FA86.7000905@snapgear.com>
On Sun, Oct 23, 2011 at 13:29, Greg Ungerer <gerg@snapgear.com> wrote:
> On 10/23/2011 07:49 PM, Geert Uytterhoeven wrote:
>> On Thu, Oct 20, 2011 at 14:18, Geert Uytterhoeven<geert@linux-m68k.org>
>> wrote:
>>> On Sun, Sep 11, 2011 at 13:59, Geert Uytterhoeven<geert@linux-m68k.org>
>>> wrote:
>>>> This patch series converts the m68k/mmu (nommu was converted before)
>>>> architecture to the generic hardirq framework.
>>>>
>>>> á- [01/28] genirq: Add missing "else" in irq_shutdown()
>>>> á- [02/28] ide-{cd,floppy,tape}: Do not include<linux/irq.>
>>>> á- [03/28] keyboard: Do not include<linux/irq.>
>>>> á- [04/28] m68k/irq: Rename irq_controller to irq_chip
>>>> á- [05/28] m68k/irq: Kill irq_node_t typedef, always use struct
>>>> irq_node
>>>> á- [06/28] m68k/irq: Rename irq_node to irq_data
>>>> á- [07/28] m68k/irq: Switch irq_chip methods to "struct irq_data *data"
>>>> á- [08/28] m68k/irq: Rename setup_irq() to m68k_setup_irq() and make it
>>>> static
>>>> á- [09/28] m68k/irq: Extract irq_set_chip()
>>>> á- [10/28] m68k/irq: Add m68k_setup_irq_controller()
>>>> á- [11/28] m68k/irq: Rename {,__}m68k_handle_int()
>>>> á- [12/28] m68k/irq: Remove obsolete IRQ_FLG_* definitions and users
>>>> á- [13/28] m68k/irq: Add genirq support
>>>> á- [14/28] m68k/atari: Convert Atari to genirq
>>>> á- [15/28] m68k/atari: Remove code and comments about different irq
>>>> types
>>>> á- [16/28] m68k/amiga: Refactor amiints.c
>>>> á- [17/28] m68k/amiga: Convert Amiga to genirq
>>>> á- [18/28] m68k/amiga: Optimize interrupts using chain handlers
>>>> á- [19/28] m68k/mac: Convert Mac to genirq
>>>> á- [20/28] m68k/mac: Optimize interrupts using chain handlers
>>>> á- [21/28] m68k/hp300: Convert HP9000/300 and HP9000/400 to genirq
>>>> á- [22/28] m68k/vme: Convert VME to genirq
>>>> á- [23/28] m68k/apollo: Convert Apollo to genirq
>>>> á- [24/28] m68k/sun3: Use the kstat_irqs_cpu() wrapper
>>>> á- [25/28] m68k/sun3: Convert Sun3/3x to genirq
>>>> á- [26/28] m68k/q40: Convert Q40/Q60 to genirq
>>>> á- [27/28] m68k/irq: Remove obsolete m68k irq framework
>>>> á- [28/28] m68k/irq: Remove obsolete support for user vector interrupt
>>>> fixups
>>>>
>>>> Overview:
>>>> á- [01] is a fix for the core genirq code,
>>>
>>> This went into v3.1-rc6.
>>>
>>>> á- [02-03] are fixes to avoid compile problems later in the conversion
>>>> á áprocess,
>>>
>>> The keyboard path went into the tty -next tree.
>>> The IDE one is still pending (I've just resent it).
>>
>> The IDE one got acked in the mean time.
>>
>>>> I will update my m68k-genirq branch as soon as master.kernel.org is
>>>> available
>>>> again.
>>>
>>> Updated, on top of m68k master (which is at v3.1-rc10 now).
>>>
>>> http://git.kernel.org/?p=linux/kernel/git/geert/linux-m68k.git;a=shortlog;h=refs/heads/m68k-genirq
>>>
>>> If noone objects, I'd like to add this to the m68k master and for-3.2
>>> branches.
>>
>> I added it to m68k master.
>>
>> As there were several merge conflicts with current -next
>> (arch/m68k/kernel/Makefile_mm
>> due to the mmu/nommu merge, and drivers/net/macsonic.c in [12/28] due
>> to the network
>> driver reshuffling dance), I did not add it to for-3.2 and for-next,
>> but to for-3.3.
>>
>> Depending on Stephen's return during or after the merge window, and
>> the merge timing
>> of the m68knommu and netdev trees, I may stil try to sneak it in 3.2,
>> though.
>
> I can ask Linus to pull the m68knommu tree early in the merge window,
> if that will help.
Thanks, that will help. Then I can rebase on top of that.
And I'll split "[12/28] m68k/irq: Remove obsolete IRQ_FLG_*
definitions and users",
so the net/scsi/tty parts can hit the repective trees separately.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 1/3] drm/i915: Ivybridge still has fences!
From: Daniel Vetter @ 2011-10-23 12:09 UTC (permalink / raw)
To: Chris Wilson, Keith Packard; +Cc: Daniel Vetter, intel-gfx, stable
In-Reply-To: <aefc95$1v3t51@orsmga001.jf.intel.com>
On Sun, Oct 23, 2011 at 12:23:14PM +0100, Chris Wilson wrote:
> Regardless of the outcome of Jesse's request for an if-ladder, the
> substance of the patches look sound.
>
> However, I remain unconvinced that there are 32 fence registers on IVB.
> Daniel's evidence is based upon the size of the register map (and not
> on the BSPEC explicitly stating a change to 32 ;-), but most tellingly
> the bitfields for fence-number in other registers have not been updated -
> so we can only safely allocated the first 16 anyway...
> (For instance, FBC_CTL).
Ok, I've rechecked bspec. The FBC_CTL fence number is indeed only 4 bits
wide, but on snb+ is must be written as 0. The cpu fence stuff for fbc
moved to DPFC_CONTROL_SA, which has room enough for 5 bits. Unfortunately
bspec is silent on whether that has actually grown from 4 bits for ivb. On
a future hw iteration I'm not really allowed to talk about it is all
correctly in place (i.e. bspec definitions for all 32 fence regs plus the
5 bit wide fence number in DPFC_CTL_SA).
So I think I'll drop this patch till things clear up.
Keith, can take a look at patches 1-2 and consider merging them for 3.2?
Yours, Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply
* Re: [22/27] VFS: Fix automount for negative autofs dentries
From: Ian Kent @ 2011-10-23 12:07 UTC (permalink / raw)
To: Greg KH
Cc: Greg KH, linux-kernel, stable, stable-review, torvalds, akpm,
alan, David Howells, Al Viro, Chuck Ebbert
In-Reply-To: <20111023114851.GA24676@kroah.com>
On Sun, 2011-10-23 at 13:48 +0200, Greg KH wrote:
> On Sun, Oct 23, 2011 at 07:41:18PM +0800, Ian Kent wrote:
> > On Sun, 2011-10-23 at 08:24 +0200, Greg KH wrote:
> > > 3.0-stable review patch. If anyone has any objections, please let us know.
> >
> > Yes, as others point out, either the patch needs to be correctly
> > backported or the dependent patches need to be pulled in.
> >
> > I can do either of these, what would you prefer?
>
> I'd prefer to take the dependant patches, as that would make things sync
> up with what is in Linus's tree, I just wanted to get Miklos's and
> David's acks that this is the way to go before I did it.
Sure, just let me know if you want me to do any of the leg work (or
keyboard work in this case, ;)).
Ian
^ permalink raw reply
* Re: [PATCH v7 16/16] ARM: LPAE: Add the Kconfig entries
From: Russell King - ARM Linux @ 2011-10-23 12:00 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-kernel, linux-arm-kernel
In-Reply-To: <1312988619-16804-17-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:39PM +0100, Catalin Marinas wrote:
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 88633fe..2df5504 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -629,6 +629,19 @@ config IO_36
>
> comment "Processor Features"
>
> +config ARM_LPAE
> + bool "Support for the Large Physical Address Extension"
> + depends on MMU && CPU_V7
> + help
> + Say Y if you have an ARMv7 processor supporting the LPAE page table
> + format and you would like to access memory beyond the 4GB limit.
This help text is entirely insufficient. It doesn't tell people what the
implications are for enabling this option on CPUs without LPAE support.
(It won't boot.) It doesn't suggest what people should select when they're
unsure what setting to use.
^ permalink raw reply
* Re: [PATCH v7 15/16] ARM: LPAE: add support for ATAG_MEM64
From: Russell King - ARM Linux @ 2011-10-23 11:59 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-kernel, linux-arm-kernel, Will Deacon
In-Reply-To: <1312988619-16804-16-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:38PM +0100, Catalin Marinas wrote:
> From: Will Deacon <will.deacon@arm.com>
>
> LPAE provides support for memory banks with physical addresses of up
> to 40 bits.
>
> This patch adds a new atag, ATAG_MEM64, so that the Kernel can be
> informed about memory that exists above the 4GB boundary.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
> arch/arm/include/asm/setup.h | 8 ++++++++
> arch/arm/kernel/setup.c | 10 ++++++++++
> 2 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
> index 915696d..a3ca303 100644
> --- a/arch/arm/include/asm/setup.h
> +++ b/arch/arm/include/asm/setup.h
> @@ -43,6 +43,13 @@ struct tag_mem32 {
> __u32 start; /* physical start address */
> };
>
> +#define ATAG_MEM64 0x54420002
> +
> +struct tag_mem64 {
> + __u64 size;
> + __u64 start; /* physical start address */
> +};
> +
> /* VGA text type displays */
> #define ATAG_VIDEOTEXT 0x54410003
>
> @@ -148,6 +155,7 @@ struct tag {
> union {
> struct tag_core core;
> struct tag_mem32 mem;
> + struct tag_mem64 mem64;
> struct tag_videotext videotext;
> struct tag_ramdisk ramdisk;
> struct tag_initrd initrd;
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 70bca64..a126558 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -608,6 +608,16 @@ static int __init parse_tag_mem32(const struct tag *tag)
>
> __tagtable(ATAG_MEM, parse_tag_mem32);
>
> +#ifdef CONFIG_PHYS_ADDR_T_64BIT
> +static int __init parse_tag_mem64(const struct tag *tag)
> +{
> + /* We only use 32-bits for the size. */
> + return arm_add_memory(tag->u.mem64.start, (unsigned long)tag->u.mem64.size);
> +}
> +
> +__tagtable(ATAG_MEM64, parse_tag_mem64);
> +#endif /* CONFIG_PHYS_ADDR_T_64BIT */
> +
We should allow this even on 32-bit only kernels - but avoiding adding
>32-bit memory to the system in that case.
^ permalink raw reply
* [PATCH v7 16/16] ARM: LPAE: Add the Kconfig entries
From: Russell King - ARM Linux @ 2011-10-23 12:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1312988619-16804-17-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:39PM +0100, Catalin Marinas wrote:
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 88633fe..2df5504 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -629,6 +629,19 @@ config IO_36
>
> comment "Processor Features"
>
> +config ARM_LPAE
> + bool "Support for the Large Physical Address Extension"
> + depends on MMU && CPU_V7
> + help
> + Say Y if you have an ARMv7 processor supporting the LPAE page table
> + format and you would like to access memory beyond the 4GB limit.
This help text is entirely insufficient. It doesn't tell people what the
implications are for enabling this option on CPUs without LPAE support.
(It won't boot.) It doesn't suggest what people should select when they're
unsure what setting to use.
^ permalink raw reply
* [PATCH v7 15/16] ARM: LPAE: add support for ATAG_MEM64
From: Russell King - ARM Linux @ 2011-10-23 11:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1312988619-16804-16-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:38PM +0100, Catalin Marinas wrote:
> From: Will Deacon <will.deacon@arm.com>
>
> LPAE provides support for memory banks with physical addresses of up
> to 40 bits.
>
> This patch adds a new atag, ATAG_MEM64, so that the Kernel can be
> informed about memory that exists above the 4GB boundary.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
> arch/arm/include/asm/setup.h | 8 ++++++++
> arch/arm/kernel/setup.c | 10 ++++++++++
> 2 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
> index 915696d..a3ca303 100644
> --- a/arch/arm/include/asm/setup.h
> +++ b/arch/arm/include/asm/setup.h
> @@ -43,6 +43,13 @@ struct tag_mem32 {
> __u32 start; /* physical start address */
> };
>
> +#define ATAG_MEM64 0x54420002
> +
> +struct tag_mem64 {
> + __u64 size;
> + __u64 start; /* physical start address */
> +};
> +
> /* VGA text type displays */
> #define ATAG_VIDEOTEXT 0x54410003
>
> @@ -148,6 +155,7 @@ struct tag {
> union {
> struct tag_core core;
> struct tag_mem32 mem;
> + struct tag_mem64 mem64;
> struct tag_videotext videotext;
> struct tag_ramdisk ramdisk;
> struct tag_initrd initrd;
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 70bca64..a126558 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -608,6 +608,16 @@ static int __init parse_tag_mem32(const struct tag *tag)
>
> __tagtable(ATAG_MEM, parse_tag_mem32);
>
> +#ifdef CONFIG_PHYS_ADDR_T_64BIT
> +static int __init parse_tag_mem64(const struct tag *tag)
> +{
> + /* We only use 32-bits for the size. */
> + return arm_add_memory(tag->u.mem64.start, (unsigned long)tag->u.mem64.size);
> +}
> +
> +__tagtable(ATAG_MEM64, parse_tag_mem64);
> +#endif /* CONFIG_PHYS_ADDR_T_64BIT */
> +
We should allow this even on 32-bit only kernels - but avoiding adding
>32-bit memory to the system in that case.
^ permalink raw reply
* Re: [PATCH v7 13/16] ARM: LPAE: Add identity mapping support for the 3-level page table format
From: Russell King - ARM Linux @ 2011-10-23 11:59 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-kernel, linux-arm-kernel
In-Reply-To: <1312988619-16804-14-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:36PM +0100, Catalin Marinas wrote:
> The pmd_addr_end() definition has been removed and the
> generic one used instead.
NAK - it helps to read code comments.
commit c0ba10b512eb2e2a3888b6e6cc0e089f5e7a191b
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sun Nov 21 14:42:47 2010 +0000
ARM: improve compiler's ability to optimize page tables
Allow the compiler to better optimize the page table walking code
by avoiding over-complex pmd_addr_end() calculations. These
calculations prevent the compiler spotting that we'll never iterate
over the PMD table, causing it to create double nested loops where
a single loop will do.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index b155414..53d1d5d 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -374,6 +374,9 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd)))
+/* we don't need complex calculations here as the pmd is folded into the pgd */
+#define pmd_addr_end(addr,end) (end)
+
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
^ permalink raw reply related
* [PATCH v7 13/16] ARM: LPAE: Add identity mapping support for the 3-level page table format
From: Russell King - ARM Linux @ 2011-10-23 11:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1312988619-16804-14-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:36PM +0100, Catalin Marinas wrote:
> The pmd_addr_end() definition has been removed and the
> generic one used instead.
NAK - it helps to read code comments.
commit c0ba10b512eb2e2a3888b6e6cc0e089f5e7a191b
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sun Nov 21 14:42:47 2010 +0000
ARM: improve compiler's ability to optimize page tables
Allow the compiler to better optimize the page table walking code
by avoiding over-complex pmd_addr_end() calculations. These
calculations prevent the compiler spotting that we'll never iterate
over the PMD table, causing it to create double nested loops where
a single loop will do.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index b155414..53d1d5d 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -374,6 +374,9 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd)))
+/* we don't need complex calculations here as the pmd is folded into the pgd */
+#define pmd_addr_end(addr,end) (end)
+
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
^ permalink raw reply related
* Re: [22/27] VFS: Fix automount for negative autofs dentries
From: Ian Kent @ 2011-10-23 11:59 UTC (permalink / raw)
To: Linus Torvalds
Cc: Greg KH, linux-kernel, stable, stable-review, akpm, alan,
David Howells, Al Viro, Chuck Ebbert, Miklos Szeredi,
Trond Myklebust
In-Reply-To: <CA+55aFxkHr75LZU0udv=A+Bg52fMMOEfp47TTxHGbgf51UouRg@mail.gmail.com>
On Sun, 2011-10-23 at 10:35 +0300, Linus Torvalds wrote:
> This one is debatable.
>
> I think it also wants
Mmm .. I find myself caught by essentially the same mistake twice in one
day, ;)
>
> - commit 0ec26fd0698285b31248e34bf1abb022c00f23d6 (with
> LOOKUP_PARENT->LOOKUP_CONTINUE too)
Oh right "vfs: automount should ignore LOOKUP_FOLLOW", yes.
>
> - commit d94c177beeb4469cd4f6e83354ab0223353e98ed (to get the few
> other cases right too)
And probably 815d405ceff0d6964683f033e18b9b23a88fba87 as well as
b6c8069d3577481390b3f24a8434ad72a3235594. But I'd need to check that
would be OK.
That should bring 3.0 inline with 3.1.
>
> anything else I missed?
>
> Linus
>
> On Sun, Oct 23, 2011 at 9:24 AM, Greg KH <gregkh@suse.de> wrote:
> > 3.0-stable review patch. If anyone has any objections, please let us know.
> >
> > ------------------
> >
> > From: David Howells <dhowells@redhat.com>
> >
> > commit 5a30d8a2b8ddd5102c440c7e5a7c8e1fd729c818 upstream.
> > [ backport for 3.0.x: LOOKUP_PARENT => LOOKUP_CONTINUE by Chuck Ebbert
> > <cebbert@redhat.com> ]
> >
> > Autofs may set the DCACHE_NEED_AUTOMOUNT flag on negative dentries. These
> > need attention from the automounter daemon regardless of the LOOKUP_FOLLOW flag.
> >
> > Signed-off-by: David Howells <dhowells@redhat.com>
> > Acked-by: Ian Kent <raven@themaw.net>
> > Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
> > Cc: Chuck Ebbert <cebbert@redhat.com>
> > Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
> >
> > ---
> > fs/namei.c | 24 +++++++++++++++---------
> > 1 file changed, 15 insertions(+), 9 deletions(-)
> >
> > --- a/fs/namei.c
> > +++ b/fs/namei.c
> > @@ -779,19 +779,25 @@ static int follow_automount(struct path
> > if ((flags & LOOKUP_NO_AUTOMOUNT) && !(flags & LOOKUP_CONTINUE))
> > return -EISDIR; /* we actually want to stop here */
> >
> > - /* We want to mount if someone is trying to open/create a file of any
> > - * type under the mountpoint, wants to traverse through the mountpoint
> > - * or wants to open the mounted directory.
> > - *
> > + /*
> > * We don't want to mount if someone's just doing a stat and they've
> > * set AT_SYMLINK_NOFOLLOW - unless they're stat'ing a directory and
> > * appended a '/' to the name.
> > */
> > - if (!(flags & LOOKUP_FOLLOW) &&
> > - !(flags & (LOOKUP_CONTINUE | LOOKUP_DIRECTORY |
> > - LOOKUP_OPEN | LOOKUP_CREATE)))
> > - return -EISDIR;
> > -
> > + if (!(flags & LOOKUP_FOLLOW)) {
> > + /* We do, however, want to mount if someone wants to open or
> > + * create a file of any type under the mountpoint, wants to
> > + * traverse through the mountpoint or wants to open the mounted
> > + * directory.
> > + * Also, autofs may mark negative dentries as being automount
> > + * points. These will need the attentions of the daemon to
> > + * instantiate them before they can be used.
> > + */
> > + if (!(flags & (LOOKUP_PARENT | LOOKUP_DIRECTORY |
> > + LOOKUP_OPEN | LOOKUP_CREATE)) &&
> > + path->dentry->d_inode)
> > + return -EISDIR;
> > + }
> > current->total_link_count++;
> > if (current->total_link_count >= 40)
> > return -ELOOP;
> >
> >
> >
^ permalink raw reply
* Re: [PATCH v7 11/16] ARM: LPAE: Add fault handling support
From: Russell King - ARM Linux @ 2011-10-23 11:57 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-kernel, linux-arm-kernel
In-Reply-To: <1312988619-16804-12-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:34PM +0100, Catalin Marinas wrote:
> diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
> index be7c638..f0bf61a 100644
> --- a/arch/arm/mm/alignment.c
> +++ b/arch/arm/mm/alignment.c
> @@ -909,6 +909,12 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
> return 0;
> }
>
> +#ifdef CONFIG_ARM_LPAE
> +#define ALIGNMENT_FAULT 33
> +#else
> +#define ALIGNMENT_FAULT 1
> +#endif
Probably makes sense to move this into a header, along with the other
fault codes, other FSR bits and fsr_fs().
> +
> /*
> * This needs to be done after sysctl_init, otherwise sys/ will be
> * overwritten. Actually, this shouldn't be in sys/ at all since
> @@ -942,7 +948,7 @@ static int __init alignment_init(void)
> ai_usermode = UM_FIXUP;
> }
>
> - hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
> + hook_fault_code(ALIGNMENT_FAULT, do_alignment, SIGBUS, BUS_ADRALN,
> "alignment exception");
>
> /*
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index 3b5ea68..91d1768 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -33,10 +33,15 @@
> #define FSR_WRITE (1 << 11)
> #define FSR_FS4 (1 << 10)
> #define FSR_FS3_0 (15)
> +#define FSR_FS5_0 (0x3f)
>
> static inline int fsr_fs(unsigned int fsr)
> {
> +#ifdef CONFIG_ARM_LPAE
> + return fsr & FSR_FS5_0;
> +#else
> return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6;
> +#endif
> }
>
> #ifdef CONFIG_MMU
> @@ -122,8 +127,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
>
> pte = pte_offset_map(pmd, addr);
> printk(", *pte=%08llx", (long long)pte_val(*pte));
> +#ifndef CONFIG_ARM_LPAE
> printk(", *ppte=%08llx",
> (long long)pte_val(pte[PTE_HWTABLE_PTRS]));
> +#endif
> pte_unmap(pte);
> } while(0);
>
> @@ -440,6 +447,12 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
> pmd = pmd_offset(pud, addr);
> pmd_k = pmd_offset(pud_k, addr);
>
> +#ifdef CONFIG_ARM_LPAE
> + /*
> + * Only one hardware entry per PMD with LPAE.
> + */
> + index = 0;
> +#else
> /*
> * On ARM one Linux PGD entry contains two hardware entries (see page
> * tables layout in pgtable.h). We normally guarantee that we always
> @@ -449,6 +462,7 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
> * for the first of pair.
> */
> index = (addr >> SECTION_SHIFT) & 1;
> +#endif
> if (pmd_none(pmd_k[index]))
> goto bad_area;
>
> @@ -494,6 +508,72 @@ static struct fsr_info {
> int code;
> const char *name;
> } fsr_info[] = {
> +#ifdef CONFIG_ARM_LPAE
> + { do_bad, SIGBUS, 0, "unknown 0" },
> + { do_bad, SIGBUS, 0, "unknown 1" },
> + { do_bad, SIGBUS, 0, "unknown 2" },
> + { do_bad, SIGBUS, 0, "unknown 3" },
> + { do_bad, SIGBUS, 0, "reserved translation fault" },
> + { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
> + { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
> + { do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
> + { do_bad, SIGBUS, 0, "reserved access flag fault" },
> + { do_bad, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
> + { do_bad, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
> + { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" },
> + { do_bad, SIGBUS, 0, "reserved permission fault" },
> + { do_bad, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
> + { do_sect_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
> + { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
> + { do_bad, SIGBUS, 0, "synchronous external abort" },
> + { do_bad, SIGBUS, 0, "asynchronous external abort" },
> + { do_bad, SIGBUS, 0, "unknown 18" },
> + { do_bad, SIGBUS, 0, "unknown 19" },
> + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
> + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
> + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
> + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
> + { do_bad, SIGBUS, 0, "synchronous parity error" },
> + { do_bad, SIGBUS, 0, "asynchronous parity error" },
> + { do_bad, SIGBUS, 0, "unknown 26" },
> + { do_bad, SIGBUS, 0, "unknown 27" },
> + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
> + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
> + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
> + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
> + { do_bad, SIGBUS, 0, "unknown 32" },
> + { do_bad, SIGBUS, BUS_ADRALN, "alignment fault" },
> + { do_bad, SIGBUS, 0, "debug event" },
> + { do_bad, SIGBUS, 0, "unknown 35" },
> + { do_bad, SIGBUS, 0, "unknown 36" },
> + { do_bad, SIGBUS, 0, "unknown 37" },
> + { do_bad, SIGBUS, 0, "unknown 38" },
> + { do_bad, SIGBUS, 0, "unknown 39" },
> + { do_bad, SIGBUS, 0, "unknown 40" },
> + { do_bad, SIGBUS, 0, "unknown 41" },
> + { do_bad, SIGBUS, 0, "unknown 42" },
> + { do_bad, SIGBUS, 0, "unknown 43" },
> + { do_bad, SIGBUS, 0, "unknown 44" },
> + { do_bad, SIGBUS, 0, "unknown 45" },
> + { do_bad, SIGBUS, 0, "unknown 46" },
> + { do_bad, SIGBUS, 0, "unknown 47" },
> + { do_bad, SIGBUS, 0, "unknown 48" },
> + { do_bad, SIGBUS, 0, "unknown 49" },
> + { do_bad, SIGBUS, 0, "unknown 50" },
> + { do_bad, SIGBUS, 0, "unknown 51" },
> + { do_bad, SIGBUS, 0, "implementation fault (lockdown abort)" },
> + { do_bad, SIGBUS, 0, "unknown 53" },
> + { do_bad, SIGBUS, 0, "unknown 54" },
> + { do_bad, SIGBUS, 0, "unknown 55" },
> + { do_bad, SIGBUS, 0, "unknown 56" },
> + { do_bad, SIGBUS, 0, "unknown 57" },
> + { do_bad, SIGBUS, 0, "implementation fault (coprocessor abort)" },
> + { do_bad, SIGBUS, 0, "unknown 59" },
> + { do_bad, SIGBUS, 0, "unknown 60" },
> + { do_bad, SIGBUS, 0, "unknown 61" },
> + { do_bad, SIGBUS, 0, "unknown 62" },
> + { do_bad, SIGBUS, 0, "unknown 63" },
> +#else /* !CONFIG_ARM_LPAE */
> /*
> * The following are the standard ARMv3 and ARMv4 aborts. ARMv5
> * defines these to be "precise" aborts.
> @@ -535,6 +615,7 @@ static struct fsr_info {
> { do_bad, SIGBUS, 0, "unknown 29" },
> { do_bad, SIGBUS, 0, "unknown 30" },
> { do_bad, SIGBUS, 0, "unknown 31" }
> +#endif /* CONFIG_ARM_LPAE */
Can't we do better than this?
> };
>
> void __init
> @@ -573,6 +654,9 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
> }
>
>
> +#ifdef CONFIG_ARM_LPAE
> +#define ifsr_info fsr_info
> +#else /* !CONFIG_ARM_LPAE */
> static struct fsr_info ifsr_info[] = {
> { do_bad, SIGBUS, 0, "unknown 0" },
> { do_bad, SIGBUS, 0, "unknown 1" },
> @@ -607,6 +691,7 @@ static struct fsr_info ifsr_info[] = {
> { do_bad, SIGBUS, 0, "unknown 30" },
> { do_bad, SIGBUS, 0, "unknown 31" },
> };
> +#endif /* CONFIG_ARM_LPAE */
>
> void __init
> hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
> @@ -642,6 +727,7 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
>
> static int __init exceptions_init(void)
> {
> +#ifndef CONFIG_ARM_LPAE
> if (cpu_architecture() >= CPU_ARCH_ARMv6) {
> hook_fault_code(4, do_translation_fault, SIGSEGV, SEGV_MAPERR,
> "I-cache maintenance fault");
> @@ -657,6 +743,7 @@ static int __init exceptions_init(void)
> hook_fault_code(6, do_bad, SIGSEGV, SEGV_MAPERR,
> "section access flag fault");
> }
> +#endif
>
> return 0;
> }
Do we even need exceptions_init() at all for LPAE? If not, can't we
avoid the whole of this including the useless init call.
^ permalink raw reply
* [PATCH v7 11/16] ARM: LPAE: Add fault handling support
From: Russell King - ARM Linux @ 2011-10-23 11:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1312988619-16804-12-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:34PM +0100, Catalin Marinas wrote:
> diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
> index be7c638..f0bf61a 100644
> --- a/arch/arm/mm/alignment.c
> +++ b/arch/arm/mm/alignment.c
> @@ -909,6 +909,12 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
> return 0;
> }
>
> +#ifdef CONFIG_ARM_LPAE
> +#define ALIGNMENT_FAULT 33
> +#else
> +#define ALIGNMENT_FAULT 1
> +#endif
Probably makes sense to move this into a header, along with the other
fault codes, other FSR bits and fsr_fs().
> +
> /*
> * This needs to be done after sysctl_init, otherwise sys/ will be
> * overwritten. Actually, this shouldn't be in sys/ at all since
> @@ -942,7 +948,7 @@ static int __init alignment_init(void)
> ai_usermode = UM_FIXUP;
> }
>
> - hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
> + hook_fault_code(ALIGNMENT_FAULT, do_alignment, SIGBUS, BUS_ADRALN,
> "alignment exception");
>
> /*
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index 3b5ea68..91d1768 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -33,10 +33,15 @@
> #define FSR_WRITE (1 << 11)
> #define FSR_FS4 (1 << 10)
> #define FSR_FS3_0 (15)
> +#define FSR_FS5_0 (0x3f)
>
> static inline int fsr_fs(unsigned int fsr)
> {
> +#ifdef CONFIG_ARM_LPAE
> + return fsr & FSR_FS5_0;
> +#else
> return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6;
> +#endif
> }
>
> #ifdef CONFIG_MMU
> @@ -122,8 +127,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
>
> pte = pte_offset_map(pmd, addr);
> printk(", *pte=%08llx", (long long)pte_val(*pte));
> +#ifndef CONFIG_ARM_LPAE
> printk(", *ppte=%08llx",
> (long long)pte_val(pte[PTE_HWTABLE_PTRS]));
> +#endif
> pte_unmap(pte);
> } while(0);
>
> @@ -440,6 +447,12 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
> pmd = pmd_offset(pud, addr);
> pmd_k = pmd_offset(pud_k, addr);
>
> +#ifdef CONFIG_ARM_LPAE
> + /*
> + * Only one hardware entry per PMD with LPAE.
> + */
> + index = 0;
> +#else
> /*
> * On ARM one Linux PGD entry contains two hardware entries (see page
> * tables layout in pgtable.h). We normally guarantee that we always
> @@ -449,6 +462,7 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
> * for the first of pair.
> */
> index = (addr >> SECTION_SHIFT) & 1;
> +#endif
> if (pmd_none(pmd_k[index]))
> goto bad_area;
>
> @@ -494,6 +508,72 @@ static struct fsr_info {
> int code;
> const char *name;
> } fsr_info[] = {
> +#ifdef CONFIG_ARM_LPAE
> + { do_bad, SIGBUS, 0, "unknown 0" },
> + { do_bad, SIGBUS, 0, "unknown 1" },
> + { do_bad, SIGBUS, 0, "unknown 2" },
> + { do_bad, SIGBUS, 0, "unknown 3" },
> + { do_bad, SIGBUS, 0, "reserved translation fault" },
> + { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
> + { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
> + { do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
> + { do_bad, SIGBUS, 0, "reserved access flag fault" },
> + { do_bad, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
> + { do_bad, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
> + { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" },
> + { do_bad, SIGBUS, 0, "reserved permission fault" },
> + { do_bad, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
> + { do_sect_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
> + { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
> + { do_bad, SIGBUS, 0, "synchronous external abort" },
> + { do_bad, SIGBUS, 0, "asynchronous external abort" },
> + { do_bad, SIGBUS, 0, "unknown 18" },
> + { do_bad, SIGBUS, 0, "unknown 19" },
> + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
> + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
> + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
> + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
> + { do_bad, SIGBUS, 0, "synchronous parity error" },
> + { do_bad, SIGBUS, 0, "asynchronous parity error" },
> + { do_bad, SIGBUS, 0, "unknown 26" },
> + { do_bad, SIGBUS, 0, "unknown 27" },
> + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
> + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
> + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
> + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
> + { do_bad, SIGBUS, 0, "unknown 32" },
> + { do_bad, SIGBUS, BUS_ADRALN, "alignment fault" },
> + { do_bad, SIGBUS, 0, "debug event" },
> + { do_bad, SIGBUS, 0, "unknown 35" },
> + { do_bad, SIGBUS, 0, "unknown 36" },
> + { do_bad, SIGBUS, 0, "unknown 37" },
> + { do_bad, SIGBUS, 0, "unknown 38" },
> + { do_bad, SIGBUS, 0, "unknown 39" },
> + { do_bad, SIGBUS, 0, "unknown 40" },
> + { do_bad, SIGBUS, 0, "unknown 41" },
> + { do_bad, SIGBUS, 0, "unknown 42" },
> + { do_bad, SIGBUS, 0, "unknown 43" },
> + { do_bad, SIGBUS, 0, "unknown 44" },
> + { do_bad, SIGBUS, 0, "unknown 45" },
> + { do_bad, SIGBUS, 0, "unknown 46" },
> + { do_bad, SIGBUS, 0, "unknown 47" },
> + { do_bad, SIGBUS, 0, "unknown 48" },
> + { do_bad, SIGBUS, 0, "unknown 49" },
> + { do_bad, SIGBUS, 0, "unknown 50" },
> + { do_bad, SIGBUS, 0, "unknown 51" },
> + { do_bad, SIGBUS, 0, "implementation fault (lockdown abort)" },
> + { do_bad, SIGBUS, 0, "unknown 53" },
> + { do_bad, SIGBUS, 0, "unknown 54" },
> + { do_bad, SIGBUS, 0, "unknown 55" },
> + { do_bad, SIGBUS, 0, "unknown 56" },
> + { do_bad, SIGBUS, 0, "unknown 57" },
> + { do_bad, SIGBUS, 0, "implementation fault (coprocessor abort)" },
> + { do_bad, SIGBUS, 0, "unknown 59" },
> + { do_bad, SIGBUS, 0, "unknown 60" },
> + { do_bad, SIGBUS, 0, "unknown 61" },
> + { do_bad, SIGBUS, 0, "unknown 62" },
> + { do_bad, SIGBUS, 0, "unknown 63" },
> +#else /* !CONFIG_ARM_LPAE */
> /*
> * The following are the standard ARMv3 and ARMv4 aborts. ARMv5
> * defines these to be "precise" aborts.
> @@ -535,6 +615,7 @@ static struct fsr_info {
> { do_bad, SIGBUS, 0, "unknown 29" },
> { do_bad, SIGBUS, 0, "unknown 30" },
> { do_bad, SIGBUS, 0, "unknown 31" }
> +#endif /* CONFIG_ARM_LPAE */
Can't we do better than this?
> };
>
> void __init
> @@ -573,6 +654,9 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
> }
>
>
> +#ifdef CONFIG_ARM_LPAE
> +#define ifsr_info fsr_info
> +#else /* !CONFIG_ARM_LPAE */
> static struct fsr_info ifsr_info[] = {
> { do_bad, SIGBUS, 0, "unknown 0" },
> { do_bad, SIGBUS, 0, "unknown 1" },
> @@ -607,6 +691,7 @@ static struct fsr_info ifsr_info[] = {
> { do_bad, SIGBUS, 0, "unknown 30" },
> { do_bad, SIGBUS, 0, "unknown 31" },
> };
> +#endif /* CONFIG_ARM_LPAE */
>
> void __init
> hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
> @@ -642,6 +727,7 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
>
> static int __init exceptions_init(void)
> {
> +#ifndef CONFIG_ARM_LPAE
> if (cpu_architecture() >= CPU_ARCH_ARMv6) {
> hook_fault_code(4, do_translation_fault, SIGSEGV, SEGV_MAPERR,
> "I-cache maintenance fault");
> @@ -657,6 +743,7 @@ static int __init exceptions_init(void)
> hook_fault_code(6, do_bad, SIGSEGV, SEGV_MAPERR,
> "section access flag fault");
> }
> +#endif
>
> return 0;
> }
Do we even need exceptions_init() at all for LPAE? If not, can't we
avoid the whole of this including the useless init call.
^ permalink raw reply
* Re: [PATCH v7 08/16] ARM: LPAE: Page table maintenance for the 3-level format
From: Russell King - ARM Linux @ 2011-10-23 11:56 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-kernel, linux-arm-kernel
In-Reply-To: <1312988619-16804-9-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:31PM +0100, Catalin Marinas wrote:
> This patch modifies the pgd/pmd/pte manipulation functions to support
> the 3-level page table format. Since there is no need for an 'ext'
> argument to cpu_set_pte_ext(), this patch conditionally defines a
> different prototype for this function when CONFIG_ARM_LPAE.
This has a really large number of ifdefs. You've split the 2 and 3
level page table stuff into two different header files already,
conditionalized on CONFIG_ARM_LPAE, yet we still end up with lots of
junk in the common header file conditionalized on that symbol. Can't
we find a way to restructure pgtable.h to sort this out more cleanly?
Do we really need to change the set_pte_ext() prototype as well - do
we _really_ need ifdefs around its declaration, and every usage of it
as well? Can't we just leave the 3rd argument as zero?
^ permalink raw reply
* [PATCH v7 08/16] ARM: LPAE: Page table maintenance for the 3-level format
From: Russell King - ARM Linux @ 2011-10-23 11:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1312988619-16804-9-git-send-email-catalin.marinas@arm.com>
On Wed, Aug 10, 2011 at 04:03:31PM +0100, Catalin Marinas wrote:
> This patch modifies the pgd/pmd/pte manipulation functions to support
> the 3-level page table format. Since there is no need for an 'ext'
> argument to cpu_set_pte_ext(), this patch conditionally defines a
> different prototype for this function when CONFIG_ARM_LPAE.
This has a really large number of ifdefs. You've split the 2 and 3
level page table stuff into two different header files already,
conditionalized on CONFIG_ARM_LPAE, yet we still end up with lots of
junk in the common header file conditionalized on that symbol. Can't
we find a way to restructure pgtable.h to sort this out more cleanly?
Do we really need to change the set_pte_ext() prototype as well - do
we _really_ need ifdefs around its declaration, and every usage of it
as well? Can't we just leave the 3rd argument as zero?
^ permalink raw reply
* Re: [PATCH 2/3] mfd: Add s5m series irq support
From: Mark Brown @ 2011-10-23 11:56 UTC (permalink / raw)
To: Sangbeom Kim; +Cc: 'Samuel Ortiz', linux-kernel
In-Reply-To: <009801cc9171$c4ea1970$4ebe4c50$@com>
On Sun, Oct 23, 2011 at 07:51:50PM +0900, Sangbeom Kim wrote:
> On Sun, Oct 23, 2011 at 05:43 PM , Mark Brown wrote:
> > Actually, one of the things I want to do in the 3.3 timeframe is to
> > factor out this code from my drivers into a regmap based irq_chip since
> > it seems a lot of people are "drawing inspiration" from it. This
> > shouldn't be any form of blocker for merging this driver though.
> I hope that this driver will be base code for regmap based irq driver
> I want discuss more detail in Prague.
Like I say, the code does look rather familiar to me :P
^ permalink raw reply
* Re: [PATCH 1/3] mfd: Add S5M core driver
From: Mark Brown @ 2011-10-23 11:55 UTC (permalink / raw)
To: Sangbeom Kim; +Cc: 'Samuel Ortiz', linux-kernel
In-Reply-To: <009701cc9170$0f2e9ee0$2d8bdca0$@com>
On Sun, Oct 23, 2011 at 07:39:36PM +0900, Sangbeom Kim wrote:
> On Sun, Oct 23, 2011 at 05:37 PM +0900, Mark Brown wrote:
> > > +EXPORT_SYMBOL(s5m_bulk_read);
> > All this stuff should be _GPL as the regmap core is _GPL - you shouldn't
> > wrap a _GPL function with a non-GPL one.
> You mean that EXPORT_SYMBOL should be replace with EXPORT_SYMBOL_GPL?
Yes.
> > > +static struct mfd_cell s5m87xx_devs[] = {
> > > + {
> > > + .name = "s5m8763-pmic",
> > > + }, {
> > > + .name = "s5m8767-pmic",
> > > + }, {
> > It looks a bit odd to have both simultaneously but I guess this will
> > become more obvious later on? I guess what I'd expect is one of these
> > arrays per device variant.
> My intention of this mfd driver is supporting all samsung mfd.
> It is desirable that a core driver handle various driver to prevent produce
> similar code.
Yes, this is very similar to what the wm831x driver does to handle all
the different chips we've got with the same register interface.
> So, If I want to implement like above concept, What kind of approach can be
> advised?
What wm831x does is register a different set of devices depending on the
device that gets registered - the per-device stuff is mostly just a set
of tables of devices to register.
> > > + s5m87xx->dev = &i2c->dev;
> > > + s5m87xx->i2c = i2c;
> > > + s5m87xx->irq = i2c->irq;
> > Is SPI supported?
> SPI isn't supported by Samsung mfd
In that case it might be as well to just get things like the IRQ from
the i2c client rather than keeping a copy of the variable.
^ permalink raw reply
* [lm-sensors] sensors and fan control not working on w83627dhg
From: Miguel Figueiredo @ 2011-10-23 11:54 UTC (permalink / raw)
To: lm-sensors
SGkgYWxsLAoKc2Vuc29ycyBhbmQgZmFuIGNvbnRyb2xsaW5nIGlzIG5vdCB3b3JraW5nIHByb3Bl
cmx5IG9uIGEgVHlhbiBTNjYzMSAKbW90aGVyYm9hcmQsIHdoaWNoIHRoZWlyIHN1cHBvcnQgZG9u
J3QgaGVscC4KVGhlIGZhbnMgYXJlIGFsd2F5cyBtYWtpbmcgYSB2ZXJ5ICpsb3VkKiBub2lzZS4K
VGhlIHN5c3RlbSBoYXMgNSBmYW5zIHBsdXMgZmFuKHMpIG9uIHRoZSBwb3dlciBzdXBwbHkuCgpC
ZWxsb3cgaSBhbSBhdHRhY2hpbmcgaW5mbyBvbiB0aGUgc3lzdGVtIGFuZCBhIHBob3RvIG9mIHRo
ZSBzZW5zb3JzIGNoaXAuCgpJZiBhbnlvbmUgaGF2ZSBhbnkgdGlwIG9uIGhvdyB0byBwcm9jZWVk
IHRvIG1ha2Ugc2Vuc29ycyB3b3JrIChhbmQgcmVkdWNlIHRoZSAKZmFuIG5vaXNlKSB3aWxsIGJl
IHZlcnkgYXBwcmVjaWF0ZWQuCgpQbGVhc2UgQ0MgbWUgYXMgaSdtIG5vdCBzdWJzY3JpYmVkLgoK
SW5mbyBvbiBzeXN0ZW06Cj09PT09PT09PT0KCkltYWdlIG9mIHc4MzYyN2RoZyBvbiBtb3RoZXJi
b2FyZDogaHR0cDovL2ltZ3VyLmNvbS9LTVUxRwoKTW90aGVyYm9hcmQ6IFR5YW4gUzY2MzEKCkxt
X3NlbnNvcnMgYW5kIGtlcm5lbCB2ZXJzaW9uOiBsbS1zZW5zb3JzIDMuMy4xLTEgKGRlYmlhbiks
IGtlcm5lbDozLjEuMC1yYzEwIAooZ2l0IHVwc3RyZWFtKQoKT3V0cHV0IG9mIHNlbnNvcnM6Cnc4
Mzc5My1pMmMtMC0yZgpBZGFwdGVyOiBTTUJ1cyBJODAxIGFkYXB0ZXIgYXQgMDQwMApWY29yZUE6
ICAgICAgICsxLjEzIFYgIChtaW4gPSAgKzAuMDAgViwgbWF4ID0gICsyLjA1IFYpClZjb3JlQjog
ICAgICAgKzAuMjEgViAgKG1pbiA9ICArMC4wMCBWLCBtYXggPSAgKzIuMDUgVikKaW4yOiAgICAg
ICAgICArMS4xNCBWICAobWluID0gICswLjAwIFYsIG1heCA9ICArMi4wNSBWKQppbjM6ICAgICAg
ICAgICsxLjc5IFYgIChtaW4gPSAgKzAuMDAgViwgbWF4ID0gICs0LjA4IFYpCmluNDogICAgICAg
ICAgKzEuNDcgViAgKG1pbiA9ICArMC4wMCBWLCBtYXggPSAgKzQuMDggVikKaW41OiAgICAgICAg
ICArMy4zOSBWICAobWluID0gICswLjAwIFYsIG1heCA9ICArNC4wOCBWKQppbjY6ICAgICAgICAg
ICswLjk4IFYgIChtaW4gPSAgKzAuMDAgViwgbWF4ID0gICsyLjA0IFYpCis1VjogICAgICAgICAg
KzUuMjEgViAgKG1pbiA9ICArNC41MiBWLCBtYXggPSAgKzUuNTAgVikKNVZTQjogICAgICAgICAr
NS4wMCBWICAobWluID0gICs0LjUyIFYsIG1heCA9ICArNS41MCBWKQpWYmF0OiAgICAgICAgICsw
LjAwIFYgIChtaW4gPSAgKzIuNzAgViwgbWF4ID0gICszLjMwIFYpCmZhbjE6ICAgICAgICA4NDkw
IFJQTSAgKG1pbiA9ICAgIDAgUlBNKQpmYW4yOiAgICAgICAgICAgMCBSUE0gIChtaW4gPSAgICAw
IFJQTSkKZmFuMzogICAgICAgIDkwNjAgUlBNICAobWluID0gICAgMCBSUE0pCmZhbjQ6ICAgICAg
ICAgICAwIFJQTSAgKG1pbiA9ICAgIDAgUlBNKQpmYW41OiAgICAgICAgOTAwMCBSUE0gIChtaW4g
PSAgICAwIFJQTSkKZmFuNjogICAgICAgICAgIDAgUlBNICAobWluID0gICAgMCBSUE0pCmZhbjc6
ICAgICAgICA4OTQwIFJQTSAgKG1pbiA9ICAgIDAgUlBNKQpmYW44OiAgICAgICAgICAgMCBSUE0g
IChtaW4gPSAgICAwIFJQTSkKZmFuOTogICAgICAgIDg5NDAgUlBNICAobWluID0gICAgMCBSUE0p
CmZhbjEwOiAgICAgICAgICAwIFJQTSAgKG1pbiA9ICAgIDAgUlBNKQpmYW4xMTogICAgICAgICAg
MCBSUE0gIChtaW4gPSAgICAwIFJQTSkKZmFuMTI6ICAgICAgICAgIDAgUlBNICAobWluID0gICAg
MCBSUE0pCnRlbXAxOiAgICAgICAgKzQzLjDCsEMgIChoaWdoID0gKzEwMC4wwrBDLCBoeXN0ID0g
Kzk1LjDCsEMpICBzZW5zb3IgPSBJbnRlbCBQRUNJCnRlbXAyOiAgICAgICAtMTI4LjDCsEMgICho
aWdoID0gKzEwMC4wwrBDLCBoeXN0ID0gKzk1LjDCsEMpICBzZW5zb3IgPSB0aGVybWFsIApkaW9k
ZQp0ZW1wNTogICAgICAgICsyNy4wwrBDICAoaGlnaCA9ICsxMDAuMMKwQywgaHlzdCA9ICs5NS4w
wrBDKSAgc2Vuc29yID0gdGhlcm1pc3Rvcgp0ZW1wNjogICAgICAgICsyNS4wwrBDICAoaGlnaCA9
ICsxMDAuMMKwQywgaHlzdCA9ICs5NS4wwrBDKSAgc2Vuc29yID0gdGhlcm1pc3RvcgppbnRydXNp
b24wOiAgQUxBUk0KYmVlcF9lbmFibGU6IGRpc2FibGVkCgp3ODM2MjdkaGctaXNhLTBhMTAKQWRh
cHRlcjogSVNBIGFkYXB0ZXIKVmNvcmU6ICAgICAgICArMC4wMCBWICAobWluID0gICswLjAwIFYs
IG1heCA9ICArMS43NCBWKQppbjE6ICAgICAgICAgICswLjAwIFYgIChtaW4gPSAgKzAuMDAgViwg
bWF4ID0gICswLjI2IFYpCkFWQ0M6ICAgICAgICAgKzMuMzMgViAgKG1pbiA9ICArMi45OCBWLCBt
YXggPSAgKzMuNjMgVikKKzMuM1Y6ICAgICAgICArMy4zMyBWICAobWluID0gICsyLjk4IFYsIG1h
eCA9ICArMy42MyBWKQppbjQ6ICAgICAgICAgICswLjAwIFYgIChtaW4gPSAgKzAuMjYgViwgbWF4
ID0gICsxLjAyIFYpICBBTEFSTQppbjU6ICAgICAgICAgICswLjAwIFYgIChtaW4gPSAgKzEuNTQg
ViwgbWF4ID0gICswLjAwIFYpICBBTEFSTQppbjY6ICAgICAgICAgICswLjAwIFYgIChtaW4gPSAg
KzAuMDAgViwgbWF4ID0gICsxLjAyIFYpCjNWU0I6ICAgICAgICAgKzMuMzMgViAgKG1pbiA9ICAr
Mi45OCBWLCBtYXggPSAgKzMuNjMgVikKVmJhdDogICAgICAgICArMy4yMiBWICAobWluID0gICsy
LjcwIFYsIG1heCA9ICArMy4zMCBWKQpmYW4xOiAgICAgICAgICAgMCBSUE0gIChtaW4gPSAxMDU0
NiBSUE0sIGRpdiA9IDEyOCkgIEFMQVJNCmZhbjI6ICAgICAgICAgICAwIFJQTSAgKG1pbiA9IDEw
NTQ2IFJQTSwgZGl2ID0gMTI4KSAgQUxBUk0KZmFuMzogICAgICAgICAgIDAgUlBNICAobWluID0g
MTA1NDYgUlBNLCBkaXYgPSAxMjgpICBBTEFSTQpmYW41OiAgICAgICAgICAgMCBSUE0gIChtaW4g
PSAxMDU0NiBSUE0sIGRpdiA9IDEyOCkgIEFMQVJNCnRlbXAxOiAgICAgICArMTI3LjDCsEMgICho
aWdoID0gKzIwLjDCsEMsIGh5c3QgPSArMjAuMMKwQykgIEFMQVJNICBzZW5zb3IgPSAKdGhlcm1p
c3QKb3IKdGVtcDI6ICAgICAgICArNDAuNcKwQyAgKGhpZ2ggPSArODAuMMKwQywgaHlzdCA9ICs3
NS4wwrBDKSAgc2Vuc29yID0gZGlvZGUKdGVtcDM6ICAgICAgICsxMjcuMMKwQyAgKGhpZ2ggPSAr
ODAuMMKwQywgaHlzdCA9ICs3NS4wwrBDKSAgQUxBUk0gIHNlbnNvciA9IAp0aGVybWlzdApvcgpj
cHUwX3ZpZDogICAgKzAuMDAwIFYKCk91dHB1dCBvZiBkbWVzZzoKJCBkbWVzZ3xncmVwIDgzNjI3
ClsgICAgOC4zNDU0MTddIHc4MzYyN2VoZjogRm9yY2libHkgZW5hYmxpbmcgU3VwZXItSS9PLiBT
ZW5zb3IgaXMgcHJvYmFibHkgCnVudXNhYmxlLgpbICAgIDguMzQ1NDI3XSB3ODM2MjdlaGY6IEZv
dW5kIFc4MzYyN0RIRyBjaGlwIGF0IDB4YTEwCgpPdXRwdXQgb2YgbHNwY2kgLW5uOgokIGxzcGNp
IC1ubgowMDowMC4wIEhvc3QgYnJpZGdlIFswNjAwXTogSW50ZWwgQ29ycG9yYXRpb24gNTEwMCBD
aGlwc2V0IE1lbW9yeSBDb250cm9sbGVyIApIdWIgWzgwODY6NjVjMF0gKHJldiA5MCkgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAKMDA6MDIuMCBQQ0kgYnJpZGdlIFswNjA0XTog
SW50ZWwgQ29ycG9yYXRpb24gNTEwMCBDaGlwc2V0IFBDSSBFeHByZXNzIHg0IFBvcnQgCjIgWzgw
ODY6NjVlMl0gKHJldiA5MCkKMDA6MDMuMCBQQ0kgYnJpZGdlIFswNjA0XTogSW50ZWwgQ29ycG9y
YXRpb24gNTEwMCBDaGlwc2V0IFBDSSBFeHByZXNzIHg0IFBvcnQgCjMgWzgwODY6NjVlM10gKHJl
diA5MCkKMDA6MDQuMCBQQ0kgYnJpZGdlIFswNjA0XTogSW50ZWwgQ29ycG9yYXRpb24gNTEwMCBD
aGlwc2V0IFBDSSBFeHByZXNzIHg4IFBvcnQgCjQtNSBbODA4Njo2NWY4XSAocmV2IDkwKQowMDow
NS4wIFBDSSBicmlkZ2UgWzA2MDRdOiBJbnRlbCBDb3Jwb3JhdGlvbiA1MTAwIENoaXBzZXQgUENJ
IEV4cHJlc3MgeDQgUG9ydCAKNSBbODA4Njo2NWU1XSAocmV2IDkwKQowMDowNi4wIFBDSSBicmlk
Z2UgWzA2MDRdOiBJbnRlbCBDb3Jwb3JhdGlvbiA1MTAwIENoaXBzZXQgUENJIEV4cHJlc3MgeDgg
UG9ydCAKNi03IFs4MDg2OjY1ZjldIChyZXYgOTApCjAwOjA3LjAgUENJIGJyaWRnZSBbMDYwNF06
IEludGVsIENvcnBvcmF0aW9uIDUxMDAgQ2hpcHNldCBQQ0kgRXhwcmVzcyB4NCBQb3J0IAo3IFs4
MDg2OjY1ZTddIChyZXYgOTApCjAwOjA4LjAgU3lzdGVtIHBlcmlwaGVyYWwgWzA4ODBdOiBJbnRl
bCBDb3Jwb3JhdGlvbiA1MTAwIENoaXBzZXQgRE1BIEVuZ2luZSAKWzgwODY6NjVmZl0gKHJldiA5
MCkKMDA6MTAuMCBIb3N0IGJyaWRnZSBbMDYwMF06IEludGVsIENvcnBvcmF0aW9uIDUxMDAgQ2hp
cHNldCBGU0IgUmVnaXN0ZXJzIApbODA4Njo2NWYwXSAocmV2IDkwKQowMDoxMC4xIEhvc3QgYnJp
ZGdlIFswNjAwXTogSW50ZWwgQ29ycG9yYXRpb24gNTEwMCBDaGlwc2V0IEZTQiBSZWdpc3RlcnMg
Cls4MDg2OjY1ZjBdIChyZXYgOTApCjAwOjEwLjIgSG9zdCBicmlkZ2UgWzA2MDBdOiBJbnRlbCBD
b3Jwb3JhdGlvbiA1MTAwIENoaXBzZXQgRlNCIFJlZ2lzdGVycyAKWzgwODY6NjVmMF0gKHJldiA5
MCkKMDA6MTEuMCBIb3N0IGJyaWRnZSBbMDYwMF06IEludGVsIENvcnBvcmF0aW9uIDUxMDAgQ2hp
cHNldCBSZXNlcnZlZCBSZWdpc3RlcnMgCls4MDg2OjY1ZjFdIChyZXYgOTApCjAwOjEzLjAgSG9z
dCBicmlkZ2UgWzA2MDBdOiBJbnRlbCBDb3Jwb3JhdGlvbiA1MTAwIENoaXBzZXQgUmVzZXJ2ZWQg
UmVnaXN0ZXJzIApbODA4Njo2NWYzXSAocmV2IDkwKQowMDoxNS4wIEhvc3QgYnJpZGdlIFswNjAw
XTogSW50ZWwgQ29ycG9yYXRpb24gNTEwMCBDaGlwc2V0IEREUiBDaGFubmVsIDAgClJlZ2lzdGVy
cyBbODA4Njo2NWY1XSAocmV2IDkwKQowMDoxNi4wIEhvc3QgYnJpZGdlIFswNjAwXTogSW50ZWwg
Q29ycG9yYXRpb24gNTEwMCBDaGlwc2V0IEREUiBDaGFubmVsIDEgClJlZ2lzdGVycyBbODA4Njo2
NWY2XSAocmV2IDkwKQowMDoxYS4wIFVTQiBDb250cm9sbGVyIFswYzAzXTogSW50ZWwgQ29ycG9y
YXRpb24gODI4MDFJIChJQ0g5IEZhbWlseSkgVVNCIFVIQ0kgCkNvbnRyb2xsZXIgIzQgWzgwODY6
MjkzN10gKHJldiAwMikKMDA6MWEuMSBVU0IgQ29udHJvbGxlciBbMGMwM106IEludGVsIENvcnBv
cmF0aW9uIDgyODAxSSAoSUNIOSBGYW1pbHkpIFVTQiBVSENJIApDb250cm9sbGVyICM1IFs4MDg2
OjI5MzhdIChyZXYgMDIpCjAwOjFhLjcgVVNCIENvbnRyb2xsZXIgWzBjMDNdOiBJbnRlbCBDb3Jw
b3JhdGlvbiA4MjgwMUkgKElDSDkgRmFtaWx5KSBVU0IyIApFSENJIENvbnRyb2xsZXIgIzIgWzgw
ODY6MjkzY10gKHJldiAwMikKMDA6MWMuMCBQQ0kgYnJpZGdlIFswNjA0XTogSW50ZWwgQ29ycG9y
YXRpb24gODI4MDFJIChJQ0g5IEZhbWlseSkgUENJIEV4cHJlc3MgClBvcnQgMSBbODA4NjoyOTQw
XSAocmV2IDAyKQowMDoxYy40IFBDSSBicmlkZ2UgWzA2MDRdOiBJbnRlbCBDb3Jwb3JhdGlvbiA4
MjgwMUkgKElDSDkgRmFtaWx5KSBQQ0kgRXhwcmVzcyAKUG9ydCA1IFs4MDg2OjI5NDhdIChyZXYg
MDIpCjAwOjFjLjUgUENJIGJyaWRnZSBbMDYwNF06IEludGVsIENvcnBvcmF0aW9uIDgyODAxSSAo
SUNIOSBGYW1pbHkpIFBDSSBFeHByZXNzIApQb3J0IDYgWzgwODY6Mjk0YV0gKHJldiAwMikKMDA6
MWQuMCBVU0IgQ29udHJvbGxlciBbMGMwM106IEludGVsIENvcnBvcmF0aW9uIDgyODAxSSAoSUNI
OSBGYW1pbHkpIFVTQiBVSENJIApDb250cm9sbGVyICMxIFs4MDg2OjI5MzRdIChyZXYgMDIpCjAw
OjFkLjEgVVNCIENvbnRyb2xsZXIgWzBjMDNdOiBJbnRlbCBDb3Jwb3JhdGlvbiA4MjgwMUkgKElD
SDkgRmFtaWx5KSBVU0IgVUhDSSAKQ29udHJvbGxlciAjMiBbODA4NjoyOTM1XSAocmV2IDAyKQow
MDoxZC4yIFVTQiBDb250cm9sbGVyIFswYzAzXTogSW50ZWwgQ29ycG9yYXRpb24gODI4MDFJIChJ
Q0g5IEZhbWlseSkgVVNCIFVIQ0kgCkNvbnRyb2xsZXIgIzMgWzgwODY6MjkzNl0gKHJldiAwMikK
MDA6MWQuMyBVU0IgQ29udHJvbGxlciBbMGMwM106IEludGVsIENvcnBvcmF0aW9uIDgyODAxSSAo
SUNIOSBGYW1pbHkpIFVTQiBVSENJIApDb250cm9sbGVyICM2IFs4MDg2OjI5MzldIChyZXYgMDIp
CjAwOjFkLjcgVVNCIENvbnRyb2xsZXIgWzBjMDNdOiBJbnRlbCBDb3Jwb3JhdGlvbiA4MjgwMUkg
KElDSDkgRmFtaWx5KSBVU0IyIApFSENJIENvbnRyb2xsZXIgIzEgWzgwODY6MjkzYV0gKHJldiAw
MikKMDA6MWUuMCBQQ0kgYnJpZGdlIFswNjA0XTogSW50ZWwgQ29ycG9yYXRpb24gODI4MDEgUENJ
IEJyaWRnZSBbODA4NjoyNDRlXSAocmV2IAo5MikKMDA6MWYuMCBJU0EgYnJpZGdlIFswNjAxXTog
SW50ZWwgQ29ycG9yYXRpb24gODI4MDFJUiAoSUNIOVIpIExQQyBJbnRlcmZhY2UgCkNvbnRyb2xs
ZXIgWzgwODY6MjkxNl0gKHJldiAwMikKMDA6MWYuMiBTQVRBIGNvbnRyb2xsZXIgWzAxMDZdOiBJ
bnRlbCBDb3Jwb3JhdGlvbiA4MjgwMUlSL0lPL0lIIChJQ0g5Ui9ETy9ESCkgCjYgcG9ydCBTQVRB
IEFIQ0kgQ29udHJvbGxlciBbODA4NjoyOTIyXSAocmV2IDAyKQowMDoxZi4zIFNNQnVzIFswYzA1
XTogSW50ZWwgQ29ycG9yYXRpb24gODI4MDFJIChJQ0g5IEZhbWlseSkgU01CdXMgQ29udHJvbGxl
ciAKWzgwODY6MjkzMF0gKHJldiAwMikKMDI6MDAuMCBFdGhlcm5ldCBjb250cm9sbGVyIFswMjAw
XTogSW50ZWwgQ29ycG9yYXRpb24gODI1NzRMIEdpZ2FiaXQgTmV0d29yayAKQ29ubmVjdGlvbiBb
ODA4NjoxMGQzXQowMzowMC4wIEV0aGVybmV0IGNvbnRyb2xsZXIgWzAyMDBdOiBJbnRlbCBDb3Jw
b3JhdGlvbiA4MjU3NEwgR2lnYWJpdCBOZXR3b3JrIApDb25uZWN0aW9uIFs4MDg2OjEwZDNdCjA2
OjAwLjAgVkdBIGNvbXBhdGlibGUgY29udHJvbGxlciBbMDMwMF06IEFUSSBUZWNobm9sb2dpZXMg
SW5jIFJWNzEwIFtSYWRlb24gCkhEIDQzNTBdIFsxMDAyOjk1NGZdCjA2OjAwLjEgQXVkaW8gZGV2
aWNlIFswNDAzXTogQVRJIFRlY2hub2xvZ2llcyBJbmMgUlY3MTAvNzMwIFsxMDAyOmFhMzhdCjA5
OjAwLjAgRXRoZXJuZXQgY29udHJvbGxlciBbMDIwMF06IEludGVsIENvcnBvcmF0aW9uIDgyNTcx
RUIgR2lnYWJpdCBFdGhlcm5ldCAKQ29udHJvbGxlciBbODA4NjoxMDVlXSAocmV2IDA2KQowOTow
MC4xIEV0aGVybmV0IGNvbnRyb2xsZXIgWzAyMDBdOiBJbnRlbCBDb3Jwb3JhdGlvbiA4MjU3MUVC
IEdpZ2FiaXQgRXRoZXJuZXQgCkNvbnRyb2xsZXIgWzgwODY6MTA1ZV0gKHJldiAwNikKMGE6MDAu
MCBFdGhlcm5ldCBjb250cm9sbGVyIFswMjAwXTogSW50ZWwgQ29ycG9yYXRpb24gODI1NzFFQiBH
aWdhYml0IEV0aGVybmV0IApDb250cm9sbGVyIFs4MDg2OjEwNWVdIChyZXYgMDYpCjBhOjAwLjEg
RXRoZXJuZXQgY29udHJvbGxlciBbMDIwMF06IEludGVsIENvcnBvcmF0aW9uIDgyNTcxRUIgR2ln
YWJpdCBFdGhlcm5ldCAKQ29udHJvbGxlciBbODA4NjoxMDVlXSAocmV2IDA2KQoKaTJjZGV0ZWN0
IC1sIG91dHB1dDoKbm9uZQoKCi0tIApNZWxob3JlcyBjdW1wcmltZW50b3MvQmVzdCBSZWdhcmRz
LAoKTWlndWVsIEZpZ3VlaXJlZG8KaHR0cDovL3d3dy5EZWJpYW5QVC5vcmcKCl9fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxtLXNlbnNvcnMgbWFpbGluZyBs
aXN0CmxtLXNlbnNvcnNAbG0tc2Vuc29ycy5vcmcKaHR0cDovL2xpc3RzLmxtLXNlbnNvcnMub3Jn
L21haWxtYW4vbGlzdGluZm8vbG0tc2Vuc29ycw=
^ permalink raw reply
* [PATCH 2/2] pretty.c: use original commit message if reencoding fails
From: Nguyễn Thái Ngọc Duy @ 2011-10-23 11:51 UTC (permalink / raw)
To: git; +Cc: Junio C Hamano, Nguyễn Thái Ngọc Duy
In-Reply-To: <1319370695-12638-1-git-send-email-pclouds@gmail.com>
Signed-off-by: Nguyễn Thái Ngọc Duy <pclouds@gmail.com>
---
pretty.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/pretty.c b/pretty.c
index 375ff7b..230fe1c 100644
--- a/pretty.c
+++ b/pretty.c
@@ -1103,8 +1103,11 @@ void format_commit_message(const struct commit *commit,
context.message = commit->buffer;
if (output_enc) {
char *enc = get_header(commit, "encoding");
- if (strcmp(enc ? enc : utf8, output_enc))
+ if (strcmp(enc ? enc : utf8, output_enc)) {
context.message = logmsg_reencode(commit, output_enc);
+ if (!context.message)
+ context.message = commit->buffer;
+ }
free(enc);
}
--
1.7.3.1.256.g2539c.dirty
^ permalink raw reply related
* [PATCH 1/2] pretty.c: free get_header() return value
From: Nguyễn Thái Ngọc Duy @ 2011-10-23 11:51 UTC (permalink / raw)
To: git; +Cc: Junio C Hamano, Nguyễn Thái Ngọc Duy
Signed-off-by: Nguyễn Thái Ngọc Duy <pclouds@gmail.com>
---
pretty.c | 7 +++----
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/pretty.c b/pretty.c
index f45eb54..375ff7b 100644
--- a/pretty.c
+++ b/pretty.c
@@ -1094,7 +1094,6 @@ void format_commit_message(const struct commit *commit,
{
struct format_commit_context context;
static const char utf8[] = "UTF-8";
- const char *enc;
const char *output_enc = pretty_ctx->output_encoding;
memset(&context, 0, sizeof(context));
@@ -1103,10 +1102,10 @@ void format_commit_message(const struct commit *commit,
context.wrap_start = sb->len;
context.message = commit->buffer;
if (output_enc) {
- enc = get_header(commit, "encoding");
- enc = enc ? enc : utf8;
- if (strcmp(enc, output_enc))
+ char *enc = get_header(commit, "encoding");
+ if (strcmp(enc ? enc : utf8, output_enc))
context.message = logmsg_reencode(commit, output_enc);
+ free(enc);
}
strbuf_expand(sb, format, format_commit_item, &context);
--
1.7.3.1.256.g2539c.dirty
^ permalink raw reply related
* [U-Boot] [PATCH] Update s3c24x0 timer implementation
From: Mark Norman @ 2011-10-23 11:52 UTC (permalink / raw)
To: u-boot
I have been doing some work to get U-Boot running on a samsung S3C2440
based SBC (QQ2440). I experienced several issues getting the board
running including "raise: Signal # 8 caught" errors being printed to
the console. After a bit of debugging with a JTAG debugger I found
the problems were due to arch/arm/cpu/arm920t/s3c24x0/timer.c using
several global variables prior to relocation to RAM. I noticed that
the global variable .bss section is shared with the .rel.text section.
Since the .rel.text section is required by the relocation code, I
assume that .bss global variables cannot be used until after
relocation?
After studying several other timer.c files I developed the following
patch which uses the global data struct to store the global variables.
I also restructured some of the code based on structure of the other
timer.c files. I have confirmed it works correctly on the SBC I have.
Regards
Mark Norman
The s3c24x0 timer has been updated to use the global_data struct.
Restructured code based on other timer.c files.
Updated comments and several parameters.
Signed-off-by: Mark Norman <mpnorman@gmail.com>
---
arch/arm/cpu/arm920t/s3c24x0/timer.c | 158 +++++++++++++--------------------
arch/arm/include/asm/global_data.h | 12 +--
2 files changed, 66 insertions(+), 104 deletions(-)
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c
b/arch/arm/cpu/arm920t/s3c24x0/timer.c
index 9571870..1552345 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -35,146 +35,112 @@
#include <asm/io.h>
#include <asm/arch/s3c24x0_cpu.h>
-int timer_load_val = 0;
-static ulong timer_clk;
+DECLARE_GLOBAL_DATA_PTR;
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
+/* Read the 16 bit timer */
+static inline ulong read_timer(void)
{
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
-
return readl(&timers->tcnto4) & 0xffff;
}
-static ulong timestamp;
-static ulong lastdec;
-
int timer_init(void)
{
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
ulong tmr;
- /* use PWM Timer 4 because it has no output */
- /* prescaler for Timer 4 is 16 */
- writel(0x0f00, &timers->tcfg0);
- if (timer_load_val == 0) {
- /*
- * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
- * (default) and prescaler = 16. Should be 10390
- * @33.25MHz and 15625 @ 50 MHz
- */
- timer_load_val = get_PCLK() / (2 * 16 * 100);
- timer_clk = get_PCLK() / (2 * 16);
- }
- /* load value for 10 ms timeout */
- lastdec = timer_load_val;
- writel(timer_load_val, &timers->tcntb4);
- /* auto load, manual update of timer 4 */
+ /* Use PWM Timer 4 because it has no output.
+ * Prescaler is hard fixed at 250, divider at 2.
+ * This generates a Timer clock frequency of 100kHz (@PCLK=50MHz) and
+ * therefore 10us timer ticks.
+ */
+
+ /* Prescaler for Timer 4 is 250 */
+ const ulong prescaler = 250;
+ writel((prescaler-1) << 8, &timers->tcfg0);
+
+ /* Calculate timer freq, approx 100kHz @ PCLK=50MHz. */
+ gd->timer_rate_hz = get_PCLK() / (2 * prescaler);
+
+ /* Set timer for 0.5s timeout (50000 ticks @ 10us ticks). */
+ gd->timer_reset_value = 50000;
+ writel(gd->timer_reset_value, &timers->tcntb4);
+ gd->lastdec = gd->timer_reset_value;
+
+ /* Load the initial timer 4 count value using the manual update bit. */
tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->tcon);
- /* auto load, start timer 4 */
+
+ /* Configure timer 4 for auto reload and start it. */
tmr = (tmr & ~0x0700000) | 0x0500000;
writel(tmr, &timers->tcon);
- timestamp = 0;
+
+ gd->timestamp = 0;
return (0);
}
/*
- * timer without interrupts
+ * Get the number of ticks (in CONFIG_SYS_HZ resolution)
*/
-ulong get_timer(ulong base)
+unsigned long long get_ticks(void)
{
- return get_timer_masked() - base;
+ return get_timer(0);
}
-void __udelay (unsigned long usec)
+unsigned long get_timer_raw(void)
{
- ulong tmo;
- ulong start = get_ticks();
+ ulong now = read_timer();
- tmo = usec / 1000;
- tmo *= (timer_load_val * 100);
- tmo /= 1000;
+ if (gd->lastdec >= now) {
+ /* normal mode */
+ gd->timestamp += gd->lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ gd->timestamp += gd->lastdec + gd->timer_reset_value - now;
+ }
+ gd->lastdec = now;
- while ((ulong) (get_ticks() - start) < tmo)
- /*NOP*/;
+ return gd->timestamp;
}
-ulong get_timer_masked(void)
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
{
- ulong tmr = get_ticks();
-
- return tmr / (timer_clk / CONFIG_SYS_HZ);
+ return CONFIG_SYS_HZ;
}
-void udelay_masked(unsigned long usec)
+ulong get_timer_masked(void)
{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- if (usec >= 1000) {
- tmo = usec / 1000;
- tmo *= (timer_load_val * 100);
- tmo /= 1000;
- } else {
- tmo = usec * (timer_load_val * 100);
- tmo /= (1000 * 1000);
- }
+ unsigned long tmr = get_timer_raw();
- endtime = get_ticks() + tmo;
+ return (tmr * CONFIG_SYS_HZ) / gd->timer_rate_hz;
+}
- do {
- ulong now = get_ticks();
- diff = endtime - now;
- } while (diff >= 0);
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
}
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
+void __udelay(unsigned long usec)
{
- ulong now = READ_TIMER();
+ unsigned long tmp;
+ unsigned long tmo;
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec + timer_load_val - now;
- }
- lastdec = now;
+ /* convert usec to ticks. */
+ tmo = ((gd->timer_rate_hz / 1000) * usec) / 1000;
- return timestamp;
-}
+ tmp = get_timer_raw() + tmo; /* get current timestamp */
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
-#if defined(CONFIG_SMDK2400)
- tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SBC2410X) || \
- defined(CONFIG_SMDK2410) || \
- defined(CONFIG_S3C2440) || \
- defined(CONFIG_VCMA9)
- tbclk = CONFIG_SYS_HZ;
-#else
-# error "tbclk not configured"
-#endif
-
- return tbclk;
+ while (get_timer_raw() < tmp) /* loop till event */
+ /*NOP*/;
}
/*
- * reset the cpu by setting up the watchdog timer and let him time out
+ * Reset the cpu by setting up the watchdog timer and let him time out
*/
void reset_cpu(ulong ignored)
{
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index fac98d5..a20a9f7 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -38,9 +38,6 @@ typedef struct global_data {
unsigned long flags;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long fb_base; /* base address of frame buffer */
@@ -67,6 +64,10 @@ typedef struct global_data {
#ifdef CONFIG_IXP425
unsigned long timestamp;
#endif
+#ifdef CONFIG_S3C24X0
+ unsigned long lastdec;
+ unsigned long timestamp;
+#endif
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */
unsigned long mon_len; /* monitor len */
@@ -78,11 +79,6 @@ typedef struct global_data {
#endif
void **jt; /* jump table */
char env_buf[32]; /* buffer for getenv() before reloc. */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
- unsigned long post_log_word; /* Record POST activities */
- unsigned long post_log_res; /* success of POST test */
- unsigned long post_init_f_time; /* When post_init_f started */
-#endif
} gd_t;
/*
--
1.7.1
^ permalink raw reply related
* [U-Boot] [PATCH v4 2/2] NS16550: buffer reads
From: Graeme Russ @ 2011-10-23 11:50 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20111023082051.6397518AE823@gemini.denx.de>
Hi Wolgang,
On Oct 23, 2011 7:20 PM, "Wolfgang Denk" <wd@denx.de> wrote:
>
> Dear Graeme Russ,
>
> In message <4EA34086.4030101@gmail.com> you wrote:
> >
> > One problem I see with XON/XOFF is that if we don't send XOFF at the
right
> > time, we run the risk of entering a busy loop (any reasonable timeout
delay
> > for example) and loosing input. So in theory, we would need to send XOFF
> > after every getc() ...
>
> That's not true. I am not aware of any significant delays that take
> place while receiving characters that belong to a single line. If we
> had any of these, we would lose characters all the time - but we
> don't.
>
> It should be sufficient to send XOFF after receiving a newline
> character.
And, ergo, we send an XON when entering the readline function
Hmm, should we move readline() into console.c
> > Maybe we need disable/enable flow control functions for when we know we
> > will be entering a busy loop the consumes serial input (ymodem and
kermit
> > transfers and readline for example)
>
> This should not be necessary. Actually the implementation should not
> need to know about such special cases.
So how does kermit/ymodem send the XON after the user has entered the
receive command and we have sent the XOFF after the newline?
Regards,
Graeme
^ permalink raw reply
* Re: [PATCH 2/2] x86, microcode, AMD: Add microcode revision to /proc/cpuinfo
From: Ingo Molnar @ 2011-10-23 11:48 UTC (permalink / raw)
To: Borislav Petkov; +Cc: X86-ML, LKML
In-Reply-To: <20111019142057.GA26786@aftab>
* Borislav Petkov <bp@amd64.org> wrote:
> On Tue, Oct 18, 2011 at 02:25:10AM -0400, Ingo Molnar wrote:
> > The standard way we mention commits in changelogs is:
> >
> > Enable microcode revision output for AMD after commit 506ed6b53e00
> > ("x86, intel: Output microcode revision in /proc/cpuinfo") did it
> > for Intel.
> >
> > ... because humans are pretty bad at transforming sha1's to the real
> > commit title when reading such text.
>
> Why, I thought transforming sha1's to commit messages is one of the job
> requirements of serious kernel hackers.
>
> :-)
But they are not the only ones reading changelogs ;-)
> > Please fix the changelog for the first commit as well.
>
> Done, git branch at
>
> git://amd64.org/linux/bp.git tip-ucode
>
> updated.
Pulled, thanks,
Ingo
^ permalink raw reply
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