* Re: [PATCH] KVM: MMU: initialize sptes early
From: Xiao Guangrong @ 2011-10-24 7:41 UTC (permalink / raw)
To: Zhao Jin; +Cc: avi, mtosatti, linux-kernel, kvm
In-Reply-To: <1319440880-2610-1-git-send-email-cronozhj@gmail.com>
On 2011/10/24 15:21, Zhao Jin wrote:
> Otherwise, the following kvm_sync_pages() will see invalid sptes in a new
> shadow page.
>
No, kvm_sync_pages just handle the unsync page, but the new sp is the sync page.
^ permalink raw reply
* Re: DeviceTree and children devices
From: Grant Likely @ 2011-10-24 7:41 UTC (permalink / raw)
To: Felipe Balbi; +Cc: Linux Kernel Mailing List, Linux USB Mailing List
In-Reply-To: <20111024064227.GW5453@legolas.emea.dhcp.ti.com>
On Mon, Oct 24, 2011 at 09:42:28AM +0300, Felipe Balbi wrote:
> Hi Grant,
>
> I have a question about how DeviceTree should be written in case a
> device has a child device.
>
> The way things are integrated on OMAP is that we will always have a
> parent device which is a wrapper around an IP core in order to
> integrate with the OMAP context (clocks, power management, etc).
>
> That wrapper has its own address space and its own IRQ number
> (generally). On my dwc3 driver I have modeled the OMAP wrapper as a
> parent device which allocates a child device for the core IP driver.
> This makes it a lot easier to re-use the core IP driver on other SoCs or
> PCI (there's a glue layer for PCI too).
>
> So I wonder if we should describe that on DeviceTree and not have the
> OMAP glue layer allocate the core IP driver. Just to illustrate, here's
> what we have:
>
> static int dwc3_omap_probe(struct platform_device *pdev)
> {
> struct platform_device *dwc3;
> struct resource res[2];
>
> dwc3 = platform_device_alloc("dwc3", -1);
> /* check*/
>
> dwc3->dev.parent = &pdev->dev;
>
> /* copy DMA fields from parent too */
>
> res[0].start = start_address;
> res[0].end = end_address;
> res[0].flags = IORESOURCE_MEM;
>
> res[1].start = irq_number;
> res[1].flags = IORESOURCE_IRQ;
>
> ret = platform_add_resources(dwc3, res, ARRAY_SIZE(res));
> /* check */
>
> return platform_add_device(dwc3);
> }
>
> and I wonder if I should have a DeviceTree like so:
>
> usb@xxxxx {
> compatible = "ti,dwc3-omap"; // This is TI OMAP
> // wrapper
> range = <....>;
>
> ...
>
> usb@yyyy {
> compatible = "synopsys,dwc3", // This is core IP
> // inside wrapper
>
> ...
> };
> };
>
> then I can drop the dwc3 platform_device allocation and all of that
> resource copying, etc.
>
> What do you think ?
Looks reasonable to me. of_platform_populate() should be able to
handle the device generation for you here.
g.
^ permalink raw reply
* [U-Boot] [PATCH v4 11/11] arm, davinci: add cam_enc_4xx support
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
- DM368 SOC
- booting with spl not with UBL from TI
- before loading u-boot from NAND into RAM, test
the RAM with the post memory test. If error
is found, switch all LEDs on and halt system.
- SPI Flash
Dataflash Typ: M25PE80
- Ethernet DM9161BI
- MMC
- USB
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
changes for v2:
- rebase to TOT
- adapted to new spl framework
- add USB support
- MDIO Clk only 1MHz
- LED: set LED in spl code, and clear them after 1 second
- add "bdinfo" command
- add nandrbl board specific command for switching
between rbl and uboot ecc calculation algorithm
changes for v3:
- add CONFIG_SYS_NAND_HW_ECC_OOBFIRST
changes for v4:
- add comments from Igor Grinberg
- remove in board/ait/cam_enc_4xx/Makefile
unnecessary targets clean, distcelan
- use CONFIG_MACH_TYPE option
- removed some unnecessary brackets
- new patch: add a weak enable_vbus() in
drivers/usb/musb/davinci.c
- add a comment to an "#else" to make it clearer
to which "#if" it belongs
- fix ALL to ALL-y in board config.mk, and add this only
if CONFIG_SPL_BUILD is not set.
MAINTAINERS | 1 +
board/ait/cam_enc_4xx/Makefile | 46 ++++
board/ait/cam_enc_4xx/cam_enc_4xx.c | 446 +++++++++++++++++++++++++++++++++
board/ait/cam_enc_4xx/config.mk | 15 ++
board/ait/cam_enc_4xx/u-boot-spl.lds | 73 ++++++
board/ait/cam_enc_4xx/ublimage.cfg | 48 ++++
boards.cfg | 1 +
doc/README.davinci.nand_spl | 141 +++++++++++
include/configs/cam_enc_4xx.h | 452 ++++++++++++++++++++++++++++++++++
tools/ublimage.h | 2 +-
10 files changed, 1224 insertions(+), 1 deletions(-)
create mode 100644 board/ait/cam_enc_4xx/Makefile
create mode 100644 board/ait/cam_enc_4xx/cam_enc_4xx.c
create mode 100644 board/ait/cam_enc_4xx/config.mk
create mode 100644 board/ait/cam_enc_4xx/u-boot-spl.lds
create mode 100644 board/ait/cam_enc_4xx/ublimage.cfg
create mode 100644 doc/README.davinci.nand_spl
create mode 100644 include/configs/cam_enc_4xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f5168b0..1740143 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -413,6 +413,7 @@ Georg Schardt <schardt@team-ctech.de>
Heiko Schocher <hs@denx.de>
+ cam_enc_4xx davinci/ARM926EJS
charon MPC5200
ids8247 MPC8247
jupiter MPC5200
diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile
new file mode 100644
index 0000000..2b22124
--- /dev/null
+++ b/board/ait/cam_enc_4xx/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c
new file mode 100644
index 0000000..1351358
--- /dev/null
+++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c
@@ -0,0 +1,446 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+#include <nand.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+static struct davinci_timer *timer =
+ (struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+static unsigned long get_timer_val(void)
+{
+ unsigned long now = readl(&timer->tim34);
+
+ return now;
+}
+
+static void stop_timer(void)
+{
+ writel(0x0, &timer->tcr);
+ return;
+}
+
+int checkboard(void)
+{
+ printf("Board: AIT CAM ENC 4XX\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+int board_eth_init(bd_t *bis)
+{
+ davinci_emac_initialize();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+static int
+davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ struct nand_chip *this = mtd->priv;
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *oob = chip->oob_poi;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+ chip->read_buf(mtd, oob, mtd->oobsize);
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
+
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+ chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
+
+ if (chip->ecc.prepad)
+ oob += chip->ecc.prepad;
+
+ stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+ if (stat == -1)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+
+ oob += eccbytes;
+
+ if (chip->ecc.postpad)
+ oob += chip->ecc.postpad;
+ }
+
+ /* Calculate remaining oob bytes */
+ i = mtd->oobsize - (oob - chip->oob_poi);
+ if (i)
+ chip->read_buf(mtd, oob, i);
+
+ return 0;
+}
+
+static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf)
+{
+ unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
+ struct nand_chip *this = mtd->priv;
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+ int offset = 0;
+ const uint8_t *p = buf;
+ uint8_t *oob = chip->oob_poi;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, p, eccsize);
+
+ /* Calculate ECC without prepad */
+ chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
+
+ if (chip->ecc.prepad) {
+ offset = (chip->ecc.steps - eccsteps) * chunk;
+ memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
+ oob += chip->ecc.prepad;
+ }
+
+ offset = ((chip->ecc.steps - eccsteps) * chunk) +
+ chip->ecc.prepad;
+ memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
+ oob += eccbytes;
+
+ if (chip->ecc.postpad) {
+ offset = ((chip->ecc.steps - eccsteps) * chunk) +
+ chip->ecc.prepad + eccbytes;
+ memcpy(&davinci_ecc_buf[offset], oob,
+ chip->ecc.postpad);
+ oob += chip->ecc.postpad;
+ }
+ }
+
+ /*
+ * Write the sparebytes into the page once
+ * all eccsteps have been covered
+ */
+ for (i = 0; i < mtd->oobsize; i++)
+ writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
+
+ /* Calculate remaining oob bytes */
+ i = mtd->oobsize - (oob - chip->oob_poi);
+ if (i)
+ chip->write_buf(mtd, oob, i);
+}
+
+static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ int pos, status = 0;
+ const uint8_t *bufpoi = chip->oob_poi;
+
+ pos = mtd->writesize;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
+
+ chip->write_buf(mtd, bufpoi, mtd->oobsize);
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -1 : 0;
+}
+
+static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, int page, int sndcmd)
+{
+ struct nand_chip *this = mtd->priv;
+ uint8_t *buf = chip->oob_poi;
+ uint8_t *bufpoi = buf;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+ chip->read_buf(mtd, bufpoi, mtd->oobsize);
+
+ return 1;
+}
+
+static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long wbase = (unsigned long) this->IO_ADDR_W;
+ unsigned long rbase = (unsigned long) this->IO_ADDR_R;
+
+ if (chip == 1) {
+ __set_bit(14, &wbase);
+ __set_bit(14, &rbase);
+ } else {
+ __clear_bit(14, &wbase);
+ __clear_bit(14, &rbase);
+ }
+ this->IO_ADDR_W = (void *)wbase;
+ this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+ nand->select_chip = nand_dm365evm_select_chip;
+
+ return 0;
+}
+
+struct nand_ecc_ctrl org_ecc;
+static int notsaved = 1;
+
+static int nand_switch_hw_func(int mode)
+{
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+
+ if (nand_curr_device < 0 ||
+ nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
+ !nand_info[nand_curr_device].name) {
+ printf("Error: Can't switch hw functions," \
+ " no devices available\n");
+ return -1;
+ }
+
+ mtd = &nand_info[nand_curr_device];
+ nand = mtd->priv;
+
+ if (mode == 0) {
+ printf("switching to uboot hw functions.\n");
+ memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl));
+ } else {
+ /* RBL */
+ printf("switching to RBL hw functions.\n");
+ if (notsaved == 1) {
+ memcpy(&org_ecc, &nand->ecc,
+ sizeof(struct nand_ecc_ctrl));
+ notsaved = 0;
+ }
+ nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+ nand->ecc.prepad = 6;
+ nand->ecc.read_page = davinci_std_read_page_syndrome;
+ nand->ecc.write_page = davinci_std_write_page_syndrome;
+ nand->ecc.read_oob = davinci_std_read_oob_syndrome;
+ nand->ecc.write_oob = davinci_std_write_oob_syndrome;
+ }
+ return mode;
+}
+
+static int hwmode;
+
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ goto usage;
+ if (strncmp(argv[1], "rbl", 2) == 0)
+ hwmode = nand_switch_hw_func(1);
+ else if (strncmp(argv[1], "uboot", 2) == 0)
+ hwmode = nand_switch_hw_func(0);
+ else
+ goto usage;
+
+ return 0;
+
+usage:
+ printf("Usage: nandrbl %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandrbl, 2, 1, do_switch_ecc,
+ "switch between rbl/uboot NAND ECC calculation algorithm",
+ "[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
+);
+
+
+#endif /* #ifdef CONFIG_NAND_DAVINCI */
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+
+ return err;
+}
+#endif
+
+int board_late_init(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+ /* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
+ while (get_timer_val() < 0x186a00)
+ ;
+
+ /* 1 sec reached -> stop timer, clear all LED */
+ stop_timer();
+ clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+ return 0;
+}
+
+void reset_phy(void)
+{
+ char *name = "GENERIC @ 0x00";
+
+ /* reset the phy */
+ miiphy_reset(name, 0x0);
+}
+
+#else /* #ifndef CONFIG_SPL_BUILD */
+static void cam_enc_4xx_set_all_led(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+ setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+}
+
+/*
+ * TIMER 0 is used for tick
+ */
+static struct davinci_timer *timer =
+ (struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+#define TIMER_LOAD_VAL 0xffffffff
+#define TIM_CLK_DIV 16
+
+static int cam_enc_4xx_timer_init(void)
+{
+ /* We are using timer34 in unchained 32-bit mode, full speed */
+ writel(0x0, &timer->tcr);
+ writel(0x0, &timer->tgcr);
+ writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+ writel(0x0, &timer->tim34);
+ writel(TIMER_LOAD_VAL, &timer->prd34);
+ writel(2 << 22, &timer->tcr);
+ return 0;
+}
+
+void board_gpio_init(void)
+{
+ struct davinci_gpio *gpio;
+
+ cam_enc_4xx_set_all_led();
+ cam_enc_4xx_timer_init();
+ gpio = davinci_gpio_bank01;
+ clrbits_le32(&gpio->dir, ~0xfdfffffe);
+ /* clear LED D14 = GPIO25 */
+ clrbits_le32(&gpio->out_data, 0x02000000);
+ gpio = davinci_gpio_bank23;
+ clrbits_le32(&gpio->dir, ~0x5ff0afef);
+ /* set GPIO61 to 1 -> intern UART0 as Console */
+ setbits_le32(&gpio->out_data, 0x20000000);
+ /*
+ * PHY out of reset GIO 50 = 1
+ * NAND WP off GIO 51 = 1
+ */
+ setbits_le32(&gpio->out_data, 0x000c0004);
+ gpio = davinci_gpio_bank45;
+ clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
+ /*
+ * clear LED:
+ * D17 = GPIO86
+ * D11 = GPIO87
+ * GPIO88
+ * GPIO89
+ * D13 = GPIO90
+ * GPIO91
+ */
+ clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+ gpio = davinci_gpio_bank67;
+ clrbits_le32(&gpio->dir, ~0x000007ff);
+}
+
+/*
+ * functions for the post memory test.
+ */
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+ *size = PHYS_SDRAM_1_SIZE;
+ *phys_offset = 0;
+ return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+ cam_enc_4xx_set_all_led();
+ puts("mem failure\n");
+ while (1)
+ ;
+}
+#endif
diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk
new file mode 100644
index 0000000..b1f9b6c
--- /dev/null
+++ b/board/ait/cam_enc_4xx/config.mk
@@ -0,0 +1,15 @@
+#
+# AIT cam_enc_4xx board
+# cam_enc_4xx board has 1 bank of 256 MB DDR RAM
+# Physical Address: 8000'0000 to 9000'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+PAD_TO := 12320
+UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
+ifndef CONFIG_SPL_BUILD
+ALL-y += $(obj)u-boot.ubl
+endif
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
new file mode 100644
index 0000000..6f6e065
--- /dev/null
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/arm926ejs/start.o (.text)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ } >.sram
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ } >.sram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >.sram
+
+ __image_copy_end = .;
+ _end = .;
+}
diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg
new file mode 100644
index 0000000..95182ca
--- /dev/null
+++ b/board/ait/cam_enc_4xx/ublimage.cfg
@@ -0,0 +1,48 @@
+#
+# (C Copyright 2011
+# Heiko Schocher DENX Software Engineering hs at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer doc/README.ublimage for more details about how-to configure
+# and create ublimage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# UBL special mode : one of
+# safe (the board has no nand neither onenand)
+MODE safe
+
+# Entry point address for the user bootloader (absolute address)
+# nand spl TEXT_BASE = 0x20 !!
+ENTRY 0x00000020
+
+# Number of pages (size of user bootloader in number of pages)
+# @ nand spl 6 pages
+PAGES 6
+
+# Block number where user bootloader is present
+# RBL starts always with block 1
+START_BLOCK 5
+
+# Page number where user bootloader is present
+# Page 0 is always UBL header
+START_PAGE 0
+
+LD_ADDR 0x20
diff --git a/boards.cfg b/boards.cfg
index bccb832..aa4f2fc 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -120,6 +120,7 @@ pm9263 arm arm926ejs pm9263 ronetix
pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45
da830evm arm arm926ejs da8xxevm davinci davinci
da850evm arm arm926ejs da8xxevm davinci davinci
+cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx
hawkboard arm arm926ejs da8xxevm davinci davinci
hawkboard_nand arm arm926ejs da8xxevm davinci davinci hawkboard:NAND_U_BOOT
hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT
diff --git a/doc/README.davinci.nand_spl b/doc/README.davinci.nand_spl
new file mode 100644
index 0000000..f46721a
--- /dev/null
+++ b/doc/README.davinci.nand_spl
@@ -0,0 +1,141 @@
+With this approach, we don't need the UBL any more on DaVinci boards.
+A "make boardname" will compile a u-boot.ubl, with UBL Header, which is
+needed for the RBL to find the "UBL", which actually is a UBL-compatible
+header, nand spl code and u-boot code.
+
+
+As the RBL uses another read function as the "standard" u-boot,
+we need a command, which switches between this two read/write
+functions, so we can write the UBL header and the spl
+code in a format, which the RBL can read. This is realize
+(at the moment in board specific code) in the u-boot command
+nandrbl
+
+nandrbl without arguments returns actual mode (rbl or uboot).
+with nandrbl mode (mode = "rbl" or "uboot") you can switch
+between the two NAND read/write modes.
+
+
+To set up mkimage you need a config file for mkimage, example:
+board/ait/cam_enc_4xx/ublimage.cfg
+
+For information about the configuration please see:
+doc/README.ublimage
+
+Example for the cam_enc_4xx board:
+On the cam_enc_4xx board we have a NAND flash with blocksize = 0x20000 and
+pagesize = 0x800, so the u-boot.ubl image (which you get with:
+"make cam_enc_4xx") looks like this:
+
+00000000 00 ed ac a1 20 00 00 00 06 00 00 00 05 00 00 00 |.... ...........|
+00000010 00 00 00 00 20 00 00 00 ff ff ff ff ff ff ff ff |.... ...........|
+00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
+*
+00000800 14 00 00 ea 14 f0 9f e5 10 f0 9f e5 0c f0 9f e5 |................|
+00000810 08 f0 9f e5 04 f0 9f e5 00 f0 9f e5 04 f0 1f e5 |................|
+00000820 00 01 00 00 78 56 34 12 78 56 34 12 78 56 34 12 |....xV4.xV4.xV4.|
+[...]
+*
+00001fe0 00 00 00 00 00 00 00 00 ff ff ff ff ff ff ff ff |................|
+00001ff0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
+*
+00003800 14 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
+00003810 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
+00003820 80 01 08 81 e0 01 08 81 40 02 08 81 a0 02 08 81 |........ at .......|
+
+In the first "page" of the image, we have the UBL Header, needed for
+the RBL to find the spl code.
+
+The spl code starts in the second "page" of the image, with a size
+defined by:
+
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
+
+After the spl code, there comes the "real" u-boot code
+@ (6 + 1) * pagesize = 0x3800
+
+------------------------------------------------------------------------
+Setting up spl code:
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER 5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((CONFIG_SYS_NROF_UBL_HEADER * \
+ CONFIG_SYS_NAND_BLOCK_SIZE) + \
+ (CONFIG_SYS_NROF_PAGES_NAND_SPL) * \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+------------------------------------------------------------------------
+
+Burning into NAND:
+
+step 1:
+The RBL searches from Block n ( n = 1..24) on page 0 for valid UBL
+Headers, so you have to burn the UBL header page from the u-boot.ubl
+image to the blocks, you want to have the UBL header.
+!! Don;t forget to switch to rbl nand read/write functions with
+ "nandrbl rbl"
+
+step 2:
+You need to setup in the ublimage.cfg, where the RBL can find the spl
+code, and how big it is.
+
+!! RBL always starts reading from page 0 !!
+
+For the AIT board, we have:
+PAGES 6
+START_BLOCK 5
+
+So we need to copy the spl code to block 5 page 0
+!! Don;t forget to switch to rbl nand read/write functions with
+ "nandrbl rbl"
+
+step 3:
+You need to copy the u-boot image to the block/page
+where the spl code reads it (CONFIG_SYS_NAND_U_BOOT_OFFS)
+!! Don;t forget to switch to rbl nand read/write functions with
+ "nandrbl uboot", which is default.
+
+On the cam_enc_4xx board it is:
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (0xc0000)
+
+-> this results in following NAND usage on the cam_enc_4xx board:
+
+addr
+
+20000 possible UBL Header
+40000 possible UBL Header
+60000 possible UBL Header
+80000 possilbe UBL Header
+a0000 spl code
+c0000 u-boot code
+
+The above steps are executeed through the following environment vars:
+(using 80000 as address for the UBL header)
+
+pagesz=800
+uboot=/tftpboot/cam_enc_4xx/u-boot.ubl
+load=tftp 80000000 ${uboot}
+writeheader nandrbl rbl;nand erase 80000 ${pagesz};nand write 80000000 80000 ${pagesz};nandrbl uboot
+writenand_spl nandrbl rbl;nand erase a0000 3000;nand write 80000800 a0000 3000;nandrbl uboot
+writeuboot nandrbl uboot;nand erase c0000 5d000;nand write 80003800 c0000 5d000
+update=run load writeheader writenand_spl writeuboot
+
+If you do a "run load update" u-boot, spl + ubl header
+are magically updated ;-)
+
+Note:
+- There seem to be a bug in the RBL code (at least on my HW),
+ In the UBL block, I can set the page to values != 0, so it
+ is possible to burn step 1 and step 2 in one step into the
+ flash, but the RBL ignores the page settings, so I have to
+ burn the UBL Header to a page 0 and the spl code to
+ a page 0 ... :-(
+- If we make the nand read/write functions in the RBL equal to
+ the functions in u-boot (as I have no RBL code, it is only
+ possible in u-boot), we could burn the complete image in
+ one step ... that would be nice ...
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
new file mode 100644
index 0000000..6b8cffe
--- /dev/null
+++ b/include/configs/cam_enc_4xx.h
@@ -0,0 +1,452 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS /* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SOC_DM365
+
+#define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
+
+#define CONFIG_HOSTNAME cam_enc_4xx
+
+#define BOARD_LATE_INIT
+#define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
+#define DDR_4BANKS /* 4-bank DDR2 (256MB) */
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Serial Driver info: UART0 for console */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 0x01c20000
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
+#define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_RESET_PHY_R
+
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+
+/* SPI support */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
+#define CONFIG_SF_DEFAULT_SPEED 3000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_CMD_SF
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x0
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* U-Boot memory configuration */
+#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
+#define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
+
+#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/* Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT "2m(bootloader)ro,"
+#endif
+
+#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
+#define PART_REST "-(filesystem)"
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE (0x800)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (0x20000)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POST_MEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
+
+#define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE 12320
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_TEXT_BASE 0x81080000
+#endif
+
+#define CONFIG_SYS_NAND_BASE 0x02000000
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 24, 25, 26, 27, 28, \
+ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE 0x200
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+ CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL (40)
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we can write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER 5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
+
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+
+/*
+ * Post tests for memory testing
+ */
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY
+#define _POST_WORD_ADDR 0x0
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xc0000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
+
+/*
+ * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
+ * done in board_init_f from c code.
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* for UBL header */
+#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
+#define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
+#define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
+#define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
+#define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
+/* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
+/*
+ * POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
+ * interface clk)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
+/* POST DIV 680/2 = 340Mhz -> VPSS */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
+/* POST DIV 680/9 = 75.6 Mhz -> VENC */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
+/*
+ * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
+ * down to 340 Mhz)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
+/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
+/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
+
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
+/* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
+/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
+/* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
+
+/*
+ * READ LATENCY 7 (CL + 2)
+ * CONFIG_PWRDNEN = 1
+ * CONFIG_EXT_STRBEN = 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
+ | DV_DDR_PHY_EXT_STRBEN \
+ | DV_DDR_PHY_PWRDNEN \
+ | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+/*
+ * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
+ * T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
+ * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
+ * T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
+ * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
+ | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
+ | (4 << DV_DDR_SDTMR1_RP_SHIFT) \
+ | (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
+ | (5 << DV_DDR_SDTMR1_WR_SHIFT) \
+ | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
+ | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
+ | (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
+ | (2 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
+ * T_XP = tCKE - 1 = 3 - 2
+ * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
+ * T_XSRD = txsrd - 1 = 200 - 1
+ * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_CKE = tcke - 1 = 3 - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
+ | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_XP_SHIFT) \
+ | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
+ | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+/* PR_OLD_COUNT = 0xfe */
+#define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
+/* refresh rate = 0x768 */
+#define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
+
+#define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
+ | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
+ | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
+ | (5 << DV_DDR_SDCR_CL_SHIFT) \
+ | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
+ | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
+ | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
+ | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
+
+#define CONFIG_SYS_DM36x_AWCCR 0xff
+#define CONFIG_SYS_DM36x_AB1CR 0x40400204
+#define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
+
+/* All Video Inputs */
+#define CONFIG_SYS_DM36x_PINMUX0 0x00000000
+/*
+ * All Video Outputs,
+ * GPIO 86, 87 + 90 0x0000f030
+ */
+#define CONFIG_SYS_DM36x_PINMUX1 0x00530002
+#define CONFIG_SYS_DM36x_PINMUX2 0x00001815
+/*
+ * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+ * GPIO 25 0x60000000
+ */
+#define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
+/*
+ * MMC/SD0 instead of MS, SPI0
+ * GPIO 34 0x0000c000
+ */
+#define CONFIG_SYS_DM36x_PINMUX4 0x00002655
+
+/*
+ * Default environment settings
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
+/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
+#define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
+/*
+ * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
+ * CONFIG_SYS_NAND_PAGE_SIZE))
+ */
+#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
+ "load=tftp ${u_boot_addr_r} ${uboot}\0" \
+ "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
+ "writeheader=nandrbl rbl;nand erase 80000 ${pagesz};" \
+ "nand write ${u_boot_addr_r} 80000 ${pagesz};" \
+ "nandrbl uboot\0" \
+ "writenand_spl=nandrbl rbl;nand erase a0000 3000;" \
+ "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
+ " a0000 3000;nandrbl uboot\0" \
+ "writeuboot=nandrbl uboot;" \
+ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
+ ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
+ " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
+ "update=run load writenand_spl writeuboot\0" \
+ "bootcmd=run bootcmd\0" \
+ "rootpath=/opt/eldk-arm/arm\0" \
+ "\0"
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
+ USBPHY_PHY24MHZ)
+
+#define CONFIG_CMD_USB /* include support for usb cmd */
+#define CONFIG_USB_STORAGE /* MSC class support */
+#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
+
+#undef DAVINCI_DM365EVM
+#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
+#define PINMUX4_USBDRVBUS_BITSET 0x2000
+
+#endif /* __CONFIG_H */
diff --git a/tools/ublimage.h b/tools/ublimage.h
index 93ec8ee..e440625 100644
--- a/tools/ublimage.h
+++ b/tools/ublimage.h
@@ -66,7 +66,7 @@ enum ublimage_fld_types {
#define UBL_IMAGE_SIZE (0x00003800u)
/* one NAND block */
-#define UBL_BLOCK_SIZE 512
+#define UBL_BLOCK_SIZE 2048
/* from sprufg5a.pdf Table 109 */
struct ubl_header {
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 10/11] arm926ejs, davinci: add missing spi defines for dm365
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
---
arch/arm/include/asm/arch-davinci/hardware.h | 2 ++
arch/arm/include/asm/arch-davinci/pll_defs.h | 1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index e4be42a..e62142b 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -111,6 +111,8 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
#define DAVINCI_MMC_SD0_BASE 0x01d11000
#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
+#define DAVINCI_SPI0_BASE 0x01c66000
+#define DAVINCI_SPI1_BASE 0x01c66800
#elif defined(CONFIG_SOC_DM646X)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index 606ed0b..5c30953 100644
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -78,6 +78,7 @@ struct dv_pll_regs {
#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
+#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
unsigned int davinci_clk_get(unsigned int div);
#endif /* _DV_PLL_DEFS_H_ */
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 09/11] arm926ejs, davinci: add cpuinfo for dm365
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
---
Changes for v2:
- rebase to TOT
arch/arm/cpu/arm926ejs/davinci/cpu.c | 27 ++++++++++++++++++++++++-
arch/arm/include/asm/arch-davinci/pll_defs.h | 4 +++
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 02819f6..9ea9785 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -146,13 +146,15 @@ static inline unsigned pll_prediv(volatile void *pllbase)
return 8;
else
return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+ return pll_div(pllbase, PLLC_PREDIV);
#endif
return 1;
}
static inline unsigned pll_postdiv(volatile void *pllbase)
{
-#ifdef CONFIG_SOC_DM355
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
return pll_div(pllbase, PLLC_POSTDIV);
#elif defined(CONFIG_SOC_DM6446)
if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
@@ -171,9 +173,13 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
#endif
/* the PLL might be bypassed */
- if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
+ if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
base /= pll_prediv(pllbase);
+#if defined(CONFIG_SOC_DM365)
+ base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
+#else
base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+#endif
base /= pll_postdiv(pllbase);
}
return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
@@ -184,8 +190,13 @@ int print_cpuinfo(void)
/* REVISIT fetch and display CPU ID and revision information
* too ... that will matter as more revisions appear.
*/
+#if defined(CONFIG_SOC_DM365)
+ printf("Cores: ARM %d MHz",
+ pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+#else
printf("Cores: ARM %d MHz",
pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+#endif
#ifdef DSP_PLLDIV
printf(", DSP %d MHz",
@@ -194,8 +205,13 @@ int print_cpuinfo(void)
printf("\nDDR: %d MHz\n",
/* DDR PHY uses an x2 input clock */
+#if defined(CONFIG_SOC_DM365)
+ pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
+ / 2);
+#else
pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
/ 2);
+#endif
return 0;
}
@@ -205,6 +221,13 @@ unsigned int davinci_arm_clk_get()
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
}
#endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+ return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
#endif /* CONFIG_DISPLAY_CPUINFO */
#endif /* !CONFIG_SOC_DA8XX */
diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index 5d37616..606ed0b 100644
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -76,4 +76,8 @@ struct dv_pll_regs {
#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
+#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
+#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
+
+unsigned int davinci_clk_get(unsigned int div);
#endif /* _DV_PLL_DEFS_H_ */
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 08/11] arm, davinci: add lowlevel function for dm365 soc
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
used for booting (for example) from NAND using spl code.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
---
changes for v2:
- fix bug for dm365 if setup A2CR register
- rebase to TOT:
- rename DM36x_DDR_* to DV_DDR_*
- add support for new SPL framework
arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c | 466 ++++++++++++++++++++
arch/arm/include/asm/arch-davinci/dm365_lowlevel.h | 43 ++
2 files changed, 509 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
create mode 100644 arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
new file mode 100644
index 0000000..d7c6a3e
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
@@ -0,0 +1,466 @@
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ * Actually used for booting from NAND with nand_spl.
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <asm/arch/hardware.h>
+
+void dm365_waitloop(unsigned long loopcnt)
+{
+ unsigned long i;
+
+ for (i = 0; i < loopcnt; i++)
+ asm(" NOP");
+}
+
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
+{
+ unsigned int clksrc = 0x0;
+
+ /* Power up the PLL */
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
+
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
+ setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
+
+ /*
+ * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+ * through MMR
+ */
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
+
+ /* Set PLLEN=0 => PLL BYPASS MODE */
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+ dm365_waitloop(150);
+
+ /* PLLRST=1(reset assert) */
+ setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+ dm365_waitloop(300);
+
+ /*Bring PLL out of Reset*/
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+ /* Program the Multiper and Pre-Divider for PLL1 */
+ writel(pllmult, &dv_pll0_regs->pllm);
+ writel(prediv, &dv_pll0_regs->prediv);
+
+ /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+ PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+ /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+ &dv_pll0_regs->secctl);
+ /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+ writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
+ /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+
+ /* Program the PostDiv for PLL1 */
+ writel(0x8000, &dv_pll0_regs->postdiv);
+
+ /* Post divider setting for PLL1 */
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
+
+ dm365_waitloop(300);
+
+ /* Set the GOSET bit */
+ writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
+
+ dm365_waitloop(300);
+
+ /* Wait for PLL to LOCK */
+ while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
+ == PLL0_LOCK))
+ ;
+
+ /* Enable the PLL Bit of PLLCTL*/
+ setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+ return 0;
+}
+
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
+{
+ unsigned int clksrc = 0x0;
+
+ /* Power up the PLL*/
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
+
+ /*
+ * Select the Clock Mode as Onchip Oscilator or External Clock on
+ * MXI pin
+ * VDB has input on MXI pin
+ */
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
+ setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
+
+ /*
+ * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+ * through MMR
+ */
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
+
+ /* Set PLLEN=0 => PLL BYPASS MODE */
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+ dm365_waitloop(50);
+
+ /* PLLRST=1(reset assert) */
+ setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+ dm365_waitloop(300);
+
+ /* Bring PLL out of Reset */
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+ /* Program the Multiper and Pre-Divider for PLL2 */
+ writel(pllm, &dv_pll1_regs->pllm);
+ writel(prediv, &dv_pll1_regs->prediv);
+
+ writel(0x8000, &dv_pll1_regs->postdiv);
+
+ /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+ PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+ /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+ &dv_pll1_regs->secctl);
+ /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+ writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
+ /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+
+ /* Post divider setting for PLL2 */
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
+
+ /* GoCmd for PostDivider to take effect */
+ writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
+
+ dm365_waitloop(150);
+
+ /* Wait for PLL to LOCK */
+ while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
+ == PLL1_LOCK))
+ ;
+
+ dm365_waitloop(4100);
+
+ /* Enable the PLL2 */
+ setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+ /* do this after PLL's have been set up */
+ writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
+ &dv_sys_module_regs->peri_clkctl);
+
+ return 0;
+}
+
+void dm365_lpc_transition(unsigned char module, unsigned char domain,
+ unsigned char state)
+{
+ /* Wait for any outstanding transition to complete */
+ while ((readl(&dv_psc_regs->ptstat)) & (PSC_GOSTAT << domain))
+ ;
+
+ /* If we are already in that state, just return */
+ if (((readl(&dv_psc_regs->mdstat[module])) & PSC_MD_STATE_MSK)
+ == state)
+ return;
+
+ /* Perform transition */
+ writel(((readl(&dv_psc_regs->mdctl[module])) & (~PSC_MD_STATE_MSK)) |
+ state, &dv_psc_regs->mdctl[module]);
+ setbits_le32(&dv_psc_regs->ptcmd, (PSC_CMD_GO << domain));
+
+ /* Wait for transition to complete */
+ while ((readl(&dv_psc_regs->ptstat)) & (PSC_GOSTAT << domain))
+ ;
+
+ /* Wait and verify the state */
+ while (((readl(&dv_psc_regs->mdstat[module])) & PSC_MD_STATE_MSK)
+ != state)
+ ;
+}
+
+int dm365_ddr_setup(void)
+{
+ dm365_lpc_transition(LPSC_DDR2, 0, PSC_ENABLE);
+ clrbits_le32(&dv_sys_module_regs->vtpiocr,
+ VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
+
+ /* Set bit CLRZ (bit 13) */
+ setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
+
+ /* Check VTP READY Status */
+ while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
+ ;
+
+ /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
+ setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
+
+ /* Set bit LOCK(bit7) */
+ setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
+
+ /*
+ * Powerdown VTP as it is locked (bit 6)
+ * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
+ */
+ setbits_le32(&dv_sys_module_regs->vtpiocr,
+ VPTIO_IOPWRDN | VPTIO_PWRDN);
+
+ /* Wait for calibration to complete */
+ dm365_waitloop(150);
+
+ /* Set the DDR2 to synreset, then enable it again */
+ dm365_lpc_transition(LPSC_DDR2, 0, PSC_SYNCRESET);
+ dm365_lpc_transition(LPSC_DDR2, 0, PSC_ENABLE);
+
+ writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+
+ /* Program SDRAM Bank Config Register */
+ writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
+ &dv_ddr2_regs_ctrl->sdbcr);
+ writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
+ &dv_ddr2_regs_ctrl->sdbcr);
+
+ /* Program SDRAM Timing Control Register1 */
+ writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+ /* Program SDRAM Timing Control Register2 */
+ writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+ writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+ writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
+
+ /* Program SDRAM Refresh Control Register */
+ writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
+
+ dm365_lpc_transition(LPSC_DDR2, 0, PSC_SYNCRESET);
+ dm365_lpc_transition(LPSC_DDR2, 0, PSC_ENABLE);
+
+ return 0;
+}
+
+void dm365_vpss_sync_reset(void)
+{
+ unsigned int PdNum = 0;
+
+ /* VPSS_CLKMD 1:1 */
+ setbits_le32(&dv_sys_module_regs->vpss_clkctl,
+ VPSS_CLK_CTL_VPSS_CLKMD);
+
+ /* LPSC SyncReset DDR Clock Enable */
+ writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
+ PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
+
+ writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+ while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
+ ;
+ while (!((readl(&dv_psc_regs->mdstat[47]) & PSC_MD_STATE_MSK) ==
+ PSC_SYNCRESET))
+ ;
+}
+
+void dm365_por_reset(void)
+{
+ if (readl(&dv_pll0_regs->rstype) & 3)
+ dm365_vpss_sync_reset();
+}
+
+void dm365_psc_init(void)
+{
+ unsigned char i = 0;
+ unsigned char lpsc_start;
+ unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
+ unsigned int PdNum = 0;
+
+ lpscmin = 0;
+ lpscmax = 2;
+
+ for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
+ if (lpscgroup == 0) {
+ lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
+ lpsc_end = 28;
+ } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
+ lpsc_start = 38;
+ lpsc_end = 47;
+ } else {
+ lpsc_start = 50;
+ lpsc_end = 51;
+ }
+
+ /* NEXT=0x3, Enable LPSC's */
+ for (i = lpsc_start; i <= lpsc_end; i++)
+ setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
+
+ /*
+ * Program goctl to start transition sequence for LPSCs
+ * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
+ * Domain 0 Modules
+ */
+ writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+ /*
+ * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
+ */
+ while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
+ == 0))
+ ;
+
+ /* Wait for MODSTAT = ENABLE from LPSC's */
+ for (i = lpsc_start; i <= lpsc_end; i++)
+ while (!((readl(&dv_psc_regs->mdstat[i]) &
+ PSC_MD_STATE_MSK) == 0x3))
+ ;
+ }
+}
+
+static void dm365_emif_init(void)
+{
+ writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
+ writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
+
+ setbits_le32(&davinci_emif_regs->nandfcr, 1);
+
+ writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
+
+ return;
+}
+
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value)
+{
+ clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
+ setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+ return;
+}
+
+#if defined(CONFIG_POST)
+int post_log(char *format, ...)
+{
+ return 0;
+}
+#endif
+
+void dm36x_lowlevel_init(ulong bootflag)
+{
+ /*
+ * copied from arch/arm/cpu/arm926ejs/start.S
+ *
+ * flush v4 I/D caches
+ */
+ asm("mov r0, #0");
+ asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
+ asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ asm("mrc p15, 0, r0, c1, c0, 0");
+ /* clear bits 13, 9:8 (--V- --RS) */
+ asm("bic r0, r0, #0x00002300");
+ /* clear bits 7, 2:0 (B--- -CAM) */
+ asm("bic r0, r0, #0x00000087");
+ /* set bit 2 (A) Align */
+ asm("orr r0, r0, #0x00000002");
+ /* set bit 12 (I) I-Cache */
+ asm("orr r0, r0, #0x00001000");
+ asm("mcr p15, 0, r0, c1, c0, 0");
+
+ /* Mask all interrupts */
+ writel(0x04, &dv_aintc_regs->intctl);
+ writel(0x0, &dv_aintc_regs->eabase);
+ writel(0x0, &dv_aintc_regs->eint0);
+ writel(0x0, &dv_aintc_regs->eint1);
+
+ /* Clear all interrupts */
+ writel(0xffffffff, &dv_aintc_regs->fiq0);
+ writel(0xffffffff, &dv_aintc_regs->fiq1);
+ writel(0xffffffff, &dv_aintc_regs->irq0);
+ writel(0xffffffff, &dv_aintc_regs->irq1);
+
+ /* System PSC setup - enable all */
+ dm365_psc_init();
+
+ /* Setup Pinmux */
+ dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
+ dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
+ dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
+ dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
+ dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
+
+ /* PLL setup */
+ dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
+ CONFIG_SYS_DM36x_PLL1_PREDIV);
+ dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
+ CONFIG_SYS_DM36x_PLL2_PREDIV);
+
+ /* GPIO setup */
+ board_gpio_init();
+
+ NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+ /*
+ * Fix Power and Emulation Management Register
+ * see sprufh2.pdf page 38 Table 22
+ */
+ writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
+ puts("ddr init\n");
+ dm365_ddr_setup();
+
+ puts("emif init\n");
+ dm365_emif_init();
+
+#if defined(CONFIG_POST)
+ /*
+ * Do memory tests, calls arch_memory_failure_handle()
+ * if error detected.
+ */
+ memory_post_test(0);
+#endif
+}
diff --git a/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h b/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
new file mode 100644
index 0000000..078966e
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
@@ -0,0 +1,43 @@
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __DM365_LOWLEVEL_H
+#define __DM365_LOWLEVEL_H
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+void dm365_waitloop(unsigned long loopcnt);
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
+void dm365_lpc_transition(unsigned char module, unsigned char domain,
+ unsigned char state);
+int dm365_ddr_setup(void);
+void dm365_por_reset(void);
+void dm365_psc_init(void);
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value);
+void dm36x_lowlevel_init(ulong bootflag);
+
+#endif /* #ifndef __DM365_LOWLEVEL_H */
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 07/11] arm, davinci: add header files for dm365
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
---
changes for v2:
- rebase to TOT
- add defines for timer 3 and 4
- delete "struct dv_timer_regs" as it is now "davinci_timer"
arch/arm/include/asm/arch-davinci/aintc_defs.h | 50 +++++++++
arch/arm/include/asm/arch-davinci/hardware.h | 13 +++
arch/arm/include/asm/arch-davinci/pll_defs.h | 79 ++++++++++++++
arch/arm/include/asm/arch-davinci/psc_defs.h | 129 +++++++++++++++++++++++
arch/arm/include/asm/arch-davinci/syscfg_defs.h | 66 ++++++++++++
5 files changed, 337 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-davinci/aintc_defs.h
create mode 100644 arch/arm/include/asm/arch-davinci/pll_defs.h
create mode 100644 arch/arm/include/asm/arch-davinci/psc_defs.h
create mode 100644 arch/arm/include/asm/arch-davinci/syscfg_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h
new file mode 100644
index 0000000..8f37053
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/aintc_defs.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_AINTC_DEFS_H_
+#define _DV_AINTC_DEFS_H_
+
+struct dv_aintc_regs {
+ unsigned int fiq0; /* 0x00 */
+ unsigned int fiq1; /* 0x04 */
+ unsigned int irq0; /* 0x08 */
+ unsigned int irq1; /* 0x0c */
+ unsigned int fiqentry; /* 0x10 */
+ unsigned int irqentry; /* 0x14 */
+ unsigned int eint0; /* 0x18 */
+ unsigned int eint1; /* 0x1c */
+ unsigned int intctl; /* 0x20 */
+ unsigned int eabase; /* 0x24 */
+ unsigned char rsvd0[8]; /* 0x28 */
+ unsigned int intpri0; /* 0x30 */
+ unsigned int intpri1; /* 0x34 */
+ unsigned int intpri2; /* 0x38 */
+ unsigned int intpri3; /* 0x3c */
+ unsigned int intpri4; /* 0x40 */
+ unsigned int intpri5; /* 0x44 */
+ unsigned int intpri6; /* 0x48 */
+ unsigned int intpri7; /* 0x4c */
+};
+
+#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
+
+#endif /* _DV_AINTC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index b6a3209..e4be42a 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -56,6 +56,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
#define DAVINCI_UART0_BASE (0x01c20000)
#define DAVINCI_UART1_BASE (0x01c20400)
+#define DAVINCI_TIMER3_BASE (0x01c20800)
#define DAVINCI_I2C_BASE (0x01c21000)
#define DAVINCI_TIMER0_BASE (0x01c21400)
#define DAVINCI_TIMER1_BASE (0x01c21800)
@@ -63,6 +64,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_PWM0_BASE (0x01c22000)
#define DAVINCI_PWM1_BASE (0x01c22400)
#define DAVINCI_PWM2_BASE (0x01c22800)
+#define DAVINCI_TIMER4_BASE (0x01c23800)
#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
@@ -108,6 +110,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_MMC_SD1_BASE 0x01d00000
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
#define DAVINCI_MMC_SD0_BASE 0x01d11000
+#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
#elif defined(CONFIG_SOC_DM646X)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
@@ -538,4 +541,14 @@ static inline int get_async3_src(void)
#endif /* CONFIG_SOC_DA8XX */
+#if defined(CONFIG_SOC_DM365)
+#include <asm/arch/aintc_defs.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pll_defs.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/syscfg_defs.h>
+#include <asm/arch/timer_defs.h>
+#endif
#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
new file mode 100644
index 0000000..5d37616
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_PLL_DEFS_H_
+#define _DV_PLL_DEFS_H_
+
+struct dv_pll_regs {
+ unsigned int pid; /* 0x00 */
+ unsigned char rsvd0[224]; /* 0x04 */
+ unsigned int rstype; /* 0xe4 */
+ unsigned char rsvd1[24]; /* 0xe8 */
+ unsigned int pllctl; /* 0x100 */
+ unsigned char rsvd2[4]; /* 0x104 */
+ unsigned int secctl; /* 0x108 */
+ unsigned int rv; /* 0x10c */
+ unsigned int pllm; /* 0x110 */
+ unsigned int prediv; /* 0x114 */
+ unsigned int plldiv1; /* 0x118 */
+ unsigned int plldiv2; /* 0x11c */
+ unsigned int plldiv3; /* 0x120 */
+ unsigned int oscdiv1; /* 0x124 */
+ unsigned int postdiv; /* 0x128 */
+ unsigned int bpdiv; /* 0x12c */
+ unsigned char rsvd5[8]; /* 0x130 */
+ unsigned int pllcmd; /* 0x138 */
+ unsigned int pllstat; /* 0x13c */
+ unsigned int alnctl; /* 0x140 */
+ unsigned int dchange; /* 0x144 */
+ unsigned int cken; /* 0x148 */
+ unsigned int ckstat; /* 0x14c */
+ unsigned int systat; /* 0x150 */
+ unsigned char rsvd6[12]; /* 0x154 */
+ unsigned int plldiv4; /* 0x160 */
+ unsigned int plldiv5; /* 0x164 */
+ unsigned int plldiv6; /* 0x168 */
+ unsigned int plldiv7; /* 0x16C */
+ unsigned int plldiv8; /* 0x170 */
+ unsigned int plldiv9; /* 0x174 */
+};
+
+#define PLLCTL_PLLEN (1 << 0)
+#define PLLCTL_PLLPWRDN (1 << 1)
+#define PLLCTL_PLLRST (1 << 3)
+#define PLLCTL_PLLENSRC (1 << 5)
+#define PLLCTL_RES_9 (1 << 8)
+
+#define PLLSECCTL_TINITZ (1 << 16)
+#define PLLSECCTL_TENABLE (1 << 17)
+#define PLLSECCTL_TENABLEDIV (1 << 18)
+#define PLLSECCTL_STOPMODE (1 << 22)
+
+#define PLLCMD_GOSET (1 << 0)
+
+#define PLL0_LOCK 0x07000000
+#define PLL1_LOCK 0x07000000
+
+#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
+
+#endif /* _DV_PLL_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/psc_defs.h b/arch/arm/include/asm/arch-davinci/psc_defs.h
new file mode 100644
index 0000000..4a16377
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/psc_defs.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_PSC_DEFS_H_
+#define _DV_PSC_DEFS_H_
+
+/*
+ * Power/Sleep Ctrl Register structure
+ * See sprufb3.pdf, Chapter 7
+ */
+struct dv_psc_regs {
+ unsigned int pid; /* 0x000 */
+ unsigned char rsvd0[16]; /* 0x004 */
+ unsigned char rsvd1[4]; /* 0x014 */
+ unsigned int inteval; /* 0x018 */
+ unsigned char rsvd2[36]; /* 0x01C */
+ unsigned int merrpr0; /* 0x040 */
+ unsigned int merrpr1; /* 0x044 */
+ unsigned char rsvd3[8]; /* 0x048 */
+ unsigned int merrcr0; /* 0x050 */
+ unsigned int merrcr1; /* 0x054 */
+ unsigned char rsvd4[8]; /* 0x058 */
+ unsigned int perrpr; /* 0x060 */
+ unsigned char rsvd5[4]; /* 0x064 */
+ unsigned int perrcr; /* 0x068 */
+ unsigned char rsvd6[4]; /* 0x06C */
+ unsigned int epcpr; /* 0x070 */
+ unsigned char rsvd7[4]; /* 0x074 */
+ unsigned int epccr; /* 0x078 */
+ unsigned char rsvd8[144]; /* 0x07C */
+ unsigned char rsvd9[20]; /* 0x10C */
+ unsigned int ptcmd; /* 0x120 */
+ unsigned char rsvd10[4]; /* 0x124 */
+ unsigned int ptstat; /* 0x128 */
+ unsigned char rsvd11[212]; /* 0x12C */
+ unsigned int pdstat0; /* 0x200 */
+ unsigned int pdstat1; /* 0x204 */
+ unsigned char rsvd12[248]; /* 0x208 */
+ unsigned int pdctl0; /* 0x300 */
+ unsigned int pdctl1; /* 0x304 */
+ unsigned char rsvd13[536]; /* 0x308 */
+ unsigned int mckout0; /* 0x520 */
+ unsigned int mckout1; /* 0x524 */
+ unsigned char rsvd14[728]; /* 0x528 */
+ unsigned int mdstat[52]; /* 0x800 */
+ unsigned char rsvd15[304]; /* 0x8D0 */
+ unsigned int mdctl[52]; /* 0xA00 */
+};
+
+/* PSC constants */
+#define LPSC_TPCC (0)
+#define LPSC_TPTC0 (1)
+#define LPSC_TPTC1 (2)
+#define LPSC_TPTC2 (3)
+#define LPSC_TPTC3 (4)
+#define LPSC_TIMER3 (5)
+#define LPSC_SPI1 (6)
+#define LPSC_MMC_SD1 (7)
+#define LPSC_ASP1 (8)
+#define LPSC_USB (9)
+#define LPSC_PWM3 (10)
+#define LPSC_SPI2 (11)
+#define LPSC_RTO (12)
+#define LPSC_DDR2 (13)
+#define LPSC_AEMIF (14)
+#define LPSC_MMC_SD0 (15)
+#define LPSC_MEMSTK (16)
+#define TIMER4 (17)
+#define LPSC_I2C (18)
+#define LPSC_UART0 (19)
+#define LPSC_UART1 (20)
+#define LPSC_UHPI (21)
+#define LPSC_SPIO (22)
+#define LPSC_PWM0 (23)
+#define LPSC_PWM1 (24)
+#define LPSC_PWM2 (25)
+#define LPSC_GPIO (26)
+#define LPSC_TIMER0 (27)
+#define LPSC_TIMER1 (28)
+#define LPSC_TIMER2 (29)
+#define LPSC_SYSMOD (30)
+#define LPSC_ARM (31)
+#define LPSC_SPI3 (38)
+#define LPSC_SPI4 (39)
+#define LPSC_CPGMAC (40)
+#define LPSC_RTC (41)
+#define LPSC_KEYSCAN (42)
+#define LPSC_ADC (43)
+#define LPSC_VOICECODEC (44)
+#define LPSC_IMCOP (50)
+#define LPSC_KALEIDO (51)
+
+
+#define EMURSTIE_MASK (0x00000200)
+
+#define PD0 (0)
+
+#define PSC_ENABLE (0x3)
+#define PSC_DISABLE (0x2)
+#define PSC_SYNCRESET (0x1)
+#define PSC_SWRSTDISABLE (0x0)
+
+#define PSC_GOSTAT (1 << 0)
+#define PSC_MD_STATE_MSK (0x1f)
+
+#define PSC_CMD_GO (1 << 0)
+
+#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
+
+#endif /* _DV_PSC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/syscfg_defs.h b/arch/arm/include/asm/arch-davinci/syscfg_defs.h
new file mode 100644
index 0000000..05af020
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/syscfg_defs.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_SYSCFG_DEFS_H_
+#define _DV_SYSCFG_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+/* System Control Module register structure for DM365 */
+struct dv_sys_module_regs {
+ unsigned int pinmux[5]; /* 0x00 */
+ unsigned int bootcfg; /* 0x14 */
+ unsigned int arm_intmux; /* 0x18 */
+ unsigned int edma_evtmux; /* 0x1C */
+ unsigned int ddr_slew; /* 0x20 */
+ unsigned int clkout; /* 0x24 */
+ unsigned int device_id; /* 0x28 */
+ unsigned int vdac_config; /* 0x2C */
+ unsigned int timer64_ctl; /* 0x30 */
+ unsigned int usbbphy_ctl; /* 0x34 */
+ unsigned int misc; /* 0x38 */
+ unsigned int mstpri[2]; /* 0x3C */
+ unsigned int vpss_clkctl; /* 0x44 */
+ unsigned int peri_clkctl; /* 0x48 */
+ unsigned int deepsleep; /* 0x4C */
+ unsigned int dft_enable; /* 0x50 */
+ unsigned int debounce[8]; /* 0x54 */
+ unsigned int vtpiocr; /* 0x74 */
+ unsigned int pupdctl0; /* 0x78 */
+ unsigned int pupdctl1; /* 0x7C */
+ unsigned int hdimcopbt; /* 0x80 */
+ unsigned int pll0_config; /* 0x84 */
+ unsigned int pll1_config; /* 0x88 */
+};
+
+#define VPTIO_RDY (1 << 15)
+#define VPTIO_IOPWRDN (1 << 14)
+#define VPTIO_CLRZ (1 << 13)
+#define VPTIO_LOCK (1 << 7)
+#define VPTIO_PWRDN (1 << 6)
+
+#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
+
+#define dv_sys_module_regs \
+ ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
+
+#endif /* !CONFIG_SOC_DA8XX */
+#endif /* _DV_SYSCFG_DEFS_H_ */
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 06/11] spl, nand: add 4bit HW ecc oob first nand_read_page function
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
similiar to commit dc7cd8e59ba077f3b4c1a4557c9cd86a31b9ab1f, only
adapted for the new spl framework.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
---
changes for v2:
- add comment from Scott Wood:
as BSS is cleared, no need for intializing vars with 0
remove this.
changes for v3:
- add comment from Scoot Wood and Tom Rini
- rename CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST to
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
- add dokumentation in README
changes for v4:
- added Acked-by: Tom Rini <trini@ti.com>
README | 5 ++++
drivers/mtd/nand/nand_spl_simple.c | 43 +++++++++++++++++++++++++++++++++++-
2 files changed, 47 insertions(+), 1 deletions(-)
diff --git a/README b/README
index 65875c1..fa28a3c 100644
--- a/README
+++ b/README
@@ -3179,6 +3179,11 @@ Low Level (hardware related) configuration options:
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
+- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+ define this, if you want to read first the oob data
+ and then the data. This is used for example on
+ davinci plattforms.
+
- CONFIG_USE_ARCH_MEMCPY
CONFIG_USE_ARCH_MEMSET
If these options are used a optimized version of memcpy/memset will
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index 71491d4..e5003e6 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -140,6 +140,47 @@ static int nand_is_bad_block(int block)
return 0;
}
+#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
+static int nand_read_page(int block, int page, uchar *dst)
+{
+ struct nand_chip *this = mtd.priv;
+ u_char *ecc_calc;
+ u_char *ecc_code;
+ u_char *oob_data;
+ int i;
+ int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+ int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
+ uint8_t *p = dst;
+ int stat;
+
+ /*
+ * No malloc available for now, just use some temporary locations
+ * in SDRAM
+ */
+ ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
+ ecc_code = ecc_calc + 0x100;
+ oob_data = ecc_calc + 0x200;
+
+ nand_command(block, page, 0, NAND_CMD_READOOB);
+ this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+ nand_command(block, page, 0, NAND_CMD_READ0);
+
+ /* Pick the ECC bytes out of the oob data */
+ for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
+ ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ this->ecc.hwctl(&mtd, NAND_ECC_READ);
+ this->read_buf(&mtd, p, eccsize);
+ this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+ stat = this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ }
+
+ return 0;
+}
+#else
static int nand_read_page(int block, int page, void *dst)
{
struct nand_chip *this = mtd.priv;
@@ -186,6 +227,7 @@ static int nand_read_page(int block, int page, void *dst)
return 0;
}
+#endif
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
@@ -230,7 +272,6 @@ void nand_init(void)
mtd.priv = &nand_chip;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
- nand_chip.options = 0;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 05/11] arm, davinci: add support for new spl framework
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
---
Makefile | 8 +++-
arch/arm/cpu/arm926ejs/davinci/Makefile | 8 ++++
arch/arm/cpu/arm926ejs/davinci/spl.c | 63 +++++++++++++++++++++++++++++
arch/arm/cpu/arm926ejs/davinci/spl_nand.c | 57 ++++++++++++++++++++++++++
arch/arm/cpu/arm926ejs/start.S | 25 +++++++++++-
5 files changed, 158 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_nand.c
diff --git a/Makefile b/Makefile
index 400ef0b..41e98f1 100644
--- a/Makefile
+++ b/Makefile
@@ -401,9 +401,13 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
-$(obj)u-boot.ubl: $(obj)u-boot-nand.bin
+$(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
- -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+ -e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
+ rm $(obj)u-boot-ubl.bin
+ rm $(obj)spl/u-boot-spl-pad.bin
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index 0310957..d9e71bc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -35,6 +35,14 @@ COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+COBJS-y += dm365_lowlevel.o
+ifdef CONFIG_SPL_NAND_SUPPORT
+COBJS-y += spl_nand.o
+endif
+endif
+
SOBJS = reset.o
ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c
new file mode 100644
index 0000000..d9b9398
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <ns16550.h>
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
+
+ NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
+}
+
+inline void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
+}
+
+void board_init_f(ulong dummy)
+{
+ dm36x_lowlevel_init(0);
+ relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+
+ nand_init();
+ puts("Nand boot...\n");
+ nand_boot();
+}
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl_nand.c b/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
new file mode 100644
index 0000000..efc0521
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
+void nand_boot(void)
+{
+ int ret;
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ /*
+ * Load U-Boot image from NAND into RAM
+ */
+ ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+
+#ifdef CONFIG_NAND_ENV_DST
+ ret = nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ ret = nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+
+ /*
+ * Jump to U-Boot image
+ */
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ (*uboot)();
+}
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 86a0dc2..339c5ed 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -126,7 +126,15 @@ _fiq:
.globl _TEXT_BASE
_TEXT_BASE:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
.word CONFIG_SYS_TEXT_BASE
+#else
+#ifdef CONFIG_SPL_BUILD
+ .word CONFIG_SPL_TEXT_BASE
+#else
+ .word CONFIG_SYS_TEXT_BASE
+#endif
+#endif
/*
* These are defined in the board-specific linker script.
@@ -192,7 +200,15 @@ reset:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
+ ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#else
+#ifdef CONFIG_SPL_BUILD
+ ldr sp, =(CONFIG_SPL_STACK)
+#else
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
@@ -217,6 +233,7 @@ stack_setup:
mov sp, r4
adr r0, _start
+ sub r9, r6, r0 /* r9 <- relocation offset */
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
@@ -271,12 +288,17 @@ fixnext:
#endif
clear_bss:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
+ /* No relocation for SPL */
+ ldr r0, =__bss_start
+ ldr r1, =__bss_end__
+#else
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
+#endif
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
@@ -284,6 +306,7 @@ clbss_l:str r2, [r0] /* clear loop... */
cmp r0, r1
bne clbss_l
+#ifndef CONFIG_SPL_BUILD
bl coloured_LED_init
bl red_led_on
#endif
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 04/11] spl: add option for adding post memory test to the SPL framework
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Sergei Shtylyov <sshtylyov@mvista.com>
---
changes for v4:
- add comment from Sergei Shtylyov:
- remove Leftmost open parent in dox/README.SPL
doc/README.SPL | 1 +
spl/Makefile | 1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/doc/README.SPL b/doc/README.SPL
index d53ef9c..8a5f7e4 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -62,3 +62,4 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
+CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
diff --git a/spl/Makefile b/spl/Makefile
index 91dd11a..79d9f5c 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -54,6 +54,7 @@ LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
+LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
ifeq ($(SOC),omap3)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 03/11] net, davinci_emac: make clock divider in MDIO control register configurable
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
Define CONFIG_SYS_EMAC_TI_CLKDIV for setting the clkdiv value
in the MDIO control register.
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Sandeep Paulraj <s-paulraj@ti.com>
cc: Wolfgang Denk <wd@denx.de>
---
drivers/net/davinci_emac.c | 9 +++++++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index a8905b8..299f1e1 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -53,6 +53,11 @@ unsigned int emac_dbg = 0;
#define emac_gigabit_enable() /* no gigabit to enable */
#endif
+#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
+#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
+ EMAC_MDIO_CLOCK_FREQ) - 1)
+#endif
+
static void davinci_eth_mdio_enable(void);
static int gen_init_phy(int phy_addr);
@@ -126,7 +131,7 @@ static void davinci_eth_mdio_enable(void)
{
u_int32_t clkdiv;
- clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+ clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) |
MDIO_CONTROL_ENABLE |
@@ -427,7 +432,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
#endif
/* Init MDIO & get link state */
- clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+ clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
&adap_mdio->CONTROL);
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 02/11] arm, usb, davinci: make USBPHY_CTL register configurable
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
Define CONFIG_DV_USBPHY_CTL for setting the USB PHY control
register.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
cc: Sandeep Paulraj <s-paulraj@ti.com>
cc: Remy Bohmer <linux@bohmer.net>
---
drivers/usb/musb/davinci.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 27dc4bc..c17c867 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -26,6 +26,10 @@
#include "davinci.h"
#include <asm/arch/hardware.h>
+#if !defined(CONFIG_DV_USBPHY_CTL)
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN)
+#endif
+
/* MUSB platform configuration */
struct musb_config musb_cfg = {
.regs = (struct musb_regs *)MENTOR_USB0_BASE,
@@ -50,7 +54,7 @@ static u8 phy_on(void)
writel(USBPHY_PHY24MHZ | USBPHY_SESNDEN |
USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
#else
- writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
+ writel(CONFIG_DV_USBPHY_CTL, USBPHY_CTL_PADDR);
#endif
timeout = musb_cfg.timeout;
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 01/11] usb, davinci: add enable_vbus() weak function
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319441913-27233-1-git-send-email-hs@denx.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
changes for v4:
- patch is new since v4, as Igor Grinberg suggested.
drivers/usb/musb/davinci.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index f56f2df..27dc4bc 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -78,6 +78,18 @@ static void phy_off(void)
writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, USBPHY_CTL_PADDR);
}
+#ifndef DAVINCI_DM365EVM
+__attribute__((weak))
+void enable_vbus(void)
+{
+ /*
+ * nothing to do, vbus is handled through the cpu.
+ * Define this function in board code, if it is
+ * different on your board.
+ */
+}
+#endif
+
/*
* This function performs Davinci platform specific initialization for usb0.
*/
--
1.7.6.4
^ permalink raw reply related
* [U-Boot] [PATCH v4 00/11] arm, davinci: add support for dm368 based cam_enc_4xx board
From: Heiko Schocher @ 2011-10-24 7:38 UTC (permalink / raw)
To: u-boot
This is a repost of the cam_enc_4xx board support patches from
http://lists.denx.de/pipermail/u-boot/2011-October/106336.html
changes for v4:
- add comment from Sergei Shtylyov:
- remove Leftmost open parent in dox/README.SPL
- add comments from Igor Grinberg
- remove in board/ait/cam_enc_4xx/Makefile
unnecessary targets clean, distcelan
- use CONFIG_MACH_TYPE option
- removed some unnecessary brackets
- new patch: add a weak enable_vbus() in
drivers/usb/musb/davinci.c
-> new patch in this series:
"usb, davinci: add enable_vbus() weak function"
- add a comment to an "#else" to make it clearer
to which "#if" it belongs
- fix ALL to ALL-y in board config.mk, and add this only
if CONFIG_SPL_BUILD is not set.
Patches are checkpatch clean
"./MAKEALL -a arm --soc davinci" compiles clean
Also needed patches:
arm, arm926: fix missing symbols in NAND_SPL mode
http://patchwork.ozlabs.org/patch/104942/
arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD
http://patchwork.ozlabs.org/patch/106983/
already in u-boot-arm.git:
arm, logbuffer: make it compileclean
http://lists.denx.de/pipermail/u-boot/2011-October/104962.html
cosmetic, post: Codingstyle cleanup
http://lists.denx.de/pipermail/u-boot/2011-October/104963.html
arm, post: add missing post_time_ms for arm
http://lists.denx.de/pipermail/u-boot/2011-September/101415.html
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Heiko Schocher (11):
usb, davinci: add enable_vbus() weak function
arm, usb, davinci: make USBPHY_CTL register configurable
net, davinci_emac: make clock divider in MDIO control register
configurable
spl: add option for adding post memory test to the SPL framework
arm, davinci: add support for new spl framework
spl, nand: add 4bit HW ecc oob first nand_read_page function
arm, davinci: add header files for dm365
arm, davinci: add lowlevel function for dm365 soc
arm926ejs, davinci: add cpuinfo for dm365
arm926ejs, davinci: add missing spi defines for dm365
arm, davinci: add cam_enc_4xx support
MAINTAINERS | 1 +
Makefile | 8 +-
README | 5 +
arch/arm/cpu/arm926ejs/davinci/Makefile | 8 +
arch/arm/cpu/arm926ejs/davinci/cpu.c | 27 +-
arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c | 466 ++++++++++++++++++++
arch/arm/cpu/arm926ejs/davinci/spl.c | 63 +++
arch/arm/cpu/arm926ejs/davinci/spl_nand.c | 57 +++
arch/arm/cpu/arm926ejs/start.S | 25 +-
arch/arm/include/asm/arch-davinci/aintc_defs.h | 50 +++
arch/arm/include/asm/arch-davinci/dm365_lowlevel.h | 43 ++
arch/arm/include/asm/arch-davinci/hardware.h | 15 +
arch/arm/include/asm/arch-davinci/pll_defs.h | 84 ++++
arch/arm/include/asm/arch-davinci/psc_defs.h | 129 ++++++
arch/arm/include/asm/arch-davinci/syscfg_defs.h | 66 +++
board/ait/cam_enc_4xx/Makefile | 46 ++
board/ait/cam_enc_4xx/cam_enc_4xx.c | 446 +++++++++++++++++++
board/ait/cam_enc_4xx/config.mk | 15 +
board/ait/cam_enc_4xx/u-boot-spl.lds | 73 +++
board/ait/cam_enc_4xx/ublimage.cfg | 48 ++
boards.cfg | 1 +
doc/README.SPL | 1 +
doc/README.davinci.nand_spl | 141 ++++++
drivers/mtd/nand/nand_spl_simple.c | 43 ++-
drivers/net/davinci_emac.c | 9 +-
drivers/usb/musb/davinci.c | 18 +-
include/configs/cam_enc_4xx.h | 452 +++++++++++++++++++
spl/Makefile | 1 +
tools/ublimage.h | 2 +-
29 files changed, 2333 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_nand.c
create mode 100644 arch/arm/include/asm/arch-davinci/aintc_defs.h
create mode 100644 arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
create mode 100644 arch/arm/include/asm/arch-davinci/pll_defs.h
create mode 100644 arch/arm/include/asm/arch-davinci/psc_defs.h
create mode 100644 arch/arm/include/asm/arch-davinci/syscfg_defs.h
create mode 100644 board/ait/cam_enc_4xx/Makefile
create mode 100644 board/ait/cam_enc_4xx/cam_enc_4xx.c
create mode 100644 board/ait/cam_enc_4xx/config.mk
create mode 100644 board/ait/cam_enc_4xx/u-boot-spl.lds
create mode 100644 board/ait/cam_enc_4xx/ublimage.cfg
create mode 100644 doc/README.davinci.nand_spl
create mode 100644 include/configs/cam_enc_4xx.h
--
1.7.6.4
^ permalink raw reply
* [PATCH] spi/pl022: Enable clock in probe an use runtime_idle
From: Ulf Hansson @ 2011-10-24 7:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdY2Csh58QbtnfYikr-VtYR_wDRfC2_X_+wR3OPhgTBE3w@mail.gmail.com>
Linus Walleij wrote:
> On Fri, Oct 21, 2011 at 4:08 PM, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
>
>> Since we are always runtime resumed when leaving probe
>> the clock must be enabled. To accomplish that we are able
>> to be runtime suspended after probe in the case when no
>> request is going to be recieved, a runtime_idle function
>> has been implemented.
>>
>> Change-Id: I6cb86f2cad30ecaab16f512daf4674b039b18213
>> Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com>
>> Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/34447
>
> Skip the gerrit weirdo stuff.
Sorry, for not cleaning up the commit msg, my bad. I fix.
>
> Notice that this patch cannot be merged until Russell's
> AMBA PM patches are merged, so put this in Russell's
> patch tracker so he can put it on his AMBA PM branch.
>
I will do!
> But looks correct.
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
>
^ permalink raw reply
* Re: [PATCH] spi/pl022: Enable clock in probe an use runtime_idle
From: Ulf Hansson @ 2011-10-24 7:38 UTC (permalink / raw)
To: Linus Walleij
Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
Lee Jones,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Russell King - ARM Linux
In-Reply-To: <CACRpkdY2Csh58QbtnfYikr-VtYR_wDRfC2_X_+wR3OPhgTBE3w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Linus Walleij wrote:
> On Fri, Oct 21, 2011 at 4:08 PM, Ulf Hansson <ulf.hansson-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org> wrote:
>
>> Since we are always runtime resumed when leaving probe
>> the clock must be enabled. To accomplish that we are able
>> to be runtime suspended after probe in the case when no
>> request is going to be recieved, a runtime_idle function
>> has been implemented.
>>
>> Change-Id: I6cb86f2cad30ecaab16f512daf4674b039b18213
>> Signed-off-by: Ulf Hansson <ulf.hansson-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
>> Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/34447
>
> Skip the gerrit weirdo stuff.
Sorry, for not cleaning up the commit msg, my bad. I fix.
>
> Notice that this patch cannot be merged until Russell's
> AMBA PM patches are merged, so put this in Russell's
> patch tracker so he can put it on his AMBA PM branch.
>
I will do!
> But looks correct.
> Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> Yours,
> Linus Walleij
>
------------------------------------------------------------------------------
The demand for IT networking professionals continues to grow, and the
demand for specialized networking skills is growing even more rapidly.
Take a complimentary Learning@Cisco Self-Assessment and learn
about Cisco certifications, training, and career opportunities.
http://p.sf.net/sfu/cisco-dev2dev
^ permalink raw reply
* Re: [PATCH] drivers: create a pin control subsystem v8
From: Grant Likely @ 2011-10-24 7:36 UTC (permalink / raw)
To: Linus Walleij
Cc: Mike Frysinger, Linus Walleij, Stephen Warren, Sascha Hauer,
Barry Song, linux-kernel, Joe Perches, Russell King, Linaro Dev,
Lee Jones, David Brown, linux-arm-kernel, Stijn Devriendt
In-Reply-To: <CACRpkdatiBathcoo2VjKs9jHJiKC5trDCJ0bePX1q6KbrYRN-g@mail.gmail.com>
On Mon, Oct 24, 2011 at 09:26:38AM +0200, Linus Walleij wrote:
> On Sat, Oct 22, 2011 at 7:44 PM, Mike Frysinger <vapier.adi@gmail.com> wrote:
> > On Tue, Oct 4, 2011 at 16:35, Grant Likely wrote:
> >> On Sat, Oct 01, 2011 at 12:39:21PM +0200, Linus Walleij wrote:
> >>> 2011/9/30 Grant Likely:
> >>> > I'm not convinced that the sysfs approach is
> >>> > actually the right interface here (I'm certainly not a fan of the gpio
> >>> > sysfs i/f), and I'd rather not be putting in unneeded stuff until the
> >>> > userspace i/f is hammered out.
> >>>
> >>> Actually, thinking about it I cannot see what would be wrong
> >>> with /dev/gpio0 & friends in the first place.
> >>>
> >>> Using sysfs as swiss army knife for custom I/O does not
> >>> seem like it would be long-term viable so thanks for this
> >>> observation, and I think we need /dev/gpio* put on some
> >>> mental roadmap somewhere.
> >>
> >> Agreed. I don't want to be in the situation we are now with GPIO,
> >> where every time I look at the sysfs interface I shudder.
> >
> > the problem with that is it doesn't scale. if i have a device with
> > over 150 GPIOs on the SoC itself (obviously GPIO expanders can make
> > that much bigger), i don't want to see 150+ device nodes in /dev/.
> > that's a pretty big waste. sysfs only allocates/frees resources when
> > userspace actually wants to utilize a GPIO.
>
> I was more thinking along the lines of one device per GPIO controller,
> then you ioctl() to ask /dev/gpio0 how many pins it has or so.
And there is also the question of whether it is even a good idea to
export pinctrl manipulation to userspace.
g.
^ permalink raw reply
* [PATCH] drivers: create a pin control subsystem v8
From: Grant Likely @ 2011-10-24 7:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdatiBathcoo2VjKs9jHJiKC5trDCJ0bePX1q6KbrYRN-g@mail.gmail.com>
On Mon, Oct 24, 2011 at 09:26:38AM +0200, Linus Walleij wrote:
> On Sat, Oct 22, 2011 at 7:44 PM, Mike Frysinger <vapier.adi@gmail.com> wrote:
> > On Tue, Oct 4, 2011 at 16:35, Grant Likely wrote:
> >> On Sat, Oct 01, 2011 at 12:39:21PM +0200, Linus Walleij wrote:
> >>> 2011/9/30 Grant Likely:
> >>> >?I'm not convinced that the sysfs approach is
> >>> > actually the right interface here (I'm certainly not a fan of the gpio
> >>> > sysfs i/f), and I'd rather not be putting in unneeded stuff until the
> >>> > userspace i/f is hammered out.
> >>>
> >>> Actually, thinking about it I cannot see what would be wrong
> >>> with /dev/gpio0 & friends in the first place.
> >>>
> >>> Using sysfs as swiss army knife for custom I/O does not
> >>> seem like it would be long-term viable so thanks for this
> >>> observation, and I think we need /dev/gpio* put on some
> >>> mental roadmap somewhere.
> >>
> >> Agreed. ?I don't want to be in the situation we are now with GPIO,
> >> where every time I look at the sysfs interface I shudder.
> >
> > the problem with that is it doesn't scale. ?if i have a device with
> > over 150 GPIOs on the SoC itself (obviously GPIO expanders can make
> > that much bigger), i don't want to see 150+ device nodes in /dev/.
> > that's a pretty big waste. ?sysfs only allocates/frees resources when
> > userspace actually wants to utilize a GPIO.
>
> I was more thinking along the lines of one device per GPIO controller,
> then you ioctl() to ask /dev/gpio0 how many pins it has or so.
And there is also the question of whether it is even a good idea to
export pinctrl manipulation to userspace.
g.
^ permalink raw reply
* Re: cifs and win2k8
From: sean finney @ 2011-10-24 7:35 UTC (permalink / raw)
To: Jeff Layton, Pavel Shilovsky
Cc: Terrence Shipclark, linux-cifs-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20111023065534.566a0aad-4QP7MXygkU+dMjc06nkz3ljfA9RmPOcC@public.gmane.org>
Hi Jeff, Pavel,
On Sun, Oct 23, 2011 at 06:55:34AM -0400, Jeff Layton wrote:
> 3.0 got a patchset to allow superblocks to be shared, but that
> regressed the above use case (mounting a directory that you have access
> to but not the stuff below it).
I also seem to recall there being a problem with the request on the target
directory (existing behavior, not a regression), that it used the SMB
QueryFileAllInfo or whatever it's called, instead of just QueryFileInfo,
which is the motivation for needing the "read file attributes" permission.
My memory is a bit hazy here, but i have a vague recollection of looking
at smbclient using the same credentials only doing a QueryFileInfo and
succeeding.
On Sun, Oct 23, 2011 at 11:10:01PM +0400, Pavel Shilovsky wrote:
> Also, if you are interested, I can send you the right version of the
> patch I've already posted.
Please do :) I can't promise that I have any time to look at it but
it would be good to have regardless.
sean
^ permalink raw reply
* Re: [PATCH 2/4] Add parsing of A2MP signals
From: Andrei Emeltchenko @ 2011-10-24 7:34 UTC (permalink / raw)
To: Peter Krystad; +Cc: linux-bluetooth
In-Reply-To: <1319239802-22457-3-git-send-email-pkrystad@codeaurora.org>
Hi Peter,
On Fri, Oct 21, 2011 at 04:30:00PM -0700, Peter Krystad wrote:
> Add parsing of A2MP signalling.
> Example output:
>
> 2011-10-18 16:09:44.493202 > ACL data: handle 39 flags 0x02 dlen 16
> A2MP: Discover req: mtu/mps 670 mask: 0x0000
> 2011-10-18 16:09:44.493404 < ACL data: handle 39 flags 0x00 dlen 22
> A2MP: Discover rsp: mtu/mps 670 mask: 0x0000
> Controller list:
> id 0, type 0, status 0x01 (Bluetooth only)
> id 17, type 254, status 0x06 (Full capacity)
> 2011-10-18 16:09:44.697203 > ACL data: handle 39 flags 0x02 dlen 13
> A2MP: Get Info req: id 17
> 2011-10-18 16:09:44.697312 < ACL data: handle 39 flags 0x00 dlen 30
> A2MP: Get Info rsp: id 17 status (0) Success
> total bandwidth 500000
> max guaranteed bandwidth 0
> min latency 100000
> pal capabilities 0x0000
> assoc size 8
> 2011-10-18 16:09:44.893203 > ACL data: handle 39 flags 0x02 dlen 13
> A2MP: Get AMP Assoc req: id 17
> 2011-10-18 16:09:44.893618 < ACL data: handle 39 flags 0x00 dlen 22
> A2MP: Get AMP Assoc rsp: id 17 status (0) Success
> assoc data:
> 08 01 b1 01 0a 04 6c 42
> 2011-10-18 16:09:45.598201 > ACL data: handle 39 flags 0x02 dlen 22
> A2MP: Create Physical Link req: local id 1 remote id 17
> assoc data:
> 08 01 b1 01 0a 04 6d 38
> 2011-10-18 16:09:45.598643 < ACL data: handle 39 flags 0x00 dlen 15
> A2MP: Create Physical Link rsp: local id 17 remote id 1 status 0
> Success
> ---
> lib/amp.h | 133 +++++++++++++++++++
> parser/l2cap.c | 385 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
> parser/parser.h | 1 +
> src/hcidump.c | 1 +
> 4 files changed, 520 insertions(+), 0 deletions(-)
> create mode 100644 lib/amp.h
>
> diff --git a/lib/amp.h b/lib/amp.h
Minor comments. Would it be better to name it a2mp.h and functions below a2mp_*?
Otherwise as Marcel mentioned header patches shall be applied first to
bluez.
Best regards
Andrei Emeltchenko
> new file mode 100644
> index 0000000..0c6300a
> --- /dev/null
> +++ b/lib/amp.h
> @@ -0,0 +1,133 @@
> +/*
> + *
> + * BlueZ - Bluetooth protocol stack for Linux
> + *
> + * Copyright (C) 2010-2011 Code Aurora Forum. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __AMP_H
> +#define __AMP_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#define AMP_MGR_CID 0x03
> +
> +/* AMP manager codes */
> +#define AMP_COMMAND_REJ 0x01
> +#define AMP_DISCOVER_REQ 0x02
> +#define AMP_DISCOVER_RSP 0x03
> +#define AMP_CHANGE_NOTIFY 0x04
> +#define AMP_CHANGE_RSP 0x05
> +#define AMP_INFO_REQ 0x06
> +#define AMP_INFO_RSP 0x07
> +#define AMP_ASSOC_REQ 0x08
> +#define AMP_ASSOC_RSP 0x09
> +#define AMP_LINK_REQ 0x0a
> +#define AMP_LINK_RSP 0x0b
> +#define AMP_DISCONN_REQ 0x0c
> +#define AMP_DISCONN_RSP 0x0d
> +
> +typedef struct {
> + uint8_t code;
> + uint8_t ident;
> + uint16_t len;
> +} __attribute__ ((packed)) amp_mgr_hdr;
> +#define AMP_MGR_HDR_SIZE 4
> +
> +/* AMP ASSOC structure */
> +typedef struct {
> + uint8_t type_id;
> + uint16_t len;
> + uint8_t data[0];
> +} __attribute__ ((packed)) amp_assoc_tlv;
> +
> +typedef struct {
> + uint16_t reason;
> +} __attribute__ ((packed)) amp_cmd_rej_parms;
> +
> +typedef struct {
> + uint16_t mtu;
> + uint16_t mask;
> +} __attribute__ ((packed)) amp_discover_req_parms;
> +
> +typedef struct {
> + uint16_t mtu;
> + uint16_t mask;
> + uint8_t controller_list[0];
> +} __attribute__ ((packed)) amp_discover_rsp_parms;
> +
> +typedef struct {
> + uint8_t id;
> +} __attribute__ ((packed)) amp_info_req_parms;
> +
> +typedef struct {
> + uint8_t id;
> + uint8_t status;
> + uint32_t total_bandwidth;
> + uint32_t max_bandwidth;
> + uint32_t min_latency;
> + uint16_t pal_caps;
> + uint16_t assoc_size;
> +} __attribute__ ((packed)) amp_info_rsp_parms;
> +
> +typedef struct {
> + uint8_t id;
> + uint8_t status;
> + amp_assoc_tlv assoc;
> +} __attribute__ ((packed)) amp_assoc_rsp_parms;
> +
> +typedef struct {
> + uint8_t local_id;
> + uint8_t remote_id;
> + amp_assoc_tlv assoc;
> +} __attribute__ ((packed)) amp_link_req_parms;
> +
> +typedef struct {
> + uint8_t local_id;
> + uint8_t remote_id;
> + uint8_t status;
> +} __attribute__ ((packed)) amp_link_rsp_parms;
> +
> +typedef struct {
> + uint8_t local_id;
> + uint8_t remote_id;
> +} __attribute__ ((packed)) amp_disconn_req_parms;
> +
> +#define AMP_COMMAND_NOT_RECOGNIZED 0x0000
> +
> +/* AMP controller status */
> +#define AMP_CT_POWERED_DOWN 0x00
> +#define AMP_CT_BLUETOOTH_ONLY 0x01
> +#define AMP_CT_NO_CAPACITY 0x02
> +#define AMP_CT_LOW_CAPACITY 0x03
> +#define AMP_CT_MEDIUM_CAPACITY 0x04
> +#define AMP_CT_HIGH_CAPACITY 0x05
> +#define AMP_CT_FULL_CAPACITY 0x06
> +
> +/* AMP response status */
> +#define AMP_STATUS_SUCCESS 0x00
> +#define AMP_STATUS_INVALID_CTRL_ID 0x01
> +#define AMP_STATUS_UNABLE_START_LINK_CREATION 0x02
> +#define AMP_STATUS_NO_PHYSICAL_LINK_EXISTS 0x02
> +#define AMP_STATUS_COLLISION_OCCURED 0x03
> +#define AMP_STATUS_DISCONN_REQ_RECVD 0x04
> +#define AMP_STATUS_PHYS_LINK_EXISTS 0x05
> +#define AMP_STATUS_SECURITY_VIOLATION 0x06
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* __AMP_H */
> diff --git a/parser/l2cap.c b/parser/l2cap.c
> index 7547e8b..7915788 100644
> --- a/parser/l2cap.c
> +++ b/parser/l2cap.c
> @@ -36,6 +36,7 @@
> #include "parser/sdp.h"
> #include "lib/hci.h"
> #include "lib/l2cap.h"
> +#include "lib/amp.h"
>
> typedef struct {
> uint16_t handle;
> @@ -259,6 +260,16 @@ static char *reason2str(uint16_t reason)
> }
> }
>
> +static char *ampreason2str(uint16_t reason)
> +{
> + switch (reason) {
> + case AMP_COMMAND_NOT_RECOGNIZED:
> + return "Command not recognized";
> + default:
> + return "Reserved";
> + }
> +}
> +
> static char *connresult2str(uint16_t result)
> {
> switch (result) {
> @@ -399,6 +410,76 @@ static char *supervisory2str(uint8_t supervisory)
> }
> }
>
> +static char *ampctstatus2str(uint8_t status)
> +{
> + switch (status) {
> + case AMP_CT_POWERED_DOWN:
> + return "Powered down";
> + case AMP_CT_BLUETOOTH_ONLY:
> + return "Bluetooth only";
> + case AMP_CT_NO_CAPACITY:
> + return "No capacity";
> + case AMP_CT_LOW_CAPACITY:
> + return "Low capacity";
> + case AMP_CT_MEDIUM_CAPACITY:
> + return "Medium capacity";
> + case AMP_CT_HIGH_CAPACITY:
> + return "High capacity";
> + case AMP_CT_FULL_CAPACITY:
> + return "Full capacity";
> + default:
> + return "Reserved";
> +
> + }
> +}
> +
> +static char *ampstatus2str(uint8_t status)
> +{
> + switch (status) {
> + case AMP_STATUS_SUCCESS:
> + return "Success";
> + case AMP_STATUS_INVALID_CTRL_ID:
> + return "Invalid Controller ID";
> + default:
> + return "Reserved";
> + }
> +}
> +
> +static char *ampcplstatus2str(uint8_t status)
> +{
> + switch (status) {
> + case AMP_STATUS_SUCCESS:
> + return "Success";
> + case AMP_STATUS_INVALID_CTRL_ID:
> + return "Invalid Controller ID";
> + case AMP_STATUS_UNABLE_START_LINK_CREATION:
> + return "Failed - Unable to start link creation";
> + case AMP_STATUS_COLLISION_OCCURED:
> + return "Failed - Collision occured";
> + case AMP_STATUS_DISCONN_REQ_RECVD:
> + return "Failed - Disconnect physical link received";
> + case AMP_STATUS_PHYS_LINK_EXISTS:
> + return "Failed - Physical link already exists";
> + case AMP_STATUS_SECURITY_VIOLATION:
> + return "Failed - Security violation";
> + default:
> + return "Reserved";
> + }
> +}
> +
> +static char *ampdplstatus2str(uint8_t status)
> +{
> + switch (status) {
> + case AMP_STATUS_SUCCESS:
> + return "Success";
> + case AMP_STATUS_INVALID_CTRL_ID:
> + return "Invalid Controller ID";
> + case AMP_STATUS_NO_PHYSICAL_LINK_EXISTS:
> + return "Failed - No Physical Link exists";
> + default:
> + return "Reserved";
> + }
> +}
>
> static inline void command_rej(int level, struct frame *frm)
> {
> @@ -923,6 +1004,240 @@ static inline void move_cfm_rsp(int level, l2cap_cmd_hdr *cmd, struct frame *frm
> printf("Move cfm rsp: icid 0x%4.4x\n", icid);
> }
>
> +static inline void amp_command_rej(int level, struct frame *frm)
> +{
> + amp_cmd_rej_parms *h = frm->ptr;
> + uint16_t reason = btohs(h->reason);
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Command Reject: reason (%d)- ", reason);
> + p_indent(level + 1, frm);
> + printf("%s\n", ampreason2str(reason));
> +}
> +
> +static inline void amp_discover_req(int level, struct frame *frm, uint16_t len)
> +{
> + amp_discover_req_parms *h = frm->ptr;
> + uint16_t mtu = btohs(h->mtu);
> + uint8_t *octet = (uint8_t *)&(h->mask);
> + uint16_t mask;
> + uint8_t extension;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Discover req: mtu/mps %d ", mtu);
> + len -= 2;
> +
> + printf("mask:");
> +
> + do {
> + len -= 2;
> + mask = btohs(*(uint16_t *)(&octet[0]));
> + printf(" 0x%4.4x", mask);
> +
> + extension = octet[1] & 0x80;
> + octet += 2;
> + } while ((extension != 0) && (len >= 2));
> +
> + printf("\n");
> +}
> +
> +static inline void controller_list_dump (int level, uint8_t *octet, uint16_t len)
> +{
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + p_indent(level, 0);
> + printf("Controller list:\n");
> +
> + while (len >= 3) {
> + p_indent(level + 1, 0);
> + printf("id %d, type %d, status 0x%2.2x (%s)\n",
> + octet[0], octet[1], octet[2], ampctstatus2str(octet[2]));
> + octet += 3;
> + len -= 3;
> + }
> +
> +}
> +
> +static inline void amp_discover_rsp(int level, struct frame *frm, uint16_t len)
> +{
> + amp_discover_rsp_parms *h = frm->ptr;
> + uint16_t mtu = btohs(h->mtu);
> + uint8_t *octet = (uint8_t *)&(h->mask);
> + uint16_t mask;
> + uint8_t extension;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Discover rsp: mtu/mps %d ", mtu);
> + len -= 2;
> +
> + printf("mask:");
> +
> + do {
> + len -= 2;
> + mask = btohs(*(uint16_t *)(&octet[0]));
> + printf(" 0x%4.4x", mask);
> +
> + extension = octet[1] & 0x80;
> + octet += 2;
> + } while ((extension != 0) && (len >= 2));
> +
> + printf("\n");
> +
> + if (len >= 3) {
> + controller_list_dump (level + 1, octet, len);
> + }
> +}
> +
> +static inline void amp_change_notify(int level, struct frame *frm, uint16_t len)
> +{
> + uint8_t *octet = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Change Notify\n");
> +
> + if (len >= 3) {
> + controller_list_dump (level + 1, octet, len);
> + }
> +}
> +
> +static inline void amp_change_rsp(int level, struct frame *frm)
> +{
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Change Response\n");
> +}
> +
> +static inline void amp_info_req(int level, struct frame *frm)
> +{
> + amp_info_req_parms *h = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Get Info req: id %d\n", h->id);
> +}
> +
> +static inline void amp_info_rsp(int level, struct frame *frm)
> +{
> + amp_info_rsp_parms *h = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Get Info rsp: id %d status (%d) %s\n",
> + h->id, h->status, ampstatus2str(h->status));
> +
> + p_indent(level + 1, frm);
> + printf("total bandwidth %d\n", btohl(h->total_bandwidth));
> + p_indent(level + 1, frm);
> + printf("max guaranteed bandwidth %d\n", btohl(h->max_bandwidth));
> + p_indent(level + 1, frm);
> + printf("min latency %d\n", btohl(h->min_latency));
> + p_indent(level + 1, frm);
> + printf("pal capabilities 0x%4.4x\n", btohs(h->pal_caps));
> + p_indent(level + 1, frm);
> + printf("assoc size %d\n", btohs(h->assoc_size));
> +}
> +
> +static inline void amp_assoc_req(int level, struct frame *frm)
> +{
> + amp_info_req_parms *h = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Get AMP Assoc req: id %d\n", h->id);
> +}
> +
> +static inline void amp_assoc_dump(int level, uint8_t *assoc, uint16_t len)
> +{
> + int i;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + p_indent(level, 0);
> + printf("assoc data:");
> + for (i = 0; i < len; i++) {
> + if (!(i%16)) printf("\n");
> + if (!(i%16)) p_indent(level+1, 0);
> + printf("%2.2x ",*assoc++);
> + }
> + printf("\n");
> +
> +}
> +
> +static inline void amp_assoc_rsp(int level, struct frame *frm, uint16_t len)
> +{
> + amp_assoc_rsp_parms *h = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Get AMP Assoc rsp: id %d status (%d) %s \n",
> + h->id, h->status, ampstatus2str(h->status));
> + amp_assoc_dump(level + 1, (uint8_t *) &h->assoc, len - 2);
> +}
> +
> +static inline void amp_link_req(int level, struct frame *frm, uint16_t len)
> +{
> + amp_link_req_parms *h = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Create Physical Link req: local id %d remote id %d\n",
> + h->local_id, h->remote_id);
> + amp_assoc_dump(level + 1, (uint8_t *) &h->assoc, len - 2);
> +}
> +
> +static inline void amp_link_rsp(int level, struct frame *frm)
> +{
> + amp_link_rsp_parms *h = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Create Physical Link rsp: local id %d remote id %d status %d\n",
> + h->local_id, h->remote_id, h->status);
> + p_indent(level+1, 0);
> + printf("%s\n", ampcplstatus2str(h->status));
> +}
> +
> +static inline void amp_disconn_req(int level, struct frame *frm)
> +{
> + amp_disconn_req_parms *h = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Disconnect Physical Link req: local id %d remote id %d\n",
> + h->local_id, h->remote_id);
> +}
> +
> +static inline void amp_disconn_rsp(int level, struct frame *frm)
> +{
> + amp_link_rsp_parms *h = frm->ptr;
> +
> + if (p_filter(FILT_A2MP))
> + return;
> +
> + printf("Disconnect Physical Link rsp: local id %d remote id %d status %d\n",
> + h->local_id, h->remote_id, h->status);
> + p_indent(level+1, 0);
> + printf("%s\n", ampdplstatus2str(h->status));
> +}
> +
> static void l2cap_parse(int level, struct frame *frm)
> {
> l2cap_hdr *hdr = (void *)frm->ptr;
> @@ -1043,6 +1358,76 @@ static void l2cap_parse(int level, struct frame *frm)
> p_indent(level, frm);
> printf("L2CAP(c): len %d psm %d\n", dlen, psm);
> raw_dump(level, frm);
> + } else if ((cid == 0x3) && (frm->len > 4)) {
> +
> + /* Adjust for extra ERTM control bytes */
> + frm->ptr += 2;
> + frm->len -= 2;
> +
> + while (frm->len >= AMP_MGR_HDR_SIZE) {
> + amp_mgr_hdr *hdr = frm->ptr;
> +
> + frm->ptr += AMP_MGR_HDR_SIZE;
> + frm->len -= AMP_MGR_HDR_SIZE;
> +
> + if (!p_filter(FILT_A2MP)) {
> + p_indent(level, frm);
> + printf("A2MP: ");
> + }
> + switch (hdr->code) {
> + case AMP_COMMAND_REJ:
> + amp_command_rej(level, frm);
> + break;
> + case AMP_DISCOVER_REQ:
> + amp_discover_req(level, frm, hdr->len);
> + break;
> + case AMP_DISCOVER_RSP:
> + amp_discover_rsp(level, frm, hdr->len);
> + break;
> + case AMP_CHANGE_NOTIFY:
> + amp_change_notify(level, frm, hdr->len);
> + break;
> + case AMP_CHANGE_RSP:
> + amp_change_rsp(level, frm);
> + break;
> + case AMP_INFO_REQ:
> + amp_info_req(level, frm);
> + break;
> + case AMP_INFO_RSP:
> + amp_info_rsp(level, frm);
> + break;
> + case AMP_ASSOC_REQ:
> + amp_assoc_req(level, frm);
> + break;
> + case AMP_ASSOC_RSP:
> + amp_assoc_rsp(level, frm, hdr->len);
> + break;
> + case AMP_LINK_REQ:
> + amp_link_req(level, frm, hdr->len);
> + break;
> + case AMP_LINK_RSP:
> + amp_link_rsp(level, frm);
> + break;
> + case AMP_DISCONN_REQ:
> + amp_disconn_req(level, frm);
> + break;
> + case AMP_DISCONN_RSP:
> + amp_disconn_rsp(level, frm);
> + break;
> + default:
> + if (p_filter(FILT_A2MP))
> + break;
> + printf("code 0x%2.2x ident %d len %d\n",
> + hdr->code, hdr->ident, btohs(hdr->len));
> + raw_dump(level, frm);
> + }
> +
> + if (frm->len > btohs(hdr->len)) {
> + frm->len -= btohs(hdr->len);
> + frm->ptr += btohs(hdr->len);
> + } else
> + frm->len = 0;
> + }
> } else if (cid == 0x04) {
> if (!p_filter(FILT_ATT))
> att_dump(level, frm);
> diff --git a/parser/parser.h b/parser/parser.h
> index e975808..22d18c3 100644
> --- a/parser/parser.h
> +++ b/parser/parser.h
> @@ -80,6 +80,7 @@ struct frame {
> #define FILT_AVCTP 0x0800
> #define FILT_ATT 0x1000
> #define FILT_SMP 0x2000
> +#define FILT_A2MP 0x4000
>
> #define FILT_OBEX 0x00010000
> #define FILT_CAPI 0x00020000
> diff --git a/src/hcidump.c b/src/hcidump.c
> index 0c13360..2513c7c 100644
> --- a/src/hcidump.c
> +++ b/src/hcidump.c
> @@ -802,6 +802,7 @@ static struct {
> { "hci", FILT_HCI },
> { "sco", FILT_SCO },
> { "l2cap", FILT_L2CAP },
> + { "a2mp", FILT_A2MP },
> { "rfcomm", FILT_RFCOMM },
> { "sdp", FILT_SDP },
> { "bnep", FILT_BNEP },
> --
> 1.7.7
>
> --
> Peter Krystad
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum
> --
> To unsubscribe from this list: send the line "unsubscribe linux-bluetooth" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v2 3/5] regulator: helper routine to extract regulator_init_data
From: Mark Brown @ 2011-10-24 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4EA4FF6B.2080906@ti.com>
On Mon, Oct 24, 2011 at 11:32:19AM +0530, Rajendra Nayak wrote:
> On Friday 21 October 2011 05:28 PM, Shawn Guo wrote:
> >Driver name does not matter. The key for this search to work is having
> >regulator's name (regulator_desc->name) match device tree node's name,
> >case ignored.
> Mark, whats your take on this? I am somehow not quite sure if we should
> have this limitation put in to match DT node names with whats in the
> driver structs (regulator_desc).
If we're matching the string in the regulator_desc I'd expect we're
going to run into trouble with systems that have two of the same type of
regulator in the system. Is that the case? Since my primary
development system is such a system I care deeply about them :)
^ permalink raw reply
* Re: [PATCH v2 3/5] regulator: helper routine to extract regulator_init_data
From: Mark Brown @ 2011-10-24 7:34 UTC (permalink / raw)
To: Rajendra Nayak
Cc: Shawn Guo, grant.likely, patches, tony, devicetree-discuss,
linux-kernel, linux-omap, lrg, linux-arm-kernel
In-Reply-To: <4EA4FF6B.2080906@ti.com>
On Mon, Oct 24, 2011 at 11:32:19AM +0530, Rajendra Nayak wrote:
> On Friday 21 October 2011 05:28 PM, Shawn Guo wrote:
> >Driver name does not matter. The key for this search to work is having
> >regulator's name (regulator_desc->name) match device tree node's name,
> >case ignored.
> Mark, whats your take on this? I am somehow not quite sure if we should
> have this limitation put in to match DT node names with whats in the
> driver structs (regulator_desc).
If we're matching the string in the regulator_desc I'd expect we're
going to run into trouble with systems that have two of the same type of
regulator in the system. Is that the case? Since my primary
development system is such a system I care deeply about them :)
^ permalink raw reply
* Re: [Qemu-devel] [PATCH 0/2] block: Write out internal caches even with cache=unsafe
From: Kevin Wolf @ 2011-10-24 7:37 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, avi
In-Reply-To: <4EA1BD95.8030205@redhat.com>
Am 21.10.2011 20:44, schrieb Paolo Bonzini:
> On 10/21/2011 07:08 PM, Kevin Wolf wrote:
>> Avi complained that not even writing out qcow2's cache on bdrv_flush() made
>> cache=unsafe too unsafe to be useful. He's got a point.
>
> Why? cache=unsafe is explicitly allowing to s/data/manure/ on crash.
It's surely expected on a host crash, but is it for a qemu crash?
cache=unsafe was introduced to avoid fsync() costs, which it still does
after this patch.
> If you do this for raw-posix, you need to do it for all protocols.
rbd could use it, too, right. Any other protocol I missed?
Kevin
^ permalink raw reply
* [U-Boot] Failed to apply patch
From: Sadashiva @ 2011-10-24 7:33 UTC (permalink / raw)
To: u-boot
In-Reply-To: <201110181413.20478.sr@denx.de>
Hi Sir,
I downloaded the latest version of u-boot source code of version number
u-boot-2011.03.tar.bz2.
from ftp://ftp.denx.de/pub/u-boot/ website and the MPL patches for
this from the website
http://www.mpl.ch/t2722.html
Latest MPL supported version. Patches are available here: MPL
patches
But when I apply the patch example
test at test-laptop:~/toolchain_2011/u-boot-2011.03$patch -p1 <
u-boot-2011.03.mpl-patches
I am getting failed message like.
patching file MAINTAINERS
Hunk #1 FAILED at 342.
1 out of 1 hunk FAILED -- saving rejects to file MAINTAINERS.rej
patching file arch/powerpc/cpu/mpc83xx/fdt.c
Hunk #1 FAILED at 50.
Hunk #2 FAILED at 132.
2 out of 2 hunk FAILED -- saving rejects to file
arch/powerpc/cpu/mpc83xx/fdt.c.rej
patching file board/mpl/common/common_util.c
Hunk #1 FAILED at 33.
Hunk #2 FAILED at 161.
Hunk #3 FAILED at 189.
Hunk #4 FAILED at 198.
Hunk #5 FAILED at 211.
Hunk #6 FAILED at 243.
Hunk #7 FAILED at 253.
Hunk #8 FAILED at 281.
Hunk #9 FAILED at 306.
Hunk #10 FAILED at 337.
Hunk #11 FAILED at 370.
Hunk #12 FAILED at 389.
Hunk #13 FAILED at 428.
Hunk #14 FAILED at 472.
Hunk #15 FAILED at 485.
Hunk #16 FAILED at 507.
Hunk #17 FAILED at 537.
Hunk #18 FAILED at 547.
Hunk #19 FAILED@577.
19 out of 19 hunk FAILED -- saving rejects to file
board/mpl/common/common_util.c.rej
patching file board/mpl/common/flash.c
Reversed (or previous applied) patch detected! Assume -R? [n] n
Apply anyway? [n] n
skipping patch.
Can I get any help on this failed issue.
Thanking you in advance.
Best Regards,
Sadashiv
^ permalink raw reply
* serial-console: IMAGE_FEATURE, MACHINE_FEATURE or DISTRO_FEATURE?
From: Koen Kooi @ 2011-10-24 7:27 UTC (permalink / raw)
To: Patches and discussions about the oe-core layer
Hi,
Otavio is cleaning up systemd in meta-oe to work with his initramfs setup and we stumbled onto a challenge that we'd like some more feedback on.
The old sysvinit recipes always hardcode a serial getty into inittab, systemd installs a getty@<port>.service file instead. Otavio doesn't need (or want) a getty on serial in his setup, but I need (and want) it on all my setups. So we agreed that it needs to be a feature :)
I nitially suggested MACHINE_FEATURE, which Otavio implemented here: http://patchwork.openembedded.org/patch/13713/ , but I'm having second thoughs about it and am leaning toward an IMAGE_FEATURE instead. Since this involves *_FEATURE and we want systemd to move into oe-core eventually I'm moving the discussion from OE-devel to OE-core. Not much discussion has been going on, so I hope we'll get some more feedback here. I'll try to buttonhole some more OE developers at ELC and report back as well.
regards,
Koen
^ permalink raw reply
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