* Re: What is the strategy to update eglibc?
From: Kang Kai @ 2011-10-31 2:16 UTC (permalink / raw)
To: Patches and discussions about the oe-core layer; +Cc: Saul Wold
In-Reply-To: <4EAE0428.2020209@windriver.com>
On 2011年10月31日 10:12, Kang Kai wrote:
> Hi Saul,
>
> I just want to update eglibc but eglibc is using its 2.14 branch and
> use svn commit revision "15225" as current version. Of course it is
> behind the latest svn revision, but I don't quit sure about which is
> the right revision to update eglibc.
Hi Saul,
And right now is 2 commits behind the latest revision, do it worth to
update right now?
Thanks!
>
> Could you give me some guide? Thank you!
>
> Regards,
> Kai
>
> _______________________________________________
> Openembedded-core mailing list
> Openembedded-core@lists.openembedded.org
> http://lists.linuxtogo.org/cgi-bin/mailman/listinfo/openembedded-core
^ permalink raw reply
* [PATCH] pcie-gadget-spear: Add "platform:" prefix for platform modalias
From: Axel Lin @ 2011-10-31 2:20 UTC (permalink / raw)
To: linux-kernel
Cc: Pratyush Anand, Randy Dunlap, Arnd Bergmann, Greg Kroah-Hartman
Since 43cc71eed1250755986da4c0f9898f9a635cb3bf (platform: prefix MODALIAS
with "platform:"), the platform modalias is prefixed with "platform:".
Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
drivers/misc/spear13xx_pcie_gadget.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/misc/spear13xx_pcie_gadget.c b/drivers/misc/spear13xx_pcie_gadget.c
index cfbddbe..43d073b 100644
--- a/drivers/misc/spear13xx_pcie_gadget.c
+++ b/drivers/misc/spear13xx_pcie_gadget.c
@@ -903,6 +903,6 @@ static void __exit spear_pcie_gadget_exit(void)
}
module_exit(spear_pcie_gadget_exit);
-MODULE_ALIAS("pcie-gadget-spear");
+MODULE_ALIAS("platform:pcie-gadget-spear");
MODULE_AUTHOR("Pratyush Anand");
MODULE_LICENSE("GPL");
--
1.7.5.4
^ permalink raw reply related
* Re: [Qemu-devel] [PATCH v9 0/4] The intro of QEMU block I/O throttling
From: Zhi Yong Wu @ 2011-10-31 2:20 UTC (permalink / raw)
To: Richard Davies; +Cc: kwolf, Zhiyong Wu, Marcelo Tosatti, qemu-devel, stefanha
In-Reply-To: <20111030104422.GD32746@alpha.arachsys.com>
On Sun, Oct 30, 2011 at 6:44 PM, Richard Davies
<richard.davies@elastichosts.com> wrote:
> Hi,
>
> I've been following the evolution of this patch with great interest for use
> in our qemu-kvm based IaaS public cloud.
>
> I am not a qemu developer, but have watched this patch go through many
> rounds of review and we are very much hoping that it makes it into QEMU 1.0.
Yeah, we also hope that it can be merged into QEMU 1.0.
By the way, the issue below has been resolved.
1.) When bps/iops limits are specified to a small value such as 511
bytes/s, this VM will hang up. We are considering how to handle this
senario.
Any comment is appreciated if you have other concerns.
>
> In a multi-customer multi-VM public cloud environment, disk i/o limiting is
> absolutely key, and qemu itself is a much better place to do it than with a
> mix of cgroups and other technologies for each different storage backend.
> I understand that it is also more efficient:
>
> http://www.linux-kvm.org/wiki/images/7/72/2011-forum-keep-a-limit-on-it-io-throttling-in-qemu.pdf
>
> As I say, I am not a qemu developer, so cannot practically help, but wanted
> to post to emphasize the importance of this technology as a consumer of qemu.
No matter...
>
> Best regards,
>
> Richard.
>
>
--
Regards,
Zhi Yong Wu
^ permalink raw reply
* Re: ping_pong test of ceph
From: mowang da @ 2011-10-31 2:18 UTC (permalink / raw)
To: ceph-devel
In-Reply-To: <CAF3hT9CkNdi4UFgAPhqy9xzk8s_7Tz6bqG5aTW3k87oxfEEt7g@mail.gmail.com>
thanks , if there is only one client, can we use local flock to
replace flock mds?
2011/10/31 Gregory Farnum <gregory.farnum@dreamhost.com>:
> On Sun, Oct 30, 2011 at 6:21 PM, mowang da <whooya.xxl@gmail.com> wrote:
>> hi all,
>> this bug has been fixed yet? i can't find any information of it.
>> thanks for your help.
>
> Yes, it was fixed a while ago in our master branch and is fixed in our
> last couple of releases. (Our newest is v0.37.)
> As the problem was in the MDS server, to see this fix you only need to
> upgrade the userspace packages. :)
> -Greg
>
^ permalink raw reply
* What is the strategy to update eglibc?
From: Kang Kai @ 2011-10-31 2:12 UTC (permalink / raw)
To: Saul Wold, oe-core
Hi Saul,
I just want to update eglibc but eglibc is using its 2.14 branch and use
svn commit revision "15225" as current version. Of course it is behind
the latest svn revision, but I don't quit sure about which is the right
revision to update eglibc.
Could you give me some guide? Thank you!
Regards,
Kai
^ permalink raw reply
* Re: [Qemu-devel] [PATCH v2] block: avoid SIGUSR2
From: Zhi Yong Wu @ 2011-10-31 2:10 UTC (permalink / raw)
To: Stefan Hajnoczi
Cc: Lucas Meneghel Rodrigues, Kevin Wolf, aliguori, Stefan Hajnoczi,
qemu-devel, Frediano Ziglio, Cleber Rosa, Paolo Bonzini
In-Reply-To: <CAJSP0QUQC5Ue94LS=CC9PGBxo-eOP1xPQPhL_dVLpt3GXLFe1A@mail.gmail.com>
On Fri, Oct 28, 2011 at 01:31:20PM +0100, Stefan Hajnoczi wrote:
>Subject: Re: [Qemu-devel] [PATCH v2] block: avoid SIGUSR2
>From: Stefan Hajnoczi <stefanha@gmail.com>
>To: Zhi Yong Wu <wuzhy@linux.vnet.ibm.com>
>Cc: Paolo Bonzini <pbonzini@redhat.com>, Lucas Meneghel Rodrigues
> <lmr@redhat.com>, aliguori@us.ibm.com, Stefan Hajnoczi
> <stefanha@linux.vnet.ibm.com>, qemu-devel@nongnu.org, Frediano Ziglio
> <freddy77@gmail.com>, Cleber Rosa <crosa@redhat.com>, Kevin Wolf
> <kwolf@redhat.com>
>Content-Type: text/plain; charset=ISO-8859-1
>x-cbid: 11102812-3534-0000-0000-000000FD91EE
>X-IBM-ISS-SpamDetectors: Score=0; BY=0; FL=0; FP=0; FZ=0; HX=0; KW=0; PH=0;
> SC=0; ST=0; TS=0; UL=0; ISC=
>X-IBM-ISS-DetailInfo: BY=3.00000227; HX=3.00000175; KW=3.00000007;
> PH=3.00000001; SC=3.00000001; SDB=6.00082671; UDB=6.00022873;
> UTC=2011-10-28 12:31:35
>X-Xagent-From: stefanha@gmail.com
>X-Xagent-To: wuzhy@linux.vnet.ibm.com
>X-Xagent-Gateway: vmsdvm6.vnet.ibm.com (XAGENTU8 at VMSDVM6)
>
>On Fri, Oct 28, 2011 at 1:29 PM, Kevin Wolf <kwolf@redhat.com> wrote:
>> Am 28.10.2011 13:50, schrieb Paolo Bonzini:
>>> On 10/28/2011 01:33 PM, Kevin Wolf wrote:
>>>> I'm afraid that we can only avoid things like this reliably if we
>>>> convert all devices to be direct users of AIO/coroutines. The current
>>>> block layer infrastructure doesn't emulate the behaviour of bdrv_read
>>>> accurately as bottom halves can be run in the nested main loop.
>>>>
>>>> For floppy, the following seems to be a quick fix (Lucas, Cleber, does
>>>> this solve your problems?), though it's not very satisfying. And I'm not
>>>> quite sure yet why it doesn't always happen with kill() in
>>>> posix-aio-compat.c.
>>>
>>> Another "fix" is to change idle bottom halves (at least the one in
>>> hw/dma.c) to 10ms timers.
>>
>> Which would be using the fact that timers are only executed in the real
>> main loop. Which makes me wonder if it would be enough for floppy if we
>> changed qemu_bh_poll() to take a bool run_idle_bhs that would be true in
>> the main loop and false an qemu_aio_wait().
>>
>> Still this wouldn't be a general solution as normal BHs have the very
>> same problem if they are scheduled before a bdrv_read/write call. To
>> solve that I guess we'd have to reintroduce AsyncContext, but it has its
>> own problems and was removed for a reason.
>>
>> Or we make some serious effort now to convert devices to AIO.
>
>Zhi Yong: We were just talking about converting devices to aio. If
>you have time to do that for fdc, sd, or any other synchronous API
>users in hw/ that would be helpful. Please let us know which device
>you are refactoring so we don't duplicate work.
Stefan,
I am working on flash(onenand, CFI), cdrom, sd, fdc, etc. If anyone has good thought, pls let me know.:)
Regards,
Zhi Yong Wu
>
>Stefan
>
^ permalink raw reply
* PULL REQUEST - serious md/RAID10 bug in 3.1 when activating a hot-spare.
From: NeilBrown @ 2011-10-31 2:08 UTC (permalink / raw)
To: Linus Torvalds, linux RAID, lkml
[-- Attachment #1: Type: text/plain, Size: 2024 bytes --]
Hi Linus et al,
I just discovered a fairly serious flaw that I introduced into 3.1 - details
below.
Anyone running RAID10 with 3.1 is advised to either apply this patch or
revert an earlier kernel as soon as possible. In the mean time, remove any
hot spares from an RAID10 array.
NeilBrown
The following changes since commit d890fa2b0586b6177b119643ff66932127d58afa:
md: Fix some bugs in recovery_disabled handling. (2011-10-26 11:54:39 +1100)
are available in the git repository at:
git://neil.brown.name/md for-linus
last commit being 7fcc7c8acf0fba44d19a713207af7e58267c1179
NeilBrown (1):
md/raid10: Fix bug when activating a hot-spare.
drivers/md/raid10.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
commit 7fcc7c8acf0fba44d19a713207af7e58267c1179
Author: NeilBrown <neilb@suse.de>
Date: Mon Oct 31 12:59:44 2011 +1100
md/raid10: Fix bug when activating a hot-spare.
This is a fairly serious bug in RAID10.
When a RAID10 array is degraded and a hot-spare is activated, the
spare does not take up the empty slot, but rather replaces the first
working device.
This is likely to make the array non-functional. It would normally
be possible to recover the data, but that would need care and is not
guaranteed.
This bug was introduced in commit
2bb77736ae5dca0a189829fbb7379d43364a9dac
which first appeared in 3.1.
Cc: stable@kernel.org
Signed-off-by: NeilBrown <neilb@suse.de>
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 132c18e..c025a82 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -1355,7 +1355,7 @@ static int raid10_add_disk(struct mddev *mddev, struct md_rdev *rdev)
struct mirror_info *p = &conf->mirrors[mirror];
if (p->recovery_disabled == mddev->recovery_disabled)
continue;
- if (!p->rdev)
+ if (p->rdev)
continue;
disk_stack_limits(mddev->gendisk, rdev->bdev,
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 828 bytes --]
^ permalink raw reply related
* For Claims Contact: Mrs.Hope Spencer. Email:mrs.hopespencer@microsoftdonation.pcriot.com
From: Microsoft Donation @ 2011-10-31 7:30 UTC (permalink / raw)
Dear Internet User! Microsoft Company have donated £1,000,000 GBP to you and
your family has a benefit for joining us in expanding the use of microsoft
windows and internet in your country
^ permalink raw reply
* For Claims Contact: Mrs.Hope Spencer. Email:mrs.hopespencer@microsoftdonation.pcriot.com
From: Microsoft Donation @ 2011-10-31 7:30 UTC (permalink / raw)
Dear Internet User! Microsoft Company have donated £1,000,000 GBP to you and
your family has a benefit for joining us in expanding the use of microsoft
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^ permalink raw reply
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From: Microsoft Donation @ 2011-10-31 7:30 UTC (permalink / raw)
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^ permalink raw reply
* [qemu-kvm unittest failure] Autotest | Job ID: 1992 "Upstream qemu-kvm.git sanity 10-29-2011 00:04:01" | Status: 1 Completed | Success Rate: 94.74 %
From: Lucas Meneghel Rodrigues @ 2011-10-31 2:05 UTC (permalink / raw)
To: KVM mailing list; +Cc: Cleber Rosa, Avi Kivity, Marcelo Tosatti
In-Reply-To: <201110290919.p9T9JTgQ002888@int-mx10.intmail.prod.int.phx2.redhat.com>
On 10/29/2011 07:19 AM, kvm-autotest@redhat.com wrote:
> Job ID: 1992
> Job name: Upstream qemu-kvm.git sanity 10-29-2011 00:04:01
> Summary: Host: virtlab201.virt.bos.redhat.com Status: Completed
> Status: 1 Completed
> Execution time (HH:MM:SS): 01:14:09
> User tests executed: 19
> User tests passed: 18
> User tests failed: 1
> User tests success rate: 94.74 %
> Failures:
> Test Name Status Reason
> kvm.qemu-kvm-git.unittests FAIL Unit tests failed: emulator
Hi Avi and Marcelo, we just did notice the emulator unittest started to
fail after quite some time with no issues. If you need help looking into
the issues, let us know.
^ permalink raw reply
* Re: ping_pong test of ceph
From: Gregory Farnum @ 2011-10-31 2:03 UTC (permalink / raw)
To: mowang da; +Cc: ceph-devel
In-Reply-To: <CAMwsgzNkgd0gYf_LNELWfB8Fd5e7HP0v=R8wgAOG8jkEXUxG9A@mail.gmail.com>
On Sun, Oct 30, 2011 at 6:21 PM, mowang da <whooya.xxl@gmail.com> wrote:
> hi all,
> this bug has been fixed yet? i can't find any information of it.
> thanks for your help.
Yes, it was fixed a while ago in our master branch and is fixed in our
last couple of releases. (Our newest is v0.37.)
As the problem was in the MDS server, to see this fix you only need to
upgrade the userspace packages. :)
-Greg
^ permalink raw reply
* [Qemu-devel] [Qemu test report] Autotest | Job ID: 1997 "Upstream qemu.git sanity 10-30-2011 00:05:01" | Status: 1 Completed | Success Rate: 53.85 %
From: Lucas Meneghel Rodrigues @ 2011-10-31 2:01 UTC (permalink / raw)
To: QEMU devel, Kevin Wolf, Luiz Capitulino
In-Reply-To: <201110301350.p9UDowl9028582@int-mx01.intmail.prod.int.phx2.redhat.com>
Hi folks, sending this to QEMU devel to inform the current problems we
are able to reproduce on the current master branch.
So, qemu.git is presenting problems as of latest master. None of the
problems mentioned is happening on qemu-kvm.git.
-------- Original Message --------
Subject: Autotest | Job ID: 1997 "Upstream qemu.git sanity 10-30-2011
00:05:01" | Status: 1 Completed | Success Rate: 53.85 %
Date: Sun, 30 Oct 2011 09:50:58 -0400
From: kvm-autotest@redhat.com
To: lmr@redhat.com, crosa@redhat.com
Job ID: 1997
Job name: Upstream qemu.git sanity 10-30-2011 00:05:01
Summary: Host: virtlab208.virt.bos.redhat.com Status: Completed
Status: 1 Completed
Execution time (HH:MM:SS): 05:44:38
User tests executed: 26
User tests passed: 14
User tests failed: 12
User tests success rate: 53.85 %
Failures:
Test Name
Status Reason
kvm.qemu-git.virtio_blk.smp2.virtio_net.Win7.64.sp1.unattended_install.cdrom
FAIL Timeout elapsed while waiting for install to finish [context:
waiting for installation to finish]
^ Here, the windows install timeout happened due to the floppy
regression introduced by 212ec7baa28cc9d819234fed1541fc1423cfe3d8. We
did try Kevin's patches and they did not fix the issue.
kvm.qemu-git.virtio_blk.smp2.virtio_net.RHEL.6.1.x86_64.migrate.tcp
FAIL Unhandled LoginError: Client said 'connection refused'
(output: 'ssh: connect to host 192.168.122.129 port 22: Connection
refused\n') [context: logging into 'vm1']
kvm.qemu-git.virtio_blk.smp2.virtio_net.RHEL.6.1.x86_64.reboot
FAIL Unhandled LoginError: Client said 'connection refused'
(output: 'ssh: connect to host 192.168.122.25 port 22: Connection
refused\n') [context: logging into 'vm1']
kvm.qemu-git.virtio_blk.smp2.virtio_net.RHEL.6.1.x86_64.migrate.unix
FAIL Unhandled LoginError: Client said 'connection refused'
(output: 'ssh: connect to host 192.168.122.3 port 22: Connection
refused\n') [context: logging into 'vm1']
kvm.qemu-git.virtio_blk.smp2.virtio_net.RHEL.6.1.x86_64.migrate.exec
FAIL Unhandled MonitorSocketError: Could not send monitor
command 'info migrate' ([Errno 32] Broken pipe) [context:
migrating 'vm1']
^ All of those failures happened due to qemu segfaults during the
migration process. I believe Luiz had a patch to possibly fix this
migration issue, so copying him.
The segfaults generated core dumps, which we would be happy to scp to a
public box, if someone is interested in them.
Cheers,
Lucas
^ permalink raw reply
* Re: question about passing physical address to lower level driver in scsi
From: yoma sophian @ 2011-10-31 1:53 UTC (permalink / raw)
To: Stefan Richter; +Cc: linux-scsi
In-Reply-To: <20111030132821.4df33f1e@stein>
hi stefan:
Thanks for your reply.
2011/10/30, Stefan Richter <stefanr@s5r6.in-berlin.de>:
> On Oct 30 yoma sophian wrote:
>> in scsi_init_sgtable, we create sgtable, sdb->table.sgl, and get the
>> page from blk_rq_map_sg.
>> But when the dma_address of sdb->table.sgl will be calclated out
>> before send the scsi command down to the lower level driver?
>
> The low level driver, not SCSI core, is responsible to obtain a DMA
> address.
Why I ask this because I found there is no same transformation for
scsi usb subsystem.
Would anyone can let me know where it is?
>
> dma_map_sg() maps the scatter-gather list into DMA memory. Then you can
> iterate over the list with for_each_sg and obtain DMA handles and lengths
> with sg_dma_address() and sg_dma_len(). E.g.:
>
> http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/firewire/sbp2.c;h=41841a3e3f99c9acd4c4fc72c972626d8dffdcee;hb=02f8c6aee8df3cdc935e9bdd4f2d020306035dbe#l1398
> --
> Stefan Richter
> -=====-==-== =-=- ====-
> http://arcgraph.de/sr/
>
Retards,
^ permalink raw reply
* Re: [PATCH v2] drm/i915: Fix recursive calls to unmap
From: Ben Widawsky @ 2011-10-31 1:52 UTC (permalink / raw)
To: Keith Packard; +Cc: intel-gfx
In-Reply-To: <yunehxu2b8o.fsf@aiko.keithp.com>
On Sun, 30 Oct 2011 18:36:23 -0700
Keith Packard <keithp@keithp.com> wrote:
> On Sun, 30 Oct 2011 18:20:54 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> >
> > The solution here is to add a new flag to the call chain which gives the
> > routines the information they need to possibly defer actions which may
> > cause us to recurse.
>
> This looks a lot nicer; it's shorter than I feared too.
>
> > @@ -2051,7 +2052,8 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
> > * it.
> > */
> > if (obj->active) {
> > - ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
> > + ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
> > + true);
>
> > @@ -2400,7 +2402,8 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
> > if (!ring_passed_seqno(obj->last_fenced_ring,
> > obj->last_fenced_seqno)) {
> > ret = i915_wait_request(obj->last_fenced_ring,
> > - obj->last_fenced_seqno);
> > + obj->last_fenced_seqno,
> > + true);
> > if (ret)
> > return ret;
> > }
> > @@ -2541,7 +2544,8 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
> > if (!ring_passed_seqno(obj->last_fenced_ring,
> > reg->setup_seqno)) {
> > ret = i915_wait_request(obj->last_fenced_ring,
> > - reg->setup_seqno);
> > + reg->setup_seqno,
> > + true);
> > if (ret)
> > return ret;
> > }
>
> Any reason you're changing behaviour outside of the area with the actual
> problem? If so, you should stick those in a separate patch instead of
> mixing them into this bug fix.
>
Well, I had to pick one, and looking at the call chain, it seemed there wasn't
much to gain by doing retiring at this point. If you want to take the
patch, and modify those vales to false - I'm okay with it.
Ben
^ permalink raw reply
* [Qemu-devel] [PATCH 2/2] pseries: Add partial support for PCI
From: David Gibson @ 2011-10-31 1:51 UTC (permalink / raw)
To: agraf, anthony; +Cc: qemu-ppc, qemu-devel
In-Reply-To: <1320025885-29613-1-git-send-email-david@gibson.dropbear.id.au>
This patch adds a PCI bus to the pseries machine. This instantiates
the qemu generic PCI bus code, advertises a PCI host bridge in the
guest's device tree and implements the RTAS methods specified by PAPR
to access PCI config space. It also sets up the memory regions we
need to provide windows into the PCI memory and IO space, and
advertises those to the guest.
However, because qemu can't yet emulate an IOMMU, which is mandatory on
pseries, PCI devices which use DMA (i.e. most of them) will not work with
this code alone. Still, this is enough to support the virtio_pci device
(which probably _should_ use emulated PCI DMA, but is specced to use
direct hypervisor access to guest physical memory instead).
Signed-off-by: Alexey Kardashevskiy <aik@au1.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
Makefile.target | 1 +
hw/spapr.c | 36 ++++-
hw/spapr.h | 2 +
hw/spapr_pci.c | 508 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/spapr_pci.h | 59 +++++++
5 files changed, 602 insertions(+), 4 deletions(-)
create mode 100644 hw/spapr_pci.c
create mode 100644 hw/spapr_pci.h
diff --git a/Makefile.target b/Makefile.target
index fe5f6f7..2329df5 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -248,6 +248,7 @@ obj-ppc-y += ppc_newworld.o
# IBM pSeries (sPAPR)
obj-ppc-$(CONFIG_PSERIES) += spapr.o spapr_hcall.o spapr_rtas.o spapr_vio.o
obj-ppc-$(CONFIG_PSERIES) += xics.o spapr_vty.o spapr_llan.o spapr_vscsi.o
+obj-ppc-$(CONFIG_PSERIES) += spapr_pci.o device-hotplug.o pci-hotplug.o
# PowerPC 4xx boards
obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
obj-ppc-y += ppc440.o ppc440_bamboo.o
diff --git a/hw/spapr.c b/hw/spapr.c
index 933af32..bdaa938 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -39,10 +39,12 @@
#include "hw/spapr.h"
#include "hw/spapr_vio.h"
+#include "hw/spapr_pci.h"
#include "hw/xics.h"
#include "kvm.h"
#include "kvm_ppc.h"
+#include "pci.h"
#include "exec-memory.h"
@@ -62,6 +64,11 @@
#define MAX_CPUS 256
#define XICS_IRQS 1024
+#define SPAPR_PCI_BUID 0x800000020000001ULL
+#define SPAPR_PCI_MEM_WIN_ADDR (0x10000000000ULL + 0xA0000000)
+#define SPAPR_PCI_MEM_WIN_SIZE 0x20000000
+#define SPAPR_PCI_IO_WIN_ADDR (0x10000000000ULL + 0x80000000)
+
#define PHANDLE_XICP 0x00001111
sPAPREnvironment *spapr;
@@ -146,6 +153,14 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
&end_prop, sizeof(end_prop))));
_FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
+ /*
+ * Because we don't always invoke any firmware, we can't rely on
+ * that to do BAR allocation. Long term, we should probably do
+ * that ourselves, but for now, this setting (plus advertising the
+ * current BARs as 0) causes sufficiently recent kernels to to the
+ * BAR assignment themselves */
+ _FDT((fdt_property_cell(fdt, "linux,pci-probe-only", 0)));
+
_FDT((fdt_end_node(fdt)));
/* memory node(s) */
@@ -308,6 +323,7 @@ static void spapr_finalize_fdt(sPAPREnvironment *spapr,
{
int ret;
void *fdt;
+ sPAPRPHBState *phb;
fdt = g_malloc(FDT_MAX_SIZE);
@@ -320,6 +336,15 @@ static void spapr_finalize_fdt(sPAPREnvironment *spapr,
exit(1);
}
+ QLIST_FOREACH(phb, &spapr->phbs, list) {
+ ret = spapr_populate_pci_devices(phb, PHANDLE_XICP, fdt);
+ }
+
+ if (ret < 0) {
+ fprintf(stderr, "couldn't setup PCI devices in fdt\n");
+ exit(1);
+ }
+
/* RTAS */
ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
if (ret < 0) {
@@ -478,6 +503,12 @@ static void ppc_spapr_init(ram_addr_t ram_size,
}
}
+ /* Set up PCI */
+ spapr_create_phb(spapr, "pci", SPAPR_PCI_BUID,
+ SPAPR_PCI_MEM_WIN_ADDR,
+ SPAPR_PCI_MEM_WIN_SIZE,
+ SPAPR_PCI_IO_WIN_ADDR);
+
for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
@@ -488,10 +519,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
if (strcmp(nd->model, "ibmveth") == 0) {
spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd);
} else {
- fprintf(stderr, "pSeries (sPAPR) platform does not support "
- "NIC model '%s' (only ibmveth is supported)\n",
- nd->model);
- exit(1);
+ pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
}
}
diff --git a/hw/spapr.h b/hw/spapr.h
index 6657c33..5689797 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -2,12 +2,14 @@
#define __HW_SPAPR_H__
#include "hw/xics.h"
+#include "spapr_pci.h"
struct VIOsPAPRBus;
struct icp_state;
typedef struct sPAPREnvironment {
struct VIOsPAPRBus *vio_bus;
+ QLIST_HEAD(, sPAPRPHBState) phbs;
struct icp_state *icp;
target_phys_addr_t ram_limit;
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
new file mode 100644
index 0000000..2a5e637
--- /dev/null
+++ b/hw/spapr_pci.c
@@ -0,0 +1,508 @@
+/*
+ * QEMU sPAPR PCI host originated from Uninorth PCI host
+ *
+ * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
+ * Copyright (C) 2011 David Gibson, IBM Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "pci.h"
+#include "pci_host.h"
+#include "hw/spapr.h"
+#include "hw/spapr_pci.h"
+#include "exec-memory.h"
+#include <libfdt.h>
+
+#include "hw/pci_internals.h"
+
+static const uint32_t bars[] = {
+ PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
+ PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
+ PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
+ /*, PCI_ROM_ADDRESS*/
+};
+
+static PCIDevice *find_dev(sPAPREnvironment *spapr,
+ uint64_t buid, uint32_t config_addr)
+{
+ DeviceState *qdev;
+ int devfn = (config_addr >> 8) & 0xFF;
+ sPAPRPHBState *phb;
+
+ QLIST_FOREACH(phb, &spapr->phbs, list) {
+ if (phb->buid != buid) {
+ continue;
+ }
+
+ QLIST_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
+ PCIDevice *dev = (PCIDevice *)qdev;
+ if (dev->devfn == devfn) {
+ return dev;
+ }
+ }
+ }
+
+ return NULL;
+}
+
+static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args,
+ uint32_t nret, target_ulong rets)
+{
+ uint32_t val, size, addr;
+ uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
+ PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
+
+ if (!dev) {
+ rtas_st(rets, 0, -1);
+ return;
+ }
+ size = rtas_ld(args, 3);
+ addr = rtas_ld(args, 0) & 0xFF;
+ val = pci_default_read_config(dev, addr, size);
+ rtas_st(rets, 0, 0);
+ rtas_st(rets, 1, val);
+}
+
+static void rtas_read_pci_config(sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args,
+ uint32_t nret, target_ulong rets)
+{
+ uint32_t val, size, addr;
+ PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
+
+ if (!dev) {
+ rtas_st(rets, 0, -1);
+ return;
+ }
+ size = rtas_ld(args, 1);
+ addr = rtas_ld(args, 0) & 0xFF;
+ val = pci_default_read_config(dev, addr, size);
+ rtas_st(rets, 0, 0);
+ rtas_st(rets, 1, val);
+}
+
+static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args,
+ uint32_t nret, target_ulong rets)
+{
+ uint32_t val, size, addr;
+ uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
+ PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
+
+ if (!dev) {
+ rtas_st(rets, 0, -1);
+ return;
+ }
+ val = rtas_ld(args, 4);
+ size = rtas_ld(args, 3);
+ addr = rtas_ld(args, 0) & 0xFF;
+ pci_default_write_config(dev, addr, val, size);
+ rtas_st(rets, 0, 0);
+}
+
+static void rtas_write_pci_config(sPAPREnvironment *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args,
+ uint32_t nret, target_ulong rets)
+{
+ uint32_t val, size, addr;
+ PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
+
+ if (!dev) {
+ rtas_st(rets, 0, -1);
+ return;
+ }
+ val = rtas_ld(args, 2);
+ size = rtas_ld(args, 1);
+ addr = rtas_ld(args, 0) & 0xFF;
+ pci_default_write_config(dev, addr, val, size);
+ rtas_st(rets, 0, 0);
+}
+
+static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
+{
+ /*
+ * Here we need to convert pci_dev + irq_num to some unique value
+ * which is less than number of IRQs on the specific bus (now it
+ * is 16). At the moment irq_num == device_id (number of the
+ * slot?)
+ * FIXME: we should swizzle in fn and irq_num
+ */
+ return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
+}
+
+static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
+{
+ /*
+ * Here we use the number returned by pci_spapr_map_irq to find a
+ * corresponding qemu_irq.
+ */
+ sPAPRPHBState *phb = opaque;
+
+ qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
+}
+
+static int spapr_phb_init(SysBusDevice *s)
+{
+ sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
+ int i;
+
+ /* Initialize the LSI table */
+ for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
+ qemu_irq qirq;
+ uint32_t num;
+
+ qirq = spapr_allocate_irq(0, &num);
+ if (!qirq) {
+ return -1;
+ }
+
+ phb->lsi_table[i].dt_irq = num;
+ phb->lsi_table[i].qirq = qirq;
+ }
+
+ return 0;
+}
+
+static int spapr_main_pci_host_init(PCIDevice *d)
+{
+ return 0;
+}
+
+static PCIDeviceInfo spapr_main_pci_host_info = {
+ .qdev.name = "spapr-pci-host-bridge",
+ .qdev.size = sizeof(PCIDevice),
+ .init = spapr_main_pci_host_init,
+};
+
+static void spapr_register_devices(void)
+{
+ sysbus_register_dev("spapr-pci-host-bridge", sizeof(sPAPRPHBState),
+ spapr_phb_init);
+ pci_qdev_register(&spapr_main_pci_host_info);
+}
+
+device_init(spapr_register_devices)
+
+static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+ switch (size) {
+ case 1:
+ return cpu_inb(addr);
+ case 2:
+ return cpu_inw(addr);
+ case 4:
+ return cpu_inl(addr);
+ }
+ assert(0);
+}
+
+static void spapr_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t data, unsigned size)
+{
+ switch (size) {
+ case 1:
+ cpu_outb(addr, data);
+ return;
+ case 2:
+ cpu_outw(addr, data);
+ return;
+ case 4:
+ cpu_outl(addr, data);
+ return;
+ }
+ assert(0);
+}
+
+static MemoryRegionOps spapr_io_ops = {
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .read = spapr_io_read,
+ .write = spapr_io_write
+};
+
+void spapr_create_phb(sPAPREnvironment *spapr,
+ const char *busname, uint64_t buid,
+ uint64_t mem_win_addr, uint64_t mem_win_size,
+ uint64_t io_win_addr)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+ sPAPRPHBState *phb;
+ PCIBus *bus;
+ char namebuf[strlen(busname)+11];
+
+ dev = qdev_create(NULL, "spapr-pci-host-bridge");
+ qdev_init_nofail(dev);
+ s = sysbus_from_qdev(dev);
+ phb = FROM_SYSBUS(sPAPRPHBState, s);
+
+ phb->mem_win_addr = mem_win_addr;
+
+ sprintf(namebuf, "%s-mem", busname);
+ memory_region_init(&phb->memspace, namebuf, INT64_MAX);
+
+ sprintf(namebuf, "%s-memwindow", busname);
+ memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
+ SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
+ memory_region_add_subregion(get_system_memory(), mem_win_addr,
+ &phb->memwindow);
+
+ phb->io_win_addr = io_win_addr;
+
+ /* On ppc, we only have MMIO no specific IO space from the CPU
+ * perspective. In theory we ought to be able to embed the PCI IO
+ * memory region direction in the system memory space. However,
+ * if any of the IO BAR subregions use the old_portio mechanism,
+ * that won't be processed properly unless accessed from the
+ * system io address space. This hack to bounce things via
+ * system_io works around the problem until all the users of
+ * old_portion are updated */
+ sprintf(namebuf, "%s-io", busname);
+ memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
+ /* FIXME: fix to support multiple PHBs */
+ memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
+
+ sprintf(namebuf, "%s-iowindow", busname);
+ memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
+ namebuf, SPAPR_PCI_IO_WIN_SIZE);
+ memory_region_add_subregion(get_system_memory(), io_win_addr,
+ &phb->iowindow);
+
+ phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
+ pci_spapr_set_irq,
+ pci_spapr_map_irq,
+ phb,
+ &phb->memspace, &phb->iospace,
+ PCI_DEVFN(0, 0),
+ SPAPR_PCI_NUM_LSI);
+
+ spapr_rtas_register("read-pci-config", rtas_read_pci_config);
+ spapr_rtas_register("write-pci-config", rtas_write_pci_config);
+ spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
+ spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
+
+ QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
+
+ /* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
+}
+
+/* Macros to operate with address in OF binding to PCI */
+#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
+#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
+#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
+#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
+#define b_ss(x) b_x((x), 24, 2) /* the space code */
+#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
+#define b_ddddd(x) b_x((x), 11, 5) /* device number */
+#define b_fff(x) b_x((x), 8, 3) /* function number */
+#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
+
+static uint32_t regtype_to_ss(uint8_t type)
+{
+ if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ return 3;
+ }
+ if (type == PCI_BASE_ADDRESS_SPACE_IO) {
+ return 1;
+ }
+ return 2;
+}
+
+int spapr_populate_pci_devices(sPAPRPHBState *phb,
+ uint32_t xics_phandle,
+ void *fdt)
+{
+ PCIBus *bus = phb->host_state.bus;
+ int bus_off, node_off = 0, devid, fn, i, n, devices;
+ DeviceState *qdev;
+ char nodename[256];
+ struct {
+ uint32_t hi;
+ uint64_t addr;
+ uint64_t size;
+ } __attribute__((packed)) reg[PCI_NUM_REGIONS + 1],
+ assigned_addresses[PCI_NUM_REGIONS];
+ uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
+ struct {
+ uint32_t hi;
+ uint64_t child;
+ uint64_t parent;
+ uint64_t size;
+ } __attribute__((packed)) ranges[] = {
+ {
+ cpu_to_be32(b_ss(1)), cpu_to_be64(0),
+ cpu_to_be64(phb->io_win_addr),
+ cpu_to_be64(memory_region_size(&phb->iospace)),
+ },
+ {
+ cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
+ cpu_to_be64(phb->mem_win_addr),
+ cpu_to_be64(memory_region_size(&phb->memwindow)),
+ },
+ };
+ uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
+ uint32_t interrupt_map_mask[] = {
+ cpu_to_be32(b_ddddd(-1)|b_fff(-1)), 0x0, 0x0, 0x0};
+ uint32_t interrupt_map[bus->nirq][7];
+
+ /* Start populating the FDT */
+ sprintf(nodename, "pci@%" PRIx64, phb->buid);
+ bus_off = fdt_add_subnode(fdt, 0, nodename);
+ if (bus_off < 0) {
+ return bus_off;
+ }
+
+#define _FDT(exp) \
+ do { \
+ int ret = (exp); \
+ if (ret < 0) { \
+ return ret; \
+ } \
+ } while (0)
+
+ /* Write PHB properties */
+ _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
+ _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
+ _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
+ _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
+ _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
+ _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
+ _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
+ _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
+ _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
+ _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
+ &interrupt_map_mask, sizeof(interrupt_map_mask)));
+
+ /* Populate PCI devices and allocate IRQs */
+ devices = 0;
+ QLIST_FOREACH(qdev, &bus->qbus.children, sibling) {
+ PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
+ int irq_index = pci_spapr_map_irq(dev, 0);
+ uint32_t *irqmap = interrupt_map[devices];
+ uint8_t *config = dev->config;
+
+ devid = dev->devfn >> 3;
+ fn = dev->devfn & 7;
+
+ sprintf(nodename, "pci@%u,%u", devid, fn);
+
+ /* Allocate interrupt from the map */
+ if (devid > bus->nirq) {
+ printf("Unexpected behaviour in spapr_populate_pci_devices,"
+ "wrong devid %u\n", devid);
+ exit(-1);
+ }
+ irqmap[0] = cpu_to_be32(b_ddddd(devid)|b_fff(fn));
+ irqmap[1] = 0;
+ irqmap[2] = 0;
+ irqmap[3] = 0;
+ irqmap[4] = cpu_to_be32(xics_phandle);
+ irqmap[5] = cpu_to_be32(phb->lsi_table[irq_index].dt_irq);
+ irqmap[6] = cpu_to_be32(0x8);
+
+ /* Add node to FDT */
+ node_off = fdt_add_subnode(fdt, bus_off, nodename);
+ if (node_off < 0) {
+ return node_off;
+ }
+
+ _FDT(fdt_setprop_cell(fdt, node_off, "vendor-id",
+ pci_get_word(&config[PCI_VENDOR_ID])));
+ _FDT(fdt_setprop_cell(fdt, node_off, "device-id",
+ pci_get_word(&config[PCI_DEVICE_ID])));
+ _FDT(fdt_setprop_cell(fdt, node_off, "revision-id",
+ pci_get_byte(&config[PCI_REVISION_ID])));
+ _FDT(fdt_setprop_cell(fdt, node_off, "class-code",
+ pci_get_long(&config[PCI_CLASS_REVISION]) >> 8));
+ _FDT(fdt_setprop_cell(fdt, node_off, "subsystem-id",
+ pci_get_word(&config[PCI_SUBSYSTEM_ID])));
+ _FDT(fdt_setprop_cell(fdt, node_off, "subsystem-vendor-id",
+ pci_get_word(&config[PCI_SUBSYSTEM_VENDOR_ID])));
+
+ /* Config space region comes first */
+ reg[0].hi = cpu_to_be32(
+ b_n(0) |
+ b_p(0) |
+ b_t(0) |
+ b_ss(0/*config*/) |
+ b_bbbbbbbb(0) |
+ b_ddddd(devid) |
+ b_fff(fn));
+ reg[0].addr = 0;
+ reg[0].size = 0;
+
+ n = 0;
+ for (i = 0; i < PCI_NUM_REGIONS; ++i) {
+ if (0 == dev->io_regions[i].size) {
+ continue;
+ }
+
+ reg[n+1].hi = cpu_to_be32(
+ b_n(0) |
+ b_p(0) |
+ b_t(0) |
+ b_ss(regtype_to_ss(dev->io_regions[i].type)) |
+ b_bbbbbbbb(0) |
+ b_ddddd(devid) |
+ b_fff(fn) |
+ b_rrrrrrrr(bars[i]));
+ reg[n+1].addr = 0;
+ reg[n+1].size = cpu_to_be64(dev->io_regions[i].size);
+
+ assigned_addresses[n].hi = cpu_to_be32(
+ b_n(1) |
+ b_p(0) |
+ b_t(0) |
+ b_ss(regtype_to_ss(dev->io_regions[i].type)) |
+ b_bbbbbbbb(0) |
+ b_ddddd(devid) |
+ b_fff(fn) |
+ b_rrrrrrrr(bars[i]));
+
+ /*
+ * Writing zeroes to assigned_addresses causes the guest kernel to
+ * reassign BARs
+ */
+ assigned_addresses[n].addr = cpu_to_be64(dev->io_regions[i].addr);
+ assigned_addresses[n].size = reg[n+1].size;
+
+ ++n;
+ }
+ _FDT(fdt_setprop(fdt, node_off, "reg", reg, sizeof(reg[0])*(n+1)));
+ _FDT(fdt_setprop(fdt, node_off, "assigned-addresses",
+ assigned_addresses,
+ sizeof(assigned_addresses[0])*(n)));
+ _FDT(fdt_setprop_cell(fdt, node_off, "interrupts",
+ pci_get_byte(&config[PCI_INTERRUPT_PIN])));
+
+ ++devices;
+ }
+
+ /* Write interrupt map */
+ _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
+ devices * sizeof(interrupt_map[0])));
+
+ return 0;
+}
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
new file mode 100644
index 0000000..4bb8dfb
--- /dev/null
+++ b/hw/spapr_pci.h
@@ -0,0 +1,59 @@
+/*
+ * QEMU SPAPR PCI BUS definitions
+ *
+ * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#if !defined(__HW_SPAPR_PCI_H__)
+#define __HW_SPAPR_PCI_H__
+
+#include "hw/pci_host.h"
+#include "hw/xics.h"
+
+typedef struct sPAPREnvironment sPAPREnvironment;
+
+#define SPAPR_PCI_NUM_LSI 16
+
+typedef struct sPAPRPHBState {
+ SysBusDevice busdev;
+ PCIHostState host_state;
+
+ uint64_t buid;
+
+ MemoryRegion memspace, iospace;
+ target_phys_addr_t mem_win_addr, io_win_addr;
+ MemoryRegion memwindow, iowindow;
+
+ struct {
+ uint32_t dt_irq;
+ qemu_irq qirq;
+ } lsi_table[SPAPR_PCI_NUM_LSI];
+
+ QLIST_ENTRY(sPAPRPHBState) list;
+} sPAPRPHBState;
+
+#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
+#define SPAPR_PCI_IO_WIN_SIZE 0x10000
+
+void spapr_create_phb(sPAPREnvironment *spapr,
+ const char *busname, uint64_t buid,
+ uint64_t mem_win_addr, uint64_t mem_win_size,
+ uint64_t io_win_addr);
+
+int spapr_populate_pci_devices(sPAPRPHBState *phb,
+ uint32_t xics_phandle,
+ void *fdt);
+
+#endif /* __HW_SPAPR_PCI_H__ */
--
1.7.7
^ permalink raw reply related
* [Qemu-devel] [PATCH 1/2] ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate
From: David Gibson @ 2011-10-31 1:51 UTC (permalink / raw)
To: agraf, anthony; +Cc: qemu-ppc, qemu-devel
The CPU state contains two bitmaps, initialized from the CPU spec
which describes which instructions are implemented on the CPU. A
couple of bits are defined which cover instructions (VSX and DFP)
which are not currently implemented in TCG. So far, these are only
used to handle the case of -cpu host because a KVM guest can use
the instructions when the host CPU supports them.
However, it's a mild layering violation to simply not include those
bits in the CPU descriptions for those CPUs that do support them,
just because we can't handle them in TCG. This patch corrects the
situation, so that the instruction bits _are_ shown correctly in the
cpu spec table, but are masked out from the cpu state in the non-KVM
case.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu.h | 26 ++++++++++++++++++++++++++
target-ppc/translate_init.c | 20 +++++++++++++++++---
2 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3ef4eba..e84108c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1856,6 +1856,30 @@ enum {
/* popcntw and popcntd instructions */
PPC_POPCNTWD = 0x8000000000000000ULL,
+#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
+ | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
+ | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
+ | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
+ | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
+ | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
+ | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
+ | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
+ | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
+ | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
+ | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
+ | PPC_MEM_SYNC | PPC_MEM_EIEIO \
+ | PPC_CACHE | PPC_CACHE_ICBI \
+ | PPC_CACHE_DCBZ | PPC_CACHE_DCBZT \
+ | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
+ | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
+ | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
+ | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
+ | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
+ | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
+ | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
+ | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
+ | PPC_POPCNTWD)
+
/* extended type values */
/* BookE 2.06 PowerPC specification */
@@ -1864,6 +1888,8 @@ enum {
PPC2_VSX = 0x0000000000000002ULL,
/* Decimal Floating Point (DFP) */
PPC2_DFP = 0x0000000000000004ULL,
+
+#define PPC_TCG_INSNS2 (PPC2_BOOKE206)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4dfd7f3..854bc65 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6519,9 +6519,7 @@ static void init_proc_970MP (CPUPPCState *env)
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI | \
PPC_POPCNTB | PPC_POPCNTWD)
-/* FIXME: Should also have PPC2_VSX and PPC2_DFP, but we don't
- * implement those in TCG yet */
-#define POWERPC_INSNS2_POWER7 (PPC_NONE)
+#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP)
#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
@@ -9848,6 +9846,22 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
env->bus_model = def->bus_model;
env->insns_flags = def->insns_flags;
env->insns_flags2 = def->insns_flags2;
+ if (!kvm_enabled()) {
+ /* TCG doesn't (yet) emulate some groups of instructions that
+ * are implemented on some otherwise supported CPUs (e.g. VSX
+ * and decimal floating point instructions on POWER7). We
+ * remove unsupported instruction groups from the cpu state's
+ * instruction masks and hope the guest can cope. For at
+ * least the pseries machine, the unavailability of these
+ * instructions can be advertise to the guest via the device
+ * tree.
+ *
+ * FIXME: we should have a similar masking for CPU features
+ * not accessible under KVM, but so far, there aren't any of
+ * those. */
+ env->insns_flags &= PPC_TCG_INSNS;
+ env->insns_flags2 &= PPC_TCG_INSNS2;
+ }
env->flags = def->flags;
env->bfd_mach = def->bfd_mach;
env->check_pow = def->check_pow;
--
1.7.7
^ permalink raw reply related
* Re: [PATCH 5/5] drm/i915: collect more per ring error state
From: Ben Widawsky @ 2011-10-31 1:51 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
In-Reply-To: <1320001932-1846-5-git-send-email-daniel.vetter@ffwll.ch>
On Sun, 30 Oct 2011 20:12:12 +0100
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Based on a patch by Ben Widawsky, but with different colors
> for the bikeshed.
>
> In contrast to Ben's patch this one doesn't add the fault regs.
> Afaics they're for the optional page fault support which
> - we're not enabling
> - and which seems to be unsupported by the hw team. Recent bspec
> lacks tons of information about this that the public docs released
> half a year back still contain.
>
> Also dump ring HEAD/TAIL registers - I've recently seen a few
> error_state where just guessing these is not good enough.
>
> v2: Also dump INSTPM for every ring.
>
> v3: Fix a few really silly goof-ups spotted by Chris Wilson.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
^ permalink raw reply
* Re: [PATCH 4/5] drm/i915: refactor ring error state capture to use arrays
From: Ben Widawsky @ 2011-10-31 1:50 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Daniel Vetter, intel-gfx
In-Reply-To: <20111030184750.04997faf@bwidawsk.net>
On Sun, 30 Oct 2011 18:47:50 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:
> On Sun, 30 Oct 2011 20:12:11 +0100
> Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
>
> > The code already got unwindy and we want to dump more per-ring
> > registers.
> >
> > Only functional change is that we now also capture the video
> > ring registers on ilk.
> >
> > v2: fixup a refactor fumble spotted by Chris Wilson.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 55 ++++++++++++++-------------
> > drivers/gpu/drm/i915/i915_drv.h | 20 ++-------
> > drivers/gpu/drm/i915/i915_irq.c | 70 ++++++++++++++++++-----------------
> > drivers/gpu/drm/i915/i915_reg.h | 11 +----
> > 4 files changed, 73 insertions(+), 83 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 9e6cd50..290aece 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -735,6 +735,26 @@ static void print_error_buffers(struct seq_file *m,
> > }
> > }
> >
> > +static void i915_ring_error_state(struct seq_file *m,
> > + struct drm_device *dev,
> > + struct drm_i915_error_state *error,
> > + unsigned ring)
> > +{
> > + seq_printf(m, "%s command stream:\n", ring_str(ring));
> > + seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
> > + seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
> > + seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
> > + seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
> > + if (ring == RCS) {
> > + if (INTEL_INFO(dev)->gen >= 4) {
> > + seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
> > + seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
> > + }
> > + seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
> > + }
> > + seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
> > +}
> > +
> > static int i915_error_state(struct seq_file *m, void *unused)
> > {
> > struct drm_info_node *node = (struct drm_info_node *) m->private;
> > @@ -757,36 +777,19 @@ static int i915_error_state(struct seq_file *m, void *unused)
> > seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
> > seq_printf(m, "EIR: 0x%08x\n", error->eir);
> > seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
> > - if (INTEL_INFO(dev)->gen >= 6) {
> > - seq_printf(m, "ERROR: 0x%08x\n", error->error);
> > - seq_printf(m, "Blitter command stream:\n");
> > - seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
> > - seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
> > - seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
> > - seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
> > - seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
> > - seq_printf(m, "Video (BSD) command stream:\n");
> > - seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
> > - seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
> > - seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
> > - seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
> > - seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
> > - }
> > - seq_printf(m, "Render command stream:\n");
> > - seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
> > - seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
> > - seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
> > - seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
> > - if (INTEL_INFO(dev)->gen >= 4) {
> > - seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
> > - seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
> > - }
> > - seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
> > - seq_printf(m, " seqno: 0x%08x\n", error->seqno);
> >
> > for (i = 0; i < dev_priv->num_fence_regs; i++)
> > seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
> >
> > + if (INTEL_INFO(dev)->gen >= 6)
> > + seq_printf(m, "ERROR: 0x%08x\n", error->error);
> > +
> > + i915_ring_error_state(m, dev, error, RCS);
> > + if (HAS_BLT(dev))
> > + i915_ring_error_state(m, dev, error, BCS);
> > + if (HAS_BSD(dev))
> > + i915_ring_error_state(m, dev, error, VCS);
> > +
> > if (error->active_bo)
> > print_error_buffers(m, "Active",
> > error->active_bo,
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index d2da91f..17617c1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -151,25 +151,15 @@ struct drm_i915_error_state {
> > u32 eir;
> > u32 pgtbl_er;
> > u32 pipestat[I915_MAX_PIPES];
> > - u32 ipeir;
> > - u32 ipehr;
> > - u32 instdone;
> > - u32 acthd;
> > + u32 ipeir[I915_NUM_RINGS];
> > + u32 ipehr[I915_NUM_RINGS];
> > + u32 instdone[I915_NUM_RINGS];
> > + u32 acthd[I915_NUM_RINGS];
> > u32 error; /* gen6+ */
> > - u32 bcs_acthd; /* gen6+ blt engine */
> > - u32 bcs_ipehr;
> > - u32 bcs_ipeir;
> > - u32 bcs_instdone;
> > - u32 bcs_seqno;
> > - u32 vcs_acthd; /* gen6+ bsd engine */
> > - u32 vcs_ipehr;
> > - u32 vcs_ipeir;
> > - u32 vcs_instdone;
> > - u32 vcs_seqno;
> > u32 instpm;
> > u32 instps;
> > u32 instdone1;
> > - u32 seqno;
> > + u32 seqno[I915_NUM_RINGS];
> > u64 bbaddr;
> > u64 fence[I915_MAX_NUM_FENCES];
> > struct timeval time;
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 3cd85dd..70e67f1 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -876,6 +876,32 @@ i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
> > return NULL;
> > }
> >
> > +static void i915_record_ring_state(struct drm_device *dev,
> > + struct drm_i915_error_state *error,
> > + struct intel_ring_buffer *ring)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + if (INTEL_INFO(dev)->gen >= 4) {
> > + error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
> > + error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
> > + error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
> > + if (ring->id == RCS) {
> > + error->instps = I915_READ(INSTPS);
> > + error->instdone1 = I915_READ(INSTDONE1);
> > + error->bbaddr = I915_READ64(BB_ADDR);
> > + }
> > + } else {
> > + error->ipeir[ring->id] = I915_READ(IPEIR);
> > + error->ipehr[ring->id] = I915_READ(IPEHR);
> > + error->instdone[ring->id] = I915_READ(INSTDONE);
> > + error->bbaddr = 0;
> > + }
> > +
> > + error->seqno[ring->id] = ring->get_seqno(ring);
> > + error->acthd[ring->id] = intel_ring_get_active_head(ring);
> > +}
> > +
> > /**
> > * i915_capture_error_state - capture an error record for later analysis
> > * @dev: drm device
> > @@ -909,47 +935,23 @@ static void i915_capture_error_state(struct drm_device *dev)
> > DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
> > dev->primary->index);
> >
> > - error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
> > error->eir = I915_READ(EIR);
> > error->pgtbl_er = I915_READ(PGTBL_ER);
> > for_each_pipe(pipe)
> > error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
> > error->instpm = I915_READ(INSTPM);
> > - error->error = 0;
> > - if (INTEL_INFO(dev)->gen >= 6) {
> > +
> > + if (INTEL_INFO(dev)->gen >= 6)
> > error->error = I915_READ(ERROR_GEN6);
> > + else
> > + error->error = 0;
> > +
> > + i915_record_ring_state(dev, error, &dev_priv->ring[RCS]);
> > + if (HAS_BLT(dev))
> > + i915_record_ring_state(dev, error, &dev_priv->ring[BCS]);
> > + if (HAS_BSD(dev))
> > + i915_record_ring_state(dev, error, &dev_priv->ring[VCS]);
> >
> > - error->bcs_acthd = I915_READ(BCS_ACTHD);
> > - error->bcs_ipehr = I915_READ(BCS_IPEHR);
> > - error->bcs_ipeir = I915_READ(BCS_IPEIR);
> > - error->bcs_instdone = I915_READ(BCS_INSTDONE);
> > - error->bcs_seqno = 0;
> > - if (dev_priv->ring[BCS].get_seqno)
> > - error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
> > -
> > - error->vcs_acthd = I915_READ(VCS_ACTHD);
> > - error->vcs_ipehr = I915_READ(VCS_IPEHR);
> > - error->vcs_ipeir = I915_READ(VCS_IPEIR);
> > - error->vcs_instdone = I915_READ(VCS_INSTDONE);
> > - error->vcs_seqno = 0;
> > - if (dev_priv->ring[VCS].get_seqno)
> > - error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
> > - }
> > - if (INTEL_INFO(dev)->gen >= 4) {
> > - error->ipeir = I915_READ(IPEIR_I965);
> > - error->ipehr = I915_READ(IPEHR_I965);
> > - error->instdone = I915_READ(INSTDONE_I965);
> > - error->instps = I915_READ(INSTPS);
> > - error->instdone1 = I915_READ(INSTDONE1);
> > - error->acthd = I915_READ(ACTHD_I965);
> > - error->bbaddr = I915_READ64(BB_ADDR);
> > - } else {
> > - error->ipeir = I915_READ(IPEIR);
> > - error->ipehr = I915_READ(IPEHR);
> > - error->instdone = I915_READ(INSTDONE);
> > - error->acthd = I915_READ(ACTHD);
> > - error->bbaddr = 0;
> > - }
> > i915_gem_record_fences(dev, error);
> >
> > /* Record the active batch and ring buffers */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 5a09416..c292957 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -352,6 +352,9 @@
> > #define IPEIR_I965 0x02064
> > #define IPEHR_I965 0x02068
> > #define INSTDONE_I965 0x0206c
> > +#define RING_IPEIR(base) ((base)+0x64)
> > +#define RING_IPEHR(base) ((base)+0x68)
> > +#define RING_INSTDONE(base) ((base)+0x6c)
> > #define INSTPS 0x02070 /* 965+ only */
> > #define INSTDONE1 0x0207c /* 965+ only */
> > #define ACTHD_I965 0x02074
> > @@ -365,14 +368,6 @@
> > #define INSTDONE 0x02090
> > #define NOPID 0x02094
> > #define HWSTAM 0x02098
> > -#define VCS_INSTDONE 0x1206C
> > -#define VCS_IPEIR 0x12064
> > -#define VCS_IPEHR 0x12068
> > -#define VCS_ACTHD 0x12074
> > -#define BCS_INSTDONE 0x2206C
> > -#define BCS_IPEIR 0x22064
> > -#define BCS_IPEHR 0x22068
> > -#define BCS_ACTHD 0x22074
> >
> > #define ERROR_GEN6 0x040a0
> >
>
> This patch looks a lot like an earlier patch of mine except your ring ID
> changes made it quite nice. I wonder why you didn't keep my INSTPS, and INSTPM
> per ring?
>
> Ben
Ah, just saw patch 5... I guess I find this a little weird way to break
it up, but I think I did a much worse job in my patches.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
^ permalink raw reply
* Re: [Qemu-devel] [PULL 0/3] 128-bit support for the memory API
From: David Gibson @ 2011-10-31 0:36 UTC (permalink / raw)
To: Avi Kivity; +Cc: Blue Swirl, qemu-devel
In-Reply-To: <4EAD5D07.6060004@redhat.com>
On Sun, Oct 30, 2011 at 04:19:51PM +0200, Avi Kivity wrote:
> On 10/30/2011 04:12 PM, Anthony Liguori wrote:
> > On 10/30/2011 09:02 AM, Avi Kivity wrote:
> >> This somewhat controversial patchset converts internal arithmetic in the
> >> memory API to 128 bits.
> >>
> >> It has been argued that with careful coding we can make 64-bit work as
> >> well. I don't think this is true in general - a memory router can
> >> adjust
> >> addresses either forwards or backwards, and some buses (PCIe) need the
> >> full 64-bit space - though it's probably the case for all the
> >> configurations
> >> we support today. Regardless, the need for careful coding means
> >> subtle bugs,
> >> which I don't want in a core API that is driven by guest supplied
> >> values.
> >
> > The primary need for signed arithmetic is aliases, correct?
>
> > Where do we actually make use of this in practice? I think having
> > negative address spaces is a weird aspect of the memory api and wonder
> > if refactoring it away is a better solution tot he problem.
>
> There is no direct use of signed arithmetic in the API (just in the
> implementation). Aliases can cause a region to move in either the
> positive or negative direction, and this requires either signed
> arithmetic or special casing the two directions.
You keep saying we need signed arithmetic for this, but it's not
really true. *If* you see aliases as shifting the entire aliases
address space w.r.t., then just allowing a window to show through, you
get negative offsets, yes, but that's by no means the only way t think
about it.
It's basically one spot - the alias handling in render_memory_region()
- that generates a negative start intermediate. I'm convinced it's
pretty straightforward to remove this - making a patch for it just
hasn't bubbled to the top of my priority queue, though.
> Signed arithmetic is not the only motivation - overflow is another.
> Nothing prevents a user from placing a 64-bit 4k BAR at address
> ffff_ffff_ffff_f000; we could move to base/limit representation, but
> that will likely cause its own bugs. Finally, we should be able to
> represent both a 0-sized region and a 2^64 sized region.
Note that an (inclusive) start/end representation also cannot
represent a 0 sized region.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 3/3] pseries: Add partial support for PCI
From: David Gibson @ 2011-10-31 1:48 UTC (permalink / raw)
To: Alexander Graf; +Cc: qemu-ppc, qemu-devel
In-Reply-To: <16113B7F-3EB6-45D5-A7F7-107F07C84382@suse.de>
On Sun, Oct 30, 2011 at 06:06:51PM +0100, Alexander Graf wrote:
>
> On 28.10.2011, at 03:56, David Gibson wrote:
>
> > From: Alexey Kardashevskiy <aik@au1.ibm.com>
> >
> > This patch adds a PCI bus to the pseries machine. This instantiates
> > the qemu generic PCI bus code, advertises a PCI host bridge in the
> > guest's device tree and implements the RTAS methods specified by PAPR
> > to access PCI config space. It also sets up the memory regions we
> > need to provide windows into the PCI memory and IO space, and
> > advertises those to the guest.
> >
> > However, because qemu can't yet emulate an IOMMU, which is mandatory on
> > pseries, PCI devices which use DMA (i.e. most of them) will not work with
> > this code alone. Still, this is enough to support the virtio_pci device
> > (which probably _should_ use emulated PCI DMA, but is specced to use
> > direct hypervisor access to guest physical memory instead).
> >
> > Signed-off-by: Alexey Kardashevskiy <aik@au1.ibm.com>
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> > Makefile.target | 3 +
> > hw/spapr.c | 36 ++++-
> > hw/spapr.h | 2 +
> > hw/spapr_pci.c | 515 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > hw/spapr_pci.h | 59 +++++++
> > 5 files changed, 611 insertions(+), 4 deletions(-)
> > create mode 100644 hw/spapr_pci.c
> > create mode 100644 hw/spapr_pci.h
> >
> > diff --git a/Makefile.target b/Makefile.target
> > index fe5f6f7..f3eb842 100644
> > --- a/Makefile.target
> > +++ b/Makefile.target
> > @@ -248,6 +248,9 @@ obj-ppc-y += ppc_newworld.o
> > # IBM pSeries (sPAPR)
> > obj-ppc-$(CONFIG_PSERIES) += spapr.o spapr_hcall.o spapr_rtas.o spapr_vio.o
> > obj-ppc-$(CONFIG_PSERIES) += xics.o spapr_vty.o spapr_llan.o spapr_vscsi.o
> > +ifeq ($(CONFIG_PCI),y)
> > +obj-ppc-$(CONFIG_PSERIES) += spapr_pci.o device-hotplug.o pci-hotplug.o
> > +endif
>
> You make it conditional here ...
>
> > # PowerPC 4xx boards
> > obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
> > obj-ppc-y += ppc440.o ppc440_bamboo.o
> > diff --git a/hw/spapr.c b/hw/spapr.c
> > index 933af32..bdaa938 100644
> > --- a/hw/spapr.c
> > +++ b/hw/spapr.c
> > @@ -39,10 +39,12 @@
> >
> > #include "hw/spapr.h"
> > #include "hw/spapr_vio.h"
> > +#include "hw/spapr_pci.h"
> > #include "hw/xics.h"
> >
> > #include "kvm.h"
> > #include "kvm_ppc.h"
> > +#include "pci.h"
>
> ... but not here. Just throw away the condition above. We don't need
> to support -M pseries without PCI.
Good point, revision in next version.
[snip]
> > + spapr_rtas_register("read-pci-config", rtas_read_pci_config);
> > + spapr_rtas_register("write-pci-config", rtas_write_pci_config);
> > + spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
> > + spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
> > +
> > + /*
> > + * This is a workaround to disable PCI devices resetting as we do
> > + * BAR allocation on the QEMU side and reset destroys this
> > + * configuration.
> > + */
> > + bus->qbus.info->reset = NULL;
>
> Eh. What? So you're breaking reset for all PCI devices? How do you
> reboot?
Oops. That leaked in fromt he patch which adds PCI BAR allocation
(it's a workaround for the reset clobbering our allocations which we
haven't had a chance to fix properly yet). Put back where it belongs
now.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 3/5] drm/i915: switch ring->id to be a real id
From: Ben Widawsky @ 2011-10-31 1:48 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
In-Reply-To: <1320001932-1846-3-git-send-email-daniel.vetter@ffwll.ch>
On Sun, 30 Oct 2011 20:12:10 +0100
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> ... and add a helpr function for the places where we want a flag.
>
> This way we can use ring->id to index into arrays.
>
> v2: Resurrect the missing beautification-space Chris Wilson noted.
> I'm moving this space around because I'll reuse ring_str in the next
> patch.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
^ permalink raw reply
* Re: [PATCH 4/5] drm/i915: refactor ring error state capture to use arrays
From: Ben Widawsky @ 2011-10-31 1:47 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
In-Reply-To: <1320001932-1846-4-git-send-email-daniel.vetter@ffwll.ch>
On Sun, 30 Oct 2011 20:12:11 +0100
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> The code already got unwindy and we want to dump more per-ring
> registers.
>
> Only functional change is that we now also capture the video
> ring registers on ilk.
>
> v2: fixup a refactor fumble spotted by Chris Wilson.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 55 ++++++++++++++-------------
> drivers/gpu/drm/i915/i915_drv.h | 20 ++-------
> drivers/gpu/drm/i915/i915_irq.c | 70 ++++++++++++++++++-----------------
> drivers/gpu/drm/i915/i915_reg.h | 11 +----
> 4 files changed, 73 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9e6cd50..290aece 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -735,6 +735,26 @@ static void print_error_buffers(struct seq_file *m,
> }
> }
>
> +static void i915_ring_error_state(struct seq_file *m,
> + struct drm_device *dev,
> + struct drm_i915_error_state *error,
> + unsigned ring)
> +{
> + seq_printf(m, "%s command stream:\n", ring_str(ring));
> + seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
> + seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
> + seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
> + seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
> + if (ring == RCS) {
> + if (INTEL_INFO(dev)->gen >= 4) {
> + seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
> + seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
> + }
> + seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
> + }
> + seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
> +}
> +
> static int i915_error_state(struct seq_file *m, void *unused)
> {
> struct drm_info_node *node = (struct drm_info_node *) m->private;
> @@ -757,36 +777,19 @@ static int i915_error_state(struct seq_file *m, void *unused)
> seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
> seq_printf(m, "EIR: 0x%08x\n", error->eir);
> seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
> - if (INTEL_INFO(dev)->gen >= 6) {
> - seq_printf(m, "ERROR: 0x%08x\n", error->error);
> - seq_printf(m, "Blitter command stream:\n");
> - seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
> - seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
> - seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
> - seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
> - seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
> - seq_printf(m, "Video (BSD) command stream:\n");
> - seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
> - seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
> - seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
> - seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
> - seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
> - }
> - seq_printf(m, "Render command stream:\n");
> - seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
> - seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
> - seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
> - seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
> - if (INTEL_INFO(dev)->gen >= 4) {
> - seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
> - seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
> - }
> - seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
> - seq_printf(m, " seqno: 0x%08x\n", error->seqno);
>
> for (i = 0; i < dev_priv->num_fence_regs; i++)
> seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
>
> + if (INTEL_INFO(dev)->gen >= 6)
> + seq_printf(m, "ERROR: 0x%08x\n", error->error);
> +
> + i915_ring_error_state(m, dev, error, RCS);
> + if (HAS_BLT(dev))
> + i915_ring_error_state(m, dev, error, BCS);
> + if (HAS_BSD(dev))
> + i915_ring_error_state(m, dev, error, VCS);
> +
> if (error->active_bo)
> print_error_buffers(m, "Active",
> error->active_bo,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d2da91f..17617c1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -151,25 +151,15 @@ struct drm_i915_error_state {
> u32 eir;
> u32 pgtbl_er;
> u32 pipestat[I915_MAX_PIPES];
> - u32 ipeir;
> - u32 ipehr;
> - u32 instdone;
> - u32 acthd;
> + u32 ipeir[I915_NUM_RINGS];
> + u32 ipehr[I915_NUM_RINGS];
> + u32 instdone[I915_NUM_RINGS];
> + u32 acthd[I915_NUM_RINGS];
> u32 error; /* gen6+ */
> - u32 bcs_acthd; /* gen6+ blt engine */
> - u32 bcs_ipehr;
> - u32 bcs_ipeir;
> - u32 bcs_instdone;
> - u32 bcs_seqno;
> - u32 vcs_acthd; /* gen6+ bsd engine */
> - u32 vcs_ipehr;
> - u32 vcs_ipeir;
> - u32 vcs_instdone;
> - u32 vcs_seqno;
> u32 instpm;
> u32 instps;
> u32 instdone1;
> - u32 seqno;
> + u32 seqno[I915_NUM_RINGS];
> u64 bbaddr;
> u64 fence[I915_MAX_NUM_FENCES];
> struct timeval time;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3cd85dd..70e67f1 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -876,6 +876,32 @@ i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
> return NULL;
> }
>
> +static void i915_record_ring_state(struct drm_device *dev,
> + struct drm_i915_error_state *error,
> + struct intel_ring_buffer *ring)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + if (INTEL_INFO(dev)->gen >= 4) {
> + error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
> + error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
> + error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
> + if (ring->id == RCS) {
> + error->instps = I915_READ(INSTPS);
> + error->instdone1 = I915_READ(INSTDONE1);
> + error->bbaddr = I915_READ64(BB_ADDR);
> + }
> + } else {
> + error->ipeir[ring->id] = I915_READ(IPEIR);
> + error->ipehr[ring->id] = I915_READ(IPEHR);
> + error->instdone[ring->id] = I915_READ(INSTDONE);
> + error->bbaddr = 0;
> + }
> +
> + error->seqno[ring->id] = ring->get_seqno(ring);
> + error->acthd[ring->id] = intel_ring_get_active_head(ring);
> +}
> +
> /**
> * i915_capture_error_state - capture an error record for later analysis
> * @dev: drm device
> @@ -909,47 +935,23 @@ static void i915_capture_error_state(struct drm_device *dev)
> DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
> dev->primary->index);
>
> - error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
> error->eir = I915_READ(EIR);
> error->pgtbl_er = I915_READ(PGTBL_ER);
> for_each_pipe(pipe)
> error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
> error->instpm = I915_READ(INSTPM);
> - error->error = 0;
> - if (INTEL_INFO(dev)->gen >= 6) {
> +
> + if (INTEL_INFO(dev)->gen >= 6)
> error->error = I915_READ(ERROR_GEN6);
> + else
> + error->error = 0;
> +
> + i915_record_ring_state(dev, error, &dev_priv->ring[RCS]);
> + if (HAS_BLT(dev))
> + i915_record_ring_state(dev, error, &dev_priv->ring[BCS]);
> + if (HAS_BSD(dev))
> + i915_record_ring_state(dev, error, &dev_priv->ring[VCS]);
>
> - error->bcs_acthd = I915_READ(BCS_ACTHD);
> - error->bcs_ipehr = I915_READ(BCS_IPEHR);
> - error->bcs_ipeir = I915_READ(BCS_IPEIR);
> - error->bcs_instdone = I915_READ(BCS_INSTDONE);
> - error->bcs_seqno = 0;
> - if (dev_priv->ring[BCS].get_seqno)
> - error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
> -
> - error->vcs_acthd = I915_READ(VCS_ACTHD);
> - error->vcs_ipehr = I915_READ(VCS_IPEHR);
> - error->vcs_ipeir = I915_READ(VCS_IPEIR);
> - error->vcs_instdone = I915_READ(VCS_INSTDONE);
> - error->vcs_seqno = 0;
> - if (dev_priv->ring[VCS].get_seqno)
> - error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
> - }
> - if (INTEL_INFO(dev)->gen >= 4) {
> - error->ipeir = I915_READ(IPEIR_I965);
> - error->ipehr = I915_READ(IPEHR_I965);
> - error->instdone = I915_READ(INSTDONE_I965);
> - error->instps = I915_READ(INSTPS);
> - error->instdone1 = I915_READ(INSTDONE1);
> - error->acthd = I915_READ(ACTHD_I965);
> - error->bbaddr = I915_READ64(BB_ADDR);
> - } else {
> - error->ipeir = I915_READ(IPEIR);
> - error->ipehr = I915_READ(IPEHR);
> - error->instdone = I915_READ(INSTDONE);
> - error->acthd = I915_READ(ACTHD);
> - error->bbaddr = 0;
> - }
> i915_gem_record_fences(dev, error);
>
> /* Record the active batch and ring buffers */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5a09416..c292957 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -352,6 +352,9 @@
> #define IPEIR_I965 0x02064
> #define IPEHR_I965 0x02068
> #define INSTDONE_I965 0x0206c
> +#define RING_IPEIR(base) ((base)+0x64)
> +#define RING_IPEHR(base) ((base)+0x68)
> +#define RING_INSTDONE(base) ((base)+0x6c)
> #define INSTPS 0x02070 /* 965+ only */
> #define INSTDONE1 0x0207c /* 965+ only */
> #define ACTHD_I965 0x02074
> @@ -365,14 +368,6 @@
> #define INSTDONE 0x02090
> #define NOPID 0x02094
> #define HWSTAM 0x02098
> -#define VCS_INSTDONE 0x1206C
> -#define VCS_IPEIR 0x12064
> -#define VCS_IPEHR 0x12068
> -#define VCS_ACTHD 0x12074
> -#define BCS_INSTDONE 0x2206C
> -#define BCS_IPEIR 0x22064
> -#define BCS_IPEHR 0x22068
> -#define BCS_ACTHD 0x22074
>
> #define ERROR_GEN6 0x040a0
>
This patch looks a lot like an earlier patch of mine except your ring ID
changes made it quite nice. I wonder why you didn't keep my INSTPS, and INSTPM
per ring?
Ben
^ permalink raw reply
* [GIT PULL] GIC DT binding support
From: Rob Herring @ 2011-10-31 1:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201110310131.53251.arnd@arndb.de>
Arnd,
On 10/30/2011 07:31 PM, Arnd Bergmann wrote:
> On Friday 28 October 2011, Rob Herring wrote:
>> Merge branch 'for-sfr' of
>> git://openlinux.windriver.com/people/paulg/linux-next into HEAD
>> (2011-10-28 15:51:07 -0500)
>>
>
> Rob, I think there is no chance that this is working out.
>
> I've just spent a few hours trying to resolve all the dependencies from this,
> but I don't think it will work out, unless Linus pulls that tree very soon,
> which I think is very unlikely.
>
> Have you made sure that Paul even considers this branch stable?
No.
> Normally this kind of change gets pushed *last* in the merge window, to make
> it possible to fix up all the stuff that breaks. This means I cannot
> wait for the branch to get merged upstream before send a pull request for
> my next/dt and next/soc branches.
>
> Do you even depend on that branch? It seems to me that you merely have a
> conflict, not a dependency, so why do you even try fixing it up?
Sorry about this. I thought I needed to fix the linux-next build
breakage. I only depend on it when export.h gets introduced, so I can
drop that out. All the other dependencies are in Linus' master now. I
pushed out a branch without Paul's branch:
I get to Connect around 2PM tomorrow, we can discuss further then if
necessary.
The following changes since commit ce949717b559709423c1ef716a9db16d1dcadaed:
Merge git://github.com/rustyrussell/linux (2011-10-29 07:52:16 -0700)
are available in the git repository at:
git://sources.calxeda.com/kernel/linux.git gic-dt-v2
Rob Herring (5):
of/irq: introduce of_irq_init
irq: support domains with non-zero hwirq base
ARM: gic: add irq_domain support
ARM: gic: add OF based initialization
ARM: gic: fix irq_alloc_descs handling for sparse irq
Documentation/devicetree/bindings/arm/gic.txt | 55 +++++++
arch/arm/common/Kconfig | 1 +
arch/arm/common/gic.c | 187
++++++++++++++++---------
arch/arm/include/asm/hardware/gic.h | 10 +-
drivers/of/irq.c | 107 ++++++++++++++
include/linux/irqdomain.h | 16 ++-
include/linux/of_irq.h | 3 +
kernel/irq/irqdomain.c | 12 +-
8 files changed, 319 insertions(+), 72 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/gic.txt
Rob
^ permalink raw reply
* Build Error Report
From: Masahiro Inoue @ 2011-10-31 1:35 UTC (permalink / raw)
To: linux-wireless
Hello,
The build error occurs by compat-wireless-2011-10-30.
My kernel is 2.6.27.
LD /home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c/built-in.o
CC [M] /home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c/atl1c_main.o
/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c/atl1c_main.c: In function 'atl1c_tx_map':
/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c/atl1c_main.c:2199: error: implicit declaration of function 'skb_frag_size'
/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c/atl1c_main.c: At top level:
/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c/atl1c_main.c:2926: warning: useless storage class specifier in empty declaration
/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c/atl1c_main.c:2926: warning: empty declaration
make[4]: *** [/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c/atl1c_main.o] Error 1
make[3]: *** [/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros/atl1c] Error 2
make[2]: *** [/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30/drivers/net/ethernet/atheros] Error 2
make[1]: *** [_module_/home/miyabi/test/compat-wireless/compat-wireless-2011-10-30] Error 2
make[1]: Leaving directory `/usr/src/kernels/2.6.27-71vl5-x86_64'
make: *** [modules] Error 2
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