* Re: [Qemu-devel] [PATCH] acl: Fix use after free in qemu_acl_reset()
From: Stefan Hajnoczi @ 2011-10-31 11:55 UTC (permalink / raw)
To: Markus Armbruster; +Cc: qemu-trivial, qemu-devel
In-Reply-To: <1319814422-17952-1-git-send-email-armbru@redhat.com>
On Fri, Oct 28, 2011 at 05:07:02PM +0200, Markus Armbruster wrote:
> Reproducer:
>
> $ MALLOC_PERTURB_=234 qemu-system-x86_64 -vnc :0,acl,sasl [...]
> QEMU 0.15.50 monitor - type 'help' for more information
> (qemu) acl_add vnc.username fred allow
> acl: added rule at position 1
> (qemu) acl_reset vnc.username
> Segmentation fault (core dumped)
>
> Spotted by Coverity.
>
> Signed-off-by: Markus Armbruster <armbru@redhat.com>
> ---
> acl.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
Thanks, applied to the trivial patches -next tree:
http://repo.or.cz/w/qemu/stefanha.git/shortlog/refs/heads/trivial-patches-next
Stefan
^ permalink raw reply
* Re: [PATCH 01/11] drm: add plane support
From: Inki Dae @ 2011-10-31 11:40 UTC (permalink / raw)
To: intel-gfx
In-Reply-To: <loom.20111027T153300-610@post.gmane.org>
Hi, all.
SW Kim <devusr.opensw <at> gmail.com> writes:
>
> Daniel Vetter <daniel <at> ffwll.ch> writes:
>
> [snip]
>
> > > struct drm_mode_fb_cmd2 {
> > > __u32 fb_id;
> > > __u32 width, height;
> > > __u32 pixel_format; /* fourcc code from videodev2.h */
> > > __u64 priv; /* private data, depends on pixelformat */
> > >
>
> [snip]
>
> > > struct {
> > > __u32 pitch;
> > > /* driver specific handle */
> > > __u32 handle;
> >
> > Why not just add a
> > __u32 offset;
> > __u32 rsvd;
>
> For normal NV12 format, I agree that just offset is enough.
> But considering more specific format like NV12M, that has two separated
memory
> spaces, IMHO, it needs handle per each plane.
>
> Each plane of NV12M has it own base address and space between these two
memory
> spaces can be used by others.
>
> You can refer following link about NV12M used by V4L2.
> http://linuxtv.org/downloads/v4l-dvb-apis/V4L2-PIX-FMT-NV12M.html
>
> > and call it a day. This thing is pretty big already, so that bloat doesn't
> > matter that much. Maybe spec that buffer[0].offset must be zero. With that
> > you can also do I420 with the following layout
> > +-------+
> > |YYYYYYY|
> > |YYYYYYY|
> > |YYYYYYY|
> > |YYYYYYY|
> > +---+---+
> > |UUU|VVV|
> > |UUU|VVV|
> > +---+---+
> >
> > i.e. stride_U == stride_V, with their lines meshed into one line.
> > -Daniel
> >
> > > } buffer[16];
>
> and just question, is there any meaning about buffer array size 16?
>
> > > };
>
> [snip]
>
> Thanks and Regards,
> - SW Kim
>
I have a opinion for multi planer. before that, I'd like to mention some
considerations.
I think adding any variables such as offset or handle(as plane count) to
drm_mode_fb_cmd2 structure could occurs that in application point of view,
user could be confused because with the ways above, user needs to allocate
buffers as plane count(it depends on pixel format) and also user should know
buffer size according to pixel format. so I think it's good way that user sets
only pixel format and resolution(width, height) and then specific gem
framework allocates buffers according to pixel format as plane count and then
user sets the gem handle to drm_mode_fb_cmd2 structure. specific gem framework
could get all buffers through only the gem handle.
below is my simple idea.
1. user requests buffer allocation with pixel format and resolution through
gem framework.
2. gem framework checks pixel format.
3. specific gem framework allocates buffers as plane count according to the
pixel format. (please, know that gem framework provides just interface so
acctual implementation would be done at specific gem framework)
4. user gets the gem handle from gem framework.
5. user sets the gem handle to specific drm framebuffer through
drm_mode_addfb2 function.
6. user requests setcrtc with fb id and crtc id.
7. drm framework sets framebuffer(corresponding to fb id) to drm_mode_set.
8. crtc calls set_config callbacks to configure hardware.
9. specific crtc framework gets all buffers through framebuffer(actually, it
would be specific framebuffer)and sets them to overlay registers of hardware
appropriately.
like this, how about using framebuffer and gem framework instead of plane? I'd
be glad to give me your opinions.
Thank you,
Inki Dae.
^ permalink raw reply
* Re: [Qemu-trivial] [PATCH] qapi: fix typos in documentation JSON examples
From: Stefan Hajnoczi @ 2011-10-31 11:53 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-trivial, qemu-devel
In-Reply-To: <1319813906-21196-1-git-send-email-stefanha@linux.vnet.ibm.com>
On Fri, Oct 28, 2011 at 03:58:26PM +0100, Stefan Hajnoczi wrote:
> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
> ---
> docs/qapi-code-gen.txt | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
Applied to the trivial patches -next tree:
http://repo.or.cz/w/qemu/stefanha.git/shortlog/refs/heads/trivial-patches-next
Stefan
^ permalink raw reply
* Re: [Qemu-devel] [Qemu-trivial] [PATCH] qapi: fix typos in documentation JSON examples
From: Stefan Hajnoczi @ 2011-10-31 11:53 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-trivial, qemu-devel
In-Reply-To: <1319813906-21196-1-git-send-email-stefanha@linux.vnet.ibm.com>
On Fri, Oct 28, 2011 at 03:58:26PM +0100, Stefan Hajnoczi wrote:
> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
> ---
> docs/qapi-code-gen.txt | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
Applied to the trivial patches -next tree:
http://repo.or.cz/w/qemu/stefanha.git/shortlog/refs/heads/trivial-patches-next
Stefan
^ permalink raw reply
* Re: [Qemu-trivial] [Qemu-devel] [PATCH 1/2] sysbus: Supply missing va_end()
From: Stefan Hajnoczi @ 2011-10-31 11:52 UTC (permalink / raw)
To: Markus Armbruster; +Cc: qemu-trivial, jvrao, qemu-devel
In-Reply-To: <1319791946-15602-2-git-send-email-armbru@redhat.com>
On Fri, Oct 28, 2011 at 10:52:25AM +0200, Markus Armbruster wrote:
> C99 7.15.1: Each invocation of the va_start and va_copy macros shall
> be matched by a corresponding invocation of the va_end macro in the
> same function.
>
> Spotted by Coverity. Harmless on the (common) systems where va_end()
> does nothing.
>
> Signed-off-by: Markus Armbruster <armbru@redhat.com>
> ---
> hw/sysbus.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
Thanks, applied to the trivial patches -next tree:
http://repo.or.cz/w/qemu/stefanha.git/shortlog/refs/heads/trivial-patches-next
Stefan
^ permalink raw reply
* Re: [Qemu-devel] [PATCH 1/2] sysbus: Supply missing va_end()
From: Stefan Hajnoczi @ 2011-10-31 11:52 UTC (permalink / raw)
To: Markus Armbruster; +Cc: qemu-trivial, jvrao, qemu-devel
In-Reply-To: <1319791946-15602-2-git-send-email-armbru@redhat.com>
On Fri, Oct 28, 2011 at 10:52:25AM +0200, Markus Armbruster wrote:
> C99 7.15.1: Each invocation of the va_start and va_copy macros shall
> be matched by a corresponding invocation of the va_end macro in the
> same function.
>
> Spotted by Coverity. Harmless on the (common) systems where va_end()
> does nothing.
>
> Signed-off-by: Markus Armbruster <armbru@redhat.com>
> ---
> hw/sysbus.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
Thanks, applied to the trivial patches -next tree:
http://repo.or.cz/w/qemu/stefanha.git/shortlog/refs/heads/trivial-patches-next
Stefan
^ permalink raw reply
* Re: [Qemu-trivial] [PATCH 2/2] hw/9pfs: Supply missing va_end()
From: Stefan Hajnoczi @ 2011-10-31 11:51 UTC (permalink / raw)
To: Markus Armbruster; +Cc: qemu-trivial, jvrao, qemu-devel
In-Reply-To: <1319791946-15602-3-git-send-email-armbru@redhat.com>
On Fri, Oct 28, 2011 at 9:52 AM, Markus Armbruster <armbru@redhat.com> wrote:
> C99 7.15.1: Each invocation of the va_start and va_copy macros shall
> be matched by a corresponding invocation of the va_end macro in the
> same function.
>
> Spotted by Coverity. Harmless on the (common) systems where va_end()
> does nothing.
>
> Signed-off-by: Markus Armbruster <armbru@redhat.com>
> ---
> hw/9pfs/virtio-9p.c | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
Thanks for this patch. I looked at the surrounding code and it turns
out this entire function duplicates g_vasprintf() from glib.
I sent a patch to use g_vasprintf() and it therefore eliminates the
varargs issue.
Stefan
^ permalink raw reply
* Re: [Qemu-devel] [Qemu-trivial] [PATCH 2/2] hw/9pfs: Supply missing va_end()
From: Stefan Hajnoczi @ 2011-10-31 11:51 UTC (permalink / raw)
To: Markus Armbruster; +Cc: qemu-trivial, jvrao, qemu-devel
In-Reply-To: <1319791946-15602-3-git-send-email-armbru@redhat.com>
On Fri, Oct 28, 2011 at 9:52 AM, Markus Armbruster <armbru@redhat.com> wrote:
> C99 7.15.1: Each invocation of the va_start and va_copy macros shall
> be matched by a corresponding invocation of the va_end macro in the
> same function.
>
> Spotted by Coverity. Harmless on the (common) systems where va_end()
> does nothing.
>
> Signed-off-by: Markus Armbruster <armbru@redhat.com>
> ---
> hw/9pfs/virtio-9p.c | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
Thanks for this patch. I looked at the surrounding code and it turns
out this entire function duplicates g_vasprintf() from glib.
I sent a patch to use g_vasprintf() and it therefore eliminates the
varargs issue.
Stefan
^ permalink raw reply
* [Bug 41592] [Radeon] The display often freezes with gnome-shell 3.2
From: bugzilla-daemon @ 2011-10-31 11:50 UTC (permalink / raw)
To: dri-devel
In-Reply-To: <bug-41592-502@http.bugs.freedesktop.org/>
https://bugs.freedesktop.org/show_bug.cgi?id=41592
--- Comment #12 from peterle@hottemptation.org 2011-10-31 04:50:56 PDT ---
Thanks! That is bad, or good.
Did you clicked on the thumbnails or just viewed the slideshow? Clicking on the
thumbnails is causing the issue, the slideshow not.
--
Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are the assignee for the bug.
^ permalink raw reply
* [U-Boot] [PATCH] ARM: define CONFIG_MACH_TYPE for all keymile boards
From: Prafulla Wadaskar @ 2011-10-31 11:50 UTC (permalink / raw)
To: u-boot
In-Reply-To: <4EAE7CE6.8080109@compulab.co.il>
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de [mailto:u-boot-
> bounces at lists.denx.de] On Behalf Of Igor Grinberg
> Sent: Monday, October 31, 2011 4:18 PM
> To: Valentin Longchamp
> Cc: u-boot at lists.denx.de; Holger Brunck
> Subject: Re: [U-Boot] [PATCH] ARM: define CONFIG_MACH_TYPE for
> all keymile boards
>
> Hi Valentin,
>
> On 10/31/11 12:07, Valentin Longchamp wrote:
> > As this is a mandatory CONFIG for ARM boards now.
> >
> > Signed-off-by: Valentin Longchamp
> <valentin.longchamp@keymile.com>
> > Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
> > ---
> > include/configs/km/km_arm.h | 2 ++
> > 1 files changed, 2 insertions(+), 0 deletions(-)
> >
> > diff --git a/include/configs/km/km_arm.h
> b/include/configs/km/km_arm.h
> > index eaf6017..f30088d 100644
> > --- a/include/configs/km/km_arm.h
> > +++ b/include/configs/km/km_arm.h
> > @@ -48,6 +48,8 @@
> > #define CONFIG_KW88F6281 /* SOC Name */
> > #define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
> >
> > +#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
> > +
>
> Probably, you also want to remove the gd->bd->bi_arch_number
> assignment from board files using this mach id?
Hi Valentin
Please post one patch for all this
(including above, MACH_TYPE_KM_KIRKDOOD definition and CONFIG_MACH_TYPE definition)
Regards...
Prafulla . . .
^ permalink raw reply
* [Qemu-devel] [PATCH] hw/9pfs: use g_vasprintf() instead of rolling our own
From: Stefan Hajnoczi @ 2011-10-31 11:49 UTC (permalink / raw)
To: qemu-devel; +Cc: Markus Armbruster, Stefan Hajnoczi, Aneesh Kumar K.V
Markus Armbruster <armbru@redhat.com> sent fixes for va_list vararg
issues in v9fs_string_alloc_printf(). It turns out the function
duplicates g_vasprintf() and can therefore be eliminated entirely.
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
---
hw/9pfs/virtio-9p.c | 103 ++-------------------------------------------------
1 files changed, 4 insertions(+), 99 deletions(-)
diff --git a/hw/9pfs/virtio-9p.c b/hw/9pfs/virtio-9p.c
index 8b6813f..253919b 100644
--- a/hw/9pfs/virtio-9p.c
+++ b/hw/9pfs/virtio-9p.c
@@ -11,6 +11,9 @@
*
*/
+#include <glib.h>
+#include <glib/gprintf.h>
+
#include "hw/virtio.h"
#include "hw/pc.h"
#include "qemu_socket.h"
@@ -161,114 +164,16 @@ void v9fs_string_null(V9fsString *str)
v9fs_string_free(str);
}
-static int number_to_string(void *arg, char type)
-{
- unsigned int ret = 0;
-
- switch (type) {
- case 'u': {
- unsigned int num = *(unsigned int *)arg;
-
- do {
- ret++;
- num = num/10;
- } while (num);
- break;
- }
- case 'U': {
- unsigned long num = *(unsigned long *)arg;
- do {
- ret++;
- num = num/10;
- } while (num);
- break;
- }
- default:
- printf("Number_to_string: Unknown number format\n");
- return -1;
- }
-
- return ret;
-}
-
-static int GCC_FMT_ATTR(2, 0)
-v9fs_string_alloc_printf(char **strp, const char *fmt, va_list ap)
-{
- va_list ap2;
- char *iter = (char *)fmt;
- int len = 0;
- int nr_args = 0;
- char *arg_char_ptr;
- unsigned int arg_uint;
- unsigned long arg_ulong;
-
- /* Find the number of %'s that denotes an argument */
- for (iter = strstr(iter, "%"); iter; iter = strstr(iter, "%")) {
- nr_args++;
- iter++;
- }
-
- len = strlen(fmt) - 2*nr_args;
-
- if (!nr_args) {
- goto alloc_print;
- }
-
- va_copy(ap2, ap);
-
- iter = (char *)fmt;
-
- /* Now parse the format string */
- for (iter = strstr(iter, "%"); iter; iter = strstr(iter, "%")) {
- iter++;
- switch (*iter) {
- case 'u':
- arg_uint = va_arg(ap2, unsigned int);
- len += number_to_string((void *)&arg_uint, 'u');
- break;
- case 'l':
- if (*++iter == 'u') {
- arg_ulong = va_arg(ap2, unsigned long);
- len += number_to_string((void *)&arg_ulong, 'U');
- } else {
- return -1;
- }
- break;
- case 's':
- arg_char_ptr = va_arg(ap2, char *);
- len += strlen(arg_char_ptr);
- break;
- case 'c':
- len += 1;
- break;
- default:
- fprintf(stderr,
- "v9fs_string_alloc_printf:Incorrect format %c", *iter);
- return -1;
- }
- iter++;
- }
-
-alloc_print:
- *strp = g_malloc((len + 1) * sizeof(**strp));
-
- return vsprintf(*strp, fmt, ap);
-}
-
void GCC_FMT_ATTR(2, 3)
v9fs_string_sprintf(V9fsString *str, const char *fmt, ...)
{
va_list ap;
- int err;
v9fs_string_free(str);
va_start(ap, fmt);
- err = v9fs_string_alloc_printf(&str->data, fmt, ap);
- BUG_ON(err == -1);
+ str->size = g_vasprintf(&str->data, fmt, ap);
va_end(ap);
-
- str->size = err;
}
void v9fs_string_copy(V9fsString *lhs, V9fsString *rhs)
--
1.7.7
^ permalink raw reply related
* Re: [Qemu-devel] GSoC mentor summit session "how to bind students long-term"
From: Stefan Hajnoczi @ 2011-10-31 8:55 UTC (permalink / raw)
To: Alexander Graf; +Cc: qemu-devel@nongnu.org Developers
In-Reply-To: <10B0F816-CA40-4642-8334-7C3E7F86D1EA@suse.de>
On Sat, Oct 29, 2011 at 04:00:34PM +0200, Alexander Graf wrote:
> During the GSoC mentor summit there was a pretty interesting session on how to get students to stick with your project even after GSoC has ended. So far we haven't really been exactly successful in that respect :). I'll just post my notes below:
>
> - send successful students to conferences
> - set expectations on what we expect from students after gsoc, lay out the achievement plan for students to times beyond gsoc
> - give students responsibility, make them maintain parts (makes it harder for them to just leave, because they feel obliged)
> - shove students to community, no sidechannel communication, make them do A&Os on the public list
My personal experience being a GSoC student was that responsibility and
fellowship matters most - it's what makes contributing addictive. It's
one thing to do an interesting project for 12 weeks but another to stick
around because the group of developers have become your friends and you
feel responsibility and satisfaction from supporting users on
IRC/mailing lists.
The easiest way to give students responsibility is to get them actively
involved in supporting users on IRC/mailing lists and fixing bugs.
Doing this in addition to the official GSoC project is more likely to
keep them hooked. It helps turn them into a QEMU expert and someone who
can help others - and hopefully they'll want to continue using this
skill once the summer is over.
Stefan
^ permalink raw reply
* Re: [PATCH RFC v2 13/13] libxl: New event generation API
From: Ian Campbell @ 2011-10-31 11:49 UTC (permalink / raw)
To: Ian Jackson, Jim Fehlig, Dave Scott, Jon Ludlam
Cc: xen-devel@lists.xensource.com
In-Reply-To: <1319827031-15395-14-git-send-email-ian.jackson@eu.citrix.com>
I've not looked at this yet but CCing a few potential users of this
interface. I've trimmed it to just the public header changes for their
benefit, I'm sure they can find the full thing in the archive if they
are interested in the gorey details.
On Fri, 2011-10-28 at 19:37 +0100, Ian Jackson wrote:
> Replace the existing API for retrieving high-level events (events
> about domains, etc.) from libxl with a new one.
>
> This changes the definition and semantics of the `libxl_event'
> structure, and replaces the calls for obtaining information about
> domain death and disk eject events.
>
> This is an incompatible change, sorry. The alternative was to try to
> provide both the previous horrid API and the new one, and would also
> involve never using the name `libxl_event' for the new interface.
>
> Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
> ---
> tools/libxl/libxl.c | 306 +++++++++++++++++++++++++++++------------
> tools/libxl/libxl.h | 55 ++-------
> tools/libxl/libxl_event.c | 182 +++++++++++++++++++++++---
> tools/libxl/libxl_event.h | 172 +++++++++++++++++++++++
> tools/libxl/libxl_internal.c | 6 +
> tools/libxl/libxl_internal.h | 66 +++++++++
> tools/libxl/libxl_types.idl | 35 ++++-
> tools/libxl/xl_cmdimpl.c | 261 +++++++++++++++++++++---------------
> 8 files changed, 815 insertions(+), 268 deletions(-)
>
> diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
> index da06ed2..4759c18 100644
> --- a/tools/libxl/libxl.h
> +++ b/tools/libxl/libxl.h
> @@ -53,7 +53,10 @@
> * A public function may be called from within libxl; the call
> * context initialisation macros will make sure that the internal
> * caller's context is reused (eg, so that the same xenstore
> - * transaction is used).
> + * transaction is used). But in-libxl callers of libxl public
> + * functions should note that any libxl public function may cause
> + * recursively reentry into libxl via the application's event
> + * callback hook.
> *
> * Public functions have names like libxl_foobar.
> *
> @@ -152,6 +155,8 @@ void libxl_key_value_list_destroy(libxl_key_value_list *kvl);
>
> typedef uint32_t libxl_hwcap[8];
>
> +typedef uint64_t libxl_ev_user;
> +
> typedef struct {
> uint32_t size; /* number of bytes in map */
> uint8_t *map;
> @@ -200,6 +205,9 @@ typedef struct {
> int v;
> } libxl_enum_string_table;
>
> +struct libxl_event;
> +typedef LIBXL_TAILQ_ENTRY(struct libxl_event) libxl_ev_link;
> +
> typedef struct libxl__ctx libxl_ctx;
>
> #include "_libxl_types.h"
> @@ -295,51 +303,6 @@ int libxl_run_bootloader(libxl_ctx *ctx,
>
> /* 0 means ERROR_ENOMEM, which we have logged */
>
> -/* events handling */
> -
> -typedef struct {
> - /* event type */
> - libxl_event_type type;
> - /* data for internal use of the library */
> - char *path;
> - char *token;
> -} libxl_event;
> -
> -typedef struct {
> - char *path;
> - char *token;
> -} libxl_waiter;
> -
> -
> -int libxl_get_wait_fd(libxl_ctx *ctx, int *fd);
> -/* waiter is allocated by the caller */
> -int libxl_wait_for_domain_death(libxl_ctx *ctx, uint32_t domid, libxl_waiter *waiter);
> -/* waiter is a preallocated array of num_disks libxl_waiter elements */
> -int libxl_wait_for_disk_ejects(libxl_ctx *ctx, uint32_t domid, libxl_device_disk *disks, int num_disks, libxl_waiter *waiter);
> -int libxl_get_event(libxl_ctx *ctx, libxl_event *event);
> -int libxl_stop_waiting(libxl_ctx *ctx, libxl_waiter *waiter);
> -int libxl_free_event(libxl_event *event);
> -int libxl_free_waiter(libxl_waiter *waiter);
> -
> -/*
> - * Returns:
> - * - 0 if the domain is dead but there is no cleanup to be done. e.g
> - * because someone else has already done it.
> - * - 1 if the domain is dead and there is cleanup to be done.
> - *
> - * Can return error if the domain exists and is still running.
> - *
> - * *info will contain valid domain state iff 1 is returned. In
> - * particular if 1 is returned then info->shutdown_reason is
> - * guaranteed to be valid since by definition the domain is
> - * (shutdown||dying))
> - */
> -int libxl_event_get_domain_death_info(libxl_ctx *ctx, uint32_t domid, libxl_event *event, libxl_dominfo *info);
> -
> -/*
> - * Returns true and fills *disk if the caller should eject the disk
> - */
> -int libxl_event_get_disk_eject_info(libxl_ctx *ctx, uint32_t domid, libxl_event *event, libxl_device_disk *disk);
>
> int libxl_domain_rename(libxl_ctx *ctx, uint32_t domid,
> const char *old_name, const char *new_name);
[...]
> diff --git a/tools/libxl/libxl_event.h b/tools/libxl/libxl_event.h
> index 48c6277..c52addc 100644
> --- a/tools/libxl/libxl_event.h
> +++ b/tools/libxl/libxl_event.h
> @@ -18,6 +18,178 @@
>
> #include <libxl.h>
>
> +/*======================================================================*/
> +
> +/*
> + * Domain event handling - getting Xen events from libxl
> + */
> +
> +#define LIBXL_EVENTMASK_ALL (~(unsigned long)0)
> +
> +typedef int libxl_event_predicate(const libxl_event*, void *user);
> + /* Return value is 0 if the event is unwanted or non-0 if it is.
> + * Predicates are not allowed to fail.
> + */
> +
> +int libxl_event_check(libxl_ctx *ctx, libxl_event **event_r,
> + unsigned long typemask,
> + libxl_event_predicate *predicate, void *predicate_user);
> + /* Searches for an event, already-happened, which matches typemask
> + * and predicate. predicate==0 matches any event.
> + * libxl_event_check returns the event, which must then later be
> + * freed by the caller using libxl_event_free.
> + *
> + * Returns ERROR_NOT_READY if no such event has happened.
> + */
> +
> +int libxl_event_wait(libxl_ctx *ctx, libxl_event **event_r,
> + unsigned long typemask,
> + libxl_event_predicate *predicate, void *predicate_user);
> + /* Like libxl_event_check but blocks if no suitable events are
> + * available, until some are. Uses libxl_osevent_beforepoll/
> + * _afterpoll so may be inefficient if very many domains are being
> + * handled by a single program.
> + */
> +
> +int libxl_event_free(libxl_ctx *ctx, libxl_event *event);
> +
> +
> +/* Alternatively or additionally, the application may also use this: */
> +
> +typedef struct libxl_event_hooks {
> + uint64_t event_occurs_mask;
> + void (*event_occurs)(void *user, const libxl_event *event);
> + void (*disaster)(void *user, libxl_event_type type,
> + const char *msg, int errnoval);
> +} libxl_event_hooks;
> +
> +void libxl_event_register_callbacks(libxl_ctx *ctx,
> + const libxl_event_hooks *hooks, void *user);
> + /*
> + * Arranges that libxl will henceforth call event_occurs for any
> + * events whose type is set in event_occurs_mask, rather than
> + * queueing the event for retrieval by libxl_event_check/wait.
> + * Events whose bit is clear in mask are not affected.
> + *
> + * event becomes owned by the application and must be freed, either
> + * by event_occurs or later.
> + *
> + * event_occurs may be NULL if mask is 0.
> + *
> + * libxl_event_register_callback also provides a way for libxl to
> + * report to the application that there was a problem reporting
> + * events; this can occur due to lack of host memory during event
> + * handling, or other wholly unrecoverable errors from system calls
> + * made by libxl. This will not happen for frivolous reasons - only
> + * if the system, or the Xen components of it, are badly broken.
> + *
> + * msg and errnoval will describe the action that libxl was trying
> + * to do, and type specifies the type of libxl events which may be
> + * missing. type may be 0 in which case events of all types may be
> + * missing.
> + *
> + * disaster may be NULL. If it is, or if _register_callbacks has
> + * not been called, errors of this kind are fatal to the entire
> + * application: libxl will print messages to its logs and to stderr
> + * and call exit(-1).
> + *
> + * If disaster returns, it may be the case that some or all future
> + * libxl calls will return errors; likewise it may be the case that
> + * no more events (of the specified type, if applicable) can be
> + * produced. An application which supplies a disaster function
> + * should normally react either by exiting, or by (when it has
> + * returned to its main event loop) shutting down libxl with
> + * libxl_ctx_free and perhaps trying to restart it with
> + * libxl_ctx_init.
> + *
> + * In any case before calling disaster, libxl will have logged a
> + * message with level XTL_CRITICAL.
> + *
> + * Reentrancy: it IS permitted to call libxl from within
> + * event_occurs. It is NOT permitted to call libxl from within
> + * disaster.
> + *
> + * libxl_event_register_callbacks may be called as many times, with
> + * different parameters, as the application likes; the most recent
> + * call determines the libxl behaviour. However it is NOT safe to
> + * call _register_callbacks concurrently with, or reentrantly from,
> + * any other libxl function.
> + *
> + * Calls to _register_callbacks do not affect events which have
> + * already occurred.
> + */
> +
> +
> +/*
> + * Events are only generated if they have been requested.
> + * The following functions request the generation of specific events.
> + *
> + * Each set of functions for controlling event generation has this form:
> + *
> + * typedef struct libxl__evgen_FOO libxl__evgen_FOO;
> + * int libxl_evenable_FOO(libxl_ctx *ctx, FURTHER PARAMETERS,
> + * libxl_ev_user user, libxl__evgen_FOO **evgen_out);
> + * void libxl_evdisable_FOO(libxl_ctx *ctx, libxl__evgen_FOO *evgen);
> + *
> + * The evenable function arranges that the events (as described in the
> + * doc comment for the individual function) will start to be generated
> + * by libxl. On success, *evgen_out is set to a non-null pointer to
> + * an opaque struct.
> + *
> + * The user value is returned in the generated events and may be
> + * used by the caller for whatever it likes. The type ev_user is
> + * guaranteed to be an unsigned integer type which is at least
> + * as big as uint64_t and is also guaranteed to be big enough to
> + * contain any intptr_t value.
> + *
> + * If it becomes desirable to stop generation of the relevant events,
> + * or to reclaim the resources in libxl associated with the evgen
> + * structure, the same evgen value should be passed to the evdisable
> + * function. However, note that events which occurred prior to the
> + * evdisable call may still be returned.
> + *
> + * The caller may enable identical events more than once. If they do
> + * so, each actual occurrence will generate several events to be
> + * returned by libxl_event_check, with the appropriate user value(s).
> + * Aside from this, each occurrence of each event is returned by
> + * libxl_event_check exactly once.
> + *
> + * An evgen is associated with the libxl_ctx used for its creation.
> + * After libxl_ctx_free, all corresponding evgen handles become
> + * invalid and must no longer be passed to evdisable.
> + *
> + * Events enabled with evenable prior to a fork and libxl_ctx_postfork
> + * are no longer generated after the fork/postfork; however the evgen
> + * structures are still valid and must be passed to evdisable if the
> + * memory they use should not be leaked.
> + *
> + * Applications should ensure that they eventually retrieve every
> + * event using libxl_event_check or libxl_event_wait, since events
> + * which occur but are not retreived by the application will be queued
> + * inside libxl indefinitely. libxl_event_check/_wait may be O(n)
> + * where n is the number of queued events which do not match the
> + * criteria specified in the arguments to check/wait.
> + */
> +
> +typedef struct libxl__evgen_domain_death libxl_evgen_domain_death;
> +int libxl_evenable_domain_death(libxl_ctx *ctx, uint32_t domid,
> + libxl_ev_user, libxl_evgen_domain_death **evgen_out);
> +void libxl_evdisable_domain_death(libxl_ctx *ctx, libxl_evgen_domain_death*);
> + /* Arranges for the generation of DOMAIN_SHUTDOWN and DOMAIN_DESTROY
> + * events. A domain which is destroyed before it shuts down
> + * may generate only a DESTROY event.
> + */
> +
> +typedef struct libxl__evgen_disk_eject libxl_evgen_disk_eject;
> +int libxl_evenable_disk_eject(libxl_ctx *ctx, uint32_t domid, const char *vdev,
> + libxl_ev_user, libxl_evgen_disk_eject **evgen_out);
> +void libxl_evdisable_disk_eject(libxl_ctx *ctx, libxl_evgen_disk_eject*);
> + /* Arranges for the generation of DISK_EJECT events. A copy of the
> + * string *vdev will be made for libxl's internal use, and a pointer
> + * to this (or some other) copy will be returned as the vdev
> + * member of event.u.
> + */
> +
>
> /*======================================================================*/
>
> diff --git a/tools/libxl/libxl_internal.c b/tools/libxl/libxl_internal.c
> index 62e7fba..202ba89 100644
> --- a/tools/libxl/libxl_internal.c
> +++ b/tools/libxl/libxl_internal.c
> @@ -74,6 +74,12 @@ void libxl__free_all(libxl__gc *gc)
> free(gc->alloc_ptrs);
> gc->alloc_ptrs = 0;
> gc->alloc_maxsize = 0;
> +
> + libxl_event *ev, *ev_tmp;
> + LIBXL_TAILQ_FOREACH_SAFE(ev, &gc->occurred_for_callback, link, ev_tmp) {
> + LIBXL_TAILQ_REMOVE(&gc->occurred_for_callback, ev, link);
> + CTX->event_hooks->event_occurs(CTX->event_hooks_user, ev);
> + }
> }
>
> void *libxl__zalloc(libxl__gc *gc, int bytes)
[...]
> diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
> index 93fb8cd..53c07ee 100644
> --- a/tools/libxl/libxl_types.idl
> +++ b/tools/libxl/libxl_types.idl
> @@ -75,11 +75,6 @@ libxl_action_on_shutdown = Enumeration("action_on_shutdown", [
> (6, "COREDUMP_RESTART"),
> ])
>
> -libxl_event_type = Enumeration("event_type", [
> - (1, "DOMAIN_DEATH"),
> - (2, "DISK_EJECT"),
> - ])
> -
> libxl_button = Enumeration("button", [
> (1, "POWER"),
> (2, "SLEEP"),
> @@ -374,3 +369,33 @@ libxl_sched_credit = Struct("sched_credit", [
> ("weight", integer),
> ("cap", integer),
> ], destructor_fn=None)
> +
> +libxl_event_type = Enumeration("event_type", [
> + (1, "DOMAIN_SHUTDOWN"),
> + (2, "DOMAIN_DESTROY"),
> + (3, "DISK_EJECT"),
> + ])
> +
> +libxl_ev_user = Number("libxl_ev_user")
> +
> +libxl_ev_link = Builtin("ev_link", passby=PASS_BY_REFERENCE, c_only=True)
> +
> +libxl_event = Struct("event",[
> + ("link", libxl_ev_link,0,
> + "for use by libxl; caller may use this once the event has been"
> + " returned by libxl_event_{check,wait}"),
> + ("domid", libxl_domid),
> + ("domuuid", libxl_uuid),
> + ("for_user", libxl_ev_user),
> + ("type", libxl_event_type),
> + ("u", KeyedUnion(None, libxl_event_type, "type",
> + [("domain_shutdown", Struct(None, [
> + ("shutdown_reason", uint8),
> + ])),
> + ("domain_destroy", Struct(None, [])),
> + ("disk_eject", Struct(None, [
> + ("vdev", string),
> + ("disk", libxl_device_disk),
> + ])),
> + ]))])
> +
^ permalink raw reply
* [PATCH] t7511: avoid use of reserved filename on Windows.
From: Pat Thoyts @ 2011-10-31 11:44 UTC (permalink / raw)
To: "Git; +Cc: "msysGit
PRN is a special filename on Windows to send data to the printer. As
this is generated during test 2 - use an alternate prefix.
Signed-off-by: Pat Thoyts <patthoyts@users.sourceforge.net>
---
t/t7511-status-index.sh | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/t/t7511-status-index.sh b/t/t7511-status-index.sh
index bca359d..b5fdc04 100755
--- a/t/t7511-status-index.sh
+++ b/t/t7511-status-index.sh
@@ -24,7 +24,7 @@ check() {
check 1
check 2 p
-check 3 pr
+check 3 px
check 4 pre
check 5 pref
check 6 prefi
--
1.7.8.rc0.200.gbcc18
^ permalink raw reply related
* Re: [Qemu-devel] [Qemu test report] Autotest | Job ID: 1997 "Upstream qemu.git sanity 10-30-2011 00:05:01" | Status: 1 Completed | Success Rate: 53.85 %
From: Luiz Capitulino @ 2011-10-31 11:47 UTC (permalink / raw)
To: Lucas Meneghel Rodrigues; +Cc: Kevin Wolf, QEMU devel
In-Reply-To: <4EAE0163.20303@redhat.com>
On Mon, 31 Oct 2011 00:01:07 -0200
Lucas Meneghel Rodrigues <lmr@redhat.com> wrote:
> Hi folks, sending this to QEMU devel to inform the current problems we
> are able to reproduce on the current master branch.
>
> So, qemu.git is presenting problems as of latest master. None of the
> problems mentioned is happening on qemu-kvm.git.
>
> -------- Original Message --------
> Subject: Autotest | Job ID: 1997 "Upstream qemu.git sanity 10-30-2011
> 00:05:01" | Status: 1 Completed | Success Rate: 53.85 %
> Date: Sun, 30 Oct 2011 09:50:58 -0400
> From: kvm-autotest@redhat.com
> To: lmr@redhat.com, crosa@redhat.com
>
> Job ID: 1997
> Job name: Upstream qemu.git sanity 10-30-2011 00:05:01
> Summary: Host: virtlab208.virt.bos.redhat.com Status: Completed
> Status: 1 Completed
> Execution time (HH:MM:SS): 05:44:38
> User tests executed: 26
> User tests passed: 14
> User tests failed: 12
> User tests success rate: 53.85 %
> Failures:
> Test Name
> Status Reason
>
>
> kvm.qemu-git.virtio_blk.smp2.virtio_net.Win7.64.sp1.unattended_install.cdrom
> FAIL Timeout elapsed while waiting for install to finish [context:
> waiting for installation to finish]
>
>
> ^ Here, the windows install timeout happened due to the floppy
> regression introduced by 212ec7baa28cc9d819234fed1541fc1423cfe3d8. We
> did try Kevin's patches and they did not fix the issue.
>
> kvm.qemu-git.virtio_blk.smp2.virtio_net.RHEL.6.1.x86_64.migrate.tcp
> FAIL Unhandled LoginError: Client said 'connection refused'
> (output: 'ssh: connect to host 192.168.122.129 port 22: Connection
> refused\n') [context: logging into 'vm1']
> kvm.qemu-git.virtio_blk.smp2.virtio_net.RHEL.6.1.x86_64.reboot
> FAIL Unhandled LoginError: Client said 'connection refused'
> (output: 'ssh: connect to host 192.168.122.25 port 22: Connection
> refused\n') [context: logging into 'vm1']
> kvm.qemu-git.virtio_blk.smp2.virtio_net.RHEL.6.1.x86_64.migrate.unix
> FAIL Unhandled LoginError: Client said 'connection refused'
> (output: 'ssh: connect to host 192.168.122.3 port 22: Connection
> refused\n') [context: logging into 'vm1']
> kvm.qemu-git.virtio_blk.smp2.virtio_net.RHEL.6.1.x86_64.migrate.exec
> FAIL Unhandled MonitorSocketError: Could not send monitor
> command 'info migrate' ([Errno 32] Broken pipe) [context:
> migrating 'vm1']
>
> ^ All of those failures happened due to qemu segfaults during the
> migration process. I believe Luiz had a patch to possibly fix this
> migration issue, so copying him.
Yes, it's already on the list:
http://lists.gnu.org/archive/html/qemu-devel/2011-10/msg03597.html
>
> The segfaults generated core dumps, which we would be happy to scp to a
> public box, if someone is interested in them.
>
> Cheers,
>
> Lucas
>
^ permalink raw reply
* Re: [PATCH v3 4/14] staging/media/as102: checkpatch fixes
From: Mauro Carvalho Chehab @ 2011-10-31 11:47 UTC (permalink / raw)
To: Stefan Richter
Cc: Piotr Chmura, Sylwester Nawrocki, Devin Heitmueller, Greg KH,
Patrick Dickey, LMML, devel
In-Reply-To: <4EAE7CE4.10809@s5r6.in-berlin.de>
Em 31-10-2011 08:48, Stefan Richter escreveu:
>> On Oct 30 Piotr Chmura wrote:
>>> Patch taken from http://kernellabs.com/hg/~dheitmueller/v4l-dvb-as102-2/
>>>
>>> Original source and comment:
>>> # HG changeset patch
>
> By the way, the brand new git 1.7.8.rc0 features some HG support in "git am":
> https://code.google.com/p/git-core/source/detail?spec=svnbe3fa9125e708348c7baf04ebe9507a72a9d1800&r=0cfd112032017ab68ed576f6bb5258452084ebf1
>
> This converts the "# User" and "# Date" lines of HG patches into RFC 2822
> "From: " and "Date: " lines which are then used as authorship metadata.
hg headers are fine. As we moved from hg a few years, the scripts I use here already
handles hg headers, converting them to rfc-2822 (it also does other neat things like
calling checkpatch.pl ;) ).
Cheers,
Mauro
^ permalink raw reply
* Re: [GIT PULL] Queue free fix (was Re: [PATCH] block: Free queue resources at blk_release_queue())
From: Jun'ichi Nomura @ 2011-10-31 11:46 UTC (permalink / raw)
To: Heiko Carstens, James Bottomley
Cc: Steffen Maier, linux-scsi@vger.kernel.org, Jens Axboe,
Hannes Reinecke, Linux Kernel, Alan Stern,
Thadeu Lima de Souza Cascardo, Taraka R. Bodireddy,
Seshagiri N. Ippili, Manvanthara B. Puttashankar, Jeff Moyer,
Shaohua Li, Mike Snitzer, gmuelas
In-Reply-To: <1320057746.2964.1.camel@dabdike>
On 10/31/11 19:42, James Bottomley wrote:
> On Mon, 2011-10-31 at 11:05 +0100, Heiko Carstens wrote:
>> On Tue, Oct 18, 2011 at 11:29:40AM -0500, James Bottomley wrote:
>>> On Tue, 2011-10-18 at 17:45 +0200, Heiko Carstens wrote:
>>>> On Tue, Oct 18, 2011 at 10:31:20PM +0900, Jun'ichi Nomura wrote:
>>>>> On 10/17/11 23:06, James Bottomley wrote:
>>>>>> On Mon, 2011-10-17 at 17:46 +0900, Jun'ichi Nomura wrote:
>>>>>>> On 10/15/11 01:03, James Bottomley wrote:
>>>>>>>> On Thu, 2011-10-13 at 15:09 +0200, Steffen Maier wrote:
>>>>>>>>> Initially, we encountered use-after-free bugs in
>>>>>>>>> scsi_print_command / scsi_dispatch_cmd
>>>>>>>>> http://marc.info/?l=linux-scsi&m=130824013229933&w=2
>>>>>>>
>>>>>>> It is interesting that both this and the older report
>>>>>>> got oopsed in scsi_log_send(), while there are other
>>>>>>> dereferences of 'cmd' around scsi_dispatch_cmd().
>>>>>>> Are there any reason they are special? Just by accident?
>>>>>>
>>>>>> Right, that's why it looks like the command area got freed rather than
>>>>>> the command pointer was bogus (6b is a poison free pattern). Perhaps if
>>>>>> the reporter could pin down the failing source line, we'd know better
>>>>>> what was going on?
>>>>>
>>>>> Yeah, that might be useful.
>>>>
>>>> The struct scsi_cmnd that was passed to scsi_log_send() was already freed
>>>> (contents completely 6b6b6b...).
>>>> Since SLUB debugging was turned on we can see that it was freed from
>>>> __scsi_put_command(). Not too much of a surprise.
>>>
>>> But it does tell us the put must be racing with dispatch, since
>>> dereferencing the command to find the device worked higher up in
>>> scsi_dispatch_cmd().
>>>
>>> There is one way to invalidate the theory that we cloned something with
>>> an attached command, and that's to put
>>>
>>> BUG_ON(rq->special)
>>>
>>> in blk_insert_cloned_request(). I think we're careful about clearing
>>> it, so it should work (perhaps a warn on just in case).
>>
>> It _looks_ like we do not hit the BUG_ON() that. This time we get this instead:
>>
>> [ 4024.937870] Unable to handle kernel pointer dereference at virtual kernel address 000003e004d41000
>> [ 4024.937886] Oops: 0011 [#1] PREEMPT SMP DEBUG_PAGEALLOC
>> [ 4024.937899] Modules linked in: dm_round_robin sunrpc ipv6 qeth_l2 binfmt_misc dm_multipath scsi_dh dm_mod qeth ccwgroup [las
>> t unloaded: scsi_wait_scan]
>> [ 4024.937925] CPU: 1 Not tainted 3.0.7-50.x.20111021-s390xdefault #1
>> [ 4024.937930] Process ksoftirqd/1 (pid: 1942, task: 0000000079c6c750, ksp: 0000000073adfc50)
>> [ 4024.937936] Krnl PSW : 0704000180000000 000003e00126263a (dm_softirq_done+0x72/0x140 [dm_mod])
>> [ 4024.937959] R:0 T:1 IO:1 EX:1 Key:0 M:1 W:0 P:0 AS:0 CC:0 PM:0 EA:3
>> [ 4024.937966] Krnl GPRS: 000000007b9156b0 000003e004d41100 000000000e14b600 000000000000006d
>> [ 4024.937971] 00000000715332b0 000000000c140ce8 000000000090d2ef 0000000000000005
>> [ 4024.937977] 0000000000000001 0000000000000101 000000000c140d00 0000000000000000
>> [ 4024.937983] 000003e001260000 000003e00126f098 0000000073adfd08 0000000073adfcb8
>> [ 4024.938001] Krnl Code: 000003e00126262a: f0a0000407f1 srp 4(11,%r0),2033,0
>> [ 4024.938009] 000003e001262630: e31050080004 lg %r1,8(%r5)
>> [ 4024.938017] 000003e001262636: 58b05180 l %r11,384(%r5)
>> [ 4024.938024] >000003e00126263a: e31010080004 lg %r1,8(%r1)
>> [ 4024.938031] 000003e001262640: e31010500004 lg %r1,80(%r1)
>> [ 4024.938038] 000003e001262646: b9020011 ltgr %r1,%r1
>> [ 4024.938045] 000003e00126264a: a784ffdf brc 8,3e001262608
>> [ 4024.938053] 000003e00126264e: e32050080004 lg %r2,8(%r5)
>> [ 4024.938060] Call Trace:
>> [ 4024.938063] ([<070000000040716c>] 0x70000000040716c)
>> [ 4024.938069] [<000000000040d29c>] blk_done_softirq+0xd4/0xf0
>> [ 4024.938080] [<00000000001587c2>] __do_softirq+0xda/0x398
>> [ 4024.938088] [<0000000000158ba0>] run_ksoftirqd+0x120/0x23c
>> [ 4024.938095] [<000000000017c2aa>] kthread+0xa6/0xb0
>> [ 4024.938102] [<000000000061970e>] kernel_thread_starter+0x6/0xc
>> [ 4024.938112] [<0000000000619708>] kernel_thread_starter+0x0/0xc
>> [ 4024.938118] INFO: lockdep is turned off.
>> [ 4024.938121] Last Breaking-Event-Address:
>> [ 4024.938124] [<000003e001262600>] dm_softirq_done+0x38/0x140 [dm_mod]
>> [ 4024.938135]
>> [ 4024.938139] Kernel panic - not syncing: Fatal exception in interrupt
>> [ 4024.938144] CPU: 1 Tainted: G D 3.0.7-50.x.20111021-s390xdefault #1
>> [ 4024.938150] Process ksoftirqd/1 (pid: 1942, task: 0000000079c6c750, ksp: 0000000073adfc50)
>> [ 4024.938155] 0000000073adf958 0000000073adf8d8 0000000000000002 0000000000000000
>> [ 4024.938164] 0000000073adf978 0000000073adf8f0 0000000073adf8f0 000000000061386a
>> [ 4024.938174] 0000000000000000 0000000000000000 0000000000000005 0000000000100ec6
>> [ 4024.938184] 000000000000000d 000000000000000c 0000000073adf940 0000000000000000
>> [ 4024.938194] 0000000000000000 0000000000100a18 0000000073adf8d8 0000000073adf918
>> [ 4024.938205] Call Trace:
>> [ 4024.938208] ([<0000000000100926>] show_trace+0xee/0x144)
>> [ 4024.938216] [<0000000000613694>] panic+0xb0/0x234
>> [ 4024.938224] [<0000000000100ec6>] die+0x15a/0x168
>> [ 4024.938230] [<000000000011fb9e>] do_no_context+0xba/0xf8
>> [ 4024.938306] [<000000000061c074>] do_dat_exception+0x378/0x3e4
>> [ 4024.938314] [<0000000000619e02>] pgm_exit+0x0/0x4
>> [ 4024.938319] [<000003e00126263a>] dm_softirq_done+0x72/0x140 [dm_mod]
>> [ 4024.938329] ([<070000000040716c>] 0x70000000040716c)
>> [ 4024.938334] [<000000000040d29c>] blk_done_softirq+0xd4/0xf0
>> [ 4024.938341] [<00000000001587c2>] __do_softirq+0xda/0x398
>> [ 4024.938347] [<0000000000158ba0>] run_ksoftirqd+0x120/0x23c
>> [ 4024.938354] [<000000000017c2aa>] kthread+0xa6/0xb0
>> [ 4024.938360] [<000000000061970e>] kernel_thread_starter+0x6/0xc
>> [ 4024.938366] [<0000000000619708>] kernel_thread_starter+0x0/0xc
>> [ 4024.938373] INFO: lockdep is turned off.
>>
>> So we thought we might as well upgrade to 3.1 but immediately got a
>>
>> kernel BUG at block/blk-flush.c:323!
>>
>> which was handled here https://lkml.org/lkml/2011/10/4/105 and
>> here https://lkml.org/lkml/2011/10/12/408 .
>>
>> But no patches for that one went upstream AFAICS.
>
> Well, all I can say is "hm". You put only a BUG_ON() in the code, which
> wasn't triggered, but now we get a completely different oops. However,
> I think it does point to the dm barrier handling code. Can you turn off
> barriers and see if all oopses go away?
Hm, dm_softirq_done is generic completion code of original
request in dm-multipath.
So oops here might be another manifestation of use-after-free.
Do you always hit the oops at the same address?
Could you find corresponding source code line for
the crashed address, dm_softirq_done+0x72/0x140,
and which pointer was invalid?
--
Jun'ichi Nomura, NEC Corporation
^ permalink raw reply
* Re: libfdt queries
From: Varun Wadekar @ 2011-10-31 11:45 UTC (permalink / raw)
To: David Gibson; +Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
In-Reply-To: <20111025064723.GA5513-MK4v0fQdeXQXU02nzanrWNbf9cGiqdzd@public.gmane.org>
> That seems a bit unlikely, but maybe. Is there any way you can dump
> out the dtb after processing by your bootloader?
>
Found out the root cause. My bootloader was not manipulating the dtb
blob size properly and hence the final dtb was messed up. This resulted
in the kernel not finding proper fields inside the dtb.
Sorry for the false alarm. Issue closed.
-----------------------------------------------------------------------------------
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^ permalink raw reply
* [U-Boot] [PATCH 17/17 V2] M28: Add memory detection into SPL
From: Marek Vasut @ 2011-10-31 11:45 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319237066-14954-18-git-send-email-marek.vasut@gmail.com>
This code allows the DDR DRAM size to be detected at runtime. The RAM size is
stored into two scratch registers, from which it is then fetched in U-Boot.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
---
board/denx/m28evk/Makefile | 7 ++++++-
board/denx/m28evk/m28evk.c | 18 ++++++++++++++++--
board/denx/m28evk/mem_init.c | 27 +++++++++++++++++++++++++++
include/configs/m28evk.h | 2 +-
4 files changed, 50 insertions(+), 4 deletions(-)
V2: Drop clean and distclean targets
diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile
index 47229e6..b32ce12 100644
--- a/board/denx/m28evk/Makefile
+++ b/board/denx/m28evk/Makefile
@@ -30,7 +30,7 @@ COBJS := m28evk.o
endif
ifdef CONFIG_SPL_BUILD
-COBJS := mem_init.o mmc_boot.o power_init.o
+COBJS := mem_init.o mmc_boot.o power_init.o memsize.o
endif
SRCS := $(COBJS:.o=.c)
@@ -41,6 +41,11 @@ $(LIB): $(obj).depend $(OBJS)
all: $(ALL)
+ifdef CONFIG_SPL_BUILD
+$(obj)/memsize.c:
+ ln -sf $(TOPDIR)/common/memsize.c $@
+endif
+
#########################################################################
# defines $(obj).depend target
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
index 118e222..168ceeb 100644
--- a/board/denx/m28evk/m28evk.c
+++ b/board/denx/m28evk/m28evk.c
@@ -63,10 +63,24 @@ int board_init(void)
return 0;
}
+#define HW_DIGCTRL_SCRATCH0 0x8001c280
+#define HW_DIGCTRL_SCRATCH1 0x8001c290
int dram_init(void)
{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ uint32_t sz[2];
+
+ sz[0] = readl(HW_DIGCTRL_SCRATCH0);
+ sz[1] = readl(HW_DIGCTRL_SCRATCH1);
+
+ if (sz[0] != sz[1]) {
+ printf("MX28:\n"
+ "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
+ "HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
+ "verify these two registers contain valid RAM size!\n");
+ hang();
+ }
+
+ gd->ram_size = sz[0];
return 0;
}
diff --git a/board/denx/m28evk/mem_init.c b/board/denx/m28evk/mem_init.c
index 066fe0d..17d1f9b 100644
--- a/board/denx/m28evk/mem_init.c
+++ b/board/denx/m28evk/mem_init.c
@@ -165,6 +165,31 @@ void mx28_mem_setup_vddd(void)
&power_regs->hw_power_vdddctrl);
}
+#define HW_DIGCTRL_SCRATCH0 0x8001c280
+#define HW_DIGCTRL_SCRATCH1 0x8001c290
+void data_abort_memdetect_handler(void) __attribute__((naked));
+void data_abort_memdetect_handler(void)
+{
+ asm volatile("subs pc, r14, #4");
+}
+
+void mx28_mem_get_size(void)
+{
+ uint32_t sz, da;
+ uint32_t *vt = (uint32_t *)0x20;
+
+ /* Replace the DABT handler. */
+ da = vt[4];
+ vt[4] = (uint32_t)&data_abort_memdetect_handler;
+
+ sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ writel(sz, HW_DIGCTRL_SCRATCH0);
+ writel(sz, HW_DIGCTRL_SCRATCH1);
+
+ /* Restore the old DABT handler. */
+ vt[4] = da;
+}
+
void mx28_mem_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
@@ -210,4 +235,6 @@ void mx28_mem_init(void)
early_delay(10000);
mx28_mem_setup_cpu_and_hbus();
+
+ mx28_mem_get_size();
}
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 381b01e..c8b0cf5 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -81,7 +81,7 @@
*/
#define CONFIG_NR_DRAM_BANKS 1 /* 2 banks of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
--
1.7.6.3
^ permalink raw reply related
* [U-Boot] [PATCH 14/17 V5] M28: Add MMC SPL
From: Marek Vasut @ 2011-10-31 11:44 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319237066-14954-15-git-send-email-marek.vasut@gmail.com>
This patch adds SPL code for the M28 board.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
---
board/denx/m28evk/Makefile | 8 +
board/denx/m28evk/m28_init.h | 41 ++
board/denx/m28evk/mem_init.c | 213 +++++++++
board/denx/m28evk/mmc_boot.c | 273 ++++++++++++
board/denx/m28evk/power_init.c | 913 ++++++++++++++++++++++++++++++++++++++
board/denx/m28evk/start.S | 396 +++++++++++++++++
board/denx/m28evk/u-boot-spl.lds | 87 ++++
board/denx/m28evk/u-boot.bd | 14 +
include/configs/m28evk.h | 8 +
9 files changed, 1953 insertions(+), 0 deletions(-)
create mode 100644 board/denx/m28evk/m28_init.h
create mode 100644 board/denx/m28evk/mem_init.c
create mode 100644 board/denx/m28evk/mmc_boot.c
create mode 100644 board/denx/m28evk/power_init.c
create mode 100644 board/denx/m28evk/start.S
create mode 100644 board/denx/m28evk/u-boot-spl.lds
create mode 100644 board/denx/m28evk/u-boot.bd
V2: Make waiting for powerswitch to be pressed configurable
V3: Squash checkpatch warning
V4: Configure DUART on PWM pins for V1.1 module
V5: Drop clean and distclean targets
diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile
index e6aba9a..47229e6 100644
--- a/board/denx/m28evk/Makefile
+++ b/board/denx/m28evk/Makefile
@@ -25,7 +25,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
+ifndef CONFIG_SPL_BUILD
COBJS := m28evk.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mem_init.o mmc_boot.o power_init.o
+endif
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
@@ -33,6 +39,8 @@ OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+all: $(ALL)
+
#########################################################################
# defines $(obj).depend target
diff --git a/board/denx/m28evk/m28_init.h b/board/denx/m28evk/m28_init.h
new file mode 100644
index 0000000..98d3631
--- /dev/null
+++ b/board/denx/m28evk/m28_init.h
@@ -0,0 +1,41 @@
+/*
+ * Freescale i.MX28 SPL functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M28_INIT_H__
+#define __M28_INIT_H__
+
+void early_delay(int delay);
+
+void mx28_power_init(void);
+
+#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
+void mx28_power_wait_pswitch(void);
+#else
+static inline void mx28_power_wait_pswitch(void) { }
+#endif
+
+void mx28_mem_init(void);
+
+#endif /* __M28_INIT_H__ */
diff --git a/board/denx/m28evk/mem_init.c b/board/denx/m28evk/mem_init.c
new file mode 100644
index 0000000..066fe0d
--- /dev/null
+++ b/board/denx/m28evk/mem_init.c
@@ -0,0 +1,213 @@
+/*
+ * Freescale i.MX28 RAM init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+
+#include "m28_init.h"
+
+uint32_t dram_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
+ 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
+ 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+ 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
+ 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
+ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
+ 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
+ 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
+ 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
+ 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
+ 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
+ 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+ 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
+};
+
+void init_m28_200mhz_ddr2(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+
+void mx28_mem_init_clock(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* Gate EMI clock */
+ writel(CLKCTRL_FRAC0_CLKGATEEMI,
+ &clkctrl_regs->hw_clkctrl_frac0_set);
+
+ /* EMI = 205MHz */
+ writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
+ &clkctrl_regs->hw_clkctrl_frac0_set);
+ writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
+ CLKCTRL_FRAC0_EMIFRAC_MASK,
+ &clkctrl_regs->hw_clkctrl_frac0_clr);
+
+ /* Ungate EMI clock */
+ writel(CLKCTRL_FRAC0_CLKGATEEMI,
+ &clkctrl_regs->hw_clkctrl_frac0_clr);
+
+ early_delay(11000);
+
+ writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
+ (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
+ &clkctrl_regs->hw_clkctrl_emi);
+
+ /* Unbypass EMI */
+ writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+ early_delay(10000);
+}
+
+void mx28_mem_setup_cpu_and_hbus(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* CPU = 454MHz and ungate CPU clock */
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
+ CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
+ 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
+
+ /* Set CPU bypass */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_set);
+
+ /* HBUS = 151MHz */
+ writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
+ writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
+ &clkctrl_regs->hw_clkctrl_hbus_clr);
+
+ early_delay(10000);
+
+ /* CPU clock divider = 1 */
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
+ CLKCTRL_CPU_DIV_CPU_MASK, 1);
+
+ /* Disable CPU bypass */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+void mx28_mem_setup_vdda(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
+ (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
+ POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
+ &power_regs->hw_power_vddactrl);
+}
+
+void mx28_mem_setup_vddd(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
+ (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
+ POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
+ &power_regs->hw_power_vdddctrl);
+}
+
+void mx28_mem_init(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mx28_pinctrl_regs *pinctrl_regs =
+ (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
+
+ /* Set DDR2 mode */
+ writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
+ &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+
+ /* Power up PLL0 */
+ writel(CLKCTRL_PLL0CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+
+ early_delay(11000);
+
+ mx28_mem_init_clock();
+
+ mx28_mem_setup_vdda();
+
+ /*
+ * Configure the DRAM registers
+ */
+
+ /* Clear START bit from DRAM_CTL16 */
+ clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
+
+ init_m28_200mhz_ddr2();
+
+ /* Clear SREFRESH bit from DRAM_CTL17 */
+ clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
+
+ /* Set START bit in DRAM_CTL16 */
+ setbits_le32(MXS_DRAM_BASE + 0x40, 1);
+
+ /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
+ while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
+ ;
+
+ mx28_mem_setup_vddd();
+
+ early_delay(10000);
+
+ mx28_mem_setup_cpu_and_hbus();
+}
diff --git a/board/denx/m28evk/mmc_boot.c b/board/denx/m28evk/mmc_boot.c
new file mode 100644
index 0000000..86d3ab5
--- /dev/null
+++ b/board/denx/m28evk/mmc_boot.c
@@ -0,0 +1,273 @@
+/*
+ * Freescale i.MX28 Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+
+#include "m28_init.h"
+
+/*
+ * This delay function is intended to be used only in early stage of boot, where
+ * clock are not set up yet. The timer used here is reset on every boot and
+ * takes a few seconds to roll. The boot doesn't take that long, so to keep the
+ * code simple, it doesn't take rolling into consideration.
+ */
+#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
+void early_delay(int delay)
+{
+ uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
+ st += delay;
+ while (st > readl(HW_DIGCTRL_MICROSECONDS))
+ ;
+}
+
+#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA)
+#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* LED */
+ MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
+
+ /* framebuffer */
+ MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
+
+ /* UART1 */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+ MX28_PAD_AUART0_TX__DUART_RTS,
+ MX28_PAD_AUART0_RX__DUART_CTS,
+
+ /* UART2 */
+ MX28_PAD_AUART1_RX__AUART1_RX,
+ MX28_PAD_AUART1_TX__AUART1_TX,
+ MX28_PAD_AUART1_RTS__AUART1_RTS,
+ MX28_PAD_AUART1_CTS__AUART1_CTS,
+
+ /* CAN */
+ MX28_PAD_GPMI_RDY2__CAN0_TX,
+ MX28_PAD_GPMI_RDY3__CAN0_RX,
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* TSC2007 */
+ MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+ MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0, /* Power .. FIXME */
+ MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */
+
+ /* GPMI NAND */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+ /* FEC Ethernet */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* SPI2 (for flash) */
+ MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_SS0__SSP2_D3 |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void board_init_ll(void)
+{
+ mxs_iomux_setup_multiple_pads(iomux_setup, ARRAY_SIZE(iomux_setup));
+ mx28_power_init();
+ mx28_mem_init();
+ mx28_power_wait_pswitch();
+}
+
+/* Support aparatus */
+inline void board_init_f(unsigned long bootflag)
+{
+ for (;;)
+ ;
+}
+
+inline void board_init_r(gd_t *id, ulong dest_addr)
+{
+ for (;;)
+ ;
+}
+
+inline int printf(const char *fmt, ...)
+{
+ return 0;
+}
+
+inline void __coloured_LED_init(void) {}
+inline void __red_LED_on(void) {}
+void coloured_LED_init(void)
+ __attribute__((weak, alias("__coloured_LED_init")));
+void red_LED_on(void)
+ __attribute__((weak, alias("__red_LED_on")));
+void hang(void) __attribute__ ((noreturn));
+void hang(void)
+{
+ for (;;)
+ ;
+}
diff --git a/board/denx/m28evk/power_init.c b/board/denx/m28evk/power_init.c
new file mode 100644
index 0000000..27322b4
--- /dev/null
+++ b/board/denx/m28evk/power_init.c
@@ -0,0 +1,913 @@
+/*
+ * Freescale i.MX28 Boot PMIC init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+#include "m28_init.h"
+
+void mx28_power_clock2xtal(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* Set XTAL as CPU reference clock */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_set);
+}
+
+void mx28_power_clock2pll(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ writel(CLKCTRL_PLL0CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+ early_delay(100);
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+void mx28_power_clear_auto_restart(void)
+{
+ struct mx28_rtc_regs *rtc_regs =
+ (struct mx28_rtc_regs *)MXS_RTC_BASE;
+
+ writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
+ while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
+ ;
+
+ writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
+ while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
+ ;
+
+ /*
+ * Due to the hardware design bug of mx28 EVK-A
+ * we need to set the AUTO_RESTART bit.
+ */
+ if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
+ return;
+
+ while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+ ;
+
+ setbits_le32(&rtc_regs->hw_rtc_persistent0,
+ RTC_PERSISTENT0_AUTO_RESTART);
+ writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
+ writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
+ while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+ ;
+ while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
+ ;
+}
+
+void mx28_power_set_linreg(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Set linear regulator 25mV below switching converter */
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_LINREG_OFFSET_MASK,
+ POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+ clrsetbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_LINREG_OFFSET_MASK,
+ POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
+ POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
+}
+
+void mx28_power_setup_5v_detect(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Start 5V detection */
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_VBUSVALID_TRSH_MASK,
+ POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
+ POWER_5VCTRL_PWRUP_VBUS_CMPS);
+}
+
+void mx28_src_power_init(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Improve efficieny and reduce transient ripple */
+ writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
+ POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
+
+ clrsetbits_le32(&power_regs->hw_power_dclimits,
+ POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
+ 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
+
+ setbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_EN_BATADJ);
+
+ /* Increase the RCSCALE level for quick DCDC response to dynamic load */
+ clrsetbits_le32(&power_regs->hw_power_loopctrl,
+ POWER_LOOPCTRL_EN_RCSCALE_MASK,
+ POWER_LOOPCTRL_RCSCALE_THRESH |
+ POWER_LOOPCTRL_EN_RCSCALE_8X);
+
+ clrsetbits_le32(&power_regs->hw_power_minpwr,
+ POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
+
+ /* 5V to battery handoff ... FIXME */
+ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ early_delay(30);
+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+}
+
+void mx28_power_init_4p2_params(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Setup 4P2 parameters */
+ clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
+ POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
+
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_HEADROOM_ADJ_MASK,
+ 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
+
+ clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_DROPOUT_CTRL_MASK,
+ POWER_DCDC4P2_DROPOUT_CTRL_100MV |
+ POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+ 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+}
+
+void mx28_enable_4p2_dcdc_input(int xfer)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
+ uint32_t prev_5v_brnout, prev_5v_droop;
+
+ prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_PWDN_5VBRNOUT;
+ prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
+ POWER_CTRL_ENIRQ_VDD5V_DROOP;
+
+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+ writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+ &power_regs->hw_power_reset);
+
+ clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
+
+ if (xfer && (readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return;
+ }
+
+ /*
+ * Recording orignal values that will be modified temporarlily
+ * to handle a chip bug. See chip errata for CQ ENGR00115837
+ */
+ tmp = readl(&power_regs->hw_power_5vctrl);
+ vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
+ vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
+
+ pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
+
+ /*
+ * Disable mechanisms that get erroneously tripped by when setting
+ * the DCDC4P2 EN_DCDC
+ */
+ clrbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_VBUSVALID_5VDETECT |
+ POWER_5VCTRL_VBUSVALID_TRSH_MASK);
+
+ writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
+
+ if (xfer) {
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_DCDC_XFER);
+ early_delay(20);
+ clrbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_DCDC_XFER);
+
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_ENABLE_DCDC);
+ } else {
+ setbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_ENABLE_DCDC);
+ }
+
+ early_delay(25);
+
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
+
+ if (vbus_5vdetect)
+ writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
+
+ if (!pwd_bo)
+ clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
+
+ while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
+ clrbits_le32(&power_regs->hw_power_ctrl,
+ POWER_CTRL_VBUS_VALID_IRQ);
+
+ if (prev_5v_brnout) {
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_set);
+ writel(POWER_RESET_UNLOCK_KEY,
+ &power_regs->hw_power_reset);
+ } else {
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_clr);
+ writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+ &power_regs->hw_power_reset);
+ }
+
+ while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
+ clrbits_le32(&power_regs->hw_power_ctrl,
+ POWER_CTRL_VDD5V_DROOP_IRQ);
+
+ if (prev_5v_droop)
+ clrbits_le32(&power_regs->hw_power_ctrl,
+ POWER_CTRL_ENIRQ_VDD5V_DROOP);
+ else
+ setbits_le32(&power_regs->hw_power_ctrl,
+ POWER_CTRL_ENIRQ_VDD5V_DROOP);
+}
+
+void mx28_power_init_4p2_regulator(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp, tmp2;
+
+ setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
+
+ writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
+
+ writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+ &power_regs->hw_power_5vctrl_clr);
+ clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
+
+ /* Power up the 4p2 rail and logic/control */
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_clr);
+
+ /*
+ * Start charging up the 4p2 capacitor. We ramp of this charge
+ * gradually to avoid large inrush current from the 5V cable which can
+ * cause transients/problems
+ */
+ mx28_enable_4p2_dcdc_input(0);
+
+ if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+ /*
+ * If we arrived here, we were unable to recover from mx23 chip
+ * errata 5837. 4P2 is disabled and sufficient battery power is
+ * not present. Exiting to not enable DCDC power during 5V
+ * connected state.
+ */
+ clrbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_ENABLE_DCDC);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
+ hang();
+ }
+
+ /*
+ * Here we set the 4p2 brownout level to something very close to 4.2V.
+ * We then check the brownout status. If the brownout status is false,
+ * the voltage is already close to the target voltage of 4.2V so we
+ * can go ahead and set the 4P2 current limit to our max target limit.
+ * If the brownout status is true, we need to ramp us the current limit
+ * so that we don't cause large inrush current issues. We step up the
+ * current limit until the brownout status is false or until we've
+ * reached our maximum defined 4p2 current limit.
+ */
+ clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_BO_MASK,
+ 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
+
+ if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+ } else {
+ tmp = (readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+ while (tmp < 0x3f) {
+ if (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DCDC_4P2_BO)) {
+ tmp = readl(&power_regs->hw_power_5vctrl);
+ tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+ early_delay(100);
+ writel(tmp, &power_regs->hw_power_5vctrl);
+ break;
+ } else {
+ tmp++;
+ tmp2 = readl(&power_regs->hw_power_5vctrl);
+ tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+ tmp2 |= tmp <<
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+ writel(tmp2, &power_regs->hw_power_5vctrl);
+ early_delay(100);
+ }
+ }
+ }
+
+ clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
+ writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+}
+
+void mx28_power_init_dcdc_4p2_source(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ if (!(readl(&power_regs->hw_power_dcdc4p2) &
+ POWER_DCDC4P2_ENABLE_DCDC)) {
+ hang();
+ }
+
+ mx28_enable_4p2_dcdc_input(1);
+
+ if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+ clrbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_ENABLE_DCDC);
+ writel(POWER_5VCTRL_ENABLE_DCDC,
+ &power_regs->hw_power_5vctrl_clr);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
+ }
+}
+
+void mx28_power_enable_4p2(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t vdddctrl, vddactrl, vddioctrl;
+ uint32_t tmp;
+
+ vdddctrl = readl(&power_regs->hw_power_vdddctrl);
+ vddactrl = readl(&power_regs->hw_power_vddactrl);
+ vddioctrl = readl(&power_regs->hw_power_vddioctrl);
+
+ setbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
+ POWER_VDDDCTRL_PWDN_BRNOUT);
+
+ setbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+ POWER_VDDACTRL_PWDN_BRNOUT);
+
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
+
+ mx28_power_init_4p2_params();
+ mx28_power_init_4p2_regulator();
+
+ /* Shutdown battery (none present) */
+ clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
+ writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+ writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
+
+ mx28_power_init_dcdc_4p2_source();
+
+ writel(vdddctrl, &power_regs->hw_power_vdddctrl);
+ early_delay(20);
+ writel(vddactrl, &power_regs->hw_power_vddactrl);
+ early_delay(20);
+ writel(vddioctrl, &power_regs->hw_power_vddioctrl);
+
+ /*
+ * Check if FET is enabled on either powerout and if so,
+ * disable load.
+ */
+ tmp = 0;
+ tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
+ POWER_VDDDCTRL_DISABLE_FET);
+ tmp |= !(readl(&power_regs->hw_power_vddactrl) &
+ POWER_VDDACTRL_DISABLE_FET);
+ tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
+ POWER_VDDIOCTRL_DISABLE_FET);
+ if (tmp)
+ writel(POWER_CHARGE_ENABLE_LOAD,
+ &power_regs->hw_power_charge_clr);
+}
+
+void mx28_boot_valid_5v(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /*
+ * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
+ * disconnect event. FIXME
+ */
+ writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
+ &power_regs->hw_power_5vctrl_set);
+
+ /* Configure polarity to check for 5V disconnection. */
+ writel(POWER_CTRL_POLARITY_VBUSVALID |
+ POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
+ &power_regs->hw_power_ctrl_clr);
+
+ writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+ &power_regs->hw_power_ctrl_clr);
+
+ mx28_power_enable_4p2();
+}
+
+void mx28_powerdown(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
+ writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+ &power_regs->hw_power_reset);
+}
+
+void mx28_handle_5v_conflict(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp;
+
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_BO_OFFSET_MASK);
+
+ for (;;) {
+ tmp = readl(&power_regs->hw_power_sts);
+
+ if (tmp & POWER_STS_VDDIO_BO) {
+ mx28_powerdown();
+ break;
+ }
+
+ if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
+ mx28_boot_valid_5v();
+ break;
+ } else {
+ mx28_powerdown();
+ break;
+ }
+ }
+}
+
+int mx28_get_batt_volt(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+ volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+ volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+ volt *= 8;
+ return volt;
+}
+
+int mx28_is_batt_ready(void)
+{
+ return (mx28_get_batt_volt() >= 3600);
+}
+
+void mx28_5v_boot(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /*
+ * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
+ * but their implementation always returns 1 so we omit it here.
+ */
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ mx28_boot_valid_5v();
+ return;
+ }
+
+ early_delay(1000);
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ mx28_boot_valid_5v();
+ return;
+ }
+
+ mx28_handle_5v_conflict();
+}
+
+void mx28_init_batt_bo(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Brownout at 3V */
+ clrsetbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
+ 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+
+ writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+ writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+}
+
+void mx28_switch_vddd_to_dcdc_source(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_LINREG_OFFSET_MASK,
+ POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+ clrbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
+ POWER_VDDDCTRL_DISABLE_STEPPING);
+}
+
+int mx28_is_batt_good(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t volt;
+
+ volt = readl(&power_regs->hw_power_battmonitor);
+ volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+ volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+ volt *= 8;
+
+ if ((volt >= 2400) && (volt <= 4300))
+ return 1;
+
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+ 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_clr);
+
+ clrsetbits_le32(&power_regs->hw_power_charge,
+ POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+ POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
+
+ writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_clr);
+
+ early_delay(500000);
+
+ volt = readl(&power_regs->hw_power_battmonitor);
+ volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+ volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+ volt *= 8;
+
+ if (volt >= 3500)
+ return 0;
+
+ if (volt >= 2400)
+ return 1;
+
+ writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+ &power_regs->hw_power_charge_clr);
+ writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+ return 0;
+}
+
+void mx28_power_configure_power_source(void)
+{
+ mx28_src_power_init();
+
+ mx28_5v_boot();
+ mx28_power_clock2pll();
+
+ mx28_init_batt_bo();
+ mx28_switch_vddd_to_dcdc_source();
+}
+
+void mx28_enable_output_rail_protection(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
+ POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+
+ setbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_PWDN_BRNOUT);
+
+ setbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_PWDN_BRNOUT);
+
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_PWDN_BRNOUT);
+}
+
+int mx28_get_vddio_power_source_off(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp;
+
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ tmp = readl(&power_regs->hw_power_vddioctrl);
+ if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
+ if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
+ }
+ }
+
+ if (!(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+
+}
+
+int mx28_get_vddd_power_source_off(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp;
+
+ tmp = readl(&power_regs->hw_power_vdddctrl);
+ if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
+ if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
+ }
+ }
+
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if (!(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return 1;
+ }
+ }
+
+ if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
+ if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t cur_target, diff, bo_int = 0;
+ uint32_t powered_by_linreg = 0;
+
+ new_brownout = new_target - new_brownout;
+
+ cur_target = readl(&power_regs->hw_power_vddioctrl);
+ cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+ cur_target *= 50; /* 50 mV step*/
+ cur_target += 2800; /* 2800 mV lowest */
+
+ powered_by_linreg = mx28_get_vddio_power_source_off();
+ if (new_target > cur_target) {
+
+ if (powered_by_linreg) {
+ bo_int = readl(&power_regs->hw_power_vddioctrl);
+ clrbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_CTRL_ENIRQ_VDDIO_BO);
+ }
+
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_BO_OFFSET_MASK);
+ do {
+ if (new_target - cur_target > 100)
+ diff = cur_target + 100;
+ else
+ diff = new_target;
+
+ diff -= 2800;
+ diff /= 50;
+
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_TRG_MASK, diff);
+
+ if (powered_by_linreg)
+ early_delay(1500);
+ else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK))
+ ;
+
+ }
+
+ cur_target = readl(&power_regs->hw_power_vddioctrl);
+ cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+ cur_target *= 50; /* 50 mV step*/
+ cur_target += 2800; /* 2800 mV lowest */
+ } while (new_target > cur_target);
+
+ if (powered_by_linreg) {
+ writel(POWER_CTRL_VDDIO_BO_IRQ,
+ &power_regs->hw_power_ctrl_clr);
+ if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_CTRL_ENIRQ_VDDIO_BO);
+ }
+ } else {
+ do {
+ if (cur_target - new_target > 100)
+ diff = cur_target - 100;
+ else
+ diff = new_target;
+
+ diff -= 2800;
+ diff /= 50;
+
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_TRG_MASK, diff);
+
+ if (powered_by_linreg)
+ early_delay(1500);
+ else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK))
+ ;
+
+ }
+
+ cur_target = readl(&power_regs->hw_power_vddioctrl);
+ cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+ cur_target *= 50; /* 50 mV step*/
+ cur_target += 2800; /* 2800 mV lowest */
+ } while (new_target < cur_target);
+ }
+
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDDCTRL_BO_OFFSET_MASK,
+ new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+}
+
+void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t cur_target, diff, bo_int = 0;
+ uint32_t powered_by_linreg = 0;
+
+ new_brownout = new_target - new_brownout;
+
+ cur_target = readl(&power_regs->hw_power_vdddctrl);
+ cur_target &= POWER_VDDDCTRL_TRG_MASK;
+ cur_target *= 25; /* 25 mV step*/
+ cur_target += 800; /* 800 mV lowest */
+
+ powered_by_linreg = mx28_get_vddd_power_source_off();
+ if (new_target > cur_target) {
+ if (powered_by_linreg) {
+ bo_int = readl(&power_regs->hw_power_vdddctrl);
+ clrbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_CTRL_ENIRQ_VDDD_BO);
+ }
+
+ setbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_BO_OFFSET_MASK);
+
+ do {
+ if (new_target - cur_target > 100)
+ diff = cur_target + 100;
+ else
+ diff = new_target;
+
+ diff -= 800;
+ diff /= 25;
+
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_TRG_MASK, diff);
+
+ if (powered_by_linreg)
+ early_delay(1500);
+ else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK))
+ ;
+
+ }
+
+ cur_target = readl(&power_regs->hw_power_vdddctrl);
+ cur_target &= POWER_VDDDCTRL_TRG_MASK;
+ cur_target *= 25; /* 25 mV step*/
+ cur_target += 800; /* 800 mV lowest */
+ } while (new_target > cur_target);
+
+ if (powered_by_linreg) {
+ writel(POWER_CTRL_VDDD_BO_IRQ,
+ &power_regs->hw_power_ctrl_clr);
+ if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
+ setbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_CTRL_ENIRQ_VDDD_BO);
+ }
+ } else {
+ do {
+ if (cur_target - new_target > 100)
+ diff = cur_target - 100;
+ else
+ diff = new_target;
+
+ diff -= 800;
+ diff /= 25;
+
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_TRG_MASK, diff);
+
+ if (powered_by_linreg)
+ early_delay(1500);
+ else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK))
+ ;
+
+ }
+
+ cur_target = readl(&power_regs->hw_power_vdddctrl);
+ cur_target &= POWER_VDDDCTRL_TRG_MASK;
+ cur_target *= 25; /* 25 mV step*/
+ cur_target += 800; /* 800 mV lowest */
+ } while (new_target < cur_target);
+ }
+
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_BO_OFFSET_MASK,
+ new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+}
+
+void mx28_power_init(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ mx28_power_clock2xtal();
+ mx28_power_clear_auto_restart();
+ mx28_power_set_linreg();
+ mx28_power_setup_5v_detect();
+ mx28_power_configure_power_source();
+ mx28_enable_output_rail_protection();
+
+ mx28_power_set_vddio(3300, 3150);
+
+ mx28_power_set_vddd(1350, 1200);
+
+ writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
+ POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
+ POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
+ POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
+
+ early_delay(1000);
+}
+
+#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
+void mx28_power_wait_pswitch(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
+ ;
+}
+#endif
diff --git a/board/denx/m28evk/start.S b/board/denx/m28evk/start.S
new file mode 100644
index 0000000..cf67599
--- /dev/null
+++ b/board/denx/m28evk/start.S
@@ -0,0 +1,396 @@
+/*
+ * armboot - Startup Code for ARM926EJS CPU-core
+ *
+ * Copyright (c) 2003 Texas Instruments
+ *
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ * Copyright (c) 2001 Marius Groger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
+ *
+ * Change to support call back into iMX28 bootrom
+ * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#elif defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:
+ b reset
+#ifdef CONFIG_SPL_BUILD
+/* No exception handlers in preloader */
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ b reset
+ ldr pc, _hang
+ ldr pc, _hang
+
+_hang:
+ .word do_hang
+/* pad to 64 byte boundary */
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+#else
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction:
+ .word undefined_instruction
+_software_interrupt:
+ .word software_interrupt
+_prefetch_abort:
+ .word prefetch_abort
+_data_abort:
+ .word data_abort
+_not_used:
+ .word not_used
+_irq:
+ .word irq
+_fiq:
+ .word fiq
+
+#endif /* CONFIG_SPL_BUILD */
+ .balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+.globl _TEXT_BASE
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
+ .word _end - _start
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+ .word 0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+ /*
+ * Store all registers on old stack pointer, this will allow us later to
+ * return to the BootROM and let the BootROM load U-Boot into RAM.
+ */
+ push {r0-r12,r14}
+
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ bl cpu_init_crit
+#endif
+
+ bl board_init_ll
+
+ pop {r0-r12,r14}
+ bx lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
+ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
+ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
+ mcr p15, 0, r0, c1, c0, 0
+
+ mov pc, lr /* back to my caller */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ @ carve out a frame on current user stack
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
+ ldr r2, IRQ_STACK_START_IN
+ @ get values for "aborted" pc and cpsr (into parm regs)
+ ldmia r2, {r2 - r3}
+ add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
+ mov r0, sp @ save current stack into r0 (param register)
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, IRQ_STACK_START_IN @ setup our mode stack
+
+ str lr, [r13] @ save caller lr in position 0 of saved stack
+ mrs lr, spsr @ get the spsr
+ str lr, [r13, #4] @ save spsr in position 1 of saved stack
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ @ msr spsr_c, r13
+ msr spsr, r13 @ switch modes, make sure moves will execute
+ mov lr, pc @ capture return pc
+ movs pc, lr @ jump to next instruction & switch modes.
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * exception handlers
+ */
+#ifdef CONFIG_SPL_BUILD
+ .align 5
+do_hang:
+ ldr sp, _TEXT_BASE /* switch to abort stack */
+1:
+ bl 1b /* hang and never return */
+#else /* !CONFIG_SPL_BUILD */
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/denx/m28evk/u-boot-spl.lds b/board/denx/m28evk/u-boot-spl.lds
new file mode 100644
index 0000000..e296a92
--- /dev/null
+++ b/board/denx/m28evk/u-boot-spl.lds
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ board/denx/m28evk/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ /DISCARD/ : { *(.bss*) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynsym*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.hash*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
diff --git a/board/denx/m28evk/u-boot.bd b/board/denx/m28evk/u-boot.bd
new file mode 100644
index 0000000..3ce7f92
--- /dev/null
+++ b/board/denx/m28evk/u-boot.bd
@@ -0,0 +1,14 @@
+sources {
+ u_boot_spl="spl/u-boot-spl.bin";
+ u_boot="u-boot.bin";
+}
+
+section (0) {
+ load u_boot_spl > 0x0000;
+ load ivt (entry = 0x0014) > 0x8000;
+ hab call 0x8000;
+
+ load u_boot > 0x40000100;
+ load ivt (entry = 0x40000100) > 0x8000;
+ hab call 0x8000;
+}
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index d88e09e..59e3e05 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -43,6 +43,14 @@
#define CONFIG_ARCH_CPU_INIT
/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "board/denx/m28evk"
+#define CONFIG_SPL_LDSCRIPT "board/denx/m28evk/u-boot-spl.lds"
+
+/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
--
1.7.6.3
^ permalink raw reply related
* [U-Boot] [PATCH 13/17 V5] iMX28: Add support for DENX M28EVK board
From: Marek Vasut @ 2011-10-31 11:42 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1319237066-14954-14-git-send-email-marek.vasut@gmail.com>
This contains support for the following components:
- DUART
- MMC
- Both FEC interfaces
- NAND
- I2C (RTC, EEPROM)
- SPI (FLASH)
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
---
MAINTAINERS | 1 +
board/denx/m28evk/Makefile | 43 +++++++
board/denx/m28evk/m28evk.c | 195 ++++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/m28evk.h | 282 ++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 522 insertions(+), 0 deletions(-)
create mode 100644 board/denx/m28evk/Makefile
create mode 100644 board/denx/m28evk/m28evk.c
create mode 100644 include/configs/m28evk.h
V2: Use scrub -y instead of scrub.quiet in the scripts.
V3: Use CONFIG_ENV_RANGE
V4: Configure the RAM size to 128MB for V1.1 module
V5: Drop clean and distclean targets
diff --git a/MAINTAINERS b/MAINTAINERS
index bb95e6d..12c9e96 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -841,6 +841,7 @@ Marek Vasut <marek.vasut@gmail.com>
palmtc xscale/pxa
vpac270 xscale/pxa
zipitz2 xscale/pxa
+ m28evk i.MX28
efikamx i.MX51
efikasb i.MX51
diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile
new file mode 100644
index 0000000..e6aba9a
--- /dev/null
+++ b/board/denx/m28evk/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := m28evk.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
new file mode 100644
index 0000000..118e222
--- /dev/null
+++ b/board/denx/m28evk/m28evk.c
@@ -0,0 +1,195 @@
+/*
+ * DENX M28 module
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* SSP2 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int m28_mmc_wp(int id)
+{
+ if (id != 0) {
+ printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+ return 1;
+ }
+
+ return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /* Configure WP as output */
+ gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+
+ return mxsmmc_initialize(bis, 0, m28_mmc_wp);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+
+#define MII_OPMODE_STRAP_OVERRIDE 0x16
+#define MII_PHY_CTRL1 0x1e
+#define MII_PHY_CTRL2 0x1f
+
+int fecmxc_mii_postcall(int phy)
+{
+ miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+ miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+ if (phy == 3)
+ miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+ CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
+ CLKCTRL_ENET_TIME_SEL_RMII_CLK);
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC0");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC0 device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC0 mii postcall\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC1");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC1 device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC1 mii postcall\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP
+
+#define MXS_OCOTP_MAX_TIMEOUT 1000000
+void imx_get_mac_from_fuse(char *mac)
+{
+ struct mx28_ocotp_regs *ocotp_regs =
+ (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+ uint32_t data;
+
+ memset(mac, 0, 6);
+
+ writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+ if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+ MXS_OCOTP_MAX_TIMEOUT)) {
+ printf("MXS FEC: Can't get MAC from OCOTP\n");
+ return;
+ }
+
+ data = readl(&ocotp_regs->hw_ocotp_cust0);
+
+ mac[0] = 0x00;
+ mac[1] = 0x04;
+ mac[2] = (data >> 24) & 0xff;
+ mac[3] = (data >> 16) & 0xff;
+ mac[4] = (data >> 8) & 0xff;
+ mac[5] = data & 0xff;
+}
+#else
+void imx_get_mac_from_fuse(char *mac)
+{
+ memset(mac, 0, 6);
+}
+#endif
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1776a73..c863c82 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -152,6 +152,7 @@ tx25 arm arm926ejs tx25 karo
zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
+m28evk arm arm926ejs - denx mx28
nhk8815 arm arm926ejs nhk8815 st nomadik
nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
omap5912osk arm arm926ejs - ti omap
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
new file mode 100644
index 0000000..d88e09e
--- /dev/null
+++ b/include/configs/m28evk.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __M28_H__
+#define __M28_H__
+
+#include <asm/arch/regs-base.h>
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_MX28 /* i.MX28 SoC */
+#define CONFIG_MXS_GPIO /* GPIO control */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+
+/*
+ * Define M28EVK machine type by hand until it lands in mach-types
+ */
+#define MACH_TYPE_M28EVK 3613
+
+#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_CPU_INIT
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 2 banks of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
+#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+/* Point initial SP in SRAM so SPL can use it too. */
+#define CONFIG_SYS_INIT_SP_ADDR 0x00002000
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x40000100
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXS_MMC
+#endif
+
+/*
+ * NAND
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MXS
+#define CONFIG_APBH_DMA
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define NAND_MAX_CHIPS 8
+
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_RANGE (512 * 1024)
+#define CONFIG_ENV_OFFSET 0x300000
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=gpmi-nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=gpmi-nand.0:" \
+ "3m(bootloader)ro," \
+ "512k(environment)," \
+ "512k(redundant-environment)," \
+ "4m(kernel)," \
+ "-(filesystem)"
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE RMII
+#endif
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
+/*
+ * EEPROM
+ */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+/* Use the internal RTC in the MXS chip */
+#define CONFIG_RTC_INTERNAL
+#ifdef CONFIG_RTC_INTERNAL
+#define CONFIG_RTC_MXS
+#else
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+#endif
+#endif
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_HARD_SPI
+#define CONFIG_MXS_SPI
+#define CONFIG_SPI_HALF_DUPLEX
+#define CONFIG_DEFAULT_SPI_BUS 2
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
+
+/* SPI FLASH */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_CS 2
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_BUS 2
+#define CONFIG_ENV_SPI_MAX_HZ 24000000
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#endif
+#endif
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "
+#define CONFIG_BOOTCOMMAND "run bootcmd_net"
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "update_nand_full_filename=u-boot.nand\0" \
+ "update_nand_firmware_filename=u-boot.sb\0" \
+ "update_nand_firmware_maxsz=0x100000\0" \
+ "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \
+ "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \
+ "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \
+ "nand device 0 ; " \
+ "nand info ; " \
+ "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+ "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+ "update_nand_full=" /* Update FCB, DBBT and FW */ \
+ "if tftp ${update_nand_full_filename} ; then " \
+ "run update_nand_get_fcb_size ; " \
+ "nand scrub -y 0x0 ${filesize} ; " \
+ "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
+ "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+ "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+ "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+ "fi\0" \
+ "update_nand_firmware=" /* Update only firmware */ \
+ "if tftp ${update_nand_firmware_filename} ; then " \
+ "run update_nand_get_fcb_size ; " \
+ "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+ "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
+ "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+ "nand erase ${fcb_sz} ${fw_sz} ; " \
+ "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
+ "nand write ${loadaddr} ${fw_off} ${filesize} ; " \
+ "fi\0"
+
+#endif /* __M28_H__ */
--
1.7.6.3
^ permalink raw reply related
* Re: HT (Hyper Threading) aware process scheduling doesn't work as it should
From: Mike Galbraith @ 2011-10-31 11:42 UTC (permalink / raw)
To: Con Kolivas; +Cc: Artem S. Tashkinov, linux-kernel
In-Reply-To: <1479015.f2tEjKr9vR@quad>
On Mon, 2011-10-31 at 21:06 +1100, Con Kolivas wrote:
> On Sun, 30 Oct 2011 07:57:12 PM Artem S. Tashkinov wrote:
> > I've found out that even on Linux 3.0.8 the process scheduler doesn't
> > correctly distributes the load amongst virtual CPUs. E.g. on a 4-core
> > system (8 total virtual CPUs) the process scheduler often run some
> > instances of four different tasks on the same physical CPU.
>
> > Any thoughts? comments? I think this is quite a serious problem.
>
> Intense cache locality logic, power saving concepts, cpu frequency governor
> behaviour and separate runqueues per CPU within the current CPU process
> scheduler in the current mainline linux kernel will ocasionally do this. Some
> workloads will be better, while others will be worse. Feel free to try my BFS
> cpu scheduler if you wish a CPU process scheduler that spreads work more
> evenly across CPUs.
>
> Alas the last version I synced up with will not apply cleanly past about 3.0.6
> I believe:
>
> http://ck.kolivas.org/patches/bfs/3.0.0/3.0-sched-bfs-413.patch
Yeah, it handles independent tasks well, but cache misses can be
excruciatingly painful for the others.
Q6600 box, configs as identical as possible, tbench 8
3.0.6-bfs413 728.6 MB/sec
3.0.8 1146.7 MB/sec
-Mike
^ permalink raw reply
* Re: linux-next 20111025: warnings in rcu_idle_exit_common()/rcu_idle_enter_common()
From: Wu Fengguang @ 2011-10-31 11:41 UTC (permalink / raw)
To: Paul E. McKenney
Cc: Steven Rostedt, linux-kernel@vger.kernel.org, Ingo Molnar,
Lai Jiangshan, Frederic Weisbecker
In-Reply-To: <20111031104325.GA25808@localhost>
On Mon, Oct 31, 2011 at 06:43:25PM +0800, Wu Fengguang wrote:
> On Mon, Oct 31, 2011 at 05:51:52PM +0800, Paul E. McKenney wrote:
> > On Mon, Oct 31, 2011 at 04:26:34PM +0800, Wu Fengguang wrote:
> > > Hi Paul,
> > >
> > > I got two warnings in rcutree.c. The last working kernels are
> > > linux-next 20111014 and linux v3.1.
> >
> > Interesting. Could you please enable RCU event tracing at boot?
>
> Sorry I cannot...possibly due to another ftrace bug.
>
> > The RCU event tracing is at tracing/events/rcu/enable relative to
> > the debugfs mount point at runtime, if that helps.
>
> It's exactly that linux next 20111025 (comparing to 20111014) no
> longer produces all the trace events that made me looking into the
> dmesg and find the warning from RCU (rather than the expected warning
> from ftrace).
>
> The trace output is now:
>
> # tracer: nop
> #
> # WARNING: FUNCTION TRACING IS CORRUPTED
> # MAY BE MISSING FUNCTION EVENTS
> # TASK-PID CPU# TIMESTAMP FUNCTION
> # | | | | |
> (nothing more)
I checked the other test box and got the same warnings. Below is the
full dmesg.
No single trace output again..
Thanks,
Fengguang
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Linux version 3.1.0-ioless-full-next-20111025+ (wfg@bee) (gcc version 4.5.0 (GCC) ) #881 SMP Mon Oct 31 01:03:49 CST 2011
[ 0.000000] Command line: nousb hpet=disable run=/home/wfg/ioless-balance_dirty_pages/test-each-fs.sh log_buf_len=8M debug sched_debug apic=debug dynamic_printk drm.debug=6 sysrq_always_enabled panic=10 unknown_nmi_panic=1 nmi_watchdog=panic,lapic load_ramdisk=2 prompt_ramdisk=0 console=ttyS0,115200 console=tty0 netconsole=@:/eth0,6666@192.168.1.1/00:30:48:fe:19:95 ip=192.168.1.61:192.168.1.11:192.168.1.1:255.255.255.0:snb:eth0:none nfsroot=192.168.1.11:/nfsroot/wfg,tcp,v3,nocto,nolock,rsize=524288,wsize=524288 rw BOOT_IMAGE=x86_64/vmlinuz-3.1.0-ioless-full-next-20111025+
[ 0.000000] KERNEL supported cpus:
[ 0.000000] Intel GenuineIntel
[ 0.000000] Centaur CentaurHauls
[ 0.000000] BIOS-provided physical RAM map:
[ 0.000000] BIOS-e820: 0000000000000000 - 000000000009bc00 (usable)
[ 0.000000] BIOS-e820: 000000000009bc00 - 00000000000a0000 (reserved)
[ 0.000000] BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
[ 0.000000] BIOS-e820: 0000000000100000 - 00000000ab664000 (usable)
[ 0.000000] BIOS-e820: 00000000ab664000 - 00000000ab821000 (ACPI NVS)
[ 0.000000] BIOS-e820: 00000000ab821000 - 00000000bea7d000 (usable)
[ 0.000000] BIOS-e820: 00000000bea7d000 - 00000000beae9000 (ACPI data)
[ 0.000000] BIOS-e820: 00000000beae9000 - 00000000beaf2000 (usable)
[ 0.000000] BIOS-e820: 00000000beaf2000 - 00000000beb03000 (reserved)
[ 0.000000] BIOS-e820: 00000000beb03000 - 00000000bed2e000 (usable)
[ 0.000000] BIOS-e820: 00000000bed2e000 - 00000000bede7000 (reserved)
[ 0.000000] BIOS-e820: 00000000bede7000 - 00000000bee2f000 (ACPI NVS)
[ 0.000000] BIOS-e820: 00000000bee2f000 - 00000000bee30000 (ACPI data)
[ 0.000000] BIOS-e820: 00000000bee30000 - 00000000bee9b000 (ACPI NVS)
[ 0.000000] BIOS-e820: 00000000bee9b000 - 00000000bee9d000 (ACPI data)
[ 0.000000] BIOS-e820: 00000000bee9d000 - 00000000bee9e000 (ACPI NVS)
[ 0.000000] BIOS-e820: 00000000bee9e000 - 00000000beeb9000 (ACPI data)
[ 0.000000] BIOS-e820: 00000000beeb9000 - 00000000befc1000 (ACPI NVS)
[ 0.000000] BIOS-e820: 00000000befc1000 - 00000000bf000000 (usable)
[ 0.000000] BIOS-e820: 00000000bf000000 - 00000000d0000000 (reserved)
[ 0.000000] BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved)
[ 0.000000] BIOS-e820: 00000000fed19000 - 00000000fed1a000 (reserved)
[ 0.000000] BIOS-e820: 00000000fed1c000 - 00000000fed20000 (reserved)
[ 0.000000] BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
[ 0.000000] BIOS-e820: 00000000ffa20000 - 0000000100000000 (reserved)
[ 0.000000] BIOS-e820: 0000000100000000 - 0000000840000000 (usable)
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] DMI 2.6 present.
[ 0.000000] DMI: Intel Corporation SandyBridge Platform/To be filled by O.E.M., BIOS ROMLEYEP.86B.99.99.x020.022420111310 02/24/2011
[ 0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
[ 0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
[ 0.000000] last_pfn = 0x840000 max_arch_pfn = 0x400000000
[ 0.000000] MTRR default type: uncachable
[ 0.000000] MTRR fixed ranges enabled:
[ 0.000000] 00000-9FFFF write-back
[ 0.000000] A0000-BFFFF uncachable
[ 0.000000] C0000-CBFFF write-protect
[ 0.000000] CC000-E7FFF uncachable
[ 0.000000] E8000-FFFFF write-protect
[ 0.000000] MTRR variable ranges enabled:
[ 0.000000] 0 base 000000000000 mask 3FFF80000000 write-back
[ 0.000000] 1 base 000080000000 mask 3FFFC0000000 write-back
[ 0.000000] 2 base 000100000000 mask 3FFF00000000 write-back
[ 0.000000] 3 base 000200000000 mask 3FFE00000000 write-back
[ 0.000000] 4 base 000400000000 mask 3FFC00000000 write-back
[ 0.000000] 5 base 000800000000 mask 3FFFC0000000 write-back
[ 0.000000] 6 base 0000FF800000 mask 3FFFFF800000 write-protect
[ 0.000000] 7 disabled
[ 0.000000] 8 disabled
[ 0.000000] 9 disabled
[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
[ 0.000000] last_pfn = 0xbf000 max_arch_pfn = 0x400000000
[ 0.000000] Scan SMP from ffff880000000000 for 1024 bytes.
[ 0.000000] Scan SMP from ffff88000009fc00 for 1024 bytes.
[ 0.000000] Scan SMP from ffff8800000f0000 for 65536 bytes.
[ 0.000000] found SMP MP-table at [ffff8800000fcda0] fcda0
[ 0.000000] mpc: fc7d0-fcc7c
[ 0.000000] initial memory mapped : 0 - 20000000
[ 0.000000] Base memory trampoline at [ffff880000096000] 96000 size 20480
[ 0.000000] Using GB pages for direct mapping
[ 0.000000] init_memory_mapping: 0000000000000000-00000000bf000000
[ 0.000000] 0000000000 - 00bf000000 page 4k
[ 0.000000] kernel direct mapping tables up to bf000000 @ 1fa06000-20000000
[ 0.000000] init_memory_mapping: 0000000100000000-0000000840000000
[ 0.000000] 0100000000 - 0840000000 page 4k
[ 0.000000] kernel direct mapping tables up to 840000000 @ bb060000-bea7d000
[ 0.000000] log_buf_len: 8388608
[ 0.000000] early log buf free: 256692(97%)
[ 0.000000] ACPI: RSDP 00000000000f0410 00024 (v02 INTEL)
[ 0.000000] ACPI: XSDT 00000000beeb7e18 000AC (v01 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: FACP 00000000beeb6918 000F4 (v04 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: DSDT 00000000bee9e018 16368 (v02 INTEL ROMLEY 00000099 INTL 20100331)
[ 0.000000] ACPI: FACS 00000000beeb7d40 00040
[ 0.000000] ACPI: APIC 00000000beeb5018 0066A (v03 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: SPMI 00000000beeb8b18 00040 (v05 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: MCFG 00000000beeb8f18 0003C (v01 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: WDDT 00000000beeb8e98 00040 (v01 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: SRAT 00000000bee9c918 002A8 (v03 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: SLIT 00000000beeb8e18 00030 (v01 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: MSCT 00000000bee2ff18 00090 (v01 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: HPET 00000000beeb8d18 00038 (v01 INTL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: SSDT 00000000beeb8d98 0002B (v02 INTEL PtidDevc 00001000 INTL 20100331)
[ 0.000000] ACPI: BOOT 00000000beeb8c98 00028 (v01 INTEL ROMLEY 06222004 INTL 20090903)
[ 0.000000] ACPI: SSDT 00000000bea7d018 6B356 (v02 INTEL CpuPm 00004000 INTL 20100331)
[ 0.000000] ACPI: DMAR 00000000bee9be18 001B8 (v01 INTEL RML 00000001 INTL 00000001)
[ 0.000000] ACPI: HEST 00000000bee9cf18 000A8 (v01 INTEL CNPASSDP 00000001 INTL 00000001)
[ 0.000000] ACPI: BERT 00000000beeb8c18 00030 (v01 INTEL CNPASSDP 00000001 INTL 00000001)
[ 0.000000] ACPI: ERST 00000000bee2fa18 00230 (v01 INTEL CNPASSDP 00000001 INTL 00000001)
[ 0.000000] ACPI: EINJ 00000000beeb6d98 00150 (v01 INTEL CNPASSDP 00000001 INTL 00000001)
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] mapped APIC to ffffffffff5fb000 ( fee00000)
[ 0.000000] SRAT: PXM 0 -> APIC 0x00 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x01 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x02 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x03 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x04 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x05 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x06 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x07 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x08 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x09 -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x0a -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x0b -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x0c -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x0d -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x0e -> Node 0
[ 0.000000] SRAT: PXM 0 -> APIC 0x0f -> Node 0
[ 0.000000] SRAT: PXM 1 -> APIC 0x20 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x21 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x22 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x23 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x24 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x25 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x26 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x27 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x28 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x29 -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x2a -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x2b -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x2c -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x2d -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x2e -> Node 1
[ 0.000000] SRAT: PXM 1 -> APIC 0x2f -> Node 1
[ 0.000000] SRAT: Node 0 PXM 0 0-c0000000
[ 0.000000] SRAT: Node 0 PXM 0 100000000-440000000
[ 0.000000] SRAT: Node 1 PXM 1 440000000-840000000
[ 0.000000] NUMA: Initialized distance table, cnt=2
[ 0.000000] NUMA: Node 0 [0,c0000000) + [100000000,440000000) -> [0,440000000)
[ 0.000000] Initmem setup node 0 0000000000000000-0000000440000000
[ 0.000000] NODE_DATA [000000043fffb000 - 000000043fffffff]
[ 0.000000] Initmem setup node 1 0000000440000000-0000000840000000
[ 0.000000] NODE_DATA [000000083f7fa000 - 000000083f7fefff]
[ 0.000000] [ffffea0000000000-ffffea0010ffffff] PMD -> [ffff88042fe00000-ffff88043fdfffff] on node 0
[ 0.000000] [ffffea0011000000-ffffea0020ffffff] PMD -> [ffff88082ee00000-ffff88083edfffff] on node 1
[ 0.000000] Zone PFN ranges:
[ 0.000000] DMA 0x00000010 -> 0x00001000
[ 0.000000] DMA32 0x00001000 -> 0x00100000
[ 0.000000] Normal 0x00100000 -> 0x00840000
[ 0.000000] Movable zone start PFN for each node
[ 0.000000] early_node_map[8] active PFN ranges
[ 0.000000] 0: 0x00000010 -> 0x0000009b
[ 0.000000] 0: 0x00000100 -> 0x000ab664
[ 0.000000] 0: 0x000ab821 -> 0x000bea7d
[ 0.000000] 0: 0x000beae9 -> 0x000beaf2
[ 0.000000] 0: 0x000beb03 -> 0x000bed2e
[ 0.000000] 0: 0x000befc1 -> 0x000bf000
[ 0.000000] 0: 0x00100000 -> 0x00440000
[ 0.000000] 1: 0x00440000 -> 0x00840000
[ 0.000000] On node 0 totalpages: 4188862
[ 0.000000] DMA zone: 64 pages used for memmap
[ 0.000000] DMA zone: 5 pages reserved
[ 0.000000] DMA zone: 3910 pages, LIFO batch:0
[ 0.000000] DMA32 zone: 16320 pages used for memmap
[ 0.000000] DMA32 zone: 760691 pages, LIFO batch:31
[ 0.000000] Normal zone: 53248 pages used for memmap
[ 0.000000] Normal zone: 3354624 pages, LIFO batch:31
[ 0.000000] On node 1 totalpages: 4194304
[ 0.000000] Normal zone: 65536 pages used for memmap
[ 0.000000] Normal zone: 4128768 pages, LIFO batch:31
[ 0.000000] ACPI: PM-Timer IO Port: 0x408
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] mapped APIC to ffffffffff5fb000 ( fee00000)
[ 0.000000] ACPI: X2APIC (apic_id[0x00] uid[0x00] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x01] uid[0x01] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x02] uid[0x02] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x03] uid[0x03] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x04] uid[0x04] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x05] uid[0x05] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x06] uid[0x06] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x07] uid[0x07] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x08] uid[0x08] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x09] uid[0x09] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x0a] uid[0x0a] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x0b] uid[0x0b] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x0c] uid[0x0c] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x0d] uid[0x0d] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x0e] uid[0x0e] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x0f] uid[0x0f] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x10] uid[0x10] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x11] uid[0x11] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x12] uid[0x12] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x13] uid[0x13] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x14] uid[0x14] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x15] uid[0x15] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x16] uid[0x16] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x17] uid[0x17] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x18] uid[0x18] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x19] uid[0x19] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x1a] uid[0x1a] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x1b] uid[0x1b] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x1c] uid[0x1c] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x1d] uid[0x1d] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x1e] uid[0x1e] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x1f] uid[0x1f] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x20] uid[0x20] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x21] uid[0x21] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x22] uid[0x22] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x23] uid[0x23] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x24] uid[0x24] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x25] uid[0x25] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x26] uid[0x26] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x27] uid[0x27] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x28] uid[0x28] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x29] uid[0x29] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x2a] uid[0x2a] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x2b] uid[0x2b] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x2c] uid[0x2c] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x2d] uid[0x2d] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x2e] uid[0x2e] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x2f] uid[0x2f] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x30] uid[0x30] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x31] uid[0x31] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x32] uid[0x32] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x33] uid[0x33] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x34] uid[0x34] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x35] uid[0x35] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x36] uid[0x36] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x37] uid[0x37] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x38] uid[0x38] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x39] uid[0x39] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x3a] uid[0x3a] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x3b] uid[0x3b] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x3c] uid[0x3c] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x3d] uid[0x3d] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x3e] uid[0x3e] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: X2APIC (apic_id[0x3f] uid[0x3f] disabled)
[ 0.000000] ACPI: x2apic entry ignored
[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x04] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x06] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x08] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x0a] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x0c] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x0e] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x08] lapic_id[0x20] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x09] lapic_id[0x22] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x24] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x26] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x28] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x2a] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x2c] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x2e] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x10] lapic_id[0x01] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x11] lapic_id[0x03] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x12] lapic_id[0x05] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x13] lapic_id[0x07] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x14] lapic_id[0x09] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x15] lapic_id[0x0b] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x16] lapic_id[0x0d] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x17] lapic_id[0x0f] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x18] lapic_id[0x21] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x19] lapic_id[0x23] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x1a] lapic_id[0x25] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x1b] lapic_id[0x27] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x1c] lapic_id[0x29] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x1d] lapic_id[0x2b] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x1e] lapic_id[0x2d] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x1f] lapic_id[0x2f] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x20] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x21] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x22] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x23] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x24] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x25] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x26] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x27] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x28] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x29] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x2a] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x2b] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x2c] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x2d] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x2e] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x2f] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x30] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x31] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x32] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x33] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x34] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x35] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x36] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x37] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x38] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x39] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x3a] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x3b] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x3c] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x3d] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x3e] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x3f] lapic_id[0xff] disabled)
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0xff] dfl dfl lint[0x1])
[ 0.000000] ACPI: IOAPIC (id[0x00] address[0xfec00000] gsi_base[0])
[ 0.000000] IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
[ 0.000000] ACPI: IOAPIC (id[0x01] address[0xfec3f000] gsi_base[24])
[ 0.000000] IOAPIC[1]: apic_id 1, version 32, address 0xfec3f000, GSI 24-47
[ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec7f000] gsi_base[48])
[ 0.000000] IOAPIC[2]: apic_id 2, version 32, address 0xfec7f000, GSI 48-71
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 00, APIC ID 0, APIC INT 02
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[ 0.000000] Int: type 0, pol 1, trig 3, bus 00, IRQ 09, APIC ID 0, APIC INT 09
[ 0.000000] ACPI: IRQ0 used by override.
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 01, APIC ID 0, APIC INT 01
[ 0.000000] ACPI: IRQ2 used by override.
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 03, APIC ID 0, APIC INT 03
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 04, APIC ID 0, APIC INT 04
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 05, APIC ID 0, APIC INT 05
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 06, APIC ID 0, APIC INT 06
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 07, APIC ID 0, APIC INT 07
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 08, APIC ID 0, APIC INT 08
[ 0.000000] ACPI: IRQ9 used by override.
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 0a, APIC ID 0, APIC INT 0a
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 0b, APIC ID 0, APIC INT 0b
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 0c, APIC ID 0, APIC INT 0c
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 0d, APIC ID 0, APIC INT 0d
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 0e, APIC ID 0, APIC INT 0e
[ 0.000000] Int: type 0, pol 0, trig 0, bus 00, IRQ 0f, APIC ID 0, APIC INT 0f
[ 0.000000] Using ACPI (MADT) for SMP configuration information
[ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 0.000000] SMP: Allowing 64 CPUs, 32 hotplug CPUs
[ 0.000000] mapped IOAPIC to ffffffffff5fa000 (fec00000)
[ 0.000000] mapped IOAPIC to ffffffffff5f9000 (fec3f000)
[ 0.000000] mapped IOAPIC to ffffffffff5f8000 (fec7f000)
[ 0.000000] nr_irqs_gsi: 88
[ 0.000000] PM: Registered nosave memory: 000000000009b000 - 000000000009c000
[ 0.000000] PM: Registered nosave memory: 000000000009c000 - 00000000000a0000
[ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000e0000
[ 0.000000] PM: Registered nosave memory: 00000000000e0000 - 0000000000100000
[ 0.000000] PM: Registered nosave memory: 00000000ab664000 - 00000000ab821000
[ 0.000000] PM: Registered nosave memory: 00000000bea7d000 - 00000000beae9000
[ 0.000000] PM: Registered nosave memory: 00000000beaf2000 - 00000000beb03000
[ 0.000000] PM: Registered nosave memory: 00000000bed2e000 - 00000000bede7000
[ 0.000000] PM: Registered nosave memory: 00000000bede7000 - 00000000bee2f000
[ 0.000000] PM: Registered nosave memory: 00000000bee2f000 - 00000000bee30000
[ 0.000000] PM: Registered nosave memory: 00000000bee30000 - 00000000bee9b000
[ 0.000000] PM: Registered nosave memory: 00000000bee9b000 - 00000000bee9d000
[ 0.000000] PM: Registered nosave memory: 00000000bee9d000 - 00000000bee9e000
[ 0.000000] PM: Registered nosave memory: 00000000bee9e000 - 00000000beeb9000
[ 0.000000] PM: Registered nosave memory: 00000000beeb9000 - 00000000befc1000
[ 0.000000] PM: Registered nosave memory: 00000000bf000000 - 00000000d0000000
[ 0.000000] PM: Registered nosave memory: 00000000d0000000 - 00000000fec00000
[ 0.000000] PM: Registered nosave memory: 00000000fec00000 - 00000000fec01000
[ 0.000000] PM: Registered nosave memory: 00000000fec01000 - 00000000fed19000
[ 0.000000] PM: Registered nosave memory: 00000000fed19000 - 00000000fed1a000
[ 0.000000] PM: Registered nosave memory: 00000000fed1a000 - 00000000fed1c000
[ 0.000000] PM: Registered nosave memory: 00000000fed1c000 - 00000000fed20000
[ 0.000000] PM: Registered nosave memory: 00000000fed20000 - 00000000fee00000
[ 0.000000] PM: Registered nosave memory: 00000000fee00000 - 00000000fee01000
[ 0.000000] PM: Registered nosave memory: 00000000fee01000 - 00000000ffa20000
[ 0.000000] PM: Registered nosave memory: 00000000ffa20000 - 0000000100000000
[ 0.000000] Allocating PCI resources starting at d0000000 (gap: d0000000:2ec00000)
[ 0.000000] Booting paravirtualized kernel on bare hardware
[ 0.000000] setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:64 nr_node_ids:2
[ 0.000000] PERCPU: Embedded 476 pages/cpu @ffff88042be00000 s1916992 r8192 d24512 u2097152
[ 0.000000] pcpu-alloc: s1916992 r8192 d24512 u2097152 alloc=1*2097152
[ 0.000000] pcpu-alloc: [0] 00 [0] 01 [0] 02 [0] 03 [0] 04 [0] 05 [0] 06 [0] 07
[ 0.000000] pcpu-alloc: [0] 16 [0] 17 [0] 18 [0] 19 [0] 20 [0] 21 [0] 22 [0] 23
[ 0.000000] pcpu-alloc: [0] 32 [0] 34 [0] 36 [0] 38 [0] 40 [0] 42 [0] 44 [0] 46
[ 0.000000] pcpu-alloc: [0] 48 [0] 50 [0] 52 [0] 54 [0] 56 [0] 58 [0] 60 [0] 62
[ 0.000000] pcpu-alloc: [1] 08 [1] 09 [1] 10 [1] 11 [1] 12 [1] 13 [1] 14 [1] 15
[ 0.000000] pcpu-alloc: [1] 24 [1] 25 [1] 26 [1] 27 [1] 28 [1] 29 [1] 30 [1] 31
[ 0.000000] pcpu-alloc: [1] 33 [1] 35 [1] 37 [1] 39 [1] 41 [1] 43 [1] 45 [1] 47
[ 0.000000] pcpu-alloc: [1] 49 [1] 51 [1] 53 [1] 55 [1] 57 [1] 59 [1] 61 [1] 63
[ 0.000000] Built 2 zonelists in Zone order, mobility grouping on. Total pages: 8247993
[ 0.000000] Policy zone: Normal
[ 0.000000] Kernel command line: nousb hpet=disable run=/home/wfg/ioless-balance_dirty_pages/test-each-fs.sh log_buf_len=8M debug sched_debug apic=debug dynamic_printk drm.debug=6 sysrq_always_enabled panic=10 unknown_nmi_panic=1 nmi_watchdog=panic,lapic load_ramdisk=2 prompt_ramdisk=0 console=ttyS0,115200 console=tty0 netconsole=@:/eth0,6666@192.168.1.1/00:30:48:fe:19:95 ip=192.168.1.61:192.168.1.11:192.168.1.1:255.255.255.0:snb:eth0:none nfsroot=192.168.1.11:/nfsroot/wfg,tcp,v3,nocto,nolock,rsize=524288,wsize=524288 rw BOOT_IMAGE=x86_64/vmlinuz-3.1.0-ioless-full-next-20111025+
[ 0.000000] sysrq: sysrq always enabled.
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] xsave/xrstor: enabled xstate_bv 0x7, cntxt size 0x340
[ 0.000000] Memory: 32718244k/34603008k available (9793k kernel code, 1070344k absent, 814420k reserved, 5791k data, 2768k init)
[ 0.000000] SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=64, Nodes=2
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU debugfs-based tracing is enabled.
[ 0.000000] NR_IRQS:4352 nr_irqs:2008 16
[ 0.000000] Extended CMOS year: 2000
[ 0.000000] Console: colour VGA+ 80x25
[ 0.000000] console [tty0] enabled
[ 0.000000] console [ttyS0] enabled
[ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.000000] ... MAX_LOCK_DEPTH: 48
[ 0.000000] ... MAX_LOCKDEP_KEYS: 8191
[ 0.000000] ... CLASSHASH_SIZE: 4096
[ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384
[ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768
[ 0.000000] ... CHAINHASH_SIZE: 16384
[ 0.000000] memory used by lock dependency info: 6335 kB
[ 0.000000] per task-struct memory footprint: 2688 bytes
[ 0.000000] allocated 268435456 bytes of page_cgroup
[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
[ 0.001000] Fast TSC calibration using PIT
[ 0.002000] Detected 2299.479 MHz processor.
[ 0.000030] Calibrating delay loop (skipped), value calculated using timer frequency.. 4598.95 BogoMIPS (lpj=2299479)
[ 0.012819] pid_max: default: 65536 minimum: 512
[ 0.028810] Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes)
[ 0.048866] Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes)
[ 0.070117] Mount-cache hash table entries: 256
[ 0.076447] Initializing cgroup subsys debug
[ 0.081678] Initializing cgroup subsys cpuacct
[ 0.087131] Initializing cgroup subsys memory
[ 0.092545] Initializing cgroup subsys devices
[ 0.097967] Initializing cgroup subsys freezer
[ 0.103563] Initializing cgroup subsys blkio
[ 0.108968] CPU: Physical Processor ID: 0
[ 0.113908] CPU: Processor Core ID: 0
[ 0.118458] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
[ 0.118459] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
[ 0.133955] mce: CPU supports 20 MCE banks
[ 0.139017] CPU0: Thermal monitoring enabled (TM1)
[ 0.144849] using mwait in idle threads.
[ 0.151142] ACPI: Core revision 20110623
[ 0.258874] ftrace: allocating 38070 entries in 150 pages
[ 0.280790] Getting VERSION: 1060015
[ 0.285244] Getting VERSION: 1060015
[ 0.289692] Getting ID: 0
[ 0.293071] Getting ID: 0
[ 0.296453] Switched APIC routing to physical flat.
[ 0.302363] enabled ExtINT on CPU#0
[ 0.307228] ENABLING IO-APIC IRQs
[ 0.311385] init IO_APIC IRQs
[ 0.315155] apic 0 pin 0 not connected
[ 0.319905] IOAPIC[0]: Set routing entry (0-1 -> 0x31 -> IRQ 1 Mode:0 Active:0 Dest:0)
[ 0.329594] IOAPIC[0]: Set routing entry (0-2 -> 0x30 -> IRQ 0 Mode:0 Active:0 Dest:0)
[ 0.339284] IOAPIC[0]: Set routing entry (0-3 -> 0x33 -> IRQ 3 Mode:0 Active:0 Dest:0)
[ 0.348967] IOAPIC[0]: Set routing entry (0-4 -> 0x34 -> IRQ 4 Mode:0 Active:0 Dest:0)
[ 0.358651] IOAPIC[0]: Set routing entry (0-5 -> 0x35 -> IRQ 5 Mode:0 Active:0 Dest:0)
[ 0.368331] IOAPIC[0]: Set routing entry (0-6 -> 0x36 -> IRQ 6 Mode:0 Active:0 Dest:0)
[ 0.378014] IOAPIC[0]: Set routing entry (0-7 -> 0x37 -> IRQ 7 Mode:0 Active:0 Dest:0)
[ 0.387695] IOAPIC[0]: Set routing entry (0-8 -> 0x38 -> IRQ 8 Mode:0 Active:0 Dest:0)
[ 0.397375] IOAPIC[0]: Set routing entry (0-9 -> 0x39 -> IRQ 9 Mode:1 Active:0 Dest:0)
[ 0.407054] IOAPIC[0]: Set routing entry (0-10 -> 0x3a -> IRQ 10 Mode:0 Active:0 Dest:0)
[ 0.416930] IOAPIC[0]: Set routing entry (0-11 -> 0x3b -> IRQ 11 Mode:0 Active:0 Dest:0)
[ 0.426806] IOAPIC[0]: Set routing entry (0-12 -> 0x3c -> IRQ 12 Mode:0 Active:0 Dest:0)
[ 0.436680] IOAPIC[0]: Set routing entry (0-13 -> 0x3d -> IRQ 13 Mode:0 Active:0 Dest:0)
[ 0.446557] IOAPIC[0]: Set routing entry (0-14 -> 0x3e -> IRQ 14 Mode:0 Active:0 Dest:0)
[ 0.456432] IOAPIC[0]: Set routing entry (0-15 -> 0x3f -> IRQ 15 Mode:0 Active:0 Dest:0)
[ 0.466306] apic 0 pin 16 not connected
[ 0.471139] apic 0 pin 17 not connected
[ 0.475972] apic 0 pin 18 not connected
[ 0.480803] apic 0 pin 19 not connected
[ 0.485635] apic 0 pin 20 not connected
[ 0.490468] apic 0 pin 21 not connected
[ 0.495301] apic 0 pin 22 not connected
[ 0.500134] apic 0 pin 23 not connected
[ 0.504974] apic 1 pin 0 not connected
[ 0.509709] apic 1 pin 1 not connected
[ 0.514445] apic 1 pin 2 not connected
[ 0.519179] apic 1 pin 3 not connected
[ 0.523913] apic 1 pin 4 not connected
[ 0.528648] apic 1 pin 5 not connected
[ 0.533382] apic 1 pin 6 not connected
[ 0.538117] apic 1 pin 7 not connected
[ 0.542851] apic 1 pin 8 not connected
[ 0.547587] apic 1 pin 9 not connected
[ 0.552322] apic 1 pin 10 not connected
[ 0.557152] apic 1 pin 11 not connected
[ 0.561983] apic 1 pin 12 not connected
[ 0.566817] apic 1 pin 13 not connected
[ 0.571649] apic 1 pin 14 not connected
[ 0.576480] apic 1 pin 15 not connected
[ 0.581313] apic 1 pin 16 not connected
[ 0.586144] apic 1 pin 17 not connected
[ 0.590976] apic 1 pin 18 not connected
[ 0.595807] apic 1 pin 19 not connected
[ 0.600638] apic 1 pin 20 not connected
[ 0.605471] apic 1 pin 21 not connected
[ 0.610304] apic 1 pin 22 not connected
[ 0.615136] apic 1 pin 23 not connected
[ 0.619968] apic 2 pin 0 not connected
[ 0.624703] apic 2 pin 1 not connected
[ 0.629436] apic 2 pin 2 not connected
[ 0.634170] apic 2 pin 3 not connected
[ 0.638905] apic 2 pin 4 not connected
[ 0.643638] apic 2 pin 5 not connected
[ 0.648373] apic 2 pin 6 not connected
[ 0.653109] apic 2 pin 7 not connected
[ 0.657844] apic 2 pin 8 not connected
[ 0.662580] apic 2 pin 9 not connected
[ 0.667315] apic 2 pin 10 not connected
[ 0.672146] apic 2 pin 11 not connected
[ 0.676978] apic 2 pin 12 not connected
[ 0.681811] apic 2 pin 13 not connected
[ 0.686641] apic 2 pin 14 not connected
[ 0.691471] apic 2 pin 15 not connected
[ 0.696302] apic 2 pin 16 not connected
[ 0.701133] apic 2 pin 17 not connected
[ 0.705966] apic 2 pin 18 not connected
[ 0.710798] apic 2 pin 19 not connected
[ 0.715630] apic 2 pin 20 not connected
[ 0.720461] apic 2 pin 21 not connected
[ 0.725291] apic 2 pin 22 not connected
[ 0.730122] apic 2 pin 23 not connected
[ 0.735091] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[ 0.752250] CPU0: Genuine Intel(R) CPU @ 2.30GHz stepping 02
[ 0.759284] Using local APIC timer interrupts.
[ 0.759285] calibrating APIC timer ...
[ 0.871108] ... lapic delta = 624906
[ 0.875547] ... PM-Timer delta = 357901
[ 0.880277] ... PM-Timer result ok
[ 0.884521] ..... delta 624906
[ 0.888377] ..... mult: 26843588
[ 0.892426] ..... calibration result: 99984
[ 0.897545] ..... CPU clock speed is 2299.0653 MHz.
[ 0.903442] ..... host bus clock speed is 99.0984 MHz.
[ 0.909650] Performance Events: PEBS fmt1+, SandyBridge events, Intel PMU driver.
[ 0.919102] ... version: 3
[ 0.924030] ... bit width: 48
[ 0.929052] ... generic registers: 4
[ 0.933981] ... value mask: 0000ffffffffffff
[ 0.940367] ... max period: 000000007fffffff
[ 0.946753] ... fixed-purpose events: 3
[ 0.951679] ... event mask: 000000070000000f
[ 0.958671] lockdep: fixing up alternatives.
[ 0.963974] Booting Node 0, Processors #1
[ 0.968716] smpboot cpu 1: start_ip = 96000
[ 0.987235] masked ExtINT on CPU#1
[ 1.011150] ------------[ cut here ]------------
[ 1.011337] lockdep: fixing up alternatives.
[ 1.011373] #2
[ 1.011374] smpboot cpu 2: start_ip = 96000
[ 1.022482] masked ExtINT on CPU#2
[ 1.033751] WARNING: at /c/wfg/linux-next/kernel/rcutree.c:444 rcu_idle_exit_common+0xd2/0x117()
[ 1.042597] ------------[ cut here ]------------
[ 1.042602] WARNING: at /c/wfg/linux-next/kernel/rcutree.c:359 rcu_idle_enter_common+0xb3/0x130()
[ 1.042604] Hardware name: SandyBridge Platform
[ 1.042605] Modules linked in:
[ 1.042608] Pid: 0, comm: kworker/0:1 Not tainted 3.1.0-ioless-full-next-20111025+ #881
[ 1.042610] Call Trace:
[ 1.042616] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 1.042619] [<ffffffff81074566>] warn_slowpath_null+0x1a/0x1c
[ 1.042621] [<ffffffff810d5bf5>] rcu_idle_enter_common+0xb3/0x130
[ 1.042624] [<ffffffff810d5e24>] rcu_idle_enter+0x40/0x69
[ 1.042629] [<ffffffff810351ac>] cpu_idle+0x82/0xb8
[ 1.042634] [<ffffffff81978bd5>] start_secondary+0x1de/0x1e2
[ 1.042664] ---[ end trace 4eaa2a86a8e2da22 ]---
[ 1.042677] Dumping ftrace buffer:
[ 1.042686] (ftrace buffer empty)
[ 1.042690] ------------[ cut here ]------------
[ 1.042693] WARNING: at /c/wfg/linux-next/kernel/rcutree.c:444 rcu_idle_exit_common+0xd2/0x117()
[ 1.042695] Hardware name: SandyBridge Platform
[ 1.042696] Modules linked in:
[ 1.042698] Pid: 0, comm: kworker/0:1 Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 1.042700] Call Trace:
[ 1.042701] <IRQ> [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 1.042706] [<ffffffff81074566>] warn_slowpath_null+0x1a/0x1c
[ 1.042708] [<ffffffff810d5afd>] rcu_idle_exit_common+0xd2/0x117
[ 1.042710] [<ffffffff810d5fff>] rcu_irq_enter+0x75/0xa2
[ 1.042714] [<ffffffff8107ac7f>] irq_enter+0x1b/0x74
[ 1.042719] [<ffffffff81099334>] ? down_trylock+0x14/0x37
[ 1.042723] [<ffffffff8106f29e>] scheduler_ipi+0x5e/0xd5
[ 1.042726] [<ffffffff8104ce6b>] smp_reschedule_interrupt+0x2a/0x2c
[ 1.042730] [<ffffffff8198bb73>] reschedule_interrupt+0x73/0x80
[ 1.042731] <EOI> [<ffffffff81099334>] ? down_trylock+0x14/0x37
[ 1.042737] [<ffffffff8103ce2b>] ? mwait_idle+0xef/0x175
[ 1.042739] [<ffffffff8103ce22>] ? mwait_idle+0xe6/0x175
[ 1.042742] [<ffffffff810351bb>] cpu_idle+0x91/0xb8
[ 1.042744] [<ffffffff81978bd5>] start_secondary+0x1de/0x1e2
[ 1.042746] ---[ end trace 4eaa2a86a8e2da23 ]---
[ 1.042776] lockdep: fixing up alternatives.
[ 1.042815] #3
[ 1.042817] smpboot cpu 3: start_ip = 96000
[ 1.053923] masked ExtINT on CPU#3
[ 1.074206] lockdep: fixing up alternatives.
[ 1.074248] #4
[ 1.074249] smpboot cpu 4: start_ip = 96000
[ 1.085356] masked ExtINT on CPU#4
[ 1.105637] lockdep: fixing up alternatives.
[ 1.105674] #5
[ 1.105675] smpboot cpu 5: start_ip = 96000
[ 1.116781] masked ExtINT on CPU#5
[ 1.137066] lockdep: fixing up alternatives.
[ 1.137105] #6
[ 1.137107] smpboot cpu 6: start_ip = 96000
[ 1.148212] masked ExtINT on CPU#6
[ 1.168492] lockdep: fixing up alternatives.
[ 1.168533] #7
[ 1.168534] smpboot cpu 7: start_ip = 96000
[ 1.179639] masked ExtINT on CPU#7
[ 1.199933] lockdep: fixing up alternatives.
[ 1.199971] Ok.
[ 1.199972] Booting Node 1, Processors #8
[ 1.199974] smpboot cpu 8: start_ip = 96000
[ 1.211404] masked ExtINT on CPU#8
[ 1.291642] lockdep: fixing up alternatives.
[ 1.291674] #9
[ 1.291675] smpboot cpu 9: start_ip = 96000
[ 1.303144] masked ExtINT on CPU#9
[ 1.323547] lockdep: fixing up alternatives.
[ 1.323576] #10
[ 1.323577] smpboot cpu 10: start_ip = 96000
[ 1.335051] masked ExtINT on CPU#10
[ 1.355430] lockdep: fixing up alternatives.
[ 1.355459] #11
[ 1.355461] smpboot cpu 11: start_ip = 96000
[ 1.366941] masked ExtINT on CPU#11
[ 1.387305] lockdep: fixing up alternatives.
[ 1.387336] #12
[ 1.387337] smpboot cpu 12: start_ip = 96000
[ 1.398819] masked ExtINT on CPU#12
[ 1.419199] lockdep: fixing up alternatives.
[ 1.419228] #13
[ 1.419229] smpboot cpu 13: start_ip = 96000
[ 1.430696] masked ExtINT on CPU#13
[ 1.451080] lockdep: fixing up alternatives.
[ 1.451120] #14
[ 1.451121] smpboot cpu 14: start_ip = 96000
[ 1.462573] masked ExtINT on CPU#14
[ 1.482966] lockdep: fixing up alternatives.
[ 1.483002] #15
[ 1.483003] smpboot cpu 15: start_ip = 96000
[ 1.494444] masked ExtINT on CPU#15
[ 1.514740] lockdep: fixing up alternatives.
[ 1.514768] Ok.
[ 1.514769] Booting Node 0, Processors #16
[ 1.514770] smpboot cpu 16: start_ip = 96000
[ 1.526324] masked ExtINT on CPU#16
[ 1.538292] Hardware name: SandyBridge Platform
[ 1.543802] Modules linked in:lockdep: fixing up alternatives.
[ 1.546651] #17
[ 1.546652] smpboot cpu 17: start_ip = 96000
[ 1.557759] masked ExtINT on CPU#17
[ 1.562905]
[ 1.565016] Pid: 0, comm: kworker/0:0 Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 1.575758] Call Trace:
[ 1.578062] lockdep: fixing up alternatives.
[ 1.578101] #18
[ 1.578103] smpboot cpu 18: start_ip = 96000
[ 1.589208] masked ExtINT on CPU#18
[ 1.596199] <IRQ> [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 1.604132] [<ffffffff81074566>] warn_slowpath_null+0x1a/0x1c
[ 1.609481] lockdep: fixing up alternatives.
[ 1.609517] #19
[ 1.609519] smpboot cpu 19: start_ip = 96000
[ 1.620622] masked ExtINT on CPU#19
[ 1.628375] [<ffffffff810d5afd>] rcu_idle_exit_common+0xd2/0x117
[ 1.635635] [<ffffffff810d5fff>] rcu_irq_enter+0x75/0xa2
[ 1.640907] lockdep: fixing up alternatives.
[ 1.640944] #20
[ 1.640945] smpboot cpu 20: start_ip = 96000
[ 1.652050] masked ExtINT on CPU#20
[ 1.659394] [<ffffffff8107ac7f>] irq_enter+0x1b/0x74
[ 1.665491] [<ffffffff8106f29e>] scheduler_ipi+0x5e/0xd5
[ 1.671975] [<ffffffff8104ce6b>] smp_reschedule_interrupt+0x2a/0x2c
[ 1.672342] lockdep: fixing up alternatives.
[ 1.672383] #21
[ 1.672384] smpboot cpu 21: start_ip = 96000
[ 1.683502] masked ExtINT on CPU#21
[ 1.696805] [<ffffffff8198bb73>] reschedule_interrupt+0x73/0x80
[ 1.703783] lockdep: fixing up alternatives.
[ 1.703820] #22
[ 1.703821] smpboot cpu 22: start_ip = 96000
[ 1.714925] masked ExtINT on CPU#22
[ 1.721230] <EOI> [<ffffffff8198661f>] ? notifier_call_chain+0x63/0x63
[ 1.729261] [<ffffffff8103ce2b>] ? mwait_idle+0xef/0x175
[ 1.735216] lockdep: fixing up alternatives.
[ 1.735254] #23
[ 1.735255] smpboot cpu 23: start_ip = 96000
[ 1.746359] masked ExtINT on CPU#23
[ 1.753019] [<ffffffff8103ce22>] ? mwait_idle+0xe6/0x175
[ 1.759503] [<ffffffff810351bb>] cpu_idle+0x91/0xb8
[ 1.765500] [<ffffffff81978bd5>] start_secondary+0x1de/0x1e2
[ 1.766662] lockdep: fixing up alternatives.
[ 1.766702] Ok.
[ 1.766704] Booting Node 1, Processors #24
[ 1.766706] smpboot cpu 24: start_ip = 96000
[ 1.778148] masked ExtINT on CPU#24
[ 1.794945] ---[ end trace 4eaa2a86a8e2da24 ]---
[ 1.798454] lockdep: fixing up alternatives.
[ 1.798483] #25
[ 1.798484] smpboot cpu 25: start_ip = 96000
[ 1.809958] masked ExtINT on CPU#25
[ 1.830333] lockdep: fixing up alternatives.
[ 1.835589] #26
[ 1.837523] smpboot cpu 26: start_ip = 96000
[ 1.854862] masked ExtINT on CPU#26
[ 1.879078] lockdep: fixing up alternatives.
[ 1.884329] #27
[ 1.886264] smpboot cpu 27: start_ip = 96000
[ 1.903616] masked ExtINT on CPU#27
[ 1.927812] lockdep: fixing up alternatives.
[ 1.933062] #28
[ 1.934997] smpboot cpu 28: start_ip = 96000
[ 1.952341] masked ExtINT on CPU#28
[ 1.976550] lockdep: fixing up alternatives.
[ 1.981802] #29
[ 1.983735] smpboot cpu 29: start_ip = 96000
[ 2.001073] masked ExtINT on CPU#29
[ 2.025285] lockdep: fixing up alternatives.
[ 2.030537] #30
[ 2.032473] smpboot cpu 30: start_ip = 96000
[ 2.049789] masked ExtINT on CPU#30
[ 2.074029] lockdep: fixing up alternatives.
[ 2.079270] #31
[ 2.081204] smpboot cpu 31: start_ip = 96000
[ 2.098517] masked ExtINT on CPU#31
[ 2.122621] Brought up 32 CPUs
[ 2.126486] Total of 32 processors activated (147173.18 BogoMIPS).
[ 2.174403] CPU0 attaching sched-domain:
[ 2.179248] domain 0: span 0,16 level SIBLING
[ 2.184752] groups: 0 (cpu_power = 589) 16 (cpu_power = 589)
[ 2.192151] domain 1: span 0-7,16-23 level MC
[ 2.197746] groups: 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178)
[ 2.221680] domain 2: span 0-31 level NODE
[ 2.227086] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 2.236812] CPU1 attaching sched-domain:
[ 2.241658] domain 0: span 1,17 level SIBLING
[ 2.247161] groups: 1 (cpu_power = 589) 17 (cpu_power = 589)
[ 2.254556] domain 1: span 0-7,16-23 level MC
[ 2.260154] groups: 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178)
[ 2.284091] domain 2: span 0-31 level NODE
[ 2.289489] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 2.299194] CPU2 attaching sched-domain:
[ 2.304030] domain 0: span 2,18 level SIBLING
[ 2.309531] groups: 2 (cpu_power = 589) 18 (cpu_power = 589)
[ 2.316909] domain 1: span 0-7,16-23 level MC
[ 2.322514] groups: 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178)
[ 2.346454] domain 2: span 0-31 level NODE
[ 2.351858] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 2.361579] CPU3 attaching sched-domain:
[ 2.366416] domain 0: span 3,19 level SIBLING
[ 2.371908] groups: 3 (cpu_power = 589) 19 (cpu_power = 589)
[ 2.379309] domain 1: span 0-7,16-23 level MC
[ 2.384912] groups: 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178)
[ 2.408861] domain 2: span 0-31 level NODE
[ 2.414269] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 2.423994] CPU4 attaching sched-domain:
[ 2.428828] domain 0: span 4,20 level SIBLING
[ 2.434324] groups: 4 (cpu_power = 589) 20 (cpu_power = 589)
[ 2.450942] domain 1: span 0-7,16-23 level MC
[ 2.456544] groups: 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178)
[ 2.480470] domain 2: span 0-31 level NODE
[ 2.485867] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 2.495587] CPU5 attaching sched-domain:
[ 2.500422] domain 0: span 5,21 level SIBLING
[ 2.505927] groups: 5 (cpu_power = 589) 21 (cpu_power = 589)
[ 2.513329] domain 1: span 0-7,16-23 level MC
[ 2.518926] groups: 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178)
[ 2.542878] domain 2: span 0-31 level NODE
[ 2.548277] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 2.557994] CPU6 attaching sched-domain:
[ 2.562829] domain 0: span 6,22 level SIBLING
[ 2.568334] groups: 6 (cpu_power = 589) 22 (cpu_power = 589)
[ 2.575730] domain 1: span 0-7,16-23 level MC
[ 2.581329] groups: 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178)
[ 2.605259] domain 2: span 0-31 level NODE
[ 2.610665] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 2.620386] CPU7 attaching sched-domain:
[ 2.625221] domain 0: span 7,23 level SIBLING
[ 2.630728] groups: 7 (cpu_power = 589) 23 (cpu_power = 589)
[ 2.638129] domain 1: span 0-7,16-23 level MC
[ 2.643730] groups: 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178)
[ 2.667680] domain 2: span 0-31 level NODE
[ 2.673088] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 2.682809] CPU8 attaching sched-domain:
[ 2.687646] domain 0: span 8,24 level SIBLING
[ 2.693140] groups: 8 (cpu_power = 589) 24 (cpu_power = 589)
[ 2.700526] domain 1: span 8-15,24-31 level MC
[ 2.706229] groups: 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178)
[ 2.730753] domain 2: span 0-31 level NODE
[ 2.736160] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 2.745882] CPU9 attaching sched-domain:
[ 2.750715] domain 0: span 9,25 level SIBLING
[ 2.756220] groups: 9 (cpu_power = 589) 25 (cpu_power = 589)
[ 2.763616] domain 1: span 8-15,24-31 level MC
[ 2.769305] groups: 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178)
[ 2.793844] domain 2: span 0-31 level NODE
[ 2.799243] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 2.808956] CPU10 attaching sched-domain:
[ 2.813884] domain 0: span 10,26 level SIBLING
[ 2.819488] groups: 10 (cpu_power = 589) 26 (cpu_power = 589)
[ 2.826985] domain 1: span 8-15,24-31 level MC
[ 2.832682] groups: 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178)
[ 2.857206] domain 2: span 0-31 level NODE
[ 2.862612] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 2.872338] CPU11 attaching sched-domain:
[ 2.877269] domain 0: span 11,27 level SIBLING
[ 2.882869] groups: 11 (cpu_power = 589) 27 (cpu_power = 589)
[ 2.890361] domain 1: span 8-15,24-31 level MC
[ 2.896062] groups: 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178)
[ 2.920598] domain 2: span 0-31 level NODE
[ 2.926003] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 2.935730] CPU12 attaching sched-domain:
[ 2.940660] domain 0: span 12,28 level SIBLING
[ 2.946254] groups: 12 (cpu_power = 589) 28 (cpu_power = 589)
[ 2.953736] domain 1: span 8-15,24-31 level MC
[ 2.959431] groups: 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178)
[ 2.983957] domain 2: span 0-31 level NODE
[ 2.989361] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 2.999086] CPU13 attaching sched-domain:
[ 3.004016] domain 0: span 13,29 level SIBLING
[ 3.009615] groups: 13 (cpu_power = 589) 29 (cpu_power = 589)
[ 3.017107] domain 1: span 8-15,24-31 level MC
[ 3.022804] groups: 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178)
[ 3.047337] domain 2: span 0-31 level NODE
[ 3.052739] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 3.062469] CPU14 attaching sched-domain:
[ 3.067399] domain 0: span 14,30 level SIBLING
[ 3.072998] groups: 14 (cpu_power = 589) 30 (cpu_power = 589)
[ 3.080484] domain 1: span 8-15,24-31 level MC
[ 3.086183] groups: 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178)
[ 3.110715] domain 2: span 0-31 level NODE
[ 3.116116] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 3.125835] CPU15 attaching sched-domain:
[ 3.130765] domain 0: span 15,31 level SIBLING
[ 3.136363] groups: 15 (cpu_power = 589) 31 (cpu_power = 589)
[ 3.143861] domain 1: span 8-15,24-31 level MC
[ 3.149559] groups: 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178)
[ 3.174095] domain 2: span 0-31 level NODE
[ 3.179498] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 3.189224] CPU16 attaching sched-domain:
[ 3.194155] domain 0: span 0,16 level SIBLING
[ 3.199648] groups: 16 (cpu_power = 589) 0 (cpu_power = 589)
[ 3.207036] domain 1: span 0-7,16-23 level MC
[ 3.212625] groups: 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178)
[ 3.236564] domain 2: span 0-31 level NODE
[ 3.241969] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 3.251693] CPU17 attaching sched-domain:
[ 3.256623] domain 0: span 1,17 level SIBLING
[ 3.262132] groups: 17 (cpu_power = 589) 1 (cpu_power = 589)
[ 3.269527] domain 1: span 0-7,16-23 level MC
[ 3.275128] groups: 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178)
[ 3.299059] domain 2: span 0-31 level NODE
[ 3.304467] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 3.314187] CPU18 attaching sched-domain:
[ 3.319121] domain 0: span 2,18 level SIBLING
[ 3.324624] groups: 18 (cpu_power = 589) 2 (cpu_power = 589)
[ 3.332011] domain 1: span 0-7,16-23 level MC
[ 3.337613] groups: 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178)
[ 3.361560] domain 2: span 0-31 level NODE
[ 3.366969] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 3.376682] CPU19 attaching sched-domain:
[ 3.381608] domain 0: span 3,19 level SIBLING
[ 3.387108] groups: 19 (cpu_power = 589) 3 (cpu_power = 589)
[ 3.394505] domain 1: span 0-7,16-23 level MC
[ 3.400105] groups: 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178)
[ 3.424042] domain 2: span 0-31 level NODE
[ 3.429439] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 3.439168] CPU20 attaching sched-domain:
[ 3.444097] domain 0: span 4,20 level SIBLING
[ 3.449598] groups: 20 (cpu_power = 589) 4 (cpu_power = 589)
[ 3.456990] domain 1: span 0-7,16-23 level MC
[ 3.462584] groups: 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178)
[ 3.486522] domain 2: span 0-31 level NODE
[ 3.491920] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 3.501639] CPU21 attaching sched-domain:
[ 3.506569] domain 0: span 5,21 level SIBLING
[ 3.512061] groups: 21 (cpu_power = 589) 5 (cpu_power = 589)
[ 3.519453] domain 1: span 0-7,16-23 level MC
[ 3.525053] groups: 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178)
[ 3.549009] domain 2: span 0-31 level NODE
[ 3.554408] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 3.564125] CPU22 attaching sched-domain:
[ 3.569059] domain 0: span 6,22 level SIBLING
[ 3.574562] groups: 22 (cpu_power = 589) 6 (cpu_power = 589)
[ 3.591179] domain 1: span 0-7,16-23 level MC
[ 3.596779] groups: 6,22 (cpu_power = 1178) 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178)
[ 3.620710] domain 2: span 0-31 level NODE
[ 3.626115] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 3.635824] CPU23 attaching sched-domain:
[ 3.640756] domain 0: span 7,23 level SIBLING
[ 3.646258] groups: 23 (cpu_power = 589) 7 (cpu_power = 589)
[ 3.653654] domain 1: span 0-7,16-23 level MC
[ 3.659248] groups: 7,23 (cpu_power = 1178) 0,16 (cpu_power = 1178) 1,17 (cpu_power = 1178) 2,18 (cpu_power = 1178) 3,19 (cpu_power = 1178) 4,20 (cpu_power = 1178) 5,21 (cpu_power = 1178) 6,22 (cpu_power = 1178)
[ 3.683197] domain 2: span 0-31 level NODE
[ 3.688599] groups: 0-7,16-23 (cpu_power = 9424) 8-15,24-31 (cpu_power = 9424)
[ 3.698328] CPU24 attaching sched-domain:
[ 3.703263] domain 0: span 8,24 level SIBLING
[ 3.708765] groups: 24 (cpu_power = 589) 8 (cpu_power = 589)
[ 3.716161] domain 1: span 8-15,24-31 level MC
[ 3.721853] groups: 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178)
[ 3.746373] domain 2: span 0-31 level NODE
[ 3.751773] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 3.761486] CPU25 attaching sched-domain:
[ 3.766416] domain 0: span 9,25 level SIBLING
[ 3.771914] groups: 25 (cpu_power = 589) 9 (cpu_power = 589)
[ 3.779296] domain 1: span 8-15,24-31 level MC
[ 3.784994] groups: 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178)
[ 3.809530] domain 2: span 0-31 level NODE
[ 3.814937] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 3.824654] CPU26 attaching sched-domain:
[ 3.829586] domain 0: span 10,26 level SIBLING
[ 3.835190] groups: 26 (cpu_power = 589) 10 (cpu_power = 589)
[ 3.842686] domain 1: span 8-15,24-31 level MC
[ 3.848374] groups: 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178)
[ 3.872901] domain 2: span 0-31 level NODE
[ 3.878309] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 3.888030] CPU27 attaching sched-domain:
[ 3.892960] domain 0: span 11,27 level SIBLING
[ 3.898565] groups: 27 (cpu_power = 589) 11 (cpu_power = 589)
[ 3.906056] domain 1: span 8-15,24-31 level MC
[ 3.911744] groups: 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178)
[ 3.936290] domain 2: span 0-31 level NODE
[ 3.941696] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 3.951418] CPU28 attaching sched-domain:
[ 3.956352] domain 0: span 12,28 level SIBLING
[ 3.961942] groups: 28 (cpu_power = 589) 12 (cpu_power = 589)
[ 3.969442] domain 1: span 8-15,24-31 level MC
[ 3.975143] groups: 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178)
[ 3.999678] domain 2: span 0-31 level NODE
[ 4.005086] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 4.014804] CPU29 attaching sched-domain:
[ 4.019732] domain 0: span 13,29 level SIBLING
[ 4.025316] groups: 29 (cpu_power = 589) 13 (cpu_power = 589)
[ 4.032812] domain 1: span 8-15,24-31 level MC
[ 4.038511] groups: 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178)
[ 4.063041] domain 2: span 0-31 level NODE
[ 4.068446] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 4.078179] CPU30 attaching sched-domain:
[ 4.083110] domain 0: span 14,30 level SIBLING
[ 4.088709] groups: 30 (cpu_power = 589) 14 (cpu_power = 589)
[ 4.096213] domain 1: span 8-15,24-31 level MC
[ 4.101908] groups: 14,30 (cpu_power = 1178) 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178)
[ 4.126438] domain 2: span 0-31 level NODE
[ 4.131841] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 4.141572] CPU31 attaching sched-domain:
[ 4.146503] domain 0: span 15,31 level SIBLING
[ 4.152104] groups: 31 (cpu_power = 589) 15 (cpu_power = 589)
[ 4.159608] domain 1: span 8-15,24-31 level MC
[ 4.165296] groups: 15,31 (cpu_power = 1178) 8,24 (cpu_power = 1178) 9,25 (cpu_power = 1178) 10,26 (cpu_power = 1178) 11,27 (cpu_power = 1178) 12,28 (cpu_power = 1178) 13,29 (cpu_power = 1178) 14,30 (cpu_power = 1178)
[ 4.189824] domain 2: span 0-31 level NODE
[ 4.195229] groups: 8-15,24-31 (cpu_power = 9424) 0-7,16-23 (cpu_power = 9424)
[ 4.207054] devtmpfs: initialized
[ 4.216221] PM: Registering ACPI NVS region at ab664000 (1822720 bytes)
[ 4.224137] PM: Registering ACPI NVS region at bede7000 (294912 bytes)
[ 4.231899] PM: Registering ACPI NVS region at bee30000 (438272 bytes)
[ 4.239667] PM: Registering ACPI NVS region at bee9d000 (4096 bytes)
[ 4.247223] PM: Registering ACPI NVS region at beeb9000 (1081344 bytes)
[ 4.256027] xor: automatically using best checksumming function: generic_sse
[ 4.268475] generic_sse: 10184.000 MB/sec
[ 4.273689] xor: using function: generic_sse (10184.000 MB/sec)
[ 4.281110] kworker/u:0 used greatest stack depth: 5608 bytes left
[ 4.281178] RTC time: 18:56:49, date: 10/31/11
[ 4.281375] NET: Registered protocol family 16
[ 4.284250] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
[ 4.284257] ACPI: bus type pci registered
[ 4.288038] dca service started, version 1.12.1
[ 4.288325] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xc0000000-0xcfffffff] (base 0xc0000000)
[ 4.288329] PCI: MMCONFIG at [mem 0xc0000000-0xcfffffff] reserved in E820
[ 4.338437] kworker/u:0 used greatest stack depth: 5192 bytes left
[ 4.404017] PCI: Using configuration type 1 for base access
[ 4.488155] bio: create slab <bio-0> at 0
[ 4.510363] raid6: int64x1 1257 MB/s
[ 4.531313] raid6: int64x2 1316 MB/s
[ 4.552306] raid6: int64x4 1160 MB/s
[ 4.573279] raid6: int64x8 902 MB/s
[ 4.594267] raid6: sse2x1 3171 MB/s
[ 4.615265] raid6: sse2x2 3910 MB/s
[ 4.636247] raid6: sse2x4 4433 MB/s
[ 4.640902] raid6: using algorithm sse2x4 (4433 MB/s)
[ 4.647318] ACPI: Added _OSI(Module Device)
[ 4.652465] ACPI: Added _OSI(Processor Device)
[ 4.657901] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 4.663615] ACPI: Added _OSI(Processor Aggregator Device)
[ 4.759319] ACPI: EC: Look up EC in DSDT
[ 4.855990] ACPI: Executed 1 blocks of module-level executable AML code
[ 5.370489] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
[ 5.450998] ACPI: Interpreter enabled
[ 5.455566] ACPI: (supports S0 S1 S5)
[ 5.460482] ACPI: Using IOAPIC for interrupt routing
[ 5.598234] ACPI: No dock devices found.
[ 5.603092] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 5.616516] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-7e])
[ 5.625846] pci_root PNP0A08:00: host bridge window [io 0x0000-0x0cf7]
[ 5.633715] pci_root PNP0A08:00: host bridge window [io 0x0000-0xbfff]
[ 5.641581] pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
[ 5.650603] pci_root PNP0A08:00: host bridge window [mem 0x000c0000-0x000c3fff]
[ 5.659627] pci_root PNP0A08:00: host bridge window [mem 0x000c4000-0x000c7fff]
[ 5.668651] pci_root PNP0A08:00: host bridge window [mem 0x000c8000-0x000cbfff]
[ 5.677674] pci_root PNP0A08:00: host bridge window [mem 0x000cc000-0x000cffff]
[ 5.686686] pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000d3fff]
[ 5.695705] pci_root PNP0A08:00: host bridge window [mem 0x000d4000-0x000d7fff]
[ 5.704724] pci_root PNP0A08:00: host bridge window [mem 0x000d8000-0x000dbfff]
[ 5.713746] pci_root PNP0A08:00: host bridge window [mem 0x000dc000-0x000dffff]
[ 5.722769] pci_root PNP0A08:00: host bridge window [mem 0x000e0000-0x000e3fff]
[ 5.731783] pci_root PNP0A08:00: host bridge window [mem 0x000e4000-0x000e7fff]
[ 5.740804] pci_root PNP0A08:00: host bridge window [mem 0x000e8000-0x000ebfff]
[ 5.749826] pci_root PNP0A08:00: host bridge window [mem 0x000ec000-0x000effff]
[ 5.758849] pci_root PNP0A08:00: host bridge window [mem 0x000f0000-0x000fffff]
[ 5.767873] pci_root PNP0A08:00: host bridge window [mem 0xd0000000-0xebffffff]
[ 5.776896] pci_root PNP0A08:00: host bridge window [mem 0x3f8000000000-0x3f807fffffff]
[ 5.786700] pci_root PNP0A08:00: host bridge window expanded to [io 0x0000-0xbfff]; [io 0x0000-0xbfff] ignored
[ 5.798993] pci 0000:00:00.0: [8086:3c00] type 0 class 0x000600
[ 5.806223] pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
[ 5.813516] pci 0000:00:00.0: PME# disabled
[ 5.828114] pci 0000:00:01.0: [8086:3c02] type 1 class 0x000604
[ 5.835337] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
[ 5.842620] pci 0000:00:01.0: PME# disabled
[ 5.847816] pci 0000:00:01.1: [8086:3c03] type 1 class 0x000604
[ 5.855038] pci 0000:00:01.1: PME# supported from D0 D3hot D3cold
[ 5.862324] pci 0000:00:01.1: PME# disabled
[ 5.867538] pci 0000:00:02.0: [8086:3c04] type 1 class 0x000604
[ 5.874759] pci 0000:00:02.0: PME# supported from D0 D3hot D3cold
[ 5.882047] pci 0000:00:02.0: PME# disabled
[ 5.887243] pci 0000:00:02.2: [8086:3c06] type 1 class 0x000604
[ 5.894459] pci 0000:00:02.2: PME# supported from D0 D3hot D3cold
[ 5.901739] pci 0000:00:02.2: PME# disabled
[ 5.906945] pci 0000:00:03.0: [8086:3c08] type 1 class 0x000604
[ 5.914165] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
[ 5.921448] pci 0000:00:03.0: PME# disabled
[ 5.926646] pci 0000:00:03.2: [8086:3c0a] type 1 class 0x000604
[ 5.933860] pci 0000:00:03.2: PME# supported from D0 D3hot D3cold
[ 5.941146] pci 0000:00:03.2: PME# disabled
[ 5.946350] pci 0000:00:04.0: [8086:3c20] type 0 class 0x000880
[ 5.953469] pci 0000:00:04.0: reg 10: [mem 0xebfb0000-0xebfb3fff 64bit]
[ 5.961509] pci 0000:00:04.1: [8086:3c21] type 0 class 0x000880
[ 5.968625] pci 0000:00:04.1: reg 10: [mem 0xebfa0000-0xebfa3fff 64bit]
[ 5.976662] pci 0000:00:04.2: [8086:3c22] type 0 class 0x000880
[ 5.983778] pci 0000:00:04.2: reg 10: [mem 0xebf90000-0xebf93fff 64bit]
[ 5.991816] pci 0000:00:04.3: [8086:3c23] type 0 class 0x000880
[ 5.998934] pci 0000:00:04.3: reg 10: [mem 0xebf80000-0xebf83fff 64bit]
[ 6.006979] pci 0000:00:04.4: [8086:3c24] type 0 class 0x000880
[ 6.014095] pci 0000:00:04.4: reg 10: [mem 0xebf70000-0xebf73fff 64bit]
[ 6.022134] pci 0000:00:04.5: [8086:3c25] type 0 class 0x000880
[ 6.029247] pci 0000:00:04.5: reg 10: [mem 0xebf60000-0xebf63fff 64bit]
[ 6.037285] pci 0000:00:04.6: [8086:3c26] type 0 class 0x000880
[ 6.044397] pci 0000:00:04.6: reg 10: [mem 0xebf50000-0xebf53fff 64bit]
[ 6.052434] pci 0000:00:04.7: [8086:3c27] type 0 class 0x000880
[ 6.059548] pci 0000:00:04.7: reg 10: [mem 0xebf40000-0xebf43fff 64bit]
[ 6.067596] pci 0000:00:05.0: [8086:3c28] type 0 class 0x000880
[ 6.074865] pci 0000:00:05.2: [8086:3c2a] type 0 class 0x000880
[ 6.082129] pci 0000:00:05.4: [8086:3c2c] type 0 class 0x000800
[ 6.089244] pci 0000:00:05.4: reg 10: [mem 0xd3140000-0xd3140fff]
[ 6.096690] pci 0000:00:06.0: [8086:3c60] type 0 class 0x000880
[ 6.103976] pci 0000:00:07.0: [8086:3c68] type 0 class 0x000600
[ 6.111252] pci 0000:00:16.0: [8086:1d3a] type 0 class 0x000780
[ 6.118384] pci 0000:00:16.0: reg 10: [mem 0xebf30000-0xebf3000f 64bit]
[ 6.126378] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
[ 6.133663] pci 0000:00:16.0: PME# disabled
[ 6.138885] pci 0000:00:1a.0: [8086:1d2d] type 0 class 0x000c03
[ 6.146013] pci 0000:00:1a.0: reg 10: [mem 0xd3130000-0xd31303ff]
[ 6.153453] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
[ 6.160740] pci 0000:00:1a.0: PME# disabled
[ 6.165937] pci 0000:00:1b.0: [8086:1d20] type 0 class 0x000403
[ 6.173055] pci 0000:00:1b.0: reg 10: [mem 0xebf20000-0xebf23fff 64bit]
[ 6.181049] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
[ 6.188333] pci 0000:00:1b.0: PME# disabled
[ 6.193515] pci 0000:00:1c.0: [8086:1d10] type 1 class 0x000604
[ 6.200742] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[ 6.208027] pci 0000:00:1c.0: PME# disabled
[ 6.213226] pci 0000:00:1c.4: [8086:1d18] type 1 class 0x000604
[ 6.220456] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
[ 6.227741] pci 0000:00:1c.4: PME# disabled
[ 6.232933] pci 0000:00:1c.6: [8086:1d1c] type 1 class 0x000604
[ 6.240161] pci 0000:00:1c.6: PME# supported from D0 D3hot D3cold
[ 6.247444] pci 0000:00:1c.6: PME# disabled
[ 6.252636] pci 0000:00:1c.7: [8086:1d1e] type 1 class 0x000604
[ 6.259872] pci 0000:00:1c.7: PME# supported from D0 D3hot D3cold
[ 6.267157] pci 0000:00:1c.7: PME# disabled
[ 6.272352] pci 0000:00:1d.0: [8086:1d26] type 0 class 0x000c03
[ 6.279480] pci 0000:00:1d.0: reg 10: [mem 0xd3120000-0xd31203ff]
[ 6.286924] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[ 6.294208] pci 0000:00:1d.0: PME# disabled
[ 6.299391] pci 0000:00:1e.0: [8086:244e] type 1 class 0x000604
[ 6.306611] pci 0000:00:1f.0: [8086:1d40] type 0 class 0x000601
[ 6.313940] pci 0000:00:1f.2: [8086:1d02] type 0 class 0x000106
[ 6.321069] pci 0000:00:1f.2: reg 10: [io 0x4070-0x4077]
[ 6.327574] pci 0000:00:1f.2: reg 14: [io 0x4060-0x4063]
[ 6.334092] pci 0000:00:1f.2: reg 18: [io 0x4050-0x4057]
[ 6.340608] pci 0000:00:1f.2: reg 1c: [io 0x4040-0x4043]
[ 6.347126] pci 0000:00:1f.2: reg 20: [io 0x4020-0x403f]
[ 6.353647] pci 0000:00:1f.2: reg 24: [mem 0xd3110000-0xd31107ff]
[ 6.361011] pci 0000:00:1f.2: PME# supported from D3hot
[ 6.367323] pci 0000:00:1f.2: PME# disabled
[ 6.372510] pci 0000:00:1f.3: [8086:1d22] type 0 class 0x000c05
[ 6.379629] pci 0000:00:1f.3: reg 10: [mem 0xebf10000-0xebf100ff 64bit]
[ 6.387539] pci 0000:00:1f.3: reg 20: [io 0x4000-0x401f]
[ 6.394111] pci 0000:00:1f.4: [8086:1d23] type 0 class 0x001101
[ 6.401222] pci 0000:00:1f.4: reg 10: [mem 0xd3100000-0xd3100fff]
[ 6.408778] pci 0000:01:00.0: [8086:1d74] type 1 class 0x000604
[ 6.415884] pci 0000:01:00.0: reg 10: [mem 0xd3000000-0xd3003fff]
[ 6.423252] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
[ 6.430535] pci 0000:01:00.0: PME# disabled
[ 6.435697] pci 0000:00:01.0: PCI bridge to [bus 01-03]
[ 6.442015] pci 0000:00:01.0: bridge window [mem 0xd3000000-0xd30fffff]
[ 6.450195] pci 0000:02:08.0: [8086:1d3f] type 1 class 0x000604
[ 6.457398] pci 0000:02:08.0: PME# supported from D0 D3hot D3cold
[ 6.464673] pci 0000:02:08.0: PME# disabled
[ 6.469899] pci 0000:01:00.0: PCI bridge to [bus 02-03]
[ 6.476312] pci 0000:02:08.0: PCI bridge to [bus 03-03]
[ 6.482766] pci 0000:00:01.1: PCI bridge to [bus 04-04]
[ 6.489192] pci 0000:00:02.0: PCI bridge to [bus 05-05]
[ 6.495623] pci 0000:00:02.2: PCI bridge to [bus 06-06]
[ 6.502052] pci 0000:00:03.0: PCI bridge to [bus 07-07]
[ 6.508478] pci 0000:00:03.2: PCI bridge to [bus 08-08]
[ 6.514940] pci 0000:09:00.0: [8086:150e] type 0 class 0x000200
[ 6.522057] pci 0000:09:00.0: reg 10: [mem 0xd2e80000-0xd2efffff]
[ 6.529378] pci 0000:09:00.0: reg 18: [io 0x3060-0x307f]
[ 6.535903] pci 0000:09:00.0: reg 1c: [mem 0xd2f30000-0xd2f33fff]
[ 6.543317] pci 0000:09:00.0: PME# supported from D0 D3hot D3cold
[ 6.550605] pci 0000:09:00.0: PME# disabled
[ 6.555832] pci 0000:09:00.1: [8086:150e] type 0 class 0x000200
[ 6.562946] pci 0000:09:00.1: reg 10: [mem 0xd2e00000-0xd2e7ffff]
[ 6.570267] pci 0000:09:00.1: reg 18: [io 0x3040-0x305f]
[ 6.576790] pci 0000:09:00.1: reg 1c: [mem 0xd2f20000-0xd2f23fff]
[ 6.584210] pci 0000:09:00.1: PME# supported from D0 D3hot D3cold
[ 6.591493] pci 0000:09:00.1: PME# disabled
[ 6.596712] pci 0000:09:00.2: [8086:150e] type 0 class 0x000200
[ 6.603827] pci 0000:09:00.2: reg 10: [mem 0xd2d80000-0xd2dfffff]
[ 6.611153] pci 0000:09:00.2: reg 18: [io 0x3020-0x303f]
[ 6.617678] pci 0000:09:00.2: reg 1c: [mem 0xd2f10000-0xd2f13fff]
[ 6.625099] pci 0000:09:00.2: PME# supported from D0 D3hot D3cold
[ 6.632384] pci 0000:09:00.2: PME# disabled
[ 6.637605] pci 0000:09:00.3: [8086:150e] type 0 class 0x000200
[ 6.644721] pci 0000:09:00.3: reg 10: [mem 0xd2d00000-0xd2d7ffff]
[ 6.652043] pci 0000:09:00.3: reg 18: [io 0x3000-0x301f]
[ 6.658568] pci 0000:09:00.3: reg 1c: [mem 0xd2f00000-0xd2f03fff]
[ 6.665993] pci 0000:09:00.3: PME# supported from D0 D3hot D3cold
[ 6.673278] pci 0000:09:00.3: PME# disabled
[ 6.678469] pci 0000:00:1c.0: PCI bridge to [bus 09-09]
[ 6.684773] pci 0000:00:1c.0: bridge window [io 0x3000-0x3fff]
[ 6.692058] pci 0000:00:1c.0: bridge window [mem 0xd2d00000-0xd2ffffff]
[ 6.700227] pci 0000:00:1c.4: PCI bridge to [bus 0a-0a]
[ 6.706532] pci 0000:00:1c.4: bridge window [io 0x2000-0x2fff]
[ 6.713815] pci 0000:00:1c.4: bridge window [mem 0xd2300000-0xd2cfffff]
[ 6.721883] pci 0000:00:1c.4: bridge window [mem 0xeb500000-0xebefffff 64bit pref]
[ 6.731509] pci 0000:00:1c.6: PCI bridge to [bus 0b-0b]
[ 6.737823] pci 0000:00:1c.6: bridge window [io 0x1000-0x1fff]
[ 6.745111] pci 0000:00:1c.6: bridge window [mem 0xd1900000-0xd22fffff]
[ 6.753179] pci 0000:00:1c.6: bridge window [mem 0xeab00000-0xeb4fffff 64bit pref]
[ 6.762825] pci 0000:0c:00.0: [102b:0522] type 0 class 0x000300
[ 6.769947] pci 0000:0c:00.0: reg 10: [mem 0xd0000000-0xd0ffffff]
[ 6.777251] pci 0000:0c:00.0: reg 14: [mem 0xd1810000-0xd1813fff]
[ 6.784557] pci 0000:0c:00.0: reg 18: [mem 0xd1000000-0xd17fffff]
[ 6.791936] pci 0000:0c:00.0: reg 30: [mem 0xd1800000-0xd180ffff pref]
[ 6.799806] pci 0000:00:1c.7: PCI bridge to [bus 0c-0c]
[ 6.806124] pci 0000:00:1c.7: bridge window [mem 0xd0000000-0xd18fffff]
[ 6.814332] pci 0000:00:1e.0: PCI bridge to [bus 0d-0d] (subtractive decode)
[ 6.822700] pci 0000:00:1e.0: bridge window [io 0x0000-0xbfff] (subtractive decode)
[ 6.832404] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
[ 6.842880] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000c3fff] (subtractive decode)
[ 6.853362] pci 0000:00:1e.0: bridge window [mem 0x000c4000-0x000c7fff] (subtractive decode)
[ 6.863842] pci 0000:00:1e.0: bridge window [mem 0x000c8000-0x000cbfff] (subtractive decode)
[ 6.874324] pci 0000:00:1e.0: bridge window [mem 0x000cc000-0x000cffff] (subtractive decode)
[ 6.884800] pci 0000:00:1e.0: bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode)
[ 6.895282] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode)
[ 6.905762] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode)
[ 6.916243] pci 0000:00:1e.0: bridge window [mem 0x000dc000-0x000dffff] (subtractive decode)
[ 6.926724] pci 0000:00:1e.0: bridge window [mem 0x000e0000-0x000e3fff] (subtractive decode)
[ 6.937202] pci 0000:00:1e.0: bridge window [mem 0x000e4000-0x000e7fff] (subtractive decode)
[ 6.947679] pci 0000:00:1e.0: bridge window [mem 0x000e8000-0x000ebfff] (subtractive decode)
[ 6.958159] pci 0000:00:1e.0: bridge window [mem 0x000ec000-0x000effff] (subtractive decode)
[ 6.968638] pci 0000:00:1e.0: bridge window [mem 0x000f0000-0x000fffff] (subtractive decode)
[ 6.979117] pci 0000:00:1e.0: bridge window [mem 0xd0000000-0xebffffff] (subtractive decode)
[ 6.989601] pci 0000:00:1e.0: bridge window [mem 0x3f8000000000-0x3f807fffffff] (subtractive decode)
[ 7.000965] pci_bus 0000:00: on NUMA node 0 (pxm 0)
[ 7.016290] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[ 7.024368] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP01._PRT]
[ 7.032203] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP05._PRT]
[ 7.039965] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP07._PRT]
[ 7.047709] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP08._PRT]
[ 7.055468] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BR10._PRT]
[ 7.063198] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BR10.EPCU._PRT]
[ 7.071436] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BR10.EPCU.EVSP._PRT]
[ 7.080785] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BR11._PRT]
[ 7.088740] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BR12._PRT]
[ 7.096708] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BR14._PRT]
[ 7.104698] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BR18._PRT]
[ 7.112681] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BR16._PRT]
[ 7.121581] pci0000:00: Unable to request _OSC control (_OSC support mask: 0x19)
[ 7.206580] ACPI: PCI Root Bridge [PCI1] (domain 0000 [bus 80-fe])
[ 7.215844] pci_root PNP0A08:01: host bridge window [io 0xc000-0xffff]
[ 7.223715] pci_root PNP0A08:01: host bridge window [mem 0xec000000-0xfbffffff]
[ 7.232740] pci_root PNP0A08:01: host bridge window [mem 0x3f8080000000-0x3f80ffffffff]
[ 7.242589] pci 0000:80:02.0: [8086:3c04] type 1 class 0x000604
[ 7.249821] pci 0000:80:02.0: PME# supported from D0 D3hot D3cold
[ 7.257109] pci 0000:80:02.0: PME# disabled
[ 7.262324] pci 0000:80:04.0: [8086:3c20] type 0 class 0x000880
[ 7.269441] pci 0000:80:04.0: reg 10: [mem 0xfbf70000-0xfbf73fff 64bit]
[ 7.277492] pci 0000:80:04.1: [8086:3c21] type 0 class 0x000880
[ 7.284607] pci 0000:80:04.1: reg 10: [mem 0xfbf60000-0xfbf63fff 64bit]
[ 7.292653] pci 0000:80:04.2: [8086:3c22] type 0 class 0x000880
[ 7.299771] pci 0000:80:04.2: reg 10: [mem 0xfbf50000-0xfbf53fff 64bit]
[ 7.307820] pci 0000:80:04.3: [8086:3c23] type 0 class 0x000880
[ 7.314942] pci 0000:80:04.3: reg 10: [mem 0xfbf40000-0xfbf43fff 64bit]
[ 7.322986] pci 0000:80:04.4: [8086:3c24] type 0 class 0x000880
[ 7.330107] pci 0000:80:04.4: reg 10: [mem 0xfbf30000-0xfbf33fff 64bit]
[ 7.338157] pci 0000:80:04.5: [8086:3c25] type 0 class 0x000880
[ 7.345266] pci 0000:80:04.5: reg 10: [mem 0xfbf20000-0xfbf23fff 64bit]
[ 7.353326] pci 0000:80:04.6: [8086:3c26] type 0 class 0x000880
[ 7.360436] pci 0000:80:04.6: reg 10: [mem 0xfbf10000-0xfbf13fff 64bit]
[ 7.368482] pci 0000:80:04.7: [8086:3c27] type 0 class 0x000880
[ 7.375601] pci 0000:80:04.7: reg 10: [mem 0xfbf00000-0xfbf03fff 64bit]
[ 7.383644] pci 0000:80:05.0: [8086:3c28] type 0 class 0x000880
[ 7.390921] pci 0000:80:05.2: [8086:3c2a] type 0 class 0x000880
[ 7.398191] pci 0000:80:05.4: [8086:3c2c] type 0 class 0x000800
[ 7.405307] pci 0000:80:05.4: reg 10: [mem 0xec000000-0xec000fff]
[ 7.412749] pci 0000:80:06.0: [8086:3c60] type 0 class 0x000880
[ 7.420037] pci 0000:80:07.0: [8086:3c68] type 0 class 0x000600
[ 7.427419] pci 0000:80:02.0: PCI bridge to [bus 81-81]
[ 7.433766] pci_bus 0000:80: on NUMA node 1 (pxm 1)
[ 7.439694] ACPI: PCI Interrupt Routing Table [\_SB_.PCI1._PRT]
[ 7.447224] ACPI: PCI Interrupt Routing Table [\_SB_.PCI1.BR44._PRT]
[ 7.455582] pci0000:80: Unable to request _OSC control (_OSC support mask: 0x19)
[ 7.476858] ACPI: PCI Root Bridge [UCR0] (domain 0000 [bus 7f])
[ 7.484398] pci 0000:7f:08.0: [8086:3c80] type 0 class 0x000880
[ 7.491628] pci 0000:7f:08.3: [8086:3c83] type 0 class 0x000880
[ 7.498865] pci 0000:7f:08.4: [8086:3c84] type 0 class 0x000880
[ 7.506112] pci 0000:7f:09.0: [8086:3c90] type 0 class 0x000880
[ 7.513331] pci 0000:7f:09.3: [8086:3c93] type 0 class 0x000880
[ 7.520562] pci 0000:7f:09.4: [8086:3c94] type 0 class 0x000880
[ 7.527806] pci 0000:7f:0a.0: [8086:3cc0] type 0 class 0x000880
[ 7.535028] pci 0000:7f:0a.1: [8086:3cc1] type 0 class 0x000880
[ 7.542231] pci 0000:7f:0a.2: [8086:3cc2] type 0 class 0x000880
[ 7.549444] pci 0000:7f:0a.3: [8086:3cd0] type 0 class 0x000880
[ 7.556656] pci 0000:7f:0b.0: [8086:3ce0] type 0 class 0x000880
[ 7.563859] pci 0000:7f:0b.3: [8086:3ce3] type 0 class 0x000880
[ 7.571075] pci 0000:7f:0c.0: [8086:3ce8] type 0 class 0x000880
[ 7.578281] pci 0000:7f:0c.1: [8086:3ce8] type 0 class 0x000880
[ 7.585482] pci 0000:7f:0c.2: [8086:3ce8] type 0 class 0x000880
[ 7.592682] pci 0000:7f:0c.3: [8086:3ce8] type 0 class 0x000880
[ 7.599895] pci 0000:7f:0c.6: [8086:3cf4] type 0 class 0x000880
[ 7.607095] pci 0000:7f:0c.7: [8086:3cf6] type 0 class 0x000880
[ 7.614300] pci 0000:7f:0d.0: [8086:3ce8] type 0 class 0x000880
[ 7.621511] pci 0000:7f:0d.1: [8086:3ce8] type 0 class 0x000880
[ 7.628714] pci 0000:7f:0d.2: [8086:3ce8] type 0 class 0x000880
[ 7.635922] pci 0000:7f:0d.3: [8086:3ce8] type 0 class 0x000880
[ 7.643128] pci 0000:7f:0d.6: [8086:3cf5] type 0 class 0x000880
[ 7.650332] pci 0000:7f:0e.0: [8086:3ca0] type 0 class 0x000880
[ 7.657538] pci 0000:7f:0e.1: [8086:3c46] type 0 class 0x001101
[ 7.664789] pci 0000:7f:0f.0: [8086:3ca8] type 0 class 0x000880
[ 7.672037] pci 0000:7f:0f.1: [8086:3c71] type 0 class 0x000880
[ 7.679274] pci 0000:7f:0f.2: [8086:3caa] type 0 class 0x000880
[ 7.686511] pci 0000:7f:0f.3: [8086:3cab] type 0 class 0x000880
[ 7.693741] pci 0000:7f:0f.4: [8086:3cac] type 0 class 0x000880
[ 7.700973] pci 0000:7f:0f.5: [8086:3cad] type 0 class 0x000880
[ 7.708202] pci 0000:7f:0f.6: [8086:3cae] type 0 class 0x000880
[ 7.715427] pci 0000:7f:10.0: [8086:3cb0] type 0 class 0x000880
[ 7.722665] pci 0000:7f:10.1: [8086:3cb1] type 0 class 0x000880
[ 7.729908] pci 0000:7f:10.2: [8086:3cb2] type 0 class 0x000880
[ 7.737143] pci 0000:7f:10.3: [8086:3cb3] type 0 class 0x000880
[ 7.744380] pci 0000:7f:10.4: [8086:3cb4] type 0 class 0x000880
[ 7.751615] pci 0000:7f:10.5: [8086:3cb5] type 0 class 0x000880
[ 7.758857] pci 0000:7f:10.6: [8086:3cb6] type 0 class 0x000880
[ 7.766095] pci 0000:7f:10.7: [8086:3cb7] type 0 class 0x000880
[ 7.773322] pci 0000:7f:11.0: [8086:3cb8] type 0 class 0x000880
[ 7.780561] pci 0000:7f:13.0: [8086:3ce4] type 0 class 0x000880
[ 7.787770] pci 0000:7f:13.1: [8086:3c43] type 0 class 0x001101
[ 7.794981] pci 0000:7f:13.4: [8086:3ce6] type 0 class 0x001101
[ 7.802182] pci 0000:7f:13.5: [8086:3c44] type 0 class 0x001101
[ 7.809383] pci 0000:7f:13.6: [8086:3c45] type 0 class 0x000880
[ 7.816624] pci0000:7f: Unable to request _OSC control (_OSC support mask: 0x19)
[ 7.835928] ACPI: PCI Root Bridge [UCR1] (domain 0000 [bus ff])
[ 7.843459] pci 0000:ff:08.0: [8086:3c80] type 0 class 0x000880
[ 7.850693] pci 0000:ff:08.3: [8086:3c83] type 0 class 0x000880
[ 7.857941] pci 0000:ff:08.4: [8086:3c84] type 0 class 0x000880
[ 7.865179] pci 0000:ff:09.0: [8086:3c90] type 0 class 0x000880
[ 7.872403] pci 0000:ff:09.3: [8086:3c93] type 0 class 0x000880
[ 7.879649] pci 0000:ff:09.4: [8086:3c94] type 0 class 0x000880
[ 7.886919] pci 0000:ff:0a.0: [8086:3cc0] type 0 class 0x000880
[ 7.894128] pci 0000:ff:0a.1: [8086:3cc1] type 0 class 0x000880
[ 7.901334] pci 0000:ff:0a.2: [8086:3cc2] type 0 class 0x000880
[ 7.908543] pci 0000:ff:0a.3: [8086:3cd0] type 0 class 0x000880
[ 7.915768] pci 0000:ff:0b.0: [8086:3ce0] type 0 class 0x000880
[ 7.922992] pci 0000:ff:0b.3: [8086:3ce3] type 0 class 0x000880
[ 7.930215] pci 0000:ff:0c.0: [8086:3ce8] type 0 class 0x000880
[ 7.937412] pci 0000:ff:0c.1: [8086:3ce8] type 0 class 0x000880
[ 7.944618] pci 0000:ff:0c.2: [8086:3ce8] type 0 class 0x000880
[ 7.951829] pci 0000:ff:0c.3: [8086:3ce8] type 0 class 0x000880
[ 7.959039] pci 0000:ff:0c.6: [8086:3cf4] type 0 class 0x000880
[ 7.966243] pci 0000:ff:0c.7: [8086:3cf6] type 0 class 0x000880
[ 7.973451] pci 0000:ff:0d.0: [8086:3ce8] type 0 class 0x000880
[ 7.980670] pci 0000:ff:0d.1: [8086:3ce8] type 0 class 0x000880
[ 7.987877] pci 0000:ff:0d.2: [8086:3ce8] type 0 class 0x000880
[ 7.995084] pci 0000:ff:0d.3: [8086:3ce8] type 0 class 0x000880
[ 8.002293] pci 0000:ff:0d.6: [8086:3cf5] type 0 class 0x000880
[ 8.009503] pci 0000:ff:0e.0: [8086:3ca0] type 0 class 0x000880
[ 8.016725] pci 0000:ff:0e.1: [8086:3c46] type 0 class 0x001101
[ 8.023971] pci 0000:ff:0f.0: [8086:3ca8] type 0 class 0x000880
[ 8.031208] pci 0000:ff:0f.1: [8086:3c71] type 0 class 0x000880
[ 8.038459] pci 0000:ff:0f.2: [8086:3caa] type 0 class 0x000880
[ 8.045709] pci 0000:ff:0f.3: [8086:3cab] type 0 class 0x000880
[ 8.052952] pci 0000:ff:0f.4: [8086:3cac] type 0 class 0x000880
[ 8.060192] pci 0000:ff:0f.5: [8086:3cad] type 0 class 0x000880
[ 8.067429] pci 0000:ff:0f.6: [8086:3cae] type 0 class 0x000880
[ 8.074669] pci 0000:ff:10.0: [8086:3cb0] type 0 class 0x000880
[ 8.081912] pci 0000:ff:10.1: [8086:3cb1] type 0 class 0x000880
[ 8.089151] pci 0000:ff:10.2: [8086:3cb2] type 0 class 0x000880
[ 8.096389] pci 0000:ff:10.3: [8086:3cb3] type 0 class 0x000880
[ 8.103632] pci 0000:ff:10.4: [8086:3cb4] type 0 class 0x000880
[ 8.110876] pci 0000:ff:10.5: [8086:3cb5] type 0 class 0x000880
[ 8.118112] pci 0000:ff:10.6: [8086:3cb6] type 0 class 0x000880
[ 8.125343] pci 0000:ff:10.7: [8086:3cb7] type 0 class 0x000880
[ 8.132580] pci 0000:ff:11.0: [8086:3cb8] type 0 class 0x000880
[ 8.139815] pci 0000:ff:13.0: [8086:3ce4] type 0 class 0x000880
[ 8.147020] pci 0000:ff:13.1: [8086:3c43] type 0 class 0x001101
[ 8.154241] pci 0000:ff:13.4: [8086:3ce6] type 0 class 0x001101
[ 8.161449] pci 0000:ff:13.5: [8086:3c44] type 0 class 0x001101
[ 8.168661] pci 0000:ff:13.6: [8086:3c45] type 0 class 0x000880
[ 8.175909] pci0000:ff: Unable to request _OSC control (_OSC support mask: 0x19)
[ 8.195602] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15)
[ 8.204994] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15)
[ 8.214377] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15)
[ 8.223774] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15)
[ 8.233154] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 *5 6 10 11 12 14 15)
[ 8.242547] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15)
[ 8.251933] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 *10 11 12 14 15)
[ 8.261300] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 *10 11 12 14 15)
[ 8.271443] vgaarb: device added: PCI:0000:0c:00.0,decodes=io+mem,owns=io+mem,locks=none
[ 8.281679] vgaarb: loaded
[ 8.285168] vgaarb: bridge control possible 0000:0c:00.0
[ 8.292235] SCSI subsystem initialized
[ 8.297438] libata version 3.00 loaded.
[ 8.302618] usbcore: USB support disabled
[ 8.309130] wmi: Mapper loaded
[ 8.313201] Advanced Linux Sound Architecture Driver Version 1.0.24.
[ 8.320776] PCI: Using ACPI for IRQ routing
[ 8.337277] PCI: pci_cache_line_size set to 64 bytes
[ 8.344866] reserve RAM buffer: 000000000009bc00 - 000000000009ffff
[ 8.351865] reserve RAM buffer: 00000000ab664000 - 00000000abffffff
[ 8.359521] reserve RAM buffer: 00000000bea7d000 - 00000000bfffffff
[ 8.367186] reserve RAM buffer: 00000000beaf2000 - 00000000bfffffff
[ 8.374850] reserve RAM buffer: 00000000bed2e000 - 00000000bfffffff
[ 8.382514] reserve RAM buffer: 00000000bf000000 - 00000000bfffffff
[ 8.471360] pnp: PnP ACPI init
[ 8.475950] ACPI: bus type pnp registered
[ 8.481893] pnp 00:00: [bus 00-7e]
[ 8.486164] pnp 00:00: [io 0x0000-0x0cf7 window]
[ 8.501282] pnp 00:00: [io 0x0cf8-0x0cff]
[ 8.506337] pnp 00:00: [io 0x0000-0xbfff window]
[ 8.512063] pnp 00:00: [mem 0x000a0000-0x000bffff window]
[ 8.518567] pnp 00:00: [mem 0x000c0000-0x000c3fff window]
[ 8.525071] pnp 00:00: [mem 0x000c4000-0x000c7fff window]
[ 8.531577] pnp 00:00: [mem 0x000c8000-0x000cbfff window]
[ 8.538088] pnp 00:00: [mem 0x000cc000-0x000cffff window]
[ 8.544593] pnp 00:00: [mem 0x000d0000-0x000d3fff window]
[ 8.551096] pnp 00:00: [mem 0x000d4000-0x000d7fff window]
[ 8.557604] pnp 00:00: [mem 0x000d8000-0x000dbfff window]
[ 8.564098] pnp 00:00: [mem 0x000dc000-0x000dffff window]
[ 8.570605] pnp 00:00: [mem 0x000e0000-0x000e3fff window]
[ 8.577113] pnp 00:00: [mem 0x000e4000-0x000e7fff window]
[ 8.583618] pnp 00:00: [mem 0x000e8000-0x000ebfff window]
[ 8.590118] pnp 00:00: [mem 0x000ec000-0x000effff window]
[ 8.596620] pnp 00:00: [mem 0x000f0000-0x000fffff window]
[ 8.603121] pnp 00:00: [mem 0xd0000000-0xebffffff window]
[ 8.609625] pnp 00:00: [mem 0x3f8000000000-0x3f807fffffff window]
[ 8.616903] pnp 00:00: [mem 0xfed40000-0xfed44fff window]
[ 8.624092] pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
[ 8.633086] pnp 00:01: [io 0x0000-0x001f]
[ 8.638132] pnp 00:01: [io 0x0081-0x0091]
[ 8.643176] pnp 00:01: [io 0x0093-0x009f]
[ 8.648229] pnp 00:01: [io 0x00c0-0x00df]
[ 8.653284] pnp 00:01: [dma 4]
[ 8.657370] pnp 00:01: Plug and Play ACPI device, IDs PNP0200 (active)
[ 8.665190] pnp 00:02: [mem 0xff000000-0xffffffff]
[ 8.671201] pnp 00:02: Plug and Play ACPI device, IDs INT0800 (active)
[ 8.679324] pnp 00:03: [mem 0xfed00000-0xfed003ff]
[ 8.685364] pnp 00:03: Plug and Play ACPI device, IDs PNP0103 (active)
[ 8.693190] pnp 00:04: [io 0x00f0]
[ 8.697569] IOAPIC[0]: Set routing entry (0-13 -> 0x3d -> IRQ 13 Mode:0 Active:0 Dest:0)
[ 8.707483] pnp 00:04: [irq 13]
[ 8.711689] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active)
[ 8.719577] pnp 00:05: [io 0x002e-0x002f]
[ 8.724624] pnp 00:05: [io 0x004e-0x004f]
[ 8.729674] pnp 00:05: [io 0x0061]
[ 8.734037] pnp 00:05: [io 0x0063]
[ 8.738403] pnp 00:05: [io 0x0065]
[ 8.742765] pnp 00:05: [io 0x0067]
[ 8.747129] pnp 00:05: [io 0x0070]
[ 8.751493] pnp 00:05: [io 0x0080]
[ 8.755853] pnp 00:05: [io 0x0092]
[ 8.760220] pnp 00:05: [io 0x00b2-0x00b3]
[ 8.765267] pnp 00:05: [io 0x0680-0x069f]
[ 8.770317] pnp 00:05: [io 0xffff]
[ 8.774681] pnp 00:05: [io 0xffff]
[ 8.779053] pnp 00:05: [io 0xffff]
[ 8.783420] pnp 00:05: [io 0x0400-0x0453]
[ 8.788463] pnp 00:05: [io 0x0458-0x047f]
[ 8.793506] pnp 00:05: [io 0x0500-0x057f]
[ 8.798554] pnp 00:05: [io 0x164e-0x164f]
[ 8.803691] pnp 00:05: disabling [io 0x164e-0x164f] because it overlaps 0000:00:1c.6 BAR 7 [io 0x1000-0x1fff]
[ 8.816442] system 00:05: [io 0x0680-0x069f] has been reserved
[ 8.823531] system 00:05: [io 0xffff] has been reserved
[ 8.829939] system 00:05: [io 0xffff] has been reserved
[ 8.836359] system 00:05: [io 0xffff] has been reserved
[ 8.842768] system 00:05: [io 0x0400-0x0453] has been reserved
[ 8.849854] system 00:05: [io 0x0458-0x047f] has been reserved
[ 8.856942] system 00:05: [io 0x0500-0x057f] has been reserved
[ 8.864034] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 8.872133] pnp 00:06: [io 0x0070-0x0077]
[ 8.877193] IOAPIC[0]: Set routing entry (0-8 -> 0x38 -> IRQ 8 Mode:0 Active:0 Dest:0)
[ 8.886902] pnp 00:06: [irq 8]
[ 8.890993] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 8.898908] pnp 00:07: [io 0x0454-0x0457]
[ 8.904672] system 00:07: [io 0x0454-0x0457] has been reserved
[ 8.911767] system 00:07: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[ 8.922321] pnp 00:08: [io 0x03f8-0x03ff]
[ 8.927376] IOAPIC[0]: Set routing entry (0-4 -> 0x34 -> IRQ 4 Mode:0 Active:0 Dest:0)
[ 8.937093] pnp 00:08: [irq 4]
[ 8.940980] pnp 00:08: [dma 0 disabled]
[ 8.946061] pnp 00:08: Plug and Play ACPI device, IDs PNP0501 (active)
[ 8.954831] pnp 00:09: [io 0x02f8-0x02ff]
[ 8.959896] IOAPIC[0]: Set routing entry (0-3 -> 0x33 -> IRQ 3 Mode:0 Active:0 Dest:0)
[ 8.969613] pnp 00:09: [irq 3]
[ 8.973494] pnp 00:09: [dma 0 disabled]
[ 8.978584] pnp 00:09: Plug and Play ACPI device, IDs PNP0501 (active)
[ 8.988794] pnp 00:0a: [mem 0xfed1c000-0xfed1ffff]
[ 8.994629] pnp 00:0a: [mem 0xc0000000-0xcfffffff]
[ 9.000453] pnp 00:0a: [mem 0xfed20000-0xfed3ffff]
[ 9.006277] pnp 00:0a: [mem 0xebffc000-0xebffdfff]
[ 9.012093] pnp 00:0a: [mem 0xfbffe000-0xfbffffff]
[ 9.017923] pnp 00:0a: [mem 0x00000000-0xffffffffffffffff disabled]
[ 9.025401] pnp 00:0a: [mem 0x00000000-0xffffffffffffffff disabled]
[ 9.032873] pnp 00:0a: [mem 0xfed45000-0xfed8ffff]
[ 9.038690] pnp 00:0a: [mem 0xff000000-0xffffffff]
[ 9.044518] pnp 00:0a: [mem 0xfee00000-0xfeefffff]
[ 9.050340] pnp 00:0a: [mem 0xfec00000-0xfecfffff]
[ 9.056166] pnp 00:0a: [mem 0x00000000-0xffffffffffffffff disabled]
[ 9.064358] system 00:0a: [mem 0xfed1c000-0xfed1ffff] has been reserved
[ 9.072227] system 00:0a: [mem 0xc0000000-0xcfffffff] has been reserved
[ 9.080096] system 00:0a: [mem 0xfed20000-0xfed3ffff] has been reserved
[ 9.087966] system 00:0a: [mem 0xebffc000-0xebffdfff] has been reserved
[ 9.095834] system 00:0a: [mem 0xfbffe000-0xfbffffff] has been reserved
[ 9.103705] system 00:0a: [mem 0xfed45000-0xfed8ffff] has been reserved
[ 9.111572] system 00:0a: [mem 0xff000000-0xffffffff] could not be reserved
[ 9.119827] system 00:0a: [mem 0xfee00000-0xfeefffff] could not be reserved
[ 9.128082] system 00:0a: [mem 0xfec00000-0xfecfffff] could not be reserved
[ 9.136339] system 00:0a: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 9.146148] pnp 00:0b: [bus 80-fe]
[ 9.150421] pnp 00:0b: [io 0xc000-0xffff window]
[ 9.156146] pnp 00:0b: [mem 0xec000000-0xfbffffff window]
[ 9.162650] pnp 00:0b: [mem 0x3f8080000000-0x3f80ffffffff window]
[ 9.170610] pnp 00:0b: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
[ 9.179921] pnp 00:0c: [mem 0x00000000-0x0009cfff]
[ 9.186809] system 00:0c: [mem 0x00000000-0x0009cfff] could not be reserved
[ 9.195071] system 00:0c: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 9.204254] pnp 00:0d: [bus 7f]
[ 9.208876] pnp 00:0d: Plug and Play ACPI device, IDs PNP0a03 (active)
[ 9.216880] pnp 00:0e: [bus ff]
[ 9.221511] pnp 00:0e: Plug and Play ACPI device, IDs PNP0a03 (active)
[ 9.229553] pnp: PnP ACPI: found 15 devices
[ 9.234704] ACPI: ACPI bus type pnp unregistered
[ 9.263328] Switching to clocksource acpi_pm
[ 9.269368] PCI: max bus depth: 3 pci_try_num: 4
[ 9.275330] pci 0000:02:08.0: PCI bridge to [bus 03-03]
[ 9.281665] pci 0000:01:00.0: PCI bridge to [bus 02-03]
[ 9.287999] pci 0000:00:01.0: PCI bridge to [bus 01-03]
[ 9.294319] pci 0000:00:01.0: bridge window [mem 0xd3000000-0xd30fffff]
[ 9.302395] pci 0000:00:01.1: PCI bridge to [bus 04-04]
[ 9.308728] pci 0000:00:02.0: PCI bridge to [bus 05-05]
[ 9.315063] pci 0000:00:02.2: PCI bridge to [bus 06-06]
[ 9.321397] pci 0000:00:03.0: PCI bridge to [bus 07-07]
[ 9.327731] pci 0000:00:03.2: PCI bridge to [bus 08-08]
[ 9.334066] pci 0000:00:1c.0: PCI bridge to [bus 09-09]
[ 9.340382] pci 0000:00:1c.0: bridge window [io 0x3000-0x3fff]
[ 9.347677] pci 0000:00:1c.0: bridge window [mem 0xd2d00000-0xd2ffffff]
[ 9.355756] pci 0000:00:1c.4: PCI bridge to [bus 0a-0a]
[ 9.362072] pci 0000:00:1c.4: bridge window [io 0x2000-0x2fff]
[ 9.369366] pci 0000:00:1c.4: bridge window [mem 0xd2300000-0xd2cfffff]
[ 9.377437] pci 0000:00:1c.4: bridge window [mem 0xeb500000-0xebefffff 64bit pref]
[ 9.386960] pci 0000:00:1c.6: PCI bridge to [bus 0b-0b]
[ 9.393274] pci 0000:00:1c.6: bridge window [io 0x1000-0x1fff]
[ 9.400568] pci 0000:00:1c.6: bridge window [mem 0xd1900000-0xd22fffff]
[ 9.408637] pci 0000:00:1c.6: bridge window [mem 0xeab00000-0xeb4fffff 64bit pref]
[ 9.418161] pci 0000:00:1c.7: PCI bridge to [bus 0c-0c]
[ 9.424479] pci 0000:00:1c.7: bridge window [mem 0xd0000000-0xd18fffff]
[ 9.432557] pci 0000:00:1e.0: PCI bridge to [bus 0d-0d]
[ 9.438898] pci 0000:80:02.0: PCI bridge to [bus 81-81]
[ 9.445326] IOAPIC[1]: Set routing entry (1-23 -> 0x29 -> IRQ 47 Mode:1 Active:1 Dest:0)
[ 9.455246] pci 0000:00:01.0: PCI INT A -> GSI 47 (level, low) -> IRQ 47
[ 9.463249] IOAPIC[1]: Set routing entry (1-2 -> 0x41 -> IRQ 26 Mode:1 Active:1 Dest:0)
[ 9.473060] pci 0000:01:00.0: PCI INT A -> GSI 26 (level, low) -> IRQ 26
[ 9.481036] pci 0000:02:08.0: PCI INT A -> GSI 26 (level, low) -> IRQ 26
[ 9.489013] pci 0000:00:01.1: PCI INT A -> GSI 47 (level, low) -> IRQ 47
[ 9.496993] pci 0000:00:02.0: PCI INT A -> GSI 47 (level, low) -> IRQ 47
[ 9.504968] pci 0000:00:02.2: PCI INT A -> GSI 47 (level, low) -> IRQ 47
[ 9.512945] pci 0000:00:03.0: PCI INT A -> GSI 47 (level, low) -> IRQ 47
[ 9.520922] pci 0000:00:03.2: PCI INT A -> GSI 47 (level, low) -> IRQ 47
[ 9.528921] IOAPIC[0]: Set routing entry (0-16 -> 0x49 -> IRQ 16 Mode:1 Active:1 Dest:0)
[ 9.538834] pci 0000:00:1c.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[ 9.546819] pci 0000:00:1c.4: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[ 9.554817] IOAPIC[0]: Set routing entry (0-18 -> 0x51 -> IRQ 18 Mode:1 Active:1 Dest:0)
[ 9.564724] pci 0000:00:1c.6: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[ 9.572723] IOAPIC[0]: Set routing entry (0-19 -> 0x59 -> IRQ 19 Mode:1 Active:1 Dest:0)
[ 9.582627] pci 0000:00:1c.7: PCI INT D -> GSI 19 (level, low) -> IRQ 19
[ 9.590619] pci 0000:00:1e.0: setting latency timer to 64
[ 9.597221] IOAPIC[2]: Set routing entry (2-23 -> 0x61 -> IRQ 71 Mode:1 Active:1 Dest:0)
[ 9.607137] pci 0000:80:02.0: PCI INT A -> GSI 71 (level, low) -> IRQ 71
[ 9.615121] pci_bus 0000:00: resource 4 [io 0x0000-0xbfff]
[ 9.621827] pci_bus 0000:00: resource 5 [mem 0x000a0000-0x000bffff]
[ 9.629309] pci_bus 0000:00: resource 6 [mem 0x000c0000-0x000c3fff]
[ 9.636791] pci_bus 0000:00: resource 7 [mem 0x000c4000-0x000c7fff]
[ 9.653669] pci_bus 0000:00: resource 8 [mem 0x000c8000-0x000cbfff]
[ 9.661147] pci_bus 0000:00: resource 9 [mem 0x000cc000-0x000cffff]
[ 9.668626] pci_bus 0000:00: resource 10 [mem 0x000d0000-0x000d3fff]
[ 9.676208] pci_bus 0000:00: resource 11 [mem 0x000d4000-0x000d7fff]
[ 9.683786] pci_bus 0000:00: resource 12 [mem 0x000d8000-0x000dbfff]
[ 9.691352] pci_bus 0000:00: resource 13 [mem 0x000dc000-0x000dffff]
[ 9.698931] pci_bus 0000:00: resource 14 [mem 0x000e0000-0x000e3fff]
[ 9.706497] pci_bus 0000:00: resource 15 [mem 0x000e4000-0x000e7fff]
[ 9.714076] pci_bus 0000:00: resource 16 [mem 0x000e8000-0x000ebfff]
[ 9.721653] pci_bus 0000:00: resource 17 [mem 0x000ec000-0x000effff]
[ 9.729229] pci_bus 0000:00: resource 18 [mem 0x000f0000-0x000fffff]
[ 9.736805] pci_bus 0000:00: resource 19 [mem 0xd0000000-0xebffffff]
[ 9.744381] pci_bus 0000:00: resource 20 [mem 0x3f8000000000-0x3f807fffffff]
[ 9.752734] pci_bus 0000:01: resource 1 [mem 0xd3000000-0xd30fffff]
[ 9.760215] pci_bus 0000:09: resource 0 [io 0x3000-0x3fff]
[ 9.766919] pci_bus 0000:09: resource 1 [mem 0xd2d00000-0xd2ffffff]
[ 9.774397] pci_bus 0000:0a: resource 0 [io 0x2000-0x2fff]
[ 9.781102] pci_bus 0000:0a: resource 1 [mem 0xd2300000-0xd2cfffff]
[ 9.788580] pci_bus 0000:0a: resource 2 [mem 0xeb500000-0xebefffff 64bit pref]
[ 9.797518] pci_bus 0000:0b: resource 0 [io 0x1000-0x1fff]
[ 9.804217] pci_bus 0000:0b: resource 1 [mem 0xd1900000-0xd22fffff]
[ 9.811697] pci_bus 0000:0b: resource 2 [mem 0xeab00000-0xeb4fffff 64bit pref]
[ 9.820625] pci_bus 0000:0c: resource 1 [mem 0xd0000000-0xd18fffff]
[ 9.828107] pci_bus 0000:0d: resource 4 [io 0x0000-0xbfff]
[ 9.834811] pci_bus 0000:0d: resource 5 [mem 0x000a0000-0x000bffff]
[ 9.842291] pci_bus 0000:0d: resource 6 [mem 0x000c0000-0x000c3fff]
[ 9.849772] pci_bus 0000:0d: resource 7 [mem 0x000c4000-0x000c7fff]
[ 9.857248] pci_bus 0000:0d: resource 8 [mem 0x000c8000-0x000cbfff]
[ 9.864727] pci_bus 0000:0d: resource 9 [mem 0x000cc000-0x000cffff]
[ 9.872207] pci_bus 0000:0d: resource 10 [mem 0x000d0000-0x000d3fff]
[ 9.879782] pci_bus 0000:0d: resource 11 [mem 0x000d4000-0x000d7fff]
[ 9.887356] pci_bus 0000:0d: resource 12 [mem 0x000d8000-0x000dbfff]
[ 9.894939] pci_bus 0000:0d: resource 13 [mem 0x000dc000-0x000dffff]
[ 9.902514] pci_bus 0000:0d: resource 14 [mem 0x000e0000-0x000e3fff]
[ 9.910088] pci_bus 0000:0d: resource 15 [mem 0x000e4000-0x000e7fff]
[ 9.917667] pci_bus 0000:0d: resource 16 [mem 0x000e8000-0x000ebfff]
[ 9.925241] pci_bus 0000:0d: resource 17 [mem 0x000ec000-0x000effff]
[ 9.932819] pci_bus 0000:0d: resource 18 [mem 0x000f0000-0x000fffff]
[ 9.940395] pci_bus 0000:0d: resource 19 [mem 0xd0000000-0xebffffff]
[ 9.947971] pci_bus 0000:0d: resource 20 [mem 0x3f8000000000-0x3f807fffffff]
[ 9.956325] pci_bus 0000:80: resource 4 [io 0xc000-0xffff]
[ 9.963027] pci_bus 0000:80: resource 5 [mem 0xec000000-0xfbffffff]
[ 9.970509] pci_bus 0000:80: resource 6 [mem 0x3f8080000000-0x3f80ffffffff]
[ 9.979065] NET: Registered protocol family 2
[ 9.987231] IP route cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 10.003175] TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
[ 10.018117] TCP bind hash table entries: 65536 (order: 10, 5242880 bytes)
[ 10.033313] TCP: Hash tables configured (established 524288 bind 65536)
[ 10.041211] TCP reno registered
[ 10.046914] UDP hash table entries: 16384 (order: 9, 3145728 bytes)
[ 10.059843] UDP-Lite hash table entries: 16384 (order: 9, 3145728 bytes)
[ 10.072696] NET: Registered protocol family 1
[ 10.078670] RPC: Registered named UNIX socket transport module.
[ 10.085788] RPC: Registered udp transport module.
[ 10.091520] RPC: Registered tcp transport module.
[ 10.097249] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 10.105246] pci 0000:00:1a.0: EHCI: BIOS handoff
[ 10.121607] pci 0000:00:1d.0: EHCI: BIOS handoff
[ 10.138510] pci 0000:0c:00.0: Boot video device
[ 10.144758] PCI: CLS 64 bytes, default 64
[ 10.149960] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[ 10.157645] Placing 64MB software IO TLB between ffff8800b7060000 - ffff8800bb060000
[ 10.167173] software IO TLB at phys 0xb7060000 - 0xbb060000
[ 10.175529] Simple Boot Flag at 0x4f set to 0x1
[ 10.215053] Machine check injector initialized
[ 10.238139] microcode: CPU0 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.245721] microcode: CPU1 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.253288] microcode: CPU2 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.260858] microcode: CPU3 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.268427] microcode: CPU4 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.275993] microcode: CPU5 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.283576] microcode: CPU6 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.291133] microcode: CPU7 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.298704] microcode: CPU8 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.306300] microcode: CPU9 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.313906] microcode: CPU10 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.321596] microcode: CPU11 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.329288] microcode: CPU12 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.336987] microcode: CPU13 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.344687] microcode: CPU14 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.352384] microcode: CPU15 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.360079] microcode: CPU16 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.367756] microcode: CPU17 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.375408] microcode: CPU18 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.383069] microcode: CPU19 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.390728] microcode: CPU20 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.398387] microcode: CPU21 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.406047] microcode: CPU22 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.413710] microcode: CPU23 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.421373] microcode: CPU24 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.429068] microcode: CPU25 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.436762] microcode: CPU26 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.444465] microcode: CPU27 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.452158] microcode: CPU28 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.459853] microcode: CPU29 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.467548] microcode: CPU30 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.475240] microcode: CPU31 sig=0x206d2, pf=0x1, revision=0x80000206
[ 10.483235] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
[ 10.495050] audit: initializing netlink socket (disabled)
[ 10.501593] type=2000 audit(1320087409.028:1): initialized
[ 10.607787] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 10.647797] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[ 10.658085] fuse init (API version 7.17)
[ 10.664673] JFS: nTxBlock = 8192, nTxLock = 65536
[ 10.680613] SGI XFS with ACLs, security attributes, large block/inode numbers, no debug enabled
[ 10.696805] NILFS version 2 loaded
[ 10.703797] Btrfs loaded
[ 10.707128] msgmni has been set to 32768
[ 10.714980] async_tx: api initialized (async)
[ 10.720833] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[ 10.730146] io scheduler noop registered
[ 10.735007] io scheduler deadline registered
[ 10.740636] io scheduler cfq registered (default)
[ 10.751131] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[ 10.759686] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input0
[ 10.768873] ACPI: Power Button [PWRF]
[ 10.778999] ACPI: acpi_idle registered with cpuidle
[ 10.790752] Monitor-Mwait will be used to enter C-1 state
[ 10.797380] Monitor-Mwait will be used to enter C-2 state
[ 10.803983] Monitor-Mwait will be used to enter C-3 state
[ 11.030353] ioatdma: Intel(R) QuickData Technology Driver 4.00
[ 11.037609] IOAPIC[1]: Set routing entry (1-7 -> 0x69 -> IRQ 31 Mode:1 Active:1 Dest:0)
[ 11.047419] ioatdma 0000:00:04.0: PCI INT A -> GSI 31 (level, low) -> IRQ 31
[ 11.056270] ioatdma 0000:00:04.0: irq 88 for MSI/MSI-X
[ 11.063418] work_for_cpu used greatest stack depth: 5176 bytes left
[ 11.070937] IOAPIC[1]: Set routing entry (1-15 -> 0x79 -> IRQ 39 Mode:1 Active:1 Dest:0)
[ 11.080825] ioatdma 0000:00:04.1: PCI INT B -> GSI 39 (level, low) -> IRQ 39
[ 11.089565] ioatdma 0000:00:04.1: irq 89 for MSI/MSI-X
[ 11.096606] ioatdma 0000:00:04.2: PCI INT C -> GSI 31 (level, low) -> IRQ 31
[ 11.105366] ioatdma 0000:00:04.2: irq 90 for MSI/MSI-X
[ 11.112431] ioatdma 0000:00:04.3: PCI INT D -> GSI 39 (level, low) -> IRQ 39
[ 11.121196] ioatdma 0000:00:04.3: irq 91 for MSI/MSI-X
[ 11.128255] ioatdma 0000:00:04.4: PCI INT A -> GSI 31 (level, low) -> IRQ 31
[ 11.137005] ioatdma 0000:00:04.4: irq 92 for MSI/MSI-X
[ 11.144047] ioatdma 0000:00:04.5: PCI INT B -> GSI 39 (level, low) -> IRQ 39
[ 11.152796] ioatdma 0000:00:04.5: irq 93 for MSI/MSI-X
[ 11.159800] ioatdma 0000:00:04.6: PCI INT C -> GSI 31 (level, low) -> IRQ 31
[ 11.168534] ioatdma 0000:00:04.6: irq 94 for MSI/MSI-X
[ 11.175546] ioatdma 0000:00:04.7: PCI INT D -> GSI 39 (level, low) -> IRQ 39
[ 11.181876] Refined TSC clocksource calibration: 2300.002 MHz.
[ 11.181882] Switching to clocksource tsc
[ 11.196214] ioatdma 0000:00:04.7: irq 95 for MSI/MSI-X
[ 11.203131] work_for_cpu used greatest stack depth: 5144 bytes left
[ 11.203354] IOAPIC[2]: Set routing entry (2-7 -> 0xb9 -> IRQ 55 Mode:1 Active:1 Dest:0)
[ 11.203364] ioatdma 0000:80:04.0: PCI INT A -> GSI 55 (level, low) -> IRQ 55
[ 11.203862] ioatdma 0000:80:04.0: irq 96 for MSI/MSI-X
[ 11.235793] IOAPIC[2]: Set routing entry (2-15 -> 0xc9 -> IRQ 63 Mode:1 Active:1 Dest:0)
[ 11.245708] ioatdma 0000:80:04.1: PCI INT B -> GSI 63 (level, low) -> IRQ 63
[ 11.254438] ioatdma 0000:80:04.1: irq 97 for MSI/MSI-X
[ 11.261512] ioatdma 0000:80:04.2: PCI INT C -> GSI 55 (level, low) -> IRQ 55
[ 11.270254] ioatdma 0000:80:04.2: irq 98 for MSI/MSI-X
[ 11.277317] ioatdma 0000:80:04.3: PCI INT D -> GSI 63 (level, low) -> IRQ 63
[ 11.286066] ioatdma 0000:80:04.3: irq 99 for MSI/MSI-X
[ 11.293109] ioatdma 0000:80:04.4: PCI INT A -> GSI 55 (level, low) -> IRQ 55
[ 11.301845] ioatdma 0000:80:04.4: irq 100 for MSI/MSI-X
[ 11.309021] ioatdma 0000:80:04.5: PCI INT B -> GSI 63 (level, low) -> IRQ 63
[ 11.317775] ioatdma 0000:80:04.5: irq 101 for MSI/MSI-X
[ 11.324874] ioatdma 0000:80:04.6: PCI INT C -> GSI 55 (level, low) -> IRQ 55
[ 11.333622] ioatdma 0000:80:04.6: irq 102 for MSI/MSI-X
[ 11.340677] ioatdma 0000:80:04.7: PCI INT D -> GSI 63 (level, low) -> IRQ 63
[ 11.349407] ioatdma 0000:80:04.7: irq 103 for MSI/MSI-X
[ 11.461244] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 11.489680] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[ 11.527414] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
[ 11.598553] 00:08: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[ 11.636974] 00:09: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
[ 11.655293] Initializing Nozomi driver 2.1d
[ 11.671520] hpet_acpi_add: no address or irqs in _CRS
[ 11.678184] Non-volatile memory driver v1.3
[ 11.686659] Linux agpgart interface v0.103
[ 11.692091] Hangcheck: starting hangcheck timer 0.9.1 (tick is 180 seconds, margin is 60 seconds).
[ 11.702991] Hangcheck: Using getrawmonotonic().
[ 11.708709] [drm] Initialized drm 1.1.0 20060810
[ 11.714361] [drm:i915_init] *ERROR* drm/i915 can't work without intel_agp module!
[ 14.742225] floppy0: no floppy controllers found
[ 14.748362] ------------[ cut here ]------------
[ 14.754012] WARNING: at /c/wfg/linux-next/drivers/block/floppy.c:2929 do_fd_request+0x37/0xaa()
[ 14.764600] Hardware name: SandyBridge Platform
[ 14.770140] VFS: do_fd_request called on non-open device
[ 14.776553] Modules linked in:
[ 14.780528] Pid: 1, comm: swapper Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 14.790931] Call Trace:
[ 14.794141] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 14.801335] [<ffffffff810745ef>] warn_slowpath_fmt+0x46/0x48
[ 14.808239] [<ffffffff813ea19a>] ? blk_throtl_drain+0xf6/0x105
[ 14.815336] [<ffffffff819830be>] ? _raw_spin_unlock_irq+0x30/0x3c
[ 14.822720] [<ffffffff81519bcd>] do_fd_request+0x37/0xaa
[ 14.829235] [<ffffffff813d78a6>] __blk_run_queue+0x1e/0x20
[ 14.835941] [<ffffffff813dcdae>] blk_drain_queue+0x41/0x7a
[ 14.842642] [<ffffffff813dcf0c>] blk_cleanup_queue+0x125/0x184
[ 14.849741] [<ffffffff8213eb69>] floppy_init+0xd9c/0xdc2
[ 14.856253] [<ffffffff8213ddcd>] ? daring+0x65/0x65
[ 14.862285] [<ffffffff810002f7>] do_one_initcall+0x7f/0x140
[ 14.869087] [<ffffffff8210fc16>] kernel_init+0xcb/0x14f
[ 14.875509] [<ffffffff8198bf04>] kernel_thread_helper+0x4/0x10
[ 14.882606] [<ffffffff81983334>] ? retint_restore_args+0x13/0x13
[ 14.889893] [<ffffffff8210fb4b>] ? start_kernel+0x390/0x390
[ 14.896695] [<ffffffff8198bf00>] ? gs_change+0x13/0x13
[ 14.903012] ---[ end trace 4eaa2a86a8e2da25 ]---
[ 14.909113] ------------[ cut here ]------------
[ 14.914744] WARNING: at /c/wfg/linux-next/drivers/block/floppy.c:2929 do_fd_request+0x37/0xaa()
[ 14.925337] Hardware name: SandyBridge Platform
[ 14.930872] VFS: do_fd_request called on non-open device
[ 14.937284] Modules linked in:
[ 14.941260] Pid: 1, comm: swapper Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 14.951658] Call Trace:
[ 14.954868] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 14.962060] [<ffffffff810745ef>] warn_slowpath_fmt+0x46/0x48
[ 14.968959] [<ffffffff813ea19a>] ? blk_throtl_drain+0xf6/0x105
[ 14.976054] [<ffffffff819830be>] ? _raw_spin_unlock_irq+0x30/0x3c
[ 14.983441] [<ffffffff81519bcd>] do_fd_request+0x37/0xaa
[ 14.989950] [<ffffffff813d78a6>] __blk_run_queue+0x1e/0x20
[ 14.996657] [<ffffffff813dcdae>] blk_drain_queue+0x41/0x7a
[ 15.003364] [<ffffffff813dcf0c>] blk_cleanup_queue+0x125/0x184
[ 15.010456] [<ffffffff8213eb69>] floppy_init+0xd9c/0xdc2
[ 15.016967] [<ffffffff8213ddcd>] ? daring+0x65/0x65
[ 15.022994] [<ffffffff810002f7>] do_one_initcall+0x7f/0x140
[ 15.029793] [<ffffffff8210fc16>] kernel_init+0xcb/0x14f
[ 15.036208] [<ffffffff8198bf04>] kernel_thread_helper+0x4/0x10
[ 15.043302] [<ffffffff81983334>] ? retint_restore_args+0x13/0x13
[ 15.050590] [<ffffffff8210fb4b>] ? start_kernel+0x390/0x390
[ 15.057392] [<ffffffff8198bf00>] ? gs_change+0x13/0x13
[ 15.063710] ---[ end trace 4eaa2a86a8e2da26 ]---
[ 15.069687] ------------[ cut here ]------------
[ 15.075323] WARNING: at /c/wfg/linux-next/drivers/block/floppy.c:2929 do_fd_request+0x37/0xaa()
[ 15.085920] Hardware name: SandyBridge Platform
[ 15.091457] VFS: do_fd_request called on non-open device
[ 15.097868] Modules linked in:
[ 15.101842] Pid: 1, comm: swapper Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 15.112248] Call Trace:
[ 15.115454] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 15.122649] [<ffffffff810745ef>] warn_slowpath_fmt+0x46/0x48
[ 15.129550] [<ffffffff813ea19a>] ? blk_throtl_drain+0xf6/0x105
[ 15.136641] [<ffffffff819830be>] ? _raw_spin_unlock_irq+0x30/0x3c
[ 15.144026] [<ffffffff81519bcd>] do_fd_request+0x37/0xaa
[ 15.150538] [<ffffffff813d78a6>] __blk_run_queue+0x1e/0x20
[ 15.157243] [<ffffffff813dcdae>] blk_drain_queue+0x41/0x7a
[ 15.163950] [<ffffffff813dcf0c>] blk_cleanup_queue+0x125/0x184
[ 15.171046] [<ffffffff8213eb69>] floppy_init+0xd9c/0xdc2
[ 15.177553] [<ffffffff8213ddcd>] ? daring+0x65/0x65
[ 15.183579] [<ffffffff810002f7>] do_one_initcall+0x7f/0x140
[ 15.190380] [<ffffffff8210fc16>] kernel_init+0xcb/0x14f
[ 15.196791] [<ffffffff8198bf04>] kernel_thread_helper+0x4/0x10
[ 15.203884] [<ffffffff81983334>] ? retint_restore_args+0x13/0x13
[ 15.211173] [<ffffffff8210fb4b>] ? start_kernel+0x390/0x390
[ 15.217973] [<ffffffff8198bf00>] ? gs_change+0x13/0x13
[ 15.224287] ---[ end trace 4eaa2a86a8e2da27 ]---
[ 15.230251] ------------[ cut here ]------------
[ 15.235888] WARNING: at /c/wfg/linux-next/drivers/block/floppy.c:2929 do_fd_request+0x37/0xaa()
[ 15.246479] Hardware name: SandyBridge Platform
[ 15.252011] VFS: do_fd_request called on non-open device
[ 15.258423] Modules linked in:
[ 15.262391] Pid: 1, comm: swapper Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 15.272792] Call Trace:
[ 15.276000] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 15.283191] [<ffffffff810745ef>] warn_slowpath_fmt+0x46/0x48
[ 15.290089] [<ffffffff813ea19a>] ? blk_throtl_drain+0xf6/0x105
[ 15.297184] [<ffffffff819830be>] ? _raw_spin_unlock_irq+0x30/0x3c
[ 15.304567] [<ffffffff81519bcd>] do_fd_request+0x37/0xaa
[ 15.311074] [<ffffffff813d78a6>] __blk_run_queue+0x1e/0x20
[ 15.317778] [<ffffffff813dcdae>] blk_drain_queue+0x41/0x7a
[ 15.324486] [<ffffffff813dcf0c>] blk_cleanup_queue+0x125/0x184
[ 15.331577] [<ffffffff8213eb69>] floppy_init+0xd9c/0xdc2
[ 15.338087] [<ffffffff8213ddcd>] ? daring+0x65/0x65
[ 15.344114] [<ffffffff810002f7>] do_one_initcall+0x7f/0x140
[ 15.350913] [<ffffffff8210fc16>] kernel_init+0xcb/0x14f
[ 15.357327] [<ffffffff8198bf04>] kernel_thread_helper+0x4/0x10
[ 15.364422] [<ffffffff81983334>] ? retint_restore_args+0x13/0x13
[ 15.371710] [<ffffffff8210fb4b>] ? start_kernel+0x390/0x390
[ 15.378511] [<ffffffff8198bf00>] ? gs_change+0x13/0x13
[ 15.384827] ---[ end trace 4eaa2a86a8e2da28 ]---
[ 15.390794] ------------[ cut here ]------------
[ 15.396430] WARNING: at /c/wfg/linux-next/drivers/block/floppy.c:2929 do_fd_request+0x37/0xaa()
[ 15.407020] Hardware name: SandyBridge Platform
[ 15.412555] VFS: do_fd_request called on non-open device
[ 15.418964] Modules linked in:
[ 15.422943] Pid: 1, comm: swapper Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 15.433343] Call Trace:
[ 15.436555] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 15.443747] [<ffffffff810745ef>] warn_slowpath_fmt+0x46/0x48
[ 15.450644] [<ffffffff813ea19a>] ? blk_throtl_drain+0xf6/0x105
[ 15.457737] [<ffffffff819830be>] ? _raw_spin_unlock_irq+0x30/0x3c
[ 15.465126] [<ffffffff81519bcd>] do_fd_request+0x37/0xaa
[ 15.471633] [<ffffffff813d78a6>] __blk_run_queue+0x1e/0x20
[ 15.478336] [<ffffffff813dcdae>] blk_drain_queue+0x41/0x7a
[ 15.485043] [<ffffffff813dcf0c>] blk_cleanup_queue+0x125/0x184
[ 15.492138] [<ffffffff8213eb69>] floppy_init+0xd9c/0xdc2
[ 15.498646] [<ffffffff8213ddcd>] ? daring+0x65/0x65
[ 15.504673] [<ffffffff810002f7>] do_one_initcall+0x7f/0x140
[ 15.511475] [<ffffffff8210fc16>] kernel_init+0xcb/0x14f
[ 15.517886] [<ffffffff8198bf04>] kernel_thread_helper+0x4/0x10
[ 15.524979] [<ffffffff81983334>] ? retint_restore_args+0x13/0x13
[ 15.532266] [<ffffffff8210fb4b>] ? start_kernel+0x390/0x390
[ 15.539066] [<ffffffff8198bf00>] ? gs_change+0x13/0x13
[ 15.545377] ---[ end trace 4eaa2a86a8e2da29 ]---
[ 15.551339] ------------[ cut here ]------------
[ 15.556976] WARNING: at /c/wfg/linux-next/drivers/block/floppy.c:2929 do_fd_request+0x37/0xaa()
[ 15.567568] Hardware name: SandyBridge Platform
[ 15.573104] VFS: do_fd_request called on non-open device
[ 15.579508] Modules linked in:
[ 15.583480] Pid: 1, comm: swapper Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 15.593883] Call Trace:
[ 15.597089] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 15.604282] [<ffffffff810745ef>] warn_slowpath_fmt+0x46/0x48
[ 15.611183] [<ffffffff813ea19a>] ? blk_throtl_drain+0xf6/0x105
[ 15.618273] [<ffffffff819830be>] ? _raw_spin_unlock_irq+0x30/0x3c
[ 15.625658] [<ffffffff81519bcd>] do_fd_request+0x37/0xaa
[ 15.632168] [<ffffffff813d78a6>] __blk_run_queue+0x1e/0x20
[ 15.638871] [<ffffffff813dcdae>] blk_drain_queue+0x41/0x7a
[ 15.645575] [<ffffffff813dcf0c>] blk_cleanup_queue+0x125/0x184
[ 15.652669] [<ffffffff8213eb69>] floppy_init+0xd9c/0xdc2
[ 15.659178] [<ffffffff8213ddcd>] ? daring+0x65/0x65
[ 15.665203] [<ffffffff810002f7>] do_one_initcall+0x7f/0x140
[ 15.672006] [<ffffffff8210fc16>] kernel_init+0xcb/0x14f
[ 15.678419] [<ffffffff8198bf04>] kernel_thread_helper+0x4/0x10
[ 15.685509] [<ffffffff81983334>] ? retint_restore_args+0x13/0x13
[ 15.692799] [<ffffffff8210fb4b>] ? start_kernel+0x390/0x390
[ 15.699600] [<ffffffff8198bf00>] ? gs_change+0x13/0x13
[ 15.705911] ---[ end trace 4eaa2a86a8e2da2a ]---
[ 15.711878] ------------[ cut here ]------------
[ 15.717514] WARNING: at /c/wfg/linux-next/drivers/block/floppy.c:2929 do_fd_request+0x37/0xaa()
[ 15.728109] Hardware name: SandyBridge Platform
[ 15.733644] VFS: do_fd_request called on non-open device
[ 15.740055] Modules linked in:
[ 15.744035] Pid: 1, comm: swapper Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 15.754433] Call Trace:
[ 15.757640] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 15.764834] [<ffffffff810745ef>] warn_slowpath_fmt+0x46/0x48
[ 15.771730] [<ffffffff813ea19a>] ? blk_throtl_drain+0xf6/0x105
[ 15.778826] [<ffffffff819830be>] ? _raw_spin_unlock_irq+0x30/0x3c
[ 15.786214] [<ffffffff81519bcd>] do_fd_request+0x37/0xaa
[ 15.802386] [<ffffffff813d78a6>] __blk_run_queue+0x1e/0x20
[ 15.809093] [<ffffffff813dcdae>] blk_drain_queue+0x41/0x7a
[ 15.815795] [<ffffffff813dcf0c>] blk_cleanup_queue+0x125/0x184
[ 15.822887] [<ffffffff8213eb69>] floppy_init+0xd9c/0xdc2
[ 15.829398] [<ffffffff8213ddcd>] ? daring+0x65/0x65
[ 15.835414] [<ffffffff810002f7>] do_one_initcall+0x7f/0x140
[ 15.842214] [<ffffffff8210fc16>] kernel_init+0xcb/0x14f
[ 15.848620] [<ffffffff8198bf04>] kernel_thread_helper+0x4/0x10
[ 15.855715] [<ffffffff81983334>] ? retint_restore_args+0x13/0x13
[ 15.863001] [<ffffffff8210fb4b>] ? start_kernel+0x390/0x390
[ 15.869802] [<ffffffff8198bf00>] ? gs_change+0x13/0x13
[ 15.876108] ---[ end trace 4eaa2a86a8e2da2b ]---
[ 15.882068] ------------[ cut here ]------------
[ 15.887707] WARNING: at /c/wfg/linux-next/drivers/block/floppy.c:2929 do_fd_request+0x37/0xaa()
[ 15.898305] Hardware name: SandyBridge Platform
[ 15.903838] VFS: do_fd_request called on non-open device
[ 15.910252] Modules linked in:
[ 15.914227] Pid: 1, comm: swapper Tainted: G W 3.1.0-ioless-full-next-20111025+ #881
[ 15.924625] Call Trace:
[ 15.927833] [<ffffffff81074534>] warn_slowpath_common+0x85/0x9d
[ 15.935022] [<ffffffff810745ef>] warn_slowpath_fmt+0x46/0x48
[ 15.941922] [<ffffffff813ea19a>] ? blk_throtl_drain+0xf6/0x105
[ 15.949015] [<ffffffff819830be>] ? _raw_spin_unlock_irq+0x30/0x3c
[ 15.956399] [<ffffffff81519bcd>] do_fd_request+0x37/0xaa
[ 15.962905] [<ffffffff813d78a6>] __blk_run_queue+0x1e/0x20
[ 15.969609] [<ffffffff813dcdae>] blk_drain_queue+0x41/0x7a
[ 15.976316] [<ffffffff813dcf0c>] blk_cleanup_queue+0x125/0x184
[ 15.983409] [<ffffffff8213eb69>] floppy_init+0xd9c/0xdc2
[ 15.989917] [<ffffffff8213ddcd>] ? daring+0x65/0x65
[ 15.995936] [<ffffffff810002f7>] do_one_initcall+0x7f/0x140
[ 16.002738] [<ffffffff8210fc16>] kernel_init+0xcb/0x14f
[ 16.009148] [<ffffffff8198bf04>] kernel_thread_helper+0x4/0x10
[ 16.016241] [<ffffffff81983334>] ? retint_restore_args+0x13/0x13
[ 16.023530] [<ffffffff8210fb4b>] ? start_kernel+0x390/0x390
[ 16.030329] [<ffffffff8198bf00>] ? gs_change+0x13/0x13
[ 16.036645] ---[ end trace 4eaa2a86a8e2da2c ]---
[ 16.052353] brd: module loaded
[ 16.061308] loop: module loaded
[ 16.066656] Loading iSCSI transport class v2.0-870.
[ 16.074429] Loading Adaptec I2O RAID: Version 2.4 Build 5go
[ 16.081152] Detecting Adaptec I2O RAID controllers...
[ 16.088191] Adaptec aacraid driver 1.1-7[28000]-ms
[ 16.098300] aic94xx: Adaptec aic94xx SAS/SATA driver version 1.0.3 loaded
[ 16.107101] qla2xxx [0000:00:00.0]-0005: : QLogic Fibre Channel HBA Driver: 8.03.07.07-k.
[ 16.117675] iscsi: registered transport (qla4xxx)
[ 16.123757] QLogic iSCSI HBA Driver
[ 16.128519] megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
[ 16.137779] megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
[ 16.146389] megasas: 00.00.06.12-rc1 Wed. Oct. 5 17:00:00 PDT 2011
[ 16.154141] mpt2sas version 09.100.00.01 loaded
[ 16.161415] ahci 0000:00:1f.2: version 3.0
[ 16.166508] IOAPIC[0]: Set routing entry (0-21 -> 0x6a -> IRQ 21 Mode:1 Active:1 Dest:0)
[ 16.202405] ahci 0000:00:1f.2: PCI INT B -> GSI 21 (level, low) -> IRQ 21
[ 16.210614] ahci 0000:00:1f.2: irq 104 for MSI/MSI-X
[ 16.229491] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
[ 16.239385] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ems apst
[ 16.249176] ahci 0000:00:1f.2: setting latency timer to 64
[ 16.286010] scsi0 : ahci
[ 16.289722] scsi1 : ahci
[ 16.293354] scsi2 : ahci
[ 16.307557] scsi3 : ahci
[ 16.311192] scsi4 : ahci
[ 16.314807] scsi5 : ahci
[ 16.328514] ata1: SATA max UDMA/133 abar m2048@0xd3110000 port 0xd3110100 irq 104
[ 16.337735] ata2: SATA max UDMA/133 abar m2048@0xd3110000 port 0xd3110180 irq 104
[ 16.346944] ata3: DUMMY
[ 16.350131] ata4: DUMMY
[ 16.353327] ata5: DUMMY
[ 16.356517] ata6: DUMMY
[ 16.359740] work_for_cpu used greatest stack depth: 4984 bytes left
[ 16.367860] tun: Universal TUN/TAP device driver, 1.6
[ 16.373995] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
[ 16.382079] Atheros(R) L2 Ethernet Driver - version 2.2.3
[ 16.388601] Copyright (c) 2007 Atheros Corporation.
[ 16.395859] cnic: Broadcom NetXtreme II CNIC Driver cnic v2.5.7 (July 20, 2011)
[ 16.405425] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
[ 16.412720] e100: Copyright(c) 1999-2006 Intel Corporation
[ 16.419681] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 16.428048] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 16.435321] e1000e: Intel(R) PRO/1000 Network Driver - 1.5.1-k
[ 16.442324] e1000e: Copyright(c) 1999 - 2011 Intel Corporation.
[ 16.449810] Intel(R) Gigabit Ethernet Network Driver - version 3.2.10-k
[ 16.457688] Copyright (c) 2007-2011 Intel Corporation.
[ 16.464278] igb 0000:09:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[ 16.472842] igb 0000:09:00.0: irq 105 for MSI/MSI-X
[ 16.504263] igb 0000:09:00.0: irq 106 for MSI/MSI-X
[ 16.510200] igb 0000:09:00.0: irq 107 for MSI/MSI-X
[ 16.516138] igb 0000:09:00.0: irq 108 for MSI/MSI-X
[ 16.534243] igb 0000:09:00.0: irq 109 for MSI/MSI-X
[ 16.540171] igb 0000:09:00.0: irq 110 for MSI/MSI-X
[ 16.546094] igb 0000:09:00.0: irq 111 for MSI/MSI-X
[ 16.564229] igb 0000:09:00.0: irq 112 for MSI/MSI-X
[ 16.570151] igb 0000:09:00.0: irq 113 for MSI/MSI-X
[ 16.639197] igb 0000:09:00.0: DCA enabled
[ 16.644242] igb 0000:09:00.0: Intel(R) Gigabit Ethernet Network Connection
[ 16.652386] igb 0000:09:00.0: eth0: (PCIe:5.0Gb/s:Width x4) 00:1e:67:0d:ba:3a
[ 16.660898] igb 0000:09:00.0: eth0: PBA No: 0050FF-0FF
[ 16.664217] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 16.664260] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 16.681831] igb 0000:09:00.0: Using MSI-X interrupts. 8 rx queue(s), 8 tx queue(s)
[ 16.681938] ata2.00: ATAPI: ATAPI iHAS124 B, AL0L, max UDMA/100
[ 16.698797] ata1.00: ATA-8: WDC WD1002FAEX-00Z3A0, 05.01D05, max UDMA/133
[ 16.706877] ata1.00: 1953525168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
[ 16.707176] IOAPIC[0]: Set routing entry (0-17 -> 0xc2 -> IRQ 17 Mode:1 Active:1 Dest:0)
[ 16.707185] igb 0000:09:00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
[ 16.707874] igb 0000:09:00.1: irq 114 for MSI/MSI-X
[ 16.707888] igb 0000:09:00.1: irq 115 for MSI/MSI-X
[ 16.707902] igb 0000:09:00.1: irq 116 for MSI/MSI-X
[ 16.707915] igb 0000:09:00.1: irq 117 for MSI/MSI-X
[ 16.707929] igb 0000:09:00.1: irq 118 for MSI/MSI-X
[ 16.707942] igb 0000:09:00.1: irq 119 for MSI/MSI-X
[ 16.707961] igb 0000:09:00.1: irq 120 for MSI/MSI-X
[ 16.707974] igb 0000:09:00.1: irq 121 for MSI/MSI-X
[ 16.707987] igb 0000:09:00.1: irq 122 for MSI/MSI-X
[ 16.761252] igb 0000:09:00.1: DCA enabled
[ 16.761408] igb 0000:09:00.1: Intel(R) Gigabit Ethernet Network Connection
[ 16.761410] igb 0000:09:00.1: eth1: (PCIe:5.0Gb/s:Width x4) 00:1e:67:0d:ba:3b
[ 16.761489] igb 0000:09:00.1: eth1: PBA No: 0050FF-0FF
[ 16.761491] igb 0000:09:00.1: Using MSI-X interrupts. 8 rx queue(s), 8 tx queue(s)
[ 16.770125] igb 0000:09:00.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[ 16.770779] igb 0000:09:00.2: irq 123 for MSI/MSI-X
[ 16.770793] igb 0000:09:00.2: irq 124 for MSI/MSI-X
[ 16.770807] igb 0000:09:00.2: irq 125 for MSI/MSI-X
[ 16.770820] igb 0000:09:00.2: irq 126 for MSI/MSI-X
[ 16.770838] igb 0000:09:00.2: irq 127 for MSI/MSI-X
[ 16.770852] igb 0000:09:00.2: irq 128 for MSI/MSI-X
[ 16.770866] igb 0000:09:00.2: irq 129 for MSI/MSI-X
[ 16.770879] igb 0000:09:00.2: irq 130 for MSI/MSI-X
[ 16.770897] igb 0000:09:00.2: irq 131 for MSI/MSI-X
[ 16.824529] igb 0000:09:00.2: DCA enabled
[ 16.824712] igb 0000:09:00.2: Intel(R) Gigabit Ethernet Network Connection
[ 16.824714] igb 0000:09:00.2: eth2: (PCIe:5.0Gb/s:Width x4) 00:1e:67:0d:ba:3c
[ 16.824794] igb 0000:09:00.2: eth2: PBA No: 0050FF-0FF
[ 16.824796] igb 0000:09:00.2: Using MSI-X interrupts. 8 rx queue(s), 8 tx queue(s)
[ 16.837091] igb 0000:09:00.3: PCI INT D -> GSI 19 (level, low) -> IRQ 19
[ 16.837737] igb 0000:09:00.3: irq 132 for MSI/MSI-X
[ 16.837756] igb 0000:09:00.3: irq 133 for MSI/MSI-X
[ 16.837771] igb 0000:09:00.3: irq 134 for MSI/MSI-X
[ 16.837784] igb 0000:09:00.3: irq 135 for MSI/MSI-X
[ 16.837798] igb 0000:09:00.3: irq 136 for MSI/MSI-X
[ 16.837811] igb 0000:09:00.3: irq 137 for MSI/MSI-X
[ 16.837825] igb 0000:09:00.3: irq 138 for MSI/MSI-X
[ 16.837838] igb 0000:09:00.3: irq 139 for MSI/MSI-X
[ 16.837852] igb 0000:09:00.3: irq 140 for MSI/MSI-X
[ 16.891524] igb 0000:09:00.3: DCA enabled
[ 16.891680] igb 0000:09:00.3: Intel(R) Gigabit Ethernet Network Connection
[ 16.891683] igb 0000:09:00.3: eth3: (PCIe:5.0Gb/s:Width x4) 00:1e:67:0d:ba:3d
[ 16.891761] igb 0000:09:00.3: eth3: PBA No: 0050FF-0FF
[ 16.891763] igb 0000:09:00.3: Using MSI-X interrupts. 8 rx queue(s), 8 tx queue(s)
[ 16.891952] Intel(R) Gigabit Virtual Function Network Driver - version 2.0.1-k
[ 16.891954] Copyright (c) 2009 - 2011 Intel Corporation.
[ 16.892163] ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.6.7-k
[ 16.892165] ixgbe: Copyright (c) 1999-2011 Intel Corporation.
[ 16.892363] ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
[ 16.892365] ixgb: Copyright (c) 1999-2008 Intel Corporation.
[ 16.892749] jme: JMicron JMC2XX ethernet driver version 1.0.8
[ 16.893142] sky2: driver version 1.29
[ 16.894105] pegasus: v0.6.14 (2006/09/27), Pegasus/Pegasus II USB Ethernet driver
[ 16.894107] rtl8150: v0.6.2 (2004/08/27):rtl8150 based usb-ethernet driver
[ 16.894114] cdc_ncm: 04-Aug-2011
[ 16.894115] Fusion MPT base driver 3.04.20
[ 16.894116] Copyright (c) 1999-2008 LSI Corporation
[ 16.894129] Fusion MPT SPI Host driver 3.04.20
[ 16.894339] Fusion MPT FC Host driver 3.04.20
[ 16.894532] Fusion MPT SAS Host driver 3.04.20
[ 16.894730] Fusion MPT misc device (ioctl) driver 3.04.20
[ 16.894900] mptctl: Registered with Fusion MPT base driver
[ 16.894902] mptctl: /dev/mptctl @ (major,minor=10,220)
[ 16.895088] Initializing USB Mass Storage driver...
[ 16.895200] usb-serial: usb_serial_init - usb_register failed
[ 16.895327] usb-serial: usb_serial_init - returning with error -19
[ 16.895711] i8042: PNP: No PS/2 controller found. Probing ports directly.
[ 17.185333] ata2.00: configured for UDMA/100
[ 17.192825] ata1.00: configured for UDMA/133
[ 17.198427] scsi 0:0:0:0: Direct-Access ATA WDC WD1002FAEX-0 05.0 PQ: 0 ANSI: 5
[ 17.209141] sd 0:0:0:0: [sda] 1953525168 512-byte logical blocks: (1.00 TB/931 GiB)
[ 17.210939] scsi 1:0:0:0: CD-ROM ATAPI iHAS124 B AL0L PQ: 0 ANSI: 5
[ 17.228715] sd 0:0:0:0: [sda] Write Protect is off
[ 17.234557] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 17.240770] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 17.292277] sda: sda1 sda2 sda3 sda4 < sda5 sda6 sda7 >
[ 17.411499] i8042: Can't read CTR while initializing i8042
[ 17.412772] sd 0:0:0:0: [sda] Attached SCSI disk
[ 17.423782] i8042: probe of i8042 failed with error -5
[ 17.430837] mousedev: PS/2 mouse device common for all mice
[ 17.438692] rtc_cmos 00:06: RTC can wake from S4
[ 17.444734] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0
[ 17.452087] rtc0: alarms up to one year, y3k, 242 bytes nvram
[ 17.459123] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.06
[ 17.466305] iTCO_wdt: unable to reset NO_REBOOT flag, device disabled by hardware/BIOS
[ 17.476512] iTCO_vendor_support: vendor-support=0
[ 17.482469] Software Watchdog Timer: 0.07 initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout= 0)
[ 17.494945] md: linear personality registered for level -1
[ 17.501566] md: raid0 personality registered for level 0
[ 17.507990] md: raid1 personality registered for level 1
[ 17.514410] md: raid10 personality registered for level 10
[ 17.521025] md: raid6 personality registered for level 6
[ 17.527448] md: raid5 personality registered for level 5
[ 17.533865] md: raid4 personality registered for level 4
[ 17.540291] md: multipath personality registered for level -4
[ 17.547198] md: faulty personality registered for level -5
[ 17.554816] device-mapper: uevent: version 1.0.3
[ 17.561043] device-mapper: ioctl: 4.21.0-ioctl (2011-07-06) initialised: dm-devel@redhat.com
[ 17.571661] device-mapper: multipath: version 1.3.0 loaded
[ 17.578300] device-mapper: multipath round-robin: version 1.0.0 loaded
[ 17.586088] device-mapper: multipath queue-length: version 0.1.0 loaded
[ 17.593962] device-mapper: multipath service-time: version 0.2.0 loaded
[ 17.602266] device-mapper: dm-log-userspace: version 1.1.0 loaded
[ 17.615003] cpuidle: using governor ladder
[ 17.630146] cpuidle: using governor menu
[ 17.636147] dell_wmi: No known WMI GUID found
[ 17.641513] acer_wmi: Acer Laptop ACPI-WMI Extras
[ 17.647255] acer_wmi: No or unsupported WMI interface, unable to load
[ 17.656765] IOAPIC[0]: Set routing entry (0-22 -> 0x64 -> IRQ 22 Mode:1 Active:1 Dest:0)
[ 17.666683] snd_hda_intel 0000:00:1b.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
[ 17.701816] snd_hda_intel 0000:00:1b.0: irq 141 for MSI/MSI-X
[ 17.708772] ALSA hda_intel.c:2733 chipset global capabilities = 0x4401
[ 17.728682] ALSA hda_intel.c:1163 Clearing TCSEL
[ 17.734313] ALSA hda_intel.c:1206 SCH snoop: Enabled
[ 17.756632] ALSA hda_intel.c:1009 codec_mask = 0x0
[ 17.762462] ALSA hda_intel.c:2834 no codecs found!
[ 17.768397] snd_hda_intel 0000:00:1b.0: PCI INT A disabled
[ 17.788001] ALSA device list:
[ 17.791806] No soundcards found.
[ 17.796093] oprofile: using NMI interrupt.
[ 17.801358] netem: version 1.3
[ 17.805258] Netfilter messages via NETLINK v0.30.
[ 17.811082] nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
[ 17.820455] ctnetlink v0.93: registering with nfnetlink.
[ 17.826972] NF_TPROXY: Transparent proxy support initialized, version 4.1.0
[ 17.835244] NF_TPROXY: Copyright (c) 2006-2007 BalaBit IT Ltd.
[ 17.843176] xt_time: kernel timezone is -0000
[ 17.852571] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 17.861031] ipt_CLUSTERIP: ClusterIP Version 0.8 loaded successfully
[ 17.868670] arp_tables: (C) 2002 David S. Miller
[ 17.874713] TCP bic registered
[ 17.878611] TCP cubic registered
[ 17.882702] TCP westwood registered
[ 17.887081] TCP highspeed registered
[ 17.891567] TCP hybla registered
[ 17.895657] TCP htcp registered
[ 17.899646] TCP vegas registered
[ 17.903733] TCP veno registered
[ 17.907724] TCP scalable registered
[ 17.912100] TCP lp registered
[ 17.915903] TCP yeah registered
[ 17.919893] TCP illinois registered
[ 17.924271] Initializing XFRM netlink socket
[ 17.930786] NET: Registered protocol family 10
[ 17.950609] IPv6 over IPv4 tunneling driver
[ 17.960481] NET: Registered protocol family 17
[ 17.965950] NET: Registered protocol family 15
[ 17.971761] Bridge firewalling registered
[ 17.976758] Ebtables v2.0 registered
[ 17.981499] Registering the dns_resolver key type
[ 17.987413]
[ 17.987415] printing PIC contents
[ 17.993738] ... PIC IMR: ffff
[ 17.997627] ... PIC IRR: 0c21
[ 18.001530] ... PIC ISR: 0000
[ 18.005423] ... PIC ELCR: 0c20
[ 18.009324] printing local APIC contents on CPU#0/0:
[ 18.015325] ... APIC ID: 00000000 (0)
[ 18.020350] ... APIC VERSION: 01060015
[ 18.024976] ... APIC TASKPRI: 00000000 (00)
[ 18.030099] ... APIC PROCPRI: 00000000
[ 18.034734] ... APIC LDR: 01000000
[ 18.038979] ... APIC DFR: ffffffff
[ 18.043224] ... APIC SPIV: 000001ff
[ 18.047558] ... APIC ISR field:
[ 18.051504] 0000000000000000000000000000000000000000000000000000000000000000
[ 18.060475] ... APIC TMR field:
[ 18.064429] 0000000000000000000000000000000000000000000000000000000000000000
[ 18.073390] ... APIC IRR field:
[ 18.077345] 0000000000000000000000000000000000000000000000000000000000008000
[ 18.086320] ... APIC ESR: 00000000
[ 18.090565] ... APIC ICR: 000000fd
[ 18.094809] ... APIC ICR2: 2f000000
[ 18.099151] ... APIC LVTT: 000000ef
[ 18.103483] ... APIC LVTPC: 00000400
[ 18.107921] ... APIC LVT0: 00010700
[ 18.112262] ... APIC LVT1: 00000400
[ 18.116604] ... APIC LVTERR: 000000fe
[ 18.121141] ... APIC TMICT: 00001846
[ 18.125580] ... APIC TMCCT: 00000000
[ 18.130009] ... APIC TDCR: 00000003
[ 18.134350]
[ 18.136460] number of MP IRQ sources: 15.
[ 18.141429] number of IO-APIC #0 registers: 24.
[ 18.146975] number of IO-APIC #1 registers: 24.
[ 18.152519] number of IO-APIC #2 registers: 24.
[ 18.158063] testing the IO APIC.......................
[ 18.164297]
[ 18.166441] IO APIC #0......
[ 18.170136] .... register #00: 00000000
[ 18.174904] ....... : physical APIC id: 00
[ 18.180254] ....... : Delivery Type: 0
[ 18.185216] ....... : LTS : 0
[ 18.190177] .... register #01: 00170020
[ 18.194947] ....... : max redirection entries: 17
[ 18.201076] ....... : PRQ implemented: 0
[ 18.206324] ....... : IO APIC version: 20
[ 18.211676] .... IRQ redirection table:
[ 18.216444] NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:
[ 18.223061] 00 A5 1 0 0 0 0 0 2 34
[ 18.229497] 01 00 0 0 0 0 0 0 0 31
[ 18.235924] 02 00 0 0 0 0 0 0 0 30
[ 18.242345] 03 00 0 0 0 0 0 0 0 33
[ 18.248769] 04 00 0 0 0 0 0 0 0 34
[ 18.255191] 05 00 0 0 0 0 0 0 0 35
[ 18.261616] 06 00 1 0 0 0 0 0 0 36
[ 18.268041] 07 00 0 0 0 0 0 0 0 37
[ 18.274476] 08 00 0 0 0 0 0 0 0 38
[ 18.280892] 09 00 0 1 0 0 0 0 0 39
[ 18.287317] 0a 00 0 0 0 0 0 0 0 3A
[ 18.293742] 0b 00 0 0 0 0 0 0 0 3B
[ 18.300168] 0c 00 0 0 0 0 0 0 0 3C
[ 18.306589] 0d 00 0 0 0 0 0 0 0 3D
[ 18.313014] 0e 00 0 0 0 0 0 0 0 3E
[ 18.319437] 0f 00 0 0 0 0 0 0 0 3F
[ 18.325864] 10 00 1 1 0 1 0 0 0 49
[ 18.332290] 11 00 1 1 0 1 0 0 0 C2
[ 18.338715] 12 00 1 1 0 1 0 0 0 51
[ 18.345132] 13 00 1 1 0 1 0 0 0 59
[ 18.351559] 14 00 1 0 0 0 0 0 0 00
[ 18.357984] 15 00 1 1 0 1 0 0 0 6A
[ 18.364406] 16 00 1 1 0 1 0 0 0 64
[ 18.370830] 17 00 1 0 0 0 0 0 0 00
[ 18.377257]
[ 18.379397] IO APIC #1......
[ 18.383093] .... register #00: 01000000
[ 18.387861] ....... : physical APIC id: 01
[ 18.402867] ....... : Delivery Type: 0
[ 18.407827] ....... : LTS : 0
[ 18.412786] .... register #01: 00170020
[ 18.417554] ....... : max redirection entries: 17
[ 18.423684] ....... : PRQ implemented: 0
[ 18.428939] ....... : IO APIC version: 20
[ 18.434287] .... register #02: 00000000
[ 18.439055] ....... : arbitration: 00
[ 18.444017] .... register #03: 00000001
[ 18.448773] ....... : Boot DT : 1
[ 18.453640] .... IRQ redirection table:
[ 18.458408] NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:
[ 18.465022] 00 00 1 0 0 0 0 0 0 00
[ 18.471448] 01 00 1 0 0 0 0 0 0 00
[ 18.477874] 02 00 1 1 0 1 0 0 0 41
[ 18.484298] 03 00 1 0 0 0 0 0 0 00
[ 18.490719] 04 00 1 0 0 0 0 0 0 00
[ 18.497134] 05 00 1 0 0 0 0 0 0 00
[ 18.503560] 06 00 1 0 0 0 0 0 0 00
[ 18.509983] 07 00 1 1 0 1 0 0 0 69
[ 18.516407] 08 00 1 0 0 0 0 0 0 00
[ 18.522830] 09 00 1 0 0 0 0 0 0 00
[ 18.529258] 0a 00 1 0 0 0 0 0 0 00
[ 18.535680] 0b 00 1 0 0 0 0 0 0 00
[ 18.542105] 0c 00 1 0 0 0 0 0 0 00
[ 18.548529] 0d 00 1 0 0 0 0 0 0 00
[ 18.554948] 0e 00 1 0 0 0 0 0 0 00
[ 18.561371] 0f 00 1 1 0 1 0 0 0 79
[ 18.567794] 10 00 1 0 0 0 0 0 0 00
[ 18.574218] 11 00 1 0 0 0 0 0 0 00
[ 18.580638] 12 00 1 0 0 0 0 0 0 00
[ 18.587060] 13 00 1 0 0 0 0 0 0 00
[ 18.593485] 14 00 1 0 0 0 0 0 0 00
[ 18.599905] 15 00 1 0 0 0 0 0 0 00
[ 18.606329] 16 00 1 0 0 0 0 0 0 00
[ 18.612753] 17 00 1 1 0 1 0 0 0 29
[ 18.619173]
[ 18.621316] IO APIC #2......
[ 18.625012] .... register #00: 02000000
[ 18.629779] ....... : physical APIC id: 02
[ 18.635127] ....... : Delivery Type: 0
[ 18.640089] ....... : LTS : 0
[ 18.645053] .... register #01: 00170020
[ 18.649818] ....... : max redirection entries: 17
[ 18.655946] ....... : PRQ implemented: 0
[ 18.661203] ....... : IO APIC version: 20
[ 18.666551] .... register #02: 00000000
[ 18.671318] ....... : arbitration: 00
[ 18.676281] .... register #03: 00000001
[ 18.681050] ....... : Boot DT : 1
[ 18.685911] .... IRQ redirection table:
[ 18.690679] NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:
[ 18.697295] 00 00 1 0 0 0 0 0 0 00
[ 18.703717] 01 00 1 0 0 0 0 0 0 00
[ 18.710138] 02 00 1 0 0 0 0 0 0 00
[ 18.716564] 03 00 1 0 0 0 0 0 0 00
[ 18.722984] 04 00 1 0 0 0 0 0 0 00
[ 18.729410] 05 00 1 0 0 0 0 0 0 00
[ 18.735835] 06 00 1 0 0 0 0 0 0 00
[ 18.742258] 07 00 1 1 0 1 0 0 0 B9
[ 18.748683] 08 00 1 0 0 0 0 0 0 00
[ 18.755110] 09 00 1 0 0 0 0 0 0 00
[ 18.761533] 0a 00 1 0 0 0 0 0 0 00
[ 18.767955] 0b 00 1 0 0 0 0 0 0 00
[ 18.774381] 0c 00 1 0 0 0 0 0 0 00
[ 18.780801] 0d 00 1 0 0 0 0 0 0 00
[ 18.787225] 0e 00 1 0 0 0 0 0 0 00
[ 18.793651] 0f 00 1 1 0 1 0 0 0 C9
[ 18.800072] 10 00 1 0 0 0 0 0 0 00
[ 18.806504] 11 00 1 0 0 0 0 0 0 00
[ 18.812929] 12 00 1 0 0 0 0 0 0 00
[ 18.819351] 13 00 1 0 0 0 0 0 0 00
[ 18.825773] 14 00 1 0 0 0 0 0 0 00
[ 18.832198] 15 00 1 0 0 0 0 0 0 00
[ 18.838617] 16 00 1 0 0 0 0 0 0 00
[ 18.845041] 17 00 1 1 0 1 0 0 0 61
[ 18.851461] IRQ to pin mappings:
[ 18.855551] IRQ0 -> 0:2
[ 18.858952] IRQ1 -> 0:1
[ 18.862355] IRQ3 -> 0:3
[ 18.865748] IRQ4 -> 0:4
[ 18.869152] IRQ5 -> 0:5
[ 18.872551] IRQ6 -> 0:6
[ 18.875947] IRQ7 -> 0:7
[ 18.879350] IRQ8 -> 0:8
[ 18.882750] IRQ9 -> 0:9
[ 18.886155] IRQ10 -> 0:10
[ 18.889746] IRQ11 -> 0:11
[ 18.893349] IRQ12 -> 0:12
[ 18.896945] IRQ13 -> 0:13
[ 18.900537] IRQ14 -> 0:14
[ 18.904137] IRQ15 -> 0:15
[ 18.907726] IRQ16 -> 0:16
[ 18.911327] IRQ17 -> 0:17
[ 18.914921] IRQ18 -> 0:18
[ 18.918520] IRQ19 -> 0:19
[ 18.922120] IRQ21 -> 0:21
[ 18.925712] IRQ22 -> 0:22
[ 18.929313] IRQ26 -> 1:2
[ 18.932807] IRQ31 -> 1:7
[ 18.936311] IRQ39 -> 1:15
[ 18.939903] IRQ47 -> 1:23
[ 18.943499] IRQ55 -> 2:7
[ 18.946995] IRQ63 -> 2:15
[ 18.950590] IRQ71 -> 2:23
[ 18.954194] .................................... done.
[ 18.961004] PM: Hibernation image not present or could not be loaded.
[ 18.968750] registered taskstats version 1
[ 18.977767] Magic number: 15:156:950
[ 18.982484] tty ttya5: hash matches
[ 18.986924] cpuid cpu5: hash matches
[ 18.991418] tty tty7: hash matches
[ 18.995846] netconsole: local port 6665
[ 19.000623] netconsole: local IP 10.0.0.0
[ 19.005587] netconsole: interface 'eth0'
[ 19.010451] netconsole: remote port 6666
[ 19.015318] netconsole: remote IP 192.168.1.1
[ 19.020670] netconsole: remote ethernet address 00:30:48:fe:19:95
[ 19.027966] netconsole: device eth0 not up yet, forcing it
[ 19.124399] ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 20.335815] igb: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX
[ 20.346269] ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 20.375024] console [netcon0] enabled
[ 20.379608] netconsole: network logging started
[ 20.385242] rtc_cmos 00:06: setting system clock to 2011-10-31 18:57:05 UTC (1320087425)
[ 20.433441] IP-Config: Complete:
[ 20.437542] device=eth0, addr=192.168.1.61, mask=255.255.255.0, gw=192.168.1.1,
[ 20.446701] host=snb, domain=, nis-domain=(none),
[ 20.453021] bootserver=192.168.1.11, rootserver=192.168.1.11, rootpath=
[ 20.462814] md: Waiting for all devices to be available before autodetect
[ 20.470908] md: If you don't use raid, use raid=noautodetect
[ 20.478401] md: Autodetecting RAID arrays.
[ 20.483453] md: Scanned 0 and added 0 devices.
[ 20.488886] md: autorun ...
[ 20.492474] md: ... autorun DONE.
[ 20.503368] VFS: Mounted root (nfs filesystem) on device 0:15.
[ 20.510442] debug: unmapping init memory ffffffff81f3a000..ffffffff821ee000
[ 20.619457] stty used greatest stack depth: 4192 bytes left
[ 20.639198] startpar used greatest stack depth: 3904 bytes left
[ 20.665613] uname used greatest stack depth: 3680 bytes left
[ 20.722252] S02hostname.sh used greatest stack depth: 3648 bytes left
[ 20.752254] mountpoint used greatest stack depth: 3552 bytes left
[ 22.459605] S04ssh used greatest stack depth: 3504 bytes left
[ 22.967174] EXT4-fs (sda3): warning: maximal mount count reached, running e2fsck is recommended
[ 22.982371] EXT4-fs (sda3): recovery complete
[ 22.987772] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null)
[ 23.525484] cat used greatest stack depth: 3328 bytes left
[ 23.598088] mount.nfs used greatest stack depth: 3168 bytes left
[ 25.083927] NFSD: Using /var/lib/nfs/v4recovery as the NFSv4 state recovery directory
[ 25.094437] NFSD: starting 90-second grace period
[ 27.589492] mount.nfs used greatest stack depth: 2640 bytes left
[ 28.526478] XFS (sda7): Mounting Filesystem
[ 28.653258] XFS (sda7): Ending clean mount
[ 31.208071] eth0: no IPv6 routers present
^ permalink raw reply
* Re: linux-next: build error from iio_simple_dummy_buffer.c
From: Dan Carpenter @ 2011-10-31 11:38 UTC (permalink / raw)
To: Jonathan Cameron; +Cc: linux-iio
In-Reply-To: <4EAE8574.2050900@cam.ac.uk>
[-- Attachment #1: Type: text/plain, Size: 990 bytes --]
On Mon, Oct 31, 2011 at 11:24:36AM +0000, Jonathan Cameron wrote:
> On 10/28/11 12:29, Dan Carpenter wrote:
> > I get a compile error in linux-next:
> >
> > CC [M] drivers/staging/iio/iio_simple_dummy_buffer.o
> > drivers/staging/iio/iio_simple_dummy_buffer.c: In function ‘iio_simple_dummy_configure_buffer’:
> > drivers/staging/iio/iio_simple_dummy_buffer.c:154:18: error: ‘THIS_MODULE’ undeclared (first use in this function)
> > drivers/staging/iio/iio_simple_dummy_buffer.c:154:18: note: each undeclared identifier is reported only once for each function it appears in
> > make[1]: *** [drivers/staging/iio/iio_simple_dummy_buffer.o] Error 1
> > make: *** [drivers/staging/iio/iio_simple_dummy_buffer.o] Error 2
> >
> > We could just include <linux/module.h> I guess?
> Yup, my bad. Do you want to do the patch, or shall I do it and
> credit it to you?
Do no work and collect a Reported-by is always prefered. :)
thanks,
dan carpenter
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* Re: [patch 3/5] mm: try to distribute dirty pages fairly across zones
From: Wu Fengguang @ 2011-10-31 11:33 UTC (permalink / raw)
To: Johannes Weiner
Cc: Michal Hocko, Andrew Morton, Mel Gorman, Christoph Hellwig,
Dave Chinner, Jan Kara, Rik van Riel, Minchan Kim, Chris Mason,
Theodore Ts'o, Andreas Dilger, Li, Shaohua, xfs@oss.sgi.com,
linux-btrfs@vger.kernel.org, linux-ext4@vger.kernel.org,
linux-mm@kvack.org, linux-fsdevel@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20111028201829.GA20607@localhost>
> //regression
> 3) much increased cpu %user and %system for btrfs
Sorry I find out that the CPU time regressions for btrfs are caused by
some additional trace events enabled on btrfs (for debugging an
unrelated btrfs hang bug) which results in 7 times more trace event
lines:
2701238 /export/writeback/thresh=1000M/btrfs-1dd-4k-8p-2941M-1000M:10-3.1.0-rc9-ioless-full-nfs-wq5-next-20111014+
19054054 /export/writeback/thresh=1000M/btrfs-1dd-4k-8p-2941M-1000M:10-3.1.0-rc9-ioless-full-per-zone-dirty-next-20111014+
So no real regressions.
Besides, the patchset also performs good on random writes:
3.1.0-rc9-ioless-full-nfs-wq5-next-20111014+ 3.1.0-rc9-ioless-full-per-zone-dirty-next-20111014+
------------------------ ------------------------
1.65 -5.1% 1.57 MMAP-RANDWRITE-4K/btrfs-fio_fat_mmap_randwrite_4k-4k-8p-4096M-20:10-X
18.65 -6.4% 17.46 MMAP-RANDWRITE-4K/ext3-fio_fat_mmap_randwrite_4k-4k-8p-4096M-20:10-X
2.09 +1.2% 2.12 MMAP-RANDWRITE-4K/ext4-fio_fat_mmap_randwrite_4k-4k-8p-4096M-20:10-X
2.49 -0.3% 2.48 MMAP-RANDWRITE-4K/xfs-fio_fat_mmap_randwrite_4k-4k-8p-4096M-20:10-X
51.35 +0.0% 51.36 MMAP-RANDWRITE-64K/btrfs-fio_fat_mmap_randwrite_64k-64k-8p-4096M-20:10-X
45.20 +0.5% 45.43 MMAP-RANDWRITE-64K/ext3-fio_fat_mmap_randwrite_64k-64k-8p-4096M-20:10-X
44.77 +0.7% 45.10 MMAP-RANDWRITE-64K/ext4-fio_fat_mmap_randwrite_64k-64k-8p-4096M-20:10-X
45.11 +2.5% 46.23 MMAP-RANDWRITE-64K/xfs-fio_fat_mmap_randwrite_64k-64k-8p-4096M-20:10-X
211.31 +0.2% 211.74 TOTAL write_bw
And writes to USB key:
3.1.0-rc9-ioless-full-nfs-wq5-next-20111014+ 3.1.0-rc9-ioless-full-per-zone-dirty-next-20111014+
------------------------ ------------------------
5.94 +0.8% 5.99 UKEY-thresh=1G/btrfs-1dd-4k-8p-4096M-1024M:10-X
2.64 -0.8% 2.62 UKEY-thresh=1G/ext3-10dd-4k-8p-4096M-1024M:10-X
5.10 +0.3% 5.12 UKEY-thresh=1G/ext3-1dd-4k-8p-4096M-1024M:10-X
3.26 -0.8% 3.24 UKEY-thresh=1G/ext3-2dd-4k-8p-4096M-1024M:10-X
5.63 -0.5% 5.60 UKEY-thresh=1G/ext4-10dd-4k-8p-4096M-1024M:10-X
6.04 -0.1% 6.04 UKEY-thresh=1G/ext4-1dd-4k-8p-4096M-1024M:10-X
5.90 -0.2% 5.88 UKEY-thresh=1G/ext4-2dd-4k-8p-4096M-1024M:10-X
2.45 +22.6% 3.00 UKEY-thresh=1G/xfs-10dd-4k-8p-4096M-1024M:10-X
6.18 -0.4% 6.16 UKEY-thresh=1G/xfs-1dd-4k-8p-4096M-1024M:10-X
4.81 +0.0% 4.81 UKEY-thresh=1G/xfs-2dd-4k-8p-4096M-1024M:10-X
47.94 +1.1% 48.45 TOTAL write_bw
In summary, I see no problem at all in these trivial writeback tests.
Tested-by: Wu Fengguang <fengguang.wu@intel.com>
Thanks,
Fengguang
^ permalink raw reply
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