* [net 3/5] bnx2x: Remove 100Mb force speed for BCM84833
From: Yaniv Rosner @ 2012-01-17 12:33 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Yaniv Rosner, Eilon Greenstein
In-Reply-To: <1326803609-25526-1-git-send-email-yanivr@broadcom.com>
Remove unsupported speed of 100Mb force for BCM84833 due to hardware limitation.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
---
.../net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c | 7 ++++++-
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 20 +++++++++++++++-----
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
index a688b9d..f99c6e3 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
@@ -365,13 +365,18 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
if (cmd->autoneg == AUTONEG_ENABLE) {
+ u32 an_supported_speed = bp->port.supported[cfg_idx];
+ if (bp->link_params.phy[EXT_PHY1].type ==
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
+ an_supported_speed |= (SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full);
if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
DP(NETIF_MSG_LINK, "Autoneg not supported\n");
return -EINVAL;
}
/* advertise the requested speed and duplex if supported */
- if (cmd->advertising & ~(bp->port.supported[cfg_idx])) {
+ if (cmd->advertising & ~an_supported_speed) {
DP(NETIF_MSG_LINK, "Advertisement parameters "
"are not supported\n");
return -EINVAL;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index cc80637..1d1a809 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -9454,13 +9454,10 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
an_1000_val);
/* set 100 speed advertisement */
- if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
+ if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
(phy->speed_cap_mask &
(PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
- PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
- (phy->supported &
- (SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full)))) {
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
an_10_100_val |= (1<<7);
/* Enable autoneg and restart autoneg for legacy speeds */
autoneg_val |= (1<<9 | 1<<12);
@@ -11528,6 +11525,19 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
}
phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
+ if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
+ (phy->ver_addr)) {
+ /*
+ * Remove 100Mb link supported for BCM84833 when phy fw
+ * version lower than or equal to 1.39
+ */
+ u32 raw_ver = REG_RD(bp, phy->ver_addr);
+ if (((raw_ver & 0x7F) <= 39) &&
+ (((raw_ver & 0xF80) >> 7) <= 1))
+ phy->supported &= ~(SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full);
+ }
+
/*
* In case mdc/mdio_access of the external phy is different than the
* mdc/mdio access of the XGXS, a HW lock must be taken in each access
--
1.7.7.1
^ permalink raw reply related
* [net 5/5] bnx2x: Disable AN KR work-around for BCM57810
From: Yaniv Rosner @ 2012-01-17 12:33 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Yaniv Rosner, Eilon Greenstein
In-Reply-To: <1326803609-25526-1-git-send-email-yanivr@broadcom.com>
Disable the work-around for the autoneg KR of the BCM57810 in case the Warpcore version is 0xD108 and above, which fixes this problem.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
---
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 10 +++++++++-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index a6c48d6..2091e5d 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -3763,7 +3763,15 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
/* Advertise pause */
bnx2x_ext_phy_set_pause(params, phy, vars);
- vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
+ /*
+ * Set KR Autoneg Work-Around flag for Warpcore version older than D108
+ */
+ bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
+ MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
+ if (val16 < 0xd108) {
+ DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
+ vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
+ }
bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_MISC7, &val16);
--
1.7.7.1
^ permalink raw reply related
* [net 4/5] bnx2x: Remove AutoGrEEEn for BCM84833
From: Yaniv Rosner @ 2012-01-17 12:33 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Yaniv Rosner, Eilon Greenstein
In-Reply-To: <1326803609-25526-1-git-send-email-yanivr@broadcom.com>
Disable the autoGrEEEn feature for BCM84833.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
---
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 8 ++------
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 1d1a809..a6c48d6 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -9814,12 +9814,8 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
bnx2x_84833_pair_swap_cfg(phy, params, vars);
- /* AutogrEEEn */
- if (params->feature_config_flags &
- FEATURE_CONFIG_AUTOGREEEN_ENABLED)
- cmd_args[0] = 0x2;
- else
- cmd_args[0] = 0x0;
+ /* Keep AutogrEEEn disabled. */
+ cmd_args[0] = 0x0;
cmd_args[1] = 0x0;
cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
cmd_args[3] = PHY84833_CONSTANT_LATENCY;
--
1.7.7.1
^ permalink raw reply related
* [net 2/5] bnx2x: Fix PFC setting on BCM57840
From: Yaniv Rosner @ 2012-01-17 12:33 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Yaniv Rosner, Eilon Greenstein
In-Reply-To: <1326803609-25526-1-git-send-email-yanivr@broadcom.com>
This patch handles the second port of a path in a 4-port device of BCM57840.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
---
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 22 ++++++++++++----------
drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h | 1 +
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 3b184c2..cc80637 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -2502,7 +2502,7 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
struct bnx2x_nig_brb_pfc_port_params *nig_params)
{
u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
- u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
+ u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
u32 pkt_priority_to_cos = 0;
struct bnx2x *bp = params->bp;
u8 port = params->port;
@@ -2516,9 +2516,8 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
* MAC control frames (that are not pause packets)
* will be forwarded to the XCM.
*/
- xcm_mask = REG_RD(bp,
- port ? NIG_REG_LLH1_XCM_MASK :
- NIG_REG_LLH0_XCM_MASK);
+ xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
+ NIG_REG_LLH0_XCM_MASK);
/*
* nig params will override non PFC params, since it's possible to
* do transition from PFC to SAFC
@@ -2533,8 +2532,8 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
ppp_enable = 1;
xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
- xcm0_out_en = 0;
- p0_hwpfc_enable = 1;
+ xcm_out_en = 0;
+ hwpfc_enable = 1;
} else {
if (nig_params) {
llfc_out_en = nig_params->llfc_out_en;
@@ -2545,7 +2544,7 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
- xcm0_out_en = 1;
+ xcm_out_en = 1;
}
if (CHIP_IS_E3(bp))
@@ -2564,13 +2563,16 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
NIG_REG_LLH0_XCM_MASK, xcm_mask);
- REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
+ REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
+ NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
/* output enable for RX_XCM # IF */
- REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
+ REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
+ NIG_REG_XCM0_OUT_EN, xcm_out_en);
/* HW PFC TX enable */
- REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
+ REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
+ NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
if (nig_params) {
u8 i = 0;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
index 44609de..dddbcf6 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
@@ -2176,6 +2176,7 @@
* set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
* accommodate the 9 input clients to ETS arbiter. */
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
+#define NIG_REG_P1_HWPFC_ENABLE 0x181d0
#define NIG_REG_P1_MAC_IN_EN 0x185c0
/* [RW 1] Output enable for TX MAC interface */
#define NIG_REG_P1_MAC_OUT_EN 0x185c4
--
1.7.7.1
^ permalink raw reply related
* [net 0/5] bnx2x: Link related fixes
From: Yaniv Rosner @ 2012-01-17 12:33 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Yaniv Rosner
Hi Dave,
The following patch series describe some link related fixes for the bnx2x driver.
Please consider applying it to net.
Thanks,
Yaniv
^ permalink raw reply
* [net 1/5] bnx2x: Fix Super-Isolate mode for BCM84833
From: Yaniv Rosner @ 2012-01-17 12:33 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Yaniv Rosner, Eilon Greenstein
In-Reply-To: <1326803609-25526-1-git-send-email-yanivr@broadcom.com>
The Super-Isolate mode comes to isolate the BCM84833 PHY from the outside world.
Not doing it correctly, made link partner see the link before the driver was loaded.
This patch also involves SPIROM version fixes since it is used to determine whether the common init of the PHY was already executed, and the common init of this PHY is partially responsible for setting the Super-Isolate mode.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
---
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 250 ++++++++++++----------
1 files changed, 137 insertions(+), 113 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 4df9505..3b184c2 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -9266,62 +9266,68 @@ static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
/* BCM8481/BCM84823/BCM84833 PHY SECTION */
/******************************************************************/
static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
- struct link_params *params)
+ struct bnx2x *bp,
+ u8 port)
{
u16 val, fw_ver1, fw_ver2, cnt;
- u8 port;
- struct bnx2x *bp = params->bp;
- port = params->port;
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
+ bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
+ bnx2x_save_spirom_version(bp, port,
+ ((fw_ver1 & 0xf000)>>5) | (fw_ver1 & 0x7f),
+ phy->ver_addr);
+ } else {
+ /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
+ /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
+ bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
+ bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
+ bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
+ bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
+ bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
+
+ for (cnt = 0; cnt < 100; cnt++) {
+ bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
+ if (val & 1)
+ break;
+ udelay(5);
+ }
+ if (cnt == 100) {
+ DP(NETIF_MSG_LINK, "Unable to read 848xx "
+ "phy fw version(1)\n");
+ bnx2x_save_spirom_version(bp, port, 0,
+ phy->ver_addr);
+ return;
+ }
- /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
- /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
- bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
- bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
- bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
- bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
- bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
- for (cnt = 0; cnt < 100; cnt++) {
- bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
- if (val & 1)
- break;
- udelay(5);
- }
- if (cnt == 100) {
- DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
- bnx2x_save_spirom_version(bp, port, 0,
- phy->ver_addr);
- return;
- }
+ /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
+ bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
+ bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
+ bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
+ for (cnt = 0; cnt < 100; cnt++) {
+ bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
+ if (val & 1)
+ break;
+ udelay(5);
+ }
+ if (cnt == 100) {
+ DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
+ "version(2)\n");
+ bnx2x_save_spirom_version(bp, port, 0,
+ phy->ver_addr);
+ return;
+ }
+ /* lower 16 bits of the register SPI_FW_STATUS */
+ bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
+ /* upper 16 bits of register SPI_FW_STATUS */
+ bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
- /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
- bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
- bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
- bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
- for (cnt = 0; cnt < 100; cnt++) {
- bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
- if (val & 1)
- break;
- udelay(5);
- }
- if (cnt == 100) {
- DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
- bnx2x_save_spirom_version(bp, port, 0,
+ bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
phy->ver_addr);
- return;
}
- /* lower 16 bits of the register SPI_FW_STATUS */
- bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
- /* upper 16 bits of register SPI_FW_STATUS */
- bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
-
- bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
- phy->ver_addr);
}
-
static void bnx2x_848xx_set_led(struct bnx2x *bp,
struct bnx2x_phy *phy)
{
@@ -9392,10 +9398,13 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
u16 tmp_req_line_speed;
tmp_req_line_speed = phy->req_line_speed;
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
if (phy->req_line_speed == SPEED_10000)
phy->req_line_speed = SPEED_AUTO_NEG;
-
+ } else {
+ /* Save spirom version */
+ bnx2x_save_848xx_spirom_version(phy, bp, params->port);
+ }
/*
* This phy uses the NIG latch mechanism since link indication
* arrives through its LED4 and not via its LASI signal, so we
@@ -9539,9 +9548,6 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
1);
- /* Save spirom version */
- bnx2x_save_848xx_spirom_version(phy, params);
-
phy->req_line_speed = tmp_req_line_speed;
return 0;
@@ -9749,17 +9755,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
/* Wait for GPHY to come out of reset */
msleep(50);
- if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
- /* Bring PHY out of super isolate mode */
- bnx2x_cl45_read(bp, phy,
- MDIO_CTL_DEVAD,
- MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
- val &= ~MDIO_84833_SUPER_ISOLATE;
- bnx2x_cl45_write(bp, phy,
- MDIO_CTL_DEVAD,
- MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
- bnx2x_84833_pair_swap_cfg(phy, params, vars);
- } else {
+ if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
/*
* BCM84823 requires that XGXS links up first @ 10G for normal
* behavior.
@@ -9816,24 +9812,27 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
params->multi_phy_config, val);
- /* AutogrEEEn */
- if (params->feature_config_flags &
- FEATURE_CONFIG_AUTOGREEEN_ENABLED)
- cmd_args[0] = 0x2;
- else
- cmd_args[0] = 0x0;
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
+ bnx2x_84833_pair_swap_cfg(phy, params, vars);
- cmd_args[1] = 0x0;
- cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
- cmd_args[3] = PHY84833_CONSTANT_LATENCY;
- rc = bnx2x_84833_cmd_hdlr(phy, params,
- PHY84833_CMD_SET_EEE_MODE, cmd_args);
- if (rc != 0)
- DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
+ /* AutogrEEEn */
+ if (params->feature_config_flags &
+ FEATURE_CONFIG_AUTOGREEEN_ENABLED)
+ cmd_args[0] = 0x2;
+ else
+ cmd_args[0] = 0x0;
+ cmd_args[1] = 0x0;
+ cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
+ cmd_args[3] = PHY84833_CONSTANT_LATENCY;
+ rc = bnx2x_84833_cmd_hdlr(phy, params,
+ PHY84833_CMD_SET_EEE_MODE, cmd_args);
+ if (rc != 0)
+ DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
+ }
if (initialize)
rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
else
- bnx2x_save_848xx_spirom_version(phy, params);
+ bnx2x_save_848xx_spirom_version(phy, bp, params->port);
/* 84833 PHY has a better feature and doesn't need to support this. */
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
cms_enable = REG_RD(bp, params->shmem_base +
@@ -9851,6 +9850,16 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
MDIO_CTL_REG_84823_USER_CTRL_REG, val);
}
+ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
+ /* Bring PHY out of super isolate mode as the final step. */
+ bnx2x_cl45_read(bp, phy,
+ MDIO_CTL_DEVAD,
+ MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
+ val &= ~MDIO_84833_SUPER_ISOLATE;
+ bnx2x_cl45_write(bp, phy,
+ MDIO_CTL_DEVAD,
+ MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
+ }
return rc;
}
@@ -9988,10 +9997,11 @@ static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
} else {
bnx2x_cl45_read(bp, phy,
MDIO_CTL_DEVAD,
- 0x400f, &val16);
+ MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
+ val16 |= MDIO_84833_SUPER_ISOLATE;
bnx2x_cl45_write(bp, phy,
- MDIO_PMA_DEVAD,
- MDIO_PMA_REG_CTRL, 0x800);
+ MDIO_CTL_DEVAD,
+ MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
}
}
@@ -12333,55 +12343,69 @@ static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
u32 chip_id)
{
u8 reset_gpios;
- struct bnx2x_phy phy;
- u32 shmem_base, shmem2_base, cnt;
- s8 port = 0;
- u16 val;
-
reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
udelay(10);
bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
reset_gpios);
- for (port = PORT_MAX - 1; port >= PORT_0; port--) {
- /* This PHY is for E2 and E3. */
- shmem_base = shmem_base_path[port];
- shmem2_base = shmem2_base_path[port];
- /* Extract the ext phy address for the port */
- if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
- 0, &phy) !=
- 0) {
- DP(NETIF_MSG_LINK, "populate_phy failed\n");
- return -EINVAL;
- }
+ return 0;
+}
- /* Wait for FW completing its initialization. */
- for (cnt = 0; cnt < 1000; cnt++) {
- bnx2x_cl45_read(bp, &phy,
+static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
+ struct bnx2x_phy *phy)
+{
+ u16 val, cnt;
+ /* Wait for FW completing its initialization. */
+ for (cnt = 0; cnt < 1500; cnt++) {
+ bnx2x_cl45_read(bp, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_CTRL, &val);
- if (!(val & (1<<15)))
- break;
- msleep(1);
- }
- if (cnt >= 1000)
- DP(NETIF_MSG_LINK,
- "84833 Cmn reset timeout (%d)\n", port);
-
- /* Put the port in super isolate mode. */
- bnx2x_cl45_read(bp, &phy,
- MDIO_CTL_DEVAD,
- MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
- val |= MDIO_84833_SUPER_ISOLATE;
- bnx2x_cl45_write(bp, &phy,
- MDIO_CTL_DEVAD,
- MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
+ if (!(val & (1<<15)))
+ break;
+ msleep(1);
+ }
+ if (cnt >= 1500) {
+ DP(NETIF_MSG_LINK, "84833 reset timeout\n");
+ return -EINVAL;
}
+ /* Put the port in super isolate mode. */
+ bnx2x_cl45_read(bp, phy,
+ MDIO_CTL_DEVAD,
+ MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
+ val |= MDIO_84833_SUPER_ISOLATE;
+ bnx2x_cl45_write(bp, phy,
+ MDIO_CTL_DEVAD,
+ MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
+
+ /* Save spirom version */
+ bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
return 0;
}
+int bnx2x_pre_init_phy(struct bnx2x *bp,
+ u32 shmem_base,
+ u32 shmem2_base,
+ u32 chip_id)
+{
+ int rc = 0;
+ struct bnx2x_phy phy;
+ bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
+ if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
+ PORT_0, &phy)) {
+ DP(NETIF_MSG_LINK, "populate_phy failed\n");
+ return -EINVAL;
+ }
+ switch (phy.type) {
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
+ rc = bnx2x_84833_pre_init_phy(bp, &phy);
+ break;
+ default:
+ break;
+ }
+ return rc;
+}
static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
u32 shmem2_base_path[], u8 phy_index,
--
1.7.7.1
^ permalink raw reply related
* Re: intel_idle causing 3.0.8 system reboot
From: Len Brown @ 2012-01-17 10:34 UTC (permalink / raw)
To: Arkadiusz Miśkiewicz; +Cc: linux-kernel, linux-pm, Suresh Siddha
In-Reply-To: <201111130854.56201.a.miskiewicz@gmail.com>
On 11/13/2011 02:54 AM, Arkadiusz Miśkiewicz wrote:
> On Sunday 13 of November 2011, Len Brown wrote:
>>> intel_idle.max_cstate=2 also makes the problem go away.
>>
>> Is the system running with BIOS SETUP defaults?
>
> Tried also with "safe defaults (F8)" but that didn't help.
>
>> Are there any BIOS SETUP options related to CPU idle states?
>
> Yes, there are
>
> "C state package limit setting" with values possible: Auto, C1, C3, C6, C7
> (set to "Auto" here)
> "Intel EIST technology" -> Enabled
> "C1E support" -> Enabled
> "Intel C-STATE tech" -> Enabled
> "C1 Auto Demotion" -> Enabled
> "C3 Auto Demotion" -> Enabled
>
>> please boot with intel_idle.max_cstate=0
>> and send the output of these two commands:
>>
>> dmesg |grep idle
>> grep . /sys/devices/system/cpu/cpu0/cpuidle/*/*
>
> [root@berta ~]# dmesg |grep idle
> [ 0.000000] Command line: auto BOOT_IMAGE=pld3.0.8test ro root=812
> console=tty0 console=ttyS2,38400n81 panic=60 selinux=0 intel_idle.max_cstate=0
> [ 0.000000] Kernel command line: auto BOOT_IMAGE=pld3.0.8test ro root=812
> console=tty0 console=ttyS2,38400n81 panic=60 selinux=0 intel_idle.max_cstate=0
> [ 0.000000] RCU dyntick-idle grace-period acceleration is enabled.
> [ 0.278494] using mwait in idle threads.
> [ 4.330321] intel_idle: disabled
> [ 5.794456] cpuidle: using governor ladder
> [ 5.806755] cpuidle: using governor menu
> [root@berta ~]# LC_ALL=C grep . /sys/devices/system/cpu/cpu0/cpuidle/*/*
> grep: /sys/devices/system/cpu/cpu0/cpuidle/*/*: No such file or directory
>
> There are only:
> [root@berta ~]# LC_ALL=C grep . /sys/devices/system/cpu/cpuidle/*
> /sys/devices/system/cpu/cpuidle/current_driver:none
> /sys/devices/system/cpu/cpuidle/current_governor_ro:menu
very strange.
now that it is back up...
Please file a bug report at bugzilla.kernel.org against idle/intel_idle
and assign it to me.
Please attach the complete output from dmesg -s 64000
and attach your .config
It appears that you have no acpi_idle driver installed.
If your kernel is missing
CONFIG_ACPI_PROCESSOR=y
please add it and collect the info above.
thanks,
-Len
>>
>> thanks,
>> Len Brown, Intel Open Source Technology Center
>>
>>>> # cat /proc/cpuinfo
>>>> processor : 0
>>>> vendor_id : GenuineIntel
>>>> cpu family : 6
>>>> model : 30
>>>> model name : Intel(R) Xeon(R) CPU X3430 @ 2.40GHz
>>>> stepping : 5
>
>
^ permalink raw reply
* Re: [PATCH v4] drivers: i915: Default backlight PWM frequency
From: Daniel Vetter @ 2012-01-17 10:34 UTC (permalink / raw)
To: Takashi Iwai; +Cc: intel-gfx, olofj, snanda, Simon Que
In-Reply-To: <s5hipml6x41.wl%tiwai@suse.de>
On Tue, Nov 15, 2011 at 07:47:58PM +0100, Takashi Iwai wrote:
> At Fri, 11 Nov 2011 14:12:58 -0800,
> Simon Que wrote:
> >
> > If the firmware did not initialize the backlight PWM registers, set up a
> > default PWM frequency of 200 Hz. This is determined using the following
> > formula:
> >
> > freq = refclk / (128 * pwm_max)
> >
> > The PWM register allows the max PWM value to be set. So we want to use
> > the formula, where freq = 200:
> >
> > pwm_max = refclk / (128 * freq)
> >
> > This patch will, in the case of missing PWM register initialization
> > values, look for the reference clock frequency. Based on that, it sets
> > an appropriate max PWM value for a frequency of 200 Hz.
> >
> > If no refclk frequency is found, the max PWM will be zero, which results
> > in no change to the PWM registers.
> >
> > Signed-off-by: Simon Que <sque@chromium.org>
> > ---
> > drivers/gpu/drm/i915/intel_panel.c | 38 ++++++++++++++++++++++++++++++-----
> > 1 files changed, 32 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> > index f15388c..dda5de2 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -32,6 +32,12 @@
> >
> > #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
> >
> > +/* These are used to calculate a reasonable default when firmware has not
> > + * configured a maximum PWM frequency, with 200Hz as the current default target.
> > + */
> > +#define DEFAULT_BACKLIGHT_PWM_FREQ 200
> > +#define BACKLIGHT_REFCLK_DIVISOR 128
> > +
> > void
> > intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
> > struct drm_display_mode *adjusted_mode)
> > @@ -129,12 +135,32 @@ static int is_backlight_combination_mode(struct drm_device *dev)
> > return 0;
> > }
> >
> > +static void i915_set_default_max_backlight(struct drm_i915_private *dev_priv)
> > +{
> > + u32 refclk_freq_mhz = 0;
> > + u32 max_pwm;
> > +
> > + if (HAS_PCH_SPLIT(dev_priv->dev))
> > + refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
> > + else if (dev_priv->lvds_use_ssc)
> > + refclk_freq_mhz = dev_priv->lvds_ssc_freq;
> > +
> > + max_pwm = refclk_freq_mhz * 1000000 /
> > + (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
> > +
> > + if (HAS_PCH_SPLIT(dev_priv->dev))
> > + dev_priv->saveBLC_PWM_CTL2 = max_pwm << 16;
> > + else if (IS_PINEVIEW(dev_priv->dev))
> > + dev_priv->saveBLC_PWM_CTL = max_pwm << 17;
> > + else
> > + dev_priv->saveBLC_PWM_CTL = max_pwm << 16;
>
> Is the pineview case really correct?
> The special handling for pineview in some places in intel_panel.c is
> just for omitting the bit 0, IIRC. It doesn't mean that the value is
> twice larger.
>
> BTW, this handling of bit 0 seems necessary not only for pineview but
> for the older chips (gen < 4) in general, too, as being discussed in
> another thread of LKML. 915GM hits the with problem of bit-0, for
> example.
Do we still need this patch? If so, can you please address Takashi's
comment, on a quick check he seems to have a point.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply
* Re: [PATCH 1/2] PM / devfreq: add min/max_freq limit requested by users.
From: MyungJoo Ham @ 2012-01-17 10:32 UTC (permalink / raw)
To: markgross
Cc: Turquette, Mike, linux-kernel, Linux PM list, Kyungmin Park,
Rafael J. Wysocki, Kevin Hilman
In-Reply-To: <20120113044757.GB6004@mgross-G62>
On Fri, Jan 13, 2012 at 1:47 PM, mark gross <markgross@thegnar.org> wrote:
> On Thu, Jan 12, 2012 at 11:08:44AM +0900, MyungJoo Ham wrote:
>>
>> In practice, we have been using min/max to test DVFS behaviors and its
>> side effects. And we are going to use them to 1. restrict power
>> consumption forcibly by the platform software if it is too hot or the
>> battery is low, and to 2. guarantee the minimum performance for
>> specific tasks controlled by the platform software.
>>
>> Anyway, the reason 2 could be tackled by pm-qos if we allow more
>> options in pm-qos with 1. pm qos type to enforce DVFS response time.
> what would pm_qos do with DVFS response time? What power management
> knob would it enable a constraint for?
>
> pm_qos doesn't do anything but enable power throttling code to consider
> a constraint on how far to throttle "something". pm_qos has no
> enforcement power.
- The control knob: polling interval of ondemand-like DVFS mechanisms
- It's ok to have no enforcement power. The DVFS mechanism only needs
an interface (PM QoS seems fine for this) from user space / device
drivers to get the response-time requirement.
With some events, we need to adjust DVFS polling interval.
For now, we do this in our devices for user input events (key input,
touchscreen input, ...). And some peripheral device drivers want to
get "guaranteed response time" depending on their operational modes
from memory and bus at the start of their operations.
With user input events, user may (doing something heavy) or may not
(doing something light) want fast reaction from CPU/MEM/GPU/... in
many occasions, and we cannot determine it until the DVFS polling has
been done.
In average, with near 100% threshold, ondemand-like governors will
take 1.5 x polling interval to response. In a system with 100ms
polling interval, DVFS mechanism will take usuallly 150ms (and up to
200ms) to react and this is significantly noticable to human users.
With 60Hz display system, this is loss of almost 10 frames.
In order to address this, a touch event handler (or any
thread/callback or anything deals with it) may request QoS with an
incoming event to reduce polling interval temporarily.
Although PM-QoS does not have the QoS Type for this kind of metric;
however, DVFS response time seems to be another QoS metric candidate.
>
>> 2. pm qos type to enforce graphics performance. And adding a duration
>> option to pm-qos requests will be helpful (sort of a helper function):
>> i.e., pm_qos_timed_request(struct pm_qos_request *req, int
>> pm_qos_class, s32 value, unsigned long duration_ms);
>
> What would be good units for graphics throughput?
> Where in the graphics driver would you insert the equivalent of cpufreq?
> to control the GPU core frequency?
I've not thought about this much yet. I've just seen the need for QoS
requirements from GPU people because DVFS mechanism loses a frame or
frames often during GPU usage without QoS information.
I'm not so familiar with GPUs, so I can't be sure about the metric for
graphics throughput. However, could it be "FLOPS", "triangles per
second", or GPU clock speed?
We have GPU DVFS drivers in linux/drivers/media/video/..., which
controls GPU core frequency and measures GPU usage. However, they can
be implemented with devfreq framework and move into drivers/devfreq/
later.
Cheers!
MyungJoo.
--
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics
^ permalink raw reply
* Re: [PATCH v9 3.2 7/9] tracing: uprobes trace_event interface
From: Srikar Dronamraju @ 2012-01-17 10:22 UTC (permalink / raw)
To: Ingo Molnar
Cc: Jiri Olsa, Arnaldo Carvalho de Melo, Peter Zijlstra,
Linus Torvalds, Oleg Nesterov, Andrew Morton, LKML, Linux-mm,
Andi Kleen, Christoph Hellwig, Steven Rostedt, Roland McGrath,
Thomas Gleixner, Masami Hiramatsu, Arnaldo Carvalho de Melo,
Anton Arapov, Ananth N Mavinakayanahalli, Jim Keniston,
Stephen Rothwell
In-Reply-To: <20120117092838.GB10397@elte.hu>
> >
> > and commands like:
> > perf record -a -e probe_libc:free --filter "common_pid == 1127"
> > perf record -e probe_libc:free --filter "arg1 == 0xa" ls
> >
> > got me proper results.
>
> Btw., Srikar, if that's the primary UI today then we'll need to
> make it a *lot* more user-friendly than the above usage
> workflow.
>
> In particular this line:
>
> > echo "p:probe_libc/free /lib64/libc-2.13.so:0x7a4f0 %ax" > ./uprobe_events
>
> is not something a mere mortal will be able to figure out.
Agree, perf probe is the primary interface to use uprobes.
>
> There needs to be perf probe integration, that allows intuitive
> usage, such as:
>
> perf probe add libc:free
Current usage is like perf probe -x <executable> -a <func1> -a <func2>
So we could use
perf probe -x /lib64/libc.so.6 free
or
perf probe -x /lib64/libc.so.6 -a free -a malloc -a strcpy
The -x option helps perf to identify that its a user space based probing.
This currently restricts that all probes defined per "perf probe"
invocation to just one executable. This usage was suggested by Masami.
Earlier we used perf probe free@/lib/libc.so.6 malloc@/lib/libc.so.6
The objection for this was that perf was already using @ to signify
source file. Similarly : is already used for Relative line number.
This also goes with perf probe -F -x /lib64/libc.so to list the
available probes in libc.
>
> Using the perf symbols code it should first search a libc*so DSO
> in the system, finding say /lib64/libc-2.15.so. The 'free'
> symbol is readily available there:
While I understand the ease of using a libc instead of the full path, I
think it does have few issues.
- Do we need to keep checking if the new files created in the system
match the pattern and if they match the pattern, dynamically add the
files?
- Also the current model helps if the user wants to restrict his trace
to particular executable where there are more that one executable with
the same name.
>
> aldebaran:~> eu-readelf -s /lib64/libc-2.15.so | grep ' free$'
> 7186: 00000039ff47f080 224 FUNC GLOBAL DEFAULT 12 free
>
> then the tool can automatically turn that symbol information
> into the specific probe.
>
Given a function in an executable, we are
> Will it all work with DSO randomization, prelinking and default
> placement as well?
Works with DSO randomization, I havent tried with prelinking. did you
mean http://en.wikipedia.org/wiki/Placement_syntax#Default_placement
when you said default placement?
>
> Users should not be expected to enter magic hexa numbers to get
> a trivial usecase going ...
yes, that why we dont allow perf probe -x /lib/libc.so.6 0x1234
>
> this bit:
>
> > perf record -a -e probe_libc:free --filter "common_pid == 1127"
> > perf record -e probe_libc:free --filter "arg1 == 0xa" ls
>
> looks good and intuitive and 'perf list' should list all the
> available uprobes.
Currently "perf probe -F -x /bin/zsh" lists all available functions in
zsh. perf probe --list has been enhanced to show uprobes that are
already registered.
Similar to kprobes based probes, available user space probes are not
part of "perf list".
>
> Thanks,
>
> Ingo
>
^ permalink raw reply
* Re: [PATCH v9 3.2 7/9] tracing: uprobes trace_event interface
From: Srikar Dronamraju @ 2012-01-17 10:22 UTC (permalink / raw)
To: Ingo Molnar
Cc: Jiri Olsa, Arnaldo Carvalho de Melo, Peter Zijlstra,
Linus Torvalds, Oleg Nesterov, Andrew Morton, LKML, Linux-mm,
Andi Kleen, Christoph Hellwig, Steven Rostedt, Roland McGrath,
Thomas Gleixner, Masami Hiramatsu, Arnaldo Carvalho de Melo,
Anton Arapov, Ananth N Mavinakayanahalli, Jim Keniston,
Stephen Rothwell
In-Reply-To: <20120117092838.GB10397@elte.hu>
> >
> > and commands like:
> > perf record -a -e probe_libc:free --filter "common_pid == 1127"
> > perf record -e probe_libc:free --filter "arg1 == 0xa" ls
> >
> > got me proper results.
>
> Btw., Srikar, if that's the primary UI today then we'll need to
> make it a *lot* more user-friendly than the above usage
> workflow.
>
> In particular this line:
>
> > echo "p:probe_libc/free /lib64/libc-2.13.so:0x7a4f0 %ax" > ./uprobe_events
>
> is not something a mere mortal will be able to figure out.
Agree, perf probe is the primary interface to use uprobes.
>
> There needs to be perf probe integration, that allows intuitive
> usage, such as:
>
> perf probe add libc:free
Current usage is like perf probe -x <executable> -a <func1> -a <func2>
So we could use
perf probe -x /lib64/libc.so.6 free
or
perf probe -x /lib64/libc.so.6 -a free -a malloc -a strcpy
The -x option helps perf to identify that its a user space based probing.
This currently restricts that all probes defined per "perf probe"
invocation to just one executable. This usage was suggested by Masami.
Earlier we used perf probe free@/lib/libc.so.6 malloc@/lib/libc.so.6
The objection for this was that perf was already using @ to signify
source file. Similarly : is already used for Relative line number.
This also goes with perf probe -F -x /lib64/libc.so to list the
available probes in libc.
>
> Using the perf symbols code it should first search a libc*so DSO
> in the system, finding say /lib64/libc-2.15.so. The 'free'
> symbol is readily available there:
While I understand the ease of using a libc instead of the full path, I
think it does have few issues.
- Do we need to keep checking if the new files created in the system
match the pattern and if they match the pattern, dynamically add the
files?
- Also the current model helps if the user wants to restrict his trace
to particular executable where there are more that one executable with
the same name.
>
> aldebaran:~> eu-readelf -s /lib64/libc-2.15.so | grep ' free$'
> 7186: 00000039ff47f080 224 FUNC GLOBAL DEFAULT 12 free
>
> then the tool can automatically turn that symbol information
> into the specific probe.
>
Given a function in an executable, we are
> Will it all work with DSO randomization, prelinking and default
> placement as well?
Works with DSO randomization, I havent tried with prelinking. did you
mean http://en.wikipedia.org/wiki/Placement_syntax#Default_placement
when you said default placement?
>
> Users should not be expected to enter magic hexa numbers to get
> a trivial usecase going ...
yes, that why we dont allow perf probe -x /lib/libc.so.6 0x1234
>
> this bit:
>
> > perf record -a -e probe_libc:free --filter "common_pid == 1127"
> > perf record -e probe_libc:free --filter "arg1 == 0xa" ls
>
> looks good and intuitive and 'perf list' should list all the
> available uprobes.
Currently "perf probe -F -x /bin/zsh" lists all available functions in
zsh. perf probe --list has been enhanced to show uprobes that are
already registered.
Similar to kprobes based probes, available user space probes are not
part of "perf list".
>
> Thanks,
>
> Ingo
>
--
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see: http://www.linux-mm.org/ .
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Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a>
^ permalink raw reply
* [PATCH 1/2] mach-ux500: cache operations are atomic on PL310
From: Will Deacon @ 2012-01-17 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120117062224.GA26832@bnru02>
Hi Srinidhi,
On Tue, Jan 17, 2012 at 06:22:26AM +0000, Srinidhi KASAGAR wrote:
> On Mon, Jan 16, 2012 at 15:50:08 +0100, Will Deacon wrote:
> > The lock needs to stay. Besides, the problem isn't with inv_all, the problem
> > is with not being able to disable the outer cache. So can't you just do
> > something nasty like:
> >
> > outer_cache.disable = NULL;
> >
> > after your call to l2x0_init?
>
> hmm..patch below
Thanks. Comments inline.
> >
> > Also, if you can't disable the L2 from non-secure, does that mean that you
> > boot Linux with the L2 enabled?
>
> Yes, we boot with L2 enabled.
Interesting. I'm surprised you don't have problems with stale data on the
D-side after the decompressor. Maybe you're lucky with the mappings being no
write allocate.
> From 46fdbda7d2d9a9f4df0933341bcc467b3bdd03d6 Mon Sep 17 00:00:00 2001
> From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
> Date: Tue, 17 Jan 2012 11:29:39 +0530
> Subject: [PATCH] mach-ux500: Do not override outer.inv_all
>
> outer.inv_all is currently being used only in kexec path.
> Invalidating outer cache without disabling it is a big
> nono, and so, remove the machine specific outer.inv_all
> assuming that kexec does not call inv_all in its path.
Please change this comment. Kexec doesn't do this anymore.
> And at the same time it does not prevent us overriding
> outer.disable as we do not have any such secure SMI to
> handle the same while kexec disables the outer cache.
>
> Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
> ---
> arch/arm/mach-ux500/cache-l2x0.c | 48 +++++--------------------------------
> 1 files changed, 7 insertions(+), 41 deletions(-)
>
> diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
> index 122ddde..45111c8 100644
> --- a/arch/arm/mach-ux500/cache-l2x0.c
> +++ b/arch/arm/mach-ux500/cache-l2x0.c
> @@ -12,44 +12,6 @@
>
> static void __iomem *l2x0_base;
>
> -static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
> -{
> - /* wait for the operation to complete */
> - while (readl_relaxed(reg) & mask)
> - cpu_relax();
> -}
> -
> -static inline void ux500_cache_sync(void)
> -{
> - writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC);
> - ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1);
> -}
> -
> -/*
> - * The L2 cache cannot be turned off in the non-secure world.
> - * Dummy until a secure service is in place.
> - */
> -static void ux500_l2x0_disable(void)
> -{
> -}
> -
> -/*
> - * This is only called when doing a kexec, just after turning off the L2
> - * and L1 cache, and it is surrounded by a spinlock in the generic version.
> - * However, we're not really turning off the L2 cache right now and the
> - * PL310 does not support exclusive accesses (used to implement the spinlock).
> - * So, the invalidation needs to be done without the spinlock.
> - */
> -static void ux500_l2x0_inv_all(void)
> -{
> - uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
> -
> - /* invalidate all ways */
> - writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
> - ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
> - ux500_cache_sync();
> -}
> -
> static int __init ux500_l2x0_unlock(void)
> {
> int i;
> @@ -85,9 +47,13 @@ static int __init ux500_l2x0_init(void)
> /* 64KB way size, 8 way associativity, force WA */
> l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
>
> - /* Override invalidate function */
> - outer_cache.disable = ux500_l2x0_disable;
> - outer_cache.inv_all = ux500_l2x0_inv_all;
> + /*
> + * We can't disable l2 as we are in non secure mode, currently
> + * this seems being called only during kexec path. So let's
> + * override outer.disable with nasty assignment until we have
> + * some SMI service available.
> + */
> + outer_cache.disable = NULL;
Much better!
Cheers,
Will
^ permalink raw reply
* [PATCH] amba-pl011: do not disable RTS during shutdown
From: Shreshtha Kumar SAHU @ 2012-01-17 10:29 UTC (permalink / raw)
To: gregkh, linux-serial, rmk+kernel; +Cc: linux-kernel, Shreshtha Kumar Sahu
From: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
In present driver, shutdown clears RTS in CR register. But the
documentation "Documentation/serial/driver" suggests not to
disable RTS in shutdown(). Also RTS is preserved between shutdown
and startup calls, i.e. it is restored in startup if it was enabled
during shutdown. So that if autorts is set and RTS is set using
pl011_set_mctrl then it should continue even after shutdown->startup
sequence. And hence during set_termios it will enable RTS only if RTS
bit is set in UARTx_CR register. For throttling/unthrottling user
should call pl011_set_mctrl.
Change-Id: I743f33fb10e7e655657cd5dae1ec585e914a65bc
Signed-off-by: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/tty/serial/amba-pl011.c | 17 ++++++++++++++++-
1 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 6958594..46a4690 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -160,6 +160,7 @@ struct uart_amba_port {
unsigned int lcrh_tx; /* vendor-specific */
unsigned int lcrh_rx; /* vendor-specific */
bool autorts;
+ bool rts_state; /* state during shutdown */
char type[12];
bool interrupt_may_hang; /* vendor-specific */
#ifdef CONFIG_DMA_ENGINE
@@ -1412,6 +1413,8 @@ static int pl011_startup(struct uart_port *port)
barrier();
cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
+ if (uap->rts_state)
+ cr |= UART011_CR_RTS;
writew(cr, uap->port.membase + UART011_CR);
/* Clear pending error interrupts */
@@ -1469,6 +1472,7 @@ static void pl011_shutdown_channel(struct uart_amba_port *uap,
static void pl011_shutdown(struct uart_port *port)
{
struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int cr;
/*
* disable all interrupts
@@ -1488,9 +1492,19 @@ static void pl011_shutdown(struct uart_port *port)
/*
* disable the port
+ * disable the port. It should not disable RTS.
+ * Also RTS state should be preserved to restore
+ * it during startup().
*/
uap->autorts = false;
- writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
+ cr = readw(uap->port.membase + UART011_CR);
+ if (cr & UART011_CR_RTS) {
+ uap->rts_state = true;
+ cr = UART011_CR_RTS;
+ } else
+ uap->rts_state = false;
+ cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
+ writew(cr, uap->port.membase + UART011_CR);
/*
* disable break condition and fifos
@@ -1905,6 +1919,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
uap->vendor = vendor;
uap->lcrh_rx = vendor->lcrh_rx;
uap->lcrh_tx = vendor->lcrh_tx;
+ uap->rts_state = false;
uap->fifosize = vendor->fifosize;
uap->interrupt_may_hang = vendor->interrupt_may_hang;
uap->port.dev = &dev->dev;
--
1.7.4.3
^ permalink raw reply related
* [PATCH] amba-pl011: do not disable RTS during shutdown
From: Shreshtha Kumar SAHU @ 2012-01-17 10:29 UTC (permalink / raw)
To: gregkh, linux-serial, rmk+kernel; +Cc: linux-kernel, Shreshtha Kumar Sahu
From: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
In present driver, shutdown clears RTS in CR register. But the
documentation "Documentation/serial/driver" suggests not to
disable RTS in shutdown(). Also RTS is preserved between shutdown
and startup calls, i.e. it is restored in startup if it was enabled
during shutdown. So that if autorts is set and RTS is set using
pl011_set_mctrl then it should continue even after shutdown->startup
sequence. And hence during set_termios it will enable RTS only if RTS
bit is set in UARTx_CR register. For throttling/unthrottling user
should call pl011_set_mctrl.
Change-Id: I743f33fb10e7e655657cd5dae1ec585e914a65bc
Signed-off-by: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/tty/serial/amba-pl011.c | 17 ++++++++++++++++-
1 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 6958594..46a4690 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -160,6 +160,7 @@ struct uart_amba_port {
unsigned int lcrh_tx; /* vendor-specific */
unsigned int lcrh_rx; /* vendor-specific */
bool autorts;
+ bool rts_state; /* state during shutdown */
char type[12];
bool interrupt_may_hang; /* vendor-specific */
#ifdef CONFIG_DMA_ENGINE
@@ -1412,6 +1413,8 @@ static int pl011_startup(struct uart_port *port)
barrier();
cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
+ if (uap->rts_state)
+ cr |= UART011_CR_RTS;
writew(cr, uap->port.membase + UART011_CR);
/* Clear pending error interrupts */
@@ -1469,6 +1472,7 @@ static void pl011_shutdown_channel(struct uart_amba_port *uap,
static void pl011_shutdown(struct uart_port *port)
{
struct uart_amba_port *uap = (struct uart_amba_port *)port;
+ unsigned int cr;
/*
* disable all interrupts
@@ -1488,9 +1492,19 @@ static void pl011_shutdown(struct uart_port *port)
/*
* disable the port
+ * disable the port. It should not disable RTS.
+ * Also RTS state should be preserved to restore
+ * it during startup().
*/
uap->autorts = false;
- writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
+ cr = readw(uap->port.membase + UART011_CR);
+ if (cr & UART011_CR_RTS) {
+ uap->rts_state = true;
+ cr = UART011_CR_RTS;
+ } else
+ uap->rts_state = false;
+ cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
+ writew(cr, uap->port.membase + UART011_CR);
/*
* disable break condition and fifos
@@ -1905,6 +1919,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
uap->vendor = vendor;
uap->lcrh_rx = vendor->lcrh_rx;
uap->lcrh_tx = vendor->lcrh_tx;
+ uap->rts_state = false;
uap->fifosize = vendor->fifosize;
uap->interrupt_may_hang = vendor->interrupt_may_hang;
uap->port.dev = &dev->dev;
--
1.7.4.3
^ permalink raw reply related
* Re: [PATCH 5/5] usb-926x: add dfu mem options support
From: Sascha Hauer @ 2012-01-17 10:29 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
In-Reply-To: <1326621621-11484-5-git-send-email-plagnioj@jcrosoft.com>
On Sun, Jan 15, 2012 at 11:00:21AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> this will allow to upload a bootable image in memory and boot it
> boot with the rootfs via nfs
>
> the image will must be 16MiB max
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/boards/usb-a926x/env/bin/init_board | 10 +++++++++-
> arch/arm/configs/usb_a9260_defconfig | 1 +
> arch/arm/configs/usb_a9263_128mib_defconfig | 1 +
> arch/arm/configs/usb_a9263_defconfig | 1 +
> arch/arm/configs/usb_a9g20_128mib_defconfig | 1 +
> arch/arm/configs/usb_a9g20_defconfig | 1 +
> 6 files changed, 14 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boards/usb-a926x/env/bin/init_board b/arch/arm/boards/usb-a926x/env/bin/init_board
> index 0a6baf7..4c906f0 100644
> --- a/arch/arm/boards/usb-a926x/env/bin/init_board
> +++ b/arch/arm/boards/usb-a926x/env/bin/init_board
> @@ -6,7 +6,7 @@ button_wait=5
> product_id=0x1234
> vendor_id=0x4321
>
> -dfu_config="/dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.rootfs.bb(rootfs)r"
> +dfu_config="/dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.rootfs.bb(rootfs)r,/dev/ram0.kernel(mem)r"
I really want to discourage usage of /dev/ram0 for 'official' use. Can't
you use a regular file instead? From what I see only the O_CREAT flag is
missing in the dfu driver.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* [PATCH 2/2] pango: create /etc/pango in module postinsts if it's missing
From: Koen Kooi @ 2012-01-17 10:19 UTC (permalink / raw)
To: openembedded-core; +Cc: Koen Kooi
In-Reply-To: <1326795583-22661-1-git-send-email-koen@dominion.thruhere.net>
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
---
meta/recipes-graphics/pango/pango.inc | 3 +++
meta/recipes-graphics/pango/pango_1.28.4.bb | 2 +-
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/meta/recipes-graphics/pango/pango.inc b/meta/recipes-graphics/pango/pango.inc
index bf528f4..ce8b6ba 100644
--- a/meta/recipes-graphics/pango/pango.inc
+++ b/meta/recipes-graphics/pango/pango.inc
@@ -44,6 +44,9 @@ if [ "x$D" != "x" ]; then
exit 1
fi
+if ! [ -e $D${sysconfdir}/pango ] ; then
+ mkdir -p $D${sysconfdir}/pango
+fi
}
python populate_packages_prepend () {
diff --git a/meta/recipes-graphics/pango/pango_1.28.4.bb b/meta/recipes-graphics/pango/pango_1.28.4.bb
index 5778c3f..9681f9e 100644
--- a/meta/recipes-graphics/pango/pango_1.28.4.bb
+++ b/meta/recipes-graphics/pango/pango_1.28.4.bb
@@ -2,7 +2,7 @@ require pango.inc
LIC_FILES_CHKSUM = "file://COPYING;md5=3bf50002aefd002f49e7bb854063f7e7"
-PR = "r5"
+PR = "r6"
SRC_URI += "file://no-tests.patch"
SRC_URI += "file://noconst.patch"
--
1.7.2.5
^ permalink raw reply related
* Re: [PATCH 2/3] drm: add CRTC properties
From: Daniel Vetter @ 2012-01-17 10:27 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: dri-devel
In-Reply-To: <CA+gsUGShCbtGg4-4ScPcRxP30XjpPie8PP0_yd31LHLmnD3ANw@mail.gmail.com>
On Mon, Jan 16, 2012 at 06:29:36PM -0200, Paulo Zanoni wrote:
> Three comments about the design are inline:
>
> > +void drm_crtc_attach_property(struct drm_crtc *crtc,
> > + struct drm_property *property, uint64_t init_val)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> > + if (crtc->property_ids[i] == 0) {
> > + crtc->property_ids[i] = property->base.id;
> > + crtc->property_values[i] = init_val;
> > + return;
> > + }
> > + }
> > + BUG_ON(1);
>
> I looked at drm_connector_attach_property and saw that instead of
> BUG_ON(1), it tries to return -EINVAL. The problem is that only zero
> callers check for the return value of drm_connector_attach_property. I
> can provide a patch for drm_connector_attach_property changing the
> -EINVAL for BUG_ON(1) if no one objects. Or I can also add -EINVAL to
> drm_crtc_attach_property and, to be consistent, not check for it :)
Just a quick comment: WARN is generally highly preferred over BUG. Use the
latter only when you know that the kernel _will_ go down in a horribly way
and it's better to stop it doing so (e.g. for NULL pointer checks).
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply
* [PATCH 1/2] Revert "pango.inc: add directory "/etc/pango""
From: Koen Kooi @ 2012-01-17 10:19 UTC (permalink / raw)
To: openembedded-core; +Cc: Koen Kooi
This reverts commit 65186bd86170d8c375931a18487c2fdf3bd1b3b0.
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
---
meta/recipes-graphics/pango/pango.inc | 6 +-----
1 files changed, 1 insertions(+), 5 deletions(-)
diff --git a/meta/recipes-graphics/pango/pango.inc b/meta/recipes-graphics/pango/pango.inc
index e7262c3..bf528f4 100644
--- a/meta/recipes-graphics/pango/pango.inc
+++ b/meta/recipes-graphics/pango/pango.inc
@@ -46,11 +46,6 @@ fi
}
-# Command "pango-querymodules > /etc/pango/pango.modules" needs this directory.
-do_install_prepend() {
- install -d ${D}/${sysconfdir}/pango
-}
-
python populate_packages_prepend () {
prologue = d.getVar("postinst_prologue", 1)
@@ -59,5 +54,6 @@ python populate_packages_prepend () {
do_split_packages(d, modules_root, '^pango-(.*)\.so$', 'pango-module-%s', 'Pango module %s', prologue + 'pango-querymodules > /etc/pango/pango.modules')
}
+FILES_${PN} = "/etc/pango/* ${bindir}/* ${libdir}/libpango*${SOLIBS}"
FILES_${PN}-dbg += "${libdir}/pango/${LIBV}/modules/.debug"
FILES_${PN}-dev += "${libdir}/pango/${LIBV}/modules/*.la"
--
1.7.2.5
^ permalink raw reply related
* Re: IB/iSER problems with Linux 3.0
From: Sebastian Riemer @ 2012-01-17 10:26 UTC (permalink / raw)
To: Or Gerlitz; +Cc: linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAJZOPZL=bV4SjdD2eakX9MhOhw=91xzCK=BEkirhRQd8oPA6bg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 16/01/12 22:16, Or Gerlitz wrote:
> Sebastian, I asked for the **iser** (ib_iser) and not mlx4_core debug_level=2
>
Yes, I did! I've enabled that additionally. And I've checked these
settings in /sys/module/*/parameters. They were set. The libiscsi from
OFED had only the option "debug_libiscsi" but this was too verbose, so
this was the only thing I didn't activate there.
> 1. yes, the logs (correct ones, please!) from success login on the
> very same kernel would help
>
Yes, I've sent you the correct logs. The only difference is:
1. in-tree vs. ofa-kernel-modules from OFED-1.5.4
2. open-iscsi 2.0.872 vs. open-iscsi 2.0.869 from OFED
In the log from working iSER there is the RDMA mapping debug message at
the position of the error in the other log.
Cheers,
Sebastian
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply
* [U-Boot] [PATCH] arm: Add Prep subcommand support to bootm
From: Stefano Babic @ 2012-01-17 10:26 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1326701555-2501-1-git-send-email-simonschwarzcor@gmail.com>
On 16/01/2012 09:12, Simon Schwarz wrote:
> From: Simon Schwarz <simonschwarzcor@googlemail.com>
>
> Adds prep subcommand to bootm implementation of ARM. When bootm is called
> with the subcommand prep the function stops right after ATAGS creation and
> before announce_and_cleanup.
>
> This is used in command "cmd_spl export"
>
> Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply
* Re: [Qemu-devel] [PATCH] qxl: Slot sanity check in qxl_phys2virt() is off by one, fix
From: Markus Armbruster @ 2012-01-17 9:08 UTC (permalink / raw)
To: qemu-devel; +Cc: kraxel
In-Reply-To: <1320399264-28581-1-git-send-email-armbru@redhat.com>
Ping?
Markus Armbruster <armbru@redhat.com> writes:
> Spotted by Coverity.
>
> Signed-off-by: Markus Armbruster <armbru@redhat.com>
> ---
> hw/qxl.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/qxl.c b/hw/qxl.c
> index 84ffd45..c97bebe 100644
> --- a/hw/qxl.c
> +++ b/hw/qxl.c
> @@ -1006,7 +1006,7 @@ void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
> case MEMSLOT_GROUP_HOST:
> return (void*)offset;
> case MEMSLOT_GROUP_GUEST:
> - PANIC_ON(slot > NUM_MEMSLOTS);
> + PANIC_ON(slot >= NUM_MEMSLOTS);
> PANIC_ON(!qxl->guest_slots[slot].active);
> PANIC_ON(offset < qxl->guest_slots[slot].delta);
> offset -= qxl->guest_slots[slot].delta;
^ permalink raw reply
* Re: [PATCH v3 0/6] NAND BBM + BBT updates
From: Angus CLARK @ 2012-01-17 10:22 UTC (permalink / raw)
To: dedekind1
Cc: Dan Carpenter, Kulikov Vasiliy, Sebastian Andrzej Siewior,
Nicolas Ferre, Dominik Brodowski, Adrian Hunter, Gabor Juhos,
linux-mtd, Jonas Gorski, Jamie Iles, Ivan Djelic, Robert Jarzmik,
David Woodhouse, Maxim Levitsky, Dmitry Eremin-Solenikov,
Kevin Cernekee, Barry Song, Jim Quinlan, Andres Salomon, Axel Lin,
Anatolij Gustschin, Mike Frysinger, Arnd Bergmann, Lei Wen,
Sascha Hauer, Artem Bityutskiy, Florian Fainelli, Peter Wippich,
Matthieu CASTET, Kyungmin Park, Shmulik Ladkani, Wolfram Sang,
Chuanxiao Dong, Joe Perches, Guillaume LECERF, Brian Norris,
Roman Tereshonkov
In-Reply-To: <1326320928.2338.37.camel@koala>
On 01/11/2012 10:28 PM, Artem Bityutskiy wrote:
> In my view, OOB BB markers is the primary, reliable, and simple
> mechanism. And BBT is just an additional optimization to speed up system
> startup.
This seems to be contrary to the advice given by the various NAND manufacturers
(with a quite unusual show of consensus!) Once a block has been deemed to have
gone bad, one cannot rely on *any* operations being successful, and that
includes writing a bad block marker to the OOB area. The recommended approach
has for some time been to use a Flash-resident bad block table, with an initial
scan for the manufacturer-programmed bad-block markers.
(Indeed, this issue was raised recently in a meeting with one of the major NAND
manufacturers, and the design enginner was horrified at the thought of relying
on the OOB for tracking worn blocks.)
The use of OOB BB markers certainly has some benefits (as already mentioned in
previous posts), and I like the idea of being able to use OOB markers in
conjunction with BBTs. However, IMHO, I believe the BBT should be regarded as
the primary source of information, especially when considering inconsistencies
between the OOB markers and the BBTs.
> 1. When we get erase error. Well, if SW erases a block, it does not care
> of the contents. This means that if after the reboot SW will re-try
> erasing it. And if the block is bad, and previously the erasure failed,
> it will fail again, and SW will mark it as bad again.
>
This raises another point. It is entirely possible that an erase operation will
succeed on a block where it previously failed. However, that does not mean to
say the block has now become good. On first erase failure, the block should be
considered bad and steps taken to ensure the block is not used.
In other words, we cannot rely on erase failures as a way of recovering bad
block status, although I accept in some circumstances, it is probably the best
we can do!
Cheers,
Angus
^ permalink raw reply
* [PATCH] mwl8k: Fixing Sparse ENDIAN CHECK warning
From: Yogesh Ashok Powar @ 2012-01-17 10:15 UTC (permalink / raw)
To: John W. Linville; +Cc: linux-wireless, Lennert Buytenhek
Fixing following sparse warning
>drivers/net/wireless/mwl8k.c:2780:15: warning: incorrect type in assignment (different base types)
>drivers/net/wireless/mwl8k.c:2780:15: expected restricted unsigned short [usertype] channel
>drivers/net/wireless/mwl8k.c:2780:15: got unsigned short [unsigned] [usertype] hw_value
Signed-off-by: Yogesh Ashok Powar <yogeshp@marvell.com>
---
drivers/net/wireless/mwl8k.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/wireless/mwl8k.c b/drivers/net/wireless/mwl8k.c
index 8ea7012..008f406 100644
--- a/drivers/net/wireless/mwl8k.c
+++ b/drivers/net/wireless/mwl8k.c
@@ -2777,7 +2777,7 @@ static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
else if (channel->band == IEEE80211_BAND_5GHZ)
cmd->band = cpu_to_le16(0x4);
- cmd->channel = channel->hw_value;
+ cmd->channel = cpu_to_le16(channel->hw_value);
if (conf->channel_type == NL80211_CHAN_NO_HT ||
conf->channel_type == NL80211_CHAN_HT20) {
--
1.7.5.4
^ permalink raw reply related
* Re: [PATCH 2/2] agent: allow agent to reply to RequestPinCode with bytes
From: Marcel Holtmann @ 2012-01-17 10:23 UTC (permalink / raw)
To: Scott James Remnant; +Cc: David Herrmann, linux-bluetooth
In-Reply-To: <CAHZ1yCmc0BNQ87+c9v2ZYpu47ANyB06XxN860O_A4qgNd+A9dA@mail.gmail.com>
Hi Scott,
> > > This thread doesn't give a rationale for why support for Binary PINs
> > > couldn't be added to BlueZ, just an alternate implementation in the
> > > case of the WiiMote.
> >
> > the BlueZ agent request is a direct question to the user. And the
> > question is meant to give something they can understand and something
> > they will also be entering on the other side.
> >
>
> Ok, so it'd be appropriate to write a plugin that handled, for
> example, sending 0000 to devices within a certain class?
as long as you know that it is correct PIN code. If it is not, then you
might end up in the funky case that you have to try again. Meaning
actually pair again. If the remote device lets you do this again without
pressing the magic buttons again.
> And for keyboard devices, would it be appropriate for the plugin to
> generate the PIN itself and send the DisplayPasskey method to the
> agent rather than the RequestPinCode? (This is a HID spec
> recommendation)
Something like that could be done, but you do wanna solve that part
inside the bluetoothd core somehow. Play a little bit with the timing
details on this idea. There might be a problem. You can easily run into
a LMP timeout if you supply the PIN code too fast.
> > > It's kinda difficult to do this in a plugin since each authentication
> > > request only gets one shot - it's easier (and far cleaner) in the
> > > agent, which can outlive each connection attempt and be used for both,
> > > keeping track of the PINs it's tried.
> >
> > I have to send you back to reading the Bluetooth specification for
> > Legacy Pairing when trying multiple pairing attempts. There is a
> > built-in security concept that will make this concept really
> > complicated.
> >
>
> I've read it through recently, and I don't recall anything that would
> prohibit retrying the link request again.
The is a backoff algorithm inside the core LMP on your device that will
effectively prevent these kind of "attacks".
> > And now I have to ask the question, why are we bothering this heavy with
> > trying to do auto pairing with Legacy Pairing where almost everything
> > has moved on the Simple Pairing and the users have been trained to enter
> > 0000 for their HID and headset devices if they ever get asked?
> >
>
> Well, "almost everything" unfortunately seems to exclude almost every
> device we purchased from Amazon and Fry's, which are all 2.0 at best.
That is seriously funny. I have not bought a single 2.0 device in a long
time. Only exceptions are keyboards and mice. That device class seems to
be waiting for HID over Low Energy.
> And I don't think users really have been adequately trained - take
> keyboards for example, does anyone really know that not only do you
> have to try a pin (e.g. 0000) but then you have to type that same
> exact pin on the keyboard? No, because a good OS hides all that.
>
>
> Anyway, I take your point that the Agent is intended to be a direct
> representation of the user, so will go down the plugin route and deal
> with the lazy (and complicated) devices that way.
>
> Would you like the lazy plugin contributed upstream?
Sure. Send them all upstream. You will need to touch the core anyway at
some point. Some of your ideas can not be solved with a pure plugin
right now. Especially if you wanna change the part that interacts with
the agent as well.
Regards
Marcel
^ permalink raw reply
* [PATCH] ARM pca-a-l1: fix board_init
From: Sascha Hauer @ 2012-01-17 10:23 UTC (permalink / raw)
To: barebox; +Cc: Juergen Kilb
board_init is now called omap3_board_init. broken since:
commit 494a12f703c33f80fe96e2a728545c490347eceb
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat Jan 14 15:51:05 2012 +0100
omap3: move platform lowlevel init to mach-omap
this will allow to switch omap3 to standard organisation
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/phycard-a-l1/Makefile | 1 -
arch/arm/boards/phycard-a-l1/lowlevel.c | 39 -------------------------------
arch/arm/boards/phycard-a-l1/pca-a-l1.c | 2 +-
3 files changed, 1 insertions(+), 41 deletions(-)
delete mode 100644 arch/arm/boards/phycard-a-l1/lowlevel.c
diff --git a/arch/arm/boards/phycard-a-l1/Makefile b/arch/arm/boards/phycard-a-l1/Makefile
index cb0106b..db48b6d 100644
--- a/arch/arm/boards/phycard-a-l1/Makefile
+++ b/arch/arm/boards/phycard-a-l1/Makefile
@@ -18,5 +18,4 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
-obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel.o
obj-y += pca-a-l1.o
diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c
deleted file mode 100644
index bffbb08..0000000
--- a/arch/arm/boards/phycard-a-l1/lowlevel.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * (C) Copyright 2011
- * Phytec Messtechnik GmbH <www.phytec.de>
- * Juergen Kilb <j.kilb@phytec.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/barebox-arm.h>
-#include <mach/sdrc.h>
-#include <mach/omap3-silicon.h>
-
-void __naked board_init_lowlevel(void)
-{
- uint32_t r;
-
- /* setup a stack */
- r = OMAP_SRAM_STACK;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
-
- board_init();
-
- board_init_lowlevel_return();
-}
diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
index 7b127f3..11e8638 100644
--- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c
+++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
@@ -224,7 +224,7 @@ static void pcaal1_mux_config(void)
*
* @return void
*/
-void board_init(void)
+void omap3_board_init(void)
{
int in_sdram = running_in_sdram();
--
1.7.8.3
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