* Re: [PATCH] proc: optimize render_sigset_t()
From: Alexey Dobriyan @ 2016-11-09 10:19 UTC (permalink / raw)
To: Andrei Vagin; +Cc: Linux Kernel, Andrew Morton
In-Reply-To: <1478641048-11406-1-git-send-email-avagin@openvz.org>
On Wed, Nov 9, 2016 at 12:37 AM, Andrei Vagin <avagin@openvz.org> wrote:
> @@ -245,10 +247,13 @@ void render_sigset_t(struct seq_file *m, const char *header,
> if (sigismember(set, i+2)) x |= 2;
> if (sigismember(set, i+3)) x |= 4;
> if (sigismember(set, i+4)) x |= 8;
> - seq_printf(m, "%x", x);
> + buf[j++] = hex_asc[x];
> } while (i >= 4);
>
> - seq_putc(m, '\n');
> + buf[j++] = '\n';
> + buf[j++] = 0;
> +
> + seq_puts(m, buf);
seq_write() should be used to avoid re-reading in strlen().
Anyway I suspect bulk conversion SIMD-style will still be faster.
Alexey
^ permalink raw reply
* [PATCH 09/14] crypto: caam - remove unreachable code in report_ccb_status()
From: Horia Geantă @ 2016-11-09 8:46 UTC (permalink / raw)
To: Herbert Xu; +Cc: David S. Miller, linux-crypto
In-Reply-To: <1478681184-9442-1-git-send-email-horia.geanta@nxp.com>
ERRID is a 4-bit field.
Since err_id values are in [0..15] and err_id_list array size is 16,
the condition "err_id < ARRAY_SIZE(err_id_list)" is always true.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
drivers/crypto/caam/error.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c
index 33e41ea83fcc..79a0cc70717f 100644
--- a/drivers/crypto/caam/error.c
+++ b/drivers/crypto/caam/error.c
@@ -146,10 +146,9 @@ static void report_ccb_status(struct device *jrdev, const u32 status,
strlen(rng_err_id_list[err_id])) {
/* RNG-only error */
err_str = rng_err_id_list[err_id];
- } else if (err_id < ARRAY_SIZE(err_id_list))
+ } else {
err_str = err_id_list[err_id];
- else
- snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+ }
/*
* CCB ICV check failures are part of normal operation life;
--
2.4.4
^ permalink raw reply related
* [PATCH 13/14] crypto: caam - constify pointer to descriptor buffer
From: Horia Geantă @ 2016-11-09 8:46 UTC (permalink / raw)
To: Herbert Xu; +Cc: David S. Miller, linux-crypto
In-Reply-To: <1478681184-9442-1-git-send-email-horia.geanta@nxp.com>
The pointer to the descriptor buffer is not touched,
it always points to start of the descriptor buffer.
Thus, make it const.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
drivers/crypto/caam/desc_constr.h | 72 +++++++++++++++++++++------------------
1 file changed, 38 insertions(+), 34 deletions(-)
diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index a8cd8a78ec1f..354da735af62 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -33,38 +33,39 @@
extern bool caam_little_end;
-static inline int desc_len(u32 *desc)
+static inline int desc_len(u32 * const desc)
{
return caam32_to_cpu(*desc) & HDR_DESCLEN_MASK;
}
-static inline int desc_bytes(void *desc)
+static inline int desc_bytes(void * const desc)
{
return desc_len(desc) * CAAM_CMD_SZ;
}
-static inline u32 *desc_end(u32 *desc)
+static inline u32 *desc_end(u32 * const desc)
{
return desc + desc_len(desc);
}
-static inline void *sh_desc_pdb(u32 *desc)
+static inline void *sh_desc_pdb(u32 * const desc)
{
return desc + 1;
}
-static inline void init_desc(u32 *desc, u32 options)
+static inline void init_desc(u32 * const desc, u32 options)
{
*desc = cpu_to_caam32((options | HDR_ONE) + 1);
}
-static inline void init_sh_desc(u32 *desc, u32 options)
+static inline void init_sh_desc(u32 * const desc, u32 options)
{
PRINT_POS;
init_desc(desc, CMD_SHARED_DESC_HDR | options);
}
-static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
+static inline void init_sh_desc_pdb(u32 * const desc, u32 options,
+ size_t pdb_bytes)
{
u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
@@ -72,19 +73,20 @@ static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
options);
}
-static inline void init_job_desc(u32 *desc, u32 options)
+static inline void init_job_desc(u32 * const desc, u32 options)
{
init_desc(desc, CMD_DESC_HDR | options);
}
-static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
+static inline void init_job_desc_pdb(u32 * const desc, u32 options,
+ size_t pdb_bytes)
{
u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
init_job_desc(desc, (((pdb_len + 1) << HDR_START_IDX_SHIFT)) | options);
}
-static inline void append_ptr(u32 *desc, dma_addr_t ptr)
+static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
@@ -94,8 +96,8 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
CAAM_PTR_SZ / CAAM_CMD_SZ);
}
-static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
- u32 options)
+static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
+ int len, u32 options)
{
PRINT_POS;
init_job_desc(desc, HDR_SHARED | options |
@@ -103,7 +105,7 @@ static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
append_ptr(desc, ptr);
}
-static inline void append_data(u32 *desc, void *data, int len)
+static inline void append_data(u32 * const desc, void *data, int len)
{
u32 *offset = desc_end(desc);
@@ -114,7 +116,7 @@ static inline void append_data(u32 *desc, void *data, int len)
(len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ);
}
-static inline void append_cmd(u32 *desc, u32 command)
+static inline void append_cmd(u32 * const desc, u32 command)
{
u32 *cmd = desc_end(desc);
@@ -125,7 +127,7 @@ static inline void append_cmd(u32 *desc, u32 command)
#define append_u32 append_cmd
-static inline void append_u64(u32 *desc, u64 data)
+static inline void append_u64(u32 * const desc, u64 data)
{
u32 *offset = desc_end(desc);
@@ -142,14 +144,14 @@ static inline void append_u64(u32 *desc, u64 data)
}
/* Write command without affecting header, and return pointer to next word */
-static inline u32 *write_cmd(u32 *desc, u32 command)
+static inline u32 *write_cmd(u32 * const desc, u32 command)
{
*desc = cpu_to_caam32(command);
return desc + 1;
}
-static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
+static inline void append_cmd_ptr(u32 * const desc, dma_addr_t ptr, int len,
u32 command)
{
append_cmd(desc, command | len);
@@ -157,7 +159,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
}
/* Write length after pointer, rather than inside command */
-static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
+static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
unsigned int len, u32 command)
{
append_cmd(desc, command);
@@ -166,7 +168,7 @@ static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
append_cmd(desc, len);
}
-static inline void append_cmd_data(u32 *desc, void *data, int len,
+static inline void append_cmd_data(u32 * const desc, void *data, int len,
u32 command)
{
append_cmd(desc, command | IMMEDIATE | len);
@@ -174,7 +176,7 @@ static inline void append_cmd_data(u32 *desc, void *data, int len,
}
#define APPEND_CMD_RET(cmd, op) \
-static inline u32 *append_##cmd(u32 *desc, u32 options) \
+static inline u32 *append_##cmd(u32 * const desc, u32 options) \
{ \
u32 *cmd = desc_end(desc); \
PRINT_POS; \
@@ -184,13 +186,13 @@ static inline u32 *append_##cmd(u32 *desc, u32 options) \
APPEND_CMD_RET(jump, JUMP)
APPEND_CMD_RET(move, MOVE)
-static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
+static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd)
{
*jump_cmd = cpu_to_caam32(caam32_to_cpu(*jump_cmd) |
(desc_len(desc) - (jump_cmd - desc)));
}
-static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
+static inline void set_move_tgt_here(u32 * const desc, u32 *move_cmd)
{
u32 val = caam32_to_cpu(*move_cmd);
@@ -200,7 +202,7 @@ static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
}
#define APPEND_CMD(cmd, op) \
-static inline void append_##cmd(u32 *desc, u32 options) \
+static inline void append_##cmd(u32 * const desc, u32 options) \
{ \
PRINT_POS; \
append_cmd(desc, CMD_##op | options); \
@@ -208,7 +210,8 @@ static inline void append_##cmd(u32 *desc, u32 options) \
APPEND_CMD(operation, OPERATION)
#define APPEND_CMD_LEN(cmd, op) \
-static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \
+static inline void append_##cmd(u32 * const desc, unsigned int len, \
+ u32 options) \
{ \
PRINT_POS; \
append_cmd(desc, CMD_##op | len | options); \
@@ -220,8 +223,8 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
#define APPEND_CMD_PTR(cmd, op) \
-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \
- u32 options) \
+static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
+ unsigned int len, u32 options) \
{ \
PRINT_POS; \
append_cmd_ptr(desc, ptr, len, CMD_##op | options); \
@@ -231,8 +234,8 @@ APPEND_CMD_PTR(load, LOAD)
APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
APPEND_CMD_PTR(fifo_store, FIFO_STORE)
-static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
- u32 options)
+static inline void append_store(u32 * const desc, dma_addr_t ptr,
+ unsigned int len, u32 options)
{
u32 cmd_src;
@@ -249,7 +252,8 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
}
#define APPEND_SEQ_PTR_INTLEN(cmd, op) \
-static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
+static inline void append_seq_##cmd##_ptr_intlen(u32 * const desc, \
+ dma_addr_t ptr, \
unsigned int len, \
u32 options) \
{ \
@@ -263,7 +267,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
APPEND_SEQ_PTR_INTLEN(out, OUT)
#define APPEND_CMD_PTR_TO_IMM(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
unsigned int len, u32 options) \
{ \
PRINT_POS; \
@@ -273,7 +277,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
#define APPEND_CMD_PTR_EXTLEN(cmd, op) \
-static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \
+static inline void append_##cmd##_extlen(u32 * const desc, dma_addr_t ptr, \
unsigned int len, u32 options) \
{ \
PRINT_POS; \
@@ -287,7 +291,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
* the size of its type
*/
#define APPEND_CMD_PTR_LEN(cmd, op, type) \
-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \
+static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
type len, u32 options) \
{ \
PRINT_POS; \
@@ -304,7 +308,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32)
* from length of immediate data provided, e.g., split keys
*/
#define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
unsigned int data_len, \
unsigned int len, u32 options) \
{ \
@@ -315,7 +319,7 @@ static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
APPEND_CMD_PTR_TO_IMM2(key, KEY);
#define APPEND_CMD_RAW_IMM(cmd, op, type) \
-static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \
+static inline void append_##cmd##_imm_##type(u32 * const desc, type immediate, \
u32 options) \
{ \
PRINT_POS; \
--
2.4.4
^ permalink raw reply related
* Re: [PATCH v3 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Gregory CLEMENT @ 2016-11-09 10:21 UTC (permalink / raw)
To: Romain Perier
Cc: Mark Rutland, devicetree, Yahuda Yitschak, Omri Itach,
Jason Cooper, Pawel Moll, Ian Campbell, Igal Liberman, Hanna Hawa,
Wolfram Sang, Neta Zur Hershkovits, Nadav Haklai, Rob Herring,
Andrew Lunn, linux-i2c, Kumar Gala, Shadi Ammouri, Marcin Wojtas,
Thomas Petazzoni, linux-arm-kernel, Sebastian Hesselbarth
In-Reply-To: <20161109101349.18722-2-romain.perier@free-electrons.com>
Hi Romain,
You was too fast I didn't have time to commnent about Baruch suggestion.
On mer., nov. 09 2016, Romain Perier <romain.perier@free-electrons.com> wrote:
> The Armada 3700 has two I2C controllers that is compliant with the I2C
> Bus Specificiation 2.1, supports multi-master and different bus speed:
> Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
> High speed mode (up to 3.4 Mhz).
>
> This IP block has a lot of similarity with the PXA, except some register
> offsets and bitfield. This commits adds a basic support for this I2C
> unit.
>
> Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>
> Changes in v3:
> - Replaced the type of hm_mask and fm_mask by unsigned int,
> instead of unsigned long.
[...]
> #define ISR_RWM (1 << 0) /* read/write mode */
> @@ -193,6 +204,8 @@ struct pxa_i2c {
> unsigned char master_code;
> unsigned long rate;
> bool highmode_enter;
> + unsigned int fm_mask;
> + unsigned int hs_mask;
These masks are used with writel and readl which use an u32. So the
better is to use this type.
Gregory
> };
>
> #define _IBMR(i2c) ((i2c)->reg_ibmr)
> @@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
> writel(i2c->slave_addr, _ISAR(i2c));
>
> /* set control register values */
> - writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
> - writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
> + writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
> + writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH v3 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Gregory CLEMENT @ 2016-11-09 10:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109101349.18722-2-romain.perier@free-electrons.com>
Hi Romain,
You was too fast I didn't have time to commnent about Baruch suggestion.
On mer., nov. 09 2016, Romain Perier <romain.perier@free-electrons.com> wrote:
> The Armada 3700 has two I2C controllers that is compliant with the I2C
> Bus Specificiation 2.1, supports multi-master and different bus speed:
> Standard mode (up to 100 KHz), Fast mode (up to 400 KHz),
> High speed mode (up to 3.4 Mhz).
>
> This IP block has a lot of similarity with the PXA, except some register
> offsets and bitfield. This commits adds a basic support for this I2C
> unit.
>
> Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>
> Changes in v3:
> - Replaced the type of hm_mask and fm_mask by unsigned int,
> instead of unsigned long.
[...]
> #define ISR_RWM (1 << 0) /* read/write mode */
> @@ -193,6 +204,8 @@ struct pxa_i2c {
> unsigned char master_code;
> unsigned long rate;
> bool highmode_enter;
> + unsigned int fm_mask;
> + unsigned int hs_mask;
These masks are used with writel and readl which use an u32. So the
better is to use this type.
Gregory
> };
>
> #define _IBMR(i2c) ((i2c)->reg_ibmr)
> @@ -503,8 +516,8 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
> writel(i2c->slave_addr, _ISAR(i2c));
>
> /* set control register values */
> - writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
> - writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
> + writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
> + writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
Hi everyone,
This series adds basic PSCI support for the A80 to enable SMP on the
first cluster. This at least allows people to use more than one core.
The term "basic" is used because the series does not add support for
multi-cluster cache and power management.
The PSCI code is based on existing code for all the single cluster
SoCs, and the kernel patches for MCPM SMP I did some time ago.
Unfortunately only SMP works at this time. The last patch does not
actually work. While the system is indeed booted non-secure, tested
by trying to write to secure SRAM and the results not sticking, reads
from the GIC CPU interface shows that it's still returning the secure
copy of registers, and since we use a secure monitor FIQ to do core
power down, the FIQ gets passed to the kernel. The patch is included
so people with in-depth ARM knowledge could probably help work out
what is wrong.
Regards
ChenYu
Chen-Yu Tsai (10):
ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80
sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80
sunxi: Add base address of secure SRAM B for sun9i/A80
sunxi: Use secure SRAM B for secure RAM for sun9i/A80
sunxi: Add PRCM register definition for sun9i/A80
sunxi: Add CPUCFG register definitions for sun9i/A80
sunxi: Add support for TZPC on sun9i/A80
sunxi: Add basic PSCI implementation for A80
sunxi: Enable PSCI on sun9i/A80
sunxi: Add PSCI core power off support for A80's first cluster
arch/arm/cpu/armv7/Kconfig | 1 +
arch/arm/cpu/armv7/sunxi/Makefile | 5 +
arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 322 +++++++++++++++++++++++++
arch/arm/cpu/armv7/sunxi/tzpc.c | 6 +
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 5 +
arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 51 ++++
arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 +++++
arch/arm/include/asm/arch-sunxi/tzpc.h | 4 +
arch/arm/mach-sunxi/board.c | 3 +-
board/sunxi/Kconfig | 4 +
include/configs/sun9i.h | 4 +
11 files changed, 459 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c
create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h
--
2.10.2
^ permalink raw reply
* [U-Boot] [PATCH 01/10] ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
The A80 is a big.LITTLE SoC with 4x Cortex-A7 in cluster 0 and 4x
Cortex-A15 in cluster 1.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/cpu/armv7/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index b9c4f4e79b9b..e37f1f328a34 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -44,6 +44,7 @@ config ARMV7_PSCI
config ARMV7_PSCI_NR_CPUS
int "Maximum supported CPUs for PSCI"
depends on ARMV7_NONSEC
+ default 8 if MACH_SUN9I
default 4
help
The maximum number of CPUs supported in the PSCI firmware.
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 02/10] sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
The A80, having 2 clusters of 4 cores each, has an ARM CCI-400 hardware
block for cache coherency.
Add the base address for CCI-400, and also add the base address for CPUCFG.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index c775bcc515a0..88b48c644c06 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -17,6 +17,9 @@
#define REGS_APB1_BASE 0x07000000
#define REGS_RCPUS_BASE 0x08000000
+#define SUNXI_CPUCFG_BASE 0x01700000
+#define SUNXI_CCI400_BASE 0x01790000
+
#define SUNXI_SRAM_D_BASE 0x08100000
/* AHB0 Module */
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 03/10] sunxi: Add base address of secure SRAM B for sun9i/A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
The A80 has a 256 kiB secure SRAM. However the first 4 kiB are reserved
for CPU0 hotplug flags.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index 88b48c644c06..e9839eecaa92 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -20,6 +20,7 @@
#define SUNXI_CPUCFG_BASE 0x01700000
#define SUNXI_CCI400_BASE 0x01790000
+#define SUNXI_SRAM_B_BASE 0x00020000
#define SUNXI_SRAM_D_BASE 0x08100000
/* AHB0 Module */
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 04/10] sunxi: Use secure SRAM B for secure RAM for sun9i/A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
The A80 has a 256 kiB secure SRAM. However the first 4 kiB are reserved
for CPU0 hotplug flags.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
include/configs/sun9i.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/configs/sun9i.h b/include/configs/sun9i.h
index cd9e08d8b1b9..e751c5e05c14 100644
--- a/include/configs/sun9i.h
+++ b/include/configs/sun9i.h
@@ -13,6 +13,10 @@
* A80 specific configuration
*/
+/* First 4 kiB is reserved for CPU0 hotplug flags */
+#define CONFIG_ARMV7_SECURE_BASE (SUNXI_SRAM_B_BASE + 4 * 1024)
+#define CONFIG_ARMV7_SECURE_MAX_SIZE (252 * 1024) /* 252 KB */
+
/*
* Include common sunxi configuration where most the settings are
*/
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 05/10] sunxi: Add PRCM register definition for sun9i/A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
The A80 has a different PRCM register layout.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 ++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h
diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h
new file mode 100644
index 000000000000..f4732335fbcc
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h
@@ -0,0 +1,55 @@
+/*
+ * Sunxi A80 Power Reset and Clock Module register definition
+ *
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_SUN9I_H
+#define _SUNXI_PRCM_SUN9I_H
+
+struct __packed sunxi_prcm_reg {
+ u32 cpus_rst; /* 0x000 */
+ u32 cpu_rst[2]; /* 0x004 */
+ u8 res0[0x4]; /* 0x00c */
+ u32 cpus_cfg; /* 0x010 */
+ u8 res1[0x8]; /* 0x014 */
+ u32 apbs_ratio; /* 0x01c */
+ u8 res2[0x8]; /* 0x020 */
+ u32 apbs_gate; /* 0x028 */
+ u8 res3[0x18]; /* 0x02c */
+ u32 pll_ctrl1; /* 0x044 */
+ u8 res4[0xc]; /* 0x048 */
+ u32 clk_cir; /* 0x054 */
+ u32 clk_i2s0; /* 0x058 */
+ u32 clk_i2s1; /* 0x05c */
+ u8 res5[0x50]; /* 0x060 */
+ u32 apb0_reset; /* 0x0b0 */
+ u8 res6[0x4c]; /* 0x0b4 */
+ u32 cpu_pwroff[2]; /* 0x100 */
+ u8 res7[0x8]; /* 0x108 */
+ u32 vdd_sys_pwroff; /* 0x110 */
+ u8 res8[0x4]; /* 0x114 */
+ u32 gpu_pwroff; /* 0x118 */
+ u8 res9[0x4]; /* 0x11c */
+ u32 vdd_sys_rst; /* 0x120 */
+ u8 res10[0x1c]; /* 0x124 */
+ u32 cpu_pwr_clamp[2][4]; /* 0x140 */
+ u32 super_standby_flag; /* 0x160 */
+ u32 cpu_soft_entry; /* 0x164 */
+ u32 super_standby_entry; /* 0x168 */
+ u8 res11[0x34]; /* 0x16c */
+ u32 nmi_irq_ctrl; /* 0x1a0 */
+ u32 nmi_irq_en; /* 0x1a4 */
+ u32 nmi_irq_status; /* 0x1a8 */
+ u8 res12[0x14]; /* 0x1ac */
+ u32 pll_audio_ctrl; /* 0x1c0 */
+ u32 pll_audio_bias; /* 0x1c4 */
+ u32 pll_audio_pat_cfg; /* 0x1c8 */
+ u32 pll_audio_ctrl_sw; /* 0x1cc */
+ u8 res13[0x20]; /* 0x1d0 */
+ u32 osc24m_ctrl; /* 0x1f0 */
+};
+
+#endif /* _SUNXI_PRCM_SUN9I_H */
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 06/10] sunxi: Add CPUCFG register definitions for sun9i/A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
The A80 has a different CPUCFG register layout, likely due to having
2 clusters.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 51 ++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
new file mode 100644
index 000000000000..0ee6a63e441b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
@@ -0,0 +1,51 @@
+/*
+ * Sunxi A80 CPUCFG register definition.
+ *
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPUCFG_SUN9I_H
+#define _SUNXI_CPUCFG_SUN9I_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#define CPUCFG_CX_CTRL0_L1_RST_DISABLE(core) BIT(core)
+
+#define CPUCFG_CX_STATUS_STANDBYWFI(core) BIT(16 + core)
+
+#define CPUCFG_CX_RST_CORE(core) BIT(core)
+#define CPUCFG_CX_RST_NEON(core) BIT(4 + core) /* A15 only */
+#define CPUCFG_CX_RST_L2 BIT(8)
+#define CPUCFG_CX_RST_HRESET BIT(12)
+#define CPUCFG_CX_RST_DBG(core) BIT(16 + core)
+#define CPUCFG_CX_RST_ETM(core) BIT(20 + core)
+#define CPUCFG_CX_RST_SOC_DBG BIT(24)
+
+#ifndef __ASSEMBLY__
+
+struct __packed sunxi_cpucfg_cluster {
+ u32 ctrl0; /* base + 0x0 */
+ u32 ctrl1; /* base + 0x4 */
+ u32 adb400_pwrdnreqn; /* base + 0x8 */
+ u8 res[0x4]; /* base + 0xc */
+};
+
+struct __packed sunxi_cpucfg_reg {
+ struct sunxi_cpucfg_cluster cluster[2]; /* 0x00 */
+ u8 res0[0x8]; /* 0x20 */
+ u32 gen_ctrl0; /* 0x28 */
+ u32 gen_ctrl1; /* 0x2c */
+ u32 cluster_status[2]; /* 0x30 */
+ u8 res1[0x4]; /* 0x38 */
+ u32 irq_fiq_status; /* 0x3c */
+ u32 irq_fiq_mask; /* 0x40 */
+ u8 res2[0x3c]; /* 0x44 */
+ u32 cluster_reset[2]; /* 0x80 */
+ u32 gic_jtag_reset; /* 0x88 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_SUN9I_H */
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 07/10] sunxi: Add support for TZPC on sun9i/A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
The A80 also has the TrustZone Protection Controller (TZPC), called
the Secure Memory Touch Arbiter (SMTA).
Enable non-secure access to all the peripherals at boot time.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/tzpc.c | 6 ++++++
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 1 +
arch/arm/include/asm/arch-sunxi/tzpc.h | 4 ++++
arch/arm/mach-sunxi/board.c | 3 ++-
5 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index b35b9df4a9d6..239c659ec032 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += timer.o
obj-$(CONFIG_MACH_SUN6I) += tzpc.o
obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o
+obj-$(CONFIG_MACH_SUN9I) += tzpc.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
index 6c8a0fd9a25b..2a2cf363b99c 100644
--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
@@ -24,4 +24,10 @@ void tzpc_init(void)
writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
#endif
+
+#ifdef CONFIG_MACH_SUN9I
+ writel(SUN9I_TZPC_DECPORT0_ALL, &tzpc->decport0_set);
+ writel(SUN9I_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
+ writel(SUN9I_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
+#endif
}
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index e9839eecaa92..25114174f395 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -90,6 +90,7 @@
#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
+#define SUNXI_TZPC_BASE (REGS_APB0_BASE + 0x3400)
/* APB1 Module */
#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000)
diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h
index 95c55cd4d130..3425d00edd97 100644
--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -29,6 +29,10 @@ struct sunxi_tzpc {
#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff
#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f
+#define SUN9I_TZPC_DECPORT0_ALL 0xfe
+#define SUN9I_TZPC_DECPORT1_ALL 0x7f
+#define SUN9I_TZPC_DECPORT2_ALL 0x00
+
void tzpc_init(void);
#endif /* _SUNXI_TZPC_H */
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 0f8ead980cdc..0053f562e00d 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -190,7 +190,8 @@ void s_init(void)
"orr r0, r0, #1 << 6\n"
"mcr p15, 0, r0, c1, c0, 1\n");
#endif
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 || \
+ defined CONFIG_MACH_SUN9I
/* Enable non-secure access to some peripherals */
tzpc_init();
#endif
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 08/10] sunxi: Add basic PSCI implementation for A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
The A80 is a big.LITTLE multi-cluster SoC, with a different layout for
the PRCM and CPUCFG registers. As such it needs a different PSCI
implementation.
This patch adds a basic version that allows bringing up the four cores
in the first cluster. The structure is based on existing sunxi PSCI code.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/cpu/armv7/sunxi/Makefile | 4 +
arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 234 +++++++++++++++++++++++++++++++++++
2 files changed, 238 insertions(+)
create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 239c659ec032..b18e5f1fa974 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -14,8 +14,12 @@ obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o
obj-$(CONFIG_MACH_SUN9I) += tzpc.o
ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_MACH_SUN9I
+obj-$(CONFIG_ARMV7_PSCI) += psci-mcpm.o
+else
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
+endif
ifdef CONFIG_SPL_BUILD
obj-y += fel_utils.o
diff --git a/arch/arm/cpu/armv7/sunxi/psci-mcpm.c b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
new file mode 100644
index 000000000000..3ede07cace2c
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2016
+ * Author: Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
+ * which was based on code by Carl van Schaik <carl@ok-labs.com>.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <config.h>
+#include <common.h>
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/cpucfg_sun9i.h>
+#include <asm/arch/prcm_sun9i.h>
+#include <asm/armv7.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+
+#include <linux/bitops.h>
+
+/*
+ * NOTE dense CPU IDs (0~3 for first cluster of 4 cores, 4~7 for the
+ * second cluster) are used throughout the PSCI code. Any MPIDR style
+ * values must be converted.
+ */
+
+/*
+ * Provide a dense CPU ID for 2-cluster systems. This must be coded in
+ * assembly as it gets called from psci_stack_setup, when the stack isn't
+ * available yet.
+ *
+ * Only r0 and r3 is usable. r8 - r12 are available if this function is
+ * only called from psci_stack_setup, which we cannot guarantee.
+ */
+u32 __secure __naked psci_get_cpu_id(void)
+{
+ asm volatile (
+ "mrc p15, 0, r3, c0, c0, 5 @ Get MPIDR\n"
+ "lsr r0, r3, #6\n"
+ "and r3, r3, #3\n"
+ "and r0, r0, #4\n"
+ "orr r0, r0, r3\n"
+ "bx lr\n"
+ );
+
+ /*
+ * The last five lines are the compiler generated assembly code for
+ *
+ * return (reg & 0x3) | (((reg >> 8) & 0x1) << 2);
+ *
+ * We can't guarantee that all compilers correctly use only r0 and
+ * r3, so we use inline assembly here.
+ */
+}
+
+static void __secure cp15_write_cntp_tval(u32 tval)
+{
+ asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+}
+
+static void __secure cp15_write_cntp_ctl(u32 val)
+{
+ asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+}
+
+static u32 __secure cp15_read_cntp_ctl(void)
+{
+ u32 val;
+
+ asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+
+ return val;
+}
+
+#define ONE_US (CONFIG_TIMER_CLK_FREQ / 1000000)
+
+/* Use a different name to avoid clashing with the non-secure function */
+static void __secure __udelay_sec(unsigned long us)
+{
+ u32 reg = ONE_US * us;
+
+ cp15_write_cntp_tval(reg);
+ isb();
+ cp15_write_cntp_ctl(3);
+
+ do {
+ isb();
+ reg = cp15_read_cntp_ctl();
+ } while (!(reg & BIT(2)));
+
+ cp15_write_cntp_ctl(0);
+ isb();
+}
+
+static void __secure clamp_release(u32 *clamp)
+{
+ writel(0xff, clamp);
+ __udelay_sec(10);
+ writel(0xfe, clamp);
+ __udelay_sec(10);
+ writel(0xf8, clamp);
+ __udelay_sec(10);
+ writel(0xf0, clamp);
+ __udelay_sec(10);
+ writel(0x00, clamp);
+}
+
+static void __secure clamp_set(u32 *clamp)
+{
+ writel(0xff, clamp);
+}
+
+static void __secure sunxi_core_power_switch(u32 *clamp, u32 *pwroff,
+ bool on, int cpu)
+{
+ if (on) {
+ /* Release power clamp */
+ clamp_release(clamp);
+
+ __udelay_sec(20);
+
+ /* Clear power gating */
+ clrbits_le32(pwroff, BIT(cpu));
+ } else {
+ /* Set power gating */
+ setbits_le32(pwroff, BIT(cpu));
+
+ __udelay_sec(20);
+
+ /* Activate power clamp */
+ clamp_set(clamp);
+ }
+}
+
+static void __secure sunxi_cpu_set_power(int cpu, bool on)
+{
+ struct sunxi_prcm_reg *prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ int cluster = (cpu >> 2) & 0x1;
+ int core = cpu & 0x3;
+
+ sunxi_core_power_switch(&prcm->cpu_pwr_clamp[cluster][core],
+ &prcm->cpu_pwroff[cluster], on, core);
+}
+
+static u32 __secure cp15_read_scr(void)
+{
+ u32 scr;
+
+ asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
+
+ return scr;
+}
+
+static void __secure cp15_write_scr(u32 scr)
+{
+ asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
+ isb();
+}
+
+int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
+{
+ struct sunxi_cpucfg_reg *cpucfg =
+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+ struct sunxi_prcm_reg *prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ u32 cluster = (mpidr >> 8) & 0x1;
+ u32 cpu = mpidr & 0x3;
+ u32 cpuid = cpu | (cluster << 2);
+
+ /* TODO We don't support multi-cluster yet */
+ if (cluster > 0)
+ return ARM_PSCI_RET_INVAL;
+
+ /* store target PC */
+ psci_save_target_pc(cpuid, pc);
+
+ /* Set secondary core power on PC */
+ writel((u32)&psci_cpu_entry, &prcm->cpu_soft_entry);
+
+ /* Assert power-on reset on target CPU */
+ clrbits_le32(&prcm->cpu_rst[cluster], BIT(cpu));
+
+ /* Cortex-A7: hold L1 cache reset disable signal low */
+ if (cluster == 0)
+ clrbits_le32(&cpucfg->cluster[cluster].ctrl0,
+ CPUCFG_CX_CTRL0_L1_RST_DISABLE(cpu));
+
+ /* Lock CPU (Disable external debug access) */
+ clrbits_le32(&cpucfg->cluster_reset[cluster],
+ CPUCFG_CX_RST_DBG(cpu));
+
+ /* Cortex-A7: Assert ETM reset */
+ if (cluster == 0)
+ clrbits_le32(&cpucfg->cluster_reset[cluster],
+ CPUCFG_CX_RST_ETM(cpu));
+
+ /*
+ * Allwinner code also asserts resets for NEON on A15. According
+ * to ARM manuals, asserting power-on reset is sufficient.
+ */
+
+ /* Power up target CPU */
+ sunxi_cpu_set_power(cpu, true);
+
+ /* De-assert power-on reset on target CPU */
+ setbits_le32(&prcm->cpu_rst[cluster], BIT(cpu));
+
+ /* De-assert core reset on target CPU */
+ setbits_le32(&cpucfg->cluster_reset[cluster],
+ CPUCFG_CX_RST_CORE(cpu));
+
+ /* Cortex-A7: De-assert ETM reset */
+ if (cluster == 0)
+ setbits_le32(&cpucfg->cluster_reset[cluster],
+ CPUCFG_CX_RST_ETM(cpu));
+
+ /* Unlock CPU (Disable external debug access) */
+ setbits_le32(&cpucfg->cluster_reset[cluster],
+ CPUCFG_CX_RST_DBG(cpu));
+
+ return ARM_PSCI_RET_SUCCESS;
+}
+
+void __secure psci_arch_init(void)
+{
+ u32 reg;
+
+ reg = cp15_read_scr();
+ reg &= ~BIT(0); /* Secure mode */
+ cp15_write_scr(reg);
+}
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 09/10] sunxi: Enable PSCI on sun9i/A80
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
Now that we have a basic version of PSCI firmware, enable non-secure
boot and PSCI on the A80.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
board/sunxi/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index e1d4ab148f08..ae2fba1368cc 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -118,8 +118,12 @@ config MACH_SUN8I_H3
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
--
2.10.2
^ permalink raw reply related
* [U-Boot] [PATCH 10/10] sunxi: Add PSCI core power off support for A80's first cluster
From: Chen-Yu Tsai @ 2016-11-09 10:21 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
This patch adds the ability to power off cores in the first cluster of
the A80 SoC. Following the single cluster sunxi PSCI implementation,
the core being powered down signals core0 via secure monitor FIQ that
it should be shut down, and enters WFI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
This does not actually work. While the system is indeed booted non-secure,
tested by trying to write to secure SRAM and the results not sticking,
reads from the GIC CPU interface shows that it's still returning the
secure copy of registers, and since we use a secure monitor FIQ to do
core power down, the FIQ gets passed to the kernel. The patch is included
so people with in-depth ARM knowledge could probably help work out what
is wrong.
Any thoughts on this is appreciated.
---
arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 88 ++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/psci-mcpm.c b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
index 3ede07cace2c..1403aeed74f4 100644
--- a/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
+++ b/arch/arm/cpu/armv7/sunxi/psci-mcpm.c
@@ -14,12 +14,19 @@
#include <asm/arch/cpucfg_sun9i.h>
#include <asm/arch/prcm_sun9i.h>
#include <asm/armv7.h>
+#include <asm/gic.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
+#include <asm/system.h>
#include <linux/bitops.h>
+#define __irq __attribute__ ((interrupt ("IRQ")))
+
+#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
+#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+
/*
* NOTE dense CPU IDs (0~3 for first cluster of 4 cores, 4~7 for the
* second cluster) are used throughout the PSCI code. Any MPIDR style
@@ -145,6 +152,25 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
&prcm->cpu_pwroff[cluster], on, core);
}
+void __secure sunxi_cpu_power_off(u32 cpuid)
+{
+ struct sunxi_cpucfg_reg *cpucfg =
+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+ u32 cluster = (cpuid >> 2) & 0x1;
+ u32 core = cpuid & 0x3;
+
+ /* Wait for the core to enter WFI */
+ while (1) {
+ if (readl(&cpucfg->cluster_status[cluster]) &
+ CPUCFG_CX_STATUS_STANDBYWFI(core))
+ break;
+ __udelay_sec(1000);
+ }
+
+ /* Power down CPU */
+ sunxi_cpu_set_power(cpuid, false);
+}
+
static u32 __secure cp15_read_scr(void)
{
u32 scr;
@@ -160,6 +186,42 @@ static void __secure cp15_write_scr(u32 scr)
isb();
}
+/*
+ * Although this is an FIQ handler, the FIQ is processed in monitor mode,
+ * which means there's no FIQ banked registers. This is the same as IRQ
+ * mode, so use the IRQ attribute to ask the compiler to handler entry
+ * and return.
+ */
+void __secure __irq psci_fiq_enter(void)
+{
+ u32 scr, reg, cpu;
+
+ /* Switch to secure mode */
+ scr = cp15_read_scr();
+ cp15_write_scr(scr & ~BIT(0));
+
+ /* Validate reason based on IAR and acknowledge */
+ reg = readl(GICC_BASE + GICC_IAR);
+
+ /* Skip spurious interrupts 1022 and 1023 */
+ if (reg == 1023 || reg == 1022)
+ goto out;
+
+ /* End of interrupt */
+ writel(reg, GICC_BASE + GICC_EOIR);
+ dsb();
+
+ /* Get CPU number */
+ cpu = (reg >> 10) & 0x7;
+
+ /* Power off the CPU */
+ sunxi_cpu_power_off(cpu);
+
+out:
+ /* Restore security level */
+ cp15_write_scr(scr);
+}
+
int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
{
struct sunxi_cpucfg_reg *cpucfg =
@@ -224,11 +286,37 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
return ARM_PSCI_RET_SUCCESS;
}
+void __secure psci_cpu_off(void)
+{
+ psci_cpu_off_common();
+
+ /* Ask CPU0 via SGI15 to pull the rug... */
+ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
+ dsb();
+
+ /* Wait to be turned off */
+ while (1)
+ wfi();
+}
+
void __secure psci_arch_init(void)
{
u32 reg;
+ /* SGI15 as Group-0 */
+ clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
+
+ /* Set SGI15 priority to 0 */
+ writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
+
+ /* Be cool with non-secure */
+ writel(0xff, GICC_BASE + GICC_PMR);
+
+ /* Switch FIQEn on */
+ setbits_le32(GICC_BASE + GICC_CTLR, BIT(3));
+
reg = cp15_read_scr();
+ reg |= BIT(2); /* Enable FIQ in monitor mode */
reg &= ~BIT(0); /* Secure mode */
cp15_write_scr(reg);
}
--
2.10.2
^ permalink raw reply related
* [Buildroot] [Question] Downgrade package application.
From: Thomas Petazzoni @ 2016-11-09 10:22 UTC (permalink / raw)
To: buildroot
In-Reply-To: <CADZ=QZmHuyjuctpfxNLn_up=41HXc_8Y+BtDx+4EScrRda04QA@mail.gmail.com>
Hello,
On Wed, 9 Nov 2016 18:04:20 +0800, Yu-Ting Kao wrote:
> I have a patch for new feature on a package, but it works on lower
> version. How can I build lower version in buildroot ? Are there any
> menuconfig I can choose ?
No. For the vast majority of the packages, we only allow building a
single version, as we can't test all combinations of all package
versions.
So if you need a lower version than the one in Buildroot:
1/ Short-term, you can just modify the .mk file, so that it uses
whichever version you need.
2/ Long-term, you should really upgrade to the latest version. If this
latest version is causing issues for you, then work with the
upstream project to fix them. Staying on an older version is
definitely not a good idea.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH] examples/l3fwd: force CRC stripping for i40evf
From: Thomas Monjalon @ 2016-11-09 10:22 UTC (permalink / raw)
To: Björn Töpel
Cc: Ananyev, Konstantin, dev, helin.zhang, Xu, Qian Q, Yao, Lei A,
Wu, Jingjing
In-Reply-To: <5ad83b54-f13b-787e-c056-958f5cb8bd61@intel.com>
2016-11-09 11:05, Björn Töpel:
> > BTW, all other examples would experience same problem too, right?
>
> Correct, so the broader question would be "what is the correct behavior
> for an example application, when a port configuration isn't supported by
> the hardware?".
>
> My stand, FWIW, is that igb and ixgbe should have the same semantics as
> i40e currently has, i.e. return an error to the user if the port is
> mis-configured, NOT changing the setting behind the users back.
Yes it sounds sane.
^ permalink raw reply
* FAILED: patch "[PATCH] btrfs: qgroup: Prevent qgroup->reserved from going subzero" failed to apply to 4.4-stable tree
From: gregkh @ 2016-11-09 10:22 UTC (permalink / raw)
To: rgoldwyn, dsterba, quwenruo; +Cc: stable
The patch below does not apply to the 4.4-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
>From 0b34c261e235a5c74dcf78bd305845bd15fe2b42 Mon Sep 17 00:00:00 2001
From: Goldwyn Rodrigues <rgoldwyn@suse.com>
Date: Fri, 30 Sep 2016 10:40:52 -0500
Subject: [PATCH] btrfs: qgroup: Prevent qgroup->reserved from going subzero
While free'ing qgroup->reserved resources, we much check if
the page has not been invalidated by a truncate operation
by checking if the page is still dirty before reducing the
qgroup resources. Resources in such a case are free'd when
the entire extent is released by delayed_ref.
This fixes a double accounting while releasing resources
in case of truncating a file, reproduced by the following testcase.
SCRATCH_DEV=/dev/vdb
SCRATCH_MNT=/mnt
mkfs.btrfs -f $SCRATCH_DEV
mount -t btrfs $SCRATCH_DEV $SCRATCH_MNT
cd $SCRATCH_MNT
btrfs quota enable $SCRATCH_MNT
btrfs subvolume create a
btrfs qgroup limit 500m a $SCRATCH_MNT
sync
for c in {1..15}; do
dd if=/dev/zero bs=1M count=40 of=$SCRATCH_MNT/a/file;
done
sleep 10
sync
sleep 5
touch $SCRATCH_MNT/a/newfile
echo "Removing file"
rm $SCRATCH_MNT/a/file
Fixes: b9d0b38928 ("btrfs: Add handler for invalidate page")
Signed-off-by: Goldwyn Rodrigues <rgoldwyn@suse.com>
Reviewed-by: Qu Wenruo <quwenruo@cn.fujitsu.com>
Signed-off-by: David Sterba <dsterba@suse.com>
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 50ba4ca167e7..6677674d0505 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -8930,9 +8930,14 @@ static void btrfs_invalidatepage(struct page *page, unsigned int offset,
* So even we call qgroup_free_data(), it won't decrease reserved
* space.
* 2) Not written to disk
- * This means the reserved space should be freed here.
+ * This means the reserved space should be freed here. However,
+ * if a truncate invalidates the page (by clearing PageDirty)
+ * and the page is accounted for while allocating extent
+ * in btrfs_check_data_free_space() we let delayed_ref to
+ * free the entire extent.
*/
- btrfs_qgroup_free_data(inode, page_start, PAGE_SIZE);
+ if (PageDirty(page))
+ btrfs_qgroup_free_data(inode, page_start, PAGE_SIZE);
if (!inode_evicting) {
clear_extent_bit(tree, page_start, page_end,
EXTENT_LOCKED | EXTENT_DIRTY |
^ permalink raw reply related
* [PATCH] dbus: Don't send replies to messages with no reply flag
From: Andrew Zaborowski @ 2016-11-09 10:22 UTC (permalink / raw)
To: ell
[-- Attachment #1: Type: text/plain, Size: 2332 bytes --]
Kdbus doesn't store the cookies for messages that have the no reply flag
and throws error when a reply is sent with reply_cookie that it doesn't
know. It's not fatal, but we save some cycles by not sending the message
with both dbus versions.
We mark those replies with reply_serial == 0, rather than setting a
"discard" flag on the message, because the method call's serial is
effectively an invalid reply_serial value.
---
ell/dbus-message.c | 10 +++++++---
ell/dbus.c | 10 ++++++++++
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/ell/dbus-message.c b/ell/dbus-message.c
index 072a902..3b44fb8 100644
--- a/ell/dbus-message.c
+++ b/ell/dbus-message.c
@@ -326,7 +326,8 @@ LIB_EXPORT struct l_dbus_message *l_dbus_message_new_method_return(
DBUS_MESSAGE_FLAG_NO_REPLY_EXPECTED,
hdr->version);
- message->reply_serial = _dbus_message_get_serial(method_call);
+ if (!l_dbus_message_get_no_reply(method_call))
+ message->reply_serial = _dbus_message_get_serial(method_call);
sender = l_dbus_message_get_sender(method_call);
if (sender)
@@ -369,11 +370,14 @@ LIB_EXPORT struct l_dbus_message *l_dbus_message_new_error_valist(
{
char str[1024];
struct dbus_header *hdr = method_call->header;
+ uint32_t reply_serial = 0;
vsnprintf(str, sizeof(str), format, args);
- return _dbus_message_new_error(hdr->version,
- _dbus_message_get_serial(method_call),
+ if (!l_dbus_message_get_no_reply(method_call))
+ reply_serial = _dbus_message_get_serial(method_call);
+
+ return _dbus_message_new_error(hdr->version, reply_serial,
l_dbus_message_get_sender(method_call),
name, str);
}
diff --git a/ell/dbus.c b/ell/dbus.c
index 236c35a..2c04ec9 100644
--- a/ell/dbus.c
+++ b/ell/dbus.c
@@ -313,6 +313,16 @@ static uint32_t send_message(struct l_dbus *dbus, bool priority,
void *user_data, l_dbus_destroy_func_t destroy)
{
struct message_callback *callback;
+ enum dbus_message_type type;
+
+ type = _dbus_message_get_type(message);
+
+ if ((type == DBUS_MESSAGE_TYPE_METHOD_RETURN ||
+ type == DBUS_MESSAGE_TYPE_ERROR) &&
+ _dbus_message_get_reply_serial(message) == 0) {
+ l_dbus_message_unref(message);
+ return 0;
+ }
callback = l_new(struct message_callback, 1);
--
2.7.4
^ permalink raw reply related
* Re: [Qemu-devel] [PATCH] cipher: fix leak on initialization error
From: Daniel P. Berrange @ 2016-11-09 10:22 UTC (permalink / raw)
To: Marc-André Lureau; +Cc: qemu-devel
In-Reply-To: <20161109101815.9057-1-marcandre.lureau@redhat.com>
On Wed, Nov 09, 2016 at 02:18:15PM +0400, Marc-André Lureau wrote:
> If ctx->blocksize != XTS_BLOCK_SIZE, ctx will be leaked.
> Assign ctx earler, and call qcrypto_cipher_free() on error.
>
> Spotted thanks to ASAN.
>
> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> crypto/cipher-nettle.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/crypto/cipher-nettle.c b/crypto/cipher-nettle.c
> index cd094cd..593962c 100644
> --- a/crypto/cipher-nettle.c
> +++ b/crypto/cipher-nettle.c
> @@ -376,6 +376,7 @@ QCryptoCipher *qcrypto_cipher_new(QCryptoCipherAlgorithm alg,
> goto error;
> }
'ctx' is non-NULL at this point and there's a 'goto error' just
above here....
>
> + cipher->opaque = ctx;
> if (mode == QCRYPTO_CIPHER_MODE_XTS &&
> ctx->blocksize != XTS_BLOCK_SIZE) {
> error_setg(errp, "Cipher block size %zu must equal XTS block size %d",
> @@ -384,13 +385,11 @@ QCryptoCipher *qcrypto_cipher_new(QCryptoCipherAlgorithm alg,
> }
>
> ctx->iv = g_new0(uint8_t, ctx->blocksize);
> - cipher->opaque = ctx;
>
> return cipher;
>
> error:
> - g_free(cipher);
> - g_free(ctx);
> + qcrypto_cipher_free(cipher);
> return NULL;
> }
...so you're leaking 'ctx' now, since it hasn't been assigned
to cipher->ctx.
You need to move 'cipher->opque = ctx' to the place where we
initially allocate 'ctx', before any gotos at which point....
>
> @@ -404,10 +403,12 @@ void qcrypto_cipher_free(QCryptoCipher *cipher)
> }
>
> ctx = cipher->opaque;
> - g_free(ctx->iv);
> - g_free(ctx->ctx);
> - g_free(ctx->ctx_tweak);
> - g_free(ctx);
> + if (ctx) {
> + g_free(ctx->iv);
> + g_free(ctx->ctx);
> + g_free(ctx->ctx_tweak);
> + g_free(ctx);
> + }
> g_free(cipher);
> }
...this change is not needed
Regards,
Daniel
--
|: http://berrange.com -o- http://www.flickr.com/photos/dberrange/ :|
|: http://libvirt.org -o- http://virt-manager.org :|
|: http://entangle-photo.org -o- http://search.cpan.org/~danberr/ :|
^ permalink raw reply
* Re: [PATCH] [RFC] drivers: dma-coherent: use MEMREMAP_WB instead of MEMREMAP_WC
From: Brian Starkey @ 2016-11-09 10:23 UTC (permalink / raw)
To: Jaewon Kim; +Cc: linux-mm, linux-kernel
In-Reply-To: <5822F0AE.30101@samsung.com>
Hi,
On Wed, Nov 09, 2016 at 06:47:26PM +0900, Jaewon Kim wrote:
>
>
>On 2016e?? 11i?? 09i? 1/4 18:27, Brian Starkey wrote:
>> Hi Jaewon,
>>
>> On Wed, Nov 09, 2016 at 06:10:09PM +0900, Jaewon Kim wrote:
>>> Commit 6b03ae0d42bf (drivers: dma-coherent: use MEMREMAP_WC for DMA_MEMORY_MA)
>>> added MEMREMAP_WC for DMA_MEMORY_MAP. If, however, CPU cache can be used on
>>> DMA_MEMORY_MAP, I think MEMREMAP_WC can be changed to MEMREMAP_WB. On my local
>>> ARM device, memset in dma_alloc_from_coherent sometimes takes much longer with
>>> MEMREMAP_WC compared to MEMREMAP_WB.
>>>
>>> Test results on AArch64 by allocating 4MB with putting trace_printk right
>>> before and after memset.
>>> MEMREMAP_WC : 11.0ms, 5.7ms, 4.2ms, 4.9ms, 5.4ms, 4.3ms, 3.5ms
>>> MEMREMAP_WB : 0.7ms, 0.6ms, 0.6ms, 0.6ms, 0.6ms, 0.5ms, 0.4 ms
>>>
>>
>> This doesn't look like a good idea to me. The point of coherent memory
>> is to have it non-cached, however WB will make writes hit the cache.
>>
>> Writing to the cache is of course faster than writing to RAM, but
>> that's not what we want to do here.
>>
>> -Brian
>>
>Hi Brian
>
>Thank you for your comment.
>If allocated memory will be used by TZ side, however, I think cacheable
>also can be used to be fast on memset in dma_alloc_from_coherent.
Are you trying to share the buffer between the secure and non-secure
worlds on the CPU? In that case, I don't think caching really helps
you. I'm not a TZ expert, but I believe the two worlds can never
share cached data.
If you want the secure world to see the non-secure world's data, as
far as I know you will need to clean the cache in the non-secure world
to make sure the secure world can see it (and vice-versa). I'd expect
this to remove most of the speed advantage of using WB in the first
place, except for some possible speedup from more efficient bursting.
If you're sharing the buffer with other DMA masters, regardless of
secure/non-secure you're not going to want WB mappings.
>How do you think to add another flag to distinguish this case?
You could look into the streaming DMA API. It will depend on the exact
implementation, but at some point you're still going to have to pay
the penalty of syncing the CPU and device.
-Brian
>>> Signed-off-by: Jaewon Kim <jaewon31.kim@samsung.com>
>>> ---
>>> drivers/base/dma-coherent.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
>>> index 640a7e6..0512a1d 100644
>>> --- a/drivers/base/dma-coherent.c
>>> +++ b/drivers/base/dma-coherent.c
>>> @@ -33,7 +33,7 @@ static bool dma_init_coherent_memory(
>>> goto out;
>>>
>>> if (flags & DMA_MEMORY_MAP)
>>> - mem_base = memremap(phys_addr, size, MEMREMAP_WC);
>>> + mem_base = memremap(phys_addr, size, MEMREMAP_WB);
>>> else
>>> mem_base = ioremap(phys_addr, size);
>>> if (!mem_base)
>>> --
>>> 1.9.1
>>>
>>
>>
>>
>
--
To unsubscribe, send a message with 'unsubscribe linux-mm' in
the body to majordomo@kvack.org. For more info on Linux MM,
see: http://www.linux-mm.org/ .
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^ permalink raw reply
* Re: [PATCH] [RFC] drivers: dma-coherent: use MEMREMAP_WB instead of MEMREMAP_WC
From: Brian Starkey @ 2016-11-09 10:23 UTC (permalink / raw)
To: Jaewon Kim; +Cc: linux-mm, linux-kernel
In-Reply-To: <5822F0AE.30101@samsung.com>
Hi,
On Wed, Nov 09, 2016 at 06:47:26PM +0900, Jaewon Kim wrote:
>
>
>On 2016년 11월 09일 18:27, Brian Starkey wrote:
>> Hi Jaewon,
>>
>> On Wed, Nov 09, 2016 at 06:10:09PM +0900, Jaewon Kim wrote:
>>> Commit 6b03ae0d42bf (drivers: dma-coherent: use MEMREMAP_WC for DMA_MEMORY_MA)
>>> added MEMREMAP_WC for DMA_MEMORY_MAP. If, however, CPU cache can be used on
>>> DMA_MEMORY_MAP, I think MEMREMAP_WC can be changed to MEMREMAP_WB. On my local
>>> ARM device, memset in dma_alloc_from_coherent sometimes takes much longer with
>>> MEMREMAP_WC compared to MEMREMAP_WB.
>>>
>>> Test results on AArch64 by allocating 4MB with putting trace_printk right
>>> before and after memset.
>>> MEMREMAP_WC : 11.0ms, 5.7ms, 4.2ms, 4.9ms, 5.4ms, 4.3ms, 3.5ms
>>> MEMREMAP_WB : 0.7ms, 0.6ms, 0.6ms, 0.6ms, 0.6ms, 0.5ms, 0.4 ms
>>>
>>
>> This doesn't look like a good idea to me. The point of coherent memory
>> is to have it non-cached, however WB will make writes hit the cache.
>>
>> Writing to the cache is of course faster than writing to RAM, but
>> that's not what we want to do here.
>>
>> -Brian
>>
>Hi Brian
>
>Thank you for your comment.
>If allocated memory will be used by TZ side, however, I think cacheable
>also can be used to be fast on memset in dma_alloc_from_coherent.
Are you trying to share the buffer between the secure and non-secure
worlds on the CPU? In that case, I don't think caching really helps
you. I'm not a TZ expert, but I believe the two worlds can never
share cached data.
If you want the secure world to see the non-secure world's data, as
far as I know you will need to clean the cache in the non-secure world
to make sure the secure world can see it (and vice-versa). I'd expect
this to remove most of the speed advantage of using WB in the first
place, except for some possible speedup from more efficient bursting.
If you're sharing the buffer with other DMA masters, regardless of
secure/non-secure you're not going to want WB mappings.
>How do you think to add another flag to distinguish this case?
You could look into the streaming DMA API. It will depend on the exact
implementation, but at some point you're still going to have to pay
the penalty of syncing the CPU and device.
-Brian
>>> Signed-off-by: Jaewon Kim <jaewon31.kim@samsung.com>
>>> ---
>>> drivers/base/dma-coherent.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
>>> index 640a7e6..0512a1d 100644
>>> --- a/drivers/base/dma-coherent.c
>>> +++ b/drivers/base/dma-coherent.c
>>> @@ -33,7 +33,7 @@ static bool dma_init_coherent_memory(
>>> goto out;
>>>
>>> if (flags & DMA_MEMORY_MAP)
>>> - mem_base = memremap(phys_addr, size, MEMREMAP_WC);
>>> + mem_base = memremap(phys_addr, size, MEMREMAP_WB);
>>> else
>>> mem_base = ioremap(phys_addr, size);
>>> if (!mem_base)
>>> --
>>> 1.9.1
>>>
>>
>>
>>
>
^ permalink raw reply
* Re: [Qemu-devel] [PATCH V10] fsdev: add IO throttle support to fsdev devices
From: Alberto Garcia @ 2016-11-09 10:23 UTC (permalink / raw)
To: Pradeep Jagadeesh, Aneesh Kumar K.V, Greg Kurz
Cc: Pradeep Jagadeesh, qemu-devel, Claudio Fontana
In-Reply-To: <1478685040-2035-1-git-send-email-pradeep.jagadeesh@huawei.com>
On Wed 09 Nov 2016 10:50:40 AM CET, Pradeep Jagadeesh wrote:
> Uses throttling APIs to limit I/O bandwidth and number of operations
> on the devices which use 9p-local driver.
>
> Signed-off-by: Pradeep Jagadeesh <pradeep.jagadeesh@huawei.com>
It looks good now, thanks!
> +void fsdev_throttle_parse_opts(QemuOpts *opts, FsThrottle *fst, Error **err)
> +{
[...]
> + throttle_is_valid(&fst->cfg, err);
> +}
Following the QEMU conventions, I would still rename 'err' to 'errp' in
this function (since it's an Error **).
Otherwise,
Reviewed-by: Alberto Garcia <berto@igalia.com>
Berto
^ permalink raw reply
* Re: [PATCH 1/2] drm/amdgpu: always un-gate UVD REGS path.
From: StDenis, Tom @ 2016-11-09 10:23 UTC (permalink / raw)
To: Zhu, Rex; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
In-Reply-To: <1478686135-21055-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 1584 bytes --]
You could do that as
WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
Unless you need 'data' somewhere else in the function.
Tom
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Wednesday, November 9, 2016 05:08
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 1/2] drm/amdgpu: always un-gate UVD REGS path.
Change-Id: I910a79b551a9b79b635161bb42ac123a23783225
Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index d2c96f1..d686946 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -596,7 +596,10 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
bool sw_mode)
{
u32 tmp, tmp2;
+ u32 data = RREG32(mmUVD_CGC_GATE);
+ data &= ~UVD_CGC_GATE__REGS_MASK;
+ WREG32(mmUVD_CGC_GATE, data);
tmp = RREG32(mmUVD_CGC_CTRL);
tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
--
1.9.1
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