* [U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster
From: Hans de Goede @ 2016-11-09 10:38 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161109102136.13479-1-wens@csie.org>
Hi,
On 09-11-16 11:21, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series adds basic PSCI support for the A80 to enable SMP on the
> first cluster. This at least allows people to use more than one core.
> The term "basic" is used because the series does not add support for
> multi-cluster cache and power management.
>
> The PSCI code is based on existing code for all the single cluster
> SoCs, and the kernel patches for MCPM SMP I did some time ago.
>
> Unfortunately only SMP works at this time. The last patch does not
> actually work. While the system is indeed booted non-secure, tested
> by trying to write to secure SRAM and the results not sticking, reads
> from the GIC CPU interface shows that it's still returning the secure
> copy of registers, and since we use a secure monitor FIQ to do core
> power down, the FIQ gets passed to the kernel. The patch is included
> so people with in-depth ARM knowledge could probably help work out
> what is wrong.
Cools stuff, when I find some time I will review and merge
patches 1-9 to sunxi-next.
First a question though, do you see any chance that merging this might
get in the way of enabling support for both clusters in the future?
Since the interface between u-boot and the kernel here is well defined
(and outside our control) I guess in the worst case, we would need to
revert some bits of this series from u-boot if they turn out to be non
suitable, right?
Regards,
Hans
>
>
> Regards
> ChenYu
>
> Chen-Yu Tsai (10):
> ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80
> sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80
> sunxi: Add base address of secure SRAM B for sun9i/A80
> sunxi: Use secure SRAM B for secure RAM for sun9i/A80
> sunxi: Add PRCM register definition for sun9i/A80
> sunxi: Add CPUCFG register definitions for sun9i/A80
> sunxi: Add support for TZPC on sun9i/A80
> sunxi: Add basic PSCI implementation for A80
> sunxi: Enable PSCI on sun9i/A80
> sunxi: Add PSCI core power off support for A80's first cluster
>
> arch/arm/cpu/armv7/Kconfig | 1 +
> arch/arm/cpu/armv7/sunxi/Makefile | 5 +
> arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 322 +++++++++++++++++++++++++
> arch/arm/cpu/armv7/sunxi/tzpc.c | 6 +
> arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 5 +
> arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 51 ++++
> arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 +++++
> arch/arm/include/asm/arch-sunxi/tzpc.h | 4 +
> arch/arm/mach-sunxi/board.c | 3 +-
> board/sunxi/Kconfig | 4 +
> include/configs/sun9i.h | 4 +
> 11 files changed, 459 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c
> create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
> create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h
>
^ permalink raw reply
* Re: [PATCH v2 2/5] drm/i915: More assorted dev_priv cleanups
From: David Weinehall @ 2016-11-09 10:38 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
In-Reply-To: <1478510960-31566-1-git-send-email-tvrtko.ursulin@linux.intel.com>
On Mon, Nov 07, 2016 at 09:29:20AM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> A small selection of macros which can only accept dev_priv from
> now on and a resulting trickle of fixups.
>
> v2: Keep original order. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 24 ++++++++++++------------
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 6 +++---
> drivers/gpu/drm/i915/intel_crt.c | 8 ++++----
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/intel_hotplug.c | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 8 files changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 45a30f730216..c56d6cf73219 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2901,24 +2901,24 @@ struct drm_i915_cmd_table {
> #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
> !(IS_I915G(dev_priv) || \
> IS_I915GM(dev_priv)))
> -#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
> -#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
> +#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
> +#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
>
> -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> -#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> -#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
> +#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> +#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
> +#define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
>
> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>
> -#define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
> +#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
>
> -#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
> -#define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
> -#define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p)
> +#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
> +#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
> +#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
> +#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
>
> -#define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
> +#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
>
> #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
> #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d430b9441e6b..35b13f178b61 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -573,7 +573,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> pdev->subsystem_device);
> err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>
> - if (HAS_CSR(dev)) {
> + if (HAS_CSR(dev_priv)) {
> struct intel_csr *csr = &dev_priv->csr;
>
> err_printf(m, "DMC loaded: %s\n",
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6d7505b5c5e7..285ee1e4352a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3678,7 +3678,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
> int pipe;
>
> - if (I915_HAS_HOTPLUG(dev)) {
> + if (I915_HAS_HOTPLUG(dev_priv)) {
> i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> }
> @@ -3712,7 +3712,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
> I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
> I915_USER_INTERRUPT;
>
> - if (I915_HAS_HOTPLUG(dev)) {
> + if (I915_HAS_HOTPLUG(dev_priv)) {
> i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> POSTING_READ(PORT_HOTPLUG_EN);
>
> @@ -3880,7 +3880,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
> int pipe;
>
> - if (I915_HAS_HOTPLUG(dev)) {
> + if (I915_HAS_HOTPLUG(dev_priv)) {
> i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> }
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 30eb95b54dcf..fed61958ffd4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -693,7 +693,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
> power_domain = intel_display_port_power_domain(intel_encoder);
> intel_display_power_get(dev_priv, power_domain);
>
> - if (I915_HAS_HOTPLUG(dev)) {
> + if (I915_HAS_HOTPLUG(dev_priv)) {
> /* We can not rely on the HPD pin always being correctly wired
> * up, for example many KVM do not pass it through, and so
> * only trust an assertion that the monitor is connected.
> @@ -715,7 +715,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
> * broken monitor (without edid) to work behind a broken kvm (that fails
> * to have the right resistors for HP detection) needs to fix this up.
> * For now just bail out. */
> - if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
> + if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
> status = connector_status_disconnected;
> goto out;
> }
> @@ -915,7 +915,7 @@ void intel_crt_init(struct drm_device *dev)
> crt->base.disable = intel_disable_crt;
> }
> crt->base.enable = intel_enable_crt;
> - if (I915_HAS_HOTPLUG(dev) &&
> + if (I915_HAS_HOTPLUG(dev_priv) &&
> !dmi_check_system(intel_spurious_crt_detect))
> crt->base.hpd_pin = HPD_CRT;
> if (HAS_DDI(dev_priv)) {
> @@ -932,7 +932,7 @@ void intel_crt_init(struct drm_device *dev)
>
> drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
>
> - if (!I915_HAS_HOTPLUG(dev))
> + if (!I915_HAS_HOTPLUG(dev_priv))
> intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 92ab01f33208..3a3b97ae6b10 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8438,7 +8438,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> }
> }
>
> - if (HAS_PIPE_CXSR(dev)) {
> + if (HAS_PIPE_CXSR(dev_priv)) {
> if (intel_crtc->lowfreq_avail) {
> DRM_DEBUG_KMS("enabling CxSR downclocking\n");
> pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
> @@ -15643,7 +15643,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> } else if (IS_GEN2(dev_priv))
> intel_dvo_init(dev);
>
> - if (SUPPORTS_TV(dev))
> + if (SUPPORTS_TV(dev_priv))
> intel_tv_init(dev);
>
> intel_psr_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d4e9cf3ad26e..4c9981ccfc23 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5742,7 +5742,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> }
>
> /* init MST on ports that can support it */
> - if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
> + if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
> (port == PORT_B || port == PORT_C || port == PORT_D))
> intel_dp_mst_encoder_init(intel_dig_port,
> intel_connector->base.base.id);
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
> index 334d47b5811a..3d546c019de0 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -501,7 +501,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
> if (intel_connector->mst_port)
> continue;
>
> - if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
> + if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) &&
> intel_connector->encoder->hpd_pin > HPD_NONE) {
> connector->polled = enabled ?
> DRM_CONNECTOR_POLL_CONNECT |
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 271a3e29ff23..41e6e920d9d7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -427,7 +427,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>
> - if (!HAS_PSR(dev)) {
> + if (!HAS_PSR(dev_priv)) {
> DRM_DEBUG_KMS("PSR not supported on this platform\n");
> return;
> }
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: [PATCH 3/5] drm/i915: Further assorted dev_priv cleanups
From: David Weinehall @ 2016-11-09 10:38 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
In-Reply-To: <1478270568-7902-4-git-send-email-tvrtko.ursulin@linux.intel.com>
On Fri, Nov 04, 2016 at 02:42:46PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> A small selection of macros which can only accept dev_priv from
> now on and a resulting trickle of fixups.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 12 ++++++------
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_guc_loader.c | 10 +++++-----
> 4 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6060e41d25e5..f392b0fb9b86 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2700,7 +2700,7 @@ struct drm_i915_cmd_table {
> #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
>
> #define REVID_FOREVER 0xff
> -#define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
> +#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
>
> #define GEN_FOREVER (0)
> /*
> @@ -2925,13 +2925,13 @@ struct drm_i915_cmd_table {
> * command submission once loaded. But these are logically independent
> * properties, so we have separate macros to test them.
> */
> -#define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
> -#define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
> -#define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
> +#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
> +#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> +#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
>
> -#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
> +#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
>
> -#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
> +#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff00
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 9c7d9c88d879..f98921174161 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1616,7 +1616,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> }
>
> if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
> - if (!HAS_RESOURCE_STREAMER(dev)) {
> + if (!HAS_RESOURCE_STREAMER(dev_priv)) {
> DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
> return -EINVAL;
> }
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 285ee1e4352a..cb8a75f6ca16 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4145,7 +4145,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
> INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
>
> - if (HAS_GUC_SCHED(dev))
> + if (HAS_GUC_SCHED(dev_priv))
> dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
>
> /* Let's track the enabled rps events */
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 1aa85236b788..34d6ad2cf7c1 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -566,7 +566,7 @@ int intel_guc_setup(struct drm_device *dev)
> ret = 0;
> }
>
> - if (err == 0 && !HAS_GUC_UCODE(dev))
> + if (err == 0 && !HAS_GUC_UCODE(dev_priv))
> ; /* Don't mention the GuC! */
> else if (err == 0)
> DRM_INFO("GuC firmware load skipped\n");
> @@ -725,18 +725,18 @@ void intel_guc_init(struct drm_device *dev)
> struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> const char *fw_path;
>
> - if (!HAS_GUC(dev)) {
> + if (!HAS_GUC(dev_priv)) {
> i915.enable_guc_loading = 0;
> i915.enable_guc_submission = 0;
> } else {
> /* A negative value means "use platform default" */
> if (i915.enable_guc_loading < 0)
> - i915.enable_guc_loading = HAS_GUC_UCODE(dev);
> + i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
> if (i915.enable_guc_submission < 0)
> - i915.enable_guc_submission = HAS_GUC_SCHED(dev);
> + i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
> }
>
> - if (!HAS_GUC_UCODE(dev)) {
> + if (!HAS_GUC_UCODE(dev_priv)) {
> fw_path = NULL;
> } else if (IS_SKYLAKE(dev_priv)) {
> fw_path = I915_SKL_GUC_UCODE;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: [PATCH -v4 1/8] locking/drm: Kill mutex trickery
From: Peter Zijlstra @ 2016-11-09 10:38 UTC (permalink / raw)
To: Linus Torvalds, Waiman Long, Jason Low, Ding Tianhong,
Thomas Gleixner, Will Deacon, Ingo Molnar, Imre Deak,
Linux Kernel Mailing List, Davidlohr Bueso, Tim Chen, Terry Rudd,
Paul E. McKenney
Cc: Chris Wilson, Daniel Vetter, Rob Clark
In-Reply-To: <20161007154351.GL3117@twins.programming.kicks-ass.net>
On Fri, Oct 07, 2016 at 05:43:51PM +0200, Peter Zijlstra wrote:
> On Fri, Oct 07, 2016 at 04:52:44PM +0200, Peter Zijlstra wrote:
> > Poking at lock internals is not cool. Since I'm going to change the
> > implementation this will break, take it out.
>
>
> So something like the below would serve as a replacement for your
> previous hacks. Is this API something acceptable to people?
Compile tested only.. Daniel reminded me in another thread.
---
Subject: locking/mutex,drm: Introduce mutex_trylock_recursive()
From: Peter Zijlstra <peterz@infradead.org>
Date: Fri, 7 Oct 2016 17:43:51 +0200
By popular DRM demand, introduce mutex_trylock_recursive() to fix up the
two GEM users.
Without this it is very easy for these drivers to get stuck in
low-memory situations and trigger OOM. Work is in progress to remove the
need for this in at least i915.
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
drivers/gpu/drm/i915/i915_gem_shrinker.c | 15 ++++++++++++---
drivers/gpu/drm/msm/msm_gem_shrinker.c | 16 ++++++++++++----
include/linux/mutex.h | 31 +++++++++++++++++++++++++++++++
scripts/checkpatch.pl | 6 ++++++
4 files changed, 61 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index e9bd2a81d03a..5543d993a50e 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -227,11 +227,20 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv)
static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
{
- if (!mutex_trylock(&dev->struct_mutex))
+ switch (mutex_trylock_recursive(&dev->struct_mutex)) {
+ case MUTEX_TRYLOCK_FAILED:
return false;
- *unlock = true;
- return true;
+ case MUTEX_TRYLOCK_SUCCESS:
+ *unlock = true;
+ return true;
+
+ case MUTEX_TRYLOCK_RECURSIVE:
+ *unlock = false;
+ return true;
+ }
+
+ BUG();
}
static unsigned long
diff --git a/drivers/gpu/drm/msm/msm_gem_shrinker.c b/drivers/gpu/drm/msm/msm_gem_shrinker.c
index 6d2e885bd58e..62b8cc653823 100644
--- a/drivers/gpu/drm/msm/msm_gem_shrinker.c
+++ b/drivers/gpu/drm/msm/msm_gem_shrinker.c
@@ -20,13 +20,21 @@
static bool msm_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
{
- if (!mutex_trylock(&dev->struct_mutex))
+ switch (mutex_trylock_recursive(&dev->struct_mutex)) {
+ case MUTEX_TRYLOCK_FAILED:
return false;
- *unlock = true;
- return true;
-}
+ case MUTEX_TRYLOCK_SUCCESS:
+ *unlock = true;
+ return true;
+ case MUTEX_TRYLOCK_RECURSIVE:
+ *unlock = false;
+ return true;
+ }
+
+ BUG();
+}
static unsigned long
msm_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
diff --git a/include/linux/mutex.h b/include/linux/mutex.h
index 4d3bccabbea5..6a902f0a2148 100644
--- a/include/linux/mutex.h
+++ b/include/linux/mutex.h
@@ -189,4 +189,35 @@ extern void mutex_unlock(struct mutex *lock);
extern int atomic_dec_and_mutex_lock(atomic_t *cnt, struct mutex *lock);
+/*
+ * These values are chosen such that FAIL and SUCCESS match the
+ * values of the regular mutex_trylock().
+ */
+enum mutex_trylock_recursive_enum {
+ MUTEX_TRYLOCK_FAILED = 0,
+ MUTEX_TRYLOCK_SUCCESS = 1,
+ MUTEX_TRYLOCK_RECURSIVE,
+};
+
+/**
+ * mutex_trylock_recursive - trylock variant that allows recursive locking
+ * @lock: mutex to be locked
+ *
+ * This function should not be used, _ever_. It is purely for hysterical GEM
+ * raisins, and once those are gone this will be removed.
+ *
+ * Returns:
+ * MUTEX_TRYLOCK_FAILED - trylock failed,
+ * MUTEX_TRYLOCK_SUCCESS - lock acquired,
+ * MUTEX_TRYLOCK_RECURSIVE - we already owned the lock.
+ */
+static inline __deprecated __must_check enum mutex_trylock_recursive_enum
+mutex_trylock_recursive(struct mutex *lock)
+{
+ if (unlikely(__mutex_owner(lock) == current))
+ return MUTEX_TRYLOCK_RECURSIVE;
+
+ return mutex_trylock(lock);
+}
+
#endif /* __LINUX_MUTEX_H */
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index a8368d1c4348..23f462f64a3f 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -6076,6 +6076,12 @@ sub process {
}
}
+# check for mutex_trylock_recursive usage
+ if ($line =~ /mutex_trylock_recursive/) {
+ ERROR("LOCKING",
+ "recursive locking is bad, do not use this ever.\n" . $herecurr);
+ }
+
# check for lockdep_set_novalidate_class
if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ ||
$line =~ /__lockdep_no_validate__\s*\)/ ) {
^ permalink raw reply related
* Re: [PATCH 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
From: David Weinehall @ 2016-11-09 10:38 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
In-Reply-To: <1478270568-7902-5-git-send-email-tvrtko.ursulin@linux.intel.com>
On Fri, Nov 04, 2016 at 02:42:47PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> After this patch only conversion of INTEL_INFO(p)->gen to
> INTEL_GEN(dev_priv) remains before the __I915__ macro can
> be removed.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_color.c | 31 ++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++---------------
> drivers/gpu/drm/i915/intel_fbdev.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_pm.c | 7 ++++---
> 6 files changed, 39 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 79cea49183b3..35940192e569 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev)
> /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
> * (which really amounts to a PCH but no South Display).
> */
> - if (INTEL_INFO(dev)->num_pipes == 0) {
> + if (INTEL_INFO(dev_priv)->num_pipes == 0) {
> dev_priv->pch_type = PCH_NOP;
> return;
> }
> @@ -607,7 +607,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>
> intel_modeset_gem_init(dev);
>
> - if (INTEL_INFO(dev)->num_pipes == 0)
> + if (INTEL_INFO(dev_priv)->num_pipes == 0)
> return 0;
>
> ret = intel_fbdev_init(dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cad6de65947d..b98f11735c5b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -714,7 +714,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
> */
> static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
> {
> - ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
> + ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
> }
>
> /* Removes entries from a single page table, releasing it if it's empty.
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 445108855275..3784940a4e7a 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -345,11 +345,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
> static void broadwell_load_luts(struct drm_crtc_state *state)
> {
> struct drm_crtc *crtc = state->crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> - uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> + uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>
> if (crtc_state_is_legacy(state)) {
> haswell_load_luts(state);
> @@ -428,8 +427,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
> static void cherryview_load_luts(struct drm_crtc_state *state)
> {
> struct drm_crtc *crtc = state->crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> struct drm_color_lut *lut;
> uint32_t i, lut_size;
> @@ -446,7 +444,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>
> if (state->degamma_lut) {
> lut = (struct drm_color_lut *) state->degamma_lut->data;
> - lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> + lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> for (i = 0; i < lut_size; i++) {
> /* Write LUT in U0.14 format. */
> word0 =
> @@ -461,7 +459,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>
> if (state->gamma_lut) {
> lut = (struct drm_color_lut *) state->gamma_lut->data;
> - lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
> + lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> for (i = 0; i < lut_size; i++) {
> /* Write LUT in U0.10 format. */
> word0 =
> @@ -497,12 +495,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state)
> int intel_color_check(struct drm_crtc *crtc,
> struct drm_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> size_t gamma_length, degamma_length;
>
> - degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
> + degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
> sizeof(struct drm_color_lut);
> - gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
> + gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
> sizeof(struct drm_color_lut);
>
> /*
> @@ -529,8 +527,7 @@ int intel_color_check(struct drm_crtc *crtc,
>
> void intel_color_init(struct drm_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>
> drm_mode_crtc_set_gamma_size(crtc, 256);
>
> @@ -549,10 +546,10 @@ void intel_color_init(struct drm_crtc *crtc)
> }
>
> /* Enable color management support when we have degamma & gamma LUTs. */
> - if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
> - INTEL_INFO(dev)->color.gamma_lut_size != 0)
> + if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
> + INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
> drm_crtc_enable_color_mgmt(crtc,
> - INTEL_INFO(dev)->color.degamma_lut_size,
> - true,
> - INTEL_INFO(dev)->color.gamma_lut_size);
> + INTEL_INFO(dev_priv)->color.degamma_lut_size,
> + true,
> + INTEL_INFO(dev_priv)->color.gamma_lut_size);
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bf8099ed0b20..aad264583378 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7057,7 +7057,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> }
> }
>
> - if (INTEL_INFO(dev)->num_pipes == 2)
> + if (INTEL_INFO(dev_priv)->num_pipes == 2)
> return 0;
>
> /* Ivybridge 3 pipe is really complicated */
> @@ -14706,8 +14706,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> {
> struct intel_atomic_state *intel_state =
> to_intel_atomic_state(new_state->state);
> - struct drm_device *dev = plane->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct drm_framebuffer *fb = new_state->fb;
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> @@ -14764,7 +14763,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> }
>
> if (plane->type == DRM_PLANE_TYPE_CURSOR &&
> - INTEL_INFO(dev)->cursor_needs_physical) {
> + INTEL_INFO(dev_priv)->cursor_needs_physical) {
> int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
> ret = i915_gem_object_attach_phys(obj, align);
> if (ret) {
> @@ -14797,7 +14796,7 @@ void
> intel_cleanup_plane_fb(struct drm_plane *plane,
> struct drm_plane_state *old_state)
> {
> - struct drm_device *dev = plane->dev;
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct intel_plane_state *old_intel_state;
> struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
> struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
> @@ -14808,7 +14807,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
> return;
>
> if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
> - !INTEL_INFO(dev)->cursor_needs_physical))
> + !INTEL_INFO(dev_priv)->cursor_needs_physical))
> intel_unpin_fb_obj(old_state->fb, old_state->rotation);
> }
>
> @@ -15133,13 +15132,13 @@ intel_update_cursor_plane(struct drm_plane *plane,
> {
> struct drm_crtc *crtc = crtc_state->base.crtc;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct drm_device *dev = plane->dev;
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
> uint32_t addr;
>
> if (!obj)
> addr = 0;
> - else if (!INTEL_INFO(dev)->cursor_needs_physical)
> + else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
> addr = i915_gem_object_ggtt_offset(obj, NULL);
> else
> addr = obj->phys_handle->busaddr;
> @@ -16421,7 +16420,7 @@ int intel_modeset_init(struct drm_device *dev)
>
> intel_init_pm(dev_priv);
>
> - if (INTEL_INFO(dev)->num_pipes == 0)
> + if (INTEL_INFO(dev_priv)->num_pipes == 0)
> return 0;
>
> /*
> @@ -16467,8 +16466,8 @@ int intel_modeset_init(struct drm_device *dev)
> dev->mode_config.fb_base = ggtt->mappable_base;
>
> DRM_DEBUG_KMS("%d display pipe%s available.\n",
> - INTEL_INFO(dev)->num_pipes,
> - INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
> + INTEL_INFO(dev_priv)->num_pipes,
> + INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
>
> for_each_pipe(dev_priv, pipe) {
> int ret;
> @@ -16556,11 +16555,10 @@ static void intel_enable_pipe_a(struct drm_device *dev)
> static bool
> intel_check_plane_mapping(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 val;
>
> - if (INTEL_INFO(dev)->num_pipes == 1)
> + if (INTEL_INFO(dev_priv)->num_pipes == 1)
> return true;
>
> val = I915_READ(DSPCNTR(!crtc->plane));
> @@ -17313,7 +17311,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
> if (!error)
> return;
>
> - err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
> + err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> err_printf(m, "PWR_WELL_CTL2: %08x\n",
> error->power_well_driver);
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> index b7098f98bb67..e3cf655bec3b 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -359,7 +359,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
> struct drm_fb_offset *offsets,
> bool *enabled, int width, int height)
> {
> - struct drm_device *dev = fb_helper->dev;
> + struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
> unsigned long conn_configured, mask;
> unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
> int i, j;
> @@ -512,7 +512,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
> * fbdev helper library.
> */
> if (num_connectors_enabled != num_connectors_detected &&
> - num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
> + num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
> DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
> DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
> num_connectors_detected);
> @@ -700,11 +700,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
>
> int intel_fbdev_init(struct drm_device *dev)
> {
> - struct intel_fbdev *ifbdev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_fbdev *ifbdev;
> int ret;
>
> - if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
> + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
> return -ENODEV;
>
> ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
> @@ -717,7 +717,7 @@ int intel_fbdev_init(struct drm_device *dev)
> ifbdev->preferred_bpp = 32;
>
> ret = drm_fb_helper_init(dev, &ifbdev->helper,
> - INTEL_INFO(dev)->num_pipes, 4);
> + INTEL_INFO(dev_priv)->num_pipes, 4);
> if (ret) {
> kfree(ifbdev);
> return ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 88e28c989b9c..4512069e4555 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1061,7 +1061,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
>
> for (level = 0; level < wm_state->num_levels; level++) {
> struct drm_device *dev = crtc->base.dev;
> - const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> + const int sr_fifo_size =
> + INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
> struct intel_plane *plane;
>
> wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
> @@ -1093,7 +1094,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct vlv_wm_state *wm_state = &crtc->wm_state;
> struct intel_plane *plane;
> - int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> + int sr_fifo_size = INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
> int level;
>
> memset(wm_state, 0, sizeof(*wm_state));
This function now contains 3 cases of to_i915(dev) and only one case
that actually uses dev directly. How about rewriting it as converting to
dev_priv only once and instead getting dev from dev_priv->drm?
> @@ -1920,7 +1921,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
>
> /* HSW allows LP1+ watermarks even with multiple pipes */
> if (level == 0 || config->num_pipes_active > 1) {
> - fifo_size /= INTEL_INFO(dev)->num_pipes;
> + fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
>
> /*
> * For some reason the non self refresh
Regards, David
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [PATCH] drm/i915/gvt: Disable access to stolen memory as a guest
From: Chris Wilson @ 2016-11-09 10:39 UTC (permalink / raw)
To: intel-gfx
Explicitly disable stolen memory when running as a guest in a virtual
machine, since the memory is not mediated between clients and reserved
entirely for the host. The actual size should be reported as zero, but
like every other quirk we want to tell the user what is happening.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 154fbb04419f..0f0b37cad63d 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -417,6 +417,11 @@ int i915_gem_init_stolen(struct drm_device *dev)
mutex_init(&dev_priv->mm.stolen_lock);
+ if (intel_vgpu_active(dev_priv)) {
+ DRM_INFO("iGVT-g active, disabling use of stolen memory\n");
+ return 0;
+ }
+
#ifdef CONFIG_INTEL_IOMMU
if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) {
DRM_INFO("DMAR active, disabling use of stolen memory\n");
--
2.10.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* Re: [PATCH 5/5] drm/i915: Convert i915_drv.c to INTEL_GEN
From: David Weinehall @ 2016-11-09 10:39 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
In-Reply-To: <1478270568-7902-6-git-send-email-tvrtko.ursulin@linux.intel.com>
On Fri, Nov 04, 2016 at 02:42:48PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 35940192e569..096c368bda0b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -374,12 +374,12 @@ static int
> intel_alloc_mchbar_resource(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> + int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> u32 temp_lo, temp_hi = 0;
> u64 mchbar_addr;
> int ret;
>
> - if (INTEL_INFO(dev)->gen >= 4)
> + if (INTEL_GEN(dev_priv) >= 4)
> pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
> pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
> mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
> @@ -406,7 +406,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
> return ret;
> }
>
> - if (INTEL_INFO(dev)->gen >= 4)
> + if (INTEL_GEN(dev_priv) >= 4)
> pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
> upper_32_bits(dev_priv->mch_res.start));
>
> @@ -420,7 +420,7 @@ static void
> intel_setup_mchbar(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> + int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> u32 temp;
> bool enabled;
>
> @@ -460,7 +460,7 @@ static void
> intel_teardown_mchbar(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> + int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>
> if (dev_priv->mchbar_need_disable) {
> if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
> @@ -879,7 +879,7 @@ static int i915_mmio_setup(struct drm_device *dev)
> * the register BAR remains the same size for all the earlier
> * generations up to Ironlake.
> */
> - if (INTEL_INFO(dev)->gen < 5)
> + if (INTEL_GEN(dev_priv) < 5)
> mmio_size = 512 * 1024;
> else
> mmio_size = 2 * 1024 * 1024;
> @@ -1512,7 +1512,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
> * Fujitsu FSC S7110
> * Acer Aspire 1830T
> */
> - if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
> + if (!(hibernation && INTEL_GEN(dev_priv) < 6))
> pci_set_power_state(pdev, PCI_D3hot);
>
> dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [Buildroot] [PATCH 1/4] configs: atmel: at91sam9260eknf: update defconfig
From: Ludovic Desroches @ 2016-11-09 10:39 UTC (permalink / raw)
To: buildroot
In-Reply-To: <20161109112550.36c1ec17@free-electrons.com>
On Wed, Nov 09, 2016 at 11:25:50AM +0100, Thomas Petazzoni wrote:
> Hello,
>
> On Wed, 9 Nov 2016 11:10:09 +0100, Ludovic Desroches wrote:
>
> > > Why enable both U-Boot and Barebox?
> > >
> >
> > I don't know why Barebox was selected but the 'official' bootloader is
> > U-Boot for all our products that's why I add it. I kept Barebox because
> > it was already selected and I don't know if someone is still using it or
> > not.
>
> But the end result is a defconfig that doesn't make any sense.
>
> Please provide a defconfig that makes sense, and with an updated
> readme.txt if you decide to change the bootloader (and therefore the
> flashing instructions).
>
> > > > # Kernel
> > > > BR2_LINUX_KERNEL=y
> > > > -BR2_LINUX_KERNEL_CUSTOM_VERSION=y
> > > > -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.9.1"
> > >
> > > For the sake of reproducibility you should set this to the version you tested,
> > > say, 4.8.6. The same goes for other patches in this series.
> >
> > As Alexandre said, we don't want to spend time for the maintainance of these
> > old boards so sticking to the mainline seems to be the way to go. Giving a
> > version is a kind of commitment but we no longer perform tests on these
> > boards excepting kernel boot with kernelci.
>
> That's not Buildroot policy. We want defconfigs with fixed kernel and
> bootloader versions, so that we know they have been tested.
>
> If you are not able/willing to test those defconfigs, then we could
> just as well remove them. But I'm not going to merge a defconfig that
> doesn't comply with our policy of having a fixed kernel and a fixed
> bootloader version.
>
Can I use a fixed version of the compiler too? It seems it makes sense
because this defconfig was tested but is no more compiling.
Regards
Ludovic
> Best regards,
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply
* Re: module: When modifying a module's text ignore modules which are going away too
From: Jessica Yu @ 2016-11-09 10:40 UTC (permalink / raw)
To: Aaron Tomlin; +Cc: Steven Rostedt, linux-kernel, rusty
In-Reply-To: <20161107114629.GB16093@atomlin.usersys.redhat.com>
+++ Aaron Tomlin [07/11/16 11:46 +0000]:
>Hi Jessica,
>
>Any thoughts?
Hi Aaron,
Thanks for your patience as I slowly work through a large swath of emails :-)
Anyway, this looks fine to me. A going module's text should be (or
soon will be) rw anyway, so checking for going modules in the ro
case should be enough.
Rusty, if you give your ack for the second patch, I can apply both
patches to my modules-next branch. I'll also incorporate Steven's
suggestion for a comment explaining why going modules shouldn't be
converted to ro in this context.
Thanks,
Jessica
^ permalink raw reply
* Re: [Qemu-devel] virsh dump (qemu guest memory dump?): KASLR enabled linux guest support
From: Andrew Jones @ 2016-11-09 10:40 UTC (permalink / raw)
To: Dave Young; +Cc: wency, qiaonuohan, anderson, lersek, qemu-devel, bhe
In-Reply-To: <20161109030146.GA3802@dhcp-128-65.nay.redhat.com>
On Wed, Nov 09, 2016 at 11:01:46AM +0800, Dave Young wrote:
> Hi,
>
> Latest linux kernel enabled kaslr to randomiz phys/virt memory
> addresses, we had some effort to support kexec/kdump so that crash
> utility can still works in case crashed kernel has kaslr enabled.
>
> But according to Dave Anderson virsh dump does not work, quoted messages
> from Dave below:
>
> """
> with virsh dump, there's no way of even knowing that KASLR
> has randomized the kernel __START_KERNEL_map region, because there is no
> virtual address information -- e.g., like "SYMBOL(_stext)" in the kdump
> vmcoreinfo data to compare against the vmlinux file symbol value.
> Unless virsh dump can export some basic virtual memory data, which
> they say it can't, I don't see how KASLR can ever be supported.
> """
>
> I assume virsh dump is using qemu guest memory dump facility so it
> should be first addressed in qemu. Thus post this query to qemu devel
> list. If this is not correct please let me know.
>
> Could you qemu dump people make it work? Or we can not support virt dump
> as long as KASLR being enabled. Latest Fedora kernel has enabled it in x86_64.
>
When the -kernel command line option is used, then it may be possible
to extract some information that could be used to supplement the memory
dump that dump-guest-memory provides. However, that would be a specific
use. In general, QEMU knows nothing about the guest kernel. It doesn't
know where it is in the disk image, and it doesn't even know if it's
Linux.
Is there anything a guest userspace application could probe from e.g.
/proc that would work? If so, then the guest agent could gain a new
feature providing that.
Thanks,
drew
^ permalink raw reply
* Re: [v5] ath9k: Switch to using mac80211 intermediate software queues.
From: Toke Høiland-Jørgensen @ 2016-11-09 10:42 UTC (permalink / raw)
To: Tim Shepard; +Cc: Kalle Valo, make-wifi-fast, linux-wireless, Felix Fietkau
In-Reply-To: <E1c4IsV-0003Rk-00@www.xplot.org>
Tim Shepard <shep@alum.mit.edu> writes:
>> While at it, could you also add to the commit log some info how awesome this
>> patch is from user's point of view and how it helps. For example, before and
>> and after numbers and other results.
>
> That varies wildly, depending on many details of the scenario
> (including the wireless capabilities of the clients connected to the
> AP using this patch, and how far away those clients are). There's
> really not enough room in a commit message to explain enough to make
> any such claimed numbers reproducible.
I disagree; it's quite straightforward to demonstrate a gain from this
on an ath9k access point. And while of course the mac80211 queues is the
reason for this, the commit that uses it (i.e. this one) can explain
that and include some numbers. I'll add that and resend :)
-Toke
^ permalink raw reply
* [PATCH v2] mtd/spi-nor: Add SPI memory controllers for Aspeed SoCs
From: Cédric Le Goater @ 2016-11-09 10:42 UTC (permalink / raw)
To: linux-mtd
Cc: Mark Rutland, Boris Brezillon, devicetree, Richard Weinberger,
Marek Vasut, Rob Herring, Joel Stanley, Cyrille Pitchen,
Brian Norris, David Woodhouse, Cédric Le Goater
This driver adds mtd support for spi-nor attached to either or both of
the Firmware Memory Controller or the SPI Flash Controller (AST2400
only).
The SMC controllers on the Aspeed AST2500 SoC are very similar to the
ones found on the AST2400. The differences are on the number of
supported flash modules and their default mappings in the SoC address
space.
The Aspeed AST2500 has one SPI controller for the BMC firmware and two
for the host firmware. All controllers have now the same set of
registers compatible with the AST2400 FMC controller and the legacy
'SMC' controller is fully gone.
Each controller has a memory range on which it maps its flash module
slaves. Each slave is assigned a memory window for its mapping that
can be changed at bootime with the Segment Address Register.
Each SPI flash slave can then be accessed in two modes: Command and
User. When in User mode, accesses to the memory segment of the slaves
are translated in SPI transfers. When in Command mode, the HW
generates the SPI commands automatically and the memory segment is
accessed as if doing a MMIO.
Currently, only the User mode is supported. Command mode needs a
little more work to check that the memory window on the AHB bus fits
the module size.
Based on previous work from Milton D. Miller II <miltonm@us.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
Tested on:
* OpenPOWER Palmetto (AST2400) with
FMC controller : n25q256a
SPI controller : mx25l25635e and n25q512ax3
* Evaluation board (AST2500) with
FMC controller : w25q256
SPI controller : w25q256
* OpenPOWER Witherspoon (AST2500) with
FMC controller : mx25l25635e * 2
SPI controller : mx66l1g45g
Changes since v2:
- added a set4b ops to handle difference in the controllers
- simplified the IO routines
- prepared for fast read using dummy cycles
Work in progress:
- read optimization using higher SPI clock frequencies
- command mode to direct reads from AHB
- DMA support
.../devicetree/bindings/mtd/aspeed-smc.txt | 72 ++
drivers/mtd/spi-nor/Kconfig | 12 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/aspeed-smc.c | 783 +++++++++++++++++++++
4 files changed, 868 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/aspeed-smc.txt
create mode 100644 drivers/mtd/spi-nor/aspeed-smc.c
diff --git a/Documentation/devicetree/bindings/mtd/aspeed-smc.txt b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt
new file mode 100644
index 000000000000..7516b0c01fcf
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt
@@ -0,0 +1,72 @@
+* Aspeed Static Memory controller
+* Aspeed SPI Flash Controller
+
+The Static memory controller in the ast2400 supports 5 chip selects
+each can be attached to NAND, parallel NOR, or SPI NOR attached flash.
+The Firmware Memory Controller in the ast2500 supports 3 chip selects,
+two of which are always in SPI-NOR mode and the third can be SPI-NOR
+or parallel flash. The SPI flash controller in the ast2400 supports
+one of 2 chip selects selected by pinmux. The two SPI flash
+controllers in the ast2500 each support two chip selects.
+
+Required properties:
+ - compatible : Should be one of
+ "aspeed,ast2400-fmc" for the AST2400 Static Memory Controller
+ "aspeed,ast2400-smc" for the AST2400 SPI Flash Controller
+ "aspeed,ast2500-fmc" for the AST2500 Firmware SPI Memory Controller
+ "aspeed,ast2500-smc" for the AST2500 SPI Flash Controllers
+ - reg : the first contains the control register location and length,
+ the second contains the memory window mapping address and length
+ - #address-cells : must be 1 corresponding to chip select child binding
+ - #size-cells : must be 0 corresponding to chip select child binding
+
+Optional properties:
+ - interrupts : Should contain the interrupt for the dma device if an fmc
+
+The child nodes are the SPI Flash modules which must have a compatible
+property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Optionally, the child node can contain properties for SPI mode (may be
+ignored):
+ - spi-max-frequency - (optional) max frequency of spi bus
+
+
+Example:
+fmc: fmc@1e620000 {
+ compatible = "aspeed,ast2400-fmc";
+ reg = < 0x1e620000 0x94
+ 0x20000000 0x02000000
+ 0x22000000 0x02000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <19>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+ /* spi-max-frequency = <>; */
+ /* m25p,fast-read; */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ boot@0 {
+ label = "boot-loader";
+ reg = < 0 0x8000 >;
+ };
+ image@8000 {
+ label = "kernel-image";
+ reg = < 0x8000 0x1f8000 >;
+ };
+ };
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor" ;
+ label = "alt";
+ /* spi-max-frequency = <>; */
+ status = "fail";
+ /* m25p,fast-read; */
+ };
+};
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 4a682ee0f632..96148600fdab 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -76,4 +76,16 @@ config SPI_NXP_SPIFI
Flash. Enable this option if you have a device with a SPIFI
controller and want to access the Flash as a mtd device.
+config ASPEED_FLASH_SPI
+ tristate "Aspeed flash controllers in SPI mode"
+ depends on HAS_IOMEM && OF
+ depends on ARCH_ASPEED || COMPILE_TEST
+ # IO_SPACE_LIMIT must be equivalent to (~0UL)
+ depends on !NEED_MACH_IO_H
+ help
+ This enables support for the New Static Memory Controller
+ (FMC) in the Aspeed SoCs (AST2400 and AST2500) when attached
+ to SPI nor chips, and support for the SPI Memory controller
+ (SPI) for the BIOS.
+
endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 121695e83542..c3174ebc45c2 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -4,4 +4,5 @@ obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
+obj-$(CONFIG_ASPEED_FLASH_SPI) += aspeed-smc.o
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
new file mode 100644
index 000000000000..30662daf89ca
--- /dev/null
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -0,0 +1,783 @@
+/*
+ * ASPEED Static Memory Controller driver
+ *
+ * Copyright (c) 2015-2016, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/spi-nor.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/sysfs.h>
+
+#define DEVICE_NAME "aspeed-smc"
+
+/*
+ * In user mode all data bytes read or written to the chip decode address
+ * range are transferred to or from the SPI bus. The range is treated as a
+ * fifo of arbitratry 1, 2, or 4 byte width but each write has to be aligned
+ * to its size. The address within the multiple 8kB range is ignored when
+ * sending bytes to the SPI bus.
+ *
+ * On the arm architecture, as of Linux version 4.3, memcpy_fromio and
+ * memcpy_toio on little endian targets use the optimized memcpy routines
+ * that were designed for well behavied memory storage. These routines
+ * have a stutter if the source and destination are not both word aligned,
+ * once with a duplicate access to the source after aligning to the
+ * destination to a word boundary, and again with a duplicate access to
+ * the source when the final byte count is not word aligned.
+ *
+ * When writing or reading the fifo this stutter discards data or sends
+ * too much data to the fifo and can not be used by this driver.
+ *
+ * While the low level io string routines that implement the insl family do
+ * the desired accesses and memory increments, the cross architecture io
+ * macros make them essentially impossible to use on a memory mapped address
+ * instead of a a token from the call to iomap of an io port.
+ *
+ * These fifo routines use readl and friends to a constant io port and update
+ * the memory buffer pointer and count via explicit code. The final updates
+ * to len are optimistically suppressed.
+ */
+static int aspeed_smc_read_from_ahb(void *buf, const void __iomem *src,
+ size_t len)
+{
+ if ((((unsigned long)src | (unsigned long)buf | len) & 3) == 0) {
+ while (len > 3) {
+ *(u32 *)buf = readl(src);
+ buf += 4;
+ src += 4;
+ len -= 4;
+ }
+ }
+
+ while (len--) {
+ *(u8 *)buf = readb(src);
+ buf += 1;
+ src += 1;
+ }
+ return 0;
+}
+
+static int aspeed_smc_write_to_ahb(void __iomem *dst, const void *buf,
+ size_t len)
+{
+ if ((((unsigned long)dst | (unsigned long)buf | len) & 3) == 0) {
+ while (len > 3) {
+ u32 val = *(u32 *)buf;
+
+ writel(val, dst);
+ buf += 4;
+ dst += 4;
+ len -= 4;
+ }
+ }
+
+ while (len--) {
+ u8 val = *(u8 *)buf;
+
+ writeb(val, dst);
+ buf += 1;
+ dst += 1;
+ }
+ return 0;
+}
+
+enum smc_flash_type {
+ smc_type_nor = 0, /* controller connected to nor flash */
+ smc_type_nand = 1, /* controller connected to nand flash */
+ smc_type_spi = 2, /* controller connected to spi flash */
+};
+
+struct aspeed_smc_chip;
+
+struct aspeed_smc_info {
+ u32 maxsize; /* maximum size of 1 chip window */
+ u8 nce; /* number of chip enables */
+ u8 maxwidth; /* max width of spi bus */
+ bool hastype; /* flash type field exists in cfg reg */
+ u8 we0; /* shift for write enable bit for ce 0 */
+ u8 ctl0; /* offset in regs of ctl for ce 0 */
+ u8 time; /* offset in regs of timing */
+ u8 misc; /* offset in regs of misc settings */
+
+ void (*set_4b)(struct aspeed_smc_chip *chip);
+};
+
+static void aspeed_smc_chip_set_4b_smc_2400(struct aspeed_smc_chip *chip);
+static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip);
+
+static const struct aspeed_smc_info fmc_2400_info = {
+ .maxsize = 64 * 1024 * 1024,
+ .nce = 5,
+ .maxwidth = 4,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .time = 0x94,
+ .misc = 0x54,
+ .set_4b = aspeed_smc_chip_set_4b,
+};
+
+static const struct aspeed_smc_info smc_2400_info = {
+ .maxsize = 64 * 1024 * 1024,
+ .nce = 1,
+ .maxwidth = 2,
+ .hastype = false,
+ .we0 = 0,
+ .ctl0 = 0x04,
+ .time = 0x14,
+ .misc = 0x10,
+ .set_4b = aspeed_smc_chip_set_4b_smc_2400,
+};
+
+static const struct aspeed_smc_info fmc_2500_info = {
+ .maxsize = 256 * 1024 * 1024,
+ .nce = 3,
+ .maxwidth = 2,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .time = 0x94,
+ .misc = 0x54,
+ .set_4b = aspeed_smc_chip_set_4b,
+};
+
+static const struct aspeed_smc_info smc_2500_info = {
+ .maxsize = 128 * 1024 * 1024,
+ .nce = 2,
+ .maxwidth = 2,
+ .hastype = false,
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .time = 0x94,
+ .misc = 0x54,
+ .set_4b = aspeed_smc_chip_set_4b,
+};
+
+enum smc_ctl_reg_value {
+ smc_base, /* base value without mode for other commands */
+ smc_read, /* command reg for (maybe fast) reads */
+ smc_write, /* command reg for writes with timings */
+ smc_num_ctl_reg_values /* last value to get count of commands */
+};
+
+struct aspeed_smc_controller;
+
+struct aspeed_smc_chip {
+ int cs;
+ struct aspeed_smc_controller *controller;
+ __le32 __iomem *ctl; /* control register */
+ void __iomem *base; /* base of chip window */
+ __le32 ctl_val[smc_num_ctl_reg_values]; /* controls with timing */
+ enum smc_flash_type type; /* what type of flash */
+ struct spi_nor nor;
+};
+
+struct aspeed_smc_controller {
+ struct device *dev;
+
+ struct mutex mutex; /* controller access mutex */
+ const struct aspeed_smc_info *info; /* type info of controller */
+ void __iomem *regs; /* controller registers */
+ void __iomem *windows; /* per-chip windows resource */
+
+ struct aspeed_smc_chip *chips[0]; /* pointers to attached chips */
+};
+
+/*
+ * SPI Flash Configuration Register (AST2400 SPI)
+ */
+#define CONFIG_REG 0x0
+#define CONFIG_ENABLE_CE_INACTIVE BIT(1)
+#define CONFIG_WRITE BIT(0)
+
+/*
+ * SPI Flash Configuration Register (AST2500 SPI)
+ * Type setting Register (AST2500 FMC and AST2400 FMC)
+ */
+#define TYPE_SETTING_REG 0x0
+#define CONFIG_DISABLE_LEGACY BIT(31) /* 1 on AST2500 FMC */
+
+#define CONFIG_CE2_WRITE BIT(18)
+#define CONFIG_CE1_WRITE BIT(17)
+#define CONFIG_CE0_WRITE BIT(16)
+
+#define CONFIG_CE2_TYPE BIT(4) /* FMC only */
+#define CONFIG_CE1_TYPE BIT(2) /* FMC only */
+#define CONFIG_CE0_TYPE BIT(0) /* FMC only */
+
+/*
+ * CE Control Register (AST2500 SPI,FMC and AST2400 FMC)
+ */
+#define CE_CONTROL_REG 0x4
+#define CE2_ENABLE_CE_INACTIVE BIT(10)
+#define CE1_ENABLE_CE_INACTIVE BIT(9)
+#define CE0_ENABLE_CE_INACTIVE BIT(8)
+#define CE2_CONTROL_EXTENDED BIT(2)
+#define CE1_CONTROL_EXTENDED BIT(1)
+#define CE0_CONTROL_EXTENDED BIT(0)
+
+/* CE0 Control Register (depends on the controller type) */
+#define CONTROL_SPI_AAF_MODE BIT(31)
+#define CONTROL_SPI_IO_MODE_MASK GENMASK(30, 28)
+#define CONTROL_SPI_IO_DUAL_DATA BIT(29)
+#define CONTROL_SPI_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28))
+#define CONTROL_SPI_IO_QUAD_DATA BIT(30)
+#define CONTROL_SPI_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28))
+#define CONTROL_SPI_CE_INACTIVE_SHIFT 24
+#define CONTROL_SPI_CE_INACTIVE_MASK GENMASK(27, CONTROL_SPI_CE_INACTIVE_SHIFT)
+/* 0 = 16T ... 15 = 1T T=HCLK */
+#define CONTROL_SPI_COMMAND_SHIFT 16
+#define CONTROL_SPI_DUMMY_CYCLE_COMMAND_OUTPUT BIT(15)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_HI BIT(14)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_HI_SHIFT 14
+#define CONTROL_SPI_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */
+#define CONTROL_SPI_CLK_DIV4 BIT(13) /* others */
+#define CONTROL_SPI_RW_MERGE BIT(12)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_LO_SHIFT 6
+#define CONTROL_SPI_IO_DUMMY_CYCLES_LO GENMASK(7, \
+ CONTROL_SPI_IO_DUMMY_CYCLES_LO_SHIFT)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_MASK (CONTROL_SPI_IO_DUMMY_CYCLES_HI | \
+ CONTROL_SPI_IO_DUMMY_CYCLES_LO)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_SET(dummy) \
+ (((((dummy) >> 2) & 0x1) << CONTROL_SPI_IO_DUMMY_CYCLES_HI_SHIFT) | \
+ (((dummy) & 0x3) << CONTROL_SPI_IO_DUMMY_CYCLES_LO_SHIFT))
+
+#define CONTROL_SPI_CLOCK_FREQ_SEL_SHIFT 8
+#define CONTROL_SPI_CLOCK_FREQ_SEL_MASK GENMASK(11, \
+ CONTROL_SPI_CLOCK_FREQ_SEL_SHIFT)
+#define CONTROL_SPI_LSB_FIRST BIT(5)
+#define CONTROL_SPI_CLOCK_MODE_3 BIT(4)
+#define CONTROL_SPI_IN_DUAL_DATA BIT(3)
+#define CONTROL_SPI_CE_STOP_ACTIVE_CONTROL BIT(2)
+#define CONTROL_SPI_COMMAND_MODE_MASK GENMASK(1, 0)
+#define CONTROL_SPI_COMMAND_MODE_NORMAL (0)
+#define CONTROL_SPI_COMMAND_MODE_FREAD (1)
+#define CONTROL_SPI_COMMAND_MODE_WRITE (2)
+#define CONTROL_SPI_COMMAND_MODE_USER (3)
+
+#define CONTROL_SPI_KEEP_MASK (CONTROL_SPI_AAF_MODE | \
+ CONTROL_SPI_CE_INACTIVE_MASK | CONTROL_SPI_CLK_DIV4 | \
+ CONTROL_SPI_IO_DUMMY_CYCLES_MASK | CONTROL_SPI_CLOCK_FREQ_SEL_MASK | \
+ CONTROL_SPI_LSB_FIRST | CONTROL_SPI_CLOCK_MODE_3)
+
+/* Segment Address Registers */
+#define SEGMENT_ADDR_REG0 0x30
+#define SEGMENT_ADDR_START(_r) ((((_r) >> 16) & 0xFF) << 23)
+#define SEGMENT_ADDR_END(_r) ((((_r) >> 24) & 0xFF) << 23)
+
+static u32 spi_control_fill_opcode(u8 opcode)
+{
+ return ((u32)(opcode)) << CONTROL_SPI_COMMAND_SHIFT;
+}
+
+static inline u32 aspeed_smc_chip_write_bit(struct aspeed_smc_chip *chip)
+{
+ return ((u32)1 << (chip->controller->info->we0 + chip->cs));
+}
+
+static void aspeed_smc_chip_check_config(struct aspeed_smc_chip *chip)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ u32 reg;
+
+ reg = readl(controller->regs + CONFIG_REG);
+
+ if (!(reg & aspeed_smc_chip_write_bit(chip))) {
+ dev_dbg(controller->dev,
+ "config write is not set ! @%p: 0x%08x\n",
+ controller->regs + CONFIG_REG, reg);
+ reg |= aspeed_smc_chip_write_bit(chip);
+ writel(reg, controller->regs + CONFIG_REG);
+ }
+}
+
+static void aspeed_smc_start_user(struct spi_nor *nor)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+ u32 ctl = chip->ctl_val[smc_base];
+
+ /*
+ * When the chip is controlled in user mode, we need write
+ * access to send the opcodes to it. So check the config.
+ */
+ aspeed_smc_chip_check_config(chip);
+
+ ctl |= CONTROL_SPI_COMMAND_MODE_USER |
+ CONTROL_SPI_CE_STOP_ACTIVE_CONTROL;
+ writel(ctl, chip->ctl);
+
+ ctl &= ~CONTROL_SPI_CE_STOP_ACTIVE_CONTROL;
+ writel(ctl, chip->ctl);
+}
+
+static void aspeed_smc_stop_user(struct spi_nor *nor)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ u32 ctl = chip->ctl_val[smc_read];
+ u32 ctl2 = ctl | CONTROL_SPI_COMMAND_MODE_USER |
+ CONTROL_SPI_CE_STOP_ACTIVE_CONTROL;
+
+ writel(ctl2, chip->ctl); /* stop user CE control */
+ writel(ctl, chip->ctl); /* default to fread or read */
+}
+
+static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ mutex_lock(&chip->controller->mutex);
+
+ aspeed_smc_start_user(nor);
+ aspeed_smc_write_to_ahb(chip->base, &opcode, 1);
+ aspeed_smc_read_from_ahb(buf, chip->base, len);
+ aspeed_smc_stop_user(nor);
+
+ mutex_unlock(&chip->controller->mutex);
+
+ return 0;
+}
+
+static int aspeed_smc_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ int len)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ mutex_lock(&chip->controller->mutex);
+
+ aspeed_smc_start_user(nor);
+ aspeed_smc_write_to_ahb(chip->base, &opcode, 1);
+ aspeed_smc_write_to_ahb(chip->base, buf, len);
+ aspeed_smc_stop_user(nor);
+
+ mutex_unlock(&chip->controller->mutex);
+
+ return 0;
+}
+
+static void aspeed_smc_send_cmd_addr(struct spi_nor *nor, u8 cmd, u32 addr)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+ __be32 temp;
+ u32 cmdaddr;
+
+ switch (nor->addr_width) {
+ default:
+ WARN_ONCE(1, "Unexpected address width %u, defaulting to 3\n",
+ nor->addr_width);
+ /* FALLTHROUGH */
+ case 3:
+ cmdaddr = addr & 0xFFFFFF;
+
+ cmdaddr |= (u32)cmd << 24;
+
+ temp = cpu_to_be32(cmdaddr);
+ aspeed_smc_write_to_ahb(chip->base, &temp, 4);
+ break;
+ case 4:
+ temp = cpu_to_be32(addr);
+ aspeed_smc_write_to_ahb(chip->base, &cmd, 1);
+ aspeed_smc_write_to_ahb(chip->base, &temp, 4);
+ break;
+ }
+}
+
+static ssize_t aspeed_smc_read_user(struct spi_nor *nor, loff_t from,
+ size_t len, u_char *read_buf)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ mutex_lock(&chip->controller->mutex);
+
+ aspeed_smc_start_user(nor);
+ aspeed_smc_send_cmd_addr(nor, nor->read_opcode, from);
+ aspeed_smc_read_from_ahb(read_buf, chip->base, len);
+ aspeed_smc_stop_user(nor);
+
+ mutex_unlock(&chip->controller->mutex);
+
+ return len;
+}
+
+static ssize_t aspeed_smc_write_user(struct spi_nor *nor, loff_t to, size_t len,
+ const u_char *write_buf)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ mutex_lock(&chip->controller->mutex);
+
+ aspeed_smc_start_user(nor);
+ aspeed_smc_send_cmd_addr(nor, nor->program_opcode, to);
+ aspeed_smc_write_to_ahb(chip->base, write_buf, len);
+ aspeed_smc_stop_user(nor);
+
+ mutex_unlock(&chip->controller->mutex);
+
+ return len;
+}
+
+static int aspeed_smc_remove(struct platform_device *dev)
+{
+ struct aspeed_smc_chip *chip;
+ struct aspeed_smc_controller *controller = platform_get_drvdata(dev);
+ int n;
+
+ for (n = 0; n < controller->info->nce; n++) {
+ chip = controller->chips[n];
+ if (chip)
+ mtd_device_unregister(&chip->nor.mtd);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id aspeed_smc_matches[] = {
+ { .compatible = "aspeed,ast2400-fmc", .data = &fmc_2400_info },
+ { .compatible = "aspeed,ast2400-smc", .data = &smc_2400_info },
+ { .compatible = "aspeed,ast2500-fmc", .data = &fmc_2500_info },
+ { .compatible = "aspeed,ast2500-smc", .data = &smc_2500_info },
+ { }
+};
+MODULE_DEVICE_TABLE(of, aspeed_smc_matches);
+
+static struct platform_device *
+of_platform_device_create_or_find(struct device_node *child,
+ struct device *parent)
+{
+ struct platform_device *cdev;
+
+ cdev = of_platform_device_create(child, NULL, parent);
+ if (!cdev)
+ cdev = of_find_device_by_node(child);
+ return cdev;
+}
+
+static void __iomem *window_start(struct aspeed_smc_controller *controller,
+ struct resource *r, unsigned int n)
+{
+ u32 offset = 0;
+ u32 reg;
+
+ if (controller->info->nce > 1) {
+ reg = readl(controller->regs + SEGMENT_ADDR_REG0 + n * 4);
+
+ if (SEGMENT_ADDR_START(reg) >= SEGMENT_ADDR_END(reg))
+ return NULL;
+
+ offset = SEGMENT_ADDR_START(reg) - r->start;
+ }
+
+ return controller->windows + offset;
+}
+
+static void aspeed_smc_chip_enable_write(struct aspeed_smc_chip *chip)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ u32 reg;
+
+ reg = readl(controller->regs + CONFIG_REG);
+
+ reg |= aspeed_smc_chip_write_bit(chip);
+ writel(reg, controller->regs + CONFIG_REG);
+}
+
+static void aspeed_smc_chip_set_type(struct aspeed_smc_chip *chip, int type)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ u32 reg;
+
+ reg = readl(controller->regs + CONFIG_REG);
+
+ chip->type = type;
+
+ reg &= ~(3 << (chip->cs * 2));
+ reg |= chip->type << (chip->cs * 2);
+ writel(reg, controller->regs + CONFIG_REG);
+}
+
+/*
+ * The AST2500 FMC and AST2400 FMC flash controllers should be
+ * strapped by hardware, or autodetected, but the AST2500 SPI flash
+ * needs to be set.
+ */
+static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ u32 reg;
+
+ if (chip->controller->info == &smc_2500_info) {
+ reg = readl(controller->regs + CE_CONTROL_REG);
+ reg |= 1 << chip->cs;
+ writel(reg, controller->regs + CE_CONTROL_REG);
+ }
+}
+
+/*
+ * The AST2400 SPI flash controller does not have a CE Control
+ * register. It uses the CE0 control register to set 4Byte mode at the
+ * controller level.
+ */
+static void aspeed_smc_chip_set_4b_smc_2400(struct aspeed_smc_chip *chip)
+{
+ chip->ctl_val[smc_base] |= CONTROL_SPI_IO_ADDRESS_4B;
+ chip->ctl_val[smc_read] |= CONTROL_SPI_IO_ADDRESS_4B;
+}
+
+static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip,
+ struct resource *r)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ const struct aspeed_smc_info *info = controller->info;
+ u32 reg, base_reg;
+
+ /*
+ * Always turn on the write enable bit to allow opcodes to be
+ * sent in user mode.
+ */
+ aspeed_smc_chip_enable_write(chip);
+
+ /* The driver only supports SPI type flash for the moment */
+ if (info->hastype)
+ aspeed_smc_chip_set_type(chip, smc_type_spi);
+
+ /*
+ * Configure chip base address in memory
+ */
+ chip->base = window_start(controller, r, chip->cs);
+ if (!chip->base) {
+ dev_warn(chip->nor.dev, "CE segment window closed.\n");
+ return -1;
+ }
+
+ /*
+ * Read the existing control register to get basic values.
+ *
+ * XXX This register probably needs more sanitation.
+ *
+ * Do we need support for mode 3 vs mode 0 clock phasing?
+ */
+ reg = readl(chip->ctl);
+ dev_dbg(controller->dev, "control register: %08x\n", reg);
+
+ base_reg = reg & CONTROL_SPI_KEEP_MASK;
+ if (base_reg != reg) {
+ dev_info(controller->dev,
+ "control register changed to: %08x\n",
+ base_reg);
+ }
+ chip->ctl_val[smc_base] = base_reg;
+
+ /*
+ * Retain the prior value of the control register as the
+ * default if it was normal access mode. Otherwise start with
+ * the sanitized base value set to read mode.
+ */
+ if ((reg & CONTROL_SPI_COMMAND_MODE_MASK) ==
+ CONTROL_SPI_COMMAND_MODE_NORMAL)
+ chip->ctl_val[smc_read] = reg;
+ else
+ chip->ctl_val[smc_read] = chip->ctl_val[smc_base] |
+ CONTROL_SPI_COMMAND_MODE_NORMAL;
+
+ dev_dbg(controller->dev, "default control register: %08x\n",
+ chip->ctl_val[smc_read]);
+ return 0;
+}
+
+static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ const struct aspeed_smc_info *info = controller->info;
+ u32 cmd;
+
+ if (chip->nor.addr_width == 4 && info->set_4b)
+ info->set_4b(chip);
+
+ /*
+ * base mode has not been optimized yet. use it for writes.
+ */
+ chip->ctl_val[smc_write] = chip->ctl_val[smc_base] |
+ spi_control_fill_opcode(chip->nor.program_opcode) |
+ CONTROL_SPI_COMMAND_MODE_WRITE;
+
+ dev_dbg(controller->dev, "write control register: %08x\n",
+ chip->ctl_val[smc_write]);
+
+ /*
+ * XXX TODO
+ * Adjust clocks if fast read and write are supported.
+ * Interpret spi-nor flags to adjust controller settings.
+ * Check if resource size big enough for detected chip and
+ * add support assisted (normal or fast-) read and dma.
+ */
+ switch (chip->nor.flash_read) {
+ case SPI_NOR_NORMAL:
+ cmd = CONTROL_SPI_COMMAND_MODE_NORMAL;
+ break;
+ case SPI_NOR_FAST:
+ cmd = CONTROL_SPI_COMMAND_MODE_FREAD;
+ break;
+ default:
+ dev_err(chip->nor.dev, "unsupported SPI read mode\n");
+ return -EINVAL;
+ }
+
+ chip->ctl_val[smc_read] |= cmd |
+ CONTROL_SPI_IO_DUMMY_CYCLES_SET(chip->nor.read_dummy / 8);
+
+ dev_dbg(controller->dev, "base control register: %08x\n",
+ chip->ctl_val[smc_read]);
+ return 0;
+}
+
+static int aspeed_smc_probe(struct platform_device *pdev)
+{
+ struct aspeed_smc_controller *controller;
+ const struct of_device_id *match;
+ const struct aspeed_smc_info *info;
+ struct resource *r;
+ struct device_node *child;
+ int err = 0;
+ unsigned int n;
+
+ match = of_match_device(aspeed_smc_matches, &pdev->dev);
+ if (!match || !match->data)
+ return -ENODEV;
+ info = match->data;
+
+ controller = devm_kzalloc(&pdev->dev, sizeof(*controller) +
+ info->nce * sizeof(controller->chips[0]), GFP_KERNEL);
+ if (!controller)
+ return -ENOMEM;
+ controller->info = info;
+
+ mutex_init(&controller->mutex);
+ platform_set_drvdata(pdev, controller);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ controller->regs = devm_ioremap_resource(&pdev->dev, r);
+ if (IS_ERR(controller->regs))
+ return PTR_ERR(controller->regs);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ controller->windows = devm_ioremap_resource(&pdev->dev, r);
+ if (IS_ERR(controller->windows))
+ return PTR_ERR(controller->windows);
+
+ controller->dev = &pdev->dev;
+
+ /* The pinmux or bootloader will disable the legacy mode controller */
+
+ /*
+ * XXX Need to add arbitration to the SMC (BIOS) controller if access
+ * is shared by the host.
+ */
+ for_each_available_child_of_node(controller->dev->of_node, child) {
+ struct platform_device *cdev;
+ struct aspeed_smc_chip *chip;
+
+ /* This version does not support nand or nor flash devices. */
+ if (!of_device_is_compatible(child, "jedec,spi-nor"))
+ continue;
+
+ /*
+ * create a platform device from the of node. If the device
+ * already was created (eg from a prior bind/unbind cycle)
+ * reuse it.
+ *
+ * The creating the device node for the child here allows its
+ * use for error reporting via dev_err below.
+ */
+ cdev = of_platform_device_create_or_find(child,
+ controller->dev);
+ if (!cdev)
+ continue;
+
+ err = of_property_read_u32(child, "reg", &n);
+ if (err == -EINVAL && info->nce == 1)
+ n = 0;
+ else if (err || n >= info->nce)
+ continue;
+ if (controller->chips[n]) {
+ dev_err(&cdev->dev,
+ "chip-id %u already in use in use by %s\n",
+ n, dev_name(controller->chips[n]->nor.dev));
+ continue;
+ }
+
+ chip = devm_kzalloc(controller->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ continue;
+ chip->controller = controller;
+ chip->ctl = controller->regs + info->ctl0 + n * 4;
+ chip->cs = n;
+
+ chip->nor.dev = &cdev->dev;
+ chip->nor.priv = chip;
+ spi_nor_set_flash_node(&chip->nor, child);
+ chip->nor.mtd.name = of_get_property(child, "label", NULL);
+ chip->nor.read = aspeed_smc_read_user;
+ chip->nor.write = aspeed_smc_write_user;
+ chip->nor.read_reg = aspeed_smc_read_reg;
+ chip->nor.write_reg = aspeed_smc_write_reg;
+
+ err = aspeed_smc_chip_setup_init(chip, r);
+ if (err)
+ continue;
+
+ /*
+ * XXX Add support for SPI_NOR_QUAD and SPI_NOR_DUAL attach
+ * when board support is present as determined by of property.
+ */
+ err = spi_nor_scan(&chip->nor, NULL, SPI_NOR_NORMAL);
+ if (err)
+ continue;
+
+ err = aspeed_smc_chip_setup_finish(chip);
+ if (err)
+ continue;
+
+ err = mtd_device_register(&chip->nor.mtd, NULL, 0);
+ if (err)
+ continue;
+ controller->chips[n] = chip;
+ }
+
+ /* Were any children registered? */
+ for (n = 0; n < info->nce; n++)
+ if (controller->chips[n])
+ break;
+
+ if (n == info->nce)
+ return -ENODEV;
+
+ return 0;
+}
+
+static struct platform_driver aspeed_smc_driver = {
+ .probe = aspeed_smc_probe,
+ .remove = aspeed_smc_remove,
+ .driver = {
+ .name = DEVICE_NAME,
+ .of_match_table = aspeed_smc_matches,
+ }
+};
+
+module_platform_driver(aspeed_smc_driver);
+
+MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
+MODULE_AUTHOR("Milton Miller");
+MODULE_LICENSE("GPL v2");
--
2.7.4
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
From: Laurent Pinchart @ 2016-11-09 10:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Niklas Söderlund, Geert Uytterhoeven, Linus Walleij,
Linux-Renesas, linux-gpio@vger.kernel.org
In-Reply-To: <CAMuHMdUhR8Kh-8XLSwPXDYf7S+UVQiGSE4esmQtAfs0Qo-paog@mail.gmail.com>
Hi Geert,
On Monday 07 Nov 2016 11:57:36 Geert Uytterhoeven wrote:
> On Thu, Nov 3, 2016 at 6:10 PM, Laurent Pinchart wrote:
> > On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
> >> There is a bug in the r8a7795 bias code where a WARN() is trigged
> >> anytime a pin from PUEN0/PUD0is accessed.
> >>
> >> # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
> >>
> >> WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> >>
> >> r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> >>
> >> Call trace:
> >> [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> >> [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> >> [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> >> [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> >> [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> >> [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> >> [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> >> [<ffff00000831a110>] full_proxy_read+0x58/0x88
> >> [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> >> [<ffff0000081d8874>] vfs_read+0x84/0x148
> >> [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> >> [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
> >>
> >> This is due to the WARN() check if the reg field of the pullups struct
> >> is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> >> registers. Change the layout of the pullups struct to embed the pin
> >> number inside the struct and loop over it to fetch the correct
> >> information or WARN() if no pin is found.
> >
> > This lowers the memory consumption at the cost of increased CPU usage.
> > Given that the get/set bias functions are not part of a critical path I'm
> > fine with that. We could possibly optimize the implementation by using a
> > dichotomic search, but I don't think that's needed at the moment.
>
> Alternatively, we could steal one bit from the "reg" bitifield to
> add a "present" bit, without increasing the table size:
That's an option too, but given how sparsely populated the table is at the
moment, I'd prefer lowering the memory consumption by moving the pin number in
the table and removing unused entries. The increase in CPU time could be
further limited by using a dichotomic search if needed.
> static const struct {
> u16 present : 1;
> u16 reg : 10;
> u16 bit : 5;
> } pullups[] = {
>
> While 10 bits is not sufficient in general (the PFC register block size
> is 0x50c), it's good enough to address the PUx registers. And if needed,
> we can switch from register byte offsets to register indices, indexing the
> 32-bit register file.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH 3/5] wic: check that filesystem is specified for a rootfs partition
From: Maciej Borzęcki @ 2016-11-09 10:42 UTC (permalink / raw)
To: Ed Bartosh
Cc: Maciej Borzecki, Patches and discussions about the oe-core layer
In-Reply-To: <20161109094451.GD10823@linux.intel.com>
On Wed, Nov 9, 2016 at 10:44 AM, Ed Bartosh <ed.bartosh@linux.intel.com> wrote:
> On Tue, Nov 08, 2016 at 04:56:09PM +0100, Maciej Borzecki wrote:
>> Signed-off-by: Maciej Borzecki <maciej.borzecki@rndity.com>
>> ---
>> scripts/lib/wic/partition.py | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/scripts/lib/wic/partition.py b/scripts/lib/wic/partition.py
>> index 8adc698240c8e3bd9f4118663a5d7a167e0bb4a4..24e657592738dc7c5cdff78e3740d7c373021e9d 100644
>> --- a/scripts/lib/wic/partition.py
>> +++ b/scripts/lib/wic/partition.py
>> @@ -184,6 +184,10 @@ class Partition():
>> if os.path.isfile(rootfs):
>> os.remove(rootfs)
>>
>> + if not self.fstype:
>> + msger.error("File system for partition %s not specified in kickstart, " \
>> + "use --fstype option" % (self.mountpoint))
>> +
> Would it make sense to make --fstype mandatory in ksparser?
I'm afraid that would make fstype mandatory in all cases, while we only
need it for rootfs source plugin.
--
Maciej Borzecki
RnDity
^ permalink raw reply
* [xen-unstable-coverity test] 102062: all pass - PUSHED
From: osstest service owner @ 2016-11-09 10:43 UTC (permalink / raw)
To: xen-devel, osstest-admin
[-- Attachment #1: Type: text/plain, Size: 6453 bytes --]
flight 102062 xen-unstable-coverity real [real]
http://logs.test-lab.xenproject.org/osstest/logs/102062/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
xen bcb13635fa503113c981c6ea7423f930c1548452
baseline version:
xen 3ebe9a1a826e8d569bef6045777cc01a5699933d
Last test of basis 101966 2016-11-06 09:19:06 Z 3 days
Testing same since 102062 2016-11-09 09:21:05 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Daniel De Graaf <dgdegra@tycho.nsa.gov>
Jan Beulich <jbeulich@suse.com>
Roger Pau Monne <roger.pau@citrix.com>
Roger Pau Monné <roger.pau@citrix.com>
Wei Liu <wei.liu2@citrix.com>
jobs:
coverity-amd64 pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Pushing revision :
+ branch=xen-unstable-coverity
+ revision=bcb13635fa503113c981c6ea7423f930c1548452
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
++++ getconfig Repos
++++ perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x '!=' x/home/osstest/repos/lock ']'
++ OSSTEST_REPOS_LOCK_LOCKED=/home/osstest/repos/lock
++ exec with-lock-ex -w /home/osstest/repos/lock ./ap-push xen-unstable-coverity bcb13635fa503113c981c6ea7423f930c1548452
+ branch=xen-unstable-coverity
+ revision=bcb13635fa503113c981c6ea7423f930c1548452
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
++++ getconfig Repos
++++ perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x/home/osstest/repos/lock '!=' x/home/osstest/repos/lock ']'
+ . ./cri-common
++ . ./cri-getconfig
++ umask 002
+ select_xenbranch
+ case "$branch" in
+ tree=xen
+ xenbranch=xen-unstable-coverity
+ qemuubranch=qemu-upstream-unstable-coverity
+ qemuubranch=qemu-upstream-unstable
+ '[' xxen = xlinux ']'
+ linuxbranch=
+ '[' xqemu-upstream-unstable = x ']'
+ select_prevxenbranch
++ ./cri-getprevxenbranch xen-unstable-coverity
+ prevxenbranch=xen-4.7-testing
+ '[' xbcb13635fa503113c981c6ea7423f930c1548452 = x ']'
+ : tested/2.6.39.x
+ . ./ap-common
++ : osstest@xenbits.xen.org
+++ getconfig OsstestUpstream
+++ perl -e '
use Osstest;
readglobalconfig();
print $c{"OsstestUpstream"} or die $!;
'
++ :
++ : git://xenbits.xen.org/xen.git
++ : osstest@xenbits.xen.org:/home/xen/git/xen.git
++ : git://xenbits.xen.org/qemu-xen-traditional.git
++ : git://git.kernel.org
++ : git://git.kernel.org/pub/scm/linux/kernel/git
++ : git
++ : git://xenbits.xen.org/xtf.git
++ : osstest@xenbits.xen.org:/home/xen/git/xtf.git
++ : git://xenbits.xen.org/xtf.git
++ : git://xenbits.xen.org/libvirt.git
++ : osstest@xenbits.xen.org:/home/xen/git/libvirt.git
++ : git://xenbits.xen.org/libvirt.git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : osstest@xenbits.xen.org:/home/xen/git/osstest/rumprun.git
++ : git://git.seabios.org/seabios.git
++ : osstest@xenbits.xen.org:/home/xen/git/osstest/seabios.git
++ : git://xenbits.xen.org/osstest/seabios.git
++ : https://github.com/tianocore/edk2.git
++ : osstest@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/linux-firmware.git
++ : osstest@xenbits.xen.org:/home/osstest/ext/linux-firmware.git
++ : git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
++ : osstest@xenbits.xen.org:/home/xen/git/linux-pvops.git
++ : git://xenbits.xen.org/linux-pvops.git
++ : tested/linux-3.14
++ : tested/linux-arm-xen
++ '[' xgit://xenbits.xen.org/linux-pvops.git = x ']'
++ '[' x = x ']'
++ : git://xenbits.xen.org/linux-pvops.git
++ : tested/linux-arm-xen
++ : git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen.git
++ : tested/2.6.39.x
++ : daily-cron.xen-unstable-coverity
++ : daily-cron.xen-unstable-coverity
++ : daily-cron.xen-unstable-coverity
++ : daily-cron.xen-unstable-coverity
++ : daily-cron.xen-unstable-coverity
++ : daily-cron.xen-unstable-coverity
++ : daily-cron.xen-unstable-coverity
++ : http://hg.uk.xensource.com/carbon/trunk/linux-2.6.27
++ : git://xenbits.xen.org/qemu-xen.git
++ : osstest@xenbits.xen.org:/home/xen/git/qemu-xen.git
++ : daily-cron.xen-unstable-coverity
++ : git://xenbits.xen.org/qemu-xen.git
++ : git://git.qemu.org/qemu.git
+ TREE_LINUX=osstest@xenbits.xen.org:/home/xen/git/linux-pvops.git
+ TREE_QEMU_UPSTREAM=osstest@xenbits.xen.org:/home/xen/git/qemu-xen.git
+ TREE_XEN=osstest@xenbits.xen.org:/home/xen/git/xen.git
+ TREE_LIBVIRT=osstest@xenbits.xen.org:/home/xen/git/libvirt.git
+ TREE_RUMPRUN=osstest@xenbits.xen.org:/home/xen/git/osstest/rumprun.git
+ TREE_SEABIOS=osstest@xenbits.xen.org:/home/xen/git/osstest/seabios.git
+ TREE_OVMF=osstest@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
+ TREE_XTF=osstest@xenbits.xen.org:/home/xen/git/xtf.git
+ info_linux_tree xen-unstable-coverity
+ case $1 in
+ return 1
+ case "$branch" in
+ cd /home/osstest/repos/xen
+ git push osstest@xenbits.xen.org:/home/xen/git/xen.git bcb13635fa503113c981c6ea7423f930c1548452:refs/heads/coverity-tested/smoke
To osstest@xenbits.xen.org:/home/xen/git/xen.git
3ebe9a1..bcb1363 bcb13635fa503113c981c6ea7423f930c1548452 -> coverity-tested/smoke
[-- Attachment #2: Type: text/plain, Size: 127 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply
* [PATCH v2] mtd/spi-nor: Add SPI memory controllers for Aspeed SoCs
From: Cédric Le Goater @ 2016-11-09 10:42 UTC (permalink / raw)
To: linux-mtd
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut,
Richard Weinberger, Cyrille Pitchen, devicetree, Rob Herring,
Mark Rutland, Joel Stanley, Cédric Le Goater
This driver adds mtd support for spi-nor attached to either or both of
the Firmware Memory Controller or the SPI Flash Controller (AST2400
only).
The SMC controllers on the Aspeed AST2500 SoC are very similar to the
ones found on the AST2400. The differences are on the number of
supported flash modules and their default mappings in the SoC address
space.
The Aspeed AST2500 has one SPI controller for the BMC firmware and two
for the host firmware. All controllers have now the same set of
registers compatible with the AST2400 FMC controller and the legacy
'SMC' controller is fully gone.
Each controller has a memory range on which it maps its flash module
slaves. Each slave is assigned a memory window for its mapping that
can be changed at bootime with the Segment Address Register.
Each SPI flash slave can then be accessed in two modes: Command and
User. When in User mode, accesses to the memory segment of the slaves
are translated in SPI transfers. When in Command mode, the HW
generates the SPI commands automatically and the memory segment is
accessed as if doing a MMIO.
Currently, only the User mode is supported. Command mode needs a
little more work to check that the memory window on the AHB bus fits
the module size.
Based on previous work from Milton D. Miller II <miltonm@us.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
Tested on:
* OpenPOWER Palmetto (AST2400) with
FMC controller : n25q256a
SPI controller : mx25l25635e and n25q512ax3
* Evaluation board (AST2500) with
FMC controller : w25q256
SPI controller : w25q256
* OpenPOWER Witherspoon (AST2500) with
FMC controller : mx25l25635e * 2
SPI controller : mx66l1g45g
Changes since v2:
- added a set4b ops to handle difference in the controllers
- simplified the IO routines
- prepared for fast read using dummy cycles
Work in progress:
- read optimization using higher SPI clock frequencies
- command mode to direct reads from AHB
- DMA support
.../devicetree/bindings/mtd/aspeed-smc.txt | 72 ++
drivers/mtd/spi-nor/Kconfig | 12 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/aspeed-smc.c | 783 +++++++++++++++++++++
4 files changed, 868 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/aspeed-smc.txt
create mode 100644 drivers/mtd/spi-nor/aspeed-smc.c
diff --git a/Documentation/devicetree/bindings/mtd/aspeed-smc.txt b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt
new file mode 100644
index 000000000000..7516b0c01fcf
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt
@@ -0,0 +1,72 @@
+* Aspeed Static Memory controller
+* Aspeed SPI Flash Controller
+
+The Static memory controller in the ast2400 supports 5 chip selects
+each can be attached to NAND, parallel NOR, or SPI NOR attached flash.
+The Firmware Memory Controller in the ast2500 supports 3 chip selects,
+two of which are always in SPI-NOR mode and the third can be SPI-NOR
+or parallel flash. The SPI flash controller in the ast2400 supports
+one of 2 chip selects selected by pinmux. The two SPI flash
+controllers in the ast2500 each support two chip selects.
+
+Required properties:
+ - compatible : Should be one of
+ "aspeed,ast2400-fmc" for the AST2400 Static Memory Controller
+ "aspeed,ast2400-smc" for the AST2400 SPI Flash Controller
+ "aspeed,ast2500-fmc" for the AST2500 Firmware SPI Memory Controller
+ "aspeed,ast2500-smc" for the AST2500 SPI Flash Controllers
+ - reg : the first contains the control register location and length,
+ the second contains the memory window mapping address and length
+ - #address-cells : must be 1 corresponding to chip select child binding
+ - #size-cells : must be 0 corresponding to chip select child binding
+
+Optional properties:
+ - interrupts : Should contain the interrupt for the dma device if an fmc
+
+The child nodes are the SPI Flash modules which must have a compatible
+property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Optionally, the child node can contain properties for SPI mode (may be
+ignored):
+ - spi-max-frequency - (optional) max frequency of spi bus
+
+
+Example:
+fmc: fmc@1e620000 {
+ compatible = "aspeed,ast2400-fmc";
+ reg = < 0x1e620000 0x94
+ 0x20000000 0x02000000
+ 0x22000000 0x02000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <19>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+ /* spi-max-frequency = <>; */
+ /* m25p,fast-read; */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ boot@0 {
+ label = "boot-loader";
+ reg = < 0 0x8000 >;
+ };
+ image@8000 {
+ label = "kernel-image";
+ reg = < 0x8000 0x1f8000 >;
+ };
+ };
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor" ;
+ label = "alt";
+ /* spi-max-frequency = <>; */
+ status = "fail";
+ /* m25p,fast-read; */
+ };
+};
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 4a682ee0f632..96148600fdab 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -76,4 +76,16 @@ config SPI_NXP_SPIFI
Flash. Enable this option if you have a device with a SPIFI
controller and want to access the Flash as a mtd device.
+config ASPEED_FLASH_SPI
+ tristate "Aspeed flash controllers in SPI mode"
+ depends on HAS_IOMEM && OF
+ depends on ARCH_ASPEED || COMPILE_TEST
+ # IO_SPACE_LIMIT must be equivalent to (~0UL)
+ depends on !NEED_MACH_IO_H
+ help
+ This enables support for the New Static Memory Controller
+ (FMC) in the Aspeed SoCs (AST2400 and AST2500) when attached
+ to SPI nor chips, and support for the SPI Memory controller
+ (SPI) for the BIOS.
+
endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 121695e83542..c3174ebc45c2 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -4,4 +4,5 @@ obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
+obj-$(CONFIG_ASPEED_FLASH_SPI) += aspeed-smc.o
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
new file mode 100644
index 000000000000..30662daf89ca
--- /dev/null
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -0,0 +1,783 @@
+/*
+ * ASPEED Static Memory Controller driver
+ *
+ * Copyright (c) 2015-2016, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/spi-nor.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/sysfs.h>
+
+#define DEVICE_NAME "aspeed-smc"
+
+/*
+ * In user mode all data bytes read or written to the chip decode address
+ * range are transferred to or from the SPI bus. The range is treated as a
+ * fifo of arbitratry 1, 2, or 4 byte width but each write has to be aligned
+ * to its size. The address within the multiple 8kB range is ignored when
+ * sending bytes to the SPI bus.
+ *
+ * On the arm architecture, as of Linux version 4.3, memcpy_fromio and
+ * memcpy_toio on little endian targets use the optimized memcpy routines
+ * that were designed for well behavied memory storage. These routines
+ * have a stutter if the source and destination are not both word aligned,
+ * once with a duplicate access to the source after aligning to the
+ * destination to a word boundary, and again with a duplicate access to
+ * the source when the final byte count is not word aligned.
+ *
+ * When writing or reading the fifo this stutter discards data or sends
+ * too much data to the fifo and can not be used by this driver.
+ *
+ * While the low level io string routines that implement the insl family do
+ * the desired accesses and memory increments, the cross architecture io
+ * macros make them essentially impossible to use on a memory mapped address
+ * instead of a a token from the call to iomap of an io port.
+ *
+ * These fifo routines use readl and friends to a constant io port and update
+ * the memory buffer pointer and count via explicit code. The final updates
+ * to len are optimistically suppressed.
+ */
+static int aspeed_smc_read_from_ahb(void *buf, const void __iomem *src,
+ size_t len)
+{
+ if ((((unsigned long)src | (unsigned long)buf | len) & 3) == 0) {
+ while (len > 3) {
+ *(u32 *)buf = readl(src);
+ buf += 4;
+ src += 4;
+ len -= 4;
+ }
+ }
+
+ while (len--) {
+ *(u8 *)buf = readb(src);
+ buf += 1;
+ src += 1;
+ }
+ return 0;
+}
+
+static int aspeed_smc_write_to_ahb(void __iomem *dst, const void *buf,
+ size_t len)
+{
+ if ((((unsigned long)dst | (unsigned long)buf | len) & 3) == 0) {
+ while (len > 3) {
+ u32 val = *(u32 *)buf;
+
+ writel(val, dst);
+ buf += 4;
+ dst += 4;
+ len -= 4;
+ }
+ }
+
+ while (len--) {
+ u8 val = *(u8 *)buf;
+
+ writeb(val, dst);
+ buf += 1;
+ dst += 1;
+ }
+ return 0;
+}
+
+enum smc_flash_type {
+ smc_type_nor = 0, /* controller connected to nor flash */
+ smc_type_nand = 1, /* controller connected to nand flash */
+ smc_type_spi = 2, /* controller connected to spi flash */
+};
+
+struct aspeed_smc_chip;
+
+struct aspeed_smc_info {
+ u32 maxsize; /* maximum size of 1 chip window */
+ u8 nce; /* number of chip enables */
+ u8 maxwidth; /* max width of spi bus */
+ bool hastype; /* flash type field exists in cfg reg */
+ u8 we0; /* shift for write enable bit for ce 0 */
+ u8 ctl0; /* offset in regs of ctl for ce 0 */
+ u8 time; /* offset in regs of timing */
+ u8 misc; /* offset in regs of misc settings */
+
+ void (*set_4b)(struct aspeed_smc_chip *chip);
+};
+
+static void aspeed_smc_chip_set_4b_smc_2400(struct aspeed_smc_chip *chip);
+static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip);
+
+static const struct aspeed_smc_info fmc_2400_info = {
+ .maxsize = 64 * 1024 * 1024,
+ .nce = 5,
+ .maxwidth = 4,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .time = 0x94,
+ .misc = 0x54,
+ .set_4b = aspeed_smc_chip_set_4b,
+};
+
+static const struct aspeed_smc_info smc_2400_info = {
+ .maxsize = 64 * 1024 * 1024,
+ .nce = 1,
+ .maxwidth = 2,
+ .hastype = false,
+ .we0 = 0,
+ .ctl0 = 0x04,
+ .time = 0x14,
+ .misc = 0x10,
+ .set_4b = aspeed_smc_chip_set_4b_smc_2400,
+};
+
+static const struct aspeed_smc_info fmc_2500_info = {
+ .maxsize = 256 * 1024 * 1024,
+ .nce = 3,
+ .maxwidth = 2,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .time = 0x94,
+ .misc = 0x54,
+ .set_4b = aspeed_smc_chip_set_4b,
+};
+
+static const struct aspeed_smc_info smc_2500_info = {
+ .maxsize = 128 * 1024 * 1024,
+ .nce = 2,
+ .maxwidth = 2,
+ .hastype = false,
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .time = 0x94,
+ .misc = 0x54,
+ .set_4b = aspeed_smc_chip_set_4b,
+};
+
+enum smc_ctl_reg_value {
+ smc_base, /* base value without mode for other commands */
+ smc_read, /* command reg for (maybe fast) reads */
+ smc_write, /* command reg for writes with timings */
+ smc_num_ctl_reg_values /* last value to get count of commands */
+};
+
+struct aspeed_smc_controller;
+
+struct aspeed_smc_chip {
+ int cs;
+ struct aspeed_smc_controller *controller;
+ __le32 __iomem *ctl; /* control register */
+ void __iomem *base; /* base of chip window */
+ __le32 ctl_val[smc_num_ctl_reg_values]; /* controls with timing */
+ enum smc_flash_type type; /* what type of flash */
+ struct spi_nor nor;
+};
+
+struct aspeed_smc_controller {
+ struct device *dev;
+
+ struct mutex mutex; /* controller access mutex */
+ const struct aspeed_smc_info *info; /* type info of controller */
+ void __iomem *regs; /* controller registers */
+ void __iomem *windows; /* per-chip windows resource */
+
+ struct aspeed_smc_chip *chips[0]; /* pointers to attached chips */
+};
+
+/*
+ * SPI Flash Configuration Register (AST2400 SPI)
+ */
+#define CONFIG_REG 0x0
+#define CONFIG_ENABLE_CE_INACTIVE BIT(1)
+#define CONFIG_WRITE BIT(0)
+
+/*
+ * SPI Flash Configuration Register (AST2500 SPI)
+ * Type setting Register (AST2500 FMC and AST2400 FMC)
+ */
+#define TYPE_SETTING_REG 0x0
+#define CONFIG_DISABLE_LEGACY BIT(31) /* 1 on AST2500 FMC */
+
+#define CONFIG_CE2_WRITE BIT(18)
+#define CONFIG_CE1_WRITE BIT(17)
+#define CONFIG_CE0_WRITE BIT(16)
+
+#define CONFIG_CE2_TYPE BIT(4) /* FMC only */
+#define CONFIG_CE1_TYPE BIT(2) /* FMC only */
+#define CONFIG_CE0_TYPE BIT(0) /* FMC only */
+
+/*
+ * CE Control Register (AST2500 SPI,FMC and AST2400 FMC)
+ */
+#define CE_CONTROL_REG 0x4
+#define CE2_ENABLE_CE_INACTIVE BIT(10)
+#define CE1_ENABLE_CE_INACTIVE BIT(9)
+#define CE0_ENABLE_CE_INACTIVE BIT(8)
+#define CE2_CONTROL_EXTENDED BIT(2)
+#define CE1_CONTROL_EXTENDED BIT(1)
+#define CE0_CONTROL_EXTENDED BIT(0)
+
+/* CE0 Control Register (depends on the controller type) */
+#define CONTROL_SPI_AAF_MODE BIT(31)
+#define CONTROL_SPI_IO_MODE_MASK GENMASK(30, 28)
+#define CONTROL_SPI_IO_DUAL_DATA BIT(29)
+#define CONTROL_SPI_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28))
+#define CONTROL_SPI_IO_QUAD_DATA BIT(30)
+#define CONTROL_SPI_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28))
+#define CONTROL_SPI_CE_INACTIVE_SHIFT 24
+#define CONTROL_SPI_CE_INACTIVE_MASK GENMASK(27, CONTROL_SPI_CE_INACTIVE_SHIFT)
+/* 0 = 16T ... 15 = 1T T=HCLK */
+#define CONTROL_SPI_COMMAND_SHIFT 16
+#define CONTROL_SPI_DUMMY_CYCLE_COMMAND_OUTPUT BIT(15)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_HI BIT(14)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_HI_SHIFT 14
+#define CONTROL_SPI_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */
+#define CONTROL_SPI_CLK_DIV4 BIT(13) /* others */
+#define CONTROL_SPI_RW_MERGE BIT(12)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_LO_SHIFT 6
+#define CONTROL_SPI_IO_DUMMY_CYCLES_LO GENMASK(7, \
+ CONTROL_SPI_IO_DUMMY_CYCLES_LO_SHIFT)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_MASK (CONTROL_SPI_IO_DUMMY_CYCLES_HI | \
+ CONTROL_SPI_IO_DUMMY_CYCLES_LO)
+#define CONTROL_SPI_IO_DUMMY_CYCLES_SET(dummy) \
+ (((((dummy) >> 2) & 0x1) << CONTROL_SPI_IO_DUMMY_CYCLES_HI_SHIFT) | \
+ (((dummy) & 0x3) << CONTROL_SPI_IO_DUMMY_CYCLES_LO_SHIFT))
+
+#define CONTROL_SPI_CLOCK_FREQ_SEL_SHIFT 8
+#define CONTROL_SPI_CLOCK_FREQ_SEL_MASK GENMASK(11, \
+ CONTROL_SPI_CLOCK_FREQ_SEL_SHIFT)
+#define CONTROL_SPI_LSB_FIRST BIT(5)
+#define CONTROL_SPI_CLOCK_MODE_3 BIT(4)
+#define CONTROL_SPI_IN_DUAL_DATA BIT(3)
+#define CONTROL_SPI_CE_STOP_ACTIVE_CONTROL BIT(2)
+#define CONTROL_SPI_COMMAND_MODE_MASK GENMASK(1, 0)
+#define CONTROL_SPI_COMMAND_MODE_NORMAL (0)
+#define CONTROL_SPI_COMMAND_MODE_FREAD (1)
+#define CONTROL_SPI_COMMAND_MODE_WRITE (2)
+#define CONTROL_SPI_COMMAND_MODE_USER (3)
+
+#define CONTROL_SPI_KEEP_MASK (CONTROL_SPI_AAF_MODE | \
+ CONTROL_SPI_CE_INACTIVE_MASK | CONTROL_SPI_CLK_DIV4 | \
+ CONTROL_SPI_IO_DUMMY_CYCLES_MASK | CONTROL_SPI_CLOCK_FREQ_SEL_MASK | \
+ CONTROL_SPI_LSB_FIRST | CONTROL_SPI_CLOCK_MODE_3)
+
+/* Segment Address Registers */
+#define SEGMENT_ADDR_REG0 0x30
+#define SEGMENT_ADDR_START(_r) ((((_r) >> 16) & 0xFF) << 23)
+#define SEGMENT_ADDR_END(_r) ((((_r) >> 24) & 0xFF) << 23)
+
+static u32 spi_control_fill_opcode(u8 opcode)
+{
+ return ((u32)(opcode)) << CONTROL_SPI_COMMAND_SHIFT;
+}
+
+static inline u32 aspeed_smc_chip_write_bit(struct aspeed_smc_chip *chip)
+{
+ return ((u32)1 << (chip->controller->info->we0 + chip->cs));
+}
+
+static void aspeed_smc_chip_check_config(struct aspeed_smc_chip *chip)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ u32 reg;
+
+ reg = readl(controller->regs + CONFIG_REG);
+
+ if (!(reg & aspeed_smc_chip_write_bit(chip))) {
+ dev_dbg(controller->dev,
+ "config write is not set ! @%p: 0x%08x\n",
+ controller->regs + CONFIG_REG, reg);
+ reg |= aspeed_smc_chip_write_bit(chip);
+ writel(reg, controller->regs + CONFIG_REG);
+ }
+}
+
+static void aspeed_smc_start_user(struct spi_nor *nor)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+ u32 ctl = chip->ctl_val[smc_base];
+
+ /*
+ * When the chip is controlled in user mode, we need write
+ * access to send the opcodes to it. So check the config.
+ */
+ aspeed_smc_chip_check_config(chip);
+
+ ctl |= CONTROL_SPI_COMMAND_MODE_USER |
+ CONTROL_SPI_CE_STOP_ACTIVE_CONTROL;
+ writel(ctl, chip->ctl);
+
+ ctl &= ~CONTROL_SPI_CE_STOP_ACTIVE_CONTROL;
+ writel(ctl, chip->ctl);
+}
+
+static void aspeed_smc_stop_user(struct spi_nor *nor)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ u32 ctl = chip->ctl_val[smc_read];
+ u32 ctl2 = ctl | CONTROL_SPI_COMMAND_MODE_USER |
+ CONTROL_SPI_CE_STOP_ACTIVE_CONTROL;
+
+ writel(ctl2, chip->ctl); /* stop user CE control */
+ writel(ctl, chip->ctl); /* default to fread or read */
+}
+
+static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ mutex_lock(&chip->controller->mutex);
+
+ aspeed_smc_start_user(nor);
+ aspeed_smc_write_to_ahb(chip->base, &opcode, 1);
+ aspeed_smc_read_from_ahb(buf, chip->base, len);
+ aspeed_smc_stop_user(nor);
+
+ mutex_unlock(&chip->controller->mutex);
+
+ return 0;
+}
+
+static int aspeed_smc_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ int len)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ mutex_lock(&chip->controller->mutex);
+
+ aspeed_smc_start_user(nor);
+ aspeed_smc_write_to_ahb(chip->base, &opcode, 1);
+ aspeed_smc_write_to_ahb(chip->base, buf, len);
+ aspeed_smc_stop_user(nor);
+
+ mutex_unlock(&chip->controller->mutex);
+
+ return 0;
+}
+
+static void aspeed_smc_send_cmd_addr(struct spi_nor *nor, u8 cmd, u32 addr)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+ __be32 temp;
+ u32 cmdaddr;
+
+ switch (nor->addr_width) {
+ default:
+ WARN_ONCE(1, "Unexpected address width %u, defaulting to 3\n",
+ nor->addr_width);
+ /* FALLTHROUGH */
+ case 3:
+ cmdaddr = addr & 0xFFFFFF;
+
+ cmdaddr |= (u32)cmd << 24;
+
+ temp = cpu_to_be32(cmdaddr);
+ aspeed_smc_write_to_ahb(chip->base, &temp, 4);
+ break;
+ case 4:
+ temp = cpu_to_be32(addr);
+ aspeed_smc_write_to_ahb(chip->base, &cmd, 1);
+ aspeed_smc_write_to_ahb(chip->base, &temp, 4);
+ break;
+ }
+}
+
+static ssize_t aspeed_smc_read_user(struct spi_nor *nor, loff_t from,
+ size_t len, u_char *read_buf)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ mutex_lock(&chip->controller->mutex);
+
+ aspeed_smc_start_user(nor);
+ aspeed_smc_send_cmd_addr(nor, nor->read_opcode, from);
+ aspeed_smc_read_from_ahb(read_buf, chip->base, len);
+ aspeed_smc_stop_user(nor);
+
+ mutex_unlock(&chip->controller->mutex);
+
+ return len;
+}
+
+static ssize_t aspeed_smc_write_user(struct spi_nor *nor, loff_t to, size_t len,
+ const u_char *write_buf)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ mutex_lock(&chip->controller->mutex);
+
+ aspeed_smc_start_user(nor);
+ aspeed_smc_send_cmd_addr(nor, nor->program_opcode, to);
+ aspeed_smc_write_to_ahb(chip->base, write_buf, len);
+ aspeed_smc_stop_user(nor);
+
+ mutex_unlock(&chip->controller->mutex);
+
+ return len;
+}
+
+static int aspeed_smc_remove(struct platform_device *dev)
+{
+ struct aspeed_smc_chip *chip;
+ struct aspeed_smc_controller *controller = platform_get_drvdata(dev);
+ int n;
+
+ for (n = 0; n < controller->info->nce; n++) {
+ chip = controller->chips[n];
+ if (chip)
+ mtd_device_unregister(&chip->nor.mtd);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id aspeed_smc_matches[] = {
+ { .compatible = "aspeed,ast2400-fmc", .data = &fmc_2400_info },
+ { .compatible = "aspeed,ast2400-smc", .data = &smc_2400_info },
+ { .compatible = "aspeed,ast2500-fmc", .data = &fmc_2500_info },
+ { .compatible = "aspeed,ast2500-smc", .data = &smc_2500_info },
+ { }
+};
+MODULE_DEVICE_TABLE(of, aspeed_smc_matches);
+
+static struct platform_device *
+of_platform_device_create_or_find(struct device_node *child,
+ struct device *parent)
+{
+ struct platform_device *cdev;
+
+ cdev = of_platform_device_create(child, NULL, parent);
+ if (!cdev)
+ cdev = of_find_device_by_node(child);
+ return cdev;
+}
+
+static void __iomem *window_start(struct aspeed_smc_controller *controller,
+ struct resource *r, unsigned int n)
+{
+ u32 offset = 0;
+ u32 reg;
+
+ if (controller->info->nce > 1) {
+ reg = readl(controller->regs + SEGMENT_ADDR_REG0 + n * 4);
+
+ if (SEGMENT_ADDR_START(reg) >= SEGMENT_ADDR_END(reg))
+ return NULL;
+
+ offset = SEGMENT_ADDR_START(reg) - r->start;
+ }
+
+ return controller->windows + offset;
+}
+
+static void aspeed_smc_chip_enable_write(struct aspeed_smc_chip *chip)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ u32 reg;
+
+ reg = readl(controller->regs + CONFIG_REG);
+
+ reg |= aspeed_smc_chip_write_bit(chip);
+ writel(reg, controller->regs + CONFIG_REG);
+}
+
+static void aspeed_smc_chip_set_type(struct aspeed_smc_chip *chip, int type)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ u32 reg;
+
+ reg = readl(controller->regs + CONFIG_REG);
+
+ chip->type = type;
+
+ reg &= ~(3 << (chip->cs * 2));
+ reg |= chip->type << (chip->cs * 2);
+ writel(reg, controller->regs + CONFIG_REG);
+}
+
+/*
+ * The AST2500 FMC and AST2400 FMC flash controllers should be
+ * strapped by hardware, or autodetected, but the AST2500 SPI flash
+ * needs to be set.
+ */
+static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ u32 reg;
+
+ if (chip->controller->info == &smc_2500_info) {
+ reg = readl(controller->regs + CE_CONTROL_REG);
+ reg |= 1 << chip->cs;
+ writel(reg, controller->regs + CE_CONTROL_REG);
+ }
+}
+
+/*
+ * The AST2400 SPI flash controller does not have a CE Control
+ * register. It uses the CE0 control register to set 4Byte mode at the
+ * controller level.
+ */
+static void aspeed_smc_chip_set_4b_smc_2400(struct aspeed_smc_chip *chip)
+{
+ chip->ctl_val[smc_base] |= CONTROL_SPI_IO_ADDRESS_4B;
+ chip->ctl_val[smc_read] |= CONTROL_SPI_IO_ADDRESS_4B;
+}
+
+static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip,
+ struct resource *r)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ const struct aspeed_smc_info *info = controller->info;
+ u32 reg, base_reg;
+
+ /*
+ * Always turn on the write enable bit to allow opcodes to be
+ * sent in user mode.
+ */
+ aspeed_smc_chip_enable_write(chip);
+
+ /* The driver only supports SPI type flash for the moment */
+ if (info->hastype)
+ aspeed_smc_chip_set_type(chip, smc_type_spi);
+
+ /*
+ * Configure chip base address in memory
+ */
+ chip->base = window_start(controller, r, chip->cs);
+ if (!chip->base) {
+ dev_warn(chip->nor.dev, "CE segment window closed.\n");
+ return -1;
+ }
+
+ /*
+ * Read the existing control register to get basic values.
+ *
+ * XXX This register probably needs more sanitation.
+ *
+ * Do we need support for mode 3 vs mode 0 clock phasing?
+ */
+ reg = readl(chip->ctl);
+ dev_dbg(controller->dev, "control register: %08x\n", reg);
+
+ base_reg = reg & CONTROL_SPI_KEEP_MASK;
+ if (base_reg != reg) {
+ dev_info(controller->dev,
+ "control register changed to: %08x\n",
+ base_reg);
+ }
+ chip->ctl_val[smc_base] = base_reg;
+
+ /*
+ * Retain the prior value of the control register as the
+ * default if it was normal access mode. Otherwise start with
+ * the sanitized base value set to read mode.
+ */
+ if ((reg & CONTROL_SPI_COMMAND_MODE_MASK) ==
+ CONTROL_SPI_COMMAND_MODE_NORMAL)
+ chip->ctl_val[smc_read] = reg;
+ else
+ chip->ctl_val[smc_read] = chip->ctl_val[smc_base] |
+ CONTROL_SPI_COMMAND_MODE_NORMAL;
+
+ dev_dbg(controller->dev, "default control register: %08x\n",
+ chip->ctl_val[smc_read]);
+ return 0;
+}
+
+static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ const struct aspeed_smc_info *info = controller->info;
+ u32 cmd;
+
+ if (chip->nor.addr_width == 4 && info->set_4b)
+ info->set_4b(chip);
+
+ /*
+ * base mode has not been optimized yet. use it for writes.
+ */
+ chip->ctl_val[smc_write] = chip->ctl_val[smc_base] |
+ spi_control_fill_opcode(chip->nor.program_opcode) |
+ CONTROL_SPI_COMMAND_MODE_WRITE;
+
+ dev_dbg(controller->dev, "write control register: %08x\n",
+ chip->ctl_val[smc_write]);
+
+ /*
+ * XXX TODO
+ * Adjust clocks if fast read and write are supported.
+ * Interpret spi-nor flags to adjust controller settings.
+ * Check if resource size big enough for detected chip and
+ * add support assisted (normal or fast-) read and dma.
+ */
+ switch (chip->nor.flash_read) {
+ case SPI_NOR_NORMAL:
+ cmd = CONTROL_SPI_COMMAND_MODE_NORMAL;
+ break;
+ case SPI_NOR_FAST:
+ cmd = CONTROL_SPI_COMMAND_MODE_FREAD;
+ break;
+ default:
+ dev_err(chip->nor.dev, "unsupported SPI read mode\n");
+ return -EINVAL;
+ }
+
+ chip->ctl_val[smc_read] |= cmd |
+ CONTROL_SPI_IO_DUMMY_CYCLES_SET(chip->nor.read_dummy / 8);
+
+ dev_dbg(controller->dev, "base control register: %08x\n",
+ chip->ctl_val[smc_read]);
+ return 0;
+}
+
+static int aspeed_smc_probe(struct platform_device *pdev)
+{
+ struct aspeed_smc_controller *controller;
+ const struct of_device_id *match;
+ const struct aspeed_smc_info *info;
+ struct resource *r;
+ struct device_node *child;
+ int err = 0;
+ unsigned int n;
+
+ match = of_match_device(aspeed_smc_matches, &pdev->dev);
+ if (!match || !match->data)
+ return -ENODEV;
+ info = match->data;
+
+ controller = devm_kzalloc(&pdev->dev, sizeof(*controller) +
+ info->nce * sizeof(controller->chips[0]), GFP_KERNEL);
+ if (!controller)
+ return -ENOMEM;
+ controller->info = info;
+
+ mutex_init(&controller->mutex);
+ platform_set_drvdata(pdev, controller);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ controller->regs = devm_ioremap_resource(&pdev->dev, r);
+ if (IS_ERR(controller->regs))
+ return PTR_ERR(controller->regs);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ controller->windows = devm_ioremap_resource(&pdev->dev, r);
+ if (IS_ERR(controller->windows))
+ return PTR_ERR(controller->windows);
+
+ controller->dev = &pdev->dev;
+
+ /* The pinmux or bootloader will disable the legacy mode controller */
+
+ /*
+ * XXX Need to add arbitration to the SMC (BIOS) controller if access
+ * is shared by the host.
+ */
+ for_each_available_child_of_node(controller->dev->of_node, child) {
+ struct platform_device *cdev;
+ struct aspeed_smc_chip *chip;
+
+ /* This version does not support nand or nor flash devices. */
+ if (!of_device_is_compatible(child, "jedec,spi-nor"))
+ continue;
+
+ /*
+ * create a platform device from the of node. If the device
+ * already was created (eg from a prior bind/unbind cycle)
+ * reuse it.
+ *
+ * The creating the device node for the child here allows its
+ * use for error reporting via dev_err below.
+ */
+ cdev = of_platform_device_create_or_find(child,
+ controller->dev);
+ if (!cdev)
+ continue;
+
+ err = of_property_read_u32(child, "reg", &n);
+ if (err == -EINVAL && info->nce == 1)
+ n = 0;
+ else if (err || n >= info->nce)
+ continue;
+ if (controller->chips[n]) {
+ dev_err(&cdev->dev,
+ "chip-id %u already in use in use by %s\n",
+ n, dev_name(controller->chips[n]->nor.dev));
+ continue;
+ }
+
+ chip = devm_kzalloc(controller->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ continue;
+ chip->controller = controller;
+ chip->ctl = controller->regs + info->ctl0 + n * 4;
+ chip->cs = n;
+
+ chip->nor.dev = &cdev->dev;
+ chip->nor.priv = chip;
+ spi_nor_set_flash_node(&chip->nor, child);
+ chip->nor.mtd.name = of_get_property(child, "label", NULL);
+ chip->nor.read = aspeed_smc_read_user;
+ chip->nor.write = aspeed_smc_write_user;
+ chip->nor.read_reg = aspeed_smc_read_reg;
+ chip->nor.write_reg = aspeed_smc_write_reg;
+
+ err = aspeed_smc_chip_setup_init(chip, r);
+ if (err)
+ continue;
+
+ /*
+ * XXX Add support for SPI_NOR_QUAD and SPI_NOR_DUAL attach
+ * when board support is present as determined by of property.
+ */
+ err = spi_nor_scan(&chip->nor, NULL, SPI_NOR_NORMAL);
+ if (err)
+ continue;
+
+ err = aspeed_smc_chip_setup_finish(chip);
+ if (err)
+ continue;
+
+ err = mtd_device_register(&chip->nor.mtd, NULL, 0);
+ if (err)
+ continue;
+ controller->chips[n] = chip;
+ }
+
+ /* Were any children registered? */
+ for (n = 0; n < info->nce; n++)
+ if (controller->chips[n])
+ break;
+
+ if (n == info->nce)
+ return -ENODEV;
+
+ return 0;
+}
+
+static struct platform_driver aspeed_smc_driver = {
+ .probe = aspeed_smc_probe,
+ .remove = aspeed_smc_remove,
+ .driver = {
+ .name = DEVICE_NAME,
+ .of_match_table = aspeed_smc_matches,
+ }
+};
+
+module_platform_driver(aspeed_smc_driver);
+
+MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
+MODULE_AUTHOR("Milton Miller");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [PATCH v2] leds: ledtrig-heartbeat: Make top brightness adjustable
From: Jacek Anaszewski @ 2016-11-09 10:43 UTC (permalink / raw)
To: linux-leds; +Cc: linux-kernel, Jacek Anaszewski, Pavel Machek, Hans de Goede
LED class heartbeat trigger allowed only for blinking with max_brightness
value. This patch adds more flexibility by exploiting part of LED core
software blink infrastructure.
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Hans de Goede <hdegoede@redhat.com>
---
Changes since v1:
- after introduction of work_flags and new_blink_brightness properties
this patch needs to be updated
drivers/leds/trigger/ledtrig-heartbeat.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/leds/trigger/ledtrig-heartbeat.c b/drivers/leds/trigger/ledtrig-heartbeat.c
index c9f3862..e6f2f8b 100644
--- a/drivers/leds/trigger/ledtrig-heartbeat.c
+++ b/drivers/leds/trigger/ledtrig-heartbeat.c
@@ -43,6 +43,9 @@ static void led_heartbeat_function(unsigned long data)
return;
}
+ if (test_and_clear_bit(LED_BLINK_BRIGHTNESS_CHANGE, &led_cdev->work_flags))
+ led_cdev->blink_brightness = led_cdev->new_blink_brightness;
+
/* acts like an actual heart beat -- ie thump-thump-pause... */
switch (heartbeat_data->phase) {
case 0:
@@ -59,26 +62,26 @@ static void led_heartbeat_function(unsigned long data)
delay = msecs_to_jiffies(70);
heartbeat_data->phase++;
if (!heartbeat_data->invert)
- brightness = led_cdev->max_brightness;
+ brightness = led_cdev->blink_brightness;
break;
case 1:
delay = heartbeat_data->period / 4 - msecs_to_jiffies(70);
heartbeat_data->phase++;
if (heartbeat_data->invert)
- brightness = led_cdev->max_brightness;
+ brightness = led_cdev->blink_brightness;
break;
case 2:
delay = msecs_to_jiffies(70);
heartbeat_data->phase++;
if (!heartbeat_data->invert)
- brightness = led_cdev->max_brightness;
+ brightness = led_cdev->blink_brightness;
break;
default:
delay = heartbeat_data->period - heartbeat_data->period / 4 -
msecs_to_jiffies(70);
heartbeat_data->phase = 0;
if (heartbeat_data->invert)
- brightness = led_cdev->max_brightness;
+ brightness = led_cdev->blink_brightness;
break;
}
@@ -133,7 +136,10 @@ static void heartbeat_trig_activate(struct led_classdev *led_cdev)
setup_timer(&heartbeat_data->timer,
led_heartbeat_function, (unsigned long) led_cdev);
heartbeat_data->phase = 0;
+ if (!led_cdev->blink_brightness)
+ led_cdev->blink_brightness = led_cdev->max_brightness;
led_heartbeat_function(heartbeat_data->timer.data);
+ set_bit(LED_BLINK_SW, &led_cdev->work_flags);
led_cdev->activated = true;
}
@@ -145,6 +151,7 @@ static void heartbeat_trig_deactivate(struct led_classdev *led_cdev)
del_timer_sync(&heartbeat_data->timer);
device_remove_file(led_cdev->dev, &dev_attr_invert);
kfree(heartbeat_data);
+ clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
led_cdev->activated = false;
}
}
--
1.9.1
^ permalink raw reply related
* [PATCH v1 03/11] drivers: soc: hisi: Add support for Hisilicon Djtag driver
From: Anurup M @ 2016-11-09 10:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1609380.NN50qvVsP7@wuerfel>
On Tuesday 08 November 2016 08:40 PM, Arnd Bergmann wrote:
> On Tuesday, November 8, 2016 1:49:43 PM CET John Garry wrote:
>> Hi Arnd,
>>
>> Thanks for the reference.
>>
>> I think the i2c interface doesn't fully satisfy our requirements as we
>> need more than just a slave bus address when accessing the slave device
>> (which I think is what i2c uses). We also need to pass "offset" and
>> "mod_mask" arguments to the djtag adapter to access specific registers
>> in the slave device.
> Ok. Are those values constant per device, or maybe a range? We may want to
> include those in the reg property as well then.
>
> Arnd
>
Hi Arnd,
The "mod_mask" is to select the sub-module within a module. This
parameter is
used for djtag write operation.
In the case of L3 cache, this will select the L3 cache bank. 0xFFFF
select all banks.
This value will change based on the L3 cache bank to be written to. I
think this value
can be in the driver itself.
For djtag read operation, the "mod_mask" is ignored. instead the input
parameter
"chain_id" is used. this will identify the sub-module or bank.
For djtag-v1, the "chain_id" is different for each L3 cache bank, But in
the case of
djtag-v2 the "chain_id" is fixed and the value is 0 as In djtag-v2 there
is separate
"module-id" for each sub-module.
The "offset" is the register offset and this value is a range for a module.
Thanks,
Anurup
^ permalink raw reply
* [PATCH 4.4 00/69] 4.4.31-stable review
From: Greg Kroah-Hartman @ 2016-11-09 10:43 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, torvalds, akpm, linux, shuah.kh, patches,
ben.hutchings, stable
This is the start of the stable review cycle for the 4.4.31 release.
There are 69 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Fri Nov 11 10:28:46 UTC 2016.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.4.31-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-4.4.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux 4.4.31-rc1
Oliver Neukum <oneukum@suse.com>
HID: usbhid: add ATEN CS962 to list of quirky devices
Boris Brezillon <boris.brezillon@free-electrons.com>
ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap()
Owen Hofmann <osh@google.com>
kvm: x86: Check memopp before dereference (CVE-2016-8630)
Jiri Slaby <jslaby@suse.cz>
tty: vt, fix bogus division in csi_J
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
usb: dwc3: Fix size used in dma_free_coherent()
David Hsu <davidhsu@google.com>
pwm: Unexport children before chip removal
Boris Brezillon <boris.brezillon@free-electrons.com>
UBI: fastmap: scrub PEB when bitflips are detected in a free PEB EC header
Linus Torvalds <torvalds@linux-foundation.org>
Disable "frame-address" warning
Arnd Bergmann <arnd@arndb.de>
smc91x: avoid self-comparison warning
Arnd Bergmann <arnd@arndb.de>
cgroup: avoid false positive gcc-6 warning
Arnd Bergmann <arnd@arndb.de>
drm/exynos: fix error handling in exynos_drm_subdrv_open
Stephen Rothwell <sfr@canb.auug.org.au>
mm/cma: silence warnings due to max() usage
Arnd Bergmann <arnd@arndb.de>
ARM: 8584/1: floppy: avoid gcc-6 warning
Khem Raj <raj.khem@gmail.com>
powerpc/ptrace: Fix out of bounds array access warning
Juergen Gross <jgross@suse.com>
x86/xen: fix upper bound of pmd loop in xen_cleanhighmap()
Jiri Olsa <jolsa@kernel.org>
perf build: Fix traceevent plugins build race
Ville Syrjälä <ville.syrjala@linux.intel.com>
drm/dp/mst: Check peer device type before attempting EDID read
Lucas Stach <dev@lynxeye.de>
drm/radeon: drop register readback in cayman_cp_int_cntl_setup
Alex Deucher <alexander.deucher@amd.com>
drm/radeon/si_dpm: workaround for SI kickers
Tom St Denis <tom.stdenis@amd.com>
drm/radeon/si_dpm: Limit clocks on HD86xx part
Michel Dänzer <michel.daenzer@amd.com>
Revert "drm/radeon: fix DP link training issue with second 4K monitor"
Jaehoon Chung <jh80.chung@samsung.com>
mmc: dw_mmc-pltfm: fix the potential NULL pointer dereference
Ching Huang <ching2048@areca.com.tw>
scsi: arcmsr: Send SYNCHRONIZE_CACHE command to firmware
Ewan D. Milne <emilne@redhat.com>
scsi: scsi_debug: Fix memory leak if LBP enabled and module is unloaded
Kashyap Desai <kashyap.desai@broadcom.com>
scsi: megaraid_sas: Fix data integrity failure for JBOD (passthrough) devices
Johannes Berg <johannes.berg@intel.com>
mac80211: discard multicast and 4-addr A-MSDUs
Stefan Richter <stefanr@s5r6.in-berlin.de>
firewire: net: fix fragmented datagram_size off-by-one
Stefan Richter <stefanr@s5r6.in-berlin.de>
firewire: net: guard against rx buffer overflows
Patrick Scheuring <patrick.scheuring.dev@gmail.com>
Input: i8042 - add XMG C504 to keyboard reset table
Heinz Mauelshagen <heinzm@redhat.com>
dm mirror: fix read error on recovery after default leg failure
Matt Redfearn <matt.redfearn@imgtec.com>
virtio: console: Unlock vqs while freeing buffers
Ladi Prosek <lprosek@redhat.com>
virtio_ring: Make interrupt suppression spec compliant
John David Anglin <dave.anglin@bell.net>
parisc: Ensure consistent state when switching to kernel stack at syscall entry
Miklos Szeredi <mszeredi@redhat.com>
ovl: fsync after copy-up
James Hogan <james.hogan@imgtec.com>
KVM: MIPS: Make ERET handle ERL before EXL
Ido Yariv <ido@wizery.com>
KVM: x86: fix wbinvd_dirty_mask use-after-free
Tahsin Erdogan <tahsin@google.com>
dm: free io_barrier after blk_cleanup_queue call
Johan Hovold <johan@kernel.org>
USB: serial: cp210x: fix tiocmget error handling
Dmitry Vyukov <dvyukov@google.com>
tty: limit terminal size to 4M chars
Mathias Nyman <mathias.nyman@linux.intel.com>
xhci: add restart quirk for Intel Wildcatpoint PCH
Long Li <longli@microsoft.com>
hv: do not lose pending heartbeat vmbus packets
Scot Doyle <lkml14@scotdoyle.com>
vt: clear selection before resizing
Linus Torvalds <torvalds@linux-foundation.org>
Fix potential infoleak in older kernels
Gerald Schaefer <gerald.schaefer@de.ibm.com>
GenWQE: Fix bad page access during abort of resource allocation
Bryan Paluch <bryanpaluch@gmail.com>
usb: increase ohci watchdog delay to 275 msec
Mathias Nyman <mathias.nyman@linux.intel.com>
xhci: use default USB_RESUME_TIMEOUT when resuming ports.
Stefan Tauner <stefan.tauner@technikum-wien.at>
USB: serial: ftdi_sio: add support for Infineon TriBoard TC2X7
Johan Hovold <johan@kernel.org>
USB: serial: fix potential NULL-dereference at probe
Felipe Balbi <felipe.balbi@linux.intel.com>
usb: gadget: function: u_ether: don't starve tx request queue
Alexander Usyskin <alexander.usyskin@intel.com>
mei: txe: don't clean an unprocessed interrupt cause.
Richard Weinberger <richard@nod.at>
ubifs: Fix regression in ubifs_readdir()
Richard Weinberger <richard@nod.at>
ubifs: Abort readdir upon error
Chris Mason <clm@fb.com>
btrfs: fix races on root_log_ctx lists
Arve Hjønnevåg <arve@android.com>
ANDROID: binder: Clear binder and cookie when setting handle in flat binder struct
Arve Hjønnevåg <arve@android.com>
ANDROID: binder: Add strong ref checks
Hui Wang <hui.wang@canonical.com>
ALSA: hda - Fix headset mic detection problem for two Dell laptops
Hui Wang <hui.wang@canonical.com>
ALSA: hda - Adding a new group of pin cfg into ALC295 pin quirk table
Ard Biesheuvel <ard.biesheuvel@linaro.org>
ALSA: hda - allow 40 bit DMA mask for NVidia devices
Takashi Iwai <tiwai@suse.de>
ALSA: hda - Raise AZX_DCAPS_RIRB_DELAY handling into top drivers
Takashi Iwai <tiwai@suse.de>
ALSA: hda - Merge RIRB_PRE_DELAY into CTX_WORKAROUND caps
Marcel Hasler <mahasler@gmail.com>
ALSA: usb-audio: Add quirk for Syntek STK1160
David Howells <dhowells@redhat.com>
KEYS: Fix short sprintf buffer in /proc/keys show function
Johannes Weiner <hannes@cmpxchg.org>
mm: memcontrol: do not recurse in direct reclaim
Alexander Polakov <apolyakov@beget.ru>
mm/list_lru.c: avoid error-path NULL pointer deref
Darrick J. Wong <darrick.wong@oracle.com>
libxfs: clean up _calc_dquots_per_chunk
Mark Rutland <mark.rutland@arm.com>
h8300: fix syscall restarting
Ville Syrjälä <ville.syrjala@linux.intel.com>
drm/dp/mst: Clear port->pdt when tearing down the i2c adapter
Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
i2c: core: fix NULL pointer dereference under race condition
Hoan Tran <hotran@apm.com>
i2c: xgene: Avoid dma_buffer overrun
-------------
Diffstat:
Makefile | 5 +--
arch/arm/include/asm/floppy.h | 2 +-
arch/h8300/include/asm/thread_info.h | 4 ---
arch/h8300/kernel/signal.c | 2 +-
arch/mips/kvm/emulate.c | 8 ++---
arch/parisc/kernel/syscall.S | 11 ++++--
arch/powerpc/kernel/ptrace.c | 4 +--
arch/x86/include/asm/uaccess.h | 10 +++---
arch/x86/kvm/emulate.c | 2 +-
arch/x86/kvm/x86.c | 4 ++-
arch/x86/xen/mmu.c | 2 +-
drivers/android/binder.c | 35 +++++++++++++-----
drivers/char/virtio_console.c | 22 ++++++++----
drivers/firewire/net.c | 59 ++++++++++++++++++++-----------
drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++-
drivers/gpu/drm/exynos/exynos_drm_core.c | 2 +-
drivers/gpu/drm/radeon/ni.c | 4 +--
drivers/gpu/drm/radeon/radeon_dp_auxch.c | 2 +-
drivers/gpu/drm/radeon/si_dpm.c | 53 +++++++++++++++++++++------
drivers/hid/hid-ids.h | 1 +
drivers/hid/usbhid/hid-quirks.c | 1 +
drivers/hv/hv_util.c | 10 ++++--
drivers/i2c/busses/i2c-xgene-slimpro.c | 2 +-
drivers/i2c/i2c-core.c | 2 +-
drivers/input/serio/i8042-x86ia64io.h | 7 ++++
drivers/md/dm-raid1.c | 1 +
drivers/md/dm.c | 4 +--
drivers/misc/genwqe/card_utils.c | 12 ++++++-
drivers/misc/mei/hw-txe.c | 6 ++--
drivers/mmc/host/dw_mmc-pltfm.c | 5 +--
drivers/mtd/ubi/fastmap.c | 17 ++++-----
drivers/net/ethernet/smsc/smc91x.c | 2 +-
drivers/pwm/core.c | 2 ++
drivers/pwm/sysfs.c | 18 ++++++++++
drivers/scsi/arcmsr/arcmsr_hba.c | 9 -----
drivers/scsi/megaraid/megaraid_sas_base.c | 13 +++----
drivers/scsi/scsi_debug.c | 1 +
drivers/tty/vt/vt.c | 7 +++-
drivers/usb/dwc3/gadget.c | 4 +--
drivers/usb/gadget/function/u_ether.c | 5 +--
drivers/usb/host/ohci-hcd.c | 2 +-
drivers/usb/host/xhci-hub.c | 4 +--
drivers/usb/host/xhci-pci.c | 4 ++-
drivers/usb/serial/cp210x.c | 4 ++-
drivers/usb/serial/ftdi_sio.c | 3 +-
drivers/usb/serial/ftdi_sio_ids.h | 5 +--
drivers/usb/serial/usb-serial.c | 3 +-
drivers/virtio/virtio_ring.c | 14 +++++---
fs/btrfs/tree-log.c | 20 ++++-------
fs/overlayfs/copy_up.c | 2 ++
fs/ubifs/dir.c | 16 ++++++---
fs/xfs/libxfs/xfs_dquot_buf.c | 3 +-
include/linux/pwm.h | 5 +++
kernel/cgroup.c | 3 ++
mm/cma.c | 7 ++--
mm/list_lru.c | 2 ++
mm/memcontrol.c | 9 +++++
mm/vmscan.c | 2 ++
net/mac80211/rx.c | 24 ++++++++-----
security/keys/proc.c | 2 +-
sound/pci/hda/hda_controller.c | 7 +---
sound/pci/hda/hda_controller.h | 4 +--
sound/pci/hda/hda_intel.c | 18 ++++++----
sound/pci/hda/hda_tegra.c | 5 +--
sound/pci/hda/patch_realtek.c | 18 ++++++++--
sound/usb/quirks-table.h | 17 +++++++++
tools/perf/Makefile.perf | 2 +-
67 files changed, 385 insertions(+), 186 deletions(-)
^ permalink raw reply
* [PATCH 4.4 01/69] i2c: xgene: Avoid dma_buffer overrun
From: Greg Kroah-Hartman @ 2016-11-09 10:43 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Phil Endecott, Hoan Tran,
Wolfram Sang
In-Reply-To: <20161109102901.127641653@linuxfoundation.org>
4.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Hoan Tran <hotran@apm.com>
commit 603616017c35f4d0fbdbcace72adf9bf949c4a65 upstream.
SMBus block command uses the first byte of buffer for the data length.
The dma_buffer should be increased by 1 to avoid the overrun issue.
Reported-by: Phil Endecott <phil_gjouf_endecott@chezphil.org>
Signed-off-by: Hoan Tran <hotran@apm.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/i2c/busses/i2c-xgene-slimpro.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/i2c/busses/i2c-xgene-slimpro.c
+++ b/drivers/i2c/busses/i2c-xgene-slimpro.c
@@ -105,7 +105,7 @@ struct slimpro_i2c_dev {
struct mbox_chan *mbox_chan;
struct mbox_client mbox_client;
struct completion rd_complete;
- u8 dma_buffer[I2C_SMBUS_BLOCK_MAX];
+ u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* dma_buffer[0] is used for length */
u32 *resp_msg;
};
^ permalink raw reply
* [PATCH 4.4 04/69] h8300: fix syscall restarting
From: Greg Kroah-Hartman @ 2016-11-09 10:43 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Mark Rutland, Andy Lutomirski,
Yoshinori Sato, uclinux-h8-devel, Andrew Morton, Linus Torvalds
In-Reply-To: <20161109102901.127641653@linuxfoundation.org>
4.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Mark Rutland <mark.rutland@arm.com>
commit 21753583056d48a5fad964d6f272e28168426845 upstream.
Back in commit f56141e3e2d9 ("all arches, signal: move restart_block to
struct task_struct"), all architectures and core code were changed to
use task_struct::restart_block. However, when h8300 support was
subsequently restored in v4.2, it was not updated to account for this,
and maintains thread_info::restart_block, which is not kept in sync.
This patch drops the redundant restart_block from thread_info, and moves
h8300 to the common one in task_struct, ensuring that syscall restarting
always works as expected.
Fixes: f56141e3e2d9 ("all arches, signal: move restart_block to struct task_struct")
Link: http://lkml.kernel.org/r/1476714934-11635-1-git-send-email-mark.rutland@arm.com
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: uclinux-h8-devel@lists.sourceforge.jp
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/h8300/include/asm/thread_info.h | 4 ----
arch/h8300/kernel/signal.c | 2 +-
2 files changed, 1 insertion(+), 5 deletions(-)
--- a/arch/h8300/include/asm/thread_info.h
+++ b/arch/h8300/include/asm/thread_info.h
@@ -31,7 +31,6 @@ struct thread_info {
int cpu; /* cpu we're on */
int preempt_count; /* 0 => preemptable, <0 => BUG */
mm_segment_t addr_limit;
- struct restart_block restart_block;
};
/*
@@ -44,9 +43,6 @@ struct thread_info {
.cpu = 0, \
.preempt_count = INIT_PREEMPT_COUNT, \
.addr_limit = KERNEL_DS, \
- .restart_block = { \
- .fn = do_no_restart_syscall, \
- }, \
}
#define init_thread_info (init_thread_union.thread_info)
--- a/arch/h8300/kernel/signal.c
+++ b/arch/h8300/kernel/signal.c
@@ -79,7 +79,7 @@ restore_sigcontext(struct sigcontext *us
unsigned int er0;
/* Always make any pending restarted system calls return -EINTR */
- current_thread_info()->restart_block.fn = do_no_restart_syscall;
+ current->restart_block.fn = do_no_restart_syscall;
/* restore passed registers */
#define COPY(r) do { err |= get_user(regs->r, &usc->sc_##r); } while (0)
^ permalink raw reply
* [PATCH 4.4 06/69] mm/list_lru.c: avoid error-path NULL pointer deref
From: Greg Kroah-Hartman @ 2016-11-09 10:43 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Alexander Polakov, Vladimir Davydov,
Al Viro, Andrew Morton, Linus Torvalds
In-Reply-To: <20161109102901.127641653@linuxfoundation.org>
4.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Alexander Polakov <apolyakov@beget.ru>
commit 1bc11d70b5db7c6bb1414b283d7f09b1fe1ac0d0 upstream.
As described in https://bugzilla.kernel.org/show_bug.cgi?id=177821:
After some analysis it seems to be that the problem is in alloc_super().
In case list_lru_init_memcg() fails it goes into destroy_super(), which
calls list_lru_destroy().
And in list_lru_init() we see that in case memcg_init_list_lru() fails,
lru->node is freed, but not set NULL, which then leads list_lru_destroy()
to believe it is initialized and call memcg_destroy_list_lru().
memcg_destroy_list_lru() in turn can access lru->node[i].memcg_lrus,
which is NULL.
[akpm@linux-foundation.org: add comment]
Signed-off-by: Alexander Polakov <apolyakov@beget.ru>
Acked-by: Vladimir Davydov <vdavydov.dev@gmail.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
mm/list_lru.c | 2 ++
1 file changed, 2 insertions(+)
--- a/mm/list_lru.c
+++ b/mm/list_lru.c
@@ -554,6 +554,8 @@ int __list_lru_init(struct list_lru *lru
err = memcg_init_list_lru(lru, memcg_aware);
if (err) {
kfree(lru->node);
+ /* Do this so a list_lru_destroy() doesn't crash: */
+ lru->node = NULL;
goto out;
}
^ permalink raw reply
* [PATCH 4.4 05/69] libxfs: clean up _calc_dquots_per_chunk
From: Greg Kroah-Hartman @ 2016-11-09 10:43 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Darrick J. Wong, Eric Sandeen,
Dave Chinner
In-Reply-To: <20161109102901.127641653@linuxfoundation.org>
4.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Darrick J. Wong <darrick.wong@oracle.com>
commit 58d789678546d46d7bbd809dd7dab417c0f23655 upstream.
The function xfs_calc_dquots_per_chunk takes a parameter in units
of basic blocks. The kernel seems to get the units wrong, but
userspace got 'fixed' by commenting out the unnecessary conversion.
Fix both.
Signed-off-by: Darrick J. Wong <darrick.wong@oracle.com>
Reviewed-by: Eric Sandeen <sandeen@redhat.com>
Signed-off-by: Dave Chinner <david@fromorbit.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
fs/xfs/libxfs/xfs_dquot_buf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/fs/xfs/libxfs/xfs_dquot_buf.c
+++ b/fs/xfs/libxfs/xfs_dquot_buf.c
@@ -191,8 +191,7 @@ xfs_dquot_buf_verify_crc(
if (mp->m_quotainfo)
ndquots = mp->m_quotainfo->qi_dqperchunk;
else
- ndquots = xfs_calc_dquots_per_chunk(
- XFS_BB_TO_FSB(mp, bp->b_length));
+ ndquots = xfs_calc_dquots_per_chunk(bp->b_length);
for (i = 0; i < ndquots; i++, d++) {
if (!xfs_verify_cksum((char *)d, sizeof(struct xfs_dqblk),
^ permalink raw reply
* [PATCH] drm/i915: Demote i915_gem_open() debugging from DRIVER to USER
From: Chris Wilson @ 2016-11-09 10:45 UTC (permalink / raw)
To: intel-gfx
We use DRM_DEBUG() when reporting on user actions, to try and keep
intentional errors out of the CI dmesg. Demote the debug from
i915_gem_open() similarly so that it is only apparent with drm.debug & 1
like its brethren.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2450c99d29ae..951d392427d8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5054,7 +5054,7 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file)
struct drm_i915_file_private *file_priv;
int ret;
- DRM_DEBUG_DRIVER("\n");
+ DRM_DEBUG("\n");
file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
if (!file_priv)
--
2.10.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [PATCH 4.4 19/69] ubifs: Fix regression in ubifs_readdir()
From: Greg Kroah-Hartman @ 2016-11-09 10:43 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Peter Rosin, Ralph Sennhauser,
Richard Weinberger
In-Reply-To: <20161109102901.127641653@linuxfoundation.org>
4.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Richard Weinberger <richard@nod.at>
commit a00052a296e54205cf238c75bd98d17d5d02a6db upstream.
Commit c83ed4c9dbb35 ("ubifs: Abort readdir upon error") broke
overlayfs support because the fix exposed an internal error
code to VFS.
Reported-by: Peter Rosin <peda@axentia.se>
Tested-by: Peter Rosin <peda@axentia.se>
Reported-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Tested-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Fixes: c83ed4c9dbb35 ("ubifs: Abort readdir upon error")
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
fs/ubifs/dir.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/fs/ubifs/dir.c
+++ b/fs/ubifs/dir.c
@@ -454,6 +454,14 @@ out:
if (err != -ENOENT)
ubifs_err(c, "cannot find next direntry, error %d", err);
+ else
+ /*
+ * -ENOENT is a non-fatal error in this context, the TNC uses
+ * it to indicate that the cursor moved past the current directory
+ * and readdir() has to stop.
+ */
+ err = 0;
+
/* 2 is a special value indicating that there are no more direntries */
ctx->pos = 2;
^ permalink raw reply
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