* Re: [PATCH v3] drm: move allocation out of drm_get_format_name()
From: Eric Engestrom @ 2016-11-09 11:42 UTC (permalink / raw)
To: Eric Engestrom, linux-kernel, David Airlie, dri-devel,
Wei Yongjun, Daniel Vetter, Flora Cui, Gustavo Padovan,
Tom St Denis, Chunming Zhou, Thomas Hellstrom, Laurent Pinchart,
Sinclair Yeh, Xinliang Liu, Xinwei Kong, VMware Graphics,
Vitaly Prosyak, Alexandre Demers, Jani Nikula, intel-gfx,
Emily Deng, Colin Ian King
In-Reply-To: <20161109011325.hvvfsvpq734nduxd@phenom.ffwll.local>
On Wednesday, 2016-11-09 02:13:25 +0100, Daniel Vetter wrote:
> On Wed, Nov 09, 2016 at 02:09:16AM +0100, Daniel Vetter wrote:
> > On Wed, Nov 09, 2016 at 12:17:52AM +0000, Eric Engestrom wrote:
> > > The function's behaviour was changed in 90844f00049e, without changing
> > > its signature, causing people to keep using it the old way without
> > > realising they were now leaking memory.
> > > Rob Clark also noticed it was also allocating GFP_KERNEL memory in
> > > atomic contexts, breaking them.
> > >
> > > Instead of having to allocate GFP_ATOMIC memory and fixing the callers
> > > to make them cleanup the memory afterwards, let's change the function's
> > > signature by having the caller take care of the memory and passing it to
> > > the function.
> > > The new parameter is a single-field struct in order to enforce the size
> > > of its buffer and help callers to correctly manage their memory.
> > >
> > > Fixes: 90844f00049e ("drm: make drm_get_format_name thread-safe")
> > > Cc: Rob Clark <robdclark@gmail.com>
> > > Cc: Christian König <christian.koenig@amd.com>
> > > Acked-by: Christian König <christian.koenig@amd.com>
> > > Acked-by: Rob Clark <robdclark@gmail.com>
> > > Acked-by: Sinclair Yeh <syeh@vmware.com> (vmwgfx)
> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Eric Engestrom <eric@engestrom.ch>
> > > ---
> > > v3 - fix "Fixes" tag, replace it with an actual commit message
> > > - collect ack & r-b
> > >
> > > v2 - use single-field struct instead of typedef to let the compiler
> > > enforce the type (Christian König)
> >
> > Applied to drm-misc, thanks.
>
> Well, had to drop it again since it didn't compile:
>
>
> CC [M] drivers/gpu/drm/drm_blend.o
> drivers/gpu/drm/drm_atomic.c: In function ‘drm_atomic_plane_print_state’:
> drivers/gpu/drm/drm_atomic.c:920:5: error: too few arguments to function ‘drm_get_format_name’
> drm_get_format_name(fb->pixel_format));
> ^~~~~~~~~~~~~~~~~~~
> In file included from ./include/drm/drmP.h:71:0,
> from drivers/gpu/drm/drm_atomic.c:29:
> ./include/drm/drm_fourcc.h:65:7: note: declared here
> char *drm_get_format_name(uint32_t format, struct drm_format_name_buf *buf);
> ^~~~~~~~~~~~~~~~~~~
>
> Can you pls rebase onto drm-misc or linux-next or something?
That was based on airlied/drm-next (last fetched on Sunday I think),
I can rebase it on drm-misc if it helps, but it seems older than
drm-next.
Should I just rebase on top of current head of drm-next?
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: mbuf changes
From: Alejandro Lucero @ 2016-11-09 11:42 UTC (permalink / raw)
To: Bruce Richardson
Cc: Shreyansh Jain, Wiles, Keith, Morten Brørup, dev@dpdk.org,
Olivier Matz
In-Reply-To: <CAD+H9900j7LdYH79xBBO5wfHwomagLqpwqsDjuyJxozomL-dug@mail.gmail.com>
On Wed, Oct 26, 2016 at 10:28 AM, Alejandro Lucero <
alejandro.lucero@netronome.com> wrote:
>
>
> On Tue, Oct 25, 2016 at 2:05 PM, Bruce Richardson <
> bruce.richardson@intel.com> wrote:
>
>> On Tue, Oct 25, 2016 at 05:24:28PM +0530, Shreyansh Jain wrote:
>> > On Monday 24 October 2016 09:55 PM, Bruce Richardson wrote:
>> > > On Mon, Oct 24, 2016 at 04:11:33PM +0000, Wiles, Keith wrote:
>> > > >
>> > > > > On Oct 24, 2016, at 10:49 AM, Morten Brørup <
>> mb@smartsharesystems.com> wrote:
>> > > > >
>> > > > > First of all: Thanks for a great DPDK Userspace 2016!
>> > > > >
>> > > > >
>> > > > >
>> > > > > Continuing the Userspace discussion about Olivier Matz’s proposed
>> mbuf changes...
>> > >
>> > > Thanks for keeping the discussion going!
>> > > > >
>> > > > >
>> > > > >
>> > > > > 1.
>> > > > >
>> > > > > Stephen Hemminger had a noteworthy general comment about keeping
>> metadata for the NIC in the appropriate section of the mbuf: Metadata
>> generated by the NIC’s RX handler belongs in the first cache line, and
>> metadata required by the NIC’s TX handler belongs in the second cache line.
>> This also means that touching the second cache line on ingress should be
>> avoided if possible; and Bruce Richardson mentioned that for this reason
>> m->next was zeroed on free().
>> > > > >
>> > > Thinking about it, I suspect there are more fields we can reset on
>> free
>> > > to save time on alloc. Refcnt, as discussed below is one of them, but
>> so
>> > > too could be the nb_segs field and possibly others.
>> > >
>> > > > >
>> > > > >
>> > > > > 2.
>> > > > >
>> > > > > There seemed to be consensus that the size of m->refcnt should
>> match the size of m->port because a packet could be duplicated on all
>> physical ports for L3 multicast and L2 flooding.
>> > > > >
>> > > > > Furthermore, although a single physical machine (i.e. a single
>> server) with 255 physical ports probably doesn’t exist, it might contain
>> more than 255 virtual machines with a virtual port each, so it makes sense
>> extending these mbuf fields from 8 to 16 bits.
>> > > >
>> > > > I thought we also talked about removing the m->port from the mbuf
>> as it is not really needed.
>> > > >
>> > > Yes, this was mentioned, and also the option of moving the port value
>> to
>> > > the second cacheline, but it appears that NXP are using the port value
>> > > in their NIC drivers for passing in metadata, so we'd need their
>> > > agreement on any move (or removal).
>> >
>> > I am not sure where NXP's NIC came into picture on this, but now that
>> it is
>> > highlighted, this field is required for libevent implementation [1].
>> >
>> > A scheduler sending an event, which can be a packet, would only have
>> > information of a flow_id. From this matching it back to a port, without
>> > mbuf->port, would be very difficult (costly). There may be way around
>> this
>> > but at least in current proposal I think port would be important to
>> have -
>> > even if in second cache line.
>> >
>> > But, off the top of my head, as of now it is not being used for any
>> specific
>> > purpose in NXP's PMD implementation.
>> >
>> > Even the SoC patches don't necessarily rely on it except using it
>> because it
>> > is available.
>> >
>> > @Bruce: where did you get the NXP context here from?
>> >
>> Oh, I'm just mis-remembering. :-( It was someone else who was looking for
>> this - Netronome, perhaps?
>>
>> CC'ing Alejandro in the hope I'm remembering correctly second time
>> round!
>>
>>
> Yes. Thanks Bruce!
>
> So Netronome uses the port field and, as I commented on the user meeting,
> we are happy with the field going from 8 to 16 bits.
>
> In our case, this is something some clients have demanded, and if I'm not
> wrong (I'll double check this asap), the port value is for knowing where
> the packet is coming from. Think about a switch in the NIC, with ports
> linked to VFs/VMs, and one or more physical ports. That port value is not
> related to DPDK ports but to the switch ports. Code in the host (DPDK or
> not) can receive packets from the wire or from VFs through the NIC. This is
> also true for packets received by VMs, but I guess the port value is just
> interested for host code.
>
>
>
I consulted this functionality internally and it seems we do not need this
anymore. In fact, I will remove the metadata port handling soon from our
PMD.
> /Bruce
>>
>
>
^ permalink raw reply
* [PATCH 4.4 55/69] x86/xen: fix upper bound of pmd loop in xen_cleanhighmap()
From: Greg Kroah-Hartman @ 2016-11-09 10:44 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Linus Torvalds, Juergen Gross,
David Vrabel
In-Reply-To: <20161109102901.127641653@linuxfoundation.org>
4.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Juergen Gross <jgross@suse.com>
commit 1cf38741308c64d08553602b3374fb39224eeb5a upstream.
xen_cleanhighmap() is operating on level2_kernel_pgt only. The upper
bound of the loop setting non-kernel-image entries to zero should not
exceed the size of level2_kernel_pgt.
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/x86/xen/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -1113,7 +1113,7 @@ static void __init xen_cleanhighmap(unsi
/* NOTE: The loop is more greedy than the cleanup_highmap variant.
* We include the PMD passed in on _both_ boundaries. */
- for (; vaddr <= vaddr_end && (pmd < (level2_kernel_pgt + PAGE_SIZE));
+ for (; vaddr <= vaddr_end && (pmd < (level2_kernel_pgt + PTRS_PER_PMD));
pmd++, vaddr += PMD_SIZE) {
if (pmd_none(*pmd))
continue;
^ permalink raw reply
* Re: [PATCH v2 4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
From: David Weinehall @ 2016-11-09 11:42 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
In-Reply-To: <1478691045-18433-1-git-send-email-tvrtko.ursulin@linux.intel.com>
On Wed, Nov 09, 2016 at 11:30:45AM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> After this patch only conversion of INTEL_INFO(p)->gen to
> INTEL_GEN(dev_priv) remains before the __I915__ macro can
> be removed.
>
> v2: Tidy vlv_compute_wm. (David Weinehall)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_color.c | 31 ++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++---------------
> drivers/gpu/drm/i915/intel_fbdev.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_pm.c | 12 +++++++-----
> 6 files changed, 42 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0213a3090ab3..20b1e19d982b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev)
> /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
> * (which really amounts to a PCH but no South Display).
> */
> - if (INTEL_INFO(dev)->num_pipes == 0) {
> + if (INTEL_INFO(dev_priv)->num_pipes == 0) {
> dev_priv->pch_type = PCH_NOP;
> return;
> }
> @@ -607,7 +607,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>
> intel_modeset_gem_init(dev);
>
> - if (INTEL_INFO(dev)->num_pipes == 0)
> + if (INTEL_INFO(dev_priv)->num_pipes == 0)
> return 0;
>
> ret = intel_fbdev_init(dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index a5fafa3d4fc8..2eb22ba06bc0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -714,7 +714,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
> */
> static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
> {
> - ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
> + ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
> }
>
> /* Removes entries from a single page table, releasing it if it's empty.
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 445108855275..3784940a4e7a 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -345,11 +345,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
> static void broadwell_load_luts(struct drm_crtc_state *state)
> {
> struct drm_crtc *crtc = state->crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> - uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> + uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>
> if (crtc_state_is_legacy(state)) {
> haswell_load_luts(state);
> @@ -428,8 +427,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
> static void cherryview_load_luts(struct drm_crtc_state *state)
> {
> struct drm_crtc *crtc = state->crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> struct drm_color_lut *lut;
> uint32_t i, lut_size;
> @@ -446,7 +444,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>
> if (state->degamma_lut) {
> lut = (struct drm_color_lut *) state->degamma_lut->data;
> - lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> + lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> for (i = 0; i < lut_size; i++) {
> /* Write LUT in U0.14 format. */
> word0 =
> @@ -461,7 +459,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>
> if (state->gamma_lut) {
> lut = (struct drm_color_lut *) state->gamma_lut->data;
> - lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
> + lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> for (i = 0; i < lut_size; i++) {
> /* Write LUT in U0.10 format. */
> word0 =
> @@ -497,12 +495,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state)
> int intel_color_check(struct drm_crtc *crtc,
> struct drm_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> size_t gamma_length, degamma_length;
>
> - degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
> + degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
> sizeof(struct drm_color_lut);
> - gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
> + gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
> sizeof(struct drm_color_lut);
>
> /*
> @@ -529,8 +527,7 @@ int intel_color_check(struct drm_crtc *crtc,
>
> void intel_color_init(struct drm_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>
> drm_mode_crtc_set_gamma_size(crtc, 256);
>
> @@ -549,10 +546,10 @@ void intel_color_init(struct drm_crtc *crtc)
> }
>
> /* Enable color management support when we have degamma & gamma LUTs. */
> - if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
> - INTEL_INFO(dev)->color.gamma_lut_size != 0)
> + if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
> + INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
> drm_crtc_enable_color_mgmt(crtc,
> - INTEL_INFO(dev)->color.degamma_lut_size,
> - true,
> - INTEL_INFO(dev)->color.gamma_lut_size);
> + INTEL_INFO(dev_priv)->color.degamma_lut_size,
> + true,
> + INTEL_INFO(dev_priv)->color.gamma_lut_size);
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2a1abf293a35..e0ad0975755e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7053,7 +7053,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> }
> }
>
> - if (INTEL_INFO(dev)->num_pipes == 2)
> + if (INTEL_INFO(dev_priv)->num_pipes == 2)
> return 0;
>
> /* Ivybridge 3 pipe is really complicated */
> @@ -14725,8 +14725,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> {
> struct intel_atomic_state *intel_state =
> to_intel_atomic_state(new_state->state);
> - struct drm_device *dev = plane->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct drm_framebuffer *fb = new_state->fb;
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> @@ -14783,7 +14782,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> }
>
> if (plane->type == DRM_PLANE_TYPE_CURSOR &&
> - INTEL_INFO(dev)->cursor_needs_physical) {
> + INTEL_INFO(dev_priv)->cursor_needs_physical) {
> int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
> ret = i915_gem_object_attach_phys(obj, align);
> if (ret) {
> @@ -14816,7 +14815,7 @@ void
> intel_cleanup_plane_fb(struct drm_plane *plane,
> struct drm_plane_state *old_state)
> {
> - struct drm_device *dev = plane->dev;
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct intel_plane_state *old_intel_state;
> struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
> struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
> @@ -14827,7 +14826,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
> return;
>
> if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
> - !INTEL_INFO(dev)->cursor_needs_physical))
> + !INTEL_INFO(dev_priv)->cursor_needs_physical))
> intel_unpin_fb_obj(old_state->fb, old_state->rotation);
> }
>
> @@ -15152,13 +15151,13 @@ intel_update_cursor_plane(struct drm_plane *plane,
> {
> struct drm_crtc *crtc = crtc_state->base.crtc;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct drm_device *dev = plane->dev;
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
> uint32_t addr;
>
> if (!obj)
> addr = 0;
> - else if (!INTEL_INFO(dev)->cursor_needs_physical)
> + else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
> addr = i915_gem_object_ggtt_offset(obj, NULL);
> else
> addr = obj->phys_handle->busaddr;
> @@ -16440,7 +16439,7 @@ int intel_modeset_init(struct drm_device *dev)
>
> intel_init_pm(dev_priv);
>
> - if (INTEL_INFO(dev)->num_pipes == 0)
> + if (INTEL_INFO(dev_priv)->num_pipes == 0)
> return 0;
>
> /*
> @@ -16486,8 +16485,8 @@ int intel_modeset_init(struct drm_device *dev)
> dev->mode_config.fb_base = ggtt->mappable_base;
>
> DRM_DEBUG_KMS("%d display pipe%s available.\n",
> - INTEL_INFO(dev)->num_pipes,
> - INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
> + INTEL_INFO(dev_priv)->num_pipes,
> + INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
>
> for_each_pipe(dev_priv, pipe) {
> int ret;
> @@ -16575,11 +16574,10 @@ static void intel_enable_pipe_a(struct drm_device *dev)
> static bool
> intel_check_plane_mapping(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 val;
>
> - if (INTEL_INFO(dev)->num_pipes == 1)
> + if (INTEL_INFO(dev_priv)->num_pipes == 1)
> return true;
>
> val = I915_READ(DSPCNTR(!crtc->plane));
> @@ -17332,7 +17330,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
> if (!error)
> return;
>
> - err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
> + err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> err_printf(m, "PWR_WELL_CTL2: %08x\n",
> error->power_well_driver);
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> index b7098f98bb67..e3cf655bec3b 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -359,7 +359,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
> struct drm_fb_offset *offsets,
> bool *enabled, int width, int height)
> {
> - struct drm_device *dev = fb_helper->dev;
> + struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
> unsigned long conn_configured, mask;
> unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
> int i, j;
> @@ -512,7 +512,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
> * fbdev helper library.
> */
> if (num_connectors_enabled != num_connectors_detected &&
> - num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
> + num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
> DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
> DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
> num_connectors_detected);
> @@ -700,11 +700,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
>
> int intel_fbdev_init(struct drm_device *dev)
> {
> - struct intel_fbdev *ifbdev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_fbdev *ifbdev;
> int ret;
>
> - if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
> + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
> return -ENODEV;
>
> ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
> @@ -717,7 +717,7 @@ int intel_fbdev_init(struct drm_device *dev)
> ifbdev->preferred_bpp = 32;
>
> ret = drm_fb_helper_init(dev, &ifbdev->helper,
> - INTEL_INFO(dev)->num_pipes, 4);
> + INTEL_INFO(dev_priv)->num_pipes, 4);
> if (ret) {
> kfree(ifbdev);
> return ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 88e28c989b9c..368f801aee0f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1061,7 +1061,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
>
> for (level = 0; level < wm_state->num_levels; level++) {
> struct drm_device *dev = crtc->base.dev;
> - const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> + const int sr_fifo_size =
> + INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
> struct intel_plane *plane;
>
> wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
> @@ -1091,15 +1092,16 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
> static void vlv_compute_wm(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct vlv_wm_state *wm_state = &crtc->wm_state;
> struct intel_plane *plane;
> - int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> + int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
> int level;
>
> memset(wm_state, 0, sizeof(*wm_state));
>
> wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
> - wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
> + wm_state->num_levels = dev_priv->wm.max_level + 1;
>
> wm_state->num_active_planes = 0;
>
> @@ -1179,7 +1181,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
> }
>
> /* clear any (partially) filled invalid levels */
> - for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
> + for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
> memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
> memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
> }
> @@ -1920,7 +1922,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
>
> /* HSW allows LP1+ watermarks even with multiple pipes */
> if (level == 0 || config->num_pipes_active > 1) {
> - fifo_size /= INTEL_INFO(dev)->num_pipes;
> + fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
>
> /*
> * For some reason the non self refresh
> --
> 2.7.4
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [PATCH 4.4 50/69] drm/radeon/si_dpm: Limit clocks on HD86xx part
From: Greg Kroah-Hartman @ 2016-11-09 10:44 UTC (permalink / raw)
To: linux-kernel; +Cc: Greg Kroah-Hartman, stable, Tom St Denis, Alex Deucher
In-Reply-To: <20161109102901.127641653@linuxfoundation.org>
4.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tom St Denis <tom.stdenis@amd.com>
commit fb9a5b0c1c9893db2e0d18544fd49e19d784a87d upstream.
Limit clocks on a specific HD86xx part to avoid
crashes (while awaiting an appropriate PP fix).
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/gpu/drm/radeon/si_dpm.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -3021,6 +3021,12 @@ static void si_apply_state_adjust_rules(
max_sclk = 75000;
max_mclk = 80000;
}
+ /* limit clocks on HD8600 series */
+ if (rdev->pdev->device == 0x6660 &&
+ rdev->pdev->revision == 0x83) {
+ max_sclk = 75000;
+ max_mclk = 80000;
+ }
if (rps->vce_active) {
rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
^ permalink raw reply
* [LTP] [PATCH 1/1] network: portability: using tst_sleep instead of usleep
From: Alexey Kodanev @ 2016-11-09 11:43 UTC (permalink / raw)
To: ltp
In-Reply-To: <20161108161351.16366-1-pvorel@suse.cz>
Hi,
On 11/08/2016 07:13 PM, Petr Vorel wrote:
> Signed-off-by: Petr Vorel <pvorel@suse.cz>
> ---
> testcases/network/dhcp/dhcp_lib.sh | 4 ++--
> testcases/network/tcp_cmds/ipneigh/ipneigh01.sh | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/testcases/network/dhcp/dhcp_lib.sh b/testcases/network/dhcp/dhcp_lib.sh
> index 140619d..85f9b88 100755
> --- a/testcases/network/dhcp/dhcp_lib.sh
> +++ b/testcases/network/dhcp/dhcp_lib.sh
> @@ -26,12 +26,12 @@ stop_dhcp()
> while [ $count -le 10 ]; do
> pkill -x $dhcp_name
> [ "$(pgrep -x $dhcp_name)" ] || return 0
> - usleep 100000
> + tst_sleep 100ms
> count=$((count + 1))
> done
>
> pkill -9 -x $dhcp_name
> - usleep 100000
> + tst_sleep 100ms
> [ "$(pgrep -x $dhcp_name)" ] && return 1 || return 0
> }
>
> diff --git a/testcases/network/tcp_cmds/ipneigh/ipneigh01.sh b/testcases/network/tcp_cmds/ipneigh/ipneigh01.sh
> index 736d149..31d6cc6 100755
> --- a/testcases/network/tcp_cmds/ipneigh/ipneigh01.sh
> +++ b/testcases/network/tcp_cmds/ipneigh/ipneigh01.sh
> @@ -52,7 +52,7 @@ do_test()
> ret=0
> break;
> fi
> - usleep 100
> + tst_sleep 100us
Patch applied. I've changed sleep time here to 'ms', it should have been
"usleep 100000", so the patch is fixing it as well,
added comment about this in the patch.
Thanks,
Alexey
> done
>
> [ "$ret" -ne 0 ] && \
^ permalink raw reply
* [PATCH 4.4 48/69] mmc: dw_mmc-pltfm: fix the potential NULL pointer dereference
From: Greg Kroah-Hartman @ 2016-11-09 10:44 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, Jaehoon Chung, Shawn Lin, Ulf Hansson
In-Reply-To: <20161109102901.127641653@linuxfoundation.org>
4.4-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jaehoon Chung <jh80.chung@samsung.com>
commit 45c7a4908a307a023e237a64a3eadcafc4836493 upstream.
platform_get_resource can be returned the NULL pointer.
Then regs->start should be referred to NULL Pointer.
devm_ioremap_resource() checks whether res is NULL or not.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/mmc/host/dw_mmc-pltfm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,12 +59,13 @@ int dw_mci_pltfm_register(struct platfor
host->pdata = pdev->dev.platform_data;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- /* Get registers' physical base address */
- host->phy_regs = regs->start;
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
+ /* Get registers' physical base address */
+ host->phy_regs = regs->start;
+
platform_set_drvdata(pdev, host);
return dw_mci_probe(host);
}
^ permalink raw reply
* [U-Boot] [PATCH v3 1/3] ARM: bcm283x: Implement EFI RTS reset_system
From: Alexander Graf @ 2016-11-09 11:43 UTC (permalink / raw)
To: u-boot
In-Reply-To: <638879b7-d206-69b2-2e32-53ec00c9d2cd@wwwdotorg.org>
On 07/11/2016 22:26, Stephen Warren wrote:
> On 11/06/2016 03:24 AM, Alexander Graf wrote:
>>
>>
>> On 05/11/2016 23:01, Stephen Warren wrote:
>>> On 11/02/2016 03:36 AM, Alexander Graf wrote:
>>>> The rpi has a pretty simple way of resetting the whole system. All it
>>>> takes
>>>> is to poke a few registers at a well defined location in MMIO space.
>>>>
>>>> This patch adds support for the EFI loader implementation to allow an
>>>> OS to
>>>> reset and power off the system when we're outside of boot time.
>>>
>>> (As an aside, I'm not sure why someone wanting EFI wouldn't just use a
>>> complete EFI implementation such as TianoCore.)
>>>
>>>> diff --git a/arch/arm/mach-bcm283x/reset.c
>>>> b/arch/arm/mach-bcm283x/reset.c
>>>
>>>> +__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
>>>> + (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
>>>> +
>>>> +void __efi_runtime reset_cpu(ulong addr)
>>>> {
>>>> - struct bcm2835_wdog_regs *regs =
>>>> - (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
>>>
>>> I'm not sure why that change is required. The value of the variable is
>>> the same in both cases?
>>
>> Take a look a few lines down in the patch:
>>
>>> +void efi_reset_system_init(void)
>>> +{
>>> + efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs));
>>> +}
>>
>> What this does is register a *pointer* as run time service pointer. What
>> does that mean?
>>
>> When we enter RTS, Linux can map any region in the EFI memory map into a
>> different place in its own virtual memory map. So any pointers we use
>> inside RTS have to be relocated to the new locations.
>>
>> For normal relocations, we move the relocations from linker time to run
>> time, so that we can relocate ourselves when Linux does the switch-over
>> to a new address space.
>>
>> However, for MMIO that's trickier. That's where the
>> efi_add_runtime_mmio() function comes into play. It takes care of adding
>> the page around the references address to the EFI memory map as RTS MMIO
>> and relocates the pointer when Linux switches us into the new address
>> space.
>>
>> Does that explain why we need to move from an inline address to an
>> address stored in a memory location?
>
> So EFI RTS runs in the same exception level as the rich OS, and not in
> EL3? I would have expected EFI to run in EL3 with a completely separate
> MMU configuration. If that's not the case, then this part of the patch
> does make sense.
Right, it runs in EL2/EL1 with a virtual memory layout that is provided
by the OS.
>
>>> Perhaps it's trying to ensure that if this gets compiled into an ldr
>>> instruction, the referenced data value is in a linker section that's
>>> still around when EFI runs? If so fine, but how is that ensured for all
>>> the other constants that this code uses, and if that happens
>>> automatically due to the __efi_runtime marker above, why doesn't it work
>>> for this one constant?
>>>
>>> Does U-Boot have a halt/poweroff/shutdown shell command? If so, it might
>>> be nice to enable it as part of this series, since the code to perform
>>> that operation is now present.
>>
>> That's what I originally wanted, yes :). Unfortunately due to the
>> relocation explained above, it's basically impossible for any reset
>> function that calls into MMIO space.
>>
>> However, we do have it now for PSCI. If you have a PSCI enabled system,
>> we don't need to call into MMIO space and thus make the common reset
>> function available as RTS.
>
> Can't the same U-Boot function be called both (a) during U-Boot runtime,
> where wdog_regs are pre-initialized to match U-Boot's MMU configuration,
> and (b) once the OS has booted, where wdog_regs has been modified
> according to the new memory map?
That's exactly what this patch does, no?
> If not, one could implement a reset/powerdown/... function that takes
> the MMIO virtual address as a pointer, and then separate trivial
> wrappers that pass in either the static/U-Boot MMIO address, or the
> value of the EFI runtime variable that points at the MMIO mapping.
You could, but because the runtime version would still have to rely on
an external variable because it doesn't know where it'll end up at
runtime, you may as well use an external variable throughout and arrive
back at this patch ;).
Alex
^ permalink raw reply
* Re: [Intel-gfx] [PATCH v3] drm: move allocation out of drm_get_format_name()
From: Eric Engestrom @ 2016-11-09 11:42 UTC (permalink / raw)
To: Eric Engestrom, linux-kernel, David Airlie, dri-devel,
Wei Yongjun, Daniel Vetter, Flora Cui, Gustavo Padovan,
Tom St Denis, Chunming Zhou, Thomas Hellstrom, Laurent Pinchart,
Sinclair Yeh, Xinliang Liu, Xinwei Kong, VMware Graphics,
Vitaly Prosyak, Alexandre Demers, Jani Nikula, intel-gfx,
Emily Deng, Colin Ian King, Junwei Zhang, Michel Dänzer,
Alex Deucher, Christian König
In-Reply-To: <20161109011325.hvvfsvpq734nduxd@phenom.ffwll.local>
On Wednesday, 2016-11-09 02:13:25 +0100, Daniel Vetter wrote:
> On Wed, Nov 09, 2016 at 02:09:16AM +0100, Daniel Vetter wrote:
> > On Wed, Nov 09, 2016 at 12:17:52AM +0000, Eric Engestrom wrote:
> > > The function's behaviour was changed in 90844f00049e, without changing
> > > its signature, causing people to keep using it the old way without
> > > realising they were now leaking memory.
> > > Rob Clark also noticed it was also allocating GFP_KERNEL memory in
> > > atomic contexts, breaking them.
> > >
> > > Instead of having to allocate GFP_ATOMIC memory and fixing the callers
> > > to make them cleanup the memory afterwards, let's change the function's
> > > signature by having the caller take care of the memory and passing it to
> > > the function.
> > > The new parameter is a single-field struct in order to enforce the size
> > > of its buffer and help callers to correctly manage their memory.
> > >
> > > Fixes: 90844f00049e ("drm: make drm_get_format_name thread-safe")
> > > Cc: Rob Clark <robdclark@gmail.com>
> > > Cc: Christian König <christian.koenig@amd.com>
> > > Acked-by: Christian König <christian.koenig@amd.com>
> > > Acked-by: Rob Clark <robdclark@gmail.com>
> > > Acked-by: Sinclair Yeh <syeh@vmware.com> (vmwgfx)
> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Eric Engestrom <eric@engestrom.ch>
> > > ---
> > > v3 - fix "Fixes" tag, replace it with an actual commit message
> > > - collect ack & r-b
> > >
> > > v2 - use single-field struct instead of typedef to let the compiler
> > > enforce the type (Christian König)
> >
> > Applied to drm-misc, thanks.
>
> Well, had to drop it again since it didn't compile:
>
>
> CC [M] drivers/gpu/drm/drm_blend.o
> drivers/gpu/drm/drm_atomic.c: In function ‘drm_atomic_plane_print_state’:
> drivers/gpu/drm/drm_atomic.c:920:5: error: too few arguments to function ‘drm_get_format_name’
> drm_get_format_name(fb->pixel_format));
> ^~~~~~~~~~~~~~~~~~~
> In file included from ./include/drm/drmP.h:71:0,
> from drivers/gpu/drm/drm_atomic.c:29:
> ./include/drm/drm_fourcc.h:65:7: note: declared here
> char *drm_get_format_name(uint32_t format, struct drm_format_name_buf *buf);
> ^~~~~~~~~~~~~~~~~~~
>
> Can you pls rebase onto drm-misc or linux-next or something?
That was based on airlied/drm-next (last fetched on Sunday I think),
I can rebase it on drm-misc if it helps, but it seems older than
drm-next.
Should I just rebase on top of current head of drm-next?
^ permalink raw reply
* Re: [PATCH 1/4] x86/cpufeature: Add User-Mode Instruction Prevention definitions
From: Andy Lutomirski @ 2016-11-09 11:02 UTC (permalink / raw)
To: Ricardo Neri
Cc: Ingo Molnar, Thomas Gleixner, H. Peter Anvin,
linux-kernel@vger.kernel.org, X86 ML, linux-doc@vger.kernel.org,
Andy Lutomirski, Andrew Morton, Borislav Petkov, Brian Gerst,
Chen Yucong, Chris Metcalf, Dave Hansen, Fenghua Yu, Huang Rui,
Jiri Slaby, Jonathan Corbet, Michael S . Tsirkin, Paul Gortmaker,
Peter Zijlstra, Ravi V . Shankar, Shuah Khan, Vlastimil Babka
In-Reply-To: <1478665516.2533.2.camel@ranerica-desktop>
On Tue, Nov 8, 2016 at 8:25 PM, Ricardo Neri
<ricardo.neri-calderon@linux.intel.com> wrote:
> On Tue, 2016-11-08 at 07:32 -0800, Andy Lutomirski wrote:
>> > diff --git a/arch/x86/include/asm/disabled-features.h
>> b/arch/x86/include/asm/disabled-features.h
>> > index 85599ad..4707445 100644
>> > --- a/arch/x86/include/asm/disabled-features.h
>> > +++ b/arch/x86/include/asm/disabled-features.h
>> > @@ -16,6 +16,12 @@
>> > # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31))
>> > #endif
>> >
>> > +#ifdef CONFIG_X86_INTEL_UMIP
>>
>> ^^^^^
>>
>> What's this?
>>
>> Let's try to do this with a minimum of configuration.
>
> My intention here is put in this file all the #if build configurations
> so that I don't have to put them other files by using functions such as
> cpu_feature_enable. Isn't this the intention of this file?
What I mean is: why does this need a config option at all?
--Andy
^ permalink raw reply
* [LTP] [PATCH 1/1] network: fix bashisms + shebang
From: Alexey Kodanev @ 2016-11-09 11:44 UTC (permalink / raw)
To: ltp
In-Reply-To: <20161108180516.10498-1-pvorel@suse.cz>
On 11/08/2016 09:05 PM, Petr Vorel wrote:
> Signed-off-by: Petr Vorel <pvorel@suse.cz>
> ---
> testcases/network/nfs/nfs_stress/nfs_lib.sh | 1 +
> testcases/network/sockets/ltpSockets.sh | 4 ++--
> testcases/network/virt/virt_lib.sh | 3 ++-
> 3 files changed, 5 insertions(+), 3 deletions(-)
Patch applied. Thank you!
Best regards,
Alexey
^ permalink raw reply
* [PATCH RFC 00/12] tda998x updates
From: Jon Medhurst (Tixy) @ 2016-11-09 11:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161108182434.GX1041@n2100.armlinux.org.uk>
On Tue, 2016-11-08 at 18:24 +0000, Russell King - ARM Linux wrote:
> On Tue, Nov 08, 2016 at 05:20:36PM +0000, Jon Medhurst (Tixy) wrote:
> > On Tue, 2016-11-08 at 13:34 +0000, Russell King - ARM Linux wrote:
> > > On Tue, Nov 08, 2016 at 01:32:15PM +0000, Russell King - ARM Linux wrote:
> > > > Unfortunately, my drm-tda998x-devel branch is slightly out of date with
> > > > these patches it's the original set of 10 patches. I've not pushed
> > > > these ones out to that branch yet, as I've three additional patches on
> > > > top of these which aren't "ready" for pushing out.
> > >
> > > Here's the delta between the branch and what I just posted:
> > >
> > > diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
> > [...]
> >
> > I have a working setup for HDMI audio on Juno an would like to test this
> > series but am struggling to work out which patches to apply in what
> > order to what branch, can you be specific? (I've tried various
> > combinations of patches series from the list, drm-tda998x-devel, and the
> > diff you posted)
>
> Hmm, I guess this is going to be annoyingly rather difficult then.
> The structure of my git tree is:
>
> v4.8 ---------------- mali patch ------------------ merge --- these patches
> v4.7 -- tda998x audio patches (up to df0bd1e8f3c5) --^
>
> which makes it rather difficult to send out a series that people can
> apply as patches without first replicating that merge. I guess the
> answer is... use the _patches_ for review, and I'll push out the
> changes into drm-tda998x-devel... should be there soon. Look for
> commit hash d61fa2e50f2a. (Bah, slow 'net connections.)
Testing gets more complicated as I'm using 4.9-rc? which has a DMA fix
needed for audio [1] and breaks hdmi-codec which I hope I fixed [2].
Anyway, I merged in drm-tda998x-devel and audio continued to work on my
HDMI connected monitor. So I guess that's
Tested-by: Jon Medhurst <tixy@linaro.org>
I also reviewed the patches in this series. They look like a mostly
mechanical code organisation improvement, and whilst I'm not very
familiar with the driver and DRM, the other actual code changes look OK
too. So, FWIW:
Acked-by: Jon Medhurst <tixy@linaro.org>
[1] Commit d64e9a2c7509 ("dmaengine: pl330: fix residual for non-running BUSY descriptors")
[2] https://patchwork.kernel.org/patch/9401485/
--
Tixy
^ permalink raw reply
* Re: [PATCH RFC 00/12] tda998x updates
From: Jon Medhurst (Tixy) @ 2016-11-09 11:45 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Liviu Dudau, dri-devel, Jyri Sarha, Robin Murphy, Brian Starkey,
linux-arm-kernel
In-Reply-To: <20161108182434.GX1041@n2100.armlinux.org.uk>
On Tue, 2016-11-08 at 18:24 +0000, Russell King - ARM Linux wrote:
> On Tue, Nov 08, 2016 at 05:20:36PM +0000, Jon Medhurst (Tixy) wrote:
> > On Tue, 2016-11-08 at 13:34 +0000, Russell King - ARM Linux wrote:
> > > On Tue, Nov 08, 2016 at 01:32:15PM +0000, Russell King - ARM Linux wrote:
> > > > Unfortunately, my drm-tda998x-devel branch is slightly out of date with
> > > > these patches it's the original set of 10 patches. I've not pushed
> > > > these ones out to that branch yet, as I've three additional patches on
> > > > top of these which aren't "ready" for pushing out.
> > >
> > > Here's the delta between the branch and what I just posted:
> > >
> > > diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
> > [...]
> >
> > I have a working setup for HDMI audio on Juno an would like to test this
> > series but am struggling to work out which patches to apply in what
> > order to what branch, can you be specific? (I've tried various
> > combinations of patches series from the list, drm-tda998x-devel, and the
> > diff you posted)
>
> Hmm, I guess this is going to be annoyingly rather difficult then.
> The structure of my git tree is:
>
> v4.8 ---------------- mali patch ------------------ merge --- these patches
> v4.7 -- tda998x audio patches (up to df0bd1e8f3c5) --^
>
> which makes it rather difficult to send out a series that people can
> apply as patches without first replicating that merge. I guess the
> answer is... use the _patches_ for review, and I'll push out the
> changes into drm-tda998x-devel... should be there soon. Look for
> commit hash d61fa2e50f2a. (Bah, slow 'net connections.)
Testing gets more complicated as I'm using 4.9-rc? which has a DMA fix
needed for audio [1] and breaks hdmi-codec which I hope I fixed [2].
Anyway, I merged in drm-tda998x-devel and audio continued to work on my
HDMI connected monitor. So I guess that's
Tested-by: Jon Medhurst <tixy@linaro.org>
I also reviewed the patches in this series. They look like a mostly
mechanical code organisation improvement, and whilst I'm not very
familiar with the driver and DRM, the other actual code changes look OK
too. So, FWIW:
Acked-by: Jon Medhurst <tixy@linaro.org>
[1] Commit d64e9a2c7509 ("dmaengine: pl330: fix residual for non-running BUSY descriptors")
[2] https://patchwork.kernel.org/patch/9401485/
--
Tixy
^ permalink raw reply
* ✗ Fi.CI.BAT: warning for drm/i915/gvt: Disable access to stolen memory as a guest
From: Patchwork @ 2016-11-09 11:45 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
In-Reply-To: <20161109103905.17860-1-chris@chris-wilson.co.uk>
== Series Details ==
Series: drm/i915/gvt: Disable access to stolen memory as a guest
URL : https://patchwork.freedesktop.org/series/15022/
State : warning
== Summary ==
Series 15022v1 drm/i915/gvt: Disable access to stolen memory as a guest
https://patchwork.freedesktop.org/api/1.0/series/15022/revisions/1/mbox/
Test kms_force_connector_basic:
Subgroup force-edid:
pass -> DMESG-WARN (fi-snb-2520m)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-snb-2520m total:244 pass:211 dwarn:1 dfail:0 fail:0 skip:32
fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
972b631c86ecf25d43d16b3617672f481a5cbd08 drm-intel-nightly: 2016y-11m-09d-10h-46m-28s UTC integration manifest
2b2fda9 drm/i915/gvt: Disable access to stolen memory as a guest
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2940/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: [Ksummit-discuss] Including images on Sphinx documents
From: Jani Nikula @ 2016-11-09 11:45 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Markus Heiser, linux-media, linux-kernel, ksummit-discuss,
linux-doc
In-Reply-To: <20161109092708.786f55da@vento.lan>
On Wed, 09 Nov 2016, Mauro Carvalho Chehab <mchehab@s-opensource.com> wrote:
> Em Wed, 09 Nov 2016 13:16:55 +0200
> Jani Nikula <jani.nikula@linux.intel.com> escreveu:
>
>> >> 1) copy (or symlink) all rst files to Documentation/output (or to the
>> >> build dir specified via O= directive) and generate the *.pdf there,
>> >> and produce those converted images via Makefile.;
>>
>> We're supposed to solve problems, not create new ones.
>
> So, what's your proposal?
Second message in the thread,
http://lkml.kernel.org/r/87wpgf8ssc.fsf@intel.com
>
> Thanks,
> Mauro
> _______________________________________________
> Ksummit-discuss mailing list
> Ksummit-discuss@lists.linuxfoundation.org
> https://lists.linuxfoundation.org/mailman/listinfo/ksummit-discuss
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply
* Re: [Ksummit-discuss] Including images on Sphinx documents
From: Jani Nikula @ 2016-11-09 11:45 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Markus Heiser, ksummit-discuss, linux-doc, linux-kernel,
linux-media
In-Reply-To: <20161109092708.786f55da@vento.lan>
On Wed, 09 Nov 2016, Mauro Carvalho Chehab <mchehab@s-opensource.com> wrote:
> Em Wed, 09 Nov 2016 13:16:55 +0200
> Jani Nikula <jani.nikula@linux.intel.com> escreveu:
>
>> >> 1) copy (or symlink) all rst files to Documentation/output (or to the
>> >> build dir specified via O= directive) and generate the *.pdf there,
>> >> and produce those converted images via Makefile.;
>>
>> We're supposed to solve problems, not create new ones.
>
> So, what's your proposal?
Second message in the thread,
http://lkml.kernel.org/r/87wpgf8ssc.fsf@intel.com
>
> Thanks,
> Mauro
> _______________________________________________
> Ksummit-discuss mailing list
> Ksummit-discuss@lists.linuxfoundation.org
> https://lists.linuxfoundation.org/mailman/listinfo/ksummit-discuss
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply
* Re: [Discussion] Performance levels of power domains
From: Viresh Kumar @ 2016-11-09 11:46 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Kevin Hilman, linux-pm@vger.kernel.org, Rafael J. Wysocki,
Vincent Guittot, Ulf Hansson, Michael Turquette, Stephen Boyd,
Nayak, Rajendra, Georgi Djakov, Lists linaro-kernel, Mark Brown
In-Reply-To: <CAJZ5v0jPeauJGpQfr1VjDo1Z-Xd6UT4_4QLeso_CSEtB4zyaag@mail.gmail.com>
On 27 October 2016 at 15:41, Rafael J. Wysocki <rafael@kernel.org> wrote:
> On Wed, Oct 26, 2016 at 9:00 PM, Kevin Hilman <khilman@baylibre.com> wrote:
>> Viresh Kumar <viresh.kumar@linaro.org> writes:
>>
>>> Hi Guys,
>>>
>>> I wanted to involve you guys to get a discussion going
>>> for a problem we want to solve, and so this mail.
>>>
>>>
>>> Platform details:
>>>
>>> Some of the Qualcom SoCs have the option to configure
>>> the performance level of their Power Domains. The performance
>>> levels are identified by integer values (lets say 0-9, 0 being the lowest).
>>>
>>> Another M3 core handles the *real* voltage scaling based on the input
>>> received (from software) in terms of these performance levels. The M3
>>> core translates the levels into a range of voltages (corners) and selects
>>> the right one by itself.
>>>
>>> Software needs to provide the performance level for the entire domain
>>> to the M3 core and so software also needs to handle performance requests
>>> from all the devices that lie in the domain X and find a Performance Level P,
>>> which can satisfy all the devices (normally the highest requrested level).
>>>
>>>
>>> Problem statement:
>>>
>>> As we aren't dealing with Voltages here, we can't really get the benefits
>>> of the Regulators framework. The regulators are managed internally
>>> by the M3 core. All we need is a way for software to comeout with inputs
>>> for the M3 core.
>>>
>>> The OPP framework can be used to include performance levels for
>>> each OPP (frequency) entry.
>>>
>>> But what framework can be used to select performance level of power
>>> domains ?
>>>
>>> By name, power-domain or genpd looks to be the right choice, but until
>>> now it is only managing power-on and power-off of devices and domains.
>>
>> genpd has also recently been extended to support multiple states, though
>> those are still idle states, not active (performance) states.
>>
>>> Should we extend that (along with runtime PM), or do something else?
>>
>> Yes. As I've suggested to qcom/linaro folks (off-list discussions), I
>> think extending genpd to handle performance states is a logical
>> extension. Otherwise, you will be (re)inventing something that looks an
>> awful lot like genpd anyways.
>
> On the Intel side we also have a mechanism to tell the processor about
> the power/performance preference and it would be good to have a common
> way to do it on all platforms and genpd doesn't look like a
> particularly good place for that.
>
>> The other related framework is per-device PM QoS which could be used to
>> set constraints on specific devices, and the genpd governors would then
>> be responsible for looking at the constraints and changing states as
>> needed.
>
> Right.
>
> Let's talk about this at the LPC.
Any updates from LPC on this ?
^ permalink raw reply
* Re: [PATCH v2] led: core: Use atomic bit-field for the blink-flags
From: Jacek Anaszewski @ 2016-11-09 11:47 UTC (permalink / raw)
To: linux-leds; +Cc: linux-kernel, Hans de Goede
In-Reply-To: <1478613535-32564-1-git-send-email-j.anaszewski@samsung.com>
Since we've already agreed on keeping the flags in the leds.h,
then I'm applying this patch to the for-next branch of linux-leds.git.
Thanks,
Jacek Anaszewski
On 11/08/2016 02:58 PM, Jacek Anaszewski wrote:
> From: Hans de Goede <hdegoede@redhat.com>
>
> All the LED_BLINK* flags are accessed read-modify-write from e.g.
> led_set_brightness and led_blink_set_oneshot while both
> set_brightness_work and the blink_timer may be running.
>
> If these race then the modify step done by one of them may be lost,
> switch the LED_BLINK* flags to a new atomic work_flags bit-field
> to avoid this race.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
> ---
> Changes since v1:
> - keep set_brightness_work in linux/leds.h
>
> drivers/leds/led-class.c | 1 +
> drivers/leds/led-core.c | 52 +++++++++++++++++++++++++-----------------------
> include/linux/leds.h | 24 ++++++++++++----------
> 3 files changed, 42 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
> index c8d2d67..b12f861 100644
> --- a/drivers/leds/led-class.c
> +++ b/drivers/leds/led-class.c
> @@ -212,6 +212,7 @@ int led_classdev_register(struct device *parent, struct led_classdev *led_cdev)
> return -ENODEV;
> }
>
> + led_cdev->work_flags = 0;
> #ifdef CONFIG_LEDS_TRIGGERS
> init_rwsem(&led_cdev->trigger_lock);
> #endif
> diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
> index e2e5cc7..620257a 100644
> --- a/drivers/leds/led-core.c
> +++ b/drivers/leds/led-core.c
> @@ -61,12 +61,13 @@ static void led_timer_function(unsigned long data)
>
> if (!led_cdev->blink_delay_on || !led_cdev->blink_delay_off) {
> led_set_brightness_nosleep(led_cdev, LED_OFF);
> - led_cdev->flags &= ~LED_BLINK_SW;
> + clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
> return;
> }
>
> - if (led_cdev->flags & LED_BLINK_ONESHOT_STOP) {
> - led_cdev->flags &= ~(LED_BLINK_ONESHOT_STOP | LED_BLINK_SW);
> + if (test_and_clear_bit(LED_BLINK_ONESHOT_STOP,
> + &led_cdev->work_flags)) {
> + clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
> return;
> }
>
> @@ -81,10 +82,9 @@ static void led_timer_function(unsigned long data)
> * Do it only if there is no pending blink brightness
> * change, to avoid overwriting the new value.
> */
> - if (!(led_cdev->flags & LED_BLINK_BRIGHTNESS_CHANGE))
> + if (!test_and_clear_bit(LED_BLINK_BRIGHTNESS_CHANGE,
> + &led_cdev->work_flags))
> led_cdev->blink_brightness = brightness;
> - else
> - led_cdev->flags &= ~LED_BLINK_BRIGHTNESS_CHANGE;
> brightness = LED_OFF;
> delay = led_cdev->blink_delay_off;
> }
> @@ -95,13 +95,15 @@ static void led_timer_function(unsigned long data)
> * the final blink state so that the led is toggled each delay_on +
> * delay_off milliseconds in worst case.
> */
> - if (led_cdev->flags & LED_BLINK_ONESHOT) {
> - if (led_cdev->flags & LED_BLINK_INVERT) {
> + if (test_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags)) {
> + if (test_bit(LED_BLINK_INVERT, &led_cdev->work_flags)) {
> if (brightness)
> - led_cdev->flags |= LED_BLINK_ONESHOT_STOP;
> + set_bit(LED_BLINK_ONESHOT_STOP,
> + &led_cdev->work_flags);
> } else {
> if (!brightness)
> - led_cdev->flags |= LED_BLINK_ONESHOT_STOP;
> + set_bit(LED_BLINK_ONESHOT_STOP,
> + &led_cdev->work_flags);
> }
> }
>
> @@ -114,10 +116,9 @@ static void set_brightness_delayed(struct work_struct *ws)
> container_of(ws, struct led_classdev, set_brightness_work);
> int ret = 0;
>
> - if (led_cdev->flags & LED_BLINK_DISABLE) {
> + if (test_and_clear_bit(LED_BLINK_DISABLE, &led_cdev->work_flags)) {
> led_cdev->delayed_set_value = LED_OFF;
> led_stop_software_blink(led_cdev);
> - led_cdev->flags &= ~LED_BLINK_DISABLE;
> }
>
> ret = __led_set_brightness(led_cdev, led_cdev->delayed_set_value);
> @@ -160,7 +161,7 @@ static void led_set_software_blink(struct led_classdev *led_cdev,
> return;
> }
>
> - led_cdev->flags |= LED_BLINK_SW;
> + set_bit(LED_BLINK_SW, &led_cdev->work_flags);
> mod_timer(&led_cdev->blink_timer, jiffies + 1);
> }
>
> @@ -169,7 +170,7 @@ static void led_blink_setup(struct led_classdev *led_cdev,
> unsigned long *delay_on,
> unsigned long *delay_off)
> {
> - if (!(led_cdev->flags & LED_BLINK_ONESHOT) &&
> + if (!test_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags) &&
> led_cdev->blink_set &&
> !led_cdev->blink_set(led_cdev, delay_on, delay_off))
> return;
> @@ -196,8 +197,8 @@ void led_blink_set(struct led_classdev *led_cdev,
> {
> del_timer_sync(&led_cdev->blink_timer);
>
> - led_cdev->flags &= ~LED_BLINK_ONESHOT;
> - led_cdev->flags &= ~LED_BLINK_ONESHOT_STOP;
> + clear_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags);
> + clear_bit(LED_BLINK_ONESHOT_STOP, &led_cdev->work_flags);
>
> led_blink_setup(led_cdev, delay_on, delay_off);
> }
> @@ -208,17 +209,17 @@ void led_blink_set_oneshot(struct led_classdev *led_cdev,
> unsigned long *delay_off,
> int invert)
> {
> - if ((led_cdev->flags & LED_BLINK_ONESHOT) &&
> + if (test_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags) &&
> timer_pending(&led_cdev->blink_timer))
> return;
>
> - led_cdev->flags |= LED_BLINK_ONESHOT;
> - led_cdev->flags &= ~LED_BLINK_ONESHOT_STOP;
> + set_bit(LED_BLINK_ONESHOT, &led_cdev->work_flags);
> + clear_bit(LED_BLINK_ONESHOT_STOP, &led_cdev->work_flags);
>
> if (invert)
> - led_cdev->flags |= LED_BLINK_INVERT;
> + set_bit(LED_BLINK_INVERT, &led_cdev->work_flags);
> else
> - led_cdev->flags &= ~LED_BLINK_INVERT;
> + clear_bit(LED_BLINK_INVERT, &led_cdev->work_flags);
>
> led_blink_setup(led_cdev, delay_on, delay_off);
> }
> @@ -229,7 +230,7 @@ void led_stop_software_blink(struct led_classdev *led_cdev)
> del_timer_sync(&led_cdev->blink_timer);
> led_cdev->blink_delay_on = 0;
> led_cdev->blink_delay_off = 0;
> - led_cdev->flags &= ~LED_BLINK_SW;
> + clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
> }
> EXPORT_SYMBOL_GPL(led_stop_software_blink);
>
> @@ -240,17 +241,18 @@ void led_set_brightness(struct led_classdev *led_cdev,
> * If software blink is active, delay brightness setting
> * until the next timer tick.
> */
> - if (led_cdev->flags & LED_BLINK_SW) {
> + if (test_bit(LED_BLINK_SW, &led_cdev->work_flags)) {
> /*
> * If we need to disable soft blinking delegate this to the
> * work queue task to avoid problems in case we are called
> * from hard irq context.
> */
> if (brightness == LED_OFF) {
> - led_cdev->flags |= LED_BLINK_DISABLE;
> + set_bit(LED_BLINK_DISABLE, &led_cdev->work_flags);
> schedule_work(&led_cdev->set_brightness_work);
> } else {
> - led_cdev->flags |= LED_BLINK_BRIGHTNESS_CHANGE;
> + set_bit(LED_BLINK_BRIGHTNESS_CHANGE,
> + &led_cdev->work_flags);
> led_cdev->blink_brightness = brightness;
> }
> return;
> diff --git a/include/linux/leds.h b/include/linux/leds.h
> index eebcd8c..1dc69df 100644
> --- a/include/linux/leds.h
> +++ b/include/linux/leds.h
> @@ -43,16 +43,20 @@ struct led_classdev {
> #define LED_UNREGISTERING (1 << 1)
> /* Upper 16 bits reflect control information */
> #define LED_CORE_SUSPENDRESUME (1 << 16)
> -#define LED_BLINK_SW (1 << 17)
> -#define LED_BLINK_ONESHOT (1 << 18)
> -#define LED_BLINK_ONESHOT_STOP (1 << 19)
> -#define LED_BLINK_INVERT (1 << 20)
> -#define LED_BLINK_BRIGHTNESS_CHANGE (1 << 21)
> -#define LED_BLINK_DISABLE (1 << 22)
> -#define LED_SYSFS_DISABLE (1 << 23)
> -#define LED_DEV_CAP_FLASH (1 << 24)
> -#define LED_HW_PLUGGABLE (1 << 25)
> -#define LED_PANIC_INDICATOR (1 << 26)
> +#define LED_SYSFS_DISABLE (1 << 17)
> +#define LED_DEV_CAP_FLASH (1 << 18)
> +#define LED_HW_PLUGGABLE (1 << 19)
> +#define LED_PANIC_INDICATOR (1 << 20)
> +
> + /* set_brightness_work / blink_timer flags, atomic, private. */
> + unsigned long work_flags;
> +
> +#define LED_BLINK_SW 0
> +#define LED_BLINK_ONESHOT 1
> +#define LED_BLINK_ONESHOT_STOP 2
> +#define LED_BLINK_INVERT 3
> +#define LED_BLINK_BRIGHTNESS_CHANGE 4
> +#define LED_BLINK_DISABLE 5
>
> /* Set LED brightness level
> * Must not sleep. Use brightness_set_blocking for drivers
>
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [Qemu-devel] virsh dump (qemu guest memory dump?): KASLR enabled linux guest support
From: Andrew Jones @ 2016-11-09 11:48 UTC (permalink / raw)
To: Daniel P. Berrange
Cc: Laszlo Ersek, Dave Young, qiaonuohan, bhe, anderson, qemu-devel
In-Reply-To: <20161109113735.GF22181@redhat.com>
On Wed, Nov 09, 2016 at 11:37:35AM +0000, Daniel P. Berrange wrote:
> On Wed, Nov 09, 2016 at 12:26:17PM +0100, Laszlo Ersek wrote:
> > On 11/09/16 11:40, Andrew Jones wrote:
> > > On Wed, Nov 09, 2016 at 11:01:46AM +0800, Dave Young wrote:
> > >> Hi,
> > >>
> > >> Latest linux kernel enabled kaslr to randomiz phys/virt memory
> > >> addresses, we had some effort to support kexec/kdump so that crash
> > >> utility can still works in case crashed kernel has kaslr enabled.
> > >>
> > >> But according to Dave Anderson virsh dump does not work, quoted messages
> > >> from Dave below:
> > >>
> > >> """
> > >> with virsh dump, there's no way of even knowing that KASLR
> > >> has randomized the kernel __START_KERNEL_map region, because there is no
> > >> virtual address information -- e.g., like "SYMBOL(_stext)" in the kdump
> > >> vmcoreinfo data to compare against the vmlinux file symbol value.
> > >> Unless virsh dump can export some basic virtual memory data, which
> > >> they say it can't, I don't see how KASLR can ever be supported.
> > >> """
> > >>
> > >> I assume virsh dump is using qemu guest memory dump facility so it
> > >> should be first addressed in qemu. Thus post this query to qemu devel
> > >> list. If this is not correct please let me know.
> > >>
> > >> Could you qemu dump people make it work? Or we can not support virt dump
> > >> as long as KASLR being enabled. Latest Fedora kernel has enabled it in x86_64.
> > >>
> > >
> > > When the -kernel command line option is used, then it may be possible
> > > to extract some information that could be used to supplement the memory
> > > dump that dump-guest-memory provides. However, that would be a specific
> > > use. In general, QEMU knows nothing about the guest kernel. It doesn't
> > > know where it is in the disk image, and it doesn't even know if it's
> > > Linux.
> > >
> > > Is there anything a guest userspace application could probe from e.g.
> > > /proc that would work? If so, then the guest agent could gain a new
> > > feature providing that.
> >
> > I fully agree. This is exactly what I suggested too, independently, in
> > the downstream thread, before arriving at this upstream thread. Let me
> > quote that email:
> >
> > On 11/09/16 12:09, Laszlo Ersek wrote:
> > > [...] the dump-guest-memory QEMU command supports an option called
> > > "paging". Here's its documentation, from the "qapi-schema.json" source
> > > file:
> > >
> > >> # @paging: if true, do paging to get guest's memory mapping. This allows
> > >> # using gdb to process the core file.
> > >> #
> > >> # IMPORTANT: this option can make QEMU allocate several gigabytes
> > >> # of RAM. This can happen for a large guest, or a
> > >> # malicious guest pretending to be large.
> > >> #
> > >> # Also, paging=true has the following limitations:
> > >> #
> > >> # 1. The guest may be in a catastrophic state or can have corrupted
> > >> # memory, which cannot be trusted
> > >> # 2. The guest can be in real-mode even if paging is enabled. For
> > >> # example, the guest uses ACPI to sleep, and ACPI sleep state
> > >> # goes in real-mode
> > >> # 3. Currently only supported on i386 and x86_64.
> > >> #
> > >
> > > "virsh dump --memory-only" sets paging=false, for obvious reasons.
> > >
> > > [...] the dump-guest-memory command provides a raw snapshot of the
> > > virtual machine's memory (and of the registers of the VCPUs); it is
> > > not enlightened about the guest.
> > >
> > > If the additional information you are looking for can be retrieved
> > > within the running Linux guest, using an appropriately privieleged
> > > userspace process, then I would recommend considering an extension to
> > > the qemu guest agent. The management layer (libvirt, [...]) could
> > > first invoke the guest agent (a process with root privileges running
> > > in the guest) from the host side, through virtio-serial. The new guest
> > > agent command would return the information necessary to deal with
> > > KASLR. Then the management layer would initiate the dump like always.
> > > Finally, the extra information would be combined with (or placed
> > > beside) the dump file in some way.
> > >
> > > So, this proposal would affect the guest agent and the management
> > > layer (= libvirt).
> >
> > Given that we already dislike "paging=true", enlightening
> > dump-guest-memory with even more guest-specific insight is the wrong
> > approach, IMO. That kind of knowledge belongs to the guest agent.
>
> If you're trying to debug a hung/panicked guest, then using a guest
> agent to fetch info is a complete non-starter as it'll be dead.
So don't wait. Management software can make this query immediately
after the guest agent goes live. The information needed won't change.
drew
^ permalink raw reply
* Re: [PATCH 2/2] led: core: Fix blink_brightness setting race
From: Jacek Anaszewski @ 2016-11-09 11:48 UTC (permalink / raw)
To: Hans de Goede, Richard Purdie; +Cc: linux-leds
In-Reply-To: <20161023194726.24388-2-hdegoede@redhat.com>
Hi Hans,
On 10/23/2016 09:47 PM, Hans de Goede wrote:
> All 3 of led_timer_func, led_set_brightness and led_set_software_blink
> set blink_brightness. If led_timer_func or led_set_software_blink race
> with led_set_brightness they may end up overwriting the new
> blink_brightness. The new atomic work_flags does not protect against
> this as it just protects the flags and not blink_brightness.
>
> This commit introduces a new new_blink_brightness value which gets
> set by led_set_brightness and read by led_timer_func on LED on, fixing
> this.
>
> Dealing with the new brightness at LED on time, makes the new
> brightness apply sooner, which also fixes a led_set_brightness which
> happens while a oneshot blink which ends in LED on is running not
> getting applied.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/leds/led-core.c | 14 +++++++-------
> include/linux/leds.h | 1 +
> 2 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
> index 17a0964..d474f97 100644
> --- a/drivers/leds/led-core.c
> +++ b/drivers/leds/led-core.c
> @@ -81,17 +81,17 @@ static void led_timer_function(unsigned long data)
> brightness = led_get_brightness(led_cdev);
> if (!brightness) {
> /* Time to switch the LED on. */
> - brightness = led_cdev->blink_brightness;
> + if (test_and_clear_bit(LED_BLINK_BRIGHTNESS_CHANGE,
> + &led_cdev->work_flags))
> + brightness = led_cdev->new_blink_brightness;
> + else
> + brightness = led_cdev->blink_brightness;
> delay = led_cdev->blink_delay_on;
> } else {
> /* Store the current brightness value to be able
> * to restore it when the delay_off period is over.
> - * Do it only if there is no pending blink brightness
> - * change, to avoid overwriting the new value.
> */
> - if (!test_and_clear_bit(LED_BLINK_BRIGHTNESS_CHANGE,
> - &led_cdev->work_flags))
> - led_cdev->blink_brightness = brightness;
> + led_cdev->blink_brightness = brightness;
> brightness = LED_OFF;
> delay = led_cdev->blink_delay_off;
> }
> @@ -260,7 +260,7 @@ void led_set_brightness(struct led_classdev *led_cdev,
> } else {
> set_bit(LED_BLINK_BRIGHTNESS_CHANGE,
> &led_cdev->work_flags);
> - led_cdev->blink_brightness = brightness;
> + led_cdev->new_blink_brightness = brightness;
> }
> return;
> }
> diff --git a/include/linux/leds.h b/include/linux/leds.h
> index cff9df7..6669404 100644
> --- a/include/linux/leds.h
> +++ b/include/linux/leds.h
> @@ -87,6 +87,7 @@ struct led_classdev {
> unsigned long blink_delay_on, blink_delay_off;
> struct timer_list blink_timer;
> int blink_brightness;
> + int new_blink_brightness;
> void (*flash_resume)(struct led_classdev *led_cdev);
>
> struct work_struct set_brightness_work;
>
Applied, thanks.
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH] x86/vm_event: Added support for VM_EVENT_REASON_INTERRUPT
From: Andrew Cooper @ 2016-11-09 11:49 UTC (permalink / raw)
To: Razvan Cojocaru, Jan Beulich
Cc: kevin.tian, sstabellini, suravee.suthikulpanit, xen-devel,
julien.grall, tamas, jun.nakajima, boris.ostrovsky
In-Reply-To: <f36b5905-f796-93f0-86ad-e73c5b3c2e26@bitdefender.com>
On 09/11/16 11:32, Razvan Cojocaru wrote:
> On 11/09/2016 01:17 PM, Jan Beulich wrote:
>>>>> On 09.11.16 at 10:42, <rcojocaru@bitdefender.com> wrote:
>>> Added support for a new event type, VM_EVENT_REASON_INTERRUPT,
>>> which is now fired in a one-shot manner when enabled via the new
>>> VM_EVENT_FLAG_GET_NEXT_INTERRUPT vm_event response flag.
>>> The patch also fixes the behaviour of the xc_hvm_inject_trap()
>>> hypercall, which would lead to non-architectural interrupts
>>> overwriting pending (specifically reinjected) architectural ones.
>> Looks quite okay, just some more or less mechanical comments.
>>
>>> --- a/xen/arch/x86/hvm/hvm.c
>>> +++ b/xen/arch/x86/hvm/hvm.c
>>> @@ -532,11 +532,23 @@ void hvm_do_resume(struct vcpu *v)
>>> }
>>> }
>>>
>>> - /* Inject pending hw/sw trap */
>>> - if ( v->arch.hvm_vcpu.inject_trap.vector != -1 )
>>> - {
>>> + /* Inject pending hw/sw trap if there are no other pending interrupts. */
>>> + if ( v->arch.hvm_vcpu.inject_trap.vector != -1 && !hvm_event_pending(v) )
>>> hvm_inject_trap(&v->arch.hvm_vcpu.inject_trap);
>>> - v->arch.hvm_vcpu.inject_trap.vector = -1;
>>> +
>>> + v->arch.hvm_vcpu.inject_trap.vector = -1;
>> I don't see why you pull this out of the if() body.
> That is intended, and covered by the "the patch also fixes the behaviour
> of the xc_hvm_inject_trap() hypercall, which would lead to
> non-architectural interrupts overwriting pending (specifically
> reinjected) architectural ones" part of the patch description.
>
> If we couldn't inject the trap because there was a pending event (i.e.
> the second if() condition, then not setting
> v->arch.hvm_vcpu.inject_trap.vector to -1 would lead to the trap being
> kept for injection at the first opportunity - and that could be when the
> context has changed and we shouldn't inject it anymore. So
> v->arch.hvm_vcpu.inject_trap.vector is therefore reset either way.
>
>>> + if ( unlikely(v->arch.vm_event) &&
>>> + v->arch.vm_event->monitor_next_interrupt )
>> Hard tab.
> I'll fix it.
>
>>> --- a/xen/arch/x86/hvm/monitor.c
>>> +++ b/xen/arch/x86/hvm/monitor.c
>>> @@ -150,6 +150,21 @@ int hvm_monitor_cpuid(unsigned long insn_length, unsigned int leaf,
>>> return monitor_traps(curr, 1, &req);
>>> }
>>>
>>> +void hvm_monitor_interrupt(unsigned int vector, unsigned int type,
>>> + unsigned int err, uint64_t cr2)
>>> +{
>>> + struct vcpu *curr = current;
>> Pointless local variable (used just once).
> I'll remove it.
>
>>> --- a/xen/arch/x86/hvm/svm/svm.c
>>> +++ b/xen/arch/x86/hvm/svm/svm.c
>>> @@ -2220,6 +2220,21 @@ static void svm_invlpg(struct vcpu *v, unsigned long vaddr)
>>> svm_asid_g_invlpg(v, vaddr);
>>> }
>>>
>>> +static bool svm_get_pending_event(struct vcpu *v, struct hvm_trap *info)
>>> +{
>>> + struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
>>> +
>>> + if ( vmcb->eventinj.fields.v )
>>> + return false;
>>> +
>>> + info->vector = vmcb->eventinj.fields.vector;
>>> + info->type = vmcb->eventinj.fields.type;
>>> + info->error_code = vmcb->eventinj.fields.errorcode;
>>> + info->cr2 = v->arch.hvm_vcpu.guest_cr[2];
>> I'd prefer for this last part to be put into generic code (i.e. the
>> wrapper).
> You mean setting CR2, which is common, right? I'll move it to the wrapper.
>
>>> --- a/xen/include/asm-arm/vm_event.h
>>> +++ b/xen/include/asm-arm/vm_event.h
>>> @@ -52,4 +52,10 @@ void vm_event_emulate_check(struct vcpu *v, vm_event_response_t *rsp)
>>> /* Not supported on ARM. */
>>> }
>>>
>>> +static inline
>>> +void vm_event_monitor_next_interrupt(struct vcpu *v)
>>> +{
>>> + /* Not supported on ARM. */
>>> +}
>> That's unfortunate. If it can't be implemented, shouldn't the caller at
>> least be advised of this being unavailable? Wasn't there even some
>> mechanism to report capabilities?
> Yes, I forgot to update the capabilities list. Good point, I'll see
> about that as well.
>
>>> --- a/xen/include/asm-x86/hvm/hvm.h
>>> +++ b/xen/include/asm-x86/hvm/hvm.h
>>> @@ -237,6 +237,8 @@ struct hvm_function_table {
>>> /* Architecture function to setup TSC scaling ratio */
>>> void (*setup)(struct vcpu *v);
>>> } tsc_scaling;
>>> +
>>> + bool (*get_pending_event)(struct vcpu *v, struct hvm_trap *info);
>>> };
>> Stylistically I think this would better go a little earlier.
> I'll move it after event_pending.
>
>>> --- a/xen/include/asm-x86/vm_event.h
>>> +++ b/xen/include/asm-x86/vm_event.h
>>> @@ -32,6 +32,7 @@ struct arch_vm_event {
>>> struct vm_event_emul_insn_data insn;
>>> } emul;
>>> struct monitor_write_data write_data;
>>> + bool monitor_next_interrupt;
>>> };
>> I think there's a 32-bit padding hole before write_data, so the new
>> field would better go earlier (perhaps even right after flags).
> I'll move it there.
>
>>> @@ -139,6 +144,8 @@
>>> * These kinds of events will be filtered out in future versions.
>>> */
>>> #define VM_EVENT_REASON_PRIVILEGED_CALL 11
>>> +/* Result of toolstack-requested (non-architectural) trap injection. */
>>> +#define VM_EVENT_REASON_INTERRUPT 12
>> Considering the event reports all kinds of interruptions, I don't think
>> the comment is appropriate.
> True, I'll update it.
>
>>> @@ -259,6 +266,13 @@ struct vm_event_cpuid {
>>> uint32_t _pad;
>>> };
>>>
>>> +struct vm_event_interrupt {
>>> + uint32_t vector;
>>> + uint32_t type;
>>> + uint32_t error_code;
>>> + uint64_t cr2;
>>> +};
>> This being x86-specific, I think it should be named or union-ized
>> accordingly.
> Right, I'll rename it.
You area also exposing X86_EVENTTYPE_* in the hypervisor ABI.
This is probably fine as it is an ABI inherited from VT-x/SVM (and by
some miracle, are actually compatible), but you do need to move the
constants into the public API as well.
~Andrew
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply
* [U-Boot] [PATCH v2 0/7] imx6: Add Engicam GEAM6UL/i.CoreM6 RQS board support
From: Jagan Teki @ 2016-11-09 11:49 UTC (permalink / raw)
To: u-boot
From: Jagan Teki <jagan@amarulasolutions.com>
Changes for v2:
- Add 'Acked-by' from Joe
- Add new i.CoreM6 RQS patches
Jagan Teki (7):
arm: dts: Add devicetree for i.MX6UL
arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support
dm: net: fec: Add .read_rom_hwaddr
net: fec: Zap local mac variable
arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial
support
arm: imx6q: Add Engicam i.CoreM6 Solo/Duallite RQS Starter Kit initial
support
imx6: icorem6: Rename engicam icorem6 defconfig files
arch/arm/cpu/armv7/mx6/Kconfig | 22 +
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/imx6dl-icore-rqs.dts | 50 ++
arch/arm/dts/imx6q-icore-rqs.dts | 50 ++
arch/arm/dts/imx6qdl-icore-rqs.dtsi | 101 +++
arch/arm/dts/imx6ul-geam-kit.dts | 119 +++
arch/arm/dts/imx6ul.dtsi | 942 +++++++++++++++++++++
board/engicam/geam6ul/Kconfig | 12 +
board/engicam/geam6ul/MAINTAINERS | 6 +
board/engicam/geam6ul/Makefile | 6 +
board/engicam/geam6ul/README | 28 +
board/engicam/geam6ul/geam6ul.c | 246 ++++++
board/engicam/icorem6/MAINTAINERS | 6 +-
board/engicam/icorem6/README | 19 +-
board/engicam/icorem6_rqs/Kconfig | 12 +
board/engicam/icorem6_rqs/MAINTAINERS | 7 +
board/engicam/icorem6_rqs/Makefile | 6 +
board/engicam/icorem6_rqs/README | 33 +
board/engicam/icorem6_rqs/icorem6_rqs.c | 402 +++++++++
...re_mmc_defconfig => imx6dl_icore_mmc_defconfig} | 0
..._nand_defconfig => imx6dl_icore_nand_defconfig} | 0
configs/imx6dl_icore_rqs_mmc_defconfig | 38 +
configs/imx6q_icore_mmc_defconfig | 46 +
configs/imx6q_icore_nand_defconfig | 41 +
configs/imx6q_icore_rqs_mmc_defconfig | 38 +
configs/imx6ul_geam_mmc_defconfig | 39 +
drivers/net/fec_mxc.c | 50 +-
include/configs/imx6qdl_icore_rqs.h | 124 +++
include/configs/imx6ul_geam.h | 125 +++
include/dt-bindings/clock/imx6ul-clock.h | 1 +
30 files changed, 2532 insertions(+), 42 deletions(-)
create mode 100644 arch/arm/dts/imx6dl-icore-rqs.dts
create mode 100644 arch/arm/dts/imx6q-icore-rqs.dts
create mode 100644 arch/arm/dts/imx6qdl-icore-rqs.dtsi
create mode 100644 arch/arm/dts/imx6ul-geam-kit.dts
create mode 100644 arch/arm/dts/imx6ul.dtsi
create mode 100644 board/engicam/geam6ul/Kconfig
create mode 100644 board/engicam/geam6ul/MAINTAINERS
create mode 100644 board/engicam/geam6ul/Makefile
create mode 100644 board/engicam/geam6ul/README
create mode 100644 board/engicam/geam6ul/geam6ul.c
create mode 100644 board/engicam/icorem6_rqs/Kconfig
create mode 100644 board/engicam/icorem6_rqs/MAINTAINERS
create mode 100644 board/engicam/icorem6_rqs/Makefile
create mode 100644 board/engicam/icorem6_rqs/README
create mode 100644 board/engicam/icorem6_rqs/icorem6_rqs.c
rename configs/{imx6qdl_icore_mmc_defconfig => imx6dl_icore_mmc_defconfig} (100%)
rename configs/{imx6qdl_icore_nand_defconfig => imx6dl_icore_nand_defconfig} (100%)
create mode 100644 configs/imx6dl_icore_rqs_mmc_defconfig
create mode 100644 configs/imx6q_icore_mmc_defconfig
create mode 100644 configs/imx6q_icore_nand_defconfig
create mode 100644 configs/imx6q_icore_rqs_mmc_defconfig
create mode 100644 configs/imx6ul_geam_mmc_defconfig
create mode 100644 include/configs/imx6qdl_icore_rqs.h
create mode 100644 include/configs/imx6ul_geam.h
--
1.9.1
^ permalink raw reply
* [U-Boot] [PATCH v2 1/7] arm: dts: Add devicetree for i.MX6UL
From: Jagan Teki @ 2016-11-09 11:49 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1478692203-4442-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Add i.MX6UL dtsi support from Linux.
Here is the last commit:
"ARM: dts: add gpio-ranges property to iMX GPIO controllers"
(sha1: bb728d662bed0fe91b152550e640cb3f6caa972c)
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/imx6ul.dtsi | 942 +++++++++++++++++++++++++++++++
include/dt-bindings/clock/imx6ul-clock.h | 1 +
2 files changed, 943 insertions(+)
create mode 100644 arch/arm/dts/imx6ul.dtsi
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
new file mode 100644
index 0000000..c5c05fd
--- /dev/null
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -0,0 +1,942 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx6ul-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx6ul-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ serial6 = &uart7;
+ serial7 = &uart8;
+ sai1 = &sai1;
+ sai2 = &sai2;
+ sai3 = &sai3;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
+ usbphy0 = &usbphy1;
+ usbphy1 = &usbphy2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ operating-points = <
+ /* kHz uV */
+ 528000 1175000
+ 396000 1025000
+ 198000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* KHz uV */
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+ clocks = <&clks IMX6UL_CLK_ARM>,
+ <&clks IMX6UL_CLK_PLL2_BUS>,
+ <&clks IMX6UL_CLK_PLL2_PFD2>,
+ <&clks IMX6UL_CA7_SECONDARY_SEL>,
+ <&clks IMX6UL_CLK_STEP>,
+ <&clks IMX6UL_CLK_PLL1_SW>,
+ <&clks IMX6UL_CLK_PLL1_SYS>,
+ <&clks IMX6UL_PLL1_BYPASS>,
+ <&clks IMX6UL_CLK_PLL1>,
+ <&clks IMX6UL_PLL1_BYPASS_SRC>,
+ <&clks IMX6UL_CLK_OSC>;
+ clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
+ "secondary_sel", "step", "pll1_sw",
+ "pll1_sys", "pll1_bypass", "pll1",
+ "pll1_bypass_src", "osc";
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+ };
+ };
+
+ intc: interrupt-controller at 00a01000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a02000 0x1000>,
+ <0x00a04000 0x2000>,
+ <0x00a06000 0x2000>;
+ };
+
+ ckil: clock-cli {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc: clock-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
+
+ ipp_di0: clock-di0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di0";
+ };
+
+ ipp_di1: clock-di1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di1";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gpc>;
+ ranges;
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ocram: sram at 00900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
+ };
+
+ dma_apbh: dma-apbh at 01804000 {
+ compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x01804000 0x2000>;
+ interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clks IMX6UL_CLK_APBHDMA>;
+ };
+
+ gpmi: gpmi-nand at 01806000 {
+ compatible = "fsl,imx6q-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clks IMX6UL_CLK_GPMI_IO>,
+ <&clks IMX6UL_CLK_GPMI_APB>,
+ <&clks IMX6UL_CLK_GPMI_BCH>,
+ <&clks IMX6UL_CLK_GPMI_BCH_APB>,
+ <&clks IMX6UL_CLK_PER_BCH>;
+ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ aips1: aips-bus at 02000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba-bus at 02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ ecspi1: ecspi at 02008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI1>,
+ <&clks IMX6UL_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi at 0200c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI2>,
+ <&clks IMX6UL_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi at 02010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI3>,
+ <&clks IMX6UL_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi4: ecspi at 02014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI4>,
+ <&clks IMX6UL_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart7: serial at 02018000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x02018000 0x4000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART7_IPG>,
+ <&clks IMX6UL_CLK_UART7_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial at 02020000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART1_IPG>,
+ <&clks IMX6UL_CLK_UART1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart8: serial at 02024000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x02024000 0x4000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART8_IPG>,
+ <&clks IMX6UL_CLK_UART8_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ sai1: sai at 02028000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+ reg = <0x02028000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
+ <&clks IMX6UL_CLK_SAI1>,
+ <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma 35 24 0>,
+ <&sdma 36 24 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai2: sai at 0202c000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+ reg = <0x0202c000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
+ <&clks IMX6UL_CLK_SAI2>,
+ <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma 37 24 0>,
+ <&sdma 38 24 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai3: sai at 02030000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+ reg = <0x02030000 0x4000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
+ <&clks IMX6UL_CLK_SAI3>,
+ <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma 39 24 0>,
+ <&sdma 40 24 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ };
+
+ tsc: tsc at 02040000 {
+ compatible = "fsl,imx6ul-tsc";
+ reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_IPG>,
+ <&clks IMX6UL_CLK_ADC2>;
+ clock-names = "tsc", "adc";
+ status = "disabled";
+ };
+
+ pwm1: pwm at 02080000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM1>,
+ <&clks IMX6UL_CLK_PWM1>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm at 02084000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM2>,
+ <&clks IMX6UL_CLK_PWM2>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm at 02088000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM3>,
+ <&clks IMX6UL_CLK_PWM3>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm at 0208c000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM4>,
+ <&clks IMX6UL_CLK_PWM4>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ can1: flexcan at 02090000 {
+ compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x02090000 0x4000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
+ <&clks IMX6UL_CLK_CAN1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can2: flexcan at 02094000 {
+ compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x02094000 0x4000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
+ <&clks IMX6UL_CLK_CAN2_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ gpt1: gpt at 02098000 {
+ compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
+ <&clks IMX6UL_CLK_GPT1_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ gpio1: gpio at 0209c000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
+ <&iomuxc 16 33 16>;
+ };
+
+ gpio2: gpio at 020a0000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
+ };
+
+ gpio3: gpio at 020a4000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 65 29>;
+ };
+
+ gpio4: gpio at 020a8000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
+ };
+
+ gpio5: gpio at 020ac000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
+ };
+
+ fec2: ethernet at 020b4000 {
+ compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
+ reg = <0x020b4000 0x4000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ENET>,
+ <&clks IMX6UL_CLK_ENET_AHB>,
+ <&clks IMX6UL_CLK_ENET_PTP>,
+ <&clks IMX6UL_CLK_ENET2_REF_125M>,
+ <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<1>;
+ fsl,num-rx-queues=<1>;
+ status = "disabled";
+ };
+
+ kpp: kpp at 020b8000 {
+ compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
+ reg = <0x020b8000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_KPP>;
+ status = "disabled";
+ };
+
+ wdog1: wdog at 020bc000 {
+ compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_WDOG1>;
+ };
+
+ wdog2: wdog at 020c0000 {
+ compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_WDOG2>;
+ status = "disabled";
+ };
+
+ clks: ccm at 020c4000 {
+ compatible = "fsl,imx6ul-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+ };
+
+ anatop: anatop at 020c8000 {
+ compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg_3p0: regulator-3p0 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <2625000>;
+ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
+ };
+
+ reg_arm: regulator-vddcore {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "cpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <0>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <24>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ reg_soc: regulator-vddsoc {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddsoc";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <18>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <28>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+ };
+
+ usbphy1: usbphy at 020c9000 {
+ compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBPHY1>;
+ phy-3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy at 020ca000 {
+ compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBPHY2>;
+ phy-3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ snvs: snvs at 020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_poweroff: snvs-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&snvs>;
+ offset = <0x38>;
+ mask = <0x60>;
+ status = "disabled";
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ epit1: epit at 020d0000 {
+ reg = <0x020d0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit at 020d4000 {
+ reg = <0x020d4000 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src at 020d8000 {
+ compatible = "fsl,imx6ul-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc at 020dc000 {
+ compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ };
+
+ iomuxc: iomuxc at 020e0000 {
+ compatible = "fsl,imx6ul-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr at 020e4000 {
+ compatible = "fsl,imx6ul-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ };
+
+ gpt2: gpt at 020e8000 {
+ compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
+ reg = <0x020e8000 0x4000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
+ <&clks IMX6UL_CLK_GPT2_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ sdma: sdma at 020ec000 {
+ compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
+ "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SDMA>,
+ <&clks IMX6UL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+
+ pwm5: pwm at 020f0000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f0000 0x4000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM5>,
+ <&clks IMX6UL_CLK_PWM5>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm at 020f4000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f4000 0x4000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM6>,
+ <&clks IMX6UL_CLK_PWM6>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm7: pwm at 020f8000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f8000 0x4000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM7>,
+ <&clks IMX6UL_CLK_PWM7>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm8: pwm at 020fc000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020fc000 0x4000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM8>,
+ <&clks IMX6UL_CLK_PWM8>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ aips2: aips-bus at 02100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ usbotg1: usb at 02184000 {
+ compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,anatop = <&anatop>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbotg2: usb at 02184200 {
+ compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc at 02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ };
+
+ fec1: ethernet at 02188000 {
+ compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
+ reg = <0x02188000 0x4000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ENET>,
+ <&clks IMX6UL_CLK_ENET_AHB>,
+ <&clks IMX6UL_CLK_ENET_PTP>,
+ <&clks IMX6UL_CLK_ENET_REF>,
+ <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<1>;
+ fsl,num-rx-queues=<1>;
+ status = "disabled";
+ };
+
+ usdhc1: usdhc at 02190000 {
+ compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02190000 0x4000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USDHC1>,
+ <&clks IMX6UL_CLK_USDHC1>,
+ <&clks IMX6UL_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc at 02194000 {
+ compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02194000 0x4000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USDHC2>,
+ <&clks IMX6UL_CLK_USDHC2>,
+ <&clks IMX6UL_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ adc1: adc at 02198000 {
+ compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ADC1>;
+ num-channels = <2>;
+ clock-names = "adc";
+ fsl,adck-max-frequency = <30000000>, <40000000>,
+ <20000000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ mmdc: mmdc at 021b0000 {
+ compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ lcdif: lcdif at 021c8000 {
+ compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
+ reg = <0x021c8000 0x4000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
+ <&clks IMX6UL_CLK_LCDIF_APB>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "pix", "axi", "disp_axi";
+ status = "disabled";
+ };
+
+ qspi: qspi at 021e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
+ reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_QSPI>,
+ <&clks IMX6UL_CLK_QSPI>;
+ clock-names = "qspi_en", "qspi";
+ status = "disabled";
+ };
+
+ uart2: serial at 021e8000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021e8000 0x4000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART2_IPG>,
+ <&clks IMX6UL_CLK_UART2_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial at 021ec000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021ec000 0x4000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART3_IPG>,
+ <&clks IMX6UL_CLK_UART3_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart4: serial at 021f0000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021f0000 0x4000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART4_IPG>,
+ <&clks IMX6UL_CLK_UART4_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart5: serial at 021f4000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021f4000 0x4000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART5_IPG>,
+ <&clks IMX6UL_CLK_UART5_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c4: i2c at 021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021f8000 0x4000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C4>;
+ status = "disabled";
+ };
+
+ uart6: serial at 021fc000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021fc000 0x4000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART6_IPG>,
+ <&clks IMX6UL_CLK_UART6_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index 18de070..4623f17 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -234,6 +234,7 @@
#define IMX6UL_CLK_CSI_SEL 221
#define IMX6UL_CLK_CSI_PODF 222
#define IMX6UL_CLK_PLL3_120M 223
+#define IMX6UL_CLK_KPP 224
/* For i.MX6ULL */
#define IMX6UL_CLK_ESAI_SEL 224
#define IMX6UL_CLK_ESAI_PRED 225
--
1.9.1
^ permalink raw reply related
* [U-Boot] [PATCH v2 2/7] arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support
From: Jagan Teki @ 2016-11-09 11:49 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1478692203-4442-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Boot Log:
--------
U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30)
Trying to boot from MMC1
U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530)
CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 43C
Reset cause: POR
Model: Engicam GEAM6UL
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
geam6ul>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/cpu/armv7/mx6/Kconfig | 11 ++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imx6ul-geam-kit.dts | 119 ++++++++++++++++++
board/engicam/geam6ul/Kconfig | 12 ++
board/engicam/geam6ul/MAINTAINERS | 6 +
board/engicam/geam6ul/Makefile | 6 +
board/engicam/geam6ul/README | 28 +++++
board/engicam/geam6ul/geam6ul.c | 246 ++++++++++++++++++++++++++++++++++++++
configs/imx6ul_geam_mmc_defconfig | 39 ++++++
include/configs/imx6ul_geam.h | 125 +++++++++++++++++++
10 files changed, 594 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx6ul-geam-kit.dts
create mode 100644 board/engicam/geam6ul/Kconfig
create mode 100644 board/engicam/geam6ul/MAINTAINERS
create mode 100644 board/engicam/geam6ul/Makefile
create mode 100644 board/engicam/geam6ul/README
create mode 100644 board/engicam/geam6ul/geam6ul.c
create mode 100644 configs/imx6ul_geam_mmc_defconfig
create mode 100644 include/configs/imx6ul_geam.h
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index c04536c..2cc4893 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -149,6 +149,16 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
+config TARGET_MX6UL_GEAM
+ bool "Support Engicam GEAM6UL"
+ select MX6UL
+ select OF_CONTROL
+ select DM
+ select DM_GPIO
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
select MX6ULL
@@ -237,6 +247,7 @@ source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
+source "board/engicam/geam6ul/Kconfig"
source "board/engicam/icorem6/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 836a8c4..d79b2e2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -284,7 +284,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6dl-icore.dtb \
- imx6q-icore.dtb
+ imx6q-icore.dtb \
+ imx6ul-geam-kit.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb
diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam-kit.dts
new file mode 100644
index 0000000..a039b6d
--- /dev/null
+++ b/arch/arm/dts/imx6ul-geam-kit.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6ul.dtsi"
+
+/ {
+ model = "Engicam GEAM6UL";
+ compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
+
+ memory {
+ reg = <0x80000000 0x08000000>;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <4>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ >;
+ };
+};
diff --git a/board/engicam/geam6ul/Kconfig b/board/engicam/geam6ul/Kconfig
new file mode 100644
index 0000000..8753d15
--- /dev/null
+++ b/board/engicam/geam6ul/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6UL_GEAM
+
+config SYS_BOARD
+ default "geam6ul"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "imx6ul_geam"
+
+endif
diff --git a/board/engicam/geam6ul/MAINTAINERS b/board/engicam/geam6ul/MAINTAINERS
new file mode 100644
index 0000000..6691450
--- /dev/null
+++ b/board/engicam/geam6ul/MAINTAINERS
@@ -0,0 +1,6 @@
+GEAM6UL BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: board/engicam/geam6ul
+F: include/configs/imx6ul_geam.h
+F: configs/imx6ul_geam_mmc_defconfig
diff --git a/board/engicam/geam6ul/Makefile b/board/engicam/geam6ul/Makefile
new file mode 100644
index 0000000..0e367e2
--- /dev/null
+++ b/board/engicam/geam6ul/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := geam6ul.o
diff --git a/board/engicam/geam6ul/README b/board/engicam/geam6ul/README
new file mode 100644
index 0000000..0df6ae4
--- /dev/null
+++ b/board/engicam/geam6ul/README
@@ -0,0 +1,28 @@
+How to use U-Boot on Engicam GEAM6UL Starter Kit:
+-------------------------------------------------
+
+- Configure U-Boot for Engicam GEAM6UL:
+
+$ make mrproper
+$ make imx6ul_geam_mmc_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c
new file mode 100644
index 0000000..94910d6
--- /dev/null
+++ b/board/engicam/geam6ul/geam6ul.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* VSELECT */
+ MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* CD */
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RST_B */
+ MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ default:
+ printf("Warning - USDHC%d controller not supporting\n",
+ i + 1);
+ return 0;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000008,
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00070007,
+ .p0_mpdgctrl0 = 0x41490145,
+ .p0_mprddlctl = 0x40404546,
+ .p0_mpwrdlctl = 0x4040524D,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
new file mode 100644
index 0000000..24f3fd6
--- /dev/null
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6UL_GEAM=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
+CONFIG_SYS_PROMPT="geam6ul> "
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_IMLS is not set
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h
new file mode 100644
index 0000000..8b2db68
--- /dev/null
+++ b/include/configs/imx6ul_geam.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam GEAM6UL Starter Kits.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX6UL_GEAM_CONFIG_H
+#define __IMX6UL_GEAM_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+# define CONFIG_ENV_OFFSET 0x100000
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE UART1_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV 0
+# define CONFIG_SYS_FSL_USDHC_NUM 1
+# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# define CONFIG_SPL_MMC_SUPPORT
+
+# include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+# undef CONFIG_DM_GPIO
+# undef CONFIG_DM_MMC
+# endif
+#endif
+
+#endif /* __IMX6UL_GEAM_CONFIG_H */
--
1.9.1
^ permalink raw reply related
* [U-Boot] [PATCH v2 3/7] dm: net: fec: Add .read_rom_hwaddr
From: Jagan Teki @ 2016-11-09 11:49 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1478692203-4442-1-git-send-email-jagan@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Add .read_rom_hwaddr on dm eth_ops.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/net/fec_mxc.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 367bc40..09433df 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -348,12 +348,6 @@ static void fec_rbd_clean(int last, struct fec_bd *prbd)
writew(0, &prbd->data_length);
}
-static int fec_get_hwaddr(int dev_id, unsigned char *mac)
-{
- imx_get_mac_from_fuse(dev_id, mac);
- return !is_valid_ethaddr(mac);
-}
-
static int _fec_set_hwaddr(struct fec_priv *fec, uchar *mac)
{
writel(0, &fec->eth->iaddr1);
@@ -975,6 +969,12 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
return _fec_init(fec, mac);
}
+static int fec_get_hwaddr(int dev_id, unsigned char *mac)
+{
+ imx_get_mac_from_fuse(dev_id, mac);
+ return !is_valid_ethaddr(mac);
+}
+
#ifdef CONFIG_PHYLIB
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, struct phy_device *phydev)
@@ -1128,6 +1128,16 @@ int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
#else
+static int fec_read_rom_mac(struct udevice *dev)
+{
+ struct fec_priv *fec = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ imx_get_mac_from_fuse(fec->dev_id, pdata->enetaddr);
+
+ return 0;
+}
+
static int fec_set_hwaddr(struct udevice *dev)
{
struct fec_priv *fec = dev_get_priv(dev);
@@ -1175,6 +1185,7 @@ static const struct eth_ops fecmxc_ops = {
.recv = fec_recv,
.stop = fec_halt,
.write_hwaddr = fec_set_hwaddr,
+ .read_rom_hwaddr = fec_read_rom_mac,
};
static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
@@ -1204,7 +1215,6 @@ static int fecmxc_probe(struct udevice *dev)
struct fec_priv *priv = dev_get_priv(dev);
struct mii_dev *bus = NULL;
int dev_id = -1;
- unsigned char ethaddr[6];
uint32_t start;
int ret;
@@ -1238,14 +1248,6 @@ static int fecmxc_probe(struct udevice *dev)
fec_reg_setup(priv);
priv->dev_id = (dev_id == -1) ? 0 : dev_id;
- ret = fec_get_hwaddr(dev_id, ethaddr);
- if (!ret) {
- debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
- memcpy(pdata->enetaddr, ethaddr, 6);
- if (!getenv("ethaddr"))
- eth_setenv_enetaddr("ethaddr", ethaddr);
- }
-
return 0;
err_timeout:
--
1.9.1
^ permalink raw reply related
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