* [PATCH v2 09/10] ARM: rockchip: enable support for RK1108 SoC
From: Andy Yan @ 2016-11-14 12:15 UTC (permalink / raw)
To: heiko; +Cc: linux-rockchip, linux, linux-kernel, Andy Yan
In-Reply-To: <1479124550-24037-1-git-send-email-andy.yan@rock-chips.com>
Add a rockchip,rk1108 compatible.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
Changes in v2: None
arch/arm/mach-rockchip/rockchip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index a7ab9ec..e7fdf06 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -76,6 +76,7 @@ static void __init rockchip_dt_init(void)
}
static const char * const rockchip_board_dt_compat[] = {
+ "rockchip,rk1108",
"rockchip,rk2928",
"rockchip,rk3066a",
"rockchip,rk3066b",
--
2.7.4
^ permalink raw reply related
* [PATCH v2 08/10] ARM: dts: add basic support for Rockchip RK1108 SOC
From: Andy Yan @ 2016-11-14 12:14 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, devicetree, mark.rutland, robh+dt, linux,
linux-kernel, Andy Yan
In-Reply-To: <1479124550-24037-1-git-send-email-andy.yan@rock-chips.com>
RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
It is designed for varies application scenario such as car DVR, sports
DV, secure camera and UAV camera.
This patch add basic support for it with DMAC / UART / CRU / pinctrl / MMC
enabled.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Jacob Chen <jacob2.chen@rock-chips.com>
---
Changes in v2:
- fix timer and gic dt description
- ordering devices by register address
arch/arm/boot/dts/rk1108.dtsi | 428 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 428 insertions(+)
create mode 100644 arch/arm/boot/dts/rk1108.dtsi
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
new file mode 100644
index 0000000..636c294
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -0,0 +1,428 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/rk1108-cru.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rk1108";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ bus_intmem@10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x2000>;
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma@102a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x102a0000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ uart2: serial@10210000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10210000 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "disabled";
+ };
+
+ uart1: serial@10220000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10220000 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ status = "disabled";
+ };
+
+ uart0: serial@10230000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10230000 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "disabled";
+ };
+
+ grf: syscon@10300000 {
+ compatible = "rockchip,rk1108-grf", "syscon";
+ reg = <0x10300000 0x1000>;
+ };
+
+ pmugrf: syscon@20060000 {
+ compatible = "rockchip,rk1108-pmugrf", "syscon";
+ reg = <0x20060000 0x1000>;
+ };
+
+ cru: clock-controller@20200000 {
+ compatible = "rockchip,rk1108-cru";
+ reg = <0x20200000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ emmc: dwmmc@30110000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30110000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@30120000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30120000 0x4000>;
+ status = "disabled";
+ };
+
+ sdmmc: dwmmc@30130000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 100000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30130000 0x4000>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@32010000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x32011000 0x1000>,
+ <0x32012000 0x1000>,
+ <0x32014000 0x2000>,
+ <0x32016000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk1108-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@20030000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20030000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@10310000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10310000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@10320000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10320000 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@10330000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10330000 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_input_high: pcfg-input-high {
+ bias-pull-up;
+ input-enable;
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ i2c2m1 {
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ i2c2m1_gpio: i2c2m1-gpio {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c2m05v {
+ i2c2m05v_xfer: i2c2m05v-xfer {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ i2c2m05v_gpio: i2c2m05v-gpio {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
+ <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts_gpio: uart0-rts-gpio {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m0 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m1 {
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
+ <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2_5v {
+ uart2_5v_cts: uart2_5v-cts {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart2_5v_rts: uart2_5v-rts {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 08/10] ARM: dts: add basic support for Rockchip RK1108 SOC
From: Andy Yan @ 2016-11-14 12:14 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andy Yan
In-Reply-To: <1479124550-24037-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
It is designed for varies application scenario such as car DVR, sports
DV, secure camera and UAV camera.
This patch add basic support for it with DMAC / UART / CRU / pinctrl / MMC
enabled.
Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Tested-by: Jacob Chen <jacob2.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v2:
- fix timer and gic dt description
- ordering devices by register address
arch/arm/boot/dts/rk1108.dtsi | 428 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 428 insertions(+)
create mode 100644 arch/arm/boot/dts/rk1108.dtsi
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
new file mode 100644
index 0000000..636c294
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -0,0 +1,428 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/rk1108-cru.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rk1108";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ bus_intmem@10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x2000>;
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma@102a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x102a0000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ uart2: serial@10210000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10210000 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "disabled";
+ };
+
+ uart1: serial@10220000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10220000 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ status = "disabled";
+ };
+
+ uart0: serial@10230000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10230000 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "disabled";
+ };
+
+ grf: syscon@10300000 {
+ compatible = "rockchip,rk1108-grf", "syscon";
+ reg = <0x10300000 0x1000>;
+ };
+
+ pmugrf: syscon@20060000 {
+ compatible = "rockchip,rk1108-pmugrf", "syscon";
+ reg = <0x20060000 0x1000>;
+ };
+
+ cru: clock-controller@20200000 {
+ compatible = "rockchip,rk1108-cru";
+ reg = <0x20200000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ emmc: dwmmc@30110000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30110000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@30120000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30120000 0x4000>;
+ status = "disabled";
+ };
+
+ sdmmc: dwmmc@30130000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 100000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30130000 0x4000>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@32010000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x32011000 0x1000>,
+ <0x32012000 0x1000>,
+ <0x32014000 0x2000>,
+ <0x32016000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk1108-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@20030000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20030000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@10310000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10310000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@10320000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10320000 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@10330000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10330000 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_input_high: pcfg-input-high {
+ bias-pull-up;
+ input-enable;
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ i2c2m1 {
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ i2c2m1_gpio: i2c2m1-gpio {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c2m05v {
+ i2c2m05v_xfer: i2c2m05v-xfer {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ i2c2m05v_gpio: i2c2m05v-gpio {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
+ <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts_gpio: uart0-rts-gpio {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m0 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m1 {
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
+ <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2_5v {
+ uart2_5v_cts: uart2_5v-cts {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart2_5v_rts: uart2_5v-rts {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+ };
+};
--
2.7.4
--
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^ permalink raw reply related
* Re: Debugging Ethernet issues
From: Mason @ 2016-11-14 12:13 UTC (permalink / raw)
To: Andrew Lunn
Cc: netdev, Florian Fainelli, Mans Rullgard, Sergei Shtylyov,
Tom Lendacky, Zach Brown, Shaohui Xie, Tim Beale, Brian Hill,
Vince Bridgers, Balakumaran Kannan, David S. Miller,
Sebastian Frias, Kirill Kapranov
In-Reply-To: <20161113030919.GA2892@lunn.ch>
On 13/11/2016 04:09, Andrew Lunn wrote:
> Mason wrote:
>
>> When connected to a Gigabit switch
>> 3.4 negotiates a LAN DHCP setup instantly
>> 4.7 requires over 5 seconds to do so
>
> When you run tcpdump on the DHCP server, are you noticing the first
> request is missing?
>
> What can happen is the dhclient gets started immediately and sends out
> its first request before auto-negotiation has finished. So this first packet
> gets lost. The retransmit after a few seconds is then successful.
This is what happens on 3.4
# time udhcpc | while read LINE; do date; echo $LINE; done
Mon Nov 14 11:57:12 UTC 2016
udhcpc (v1.22.1) started
Mon Nov 14 11:57:12 UTC 2016
Sending discover...
[ 50.150000] tangox-enet.0: link up (1000 Mbps - Full Duplex)
Mon Nov 14 11:57:15 UTC 2016
Sending discover...
Mon Nov 14 11:57:16 UTC 2016
Sending select for 172.27.64.58...
Mon Nov 14 11:57:17 UTC 2016
Lease of 172.27.64.58 obtained, lease time 604800
Mon Nov 14 11:57:17 UTC 2016
deleting routers
Mon Nov 14 11:57:17 UTC 2016
adding dns 172.27.0.17
real 0m4.704s
user 0m0.030s
sys 0m0.550s
The corresponding log on the DHCP server was
# tcpdump -n -i eth1-boards ether host 00:16:e8:4b:b0:7d
tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
listening on eth1-boards, link-type EN10MB (Ethernet), capture size 262144 bytes
11:57:16.095474 IP 0.0.0.0.68 > 255.255.255.255.67: BOOTP/DHCP, Request from 00:16:e8:4b:b0:7d, length 300
11:57:16.095638 IP 172.27.64.1 > 172.27.64.58: ICMP echo request, id 29883, seq 0, length 28
11:57:17.096740 IP 172.27.200.1.67 > 172.27.64.58.68: BOOTP/DHCP, Reply, length 391
11:57:17.097182 IP 0.0.0.0.68 > 255.255.255.255.67: BOOTP/DHCP, Request from 00:16:e8:4b:b0:7d, length 300
11:57:17.202842 IP 172.27.200.1.67 > 172.27.64.58.68: BOOTP/DHCP, Reply, length 391
11:57:21.101946 ARP, Request who-has 172.27.64.58 tell 172.27.64.1, length 28
11:57:21.102182 ARP, Reply 172.27.64.58 is-at 00:16:e8:4b:b0:7d, length 46
This is a different log which I got earlier, but can no longer reproduce:
# tcpdump -n -i eth1-boards ether host 00:16:e8:4b:b0:7d
tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
listening on eth1-boards, link-type EN10MB (Ethernet), capture size 262144 bytes
11:08:09.610662 IP 0.0.0.0.68 > 255.255.255.255.67: BOOTP/DHCP, Request from 00:16:e8:4b:b0:7d, length 300
11:08:10.642852 IP 172.27.200.1.67 > 172.27.64.58.68: BOOTP/DHCP, Reply, length 391
11:08:10.643276 IP 0.0.0.0.68 > 255.255.255.255.67: BOOTP/DHCP, Request from 00:16:e8:4b:b0:7d, length 300
11:08:10.790526 IP 172.27.200.1.67 > 172.27.64.58.68: BOOTP/DHCP, Reply, length 391
11:08:11.638146 ARP, Reply 172.27.64.58 is-at 00:16:e8:4b:b0:7d, length 46
11:08:11.638156 IP 172.27.64.1 > 172.27.64.58: ICMP echo request, id 29883, seq 0, length 28
11:08:11.638345 IP 172.27.64.58 > 172.27.64.1: ICMP echo reply, id 29883, seq 0, length 28
11:08:16.642811 ARP, Request who-has 172.27.64.1 tell 172.27.64.58, length 46
11:08:16.642822 ARP, Reply 172.27.64.1 is-at 00:15:17:24:e0:81, length 28
This is what happens on v4.7
# time udhcpc | while read LINE; do date; echo $LINE; done
Mon Nov 14 11:51:25 UTC 2016
udhcpc (v1.22.1) started
Mon Nov 14 11:51:25 UTC 2016
Sending discover...
Mon Nov 14 11:51:28 UTC 2016
Sending discover...
[ 342.658572] nb8800 26000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
Mon Nov 14 11:51:32 UTC 2016
Sending discover...
Mon Nov 14 11:51:33 UTC 2016
Sending select for 172.27.64.58...
Mon Nov 14 11:51:33 UTC 2016
Lease of 172.27.64.58 obtained, lease time 604800
Mon Nov 14 11:51:33 UTC 2016
deleting routers
Mon Nov 14 11:51:33 UTC 2016
adding dns 172.27.0.17
real 0m7.348s
user 0m0.053s
sys 0m0.077s
The corresponding log on the DHCP server was
# tcpdump -n -i eth1-boards ether host 00:16:e8:4b:b0:7d
tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
listening on eth1-boards, link-type EN10MB (Ethernet), capture size 262144 bytes
11:51:31.957245 IP 0.0.0.0.68 > 255.255.255.255.67: BOOTP/DHCP, Request from 00:16:e8:4b:b0:7d, length 300
11:51:31.957409 IP 172.27.64.1 > 172.27.64.58: ICMP echo request, id 29883, seq 0, length 28
11:51:32.958514 IP 172.27.200.1.67 > 172.27.64.58.68: BOOTP/DHCP, Reply, length 391
11:51:32.970538 IP 0.0.0.0.68 > 255.255.255.255.67: BOOTP/DHCP, Request from 00:16:e8:4b:b0:7d, length 300
11:51:33.038205 IP 172.27.200.1.67 > 172.27.64.58.68: BOOTP/DHCP, Reply, length 391
11:51:36.957949 ARP, Request who-has 172.27.64.58 tell 172.27.64.1, length 28
11:51:36.958112 ARP, Reply 172.27.64.58 is-at 00:16:e8:4b:b0:7d, length 46
For reference, here are the ethtool statistics on 4.7 after the DHCP setup:
# ethtool -S eth0
NIC statistics:
rx_bytes_ok: 1747
rx_frames_ok: 9
rx_undersize_frames: 0
rx_fragment_frames: 0
rx_64_byte_frames: 3
rx_127_byte_frames: 2
rx_255_byte_frames: 1
rx_511_byte_frames: 3
rx_1023_byte_frames: 0
rx_max_size_frames: 0
rx_oversize_frames: 0
rx_bad_fcs_frames: 0
rx_broadcast_frames: 4
rx_multicast_frames: 1
rx_control_frames: 0
rx_pause_frames: 0
rx_unsup_control_frames: 0
rx_align_error_frames: 0
rx_overrun_frames: 0
rx_jabber_frames: 0
rx_bytes: 1747
rx_frames: 9
tx_bytes_ok: 756
tx_frames_ok: 3
tx_64_byte_frames: 1
tx_127_byte_frames: 0
tx_255_byte_frames: 0
tx_511_byte_frames: 2
tx_1023_byte_frames: 0
tx_max_size_frames: 0
tx_oversize_frames: 0
tx_broadcast_frames: 2
tx_multicast_frames: 0
tx_control_frames: 0
tx_pause_frames: 0
tx_underrun_frames: 0
tx_single_collision_frames: 0
tx_multi_collision_frames: 0
tx_deferred_collision_frames: 0
tx_late_collision_frames: 0
tx_excessive_collision_frames: 0
tx_bytes: 756
tx_frames: 3
tx_collisions: 0
Regards.
^ permalink raw reply
* [Patch v7 6/7] irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
In-Reply-To: <20161114121351.10924-1-Zubair.Kakakhel@imgtec.com>
The powerpc dts file does not have the xlnx,kind-of-intr property.
Instead of erroring out, give a warning instead. And attempt to
continue to probe the interrupt controller while assuming
kind-of-intr is 0x0 as a fall back.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
---
V6 -> V7
Rebase to v4.9-rc5
V5 -> V6
Rebase to v4.9-rc3
V5 new patch
---
drivers/irqchip/irq-xilinx-intc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c
index 971c141..d330917 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -179,8 +179,8 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
if (ret < 0) {
- pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
- goto err_alloc;
+ pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
+ irqc->intr_mask = 0;
}
if (irqc->intr_mask >> nr_irq)
--
2.10.2
^ permalink raw reply related
* [Buildroot] [PATCH next] cmake: bump version to 3.7.0
From: Vicente Olivert Riera @ 2016-11-14 12:14 UTC (permalink / raw)
To: buildroot
libuv is now a required dependency.
Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
package/cmake/Config.in | 11 ++++++++---
package/cmake/cmake.hash | 4 ++--
package/cmake/cmake.mk | 6 +++---
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/package/cmake/Config.in b/package/cmake/Config.in
index 6f04a4a..b554d7c 100644
--- a/package/cmake/Config.in
+++ b/package/cmake/Config.in
@@ -20,11 +20,14 @@ config BR2_PACKAGE_CMAKE_CTEST
select BR2_PACKAGE_EXPAT
select BR2_PACKAGE_BZIP2
select BR2_PACKAGE_XZ
+ select BR2_PACKAGE_LIBUV
depends on BR2_PACKAGE_CMAKE_ARCH_SUPPORTS
depends on BR2_TOOLCHAIN_GCC_AT_LEAST_4_7 # from jsoncpp
depends on BR2_USE_WCHAR # libarchive
depends on BR2_INSTALL_LIBSTDCPP
- depends on !BR2_STATIC_LIBS
+ depends on !BR2_STATIC_LIBS #libuv
+ depends on BR2_TOOLCHAIN_HAS_THREADS # libuv
+ depends on BR2_USE_MMU # libuv
help
CTest is a testing tool distributed as a part of CMake. It
can be used to automate updating (using CVS for example),
@@ -34,7 +37,9 @@ config BR2_PACKAGE_CMAKE_CTEST
http://www.cmake.org/
-comment "ctest needs a toolchain w/ C++, wchar, dynamic library, gcc >= 4.7"
+comment "ctest needs a toolchain w/ C++, wchar, dynamic library, gcc >= 4.7, threads"
depends on BR2_PACKAGE_CMAKE_ARCH_SUPPORTS
+ depends on BR2_USE_MMU
depends on !BR2_INSTALL_LIBSTDCPP || !BR2_USE_WCHAR || \
- BR2_STATIC_LIBS || !BR2_TOOLCHAIN_GCC_AT_LEAST_4_7
+ BR2_STATIC_LIBS || !BR2_TOOLCHAIN_GCC_AT_LEAST_4_7 || \
+ !BR2_TOOLCHAIN_HAS_THREADS
diff --git a/package/cmake/cmake.hash b/package/cmake/cmake.hash
index f846dc9..687e5a4 100644
--- a/package/cmake/cmake.hash
+++ b/package/cmake/cmake.hash
@@ -1,2 +1,2 @@
-# From http://www.cmake.org/files/v3.6/cmake-3.6.3-SHA-256.txt
-sha256 7d73ee4fae572eb2d7cd3feb48971aea903bb30a20ea5ae8b4da826d8ccad5fe cmake-3.6.3.tar.gz
+# From http://www.cmake.org/files/v3.7/cmake-3.7.0-SHA-256.txt
+sha256 ed63e05c41aeb6c036e503114ab15847f29c312f9f21f5f1a7060a4b4ec2fb31 cmake-3.7.0.tar.gz
diff --git a/package/cmake/cmake.mk b/package/cmake/cmake.mk
index fadb09e..522d7fe 100644
--- a/package/cmake/cmake.mk
+++ b/package/cmake/cmake.mk
@@ -4,8 +4,8 @@
#
################################################################################
-CMAKE_VERSION_MAJOR = 3.6
-CMAKE_VERSION = $(CMAKE_VERSION_MAJOR).3
+CMAKE_VERSION_MAJOR = 3.7
+CMAKE_VERSION = $(CMAKE_VERSION_MAJOR).0
CMAKE_SITE = https://cmake.org/files/v$(CMAKE_VERSION_MAJOR)
CMAKE_LICENSE = BSD-3c
CMAKE_LICENSE_FILES = Copyright.txt
@@ -22,7 +22,7 @@ CMAKE_LICENSE_FILES = Copyright.txt
# the system-wide libraries instead of rebuilding and statically
# linking with the ones bundled into the CMake sources.
-CMAKE_DEPENDENCIES = zlib jsoncpp libcurl libarchive expat bzip2 xz
+CMAKE_DEPENDENCIES = zlib jsoncpp libcurl libarchive expat bzip2 xz libuv
CMAKE_CONF_OPTS = \
-DKWSYS_LFS_WORKS=TRUE \
--
2.10.1
^ permalink raw reply related
* [Patch v7 7/7] powerpc/virtex: Use generic xilinx irqchip driver
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
In-Reply-To: <20161114121351.10924-1-Zubair.Kakakhel@imgtec.com>
The Xilinx interrupt controller driver is now available in drivers/irqchip.
Switch to using that driver.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
---
V6 - V7
Rebase to v4.9-rc5
V5 -> V6 Added Acked-by Micheal Ellerman
V5 New patch
Tested on virtex440-ml507 using qemu
---
arch/powerpc/include/asm/xilinx_intc.h | 2 +-
arch/powerpc/platforms/40x/Kconfig | 1 +
arch/powerpc/platforms/40x/virtex.c | 2 +-
arch/powerpc/platforms/44x/Kconfig | 1 +
arch/powerpc/platforms/44x/virtex.c | 2 +-
arch/powerpc/sysdev/xilinx_intc.c | 211 +--------------------------------
drivers/irqchip/irq-xilinx-intc.c | 3 +-
7 files changed, 9 insertions(+), 213 deletions(-)
diff --git a/arch/powerpc/include/asm/xilinx_intc.h b/arch/powerpc/include/asm/xilinx_intc.h
index 343612f..3192d7f 100644
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -14,7 +14,7 @@
#ifdef __KERNEL__
extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xilinx_intc_get_irq(void);
+extern unsigned int xintc_get_irq(void);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index e3257f2..1d7c1b1 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -64,6 +64,7 @@ config XILINX_VIRTEX_GENERIC_BOARD
default n
select XILINX_VIRTEX_II_PRO
select XILINX_VIRTEX_4_FX
+ select XILINX_INTC
help
This option enables generic support for Xilinx Virtex based boards.
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c
index 91a08ea..e3d5e09 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -48,7 +48,7 @@ define_machine(virtex) {
.probe = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ = xilinx_intc_init_tree,
- .get_irq = xilinx_intc_get_irq,
+ .get_irq = xintc_get_irq,
.restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 48fc180..25b8d64 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -241,6 +241,7 @@ config XILINX_VIRTEX440_GENERIC_BOARD
depends on 44x
default n
select XILINX_VIRTEX_5_FXT
+ select XILINX_INTC
help
This option enables generic support for Xilinx Virtex based boards
that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c
index a7e0802..3eb13ed 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -54,7 +54,7 @@ define_machine(virtex) {
.probe = virtex_probe,
.setup_arch = xilinx_pci_init,
.init_IRQ = xilinx_intc_init_tree,
- .get_irq = xilinx_intc_get_irq,
+ .get_irq = xintc_get_irq,
.calibrate_decr = generic_calibrate_decr,
.restart = ppc4xx_reset_system,
};
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index 0f52d79..4a86dcf 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -29,194 +29,7 @@
#include <asm/processor.h>
#include <asm/i8259.h>
#include <asm/irq.h>
-
-/*
- * INTC Registers
- */
-#define XINTC_ISR 0 /* Interrupt Status */
-#define XINTC_IPR 4 /* Interrupt Pending */
-#define XINTC_IER 8 /* Interrupt Enable */
-#define XINTC_IAR 12 /* Interrupt Acknowledge */
-#define XINTC_SIE 16 /* Set Interrupt Enable bits */
-#define XINTC_CIE 20 /* Clear Interrupt Enable bits */
-#define XINTC_IVR 24 /* Interrupt Vector */
-#define XINTC_MER 28 /* Master Enable */
-
-static struct irq_domain *master_irqhost;
-
-#define XILINX_INTC_MAXIRQS (32)
-
-/* The following table allows the interrupt type, edge or level,
- * to be cached after being read from the device tree until the interrupt
- * is mapped
- */
-static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
-
-/* Map the interrupt type from the device tree to the interrupt types
- * used by the interrupt subsystem
- */
-static unsigned char xilinx_intc_map_senses[] = {
- IRQ_TYPE_EDGE_RISING,
- IRQ_TYPE_EDGE_FALLING,
- IRQ_TYPE_LEVEL_HIGH,
- IRQ_TYPE_LEVEL_LOW,
-};
-
-/*
- * The interrupt controller is setup such that it doesn't work well with
- * the level interrupt handler in the kernel because the handler acks the
- * interrupt before calling the application interrupt handler. To deal with
- * that, we use 2 different irq chips so that different functions can be
- * used for level and edge type interrupts.
- *
- * IRQ Chip common (across level and edge) operations
- */
-static void xilinx_intc_mask(struct irq_data *d)
-{
- int irq = irqd_to_hwirq(d);
- void * regs = irq_data_get_irq_chip_data(d);
- pr_debug("mask: %d\n", irq);
- out_be32(regs + XINTC_CIE, 1 << irq);
-}
-
-static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type)
-{
- return 0;
-}
-
-/*
- * IRQ Chip level operations
- */
-static void xilinx_intc_level_unmask(struct irq_data *d)
-{
- int irq = irqd_to_hwirq(d);
- void * regs = irq_data_get_irq_chip_data(d);
- pr_debug("unmask: %d\n", irq);
- out_be32(regs + XINTC_SIE, 1 << irq);
-
- /* ack level irqs because they can't be acked during
- * ack function since the handle_level_irq function
- * acks the irq before calling the inerrupt handler
- */
- out_be32(regs + XINTC_IAR, 1 << irq);
-}
-
-static struct irq_chip xilinx_intc_level_irqchip = {
- .name = "Xilinx Level INTC",
- .irq_mask = xilinx_intc_mask,
- .irq_mask_ack = xilinx_intc_mask,
- .irq_unmask = xilinx_intc_level_unmask,
- .irq_set_type = xilinx_intc_set_type,
-};
-
-/*
- * IRQ Chip edge operations
- */
-static void xilinx_intc_edge_unmask(struct irq_data *d)
-{
- int irq = irqd_to_hwirq(d);
- void *regs = irq_data_get_irq_chip_data(d);
- pr_debug("unmask: %d\n", irq);
- out_be32(regs + XINTC_SIE, 1 << irq);
-}
-
-static void xilinx_intc_edge_ack(struct irq_data *d)
-{
- int irq = irqd_to_hwirq(d);
- void * regs = irq_data_get_irq_chip_data(d);
- pr_debug("ack: %d\n", irq);
- out_be32(regs + XINTC_IAR, 1 << irq);
-}
-
-static struct irq_chip xilinx_intc_edge_irqchip = {
- .name = "Xilinx Edge INTC",
- .irq_mask = xilinx_intc_mask,
- .irq_unmask = xilinx_intc_edge_unmask,
- .irq_ack = xilinx_intc_edge_ack,
- .irq_set_type = xilinx_intc_set_type,
-};
-
-/*
- * IRQ Host operations
- */
-
-/**
- * xilinx_intc_xlate - translate virq# from device tree interrupts property
- */
-static int xilinx_intc_xlate(struct irq_domain *h, struct device_node *ct,
- const u32 *intspec, unsigned int intsize,
- irq_hw_number_t *out_hwirq,
- unsigned int *out_flags)
-{
- if ((intsize < 2) || (intspec[0] >= XILINX_INTC_MAXIRQS))
- return -EINVAL;
-
- /* keep a copy of the interrupt type til the interrupt is mapped
- */
- xilinx_intc_typetable[intspec[0]] = xilinx_intc_map_senses[intspec[1]];
-
- /* Xilinx uses 2 interrupt entries, the 1st being the h/w
- * interrupt number, the 2nd being the interrupt type, edge or level
- */
- *out_hwirq = intspec[0];
- *out_flags = xilinx_intc_map_senses[intspec[1]];
-
- return 0;
-}
-static int xilinx_intc_map(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t irq)
-{
- irq_set_chip_data(virq, h->host_data);
-
- if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
- xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
- irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip,
- handle_level_irq);
- } else {
- irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
- handle_edge_irq);
- }
- return 0;
-}
-
-static const struct irq_domain_ops xilinx_intc_ops = {
- .map = xilinx_intc_map,
- .xlate = xilinx_intc_xlate,
-};
-
-struct irq_domain * __init
-xilinx_intc_init(struct device_node *np)
-{
- struct irq_domain * irq;
- void * regs;
-
- /* Find and map the intc registers */
- regs = of_iomap(np, 0);
- if (!regs) {
- pr_err("xilinx_intc: could not map registers\n");
- return NULL;
- }
-
- /* Setup interrupt controller */
- out_be32(regs + XINTC_IER, 0); /* disable all irqs */
- out_be32(regs + XINTC_IAR, ~(u32) 0); /* Acknowledge pending irqs */
- out_be32(regs + XINTC_MER, 0x3UL); /* Turn on the Master Enable. */
-
- /* Allocate and initialize an irq_domain structure. */
- irq = irq_domain_add_linear(np, XILINX_INTC_MAXIRQS, &xilinx_intc_ops,
- regs);
- if (!irq)
- panic(__FILE__ ": Cannot allocate IRQ host\n");
-
- return irq;
-}
-
-int xilinx_intc_get_irq(void)
-{
- void * regs = master_irqhost->host_data;
- pr_debug("get_irq:\n");
- return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR));
-}
+#include <linux/irqchip.h>
#if defined(CONFIG_PPC_I8259)
/*
@@ -265,31 +78,11 @@ static void __init xilinx_i8259_setup_cascade(void)
static inline void xilinx_i8259_setup_cascade(void) { return; }
#endif /* defined(CONFIG_PPC_I8259) */
-static const struct of_device_id xilinx_intc_match[] __initconst = {
- { .compatible = "xlnx,opb-intc-1.00.c", },
- { .compatible = "xlnx,xps-intc-1.00.a", },
- {}
-};
-
/*
* Initialize master Xilinx interrupt controller
*/
void __init xilinx_intc_init_tree(void)
{
- struct device_node *np;
-
- /* find top level interrupt controller */
- for_each_matching_node(np, xilinx_intc_match) {
- if (!of_get_property(np, "interrupts", NULL))
- break;
- }
- BUG_ON(!np);
-
- master_irqhost = xilinx_intc_init(np);
- BUG_ON(!master_irqhost);
-
- irq_set_default_host(master_irqhost);
- of_node_put(np);
-
+ irqchip_init();
xilinx_i8259_setup_cascade();
}
diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c
index d330917..3db7ab1 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -237,4 +237,5 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
}
-IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
+IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
+IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
--
2.10.2
^ permalink raw reply related
* [Patch v7 6/7] irqchip: xilinx: Try to fall back if xlnx, kind-of-intr not provided
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
In-Reply-To: <20161114121351.10924-1-Zubair.Kakakhel@imgtec.com>
The powerpc dts file does not have the xlnx,kind-of-intr property.
Instead of erroring out, give a warning instead. And attempt to
continue to probe the interrupt controller while assuming
kind-of-intr is 0x0 as a fall back.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
---
V6 -> V7
Rebase to v4.9-rc5
V5 -> V6
Rebase to v4.9-rc3
V5 new patch
---
drivers/irqchip/irq-xilinx-intc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c
index 971c141..d330917 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -179,8 +179,8 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
if (ret < 0) {
- pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
- goto err_alloc;
+ pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
+ irqc->intr_mask = 0;
}
if (irqc->intr_mask >> nr_irq)
--
2.10.2
^ permalink raw reply related
* [Patch v7 5/7] irqchip: xilinx: Add support for parent intc
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
In-Reply-To: <20161114121351.10924-1-Zubair.Kakakhel@imgtec.com>
The MIPS based xilfpga platform has the following IRQ structure
Peripherals --> xilinx_intcontroller -> mips_cpu_int controller
Add support for the driver to chain the irq handler
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
---
V6 -> V7
Rebase to v4.9-rc5
V5 -> V6
Use chained_irq_enter and chained_irq_exit
Add error check for irq_of_parse_and_map
Rebase to v4.9-rc3
V4 -> V5
Rebased to v4.9-rc1
Missing curly braces
V3 -> V4
Clean up if/else when a parent is found
Pass irqchip structure to handler as data
V2 -> V3
Reused existing parent node instead of finding again.
Cleanup up handler based on review
V1 -> V2
No change
---
drivers/irqchip/irq-xilinx-intc.c | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c
index 34ec609..971c141 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -12,10 +12,12 @@
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/jump_label.h>
#include <linux/bug.h>
+#include <linux/of_irq.h>
/* No one else should require these constants, so define them locally here. */
#define ISR 0x00 /* Interrupt Status Register */
@@ -133,11 +135,26 @@ static const struct irq_domain_ops xintc_irq_domain_ops = {
.map = xintc_map,
};
+static void xil_intc_irq_handler(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 pending;
+
+ chained_irq_enter(chip, desc);
+ do {
+ pending = xintc_get_irq();
+ if (pending == -1U)
+ break;
+ generic_handle_irq(pending);
+ } while (true);
+ chained_irq_exit(chip, desc);
+}
+
static int __init xilinx_intc_of_init(struct device_node *intc,
struct device_node *parent)
{
u32 nr_irq;
- int ret;
+ int ret, irq;
struct xintc_irq_chip *irqc;
if (xintc_irqc) {
@@ -196,7 +213,20 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
goto err_alloc;
}
- irq_set_default_host(irqc->root_domain);
+ if (parent) {
+ irq = irq_of_parse_and_map(intc, 0);
+ if (irq) {
+ irq_set_chained_handler_and_data(irq,
+ xil_intc_irq_handler,
+ irqc);
+ } else {
+ pr_err("irq-xilinx: interrupts property not in DT\n");
+ ret = -EINVAL;
+ goto err_alloc;
+ }
+ } else {
+ irq_set_default_host(irqc->root_domain);
+ }
return 0;
--
2.10.2
^ permalink raw reply related
* [Patch v7 3/7] irqchip: xilinx: restructure and use jump label api
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
In-Reply-To: <20161114121351.10924-1-Zubair.Kakakhel@imgtec.com>
Add a global structure to house various variables.
And cleanup read/write handling by using jump label api.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
---
V6 -> V7
Restructure and use jump label api
Better commit log
V5 -> V6
Removed __func__ from printk
Rebase to v4.9-rc3
V4 -> V5
Rebased to v4.9-rc1
Better error handling
V3 -> V4
Better error handling for kzalloc
Erroring out if the axi intc is probed twice as that isn't
supported
V2 -> V3
New patch. Cleans up driver structure
---
drivers/irqchip/irq-xilinx-intc.c | 118 +++++++++++++++++++++-----------------
1 file changed, 66 insertions(+), 52 deletions(-)
diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c
index 096c1ed..7331d8c 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -14,10 +14,9 @@
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/io.h>
+#include <linux/jump_label.h>
#include <linux/bug.h>
-static void __iomem *intc_baseaddr;
-
/* No one else should require these constants, so define them locally here. */
#define ISR 0x00 /* Interrupt Status Register */
#define IPR 0x04 /* Interrupt Pending Register */
@@ -31,27 +30,30 @@ static void __iomem *intc_baseaddr;
#define MER_ME (1<<0)
#define MER_HIE (1<<1)
-static unsigned int (*read_fn)(void __iomem *);
-static void (*write_fn)(u32, void __iomem *);
+static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
-static void intc_write32(u32 val, void __iomem *addr)
-{
- iowrite32(val, addr);
-}
+struct xintc_irq_chip {
+ void __iomem *base;
+ struct irq_domain *root_domain;
+ u32 intr_mask;
+};
-static unsigned int intc_read32(void __iomem *addr)
-{
- return ioread32(addr);
-}
+static struct xintc_irq_chip *xintc_irqc;
-static void intc_write32_be(u32 val, void __iomem *addr)
+static void xintc_write(int reg, u32 data)
{
- iowrite32be(val, addr);
+ if (static_branch_unlikely(&xintc_is_be))
+ iowrite32be(data, xintc_irqc->base + reg);
+ else
+ iowrite32(data, xintc_irqc->base + reg);
}
-static unsigned int intc_read32_be(void __iomem *addr)
+static unsigned int xintc_read(int reg)
{
- return ioread32be(addr);
+ if (static_branch_unlikely(&xintc_is_be))
+ return ioread32be(xintc_irqc->base + reg);
+ else
+ return ioread32(xintc_irqc->base + reg);
}
static void intc_enable_or_unmask(struct irq_data *d)
@@ -65,21 +67,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
* acks the irq before calling the interrupt handler
*/
if (irqd_is_level_type(d))
- write_fn(mask, intc_baseaddr + IAR);
+ xintc_write(IAR, mask);
- write_fn(mask, intc_baseaddr + SIE);
+ xintc_write(SIE, mask);
}
static void intc_disable_or_mask(struct irq_data *d)
{
pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
- write_fn(1 << d->hwirq, intc_baseaddr + CIE);
+ xintc_write(CIE, 1 << d->hwirq);
}
static void intc_ack(struct irq_data *d)
{
pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
- write_fn(1 << d->hwirq, intc_baseaddr + IAR);
+ xintc_write(IAR, 1 << d->hwirq);
}
static void intc_mask_ack(struct irq_data *d)
@@ -87,8 +89,8 @@ static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq;
pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
- write_fn(mask, intc_baseaddr + CIE);
- write_fn(mask, intc_baseaddr + IAR);
+ xintc_write(CIE, mask);
+ xintc_write(IAR, mask);
}
static struct irq_chip intc_dev = {
@@ -99,15 +101,13 @@ static struct irq_chip intc_dev = {
.irq_mask_ack = intc_mask_ack,
};
-static struct irq_domain *root_domain;
-
unsigned int get_irq(void)
{
unsigned int hwirq, irq = -1;
- hwirq = read_fn(intc_baseaddr + IVR);
+ hwirq = xintc_read(IVR);
if (hwirq != -1U)
- irq = irq_find_mapping(root_domain, hwirq);
+ irq = irq_find_mapping(xintc_irqc->root_domain, hwirq);
pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
@@ -116,9 +116,7 @@ unsigned int get_irq(void)
static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
- u32 intr_mask = (u32)d->host_data;
-
- if (intr_mask & (1 << hw)) {
+ if (xintc_irqc->intr_mask & (1 << hw)) {
irq_set_chip_and_handler_name(irq, &intc_dev,
handle_edge_irq, "edge");
irq_clear_status_flags(irq, IRQ_LEVEL);
@@ -138,59 +136,75 @@ static const struct irq_domain_ops xintc_irq_domain_ops = {
static int __init xilinx_intc_of_init(struct device_node *intc,
struct device_node *parent)
{
- u32 nr_irq, intr_mask;
+ u32 nr_irq;
int ret;
+ struct xintc_irq_chip *irqc;
- intc_baseaddr = of_iomap(intc, 0);
- BUG_ON(!intc_baseaddr);
+ if (xintc_irqc) {
+ pr_err("irq-xilinx: Multiple instances aren't supported\n");
+ return -EINVAL;
+ }
+
+ irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
+ if (!irqc)
+ return -ENOMEM;
+
+ xintc_irqc = irqc;
+
+ irqc->base = of_iomap(intc, 0);
+ BUG_ON(!irqc->base);
ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
if (ret < 0) {
pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
- return ret;
+ goto err_alloc;
}
- ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask);
+ ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
if (ret < 0) {
pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
- return ret;
+ goto err_alloc;
}
- if (intr_mask >> nr_irq)
+ if (irqc->intr_mask >> nr_irq)
pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
pr_info("irq-xilinx: %s: num_irq=%d, edge=0x%x\n",
- intc->full_name, nr_irq, intr_mask);
+ intc->full_name, nr_irq, irqc->intr_mask);
- write_fn = intc_write32;
- read_fn = intc_read32;
/*
* Disable all external interrupts until they are
* explicity requested.
*/
- write_fn(0, intc_baseaddr + IER);
+ xintc_write(IER, 0);
/* Acknowledge any pending interrupts just in case. */
- write_fn(0xffffffff, intc_baseaddr + IAR);
+ xintc_write(IAR, 0xffffffff);
/* Turn on the Master Enable. */
- write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
- if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
- write_fn = intc_write32_be;
- read_fn = intc_read32_be;
- write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
+ xintc_write(MER, MER_HIE | MER_ME);
+ if (!(xintc_read(MER) & (MER_HIE | MER_ME))) {
+ static_branch_enable(&xintc_is_be);
+ xintc_write(MER, MER_HIE | MER_ME);
}
- /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
- * lazy and Michal can clean it up to something nicer when he tests
- * and commits this patch. ~~gcl */
- root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops,
- (void *)intr_mask);
+ irqc->root_domain = irq_domain_add_linear(intc, nr_irq,
+ &xintc_irq_domain_ops, irqc);
+ if (!irqc->root_domain) {
+ pr_err("irq-xilinx: Unable to create IRQ domain\n");
+ goto err_alloc;
+ }
- irq_set_default_host(root_domain);
+ irq_set_default_host(irqc->root_domain);
return 0;
+
+err_alloc:
+ xintc_irqc = NULL;
+ kfree(irqc);
+ return ret;
+
}
IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
--
2.10.2
^ permalink raw reply related
* [Patch v7 4/7] irqchip: xilinx: Rename get_irq to xintc_get_irq
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
In-Reply-To: <20161114121351.10924-1-Zubair.Kakakhel@imgtec.com>
Now that the driver is generic and used by multiple archs,
get_irq is too generic.
Rename get_irq to xintc_get_irq to avoid any conflicts
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
---
V6 -> V7
Rebase to v4.9-rc5
V5 -> V6
Removed __func__ in printk
Rebase to v4.9-rc3
V4 -> V5
Rebased to v4.9-rc1
Use __func__ in pr_err
V3 -> V4
New patch.
---
arch/microblaze/include/asm/irq.h | 2 +-
arch/microblaze/kernel/irq.c | 4 ++--
drivers/irqchip/irq-xilinx-intc.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/microblaze/include/asm/irq.h b/arch/microblaze/include/asm/irq.h
index bab3b13..d785def 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -16,6 +16,6 @@ struct pt_regs;
extern void do_IRQ(struct pt_regs *regs);
/* should be defined in each interrupt controller driver */
-extern unsigned int get_irq(void);
+extern unsigned int xintc_get_irq(void);
#endif /* _ASM_MICROBLAZE_IRQ_H */
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 11e24de..903dad8 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -29,12 +29,12 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
trace_hardirqs_off();
irq_enter();
- irq = get_irq();
+ irq = xintc_get_irq();
next_irq:
BUG_ON(!irq);
generic_handle_irq(irq);
- irq = get_irq();
+ irq = xintc_get_irq();
if (irq != -1U) {
pr_debug("next irq: %d\n", irq);
++concurrent_irq;
diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c
index 7331d8c..34ec609 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -101,7 +101,7 @@ static struct irq_chip intc_dev = {
.irq_mask_ack = intc_mask_ack,
};
-unsigned int get_irq(void)
+unsigned int xintc_get_irq(void)
{
unsigned int hwirq, irq = -1;
--
2.10.2
^ permalink raw reply related
* [Patch v7 2/7] irqchip: xilinx: clean up print messages
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
In-Reply-To: <20161114121351.10924-1-Zubair.Kakakhel@imgtec.com>
Remove __func__ and prefix irq-xilinx in various debug prints
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
---
V6 -> V7
New patch
This diff was squashed into another patch. Split it up for cleanliness
---
drivers/irqchip/irq-xilinx-intc.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c
index 90bec7d..096c1ed 100644
--- a/drivers/irqchip/irq-xilinx-intc.c
+++ b/drivers/irqchip/irq-xilinx-intc.c
@@ -58,7 +58,7 @@ static void intc_enable_or_unmask(struct irq_data *d)
{
unsigned long mask = 1 << d->hwirq;
- pr_debug("enable_or_unmask: %ld\n", d->hwirq);
+ pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
/* ack level irqs because they can't be acked during
* ack function since the handle_level_irq function
@@ -72,13 +72,13 @@ static void intc_enable_or_unmask(struct irq_data *d)
static void intc_disable_or_mask(struct irq_data *d)
{
- pr_debug("disable: %ld\n", d->hwirq);
+ pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
write_fn(1 << d->hwirq, intc_baseaddr + CIE);
}
static void intc_ack(struct irq_data *d)
{
- pr_debug("ack: %ld\n", d->hwirq);
+ pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
write_fn(1 << d->hwirq, intc_baseaddr + IAR);
}
@@ -86,7 +86,7 @@ static void intc_mask_ack(struct irq_data *d)
{
unsigned long mask = 1 << d->hwirq;
- pr_debug("disable_and_ack: %ld\n", d->hwirq);
+ pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
write_fn(mask, intc_baseaddr + CIE);
write_fn(mask, intc_baseaddr + IAR);
}
@@ -109,7 +109,7 @@ unsigned int get_irq(void)
if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq);
- pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
+ pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
return irq;
}
@@ -146,20 +146,20 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
if (ret < 0) {
- pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__);
+ pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
return ret;
}
ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask);
if (ret < 0) {
- pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__);
+ pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
return ret;
}
if (intr_mask >> nr_irq)
- pr_warn("%s: mismatch in kind-of-intr param\n", __func__);
+ pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
- pr_info("%s: num_irq=%d, edge=0x%x\n",
+ pr_info("irq-xilinx: %s: num_irq=%d, edge=0x%x\n",
intc->full_name, nr_irq, intr_mask);
write_fn = intc_write32;
--
2.10.2
^ permalink raw reply related
* [Patch v7 1/7] microblaze: irqchip: Move intc driver to irqchip
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
In-Reply-To: <20161114121351.10924-1-Zubair.Kakakhel@imgtec.com>
The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform and a few PowerPC based platforms.
Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
---
V6 -> V7
Rebase to v4.9-rc5
V5 -> V6
Rebase to v4.9-rc3
V4 -> V5
Rebase to v4.9-rc1
Renamed back to irq-xilinx-intc.c
V3 -> V4
No change
V2 -> V3
No change here. Cleanup patches follow after this patch.
Its debatable to cleanup before/after move. Decided to place cleanup
after move to put history in new place.
V1 -> V2
Renamed irq-xilinx to irq-axi-intc
Renamed CONFIG_XILINX_INTC to CONFIG_XILINX_AXI_INTC
Patch is now without rename flag so as to facilitate review
---
arch/microblaze/Kconfig | 1 +
arch/microblaze/kernel/Makefile | 2 +-
drivers/irqchip/Kconfig | 4 ++++
drivers/irqchip/Makefile | 1 +
arch/microblaze/kernel/intc.c => drivers/irqchip/irq-xilinx-intc.c | 0
5 files changed, 7 insertions(+), 1 deletion(-)
rename arch/microblaze/kernel/intc.c => drivers/irqchip/irq-xilinx-intc.c (100%)
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 86f6572..85885a5 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -27,6 +27,7 @@ config MICROBLAZE
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
select IRQ_DOMAIN
+ select XILINX_INTC
select MODULES_USE_ELF_RELA
select OF
select OF_EARLY_FLATTREE
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index f08baca..e098381 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -15,7 +15,7 @@ endif
extra-y := head.o vmlinux.lds
obj-y += dma.o exceptions.o \
- hw_exception_handler.o intc.o irq.o \
+ hw_exception_handler.o irq.o \
platform.o process.o prom.o ptrace.o \
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bc0af33..ae96731 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -211,6 +211,10 @@ config XTENSA_MX
bool
select IRQ_DOMAIN
+config XILINX_INTC
+ bool
+ select IRQ_DOMAIN
+
config IRQ_CROSSBAR
bool
help
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e4dbfc8..0e55d94 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
obj-$(CONFIG_TS4800_IRQ) += irq-ts4800.o
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
+obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
diff --git a/arch/microblaze/kernel/intc.c b/drivers/irqchip/irq-xilinx-intc.c
similarity index 100%
rename from arch/microblaze/kernel/intc.c
rename to drivers/irqchip/irq-xilinx-intc.c
--
2.10.2
^ permalink raw reply related
* [Patch v7 0/7] microblaze/PowerPC: Move irq-xilinx to irqchip
From: Zubair Lutfullah Kakakhel @ 2016-11-14 12:13 UTC (permalink / raw)
To: monstr, tglx, jason, marc.zyngier
Cc: linux-kernel, michal.simek, linuxppc-dev, mpe, Zubair.Kakakhel
Hi,
This patch series moves the Xilinx interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then removes another implementation of the driver in arch/powerpc.
This effort results in one common driver usable by mips,microblaze
and powerpc.
Compile tested on microblaze-el.
Tested using qemu-system-ppc using virtix440-ml507
Tested on MIPSfpga platform.
Based on v4.9-rc5
Thanks,
ZubairLK
V6 -> V7
Rebase to v4.5-rc5
Split print messages cleanup into a separate patch
Use jump label api to restructure read/write handling in driver.
V5 -> V6
Split patch series. Patches for arch/mips can go separately
Rebase to v4.9-rc3
Added chained_irq_enter/exit
Removed __func__ used in pr_err
V4 -> V5
Added a new patch that removes the PPC driver
Rebase to v4.9-rc1
Better error handling
V3 -> V4
Better error handling
Some minor fixups
V2 -> V3
Cleanup the interrupt controller driver a bit based on feedback
Rebase to v4.8-rc4
V1 -> V2
Resubmitting without truncating the diff output for file moves
Removed accidental local mac address entry
Individual logs have more detail
Zubair Lutfullah Kakakhel (7):
microblaze: irqchip: Move intc driver to irqchip
irqchip: xilinx: clean up print messages
irqchip: xilinx: restructure and use jump label api
irqchip: xilinx: Rename get_irq to xintc_get_irq
irqchip: xilinx: Add support for parent intc
irqchip: xilinx: Try to fall back if xlnx,kind-of-intr not provided
powerpc/virtex: Use generic xilinx irqchip driver
arch/microblaze/Kconfig | 1 +
arch/microblaze/include/asm/irq.h | 2 +-
arch/microblaze/kernel/Makefile | 2 +-
arch/microblaze/kernel/intc.c | 196 ---------------------------
arch/microblaze/kernel/irq.c | 4 +-
arch/powerpc/include/asm/xilinx_intc.h | 2 +-
arch/powerpc/platforms/40x/Kconfig | 1 +
arch/powerpc/platforms/40x/virtex.c | 2 +-
arch/powerpc/platforms/44x/Kconfig | 1 +
arch/powerpc/platforms/44x/virtex.c | 2 +-
arch/powerpc/sysdev/xilinx_intc.c | 211 +----------------------------
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-xilinx-intc.c | 241 +++++++++++++++++++++++++++++++++
14 files changed, 258 insertions(+), 412 deletions(-)
delete mode 100644 arch/microblaze/kernel/intc.c
create mode 100644 drivers/irqchip/irq-xilinx-intc.c
--
2.10.2
^ permalink raw reply
* Re: [PATCH v2 0/5] Make btrfs-progs really compatible with any kernel version
From: David Sterba @ 2016-11-14 12:13 UTC (permalink / raw)
To: Anand Jain; +Cc: linux-btrfs
In-Reply-To: <824aa945-fd1f-45a2-9123-2bd810f464d6@oracle.com>
On Tue, Nov 08, 2016 at 09:14:39PM +0800, Anand Jain wrote:
> This patch isn't integrated, any idea why ?
Because it does not cover all usecases. I've committed the preparatory
bits from branch where I've been working on that feature so we can
actually get to the hard parts.
^ permalink raw reply
* [LTP] [PATCH v4 5/5] flistxattr and listxattr: added tests
From: Dejan Jovicevic @ 2016-11-14 12:13 UTC (permalink / raw)
To: ltp
In-Reply-To: <1479125614-24731-1-git-send-email-dejan.jovicevic@rt-rk.com>
Tests for these two system calls were not present.
flistxattr(), listxattr() and llistxattr() are identical,
the only difference is in the first argument:
- in listxattr() it refers to the file in the path.
- in llistxattr() in the case of a symbolic link, the list
of names of extended attributes associated with the link
itself is retrieved, not the file that it refers to.
- in flistxattr() the open file referred to by fd is
interrogated in place of path.
Because of these similarities, implemented tests for flistxattr()
and listxattr() are based on the existing tests for llistxattr(),
with some adjustments to fit the appropriate system call.
Signed-off-by: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
---
runtest/syscalls | 8 ++
testcases/kernel/syscalls/.gitignore | 6 ++
testcases/kernel/syscalls/flistxattr/Makefile | 23 +++++
.../kernel/syscalls/flistxattr/flistxattr01.c | 104 ++++++++++++++++++++
.../kernel/syscalls/flistxattr/flistxattr02.c | 104 ++++++++++++++++++++
.../kernel/syscalls/flistxattr/flistxattr03.c | 99 +++++++++++++++++++
testcases/kernel/syscalls/listxattr/Makefile | 23 +++++
testcases/kernel/syscalls/listxattr/listxattr01.c | 96 ++++++++++++++++++
testcases/kernel/syscalls/listxattr/listxattr02.c | 107 +++++++++++++++++++++
testcases/kernel/syscalls/listxattr/listxattr03.c | 91 ++++++++++++++++++
10 files changed, 661 insertions(+)
create mode 100644 testcases/kernel/syscalls/flistxattr/Makefile
create mode 100644 testcases/kernel/syscalls/flistxattr/flistxattr01.c
create mode 100644 testcases/kernel/syscalls/flistxattr/flistxattr02.c
create mode 100644 testcases/kernel/syscalls/flistxattr/flistxattr03.c
create mode 100644 testcases/kernel/syscalls/listxattr/Makefile
create mode 100644 testcases/kernel/syscalls/listxattr/listxattr01.c
create mode 100644 testcases/kernel/syscalls/listxattr/listxattr02.c
create mode 100644 testcases/kernel/syscalls/listxattr/listxattr03.c
diff --git a/runtest/syscalls b/runtest/syscalls
index 64d09b2..6c68217 100644
--- a/runtest/syscalls
+++ b/runtest/syscalls
@@ -272,6 +272,10 @@ fcntl34_64 fcntl34_64
fdatasync01 fdatasync01
fdatasync02 fdatasync02
+flistxattr01 flistxattr01
+flistxattr02 flistxattr02
+flistxattr03 flistxattr03
+
flock01 flock01
flock02 flock02
flock03 flock03
@@ -523,6 +527,10 @@ linkat02 linkat02
listen01 listen01
+listxattr01 listxattr01
+listxattr02 listxattr02
+listxattr03 listxattr03
+
llistxattr01 llistxattr01
llistxattr02 llistxattr02
llistxattr03 llistxattr03
diff --git a/testcases/kernel/syscalls/.gitignore b/testcases/kernel/syscalls/.gitignore
index 506219d..de142ba 100644
--- a/testcases/kernel/syscalls/.gitignore
+++ b/testcases/kernel/syscalls/.gitignore
@@ -233,6 +233,9 @@
/fcntl/fcntl34_64
/fdatasync/fdatasync01
/fdatasync/fdatasync02
+/flistxattr/flistxattr01
+/flistxattr/flistxattr02
+/flistxattr/flistxattr03
/flock/flock01
/flock/flock02
/flock/flock03
@@ -482,6 +485,9 @@
/linkat/linkat01
/linkat/linkat02
/listen/listen01
+/listxattr/listxattr01
+/listxattr/listxattr02
+/listxattr/listxattr03
/llistxattr/llistxattr01
/llistxattr/llistxattr02
/llistxattr/llistxattr03
diff --git a/testcases/kernel/syscalls/flistxattr/Makefile b/testcases/kernel/syscalls/flistxattr/Makefile
new file mode 100644
index 0000000..b794ec0
--- /dev/null
+++ b/testcases/kernel/syscalls/flistxattr/Makefile
@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2016 RT-RK Institute for Computer Based Systems
+# Author: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+# the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.
+#
+
+top_srcdir ?= ../../../..
+
+include $(top_srcdir)/include/mk/testcases.mk
+
+include $(top_srcdir)/include/mk/generic_leaf_target.mk
diff --git a/testcases/kernel/syscalls/flistxattr/flistxattr01.c b/testcases/kernel/syscalls/flistxattr/flistxattr01.c
new file mode 100644
index 0000000..e8c2467
--- /dev/null
+++ b/testcases/kernel/syscalls/flistxattr/flistxattr01.c
@@ -0,0 +1,104 @@
+/*
+* Copyright (c) 2016 RT-RK Institute for Computer Based Systems
+* Author: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+* the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.
+*/
+
+/*
+* Test Name: verify_flistxattr01
+*
+* Description:
+* The testcase checks the basic functionality of the flistxattr(2).
+* flistxattr(2) retrieves the list of extended attribute names
+* associated with the file itself in the filesystem.
+*
+*/
+
+#include "config.h"
+#include <errno.h>
+#include <sys/types.h>
+#include <string.h>
+
+#ifdef HAVE_SYS_XATTR_H
+# include <sys/xattr.h>
+#endif
+
+#include "tst_test.h"
+
+#ifdef HAVE_SYS_XATTR_H
+
+#define SECURITY_KEY1 "security.ltptest1"
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
+#define KEY_SIZE (sizeof(SECURITY_KEY1) - 1)
+
+static int fd;
+
+static int has_attribute(const char *list, int llen, const char *attr)
+{
+ int i;
+
+ for (i = 0; i < llen; i += strlen(list + i) + 1) {
+ if (!strcmp(list + i, attr))
+ return 1;
+ }
+ return 0;
+}
+
+static void verify_flistxattr(void)
+{
+ char buf[64];
+
+ TEST(flistxattr(fd, buf, sizeof(buf)));
+ if (TEST_RETURN == -1) {
+ tst_res(TFAIL | TTERRNO, "flistxattr() failed");
+ return;
+ }
+
+ if (!has_attribute(buf, sizeof(buf), SECURITY_KEY1)) {
+ tst_res(TFAIL, "missing attribute %s",
+ SECURITY_KEY1);
+ return;
+ }
+
+ tst_res(TPASS, "flistxattr() succeeded");
+}
+
+static void setup(void)
+{
+ fd = SAFE_OPEN("testfile", O_RDWR | O_CREAT, 0644);
+
+ SAFE_FSETXATTR(fd, SECURITY_KEY1, VALUE, VALUE_SIZE, XATTR_CREATE);
+}
+
+static void cleanup(void)
+{
+ if (fd > 0 && close(fd))
+ tst_res(TWARN | TERRNO, "failed to close file");
+}
+
+static struct tst_test test = {
+ .tid = "flistxattr01",
+ .needs_tmpdir = 1,
+ .needs_root = 1,
+ .test_all = verify_flistxattr,
+ .setup = setup,
+ .cleanup = cleanup,
+};
+
+#else
+ TST_TEST_TCONF("<sys/xattr.h> does not exist.");
+#endif /* HAVE_SYS_XATTR_H */
+
diff --git a/testcases/kernel/syscalls/flistxattr/flistxattr02.c b/testcases/kernel/syscalls/flistxattr/flistxattr02.c
new file mode 100644
index 0000000..f8a761e
--- /dev/null
+++ b/testcases/kernel/syscalls/flistxattr/flistxattr02.c
@@ -0,0 +1,104 @@
+/*
+* Copyright (c) 2016 RT-RK Institute for Computer Based Systems
+* Author: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it would be useful, but
+* WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+*
+* You should have received a copy of the GNU General Public License
+* alone with this program.
+*/
+
+/*
+* Test Name: flistxattr02
+*
+* Description:
+* 1) flistxattr(2) fails if the size of the list buffer is too small
+* to hold the result.
+* 2) flistxattr(2) fails if fd is an invalid file descriptor.
+*
+* Expected Result:
+* 1) flistxattr(2) should return -1 and set errno to ERANGE.
+* 2) flistxattr(2) should return -1 and set errno to EBADF.
+*/
+
+#include "config.h"
+#include <errno.h>
+#include <sys/types.h>
+
+#ifdef HAVE_SYS_XATTR_H
+# include <sys/xattr.h>
+#endif
+
+#include "tst_test.h"
+
+#ifdef HAVE_SYS_XATTR_H
+
+#define SECURITY_KEY "security.ltptest"
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
+
+static int fd1;
+static int fd2 = -1;
+
+static struct test_case {
+ int *fd;
+ size_t size;
+ int exp_err;
+} tc[] = {
+ {&fd1, 1, ERANGE},
+ {&fd2, 20, EBADF}
+};
+
+static void verify_flistxattr(unsigned int n)
+{
+ struct test_case *t = tc + n;
+ char buf[t->size];
+
+ TEST(flistxattr(*t->fd, buf, t->size));
+ if (TEST_RETURN == 0) {
+ tst_res(TFAIL, "flistxattr() succeeded unexpectedly");
+ return;
+ }
+
+ if (t->exp_err != TEST_ERRNO) {
+ tst_res(TFAIL | TTERRNO, "flistxattr() failed "
+ "unexpectedlly, expected %s",
+ tst_strerrno(t->exp_err));
+ } else {
+ tst_res(TPASS | TTERRNO,
+ "flistxattr() failed as expected");
+ }
+}
+
+static void setup(void)
+{
+ fd1 = SAFE_OPEN("testfile", O_RDWR | O_CREAT, 0644);
+
+ SAFE_FSETXATTR(fd1, SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
+}
+
+static void cleanup(void)
+{
+ if (fd1 > 0 && close(fd1))
+ tst_res(TWARN | TERRNO, "failed to close file");
+}
+
+static struct tst_test test = {
+ .tid = "flistxattr02",
+ .needs_tmpdir = 1,
+ .needs_root = 1,
+ .test = verify_flistxattr,
+ .tcnt = ARRAY_SIZE(tc),
+ .setup = setup,
+ .cleanup = cleanup,
+};
+
+#else /* HAVE_SYS_XATTR_H */
+ TST_TEST_TCONF("<sys/xattr.h> does not exist.");
+#endif
diff --git a/testcases/kernel/syscalls/flistxattr/flistxattr03.c b/testcases/kernel/syscalls/flistxattr/flistxattr03.c
new file mode 100644
index 0000000..b9c6b73
--- /dev/null
+++ b/testcases/kernel/syscalls/flistxattr/flistxattr03.c
@@ -0,0 +1,99 @@
+/*
+* Copyright (c) 2016 RT-RK Institute for Computer Based Systems
+* Author: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+* the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.
+*/
+
+/*
+* Test Name: flistxattr03
+*
+* Description:
+* flistxattr is identical to listxattr. an empty buffer of size zero
+* can return the current size of the list of extended attribute names,
+* which can be used to estimate a suitable buffer.
+*/
+
+#include "config.h"
+#include <errno.h>
+#include <sys/types.h>
+
+#ifdef HAVE_SYS_XATTR_H
+# include <sys/xattr.h>
+#endif
+
+#include "tst_test.h"
+
+#ifdef HAVE_SYS_XATTR_H
+
+#define SECURITY_KEY "security.ltptest"
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
+
+static int fd[] = {0, 0};
+
+static int check_suitable_buf(const int file, long size)
+{
+ int n;
+ char buf[size];
+
+ n = flistxattr(file, buf, sizeof(buf));
+
+ return n != -1;
+}
+
+static void verify_flistxattr(unsigned int n)
+{
+ TEST(flistxattr(fd[n], NULL, 0));
+ if (TEST_RETURN == -1) {
+ tst_res(TFAIL | TTERRNO, "flistxattr() failed");
+ return;
+ }
+
+ if (check_suitable_buf(fd[n], TEST_RETURN))
+ tst_res(TPASS, "flistxattr() succeed with suitable buffer");
+ else
+ tst_res(TFAIL, "flistxattr() failed with small buffer");
+}
+
+static void setup(void)
+{
+ fd[0] = SAFE_OPEN("testfile1", O_RDWR | O_CREAT, 0644);
+
+ fd[1] = SAFE_OPEN("testfile2", O_RDWR | O_CREAT, 0644);
+
+ SAFE_FSETXATTR(fd[1], SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
+}
+
+static void cleanup(void)
+{
+ if (fd[1] > 0 && close(fd[1]))
+ tst_res(TWARN | TERRNO, "failed to close file");
+ if (fd[0] > 0 && close(fd[0]))
+ tst_res(TWARN | TERRNO, "failed to close file");
+}
+
+static struct tst_test test = {
+ .tid = "flistxattr03",
+ .needs_tmpdir = 1,
+ .needs_root = 1,
+ .test = verify_flistxattr,
+ .tcnt = ARRAY_SIZE(fd),
+ .setup = setup,
+ .cleanup = cleanup,
+};
+
+#else /* HAVE_SYS_XATTR_H */
+ TST_TEST_TCONF("<sys/xattr.h> does not exist.");
+#endif
diff --git a/testcases/kernel/syscalls/listxattr/Makefile b/testcases/kernel/syscalls/listxattr/Makefile
new file mode 100644
index 0000000..b794ec0
--- /dev/null
+++ b/testcases/kernel/syscalls/listxattr/Makefile
@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2016 RT-RK Institute for Computer Based Systems
+# Author: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+# the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.
+#
+
+top_srcdir ?= ../../../..
+
+include $(top_srcdir)/include/mk/testcases.mk
+
+include $(top_srcdir)/include/mk/generic_leaf_target.mk
diff --git a/testcases/kernel/syscalls/listxattr/listxattr01.c b/testcases/kernel/syscalls/listxattr/listxattr01.c
new file mode 100644
index 0000000..4793c05
--- /dev/null
+++ b/testcases/kernel/syscalls/listxattr/listxattr01.c
@@ -0,0 +1,96 @@
+/*
+* Copyright (c) 2016 RT-RK Institute for Computer Based Systems
+* Author: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+* the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.
+*/
+
+/*
+* Test Name: listxattr01
+*
+* Description:
+* The testcase checks the basic functionality of the listxattr(2).
+* listxattr(2) retrieves the list of extended attribute names
+* associated with the file itself in the filesystem.
+*
+*/
+
+#include "config.h"
+#include <errno.h>
+#include <sys/types.h>
+#include <string.h>
+
+#ifdef HAVE_SYS_XATTR_H
+# include <sys/xattr.h>
+#endif
+
+#include "tst_test.h"
+
+#ifdef HAVE_SYS_XATTR_H
+
+#define SECURITY_KEY1 "security.ltptest1"
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
+#define KEY_SIZE (sizeof(SECURITY_KEY1) - 1)
+#define TESTFILE "testfile"
+
+static int has_attribute(const char *list, int llen, const char *attr)
+{
+ int i;
+
+ for (i = 0; i < llen; i += strlen(list + i) + 1) {
+ if (!strcmp(list + i, attr))
+ return 1;
+ }
+ return 0;
+}
+
+static void verify_listxattr(void)
+{
+ char buf[64];
+
+ TEST(listxattr(TESTFILE, buf, sizeof(buf)));
+ if (TEST_RETURN == -1) {
+ tst_res(TFAIL | TTERRNO, "listxattr() failed");
+ return;
+ }
+
+ if (!has_attribute(buf, sizeof(buf), SECURITY_KEY1)) {
+ tst_res(TFAIL, "missing attribute %s",
+ SECURITY_KEY1);
+ return;
+ }
+
+ tst_res(TPASS, "listxattr() succeeded");
+}
+
+static void setup(void)
+{
+ SAFE_TOUCH(TESTFILE, 0644, NULL);
+
+ SAFE_SETXATTR(TESTFILE, SECURITY_KEY1, VALUE, VALUE_SIZE, XATTR_CREATE);
+}
+
+static struct tst_test test = {
+ .tid = "listxattr01",
+ .needs_tmpdir = 1,
+ .needs_root = 1,
+ .test_all = verify_listxattr,
+ .setup = setup,
+};
+
+#else
+ TST_TEST_TCONF("<sys/xattr.h> does not exist.");
+#endif /* HAVE_SYS_XATTR_H */
+
diff --git a/testcases/kernel/syscalls/listxattr/listxattr02.c b/testcases/kernel/syscalls/listxattr/listxattr02.c
new file mode 100644
index 0000000..15f2225
--- /dev/null
+++ b/testcases/kernel/syscalls/listxattr/listxattr02.c
@@ -0,0 +1,107 @@
+/*
+* Copyright (c) 2016 RT-RK Institute for Computer Based Systems
+* Author: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+* the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.
+*/
+
+/*
+* Test Name: listxattr02
+*
+* Description:
+* 1) listxattr(2) fails if the size of the list buffer is too small
+* to hold the result.
+* 2) listxattr(2) fails if path is an empty string.
+* 3) listxattr(2) fails when attempted to read from a invalid address.
+* 4) listxattr(2) fails if path is longer than allowed.
+*
+* Expected Result:
+* 1) listxattr(2) should return -1 and set errno to ERANGE.
+* 2) listxattr(2) should return -1 and set errno to ENOENT.
+* 3) listxattr(2) should return -1 and set errno to EFAULT.
+* 4) listxattr(2) should return -1 and set errno to ENAMETOOLONG.
+*/
+
+#include "config.h"
+#include <errno.h>
+#include <sys/types.h>
+
+#ifdef HAVE_SYS_XATTR_H
+# include <sys/xattr.h>
+#endif
+
+#include "tst_test.h"
+
+#ifdef HAVE_SYS_XATTR_H
+
+#define SECURITY_KEY "security.ltptest"
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
+#define TESTFILE "testfile"
+
+char longpathname[PATH_MAX + 2];
+
+static struct test_case {
+ const char *path;
+ size_t size;
+ int exp_err;
+} tc[] = {
+ {TESTFILE, 1, ERANGE},
+ {"", 20, ENOENT},
+ {(char *)-1, 20, EFAULT},
+ {longpathname, 20, ENAMETOOLONG}
+};
+
+static void verify_listxattr(unsigned int n)
+{
+ struct test_case *t = tc + n;
+ char buf[t->size];
+
+ TEST(listxattr(t->path, buf, sizeof(buf)));
+ if (TEST_RETURN == 0) {
+ tst_res(TFAIL, "listxattr() succeeded unexpectedly");
+ return;
+ }
+
+ if (t->exp_err != TEST_ERRNO) {
+ tst_res(TFAIL | TTERRNO, "listxattr() failed "
+ "unexpectedlly, expected %s",
+ tst_strerrno(t->exp_err));
+ } else {
+ tst_res(TPASS | TTERRNO,
+ "listxattr() failed as expected");
+ }
+}
+
+static void setup(void)
+{
+ SAFE_TOUCH(TESTFILE, 0644, NULL);
+
+ SAFE_SETXATTR(TESTFILE, SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
+
+ memset(&longpathname, 'a', sizeof(longpathname) - 1);
+}
+
+static struct tst_test test = {
+ .tid = "listxattr02",
+ .needs_tmpdir = 1,
+ .needs_root = 1,
+ .test = verify_listxattr,
+ .tcnt = ARRAY_SIZE(tc),
+ .setup = setup,
+};
+
+#else /* HAVE_SYS_XATTR_H */
+ TST_TEST_TCONF("<sys/xattr.h> does not exist.");
+#endif
diff --git a/testcases/kernel/syscalls/listxattr/listxattr03.c b/testcases/kernel/syscalls/listxattr/listxattr03.c
new file mode 100644
index 0000000..5536084
--- /dev/null
+++ b/testcases/kernel/syscalls/listxattr/listxattr03.c
@@ -0,0 +1,91 @@
+/*
+* Copyright (c) 2016 RT-RK Institute for Computer Based Systems
+* Author: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+* the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.
+*/
+
+/*
+* Test Name: listxattr03
+*
+* Description:
+* An empty buffer of size zero can return the current size of the list
+* of extended attribute names, which can be used to estimate a suitable buffer.
+*/
+
+#include "config.h"
+#include <errno.h>
+#include <sys/types.h>
+
+#ifdef HAVE_SYS_XATTR_H
+# include <sys/xattr.h>
+#endif
+
+#include "tst_test.h"
+
+#ifdef HAVE_SYS_XATTR_H
+
+#define SECURITY_KEY "security.ltptest"
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
+
+static const char * const filename[] = {"testfile1", "testfile2"};
+
+static int check_suitable_buf(const char *name, long size)
+{
+ int n;
+ char buf[size];
+
+ n = listxattr(name, buf, sizeof(buf));
+
+ return n != -1;
+}
+
+static void verify_listxattr(unsigned int n)
+{
+ const char *name = filename[n];
+
+ TEST(listxattr(name, NULL, 0));
+ if (TEST_RETURN == -1) {
+ tst_res(TFAIL | TTERRNO, "listxattr() failed");
+ return;
+ }
+
+ if (check_suitable_buf(name, TEST_RETURN))
+ tst_res(TPASS, "listxattr() succeed with suitable buffer");
+ else
+ tst_res(TFAIL, "listxattr() failed with small buffer");
+}
+
+static void setup(void)
+{
+ SAFE_TOUCH(filename[0], 0644, NULL);
+
+ SAFE_TOUCH(filename[1], 0644, NULL);
+
+ SAFE_SETXATTR(filename[1], SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
+}
+
+static struct tst_test test = {
+ .tid = "listxattr03",
+ .needs_tmpdir = 1,
+ .needs_root = 1,
+ .test = verify_listxattr,
+ .tcnt = ARRAY_SIZE(filename),
+ .setup = setup,
+};
+
+#else /* HAVE_SYS_XATTR_H */
+ TST_TEST_TCONF("<sys/xattr.h> does not exist.");
+#endif
--
1.9.1
^ permalink raw reply related
* [LTP] [PATCH v4 4/5] llistxattr: new testcase for long path name
From: Dejan Jovicevic @ 2016-11-14 12:13 UTC (permalink / raw)
To: ltp
In-Reply-To: <1479125614-24731-1-git-send-email-dejan.jovicevic@rt-rk.com>
Added a test case that checks if the path name, given by the
first argument of the function, is too long. If that is the
case, the function should return -1 and errno should be set
to ENAMETOOLONG.
Signed-off-by: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
---
testcases/kernel/syscalls/llistxattr/llistxattr02.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/testcases/kernel/syscalls/llistxattr/llistxattr02.c b/testcases/kernel/syscalls/llistxattr/llistxattr02.c
index ed3ace3..74cee00 100644
--- a/testcases/kernel/syscalls/llistxattr/llistxattr02.c
+++ b/testcases/kernel/syscalls/llistxattr/llistxattr02.c
@@ -22,11 +22,13 @@
* to hold the result.
* 2) llistxattr(2) fails if path is an empty string.
* 3) llistxattr(2) fails when attempted to read from a invalid address.
+* 4) llistxattr(2) fails if path is longer than allowed.
*
* Expected Result:
* 1) llistxattr(2) should return -1 and set errno to ERANGE.
* 2) llistxattr(2) should return -1 and set errno to ENOENT.
* 3) llistxattr(2) should return -1 and set errno to EFAULT.
+* 4) llistxattr(2) should return -1 and set errno to ENAMETOOLONG.
*/
#include "config.h"
@@ -47,6 +49,8 @@
#define TESTFILE "testfile"
#define SYMLINK "symlink"
+static char longpathname[PATH_MAX + 2];
+
static struct test_case {
const char *path;
size_t size;
@@ -54,7 +58,8 @@ static struct test_case {
} tc[] = {
{SYMLINK, 1, ERANGE},
{"", 20, ENOENT},
- {(char *)-1, 20, EFAULT}
+ {(char *)-1, 20, EFAULT},
+ {longpathname, 20, ENAMETOOLONG}
};
static void verify_llistxattr(unsigned int n)
@@ -84,6 +89,8 @@ static void setup(void)
SAFE_SYMLINK(TESTFILE, SYMLINK);
SAFE_LSETXATTR(SYMLINK, SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
+
+ memset(longpathname, 'a', sizeof(longpathname) - 1);
}
static struct tst_test test = {
--
1.9.1
^ permalink raw reply related
* [LTP] [PATCH v4 3/5] llistxattr: improved code readability and stability
From: Dejan Jovicevic @ 2016-11-14 12:13 UTC (permalink / raw)
To: ltp
In-Reply-To: <1479125614-24731-1-git-send-email-dejan.jovicevic@rt-rk.com>
Changed bits of code, such as hardcoded magic constants,
unnecessary else branches, way of passing array size to
a function, removed unnecessary comments, moved to using
macros instead of string literals where seemed to be fit.
This was done to make the code easier to read and understand,
and make it easier to maintain in case of changes
Signed-off-by: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
---
.../kernel/syscalls/llistxattr/llistxattr01.c | 30 ++++++++++++----------
.../kernel/syscalls/llistxattr/llistxattr02.c | 23 ++++++++---------
.../kernel/syscalls/llistxattr/llistxattr03.c | 12 ++++-----
3 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/testcases/kernel/syscalls/llistxattr/llistxattr01.c b/testcases/kernel/syscalls/llistxattr/llistxattr01.c
index f352032..0176893 100644
--- a/testcases/kernel/syscalls/llistxattr/llistxattr01.c
+++ b/testcases/kernel/syscalls/llistxattr/llistxattr01.c
@@ -37,11 +37,14 @@
#ifdef HAVE_SYS_XATTR_H
-#define SECURITY_KEY1 "security.ltptest1"
-#define SECURITY_KEY2 "security.ltptest2"
-#define VALUE "test"
-#define VALUE_SIZE 4
-#define KEY_SIZE 17
+#define SECURITY_KEY1 "security.ltptest1"
+#define SECURITY_KEY2 "security.ltptest2"
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
+#define KEY_SIZE (sizeof(SECURITY_KEY1) - 1)
+#define TESTFILE "testfile"
+#define SYMLINK "symlink"
+
static int has_attribute(const char *list, int llen, const char *attr)
{
@@ -56,22 +59,21 @@ static int has_attribute(const char *list, int llen, const char *attr)
static void verify_llistxattr(void)
{
- int size = 64;
- char buf[size];
+ char buf[64];
- TEST(llistxattr("symlink", buf, size));
+ TEST(llistxattr(SYMLINK, buf, sizeof(buf)));
if (TEST_RETURN == -1) {
tst_res(TFAIL | TTERRNO, "llistxattr() failed");
return;
}
- if (has_attribute(buf, size, SECURITY_KEY1)) {
+ if (has_attribute(buf, sizeof(buf), SECURITY_KEY1)) {
tst_res(TFAIL, "get file attribute %s unexpectlly",
SECURITY_KEY1);
return;
}
- if (!has_attribute(buf, size, SECURITY_KEY2)) {
+ if (!has_attribute(buf, sizeof(buf), SECURITY_KEY2)) {
tst_res(TFAIL, "missing attribute %s", SECURITY_KEY2);
return;
}
@@ -81,13 +83,13 @@ static void verify_llistxattr(void)
static void setup(void)
{
- SAFE_TOUCH("testfile", 0644, NULL);
+ SAFE_TOUCH(TESTFILE, 0644, NULL);
- SAFE_SYMLINK("testfile", "symlink");
+ SAFE_SYMLINK(TESTFILE, SYMLINK);
- SAFE_LSETXATTR("testfile", SECURITY_KEY1, VALUE, VALUE_SIZE, XATTR_CREATE);
+ SAFE_LSETXATTR(TESTFILE, SECURITY_KEY1, VALUE, VALUE_SIZE, XATTR_CREATE);
- SAFE_LSETXATTR("symlink", SECURITY_KEY2, VALUE, VALUE_SIZE, XATTR_CREATE);
+ SAFE_LSETXATTR(SYMLINK, SECURITY_KEY2, VALUE, VALUE_SIZE, XATTR_CREATE);
}
static struct tst_test test = {
diff --git a/testcases/kernel/syscalls/llistxattr/llistxattr02.c b/testcases/kernel/syscalls/llistxattr/llistxattr02.c
index 2812838..ed3ace3 100644
--- a/testcases/kernel/syscalls/llistxattr/llistxattr02.c
+++ b/testcases/kernel/syscalls/llistxattr/llistxattr02.c
@@ -41,20 +41,19 @@
#ifdef HAVE_SYS_XATTR_H
-#define SECURITY_KEY "security.ltptest"
-#define VALUE "test"
-#define VALUE_SIZE 4
+#define SECURITY_KEY "security.ltptest"
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
+#define TESTFILE "testfile"
+#define SYMLINK "symlink"
static struct test_case {
const char *path;
size_t size;
int exp_err;
} tc[] = {
- /* test1 */
- {"symlink", 1, ERANGE},
- /* test2 */
+ {SYMLINK, 1, ERANGE},
{"", 20, ENOENT},
- /* test3 */
{(char *)-1, 20, EFAULT}
};
@@ -63,8 +62,8 @@ static void verify_llistxattr(unsigned int n)
struct test_case *t = tc + n;
char buf[t->size];
- TEST(llistxattr(t->path, buf, t->size));
- if (TEST_RETURN != -1) {
+ TEST(llistxattr(t->path, buf, sizeof(buf)));
+ if (TEST_RETURN == 0) {
tst_res(TFAIL, "llistxattr() succeeded unexpectedly");
} else {
if (TEST_ERRNO != t->exp_err) {
@@ -80,11 +79,11 @@ static void verify_llistxattr(unsigned int n)
static void setup(void)
{
- SAFE_TOUCH("testfile", 0644, NULL);
+ SAFE_TOUCH(TESTFILE, 0644, NULL);
- SAFE_SYMLINK("testfile", "symlink");
+ SAFE_SYMLINK(TESTFILE, SYMLINK);
- SAFE_LSETXATTR("symlink", SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
+ SAFE_LSETXATTR(SYMLINK, SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
}
static struct tst_test test = {
diff --git a/testcases/kernel/syscalls/llistxattr/llistxattr03.c b/testcases/kernel/syscalls/llistxattr/llistxattr03.c
index 475375e..6a1cb6b 100644
--- a/testcases/kernel/syscalls/llistxattr/llistxattr03.c
+++ b/testcases/kernel/syscalls/llistxattr/llistxattr03.c
@@ -36,8 +36,8 @@
#ifdef HAVE_SYS_XATTR_H
#define SECURITY_KEY "security.ltptest"
-#define VALUE "test"
-#define VALUE_SIZE 4
+#define VALUE "test"
+#define VALUE_SIZE (sizeof(VALUE) - 1)
static const char *filename[] = {"testfile1", "testfile2"};
@@ -46,11 +46,9 @@ static int check_suitable_buf(const char *name, long size)
int n;
char buf[size];
- n = llistxattr(name, buf, size);
- if (n == -1)
- return 0;
- else
- return 1;
+ n = llistxattr(name, buf, sizeof(buf));
+
+ return n != -1;
}
static void verify_llistxattr(unsigned int n)
--
1.9.1
^ permalink raw reply related
* [LTP] [PATCH v4 2/5] llistxattr: moved to using safe macros
From: Dejan Jovicevic @ 2016-11-14 12:13 UTC (permalink / raw)
To: ltp
In-Reply-To: <1479125614-24731-1-git-send-email-dejan.jovicevic@rt-rk.com>
Apply newly created SAFE_LSETXATTR() macro to all files
that test llistxattr().
Signed-off-by: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
---
.../kernel/syscalls/llistxattr/llistxattr01.c | 25 ++--------------------
.../kernel/syscalls/llistxattr/llistxattr02.c | 12 +----------
.../kernel/syscalls/llistxattr/llistxattr03.c | 12 +----------
3 files changed, 4 insertions(+), 45 deletions(-)
diff --git a/testcases/kernel/syscalls/llistxattr/llistxattr01.c b/testcases/kernel/syscalls/llistxattr/llistxattr01.c
index 2e95faf..f352032 100644
--- a/testcases/kernel/syscalls/llistxattr/llistxattr01.c
+++ b/testcases/kernel/syscalls/llistxattr/llistxattr01.c
@@ -43,27 +43,6 @@
#define VALUE_SIZE 4
#define KEY_SIZE 17
-static void set_xattr(const char *path, const char *key)
-{
- int n;
-
- n = lsetxattr(path, key, VALUE, VALUE_SIZE, XATTR_CREATE);
- if (n == -1) {
- if (errno == ENOTSUP) {
- tst_brk(TCONF,
- "no xattr support in fs or mounted "
- "without user_xattr option");
- }
-
- if (errno == EEXIST) {
- tst_brk(TBROK, "exist attribute %s", key);
- } else {
- tst_brk(TBROK | TERRNO,
- "lsetxattr() failed");
- }
- }
-}
-
static int has_attribute(const char *list, int llen, const char *attr)
{
int i;
@@ -106,9 +85,9 @@ static void setup(void)
SAFE_SYMLINK("testfile", "symlink");
- set_xattr("testfile", SECURITY_KEY1);
+ SAFE_LSETXATTR("testfile", SECURITY_KEY1, VALUE, VALUE_SIZE, XATTR_CREATE);
- set_xattr("symlink", SECURITY_KEY2);
+ SAFE_LSETXATTR("symlink", SECURITY_KEY2, VALUE, VALUE_SIZE, XATTR_CREATE);
}
static struct tst_test test = {
diff --git a/testcases/kernel/syscalls/llistxattr/llistxattr02.c b/testcases/kernel/syscalls/llistxattr/llistxattr02.c
index ec4ba6e..2812838 100644
--- a/testcases/kernel/syscalls/llistxattr/llistxattr02.c
+++ b/testcases/kernel/syscalls/llistxattr/llistxattr02.c
@@ -80,21 +80,11 @@ static void verify_llistxattr(unsigned int n)
static void setup(void)
{
- int n;
-
SAFE_TOUCH("testfile", 0644, NULL);
SAFE_SYMLINK("testfile", "symlink");
- n = lsetxattr("symlink", SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
- if (n == -1) {
- if (errno == ENOTSUP) {
- tst_brk(TCONF, "no xattr support in fs or "
- "mounted without user_xattr option");
- } else {
- tst_brk(TBROK | TERRNO, "lsetxattr() failed");
- }
- }
+ SAFE_LSETXATTR("symlink", SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
}
static struct tst_test test = {
diff --git a/testcases/kernel/syscalls/llistxattr/llistxattr03.c b/testcases/kernel/syscalls/llistxattr/llistxattr03.c
index e6e4c68..475375e 100644
--- a/testcases/kernel/syscalls/llistxattr/llistxattr03.c
+++ b/testcases/kernel/syscalls/llistxattr/llistxattr03.c
@@ -71,21 +71,11 @@ static void verify_llistxattr(unsigned int n)
static void setup(void)
{
- int ret;
-
SAFE_TOUCH(filename[0], 0644, NULL);
SAFE_TOUCH(filename[1], 0644, NULL);
- ret = lsetxattr(filename[1], SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
- if (ret == -1) {
- if (errno == ENOTSUP) {
- tst_brk(TCONF, "no xattr support in fs or "
- "mounted without user_xattr option");
- } else {
- tst_brk(TBROK | TERRNO, "lsetxattr() failed");
- }
- }
+ SAFE_LSETXATTR(filename[1], SECURITY_KEY, VALUE, VALUE_SIZE, XATTR_CREATE);
}
static struct tst_test test = {
--
1.9.1
^ permalink raw reply related
* [LTP] [PATCH v4 1/5] safe_macros: add safe_setxattr(), safe_lsetxattr() and safe_fsetxattr()
From: Dejan Jovicevic @ 2016-11-14 12:13 UTC (permalink / raw)
To: ltp
In-Reply-To: <1479125614-24731-1-git-send-email-dejan.jovicevic@rt-rk.com>
Added SAFE_SETXATTR(), SAFE_LSETXATTR() and SAFE_FSETXATTR()
macros to simplify error checking in test preparation. Instead
of calling the system function, checking for their return value
and aborting the test if the operation has failed, just use
corresponding safe macro.
Signed-off-by: Dejan Jovicevic <dejan.jovicevic@rt-rk.com>
---
include/tst_safe_macros.h | 15 +++++++++++
lib/safe_macros.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/include/tst_safe_macros.h b/include/tst_safe_macros.h
index 59cba1a..96bec5c 100644
--- a/include/tst_safe_macros.h
+++ b/include/tst_safe_macros.h
@@ -437,4 +437,19 @@ int safe_getpriority(const char *file, const int lineno, int which, id_t who);
#define SAFE_GETPRIORITY(which, who) \
safe_getpriority(__FILE__, __LINE__, (which), (who))
+int safe_setxattr(const char *file, const int lineno, const char *path,
+ const char *name, const void *value, size_t size, int flags);
+#define SAFE_SETXATTR(path, name, value, size, flags) \
+ safe_setxattr(__FILE__, __LINE__, (path), (name), (value), (size), (flags))
+
+int safe_lsetxattr(const char *file, const int lineno, const char *path,
+ const char *name, const void *value, size_t size, int flags);
+#define SAFE_LSETXATTR(path, name, value, size, flags) \
+ safe_lsetxattr(__FILE__, __LINE__, (path), (name), (value), (size), (flags))
+
+int safe_fsetxattr(const char *file, const int lineno, int fd, const char *name,
+ const void *value, size_t size, int flags);
+#define SAFE_FSETXATTR(fd, name, value, size, flags) \
+ safe_fsetxattr(__FILE__, __LINE__, (fd), (name), (value), (size), (flags))
+
#endif /* SAFE_MACROS_H__ */
diff --git a/lib/safe_macros.c b/lib/safe_macros.c
index b97f43d..4f91bc6 100644
--- a/lib/safe_macros.c
+++ b/lib/safe_macros.c
@@ -5,6 +5,7 @@
#include <sys/stat.h>
#include <sys/wait.h>
#include <sys/mount.h>
+#include <sys/xattr.h>
#include <errno.h>
#include <fcntl.h>
#include <libgen.h>
@@ -810,3 +811,66 @@ int safe_getpriority(const char *file, const int lineno, int which, id_t who)
errno = err;
return rval;
}
+
+int safe_setxattr(const char *file, const int lineno, const char *path,
+ const char *name, const void *value, size_t size, int flags)
+{
+ int rval;
+
+ rval = setxattr(path, name, value, size, flags);
+
+ if (rval) {
+ if (errno == ENOTSUP) {
+ tst_brkm(TCONF, NULL,
+ "%s:%d: no xattr support in fs or mounted "
+ "without user_xattr option", file, lineno);
+ }
+
+ tst_brkm(TBROK | TERRNO, NULL, "%s:%d: setxattr() failed",
+ file, lineno);
+ }
+
+ return rval;
+}
+
+int safe_lsetxattr(const char *file, const int lineno, const char *path,
+ const char *name, const void *value, size_t size, int flags)
+{
+ int rval;
+
+ rval = lsetxattr(path, name, value, size, flags);
+
+ if (rval) {
+ if (errno == ENOTSUP) {
+ tst_brkm(TCONF, NULL,
+ "%s:%d: no xattr support in fs or mounted "
+ "without user_xattr option", file, lineno);
+ }
+
+ tst_brkm(TBROK | TERRNO, NULL, "%s:%d: lsetxattr() failed",
+ file, lineno);
+ }
+
+ return rval;
+}
+
+int safe_fsetxattr(const char *file, const int lineno, int fd, const char *name,
+ const void *value, size_t size, int flags)
+{
+ int rval;
+
+ rval = fsetxattr(fd, name, value, size, flags);
+
+ if (rval) {
+ if (errno == ENOTSUP) {
+ tst_brkm(TCONF, NULL,
+ "%s:%d: no xattr support in fs or mounted "
+ "without user_xattr option", file, lineno);
+ }
+
+ tst_brkm(TBROK | TERRNO, NULL, "%s:%d: fsetxattr() failed",
+ file, lineno);
+ }
+
+ return rval;
+}
--
1.9.1
^ permalink raw reply related
* [LTP] [PATCH v4 0/5] listxattr related calls: new tests and test case
From: Dejan Jovicevic @ 2016-11-14 12:13 UTC (permalink / raw)
To: ltp
v3 -> v4:
- Fixed code errors from previous series. Fixed merge conflict. Added the
safe_*setxattr() function prototypes in tst_safe_macros.h. Changed the
licence for the new tests to GPLv2+.
v2 -> v3:
- Removed the unnecessary string termination after the memset() call in
llistxattr02 and listxattr02.
- Modified the code to be more readable and maintainable,
this resulted in creating a new patch that pretty much does
the same thing for llistxattr() tests.
- Started usign corresponding safe macros in the setup of all
of the listxattr related tests. This resulted in a new patch
that implements these safe macros.
v1 -> v2:
- Modified the setup for the new test case in llistxattr02 and
a testcase in listxattr02.
- Modified commit messages.
In this series, there is a new test case added in the existing llistxattr02
test. Also, new tests are added for system calls flistxattr(), and listxattr()
which are based on the existing tests for llistxattr.
Dejan Jovicevic (5):
safe_macros: add safe_setxattr(), safe_lsetxattr() and
safe_fsetxattr()
llistxattr: moved to using safe macros
llistxattr: improved code readability and stability
llistxattr: new testcase for long path name
flistxattr and listxattr: added tests
include/tst_safe_macros.h | 15 +++
lib/safe_macros.c | 64 ++++++++++++
runtest/syscalls | 8 ++
testcases/kernel/syscalls/.gitignore | 6 ++
testcases/kernel/syscalls/flistxattr/Makefile | 23 +++++
.../kernel/syscalls/flistxattr/flistxattr01.c | 104 ++++++++++++++++++++
.../kernel/syscalls/flistxattr/flistxattr02.c | 104 ++++++++++++++++++++
.../kernel/syscalls/flistxattr/flistxattr03.c | 99 +++++++++++++++++++
testcases/kernel/syscalls/listxattr/Makefile | 23 +++++
testcases/kernel/syscalls/listxattr/listxattr01.c | 96 ++++++++++++++++++
testcases/kernel/syscalls/listxattr/listxattr02.c | 107 +++++++++++++++++++++
testcases/kernel/syscalls/listxattr/listxattr03.c | 91 ++++++++++++++++++
.../kernel/syscalls/llistxattr/llistxattr01.c | 49 +++-------
.../kernel/syscalls/llistxattr/llistxattr02.c | 40 ++++----
.../kernel/syscalls/llistxattr/llistxattr03.c | 24 ++---
15 files changed, 779 insertions(+), 74 deletions(-)
create mode 100644 testcases/kernel/syscalls/flistxattr/Makefile
create mode 100644 testcases/kernel/syscalls/flistxattr/flistxattr01.c
create mode 100644 testcases/kernel/syscalls/flistxattr/flistxattr02.c
create mode 100644 testcases/kernel/syscalls/flistxattr/flistxattr03.c
create mode 100644 testcases/kernel/syscalls/listxattr/Makefile
create mode 100644 testcases/kernel/syscalls/listxattr/listxattr01.c
create mode 100644 testcases/kernel/syscalls/listxattr/listxattr02.c
create mode 100644 testcases/kernel/syscalls/listxattr/listxattr03.c
--
1.9.1
^ permalink raw reply
* [PATCH v2 07/10] ARM: add low level debug uart for rk1108
From: Andy Yan @ 2016-11-14 12:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479124550-24037-1-git-send-email-andy.yan@rock-chips.com>
RK1108 UARTs are Synopsis DesignWare 8250 compatible.
Only with different register addresses.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Jacob Chen <jacob2.chen@rock-chips.com>
---
Changes in v2: None
arch/arm/Kconfig.debug | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index d83f7c3..408540f 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -776,6 +776,30 @@ choice
their output to the standard serial port on the RealView
PB1176 platform.
+ config DEBUG_RK1108_UART0
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART0"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
+ config DEBUG_RK1108_UART1
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART1"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
+ config DEBUG_RK1108_UART2
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART2"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
config DEBUG_RK29_UART0
bool "Kernel low-level debugging messages via Rockchip RK29 UART0"
depends on ARCH_ROCKCHIP
@@ -1465,6 +1489,9 @@ config DEBUG_UART_PHYS
default 0x10126000 if DEBUG_RK3X_UART1
default 0x101f1000 if DEBUG_VERSATILE
default 0x101fb000 if DEBUG_NOMADIK_UART
+ default 0x10210000 if DEBUG_RK1108_UART2
+ default 0x10220000 if DEBUG_RK1108_UART1
+ default 0x10230000 if DEBUG_RK1108_UART0
default 0x11002000 if DEBUG_MT8127_UART0
default 0x11006000 if DEBUG_MT6589_UART0
default 0x11009000 if DEBUG_MT8135_UART3
@@ -1563,6 +1590,9 @@ config DEBUG_UART_PHYS
config DEBUG_UART_VIRT
hex "Virtual base address of debug UART"
+ default 0xc881f000 if DEBUG_RK1108_UART2
+ default 0xc8821000 if DEBUG_RK1108_UART1
+ default 0xc8912000 if DEBUG_RK1108_UART0
default 0xe0000a00 if DEBUG_NETX_UART
default 0xe0010fe0 if ARCH_RPC
default 0xf0000be0 if ARCH_EBSA110
--
2.7.4
^ permalink raw reply related
* [PATCH v2 07/10] ARM: add low level debug uart for rk1108
From: Andy Yan @ 2016-11-14 12:12 UTC (permalink / raw)
To: heiko; +Cc: linux-rockchip, linux-arm-kernel, linux, linux-kernel, Andy Yan
In-Reply-To: <1479124550-24037-1-git-send-email-andy.yan@rock-chips.com>
RK1108 UARTs are Synopsis DesignWare 8250 compatible.
Only with different register addresses.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Jacob Chen <jacob2.chen@rock-chips.com>
---
Changes in v2: None
arch/arm/Kconfig.debug | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index d83f7c3..408540f 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -776,6 +776,30 @@ choice
their output to the standard serial port on the RealView
PB1176 platform.
+ config DEBUG_RK1108_UART0
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART0"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
+ config DEBUG_RK1108_UART1
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART1"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
+ config DEBUG_RK1108_UART2
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART2"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
config DEBUG_RK29_UART0
bool "Kernel low-level debugging messages via Rockchip RK29 UART0"
depends on ARCH_ROCKCHIP
@@ -1465,6 +1489,9 @@ config DEBUG_UART_PHYS
default 0x10126000 if DEBUG_RK3X_UART1
default 0x101f1000 if DEBUG_VERSATILE
default 0x101fb000 if DEBUG_NOMADIK_UART
+ default 0x10210000 if DEBUG_RK1108_UART2
+ default 0x10220000 if DEBUG_RK1108_UART1
+ default 0x10230000 if DEBUG_RK1108_UART0
default 0x11002000 if DEBUG_MT8127_UART0
default 0x11006000 if DEBUG_MT6589_UART0
default 0x11009000 if DEBUG_MT8135_UART3
@@ -1563,6 +1590,9 @@ config DEBUG_UART_PHYS
config DEBUG_UART_VIRT
hex "Virtual base address of debug UART"
+ default 0xc881f000 if DEBUG_RK1108_UART2
+ default 0xc8821000 if DEBUG_RK1108_UART1
+ default 0xc8912000 if DEBUG_RK1108_UART0
default 0xe0000a00 if DEBUG_NETX_UART
default 0xe0010fe0 if ARCH_RPC
default 0xf0000be0 if ARCH_EBSA110
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 3/6] iio: adc: Add support for STM32 ADC
From: Lars-Peter Clausen @ 2016-11-14 12:11 UTC (permalink / raw)
To: Fabrice Gasnier, linux-iio, linux-arm-kernel, devicetree,
linux-kernel
Cc: jic23, lee.jones, linux, robh+dt, mark.rutland, mcoquelin.stm32,
alexandre.torgue, knaack.h, pmeerw
In-Reply-To: <1478794738-28933-4-git-send-email-fabrice.gasnier@st.com>
On 11/10/2016 05:18 PM, Fabrice Gasnier wrote:
[...]
> + static int stm32_adc_single_conv(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *res)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + long timeout;
> + u32 val;
> + u16 result;
> + int ret;
> +
> + reinit_completion(&adc->completion);
> +
> + adc->buffer = &result;
> +
> + /* Program chan number in regular sequence */
> + val = stm32_adc_readl(adc, STM32F4_ADCX_SQR3);
> + val &= ~STM32F4_SQ1_MASK;
> + val |= chan->channel << STM32F4_SQ1_SHIFT;
> + stm32_adc_writel(adc, STM32F4_ADCX_SQR3, val);
> +
> + /* Set regular sequence len (0 for 1 conversion) */
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_SQR1, STM32F4_L_MASK);
> +
> + /* Trigger detection disabled (conversion can be launched in SW) */
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_EXTEN_MASK);
> +
> + stm32_adc_conv_irq_enable(adc);
> +
> + stm32_adc_start_conv(adc);
> +
> + timeout = wait_for_completion_interruptible_timeout(
> + &adc->completion, STM32_ADC_TIMEOUT);
> + if (timeout == 0) {
> + dev_warn(&indio_dev->dev, "Conversion timed out!\n");
This should be dev_dbg() at most. This out of band reporting is not
particular useful for applications as it is impossible to match the error to
the action that triggered it. And you also report the error through the
error code, so the applications knows what is going on.
> + ret = -ETIMEDOUT;
> + } else if (timeout < 0) {
> + dev_warn(&indio_dev->dev, "Interrupted conversion!\n");
> + ret = -EINTR;
This should just propagate the error returned by wait_for_completion...().
This will make sure that the right behavior occurs based on the SA_RESTART
policy.
> + } else {
> + *res = result;
> + ret = IIO_VAL_INT;
> + }
> +
> + stm32_adc_stop_conv(adc);
> +
> + stm32_adc_conv_irq_disable(adc);
> +
> + return ret;
^ permalink raw reply
* Re: [PATCH v2 3/6] iio: adc: Add support for STM32 ADC
From: Lars-Peter Clausen @ 2016-11-14 12:11 UTC (permalink / raw)
To: Fabrice Gasnier, linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, lee.jones-QSEj5FYQhm4dnm+yROfE0A,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
alexandre.torgue-qxv4g6HH51o, knaack.h-Mmb7MZpHnFY,
pmeerw-jW+XmwGofnusTnJN9+BGXg
In-Reply-To: <1478794738-28933-4-git-send-email-fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
On 11/10/2016 05:18 PM, Fabrice Gasnier wrote:
[...]
> + static int stm32_adc_single_conv(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *res)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + long timeout;
> + u32 val;
> + u16 result;
> + int ret;
> +
> + reinit_completion(&adc->completion);
> +
> + adc->buffer = &result;
> +
> + /* Program chan number in regular sequence */
> + val = stm32_adc_readl(adc, STM32F4_ADCX_SQR3);
> + val &= ~STM32F4_SQ1_MASK;
> + val |= chan->channel << STM32F4_SQ1_SHIFT;
> + stm32_adc_writel(adc, STM32F4_ADCX_SQR3, val);
> +
> + /* Set regular sequence len (0 for 1 conversion) */
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_SQR1, STM32F4_L_MASK);
> +
> + /* Trigger detection disabled (conversion can be launched in SW) */
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_EXTEN_MASK);
> +
> + stm32_adc_conv_irq_enable(adc);
> +
> + stm32_adc_start_conv(adc);
> +
> + timeout = wait_for_completion_interruptible_timeout(
> + &adc->completion, STM32_ADC_TIMEOUT);
> + if (timeout == 0) {
> + dev_warn(&indio_dev->dev, "Conversion timed out!\n");
This should be dev_dbg() at most. This out of band reporting is not
particular useful for applications as it is impossible to match the error to
the action that triggered it. And you also report the error through the
error code, so the applications knows what is going on.
> + ret = -ETIMEDOUT;
> + } else if (timeout < 0) {
> + dev_warn(&indio_dev->dev, "Interrupted conversion!\n");
> + ret = -EINTR;
This should just propagate the error returned by wait_for_completion...().
This will make sure that the right behavior occurs based on the SA_RESTART
policy.
> + } else {
> + *res = result;
> + ret = IIO_VAL_INT;
> + }
> +
> + stm32_adc_stop_conv(adc);
> +
> + stm32_adc_conv_irq_disable(adc);
> +
> + return ret;
--
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^ permalink raw reply
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