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* ✓ Fi.CI.BAT: success for drm/i915: Per-plane rotation leftovers
From: Patchwork @ 2016-11-14 17:47 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx
In-Reply-To: <1479142440-25283-1-git-send-email-ville.syrjala@linux.intel.com>

== Series Details ==

Series: drm/i915: Per-plane rotation leftovers
URL   : https://patchwork.freedesktop.org/series/15290/
State : success

== Summary ==

Series 15290v1 drm/i915: Per-plane rotation leftovers
https://patchwork.freedesktop.org/api/1.0/series/15290/revisions/1/mbox/


fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

8670f0f0d91190e0d090ee910c73ed83c37cfef5 drm-intel-nightly: 2016y-11m-14d-16h-10m-52s UTC integration manifest
86c7280 drm/i915: Add horizontal mirroring support for CHV pipe B planes
c2f2b21 drm/i915: Clean up rotation DSPCNTR/DVSCNTR/etc. setup
00f1032 drm/i915: Use & instead if == to check for rotations

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2986/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply

* [RFC][PATCH 6/7] kref: Avoid more abuse
From: Peter Zijlstra @ 2016-11-14 17:39 UTC (permalink / raw)
  To: gregkh, keescook, will.deacon, elena.reshetova, arnd, tglx, mingo,
	hpa, dave
  Cc: linux-kernel, Peter Zijlstra (Intel)
In-Reply-To: <20161114173946.501528675@infradead.org>

[-- Attachment #1: peterz-ref-4b.patch --]
[-- Type: text/plain, Size: 629 bytes --]

Leak references by unbalanced get, instead of poking at kref
implementation details.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
 drivers/usb/mon/mon_main.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/usb/mon/mon_main.c
+++ b/drivers/usb/mon/mon_main.c
@@ -409,7 +409,7 @@ static void __exit mon_exit(void)
 			printk(KERN_ERR TAG
 			    ": Outstanding opens (%d) on usb%d, leaking...\n",
 			    mbus->nreaders, mbus->u_bus->busnum);
-			atomic_set(&mbus->ref.refcount, 2);	/* Force leak */
+			kref_get(&mbus->ref); /* Force leak */
 		}
 
 		mon_dissolve(mbus, mbus->u_bus);

^ permalink raw reply

* [U-Boot] [PATCH] armv8: QSPI: Add AHB bus 16MB+ size support
From: york sun @ 2016-11-14 17:46 UTC (permalink / raw)
  To: u-boot
In-Reply-To: <DB6PR0401MB2407DAE42C7A0D03C582431989A60@DB6PR0401MB2407.eurprd04.prod.outlook.com>

On 11/07/2016 10:03 PM, Yao Yuan wrote:
> On 11/08/2016 02:27 AM, York Sun wrote:
>> On 10/25/2016 07:10 PM, Yuan Yao wrote:
>>> From: Yuan Yao <yao.yuan@nxp.com>
>>>
>>> The default configuration for QSPI AHB bus can't support 16MB+.
>>> But some flash on NXP layerscape board are more than 16MB.
>>
>> So what do you do?
>>
>> Is this an erratum workaround? If yes, please refer the erratum number.
>
> Hi York,
>
> I think It's not an erratum maybe it's better to call it new feature.
>
> As a default configuration for QSPI AHB, the address size is 3-bytes.
> It has a good compatibility for QSPI boot for different SPI-NOR flash.
>
> But if the address size is only 3-bytes, the QSPI can't access to the data that more than 16M+.
>
> So we can update the default configuration for QSPI AHB in uboot to use 4-bytes address.
> So that QSPI can access to 16M+ size by AHB bus.

Let me try to understand this. With your change, 4-byte addressing is 
supported. Do all flash chips support 4-byte addressing?


>
> Thanks.
>>
>>>
>>> Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
>>> ---
>>>  arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 37
>> ++++++++++++++++++++++
>>>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
>>> .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
>>>  include/configs/ls1012a_common.h                   |  1 +
>>>  include/configs/ls1046ardb.h                       |  1 +
>>>  5 files changed, 41 insertions(+)
>>>
>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> index d68eeba..18d753e 100644
>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> @@ -370,6 +370,40 @@ void fsl_lsch2_early_init_f(void)  }  #endif
>>>
>>> +#ifdef CONFIG_QSPI_AHB_INIT
>>> +/* Enable 4bytes address support and fast read */ int
>>> +qspi_ahb_init(void) {
>>> +	u32 *qspi_lut, lut_key, *qspi_key;
>>> +
>>> +	qspi_key = (void *)CONFIG_SYS_QSPI_ADDR + 0x300;
>>> +	qspi_lut = (void *)CONFIG_SYS_QSPI_ADDR + 0x310;
>>> +
>>> +	lut_key = in_be32(qspi_key);
>>> +
>>> +	if (lut_key == 0x5af05af0) {
>>> +		/* That means the register is BE */
>>> +		out_be32(qspi_key, 0x5af05af0);
>>> +		out_be32(qspi_key + 1, 0x00000002);
>>> +		out_be32(qspi_lut, 0x0820040c);
>>> +		out_be32(qspi_lut + 1, 0x1c080c08);
>>> +		out_be32(qspi_lut + 2, 0x00002400);
>>> +		out_be32(qspi_key, 0x5af05af0);
>>> +		out_be32(qspi_key + 1, 0x00000001);
>>> +	} else {
>>> +		/* That means the register is LE */
>>> +		out_le32(qspi_key, 0x5af05af0);
>>> +		out_le32(qspi_key + 1, 0x00000002);
>>> +		out_le32(qspi_lut, 0x0820040c);
>>> +		out_le32(qspi_lut + 1, 0x1c080c08);
>>> +		out_le32(qspi_lut + 2, 0x00002400);
>>> +		out_le32(qspi_key, 0x5af05af0);
>>> +		out_le32(qspi_key + 1, 0x00000001);
>>> +	}
>>
>> What do these sequences do?
>
> It used to set the AHB bus to use 4-bytes command and the corresponding sequence.
> So that QSPI can access to 16M+ size by AHB bus.
>
>>
>> Put a blank line before return.

You need a blank line here.

>>
>>> +	return 0;
>>> +}
>>> +#endif
>>> +
>>>  #ifdef CONFIG_BOARD_LATE_INIT
>>>  int board_late_init(void)
>>>  {
>>> @@ -379,6 +413,9 @@ int board_late_init(void)  #ifdef
>>> CONFIG_CHAIN_OF_TRUST
>>>  	fsl_setenv_chain_of_trust();
>>>  #endif
>>> +#ifdef CONFIG_QSPI_AHB_INIT
>>> +	qspi_ahb_init();
>>> +#endif
>>>
>>>  	return 0;
>>>  }
>>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
>>> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
>>> index d88543d..a28b1fd 100644
>>> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
>>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
>>> @@ -18,6 +18,7 @@
>>>  #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR +
>> 0x00180000)
>>>  #define CONFIG_SYS_GIC400_ADDR			(CONFIG_SYS_IMMR +
>> 0x00400000)
>>>  #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR +
>> 0x00530000)
>>> +#define CONFIG_SYS_QSPI_ADDR			(CONFIG_SYS_IMMR +
>> 0x00550000)
>>>  #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR +
>> 0x00560000)
>>>  #define CONFIG_SYS_FSL_CSU_ADDR
>> 	(CONFIG_SYS_IMMR + 0x00510000)
>>>  #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR +
>> 0x00ee0000)
>>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> index 7acba27..8aefc76 100644
>>> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> @@ -19,6 +19,7 @@
>>>  #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR +
>> 0x00300000)
>>>  #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR +
>> 0x00310000)
>>>  #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR +
>> 0x00370000)
>>> +#define CONFIG_SYS_QSPI_ADDR			(CONFIG_SYS_IMMR +
>> 0x010c0000)
>>>  #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR +
>> 0x01140000)
>>>  #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR +
>> 0x01240000)
>>>  #define CONFIG_SYS_NS16550_COM1
>> 	(CONFIG_SYS_IMMR + 0x011C0500)
>>> diff --git a/include/configs/ls1012a_common.h
>>> b/include/configs/ls1012a_common.h
>>> index 80603c9..c1e1102 100644
>>> --- a/include/configs/ls1012a_common.h
>>> +++ b/include/configs/ls1012a_common.h
>>> @@ -61,6 +61,7 @@
>>>
>>>  #define FSL_QSPI_FLASH_SIZE		(1 << 24)
>>>  #define FSL_QSPI_FLASH_NUM		2
>>> +#define CONFIG_QSPI_AHB_INIT

New CONFIG_* macros are not accepted. Please use Kconfig instead.

>>>
>>>  /*
>>>   * Environment
>>> diff --git a/include/configs/ls1046ardb.h
>>> b/include/configs/ls1046ardb.h index 2fe8fc1..662ecb1 100644
>>> --- a/include/configs/ls1046ardb.h
>>> +++ b/include/configs/ls1046ardb.h
>>> @@ -209,6 +209,7 @@
>>>  #define FSL_QSPI_FLASH_SIZE		(1 << 26)
>>>  #define FSL_QSPI_FLASH_NUM		2
>>>  #define CONFIG_SPI_FLASH_BAR
>>> +#define CONFIG_QSPI_AHB_INIT
>>
>> Is it really a config option? Is it really board-dependent? Does it compile on the
>> latest master branch?
>>
>
> Yes, I think it's a config option.
> 1, whether it supports 16M+ or not will not break the existing functionality.

What do you mean exactly? With this patch, old flash chips continue to 
work even you set it to 4-byte addressing? If true, why don't you enable 
this feature for all and get rid of the macro?

> 2, Some flash is just only 16M size. (the SPI flash on LS1043A)

This is not an option. It is a requirement.

>
> Yes, It's board-dependent.
> It's depend the flash size on the board whether it's more than 16M.
> For example:
> 1, LS1046ARDB, LS1012ARDB, LS1012AQDS need
> 2, LS1043 don't need.

Do LS1043A boards still work with this feature on?

>
> I have tested it on LS1046ARDB and LS1012ARDB.

The bottom of line is, if all existing and future boards work fine with 
this feature, you don't need the condition macro. If some board/flash 
cannot work without this feature, enable it in Kconfig.

York

^ permalink raw reply

* Re: [meta-raspberrypi][PATCH] linux-firmware_git.bbappend: Delete
From: Khem Raj @ 2016-11-14 17:45 UTC (permalink / raw)
  To: Piotr Lewicki; +Cc: yocto@yoctoproject.org
In-Reply-To: <c0c7583d-e393-3256-1f8a-8452f6e1f82a@elfin.de>

are you using linux-firmware-bcm43430

On Mon, Nov 14, 2016 at 4:27 AM, Piotr Lewicki <piotr.lewicki@elfin.de> wrote:
> Dear Raj,
>
> I have been trying to test this, but I get "ERROR: Nothing RPROVIDES
> 'linux-firmware-brcm43430'".
>
> I'm one hundred percent sure that I have the commit you have mentioned
> ("linux-firmware: package Broadcom BCM43430 firmware").
>
> I use poky- latest on morty branch and meta-openembedded - also latest on
> morty branch.
>
> Since I don't use bluetooth I have removed the line
>
> MACHINE_EXTRA_RRECOMMENDS += "linux-firmware-brcm43430"
>
> from the file `meta-raspberrypi/conf/machine/raspberrypi3.conf`
>
>
> Any idea why it is not building for me?
>
> BR,
>
> Piotr
>
>
> On 03.11.2016 23:26, Khem Raj wrote:
>>
>> OE-core already bumped the base rev on linux-firmware package
>> to include the upstreamed version of brcmfmac43430 firmware in
>> september via OE-Core commit a0bc732976670810505286ba43feee70e2c812ce
>>
>> Signed-off-by: Khem Raj <raj.khem@gmail.com>
>> ---
>>   .../linux-firmware/LICENSE.broadcom_brcm80211      | 205
>> ---------------------
>>   .../linux-firmware/brcmfmac43430-sdio.bin          | Bin 368957 -> 0
>> bytes
>>   .../linux-firmware/brcmfmac43430-sdio.txt          |  66 -------
>>   .../linux-firmware/linux-firmware_git.bbappend     |  34 ----
>>   4 files changed, 305 deletions(-)
>>   delete mode 100644
>> recipes-kernel/linux-firmware/linux-firmware/LICENSE.broadcom_brcm80211
>>   delete mode 100644
>> recipes-kernel/linux-firmware/linux-firmware/brcmfmac43430-sdio.bin
>>   delete mode 100644
>> recipes-kernel/linux-firmware/linux-firmware/brcmfmac43430-sdio.txt
>>   delete mode 100644
>> recipes-kernel/linux-firmware/linux-firmware_git.bbappend
>>
>> diff --git
>> a/recipes-kernel/linux-firmware/linux-firmware/LICENSE.broadcom_brcm80211
>> b/recipes-kernel/linux-firmware/linux-firmware/LICENSE.broadcom_brcm80211
>> deleted file mode 100644
>> index e2cf868..0000000
>> ---
>> a/recipes-kernel/linux-firmware/linux-firmware/LICENSE.broadcom_brcm80211
>> +++ /dev/null
>> @@ -1,205 +0,0 @@
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>> -LICENSEE FOR SOFTWARE UNDER THIS AGREEMENT.  THESE LIMITATIONS SHALL
>> APPLY
>> -NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.
>> -
>> -7.     MISCELLANEOUS
>> -
>> -7.1.   Export Regulations. YOU UNDERSTAND AND AGREE THAT THE SOFTWARE IS
>> -SUBJECT TO UNITED STATES AND OTHER APPLICABLE EXPORT-RELATED LAWS AND
>> -REGULATIONS AND THAT YOU MAY NOT EXPORT, RE-EXPORT OR TRANSFER THE
>> SOFTWARE OR
>> -ANY DIRECT PRODUCT OF THE SOFTWARE EXCEPT AS PERMITTED UNDER THOSE LAWS.
>> -WITHOUT LIMITING THE FOREGOING, EXPORT, RE-EXPORT OR TRANSFER OF THE
>> SOFTWARE
>> -TO CUBA, IRAN, NORTH KOREA, SUDAN AND SYRIA IS PROHIBITED.
>> -
>> -7.2    Assignment. This Agreement shall be binding upon and inure to the
>> -benefit of the parties and their respective successors and assigns,
>> provided,
>> -however that Licensee may not assign this Agreement or any rights or
>> obligation
>> -hereunder, directly or indirectly, by operation of law or otherwise,
>> without
>> -the prior written consent of Broadcom, and any such attempted assignment
>> shall
>> -be void.  Notwithstanding the foregoing, Licensee may assign this
>> Agreement to
>> -a successor to all or substantially all of its business or assets to
>> which this
>> -Agreement relates that is not a competitor of Broadcom.
>> -
>> -7.3.   Governing Law; Venue.  This Agreement shall be governed by the
>> laws of
>> -California without regard to any conflict-of-laws rules, and the United
>> Nations
>> -Convention on Contracts for the International Sale of Goods is hereby
>> excluded.
>> -The sole jurisdiction and venue for actions related to the subject matter
>> -hereof shall be the state and federal courts located in the County of
>> Orange,
>> -California, and both parties hereby consent to such jurisdiction and
>> venue.
>> -
>> -7.4.   Severability.  All terms and provisions of this Agreement shall,
>> if
>> -possible, be construed in a manner which makes them valid, but in the
>> event any
>> -term or provision of this Agreement is found by a court of competent
>> -jurisdiction to be illegal or unenforceable, the validity or
>> enforceability of
>> -the remainder of this Agreement shall not be affected if the illegal or
>> -unenforceable provision does not materially affect the intent of this
>> -Agreement.  If the illegal or unenforceable provision materially affects
>> the
>> -intent of the parties to this Agreement, this Agreement shall become
>> -terminated.
>> -
>> -7.5.   Equitable Relief.  Licensee hereby acknowledges that its breach of
>> this
>> -Agreement would cause irreparable harm and significant injury to Broadcom
>> that
>> -may be difficult to ascertain and that a remedy at law would be
>> inadequate.
>> -Accordingly, Licensee agrees that Broadcom shall have the right to seek
>> and
>> -obtain immediate injunctive relief to enforce obligations under the
>> Agreement
>> -in addition to any other rights and remedies it may have.
>> -
>> -7.6.   Waiver.  The waiver of, or failure to enforce, any breach or
>> default
>> -hereunder shall not constitute the waiver of any other or subsequent
>> breach or
>> -default.
>> -
>> -7.7.   Entire Agreement.  This Agreement sets forth the entire Agreement
>> -between the parties and supersedes any and all prior proposals,
>> agreements and
>> -representations between them, whether written or oral concerning the
>> Software.
>> -This Agreement may be changed only by mutual agreement of the parties in
>> -writing.
>> -
>> diff --git
>> a/recipes-kernel/linux-firmware/linux-firmware/brcmfmac43430-sdio.bin
>> b/recipes-kernel/linux-firmware/linux-firmware/brcmfmac43430-sdio.bin
>> deleted file mode 100644
>> index
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>> zHYr~_`3{z}=Fl*F>kP}cU*tQ?98>w0@||awurxGp=FajMal62VD$3UjiPlCX&Nf@I
>> z+eq4l0R3X8nD9{iAa*^sVK1a0=O0<NQ;93EhPdjPGx-i3iO89-eTrfk$=gX~SRQt9
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>> z9%E}c5BGA9kKCAbH4UuhjYz|ZG`QY0uGV=1()h8@K9a6jV~=r2gXT`l^gZlBXM^kh
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>> z?Q<0`2c|k1Z7q5RfjQRlmla;ThDT32b?s}o!^#nxV+G!=q9^xEhZYqgH&Wf4mmWGk
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>> zcKE1u@$^P5guNCrxi`dcEo5vX-H$%8Ler1$p)<=#ddtkIWp=IDHXV2UA$rOTSr+sP
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>> z0fN%g&`4PM86|RZ71n~44Qq<Xuo|LMUvK9grMgiX?w~&P@KX9Ql5z_)ReO4{d7mQA
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>> zTfWduQZfPtywqTlttAWSdqaEuc_yC^R1G>8U*UEHtq(1DNS8&!T^9^wwL2lOxtz||
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>> z_%<>MH(3r^rVn^5+QFpYd*ccd>7@&}OYXrIaZmze8bVpNObpeQhTjgYt@_uS4euo5
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>> zkg`3S_mcm0^X`&bSW9EfmDFY#FZRjFx-yKvoPL<4h^9?_8gm8b6n;l7_Aw_ZgGCVC
>> z2lNb`hF48owIbcL!Dj;gf+z%4DLkl7++cvK@i4z>AYyk_FT}$OaLu(^+2f#(1mW_b
>> zlEXDby0F3jigou-Btv4k*f=+EB4wAxS+TZa=hkG=g^K)Zlp!h~vagcuW$OHrk|V;)
>> zuvn2X7uweQPE6mWSzEDdE0Jh1BldN5ZM5(0ntm#w`&+DXl4A((d{N^>2|Bw5ds$Fv
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>> zh?N0(!H#-O2H!<kfz#RNu|HOq-?0~K(2X`4s4qW^6WI;qVc|W|JLUNfSq&XsJLFac
>> z|M$yH#Z6Y#xvm|=&uDDT%eE<;!RCgIWdK&j<o_4>`+zz@WWkjDKY`7$j!WRPCSg6`
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>> z?0sliGB^c)?Fy4F!M%*T?RAVV!T8DG;`rGEC^3G&$=FV0ADPf<#qpJ}23hMHs)ICi
>> z!%)=>pRsnhdLBmy=W+A7U;8Mp+DFz?n!pmYbUoy$Kfyex?8KZs`+iOXc@Zrm_hrBo
>> zBiL~={vq6tq*IXTxJeuF#3J8HU`8zo=UDz@4l`t_L<UB5p^$>FoXN4U47ezy+7H53
>> zg^Zc`{sPRZ<M6+x(lh-9dNS@3Boo6=jy_pDyLfW!?K@@G_kpZXy#24+u?BG{J5{UW
>> zR>QWR9<Z9YiQzM&F-56QBwNkg7WiDdR#NGT!HS(f>{x<+O2C(*f(7VLcn!Zq)+(?8
>> zOC9?gWO6@aso9GoI0=M*FR|LK$-nxtL&RSM@`)A*PIgMkSNDqXpM8S=?4saOZSqCI
>> z%LTZd@Y}sLwhQvAINpFchG^{wznTkQ#+j#y#+Pc4u9k5$_R>}HR;D2dUcVE=zZerE
>> z3IWw=dXl9c10L>T<fn0-ijDA5O5oDe7Jpwy8D46gB8Jy>{ipaBW4mjt;1!yj0{vPd
>> z(B(+av+^Wf3-q})yi!32J<!v>CN!AjKsu+4ko<w86gfqnoLa9Yzkm&~QBnM@DB4N9
>> z2L{?0=bCF?mUX@jd=Y|tK=4I~&)$}#Eh`@Gf4gq4l^KenH`=I%J7X4s@`$+~I^F_G
>> zf(~{hvJlG>qy&OT!t%G+c=$?oU2n1Dufl)KG<ale!`pRV02_>;pL~tA<{Y3Ue0LWu
>> zfrf`@vN8&23E$Oy@xP%Z*uj%;EVw!LvY_KCtOToX+4#TyMx7w`&f%sPOMsg2<q*So
>> z3*IiqKiv8b#sw9d<iA>{&|_?uT&;>R7|Tn`n^P#=#4tC~D5RQN${#QocQy*MO)c1`
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>> z$f>3D|E<Zki@Za=D1$^Fd6ooR!_BezLJqVMPT@t>5+CRkm6rrMrJ{5-NP+KKjwF)@
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>> zM#hK;YyDbk3dhzSYW-<q#XLm?HGIl00(bF_{cUT5K+PuWl{f7Hfica9>2FI`c-y2-
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>> zf}E%Uc#M=+CaGmHSHn)($-L%-Oz&-uuBTpIAN*Kzyh1%^RbUWhKGwJks3E!J3F~_m
>> z@H28qhD7qmfpjBxe=TSoYpx|^5Zs%%4qpK|5*}0L|40*Gx8~aVWo?>xF_HbmM~jcj
>> z+=ngNfb{4?E2g7fjiX~IVTUF_@=N@^E7So(HE914_|LI!dZAhK2=`(+T4}l{{4Pw*
>> zf2U0c<)x!O*8HV{$xTkgm_OQLIdPGBgF0$Yd<5$rNYPE>WB&o&8uSpgTN1q*8fY7l
>> zD>_>m?9u?K0yzrq=6F{#-A-vE`q!xNd`f4~0f)7GB?AuB4@6q>b;e*dK{v#3aUFi>
>> zPie#<5JB4AE2NhDgc!$R>leda8DZ`aYv4G3ZExn@vb(w<dJP-MtSqY}nxXCZit~V(
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>> z9RGEn_HORgTt@I0ICo;)Zty{NK+$dke--lDNNt&1BIX_X#N^nUw_ER~-5z`4&N9e8
>> z2SAaR08huYvJmy&94ns?gX1A>SPCiGqB}%Vgt2T=oldM3q0jIPO4VLseI#q6?e>`X
>> z4#RzpC)S#(tjV>H<b0{AfdsLp>U<rg%ZJqBd=+gVvt;B8X==%g1bhLgwIX}r^h~bC
>> zIt5$~M#%L~w}YQmYC0Q<^bWdI%MA@9uh4X=;U96(oPSNpCYeQCqMx)U8RMbC$P7-7
>> zwNBP{5DhS~0nEDtoEFqZO`|drI)N+(Nd?3W{Lf!kK}xsy^dVclu!!Iis}F4>wGa#!
>> zFF2MLRTvXlgbI*U8uXwceC8B<Yu%bDSOL^yrkMrgzL(e53wu<DEeATCLM!DI+EnTS
>> zls7eY(p)QKD2FWSi{y=eHd#UXMcV)hv7zGvC<fM_dKIsP_7zXi*9c8o$hgkY(5x1g
>> z!h*#1vMs?!?5dhps=~Gl=xxrtL&g8LzswqMoaYz!s*FZ|Zf}%vSwIrh8KeC3jMMyy
>> z#@s+OzSu<}Mb{vm*Td+i-o5fmXZO(h*t=J8Qf-e+FS~oSUYgi*%}QrZ#me-&pw-0#
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>> zSc#;j1~?u>QlsJ@fTYGTt^-9}GtyN~{HiEO=*Ph?5u64pUDnBH?QODijMa4dg78#!
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>> zU;YaC03evYtdn<CTND?)j7C!pzdz6dtqFEkrgIt~Mv(I-GE|pJGIaf`GiLh5m!ugp
>> z2V@yZgUd7GgKIOU`ZWVvm#`Ue!SflSOCM##^fxbojYrTodSJiI&t4+_$<hEDd~39B
>> zC!N9c?%=25-3Uz~+vl}JmqkW5N%afI7i_G9&DQl{_+d%>h1VCU<Vl4V^AL@@M0b-9
>> zGzJ!!d2HZ(X>UcBynH1K`4c%O7DtgfYxYF)NRd8Jq2^7oux-UV-OH<~=o;?2oA>it
>> zoC86H9PLPx?Q8Z0(0i+1S!a$LDP9}nXGV(Gw~g8#m-yR8yB-$@G%3V~G140H22nOO
>> z=EO900CZ6n-_hZ&OzfcGwK<2X=wL?7<*lRU{Yrm1xN%XIrlQc-6k_OmZzO|8iqt{s
>> z`_fwIqidnb+EtIZL&?6)@Z|))4=6M8=oQ5(-n{F4Ta>>oWZ%yO;O)9w9Bd0w`{xGE
>> zx8=jW84~AR>imzGFkXS$5;-Dl4K)(fk~E5K9koAzk|XvURj_rG3ZGLs3Y?q6=jI#{
>> z&h7JMVf@OdV)A4n4<@#HVsLLVF(k?6C$03tCyRe$eNXe7VwLZJjm|x=Eg(SU-l4Sp
>> z#Y*hBp0pvyHd%+<_PMpnR;Q`jW-GJ#q=h};8P0E&6rSHo51nT>A=b>MVmIQpc*6c?
>> z2j6>%dgP;*pl9D$MtbXIN?PRIDqVeXt0;#;{>_laZZ7s%>oo3S^hoEu{HuZB;Iuqg
>> zn=x=z!uGJ>b1CDjfDS9h$hpD)wuI@)N2<<WBGq>%VEpL)j5~n`c3%2S|98-2)KpT&
>> z>45~E5l#1#b0x;3m?9P#<o(HB6yC$)4CjjQek%4F*g@{#r-!d4*h9vMH50*<iAH1r
>> z7Z(t|0^&l`3Kg^iUzyx1VggsKEf!heSfv;G<5uv6OSybdJ=g72D>dgI@VpXggwtlA
>> zcTM4DKqK@&x5S|`#$h>T-FNY~bz(%dIbwPK;^xFHKRIdK9oSHD(pVmFR<OpW1O5ss
>> zy)+P4NoAA<HsB441A$tZ!VDyp>_T~4m1T3_w;>t(lVrxv;3x~uyN8ZT5k$or>kD<;
>> z=dSKc3P%#4GgtI(u3$4Qfz7pXio9!#zM<`>nfLW2RT3%Loy?5Drb<tx<r=O3Xt)b#
>> zfn9MQ4O7~WhV8R)p8AZBou>)B>pRtP#`mX=KX<eX+ls#l(GpOvS?Zuu9M^5{sPwIu
>> zM0fwp_jtzvSR|q~oCNYS5#(n~a8`KECtmq7Y#MAtYZTr(U#Xp(jI6bQmkr%9(ZISm
>> z*_+2gF_Jdn!Nv#pzYNfe>2xV9k96Dv{AU9yU)75A&MNLiD3g5yv4id}j;wuw`JA=g
>> z+9!=I+Sqv_lp+VB1Y3wRy*$bXj#>UN5c~|k?3c>BGl&!?6ian!mKC>74D;k0-K)h+
>> z(P4X-I_sf2nQ?32^Ism?D@orNATn4l1v>!IUo=18`_MkseA&KPdmju?%tCp(h8=p5
>> zwL?2o5CDF-y<`tCal8Juhss>ycUY_IWSNTtpZroXcR}EVy%gSy*se>4UJyUCS2fQV
>> zfYjOX%$_yZ<hF&PhYMa66pmyOt}@nKlUW}w$VW;Pcv0n?l7fc|1`^+}#P=nclCs9f
>> zmff^>h+spg<HpAp+`Oj~C-0)d>hYc|AR-Z<DAQ?mVSOuQo$`9DBd#$1A*n-aje1q)
>> zP!-A@P1Yx@3P+4X+DtjH4$~%hm5sC`>Op9q9jrs_#LCbR$HktEZY)Avgt%7BB%N;~
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>> z^uT5a{L5FSE#gJp#Jgk5E9{6l|JbPc!Al{E%^y;-F`yDP>_%&1umTZ92rm(Ln<caw
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>> zeYO7s6ti0|!FJ*F*KK7pV&;Z*Z7ZqSmyHtGEyv82_Rc8Gz<Ou;h=@EfRUS+ZUr!mK
>> z(i1wxsTAy6snnn}t!KrE{Xg!@{{~u}436W=uE=}^pgM0!H9Z+vA8m#3{Wehj>2z`~
>> z>nz}9B8cNJlU!!ey;2_zl54F<Oa6_{lV7|<eTr@I>1Ylj)ApK5k+tM(H#mc&J(hMd
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>> z^<RrvE0q2Kavl);vk#y&WC3J7pC@@!%t_`afKJ5?ZcLG{V)f%=vhj@_IhAtgfO>?r
>> zv<@ED%P_k5yiL3cURr!r!Sq_R6MCxzveMg1M?-S746Bf56N>f{O<+t`CO4ZG-O<6D
>> zcs4%)%d<rO7gvBcEhU;WBY*vDIgq8Jfd~Iow##yVz+g@K6_vTvPu>j}0RBc{UUpu`
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>> z{qY-;wl0a60?Cgd=!ocvFMCNmi+PA=L2^;X@BQWH1k8)Xx_Rydv3PO{OH5MWcBgYj
>> zK4Bu=*CQ;ajr>1urfOtCBl>?iWO6;iBlLPcaAmoMNSF28eSFm=dmFxESVn@mV%@J>
>> z;TK_udX-pt4+>8-DV<(!I%2=MxP?Gm5Y7H4wO&|2wfdGoXPweDh2J(vqB*ggw*60c
>> zxrga~<Xe=@c{J<Mx*#WSNJYtJ{pJEyY3+~YR@^OTM&C4NOSmlsLC#wmL)MludO=iZ
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>> zB&hb0dcCD`r!p9+6S{)57WC-7S_TIsKb|uK-~w4~1i=Gq<6?V&%c)ED$uJ*p;6y-o
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>> z+)+A+?t2sN|71YvrLdNed8Lc`q=<_lI|0lqQIE!RG9*%nvNa6@g3^@ilzEc94A$w0
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>> zYk_1{3j~a4hc(9bac!$0>S7y3b*-SOtpd{|YAmRWF*%AIupW(B?5O%yXrjf9L?cv-
>> zx62#M-Umr(=(#Aimgt5u+k1uMx(kS-!+M&87adK)D_RlGYMYt_hgOWUgI!HRgElVM
>> zR+-%q$wBTN?2-k;B_g>aIe~ieAY}4VVEKw5?_G?q0%;*+*edveGT!*$ABFqX`jI=9
>> zHP`Yo=qw_|`7Kgb-U#m0^Fc-qoGI`;u%393I(aA{V!BV*3dN$HHP@I#l2;W3LJR9{
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>> zKHS}owMIgx#xTQ>47~wCB*(m?C#CX$zE;N1ywYOxisd~mFCP~yrXlPLOa@2-sSO4@
>> zdEyFFiSK><Me^RvqHl#KXtkhF5i7KO&H}yrNt@KG&TrY)UTN(3Mkve~_IdaAN|SqB
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>> z&QW*NDgh=THR~N{&t1i?y7$^-CRdfJHcgNz*J3YGI<OZh{n#@~Rb9G$eVvReh4me@
>> z<C8Iq?QN_AdK~RZL(9&govgvQi!wCZ%XYQwitrPsgd7E#&jGlo&A%p@^~0{;15p;^
>> zKK~Fn_G#RI)~$l|-@nV8+l?=@N-)!j92j>pQQuk#(|xRhHs04)$en_J7>zg#u8y3D
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>> zPnEKT;9%iq7m8ttCaBpOv+P(^OI^(3n4D(d=EvxTu?KIb*8Z+~4&q}F?q-gEk2Mpv
>> zGWln}5gy4N@Exj4Qow@Ckldyoy|YH`SL&^tFqVD$9Yo4VpDD^YR@GE&<CLf;{q~w`
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>> zvN3@?Xg9>c!W*Zk8btTa1Io>@{cmk6;rFx0o<C+Yal}IG*tS*hXCX28?)uW#5MF!n
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>> zA>~pyC7PeSLsAwY<swqZA3i@^Di<mL3D49V96!aKwe&{*s{xXCK2px%&O97Du19za
>> zVg+TywePwy-0pX;XNHd_u4jag?_5t0AK$ueEY;W&`HPd)&{L;|(~h7nJ<2+9)ZzGR
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>> z_lW0}5lPa9B;Nk`v270o2AKQ0n?YsnjEQeA4jwy%Cm5Qo??R`f;$P~eq=uf|GX~md
>> zV@&Tkq_HFR^$l%F1n+VK$wSgeFOpJ>o?wPXhi1{_jxZK8aa0g%8CcF8#t~8?J(JyR
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>> zb!^Y~;j@-1a0I4gx$(uD@Q!(Iv9<c2Na0Mz>hg1@)AbnfN_a$1j`@I+OjhvhNfKG@
>> zae=I@5AFH9^qxeNf(&#&q;-1!w;vL%ew}R=f2RMKExGopU4`g1)_6*PXyXQ-tJ2(|
>> z*@HO1`?MVw5wpuF)L~^J%GPGWD-AL~B8_wiyCEe;jI~Z;Ll1cyr2w)s%@>QFh|3WY
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>> z(w-<EmHE7%$_5=Lx<kx&xmtpksN(;0%LEzO^j}ePw?LM5bX=rL<Bx~msTBPFv$+JP
>> zG-;QCzlO1w#y3xpxv(ig!#_Nr<)-tmUIN;UcXNs;v#6KOp#v=5%20X~`f;*;-8>$t
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>> z;a{k8bMdz9Vtw#j<zR;hwTNPq0_Q3}>A=0LWLr-02`(Wh9krHAOj+Q~M-g`wJ`i#R
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>> zLlT+P=_1@^`*GdQ{9?^E4IOG#^Z+a5Bpf>73)<Bq90;bE;(Vf^Piaw>s9t)4afs^+
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>> zVhlKhXR`++bk8!r;Zh^c6XDwlD_PzczVb+-fnh}W!nLM+(E3zh!H`^pvpawzIVX|l
>> z$Y_bb8M$K)-yw8+zG=6wQTRpn7T;A{`*<p>mJZ;GAn^em-8qAoUV*=hNY?Jhn$c^O
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>> z#Lb@w2XvnZwL3o%UXFvl(<wR;Dfj!qd`^r=KG~?Rc~FdKKjisLJ=?I3UkLg~YNfE2
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>> zDmbY}D=C%vqajKO|5wU9q=elsX?Zv%la^TUmY?35!uaXb*UiYEihFBC*Tj+}-)}6j
>> z{yF(f@JV0VHIe8~!dGV8Gv@+HjD`PsIpPAnai%=tkGOIgJlF*-K?PQHC~Oz3J=XVa
>> z8PnrO>^t=Mq8Ds`1oBHl=LJxO3y40v6g<V}x0)egDF#y3_}Hn5h=ww<{>%9{zZQ71
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>> zWrgH!F3cD!5!JAh%p8SSI}(aT-iG+!r}C51OrIeiZ)o}-v`G>qF-qRFkT;$ZnA1U?
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>> zR7lsw@bRgzh=LIb{NE>uH@|>bDwV!nzQWR|(({@xx5=LV@~QKh!l#ophn`Sz30Z}h
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>> z=$ZV<Fpk>;BOCvqhumN*O>(LDeUtk^i)QjKjvGsNwrOnFV-27eYbSJE6=${1<c|t*
>> zSIMX;gcs~%&~cfs$JB`Qh2gJIebXa|w1YsDS&TpCufWHn(kWi3&VV$%&}#w>$bk=X
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>> zoshEX$CUIeGxx@-8^arJq<4U8fmi=Bet*9l7Ly*N7T#F=W2(Ks3aEe)t~qC4^4Y}D
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>> zzZnr37*;Lidj75cZ(;fVt<aUlTQ6!pgWLqZ!np2+M<ls!!u4@nf1LH1aLPhbj+;Ic
>> zF6DhD^kVDAwh@~j+gEuXJhA+V&xFr${xP;LY`x~sga`9K6F$KC8EmKWZf#q>?K7bj
>> z=fA_&oVTwS@s>tP-c2y+xI+Dn;lm@IU`AFgHM6*uG7`(1^0HqMpKLw<Afgwp8F^&a
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>> zz=MtTYM_5bU$T`+zKIbE?0`E5T*%XP`m!0k<sviTXEDLGYBAQT%h8MIz2fe#SAjju
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>> zic#RZ$X^y>f23_1v^<Ijk423lMMNdWa0o@wAzngFIz=w9tVaHj087vDB=NoVXp#HJ
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>> zIbkY7a+(FHR>I*}X*#^J3Y3w5Uq+^#dVoqOwG7yM*G{5RS;%{m{=uz)e0V08?#ysJ
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>> z@4FPV1;4tD+BM?fFf2AS(g+Qu@Z#?J&)_?DLdI;|b__PD>PP5V{cEZop3n8Ji8!dS
>> zk8y?Ab+z$_LK{d^PB=6axG3I%zW)Q>hyz1`zQLJz1Jc#b3GW#x^UZrkIv)7Z@ejr0
>> z9~wIZo#k=)i|rAIsojPHw}(~7^MDVT%EmjgIcArNKMmh1Mb0rvCEj?*+$X)C35yx3
>> zDbs*>4-4^ctl<}6Ocmi8jnlxtIP$PR!SNm9{*{TbKJpkfOUF<aUv>o_-eE=$%V!fD
>> zEBNw`LU%&*EdJvQ6c4U3uHcpA`Nf$H7a~OVkg04QNA*zhKS3>Ou!8+7e3kKzD);}b
>> z4w4_$A!8(=nZC!jHN<0`#h<BBBd_zLd{_6WtH^~_5$_lYSMscKlsg3M#%s<y24gI%
>> zJ@|H(B}U@wqjgX)N`Yb%pyz-K306v9HvA96frp2H(8Vav#{T2OO8Ad5eF<ornaB<F
>> zt;HpsD!%P<e$S=*Z@ZlDzhnmD7@A)hy=l{h;Qk7J7#JODkLA4WN2M=ZY7pDTd?6e$
>> zdt|#H9h-2W(EgiZP>XEDvkeDohhX{m064ut^w^@X29FS%|M9)A-(_WIH^p=n#k<zI
>> zXCT6Dj*)(!##Zh>CoI1AYq4?KkIEOId}#B0jv276>+WMi)Xg)=TM%+HkUT<t1?{AV
>> zlrCoy*Lm;vu>%I`V+Vj*JYxtx;fx{PmE?{si*=v1`qr^&zEU<t4%xY71v~d}%$L}b
>> zyvz1djCZa6tk5xvO*@7E_pe!oYnGLw{P^eH_sbj+%N#+OIMIXJg>^_*3Cc_bju6^U
>> zu)iM@>vBwdez08ZI`9dW#=BO#Q_%)9#eP52C_@V@5cd}t<B{Kp;lF{F;VM5=^3|27
>> zf$HV+{@2_6&o`nsi2q-2;KEx|^ro}=tTp%+JFomdo+|1w`>PT}o&UY6y_HNd^1D<~
>> zE$k)lTvlS$%kb}25zEm1Hqb^=J82`EFDsq$M3axa#$bro&UQmq=qndfe0=qqO^d77
>> zM5nX8r`TMvRoL|0qI1GNBd`IF(wEw2r1yOR9*R4GL7)ep!?W1QslEhPh#P$79^!hL
>> zrN8dJN>P#eF%n&SytCCk>XqLke_@j_9>F21^T9H!+{?wt$ruS`qnj^k?izm8-8Eou
>> zL)<9x+(q+qyO{|o+(GVP)LDU+$*fW)E)z$~Kg7}EWd7dnl7`(IF?V}@7%{70aV7ci
>> zeizA|c5i~qRk<2@9L8JThV^Q@^$FzeV_~_7;->IZdl31KeLbIZA>I-4BRhr%aU>+;
>> z77&~N#xvNb->|~w(0+o8B0rm@@1y?NTs%MfBD6EejeppFam|Bhzw~?kuMs`6vGjsJ
>> z#uc}zQ<>HN>h}`%e($ILaj$2h$90ub|A71fP9@kgJH(#Z@uQx(3guRnk}dE!O2zLD
>> zmitgF_o0ElQB_rP8Es#w>a{vi+FAP2<@<7g`psOgvl6_|zBp)cGrS?q(k)%ejP?ir
>> zSKWej`Pu)Ey1a;f|9`8=oT?<`cxL$Ys_uI=nQ}SIiO8C%vF^Ru(yk-InyJ6YP6M7K
>> z_!eiD9fqVivy7hnu=kwMBED4%-o8d0hgss-%Q8k@J|{dR?muJ<y^MQfR69$UiQtg>
>> z`(lP>gJ@%nOR`(KTeh2>FowU-VfMqCIDwv$!gZCglhD@1fBYLeaWpprF-x(CQc1v`
>> z6FvuIFr7Gq`{HlNf;K7Kp8zWhJL$$Xuyu3Qzy>_d`TWzkKO$1<31mnkBvKBvSo5?b
>> zx6&mC0~d{sm+lY`(<9z^v~?cl)<Gb}_F~Sf=0vVJQ5TT`*Anr;aNu(R_!7MeqgK<g
>> zGI#kJ8JNl1gxSU@HF1nYhDc#MdSdDkp=dnQ#2BSb6f?;-AhH9j$HBQX7ZIGQeFlEq
>> zy&3oaJ=5*LoN<4){T!B5Fi;rp1pYdVXyScT;|IJn_Q<Apy_<!V%E0fw5ZX-4TdE}1
>> zTZ`CM`YtkWLUV9dT-p)u_yRLwH=<uL${+>mJ+WIhyJI((i!z`=ran&$d8@&A3;QaU
>> z0nH$T|5x``_x<O5+zmSy^oC8c6}+lTjTwXm^TCWEdX5^oshJQ+{UbkKMHh18M1Aaj
>> zS;J8OH70fIfc5bDzqSjT#2AT9X~A!pdhMLBM(jar3~}g(TL-Rx^pC$WBIj)Ys1p^K
>> z0e!;lB4F_<Mk8j2BBu_+Do@yi$~TdH^P(9si^2W5m-OEs-+#%>#qmcv+SaMTino+s
>> zS^(yQcEplG0|&;@wAsxfS0#{%`X;o%d0>E+StXNYz9ws=8<A}puvx<!3{?D0>+^(^
>> zDY^~*CDYHqBS=Vl;MtmTv0ehx1ifiiE-!B;ty96(wV*{*h<66wQH3l}3~#AAB<d+s
>> zs**$tj~Oe>^`@jP?ZR!~aRyqTPh#}_*#^y4NozzzVe?~zDh_-Qf%C!z%jwv*n~S%~
>> z&av>oU0@W%hhkJTT`kXa@5Cz3<W?a6pJ_dtVOqOWSc6Qd<VT9~W?;N^3R5iSVl_#j
>> zou$tvd5#YzTB7>WBaWRYeX8_X^6P4N;m$ji%;bfL5l-269{kn2gcnc4OR#b2_4-88
>> zzdsr7A3A~vc<HcO%=abnesFVhC8EKvuT(D`7}_WuX5R^BpYZg~kI;2QZO(Hq-;{~G
>> z?>7Uv!xXp5VkH^Txf9V2d7c);5qzm#dOcU7;dg;`e;bbOuOzJ5@|?VdlCxx4t;Z2L
>> zFgrWZ(ow)VMDRt}SBQNd5z07v$Sv>dP%i<(bDL1NZzk6tST;z%3bFUlAeih8v$-UU
>> zH)h}Mz-z<rR+_BNY^p(>r4;v@%vpdpnTdWPSXNu(#3Lht-`y=Ok8>-W8aJC+TC%@9
>> z1l#>3e-aK%T@LnUYg&lgh4F#jq8){HOXr!Mq%FOk;Jst$-lCr}TEtZ;`RDGkljuni
>> z#yqUAZ4$D?Q5+~@+8ajm){Cfjh0+;i-RRk0X|&q2H67`gm(%n{s+GRLDotd)Y{vc#
>> zJAvY@ar@Vs5SO6#w+U9Q!OhO9Yu!(K$kDCIs7A(Ig`XJOk0E2})`8O>A-gkLG2b$9
>> zEyx~CwrGl_^<tF@uR-w`exQS*GPC%4n`w&)@3b>xH7t}hw%0rvTbZO6ARQ+I=`*+M
>> zr~Y>;(>y5SHf<(+<O*Q>D6{1_{=Y;N=X+hO`0Hmq9f&NC1CF!EOOc+B;|}rs<O^mG
>> z9k&Z}vA$UD{TQ5}OiJ{L>WPwxdG1MD79rm4Q{Z!F3@M3IZxY5OFt$503gNk6lEL{k
>> zsTp3j4tV-Rj;Bd_w}E>MaR*;0qtCyMJ6qFmy~Kp?66H=6@1TUma-=m2qZ8=;JyGE2
>> z*FmDC!J7F6@=Xwua&H&Cn}`vgKbqGzQ<lE<mW@UC>;E&~o7cp%RTW3GZY)KtYS^<O
>> zPi?PMKnAS_8d#R5;$k+BAn%-Ma~$r?8pa^kUj`7c@WMU&cvhk^{Ct%EPl63&e*$b*
>> zab+eq^#dcf2y0Jv8de(<GBAsN3eQ?^H{jwT1~HHm&NY^g<}}E;HjZnk>@I_)-nMse
>> zN<&=j-#vfdnx%|A51vrQre)2@nxu~6H4!0RtzTkR`3e<^_OlqLkzh7d`eKoBhkUT`
>> zi0sz#C%cIWJ*0gdGEK~a%+4$t3Osd(T3|N5Vd^DWO6ZAC#C!@AU#Rq6Eu%;lDcCz4
>> zwM!N_Y{aYJ%$9ofWd{s1V7n_VgOx~_2$s}rWKp0zogpH>p$b=qPKQ5N(N+uo1NHmx
>> zO%aAaxVEVP%9ojF6HFy`VV*_CwP7Z<rte+(iu;4gGFVzyyOSy@pTtPu;9Zgy<9OjB
>> zNrt~nlTFvB{M|=-Us&hWGMllvoG}daXZEuOnu{X&O~AoU=No}d-6UfSk$eSyGlpsW
>> zVyqRXvI>3+Y}lBYrUqj~G;h;aYy`qN&Lb_~TlRn_wTwwE^6s~mS?A^+5yEY8wVEsy
>> zILs+8X1Y7wTCgtGJu^2F_(O_8{AI}=Fj07u;HS}sc=sXB_GFUMo1et`GPlIJ_k(!^
>> z(XhpA(_UeUKFr0WGj@vP2nD{)0BhWW&QB^Q=EWi=f;>5q?YrQ~*(`c;LeEFx2|xI9
>> zsJxn=bGO+&-j6dD^?!JCEa*#vf!9a$=vPbNGru&52z6rxqUvu2p1VtZ>%JE!sVwt*
>> zj&+IX(Yaeg@rgj&W_*S1E#y%Bv43al(P*v-@jFqKVH{xvWa)bT+-)g0)7^k|0a;L0
>> zgyM#Dft^dw?4m3xp(jRhp@w(2N*j&DiHbPjcmE5sWE0R-cnjphoPfN0$m&K+Pa_sa
>> zPw{5LQH40CKftZxQ@gKL$~j3=l&`p~4t{pBpDEfit(aL#EZnLbWLp`b@l#SZ68II+
>> zG^ND?#SAQElG<97_E2yOXiRFm(lxp)tj~<Rs(KSRcz;z(ya5I?tlSDa<Y`eDB02{8
>> z$K9Y~Gr58OSnP!w^RYMjM#ehPHVT`Y!r5Q`d!eNvc~2O8%!H#9Y{y`O>;Uq?P@eaS
>> z-K}{x<iLtFP1B7)%v~|pm5eYGWb4c2mh-<w&d+GO${!8u28}UQ-%N?-Py)Zas~@>T
>> zCL(5BXB_Ci(AQs{v~!|8W8EbCGkKHoXU1Qmed3|9zk+QM^;6jg`oHee9AXSAqu!o+
>> zAo`F2UbIauzX!kSK>w$GgsgxySf74~SWR^&x`D04N?D;h0ev%DDujX+O5s$wEPEF4
>> zH+$4B1^C^hnzTa_)G8a+vr|&Ut;l2fuez0-1u|?FhZszQg^%g9i8kwOpmM)#h~^_M
>> zet^tC8{hZ<R<SgfEF%r=9Oa?>A5nfq-*_N-1_CQbw4Su)CBV6-HDgW&yTpya_B&~=
>> zgMAu}0#~G>Ez(?6JF;3*tw;-AfV}QioY_qXY8LTUk$1BFX)dM#3|$RUvF#qiyotGT
>> z-)R19SH(J=`&Quhw|^r{ZBW9~ljb7)rXn*9cLu6gBg3B3l@Gku9Luf1$G0m=Ri2ho
>> zxj)TOz}*Nexbquf=DuUd2G8sQmMn?|UxdUiwIc=)8tr=%RzvRa$aSnb!C(d=uJH^}
>> zb7fAbe_zGK;BOZGsLx5QueSsx*l%FFZ4tN?5`P50uT##MD8kr8mSJgMyrvCv{W;9F
>> z5@eT&<x4KeMZ3QKNtI~VS5j2}lhG$Mrf9^0?}IjKHZhY%j8Z#!<S=p?m_2coh2R%m
>> zhF+C}IqQp|Oi^O%%ck)@VC%JfOZQI<B>A4`B!1^C=6Lp(!flD7OJCM%n9eWn%woP2
>> z7%8EA?hfx1wCNN_@es~%ohQ}EJuab{@TG3jQuUaZ9=@;$>nTEl<SgheryP$T8jm6W
>> z&LrfqWh3HG7<iV=#xHFlFjh0rt5sw(JZ5=2`!C%LW^B@Pl{T6|<lZdIE6;XhA>JYP
>> zqHKmf_1}=*@H+4{oiCtu;9oZx_|gtARvHn5vXNLzV-b7#X-PHCBBs2<RE~3zWN-fo
>> zY+pwH--5|H|HeA@9I<b&14Fg1d)<N?Y3cTC6Yvy8*v5NvZ+#hQ&(>k9Fxs=Dal8P>
>> zqfaQ|5eoOuzwwv(_1RHAS2@tr1$JckMlMloH9p8hBUT`OxsmuZ)-8$Sy`3~amn}&|
>> z--zSCM(fT5Zs&ub_f6lZR3Y;Eh4F2WQb3Zu#=>W?1PHP)z8WP~ulvURu~0jmnc!;8
>> z0rKH}><5u7%iMG}lQ1lz6qTS&h{x)F)I}6u0HjaLsA7!81U|P@F8fkwSw{Ga1U{$J
>> zoP%F%1ZF&%(H_QnFqS`vRYxeFd?6SQaywwWOY7Mb;i@$=mzlUtm|8S}J1tx=0i}8~
>> zYeNFB?>s8ZPLEZBi4m(+Vy}+M`6Z6f(I}pepyND_^FKa5Q1Me7AE+p01}aK^C?6Z5
>> z^2N#Z1Fsgvh3WZmjE?RkkxZ9NQ>FaICnAvs3$)>U>?OikNHHf;)R_r6tV+OjkqVuN
>> zwA1Gi>8O$?@}r@TMe;uf?uXi{aHY;&QyJn(<wsqh))~O+jIdBE`O}x^s>GSWY|6}u
>> z|3-}PKwd3l+ubaV&F$PMWK)jjx&<&rHiF+&741+rb=QYm<ql%@`J%sy4YK>Nla<`)
>> zy$ZXsQPLxsT<UwsFL%OIy;TV`e?DwF<-q&D7x9=c1DO785f*P4F#Fnw$GlQ(nTX}y
>> zm6u7+UW(F|2o=h_7cmz2gkya>k;R&#0J8WcRarQGGGZ=%d+~dI6^(%iejYF)S^Vs(
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>> zbFPuUJ!O$s4d&;_<5FPAC7U&E^fr3bep^I>_znr+-TB;7TyLyjnbiW_byb!orv<p~
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>> zB#Yl+qxOBn7R0UB+q#sp_9w+J!SJw-fm{BC^JB&GE5VAMS*~!bwmP!QeR3!9>_aMV
>> zmH1>>M}_*qBqQ!?R0_Y+Me*mTp^D@sz7@W~{Vx^#3X6pMUqS84bW8hANvNlU_@sTG
>> zs#Jbs0{vofXN~I5@Y1R6;hxO$UzBMe>(!2Q#Nf=Nm8wm$D}jIG5`+0)?Z9ep7u#gv
>> zb=`4(%2YJLXRJI6>y1ts^?kj=eQ9MgITkn!pfoV21F1n@RjO{JJDs?c8Po)S3j6po
>> z3P?4Xe>7SXkr)1lxoD@E8&ed_f{mGNk&Jt<r2$qoZ~#nx7Ixc0;G)aC@?S-Kl!28(
>> zSl?RYsvqhk?PM|6-~aMW#Bdp&%1{{%2V$U^SZzCm_50%YB<$|*e-_dIzZYs7$Xgu+
>> zgn$xURNqn#jpg@o4dZ{M6hh}t=CZ)lPkI3ZE#=+LWEZ$p>?Y_aHjx)&ij(w|7=Gg=
>> z;3L~i-)j(b6$8(q$_Cx0gER<2>)s0V38Vb<Bx0OWKuVKNmd+LMJHSCgD?pm*seQ-O
>> z+%7WvG`92z>swTfD-n@2j*I<;4CtU&FTuLpP>8kb;X6!<x*@Cox=rO`Q|4}pK7m++
>> zedqz2DA>%j4WYQJ3cWUzFTM*+29ldFSE0NGzhucky>+n3U@T8&y<3wlz$9ykp;W}v
>> zNbH%gWG?}Gp>&UIcQjveQI;(C9qiMCjg9S4Cdc{1`YfTPn1NPu@xXJ$pM)1`kTFp%
>> zH^SqP7Po}UGX}5!y%2penlHGhOnwAXNS3_P%iP#)+vR4HH~60Lha}58G|4uM3{`TO
>> zug*Ujwy4)_Ta%N$qmqk(sHS=RFxKW<yll#I-Vn6%3oHYq6YP8T*{}l|kjLjaKaD3T
>> zEXS+YF-gyOvr|@zafS<VU6Ge!T)@9*$l(y1wL6o4`QlH&mW;W}PMoBfuzh5y2-}_~


^ permalink raw reply

* Re: [WireGuard] [PATCH v3] ip6_output: ensure flow saddr actually belongs to device
From: David Ahern @ 2016-11-14 17:48 UTC (permalink / raw)
  To: Hannes Frederic Sowa, Jason A. Donenfeld, Netdev,
	WireGuard mailing list, LKML, YOSHIFUJI Hideaki
In-Reply-To: <7779da88-08dc-0adb-42dd-8e00502693df@stressinduktion.org>

On 11/14/16 10:33 AM, Hannes Frederic Sowa wrote:
>>>>> I just also quickly read up on the history (sorry was travelling last
>>>>> week) and wonder if you ever saw a user space facing bug or if this is
>>>>> basically some difference you saw while writing out of tree code?
>>>>
>>>> I checked the userspace API this morning. bind and cmsg for example check that the address is valid with calls to ipv6_chk_addr.
>>>
>>> Hmm, so it fixes no real bug.
>>>
>>> Because of translations of flowi6_oif we actually can't do a correct
>>> check of source address for cases like the one I outlined above? Hmm,
>>> maybe we should simply depend on user space checks.
>>
>> I believe Jason's case is forwarding path and the ipv6_stub->ipv6_dst_lookup API.
> 
> It is not a kernel API, because we don't support something like that for
> external kernel modules. We basically exported ipv6_dst_lookup to allow
> some IPv4 code to do ipv6 stunts when the IPv6 module is loaded. ;)

???

ipv6_stub is exported for modules (EXPORT_SYMBOL_GPL(ipv6_stub)).

ipv6_stub->ipv6_dst_lookup is used by several modules -- geneve, tipc, vxlan, mpls -- for IPv6 lookups, not IPv4 code do IPv6 stunts.

So how do you say that is not an exported kernel API?

^ permalink raw reply

* [PATCH v4] btrfs: make block group flags in balance printks human-readable
From: Adam Borowski @ 2016-11-14 17:44 UTC (permalink / raw)
  To: Holger Hoffstätte, David Sterba, linux-btrfs; +Cc: Adam Borowski
In-Reply-To: <20161114163747.GO12522@twin.jikos.cz>

They're not even documented anywhere, letting users with no recourse but
to RTFS.  It's no big burden to output the bitfield as words.

Also, display unknown flags as hex.

Signed-off-by: Adam Borowski <kilobyte@angband.pl>
---
 fs/btrfs/relocation.c | 42 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 39 insertions(+), 3 deletions(-)

diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c
index c4af0cd..9a3abf3 100644
--- a/fs/btrfs/relocation.c
+++ b/fs/btrfs/relocation.c
@@ -4333,6 +4333,44 @@ static struct reloc_control *alloc_reloc_control(struct btrfs_fs_info *fs_info)
 }
 
 /*
+ * printk the block group being relocated
+ */
+static void describe_relocation(struct btrfs_fs_info *fs_info,
+				struct btrfs_block_group_cache *block_group)
+{
+	char buf[128]; /* prefixed by a '|' that'll be dropped */
+	u64 flags = block_group->flags;
+
+	if (!flags) { /* shouldn't happen */
+		strcpy(buf, "|NONE");
+	} else {
+		char *bp = buf;
+
+#define DESCRIBE_FLAG(f, d) \
+		if (flags & BTRFS_BLOCK_GROUP_##f) { \
+			bp += snprintf(bp, buf - bp + sizeof(buf), "|%s", d); \
+			flags &= ~BTRFS_BLOCK_GROUP_##f; \
+		}
+		DESCRIBE_FLAG(DATA,     "data");
+		DESCRIBE_FLAG(SYSTEM,   "system");
+		DESCRIBE_FLAG(METADATA, "metadata");
+		DESCRIBE_FLAG(RAID0,    "raid0");
+		DESCRIBE_FLAG(RAID1,    "raid1");
+		DESCRIBE_FLAG(DUP,      "dup");
+		DESCRIBE_FLAG(RAID10,   "raid10");
+		DESCRIBE_FLAG(RAID5,    "raid5");
+		DESCRIBE_FLAG(RAID6,    "raid6");
+		if (flags)
+			snprintf(buf, buf - bp + sizeof(buf), "|0x%llx", flags);
+#undef DESCRIBE_FLAG
+	}
+
+	btrfs_info(fs_info,
+		   "relocating block group %llu flags %s",
+		   block_group->key.objectid, buf + 1);
+}
+
+/*
  * function to relocate all extents in a block group.
  */
 int btrfs_relocate_block_group(struct btrfs_root *extent_root, u64 group_start)
@@ -4388,9 +4426,7 @@ int btrfs_relocate_block_group(struct btrfs_root *extent_root, u64 group_start)
 		goto out;
 	}
 
-	btrfs_info(extent_root->fs_info,
-		   "relocating block group %llu flags %llu",
-		   rc->block_group->key.objectid, rc->block_group->flags);
+	describe_relocation(extent_root->fs_info, rc->block_group);
 
 	btrfs_wait_block_group_reservations(rc->block_group);
 	btrfs_wait_nocow_writers(rc->block_group);
-- 
2.10.2


^ permalink raw reply related

* Re: Long delays creating a netns after deleting one (possibly RCU related)
From: Cong Wang @ 2016-11-14 17:44 UTC (permalink / raw)
  To: Paul E. McKenney
  Cc: Rolf Neugebauer, LKML, Linux Kernel Network Developers,
	Justin Cormack, Ian Campbell
In-Reply-To: <20161114162417.GJ4127@linux.vnet.ibm.com>

On Mon, Nov 14, 2016 at 8:24 AM, Paul E. McKenney
<paulmck@linux.vnet.ibm.com> wrote:
> On Sun, Nov 13, 2016 at 10:47:01PM -0800, Cong Wang wrote:
>> On Fri, Nov 11, 2016 at 4:55 PM, Cong Wang <xiyou.wangcong@gmail.com> wrote:
>> > On Fri, Nov 11, 2016 at 4:23 PM, Paul E. McKenney
>> > <paulmck@linux.vnet.ibm.com> wrote:
>> >>
>> >> Ah!  This net_mutex is different than RTNL.  Should synchronize_net() be
>> >> modified to check for net_mutex being held in addition to the current
>> >> checks for RTNL being held?
>> >>
>> >
>> > Good point!
>> >
>> > Like commit be3fc413da9eb17cce0991f214ab0, checking
>> > for net_mutex for this case seems to be an optimization, I assume
>> > synchronize_rcu_expedited() and synchronize_rcu() have the same
>> > behavior...
>>
>> Thinking a bit more, I think commit be3fc413da9eb17cce0991f
>> gets wrong on rtnl_is_locked(), the lock could be locked by other
>> process not by the current one, therefore it should be
>> lockdep_rtnl_is_held() which, however, is defined only when LOCKDEP
>> is enabled... Sigh.
>>
>> I don't see any better way than letting callers decide if they want the
>> expedited version or not, but this requires changes of all callers of
>> synchronize_net(). Hm.
>
> I must confess that I don't understand how it would help to use an
> expedited grace period when some other process is holding RTNL.
> In contrast, I do well understand how it helps when the current process
> is holding RTNL.

Yeah, this is exactly my point. And same for ASSERT_RTNL() which checks
rtnl_is_locked(), clearly we need to assert "it is held by the current process"
rather than "it is locked by whatever process".

But given *_is_held() is always defined by LOCKDEP, so we probably need
mutex to provide such a helper directly, mutex->owner is not always defined
either. :-/

^ permalink raw reply

* [PATCH 1/2] drm/i915: Kill dp_encoder_is_mst
From: ville.syrjala @ 2016-11-14 17:44 UTC (permalink / raw)
  To: intel-gfx
In-Reply-To: <1479145447-12907-1-git-send-email-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

dp_encoder_is_mst flag in the crtc state can be replaced by
intel_crtc_has_type(..., INTEL_OUTPUT_DP_MST). Let's do that.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/intel_dp_mst.c  | 1 -
 drivers/gpu/drm/i915/intel_drv.h     | 1 -
 3 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 072a0b1bc9da..5617fb7b2f90 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5496,7 +5496,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (intel_crtc->config->has_pch_encoder)
 		lpt_pch_enable(crtc);
 
-	if (intel_crtc->config->dp_encoder_is_mst)
+	if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
 		intel_ddi_set_vc_payload_alloc(crtc, true);
 
 	assert_vblank_disabled(crtc);
@@ -5619,7 +5619,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_disable_pipe(intel_crtc);
 
-	if (intel_crtc->config->dp_encoder_is_mst)
+	if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
 		intel_ddi_set_vc_payload_alloc(crtc, false);
 
 	if (!transcoder_is_dsi(cpu_transcoder))
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 3ffbd69e4551..b029d1026a28 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -43,7 +43,6 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int mst_pbn;
 
-	pipe_config->dp_encoder_is_mst = true;
 	pipe_config->has_pch_encoder = false;
 	bpp = 24;
 	/*
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 003afb873b67..75252ecaa613 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -652,7 +652,6 @@ struct intel_crtc_state {
 
 	bool double_wide;
 
-	bool dp_encoder_is_mst;
 	int pbn;
 
 	struct intel_crtc_scaler_state scaler_state;
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related

* [PATCH 2/2] drm/i915: Simplify DP port limited color range bit platform checks
From: ville.syrjala @ 2016-11-14 17:44 UTC (permalink / raw)
  To: intel-gfx
In-Reply-To: <1479145447-12907-1-git-send-email-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Instead of checking for everything not supporting the limited color
range bit in the DP port register, let's check for the one thing
that does have it (g4x).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 56431e04c7a9..a1b0181f42c4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1791,9 +1791,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 			trans_dp &= ~TRANS_DP_ENH_FRAMING;
 		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
 	} else {
-		if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
-		    !IS_CHERRYVIEW(dev_priv) &&
-		    pipe_config->limited_color_range)
+		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
 			intel_dp->DP |= DP_COLOR_RANGE_16_235;
 
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -2515,8 +2513,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 
 	pipe_config->base.adjusted_mode.flags |= flags;
 
-	if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
-	    !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
+	if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
 	pipe_config->lane_count =
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related

* [PATCH 0/2] drm/i915: A few DP stragglers
From: ville.syrjala @ 2016-11-14 17:44 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reposting a few trivial DP related stragglers, with Jim's irc r-b
slapped on.

Ville Syrjälä (2):
  drm/i915: Kill dp_encoder_is_mst
  drm/i915: Simplify DP port limited color range bit platform checks

 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/intel_dp.c      | 7 ++-----
 drivers/gpu/drm/i915/intel_dp_mst.c  | 1 -
 drivers/gpu/drm/i915/intel_drv.h     | 1 -
 4 files changed, 4 insertions(+), 9 deletions(-)

-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply

* [PATCH][RFC] ACPI throttling: Save/restore tstate for each CPUs across suspend/resume
From: Chen Yu @ 2016-11-14 17:44 UTC (permalink / raw)
  To: linux-acpi
  Cc: Rui Wang, linux-kernel, Chen Yu, Len Brown, Rafael J. Wysocki,
	Pavel Machek, Matthew Garrett, Rui Zhang, linux-pm

This is a trial version and any comments are appreciated.

Previously a bug was reported that on certain Broadwell
platforms, after resuming from S3, the CPU is running at
an anomalously low speed, due to BIOS has enabled the
throttling across S3. The solution to this is to introduce
a quirk framework to save/restore tstate MSR register
around suspend/resume, in Commit 7a9c2dd08ead ("x86/pm:
Introduce quirk framework to save/restore extra MSR
registers around suspend/resume").

However more and more reports show that other platforms also
experienced the same issue, because some BIOSes would like to
adjust the tstate if he thinks the temperature is too high.
To deal with this situation, the Linux uses a compensation strategy
that, the thermal management leverages thermal_pm_notify() upon resume
to check if the Processors inside the thermal zone should be throttled
or not, thus tstate would be re-evaluated. Unfortunately on these bogus
platforms, none of the Processors are inside any thermal zones due
to BIOS's implementation. Thus tstate for Processors never has a
chance to be brought back to normal.

This patch tries to save/restore tstate on receiving the
PM_SUSPEND_PREPARE and PM_POST_SUSPEND, to be more specific,
the tstate is saved after thermal_pm_notify(PM_SUSPEND_PREPARE)
is called, while it's restored before thermal_pm_notify(PM_POST_SUSPEND),
in this way the thermal zone would adjust the tstate eventually and
also help adjust the tstate for Processors which do not have
thermal zone bound. Thus it does not imapct the old semantics.

Another concern is that, each CPU should take care of the
save/restore operation, thus this patch uses percpu workqueue
to achieve this.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=90041
Reported-by: Matthew Garrett <mjg59@srcf.ucam.org>
Reported-by: Kadir <kadir@colakoglu.nl>
Cc: Len Brown <lenb@kernel.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Matthew Garrett <mjg59@srcf.ucam.org>
Cc: Rui Zhang <rui.zhang@intel.com>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Chen Yu <yu.c.chen@intel.com>
---
 drivers/acpi/processor_throttling.c | 70 +++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c
index d51ca1c..8ddc7d6 100644
--- a/drivers/acpi/processor_throttling.c
+++ b/drivers/acpi/processor_throttling.c
@@ -29,6 +29,7 @@
 #include <linux/sched.h>
 #include <linux/cpufreq.h>
 #include <linux/acpi.h>
+#include <linux/suspend.h>
 #include <acpi/processor.h>
 #include <asm/io.h>
 #include <asm/uaccess.h>
@@ -758,6 +759,75 @@ static int acpi_throttling_wrmsr(u64 value)
 	}
 	return ret;
 }
+
+#ifdef CONFIG_PM_SLEEP
+static DEFINE_PER_CPU(u64, tstate_msr);
+
+static long tstate_pm_fn(void *data)
+{
+	u64 value;
+	bool save = *(bool *)data;
+
+	if (save) {
+		acpi_throttling_rdmsr(&value);
+		this_cpu_write(tstate_msr, value);
+	} else {
+		value = this_cpu_read(tstate_msr);
+		if (value)
+			acpi_throttling_wrmsr(value);
+	}
+	return 0;
+}
+
+static void tstate_check(unsigned long mode, bool suspend)
+{
+	int cpu;
+	bool save;
+
+	if (suspend && mode == PM_SUSPEND_PREPARE)
+		save = true;
+	else if (!suspend && mode == PM_POST_SUSPEND)
+		save = false;
+	else
+		return;
+
+	get_online_cpus();
+	for_each_online_cpu(cpu)
+		work_on_cpu(cpu, tstate_pm_fn, &save);
+	put_online_cpus();
+}
+
+static int tstate_suspend(struct notifier_block *nb,
+				unsigned long mode, void *_unused)
+{
+	tstate_check(mode, true);
+	return 0;
+}
+
+static int tstate_resume(struct notifier_block *nb,
+				unsigned long mode, void *_unused)
+{
+	tstate_check(mode, false);
+	return 0;
+}
+
+static int __init tstate_pm_init(void)
+{
+	/*
+	 * tstate_suspend should save tstate after
+	 * thermal zone's update in thermal_pm_notify,
+	 * vice versa tstate_resume restore tstate before
+	 * thermal_pm_notify, thus the thermal framework
+	 * has a chance to re-adjust tstate according to the
+	 * temperature trend.
+	 */
+	pm_notifier(tstate_suspend, -1);
+	pm_notifier(tstate_resume, 1);
+	return 0;
+}
+
+core_initcall(tstate_pm_init);
+#endif
 #else
 static int acpi_throttling_rdmsr(u64 *value)
 {
-- 
2.7.4


^ permalink raw reply related

* Re: [PATCH v3 6/6] grep: search history of moved submodules
From: Brandon Williams @ 2016-11-14 17:43 UTC (permalink / raw)
  To: Stefan Beller; +Cc: git@vger.kernel.org, Jonathan Tan, Junio C Hamano
In-Reply-To: <CAGZ79kbf2i5s8Y84i2Wehbffsw1dUDUY6LYPEMME3vC6zo8-aw@mail.gmail.com>

On 11/11, Stefan Beller wrote:
> On Fri, Nov 11, 2016 at 3:51 PM, Brandon Williams <bmwill@google.com> wrote:
> 
> > +
> > +       rm -rf parent sub
> 
> This line sounds like a perfect candidate for "test_when_finished"
> at the beginning of the test

K will do.

-- 
Brandon Williams

^ permalink raw reply

* Re: [PATCH] mfd: bcm590xx: Simplify a test
From: Lee Jones @ 2016-11-14 17:40 UTC (permalink / raw)
  To: Christophe JAILLET; +Cc: linux-kernel, kernel-janitors
In-Reply-To: <20161101064905.11961-1-christophe.jaillet@wanadoo.fr>

On Tue, 01 Nov 2016, Christophe JAILLET wrote:

> 'i2c_new_dummy()' does not return an error pointer, so the test can be
> simplified to be more consistent.
> 
> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
> ---
>  drivers/mfd/bcm590xx.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks.

> diff --git a/drivers/mfd/bcm590xx.c b/drivers/mfd/bcm590xx.c
> index 0d76d690176b..c572a35a9341 100644
> --- a/drivers/mfd/bcm590xx.c
> +++ b/drivers/mfd/bcm590xx.c
> @@ -67,7 +67,7 @@ static int bcm590xx_i2c_probe(struct i2c_client *i2c_pri,
>  	/* Secondary I2C slave address is the base address with A(2) asserted */
>  	bcm590xx->i2c_sec = i2c_new_dummy(i2c_pri->adapter,
>  					  i2c_pri->addr | BIT(2));
> -	if (IS_ERR_OR_NULL(bcm590xx->i2c_sec)) {
> +	if (!bcm590xx->i2c_sec) {
>  		dev_err(&i2c_pri->dev, "failed to add secondary I2C device\n");
>  		return -ENODEV;
>  	}

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
--
To unsubscribe from this list: send the line "unsubscribe kernel-janitors" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply

* [distros-debian-sid test] 68032: tolerable FAIL
From: Platform Team regression test user @ 2016-11-14 17:40 UTC (permalink / raw)
  To: xen-devel, osstest-admin

flight 68032 distros-debian-sid real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68032/

Failures :-/ but no regressions.

Regressions which are regarded as allowable (not blocking):
 test-amd64-i386-amd64-sid-netboot-pygrub  9 debian-di-install  fail like 68007
 test-amd64-i386-i386-sid-netboot-pvgrub  9 debian-di-install   fail like 68007
 test-amd64-amd64-i386-sid-netboot-pygrub  9 debian-di-install  fail like 68007
 test-armhf-armhf-armhf-sid-netboot-pygrub  9 debian-di-install fail like 68007
 test-amd64-amd64-amd64-sid-netboot-pvgrub  9 debian-di-install fail like 68007

baseline version:
 flight               68007

jobs:
 build-amd64                                                  pass    
 build-armhf                                                  pass    
 build-i386                                                   pass    
 build-amd64-pvops                                            pass    
 build-armhf-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-amd64-sid-netboot-pvgrub                    fail    
 test-amd64-i386-i386-sid-netboot-pvgrub                      fail    
 test-amd64-i386-amd64-sid-netboot-pygrub                     fail    
 test-armhf-armhf-armhf-sid-netboot-pygrub                    fail    
 test-amd64-amd64-i386-sid-netboot-pygrub                     fail    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.


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^ permalink raw reply

* [Qemu-devel] [RFC 0/2] Clean-up tlb_flush and cpu reset functions
From: Alex Bennée @ 2016-11-14 17:40 UTC (permalink / raw)
  To: rth; +Cc: qemu-devel, Alex Bennée

Hi,

These changes are cleanups for tlb_flush() and associated cpu reset
functions. The first patch fixes up all vCPU reset functions to rely
on the common reset code to issue a tlb_flush. This includes fixing up
functions which blithely memset the TLB structures which upsets tsan
in MTTCG.

The second is a clean-up to drop the long ignored global flag. AFAICT
we have never used it and there already exists more scoped functions
that deal with MMU_IDX and pages for partial clearing of the TLB.

A variant of these patches appeared in my last MTTCG patch set but
this one fixes up all machines and targets. The changes are fairly
mechanical but they span all the architectures.

Alex Bennée (2):
  qom/cpu: move tlb_flush to cpu_common_reset
  cputlb: drop flush_global flag from tlb_flush

 cputlb.c                           | 21 ++++++---------------
 exec.c                             |  4 ++--
 hw/sh4/sh7750.c                    |  2 +-
 include/exec/exec-all.h            | 14 ++++++--------
 qom/cpu.c                          | 10 ++++++++--
 target-alpha/cpu.c                 |  2 +-
 target-alpha/sys_helper.c          |  2 +-
 target-arm/cpu.c                   |  5 ++---
 target-arm/cpu.h                   |  5 ++++-
 target-arm/helper.c                | 26 +++++++++++++-------------
 target-cris/cpu.c                  |  3 +--
 target-cris/cpu.h                  |  9 ++++++---
 target-i386/cpu.c                  |  2 --
 target-i386/cpu.h                  |  6 ++++--
 target-i386/fpu_helper.c           |  2 +-
 target-i386/helper.c               |  8 ++++----
 target-i386/machine.c              |  2 +-
 target-i386/misc_helper.c          |  2 +-
 target-i386/svm_helper.c           |  2 +-
 target-lm32/cpu.c                  |  3 +--
 target-lm32/cpu.h                  |  3 +++
 target-m68k/cpu.c                  |  3 +--
 target-m68k/cpu.h                  |  3 +++
 target-microblaze/cpu.c            |  3 +--
 target-microblaze/cpu.h            |  3 +++
 target-microblaze/mmu.c            |  2 +-
 target-mips/cpu.c                  |  3 +--
 target-mips/cpu.h                  |  5 ++++-
 target-mips/helper.c               |  6 +++---
 target-mips/op_helper.c            |  8 ++++----
 target-moxie/cpu.c                 |  4 +---
 target-moxie/cpu.h                 |  3 +++
 target-openrisc/cpu.c              |  9 +--------
 target-openrisc/cpu.h              |  3 +++
 target-openrisc/interrupt.c        |  2 +-
 target-openrisc/interrupt_helper.c |  2 +-
 target-openrisc/sys_helper.c       |  2 +-
 target-ppc/helper_regs.h           |  4 ++--
 target-ppc/misc_helper.c           |  4 ++--
 target-ppc/mmu_helper.c            | 32 ++++++++++++++++----------------
 target-ppc/translate_init.c        |  3 ---
 target-s390x/cpu.c                 |  7 ++-----
 target-s390x/cpu.h                 |  5 +++--
 target-s390x/gdbstub.c             |  2 +-
 target-s390x/mem_helper.c          |  8 ++++----
 target-sh4/cpu.c                   |  3 +--
 target-sh4/cpu.h                   |  3 +++
 target-sh4/helper.c                |  2 +-
 target-sparc/cpu.c                 |  3 +--
 target-sparc/cpu.h                 |  3 +++
 target-sparc/ldst_helper.c         | 12 ++++++------
 target-tilegx/cpu.c                |  3 +--
 target-tilegx/cpu.h                |  3 +++
 target-tricore/cpu.c               |  2 --
 target-unicore32/cpu.c             |  2 +-
 target-unicore32/helper.c          |  2 +-
 target-xtensa/op_helper.c          |  2 +-
 57 files changed, 151 insertions(+), 148 deletions(-)

-- 
2.10.1

^ permalink raw reply

* [Qemu-devel] [RFC 2/2] cputlb: drop flush_global flag from tlb_flush
From: Alex Bennée @ 2016-11-14 17:40 UTC (permalink / raw)
  To: rth
  Cc: qemu-devel, Alex Bennée, Paolo Bonzini, Peter Crosthwaite,
	Aurelien Jarno, Peter Maydell, Eduardo Habkost, Edgar E. Iglesias,
	Yongbok Kim, Jia Liu, David Gibson, Alexander Graf,
	Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov,
	open list:ARM, open list:PowerPC
In-Reply-To: <20161114174010.31040-1-alex.bennee@linaro.org>

We have never has the concept of global TLB entries which would avoid
the flush so we never actually use this flag. Drop it and make clear
that tlb_flush is the sledge-hammer it has always been.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 cputlb.c                           | 21 ++++++---------------
 exec.c                             |  4 ++--
 hw/sh4/sh7750.c                    |  2 +-
 include/exec/exec-all.h            | 14 ++++++--------
 target-alpha/cpu.c                 |  2 +-
 target-alpha/sys_helper.c          |  2 +-
 target-arm/helper.c                | 26 +++++++++++++-------------
 target-i386/fpu_helper.c           |  2 +-
 target-i386/helper.c               |  8 ++++----
 target-i386/machine.c              |  2 +-
 target-i386/misc_helper.c          |  2 +-
 target-i386/svm_helper.c           |  2 +-
 target-microblaze/mmu.c            |  2 +-
 target-mips/cpu.h                  |  2 +-
 target-mips/helper.c               |  6 +++---
 target-mips/op_helper.c            |  8 ++++----
 target-openrisc/interrupt.c        |  2 +-
 target-openrisc/interrupt_helper.c |  2 +-
 target-openrisc/sys_helper.c       |  2 +-
 target-ppc/helper_regs.h           |  4 ++--
 target-ppc/misc_helper.c           |  4 ++--
 target-ppc/mmu_helper.c            | 32 ++++++++++++++++----------------
 target-s390x/gdbstub.c             |  2 +-
 target-s390x/mem_helper.c          |  8 ++++----
 target-sh4/helper.c                |  2 +-
 target-sparc/ldst_helper.c         | 12 ++++++------
 target-unicore32/cpu.c             |  2 +-
 target-unicore32/helper.c          |  2 +-
 target-xtensa/op_helper.c          |  2 +-
 29 files changed, 85 insertions(+), 96 deletions(-)

diff --git a/cputlb.c b/cputlb.c
index 813279f..6c39927 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -60,24 +60,15 @@
 /* statistics */
 int tlb_flush_count;
 
-/* NOTE:
- * If flush_global is true (the usual case), flush all tlb entries.
- * If flush_global is false, flush (at least) all tlb entries not
- * marked global.
- *
- * Since QEMU doesn't currently implement a global/not-global flag
- * for tlb entries, at the moment tlb_flush() will also flush all
- * tlb entries in the flush_global == false case. This is OK because
- * CPU architectures generally permit an implementation to drop
- * entries from the TLB at any time, so flushing more entries than
- * required is only an efficiency issue, not a correctness issue.
+/* This is OK because CPU architectures generally permit an
+ * implementation to drop entries from the TLB at any time, so
+ * flushing more entries than required is only an efficiency issue,
+ * not a correctness issue.
  */
-void tlb_flush(CPUState *cpu, int flush_global)
+void tlb_flush(CPUState *cpu)
 {
     CPUArchState *env = cpu->env_ptr;
 
-    tlb_debug("(%d)\n", flush_global);
-
     memset(env->tlb_table, -1, sizeof(env->tlb_table));
     memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
     memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
@@ -144,7 +135,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
                   TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
                   env->tlb_flush_addr, env->tlb_flush_mask);
 
-        tlb_flush(cpu, 1);
+        tlb_flush(cpu);
         return;
     }
 
diff --git a/exec.c b/exec.c
index 3d867f1..55a66da 100644
--- a/exec.c
+++ b/exec.c
@@ -511,7 +511,7 @@ static int cpu_common_post_load(void *opaque, int version_id)
     /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
        version_id is increased. */
     cpu->interrupt_request &= ~0x01;
-    tlb_flush(cpu, 1);
+    tlb_flush(cpu);
 
     return 0;
 }
@@ -2406,7 +2406,7 @@ static void tcg_commit(MemoryListener *listener)
      */
     d = atomic_rcu_read(&cpuas->as->dispatch);
     atomic_rcu_set(&cpuas->memory_dispatch, d);
-    tlb_flush(cpuas->cpu, 1);
+    tlb_flush(cpuas->cpu);
 }
 
 void address_space_init_dispatch(AddressSpace *as)
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 3132d55..166e4bd 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -417,7 +417,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
     case SH7750_PTEH_A7:
         /* If asid changes, clear all registered tlb entries. */
         if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
-            tlb_flush(CPU(s->cpu), 1);
+            tlb_flush(CPU(s->cpu));
         }
         s->cpu->env.pteh = mem_value;
         return;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index a8c13ce..bbc9478 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -95,15 +95,13 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr);
 /**
  * tlb_flush:
  * @cpu: CPU whose TLB should be flushed
- * @flush_global: ignored
  *
- * Flush the entire TLB for the specified CPU.
- * The flush_global flag is in theory an indicator of whether the whole
- * TLB should be flushed, or only those entries not marked global.
- * In practice QEMU does not implement any global/not global flag for
- * TLB entries, and the argument is ignored.
+ * Flush the entire TLB for the specified CPU. Most CPU architectures
+ * allow the implementation to drop entries from the TLB at any time
+ * so this is generally safe. If more selective flushing is required
+ * use one of the other functions for efficiency.
  */
-void tlb_flush(CPUState *cpu, int flush_global);
+void tlb_flush(CPUState *cpu);
 /**
  * tlb_flush_page_by_mmuidx:
  * @cpu: CPU whose TLB should be flushed
@@ -165,7 +163,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 {
 }
 
-static inline void tlb_flush(CPUState *cpu, int flush_global)
+static inline void tlb_flush(CPUState *cpu)
 {
 }
 
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 30d77ce..b4f9798 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -273,7 +273,7 @@ static void alpha_cpu_initfn(Object *obj)
     CPUAlphaState *env = &cpu->env;
 
     cs->env_ptr = env;
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 
     alpha_translate_init();
 
diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
index bec1e17..652195d 100644
--- a/target-alpha/sys_helper.c
+++ b/target-alpha/sys_helper.c
@@ -44,7 +44,7 @@ uint64_t helper_load_pcc(CPUAlphaState *env)
 #ifndef CONFIG_USER_ONLY
 void helper_tbia(CPUAlphaState *env)
 {
-    tlb_flush(CPU(alpha_env_get_cpu(env)), 1);
+    tlb_flush(CPU(alpha_env_get_cpu(env)));
 }
 
 void helper_tbis(CPUAlphaState *env, uint64_t p)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b5b65ca..0b2f689 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -464,7 +464,7 @@ static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
     ARMCPU *cpu = arm_env_get_cpu(env);
 
     raw_write(env, ri, value);
-    tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
+    tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
 }
 
 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -475,7 +475,7 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         /* Unlike real hardware the qemu TLB uses virtual addresses,
          * not modified virtual addresses, so this causes a TLB flush.
          */
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
         raw_write(env, ri, value);
     }
 }
@@ -491,7 +491,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
          * format) this register includes the ASID, so do a TLB flush.
          * For PMSA it is purely a process ID and no action is needed.
          */
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
     raw_write(env, ri, value);
 }
@@ -502,7 +502,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
     /* Invalidate all (TLBIALL) */
     ARMCPU *cpu = arm_env_get_cpu(env);
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -520,7 +520,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
     /* Invalidate by ASID (TLBIASID) */
     ARMCPU *cpu = arm_env_get_cpu(env);
 
-    tlb_flush(CPU(cpu), value == 0);
+    tlb_flush(CPU(cpu));
 }
 
 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -539,7 +539,7 @@ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *other_cs;
 
     CPU_FOREACH(other_cs) {
-        tlb_flush(other_cs, 1);
+        tlb_flush(other_cs);
     }
 }
 
@@ -549,7 +549,7 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *other_cs;
 
     CPU_FOREACH(other_cs) {
-        tlb_flush(other_cs, value == 0);
+        tlb_flush(other_cs);
     }
 }
 
@@ -2310,7 +2310,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 
     u32p += env->cp15.c6_rgnr;
-    tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
     *u32p = value;
 }
 
@@ -2455,7 +2455,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         /* With LPAE the TTBCR could result in a change of ASID
          * via the TTBCR.A1 bit, so do a TLB flush.
          */
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
     vmsa_ttbcr_raw_write(env, ri, value);
 }
@@ -2479,7 +2479,7 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
     TCR *tcr = raw_ptr(env, ri);
 
     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
     tcr->raw_tcr = value;
 }
 
@@ -2492,7 +2492,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     if (cpreg_field_is_64bit(ri)) {
         ARMCPU *cpu = arm_env_get_cpu(env);
 
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
     raw_write(env, ri, value);
 }
@@ -3160,7 +3160,7 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     raw_write(env, ri, value);
     /* ??? Lots of these bits are not implemented.  */
     /* This may enable/disable the MMU, so do a TLB flush.  */
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3628,7 +3628,7 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
      * HCR_DC Disables stage1 and enables stage2 translation
      */
     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
     raw_write(env, ri, value);
 }
diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c
index 2049a8c..66474ad 100644
--- a/target-i386/fpu_helper.c
+++ b/target-i386/fpu_helper.c
@@ -1465,7 +1465,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
         }
         if (env->pkru != old_pkru) {
             CPUState *cs = CPU(x86_env_get_cpu(env));
-            tlb_flush(cs, 1);
+            tlb_flush(cs);
         }
     }
 }
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 4ecc091..20a6dfc 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -586,7 +586,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
 
         /* when a20 is changed, all the MMU mappings are invalid, so
            we must flush everything */
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
         env->a20_mask = ~(1 << 20) | (a20_state << 20);
     }
 }
@@ -599,7 +599,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
     qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
     if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
         (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 
 #ifdef TARGET_X86_64
@@ -641,7 +641,7 @@ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
     if (env->cr[0] & CR0_PG_MASK) {
         qemu_log_mask(CPU_LOG_MMU,
                         "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
-        tlb_flush(CPU(cpu), 0);
+        tlb_flush(CPU(cpu));
     }
 }
 
@@ -656,7 +656,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
     if ((new_cr4 ^ env->cr[4]) &
         (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
          CR4_SMEP_MASK | CR4_SMAP_MASK)) {
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 
     /* Clear bits we're going to recompute.  */
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 760f82b..e002b4f 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -387,7 +387,7 @@ static int cpu_post_load(void *opaque, int version_id)
         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
         cpu_x86_update_dr7(env, dr7);
     }
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 
     if (tcg_enabled()) {
         cpu_smm_update(cpu);
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index 3f666b4..5029efe 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -635,5 +635,5 @@ void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
     }
 
     env->pkru = val;
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 }
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 782b3f1..210f6aa 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -289,7 +289,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
         break;
     case TLB_CONTROL_FLUSH_ALL_ASID:
         /* FIXME: this is not 100% correct but should work for now */
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
         break;
     }
 
diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
index a22a496..a0f0675 100644
--- a/target-microblaze/mmu.c
+++ b/target-microblaze/mmu.c
@@ -255,7 +255,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
             /* Changes to the zone protection reg flush the QEMU TLB.
                Fortunately, these are very uncommon.  */
             if (v != env->mmu.regs[rn]) {
-                tlb_flush(CPU(cpu), 1);
+                tlb_flush(CPU(cpu));
             }
             env->mmu.regs[rn] = v;
             break;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3146a60..e1c78f5 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -1054,7 +1054,7 @@ static inline void compute_hflags(CPUMIPSState *env)
     }
 }
 
-void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global);
+void cpu_mips_tlb_flush(CPUMIPSState *env);
 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
diff --git a/target-mips/helper.c b/target-mips/helper.c
index c864b15..d2e7795 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -223,12 +223,12 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
     return ret;
 }
 
-void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
+void cpu_mips_tlb_flush(CPUMIPSState *env)
 {
     MIPSCPU *cpu = mips_env_get_cpu(env);
 
     /* Flush qemu's TLB and discard all shadowed entries.  */
-    tlb_flush(CPU(cpu), flush_global);
+    tlb_flush(CPU(cpu));
     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
 
@@ -290,7 +290,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
 #if defined(TARGET_MIPS64)
     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
         /* Access to at least one of the 64-bit segments has been disabled */
-        cpu_mips_tlb_flush(env, 1);
+        cpu_mips_tlb_flush(env);
     }
 #endif
     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 7af4c2f..9ba4cb4 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1431,7 +1431,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
     /* If the ASID changes, flush qemu's TLB.  */
     if ((old & env->CP0_EntryHi_ASID_mask) !=
         (val & env->CP0_EntryHi_ASID_mask)) {
-        cpu_mips_tlb_flush(env, 1);
+        cpu_mips_tlb_flush(env);
     }
 }
 
@@ -2021,7 +2021,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env)
             tlb->EHINV = 1;
         }
     }
-    cpu_mips_tlb_flush(env, 1);
+    cpu_mips_tlb_flush(env);
 }
 
 void r4k_helper_tlbinvf(CPUMIPSState *env)
@@ -2031,7 +2031,7 @@ void r4k_helper_tlbinvf(CPUMIPSState *env)
     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
     }
-    cpu_mips_tlb_flush(env, 1);
+    cpu_mips_tlb_flush(env);
 }
 
 void r4k_helper_tlbwi(CPUMIPSState *env)
@@ -2145,7 +2145,7 @@ void r4k_helper_tlbr(CPUMIPSState *env)
 
     /* If this will change the current ASID, flush qemu's TLB.  */
     if (ASID != tlb->ASID)
-        cpu_mips_tlb_flush (env, 1);
+        cpu_mips_tlb_flush (env);
 
     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
 
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 5fe3f11..e43fc84 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -45,7 +45,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
 
     /* For machine-state changed between user-mode and supervisor mode,
        we need flush TLB when we enter&exit EXCP.  */
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 
     env->esr = env->sr;
     env->sr &= ~SR_DME;
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
index 116f9109..0ed5146 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -53,7 +53,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
     }
 
     if (need_flush_tlb) {
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
     }
 #endif
     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index a719e45..daea902 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -47,7 +47,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 17): /* SR */
         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
             (rb & (SR_IME | SR_DME | SR_SM))) {
-            tlb_flush(cs, 1);
+            tlb_flush(cs);
         }
         env->sr = rb;
         env->sr |= SR_FO;      /* FO is const equal to 1 */
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index bb9ce60..22c016b 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -158,7 +158,7 @@ static inline void check_tlb_flush(CPUPPCState *env, bool global)
 {
     CPUState *cs = CPU(ppc_env_get_cpu(env));
     if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
     }
 
@@ -173,7 +173,7 @@ static inline void check_tlb_flush(CPUPPCState *env, bool global)
                 CPUPPCState *other_env = &cpu->env;
 
                 other_env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
-                tlb_flush(other_cs, 1);
+                tlb_flush(other_cs);
             }
         }
         env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
index 1e6e705..ab432ba 100644
--- a/target-ppc/misc_helper.c
+++ b/target-ppc/misc_helper.c
@@ -85,7 +85,7 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
     if (!env->external_htab) {
         if (env->spr[SPR_SDR1] != val) {
             ppc_store_sdr1(env, val);
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
     }
 }
@@ -114,7 +114,7 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
     if (likely(env->pb[num] != value)) {
         env->pb[num] = value;
         /* Should be optimized */
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 }
 
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index d09fc0a..f746f53 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -248,7 +248,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
         tlb = &env->tlb.tlb6[nr];
         pte_invalidate(&tlb->pte0);
     }
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
@@ -661,7 +661,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
         tlb = &env->tlb.tlbe[i];
         tlb->prot &= ~PAGE_VALID;
     }
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
@@ -863,7 +863,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags,
         tlb += booke206_tlb_size(env, i);
     }
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
@@ -1769,7 +1769,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
 #if !defined(FLUSH_ALL_TLBS)
         do_invalidate_BAT(env, env->IBAT[0][nr], mask);
 #else
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
 #endif
     }
 }
@@ -1804,7 +1804,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
 #if !defined(FLUSH_ALL_TLBS)
         do_invalidate_BAT(env, env->DBAT[0][nr], mask);
 #else
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
 #endif
     }
 }
@@ -1852,7 +1852,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
         }
 #if defined(FLUSH_ALL_TLBS)
         if (do_inval) {
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
 #endif
     }
@@ -1892,7 +1892,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
         env->DBAT[1][nr] = value;
 #if defined(FLUSH_ALL_TLBS)
         if (do_inval) {
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
 #endif
     }
@@ -1921,7 +1921,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
         cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
         break;
     case POWERPC_MMU_BOOKE:
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
         break;
     case POWERPC_MMU_BOOKE206:
         booke206_flush_tlb(env, -1, 0);
@@ -1937,7 +1937,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
     case POWERPC_MMU_2_07a:
 #endif /* defined(TARGET_PPC64) */
         env->tlb_need_flush = 0;
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
         break;
     default:
         /* XXX: TODO */
@@ -2433,13 +2433,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
         }
         tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
         if (do_flush_tlbs) {
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
         break;
     case 1:
         RPN = value & 0xFFFFFC0F;
         if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
         tlb->RPN = RPN;
         break;
@@ -2555,7 +2555,7 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
 
     env->spr[pidn] = pid;
     /* changing PIDs mean we're in a different address space now */
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void helper_booke206_tlbwe(CPUPPCState *env)
@@ -2650,7 +2650,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
     if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
         tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
     } else {
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 }
 
@@ -2775,7 +2775,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
         /* flush TLB1 entries */
         booke206_invalidate_ea_tlb(env, 1, address);
         CPU_FOREACH(cs) {
-            tlb_flush(cs, 1);
+            tlb_flush(cs);
         }
     } else {
         /* flush TLB0 entries */
@@ -2811,7 +2811,7 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
         }
         tlb += booke206_tlb_size(env, i);
     }
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
@@ -2852,7 +2852,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
             tlb->mas1 &= ~MAS1_VALID;
         }
     }
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type)
diff --git a/target-s390x/gdbstub.c b/target-s390x/gdbstub.c
index 3d223de..ea4dc22 100644
--- a/target-s390x/gdbstub.c
+++ b/target-s390x/gdbstub.c
@@ -199,7 +199,7 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
     case S390_C0_REGNUM ... S390_C15_REGNUM:
         env->cregs[n] = ldtul_p(mem_buf);
         if (tcg_enabled()) {
-            tlb_flush(ENV_GET_CPU(env), 1);
+            tlb_flush(ENV_GET_CPU(env));
         }
         cpu_synchronize_post_init(ENV_GET_CPU(env));
         return 8;
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 99bc5e2..675aba2 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -872,7 +872,7 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
         s390_cpu_recompute_watchpoints(CPU(cpu));
     }
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
@@ -900,7 +900,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
         s390_cpu_recompute_watchpoints(CPU(cpu));
     }
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
@@ -1036,7 +1036,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
         cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]);
         if (r2 & 0x3) {
             /* flush TLB / ALB */
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
         cc = 0;
     } else {
@@ -1121,7 +1121,7 @@ void HELPER(ptlb)(CPUS390XState *env)
 {
     S390CPU *cpu = s390_env_get_cpu(env);
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 /* load using real address */
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index a33ac69..036c5ca 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -583,7 +583,7 @@ void cpu_load_tlb(CPUSH4State * env)
         entry->v = 0;
     }
 
-    tlb_flush(CPU(sh_env_get_cpu(s)), 1);
+    tlb_flush(CPU(sh_env_get_cpu(s)));
 }
 
 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index de7d53a..a0171f7 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -816,7 +816,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
             case 2: /* flush region (16M) */
             case 3: /* flush context (4G) */
             case 4: /* flush entire */
-                tlb_flush(CPU(cpu), 1);
+                tlb_flush(CPU(cpu));
                 break;
             default:
                 break;
@@ -841,7 +841,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
                    are invalid in normal mode.  */
                 if ((oldreg ^ env->mmuregs[reg])
                     & (MMU_NF | env->def->mmu_bm)) {
-                    tlb_flush(CPU(cpu), 1);
+                    tlb_flush(CPU(cpu));
                 }
                 break;
             case 1: /* Context Table Pointer Register */
@@ -852,7 +852,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
                 if (oldreg != env->mmuregs[reg]) {
                     /* we flush when the MMU context changes because
                        QEMU has no MMU context support */
-                    tlb_flush(CPU(cpu), 1);
+                    tlb_flush(CPU(cpu));
                 }
                 break;
             case 3: /* Synchronous Fault Status Register with Clear */
@@ -1509,13 +1509,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
                 env->dmmu.mmu_primary_context = val;
                 /* can be optimized to only flush MMU_USER_IDX
                    and MMU_KERNEL_IDX entries */
-                tlb_flush(CPU(cpu), 1);
+                tlb_flush(CPU(cpu));
                 break;
             case 2: /* Secondary context */
                 env->dmmu.mmu_secondary_context = val;
                 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
                    and MMU_KERNEL_SECONDARY_IDX entries */
-                tlb_flush(CPU(cpu), 1);
+                tlb_flush(CPU(cpu));
                 break;
             case 5: /* TSB access */
                 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
@@ -1654,7 +1654,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
     /* flush neverland mappings created during no-fault mode,
        so the sequential MMU faults report proper fault types */
     if (env->mmuregs[0] & MMU_NF) {
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
     }
 }
 #else
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index c169972..c9b78ce 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -133,7 +133,7 @@ static void uc32_cpu_initfn(Object *obj)
     env->regs[31] = 0x03000000;
 #endif
 
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 
     if (tcg_enabled() && !inited) {
         inited = true;
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index d603bde..9454efa 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -116,7 +116,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
     case 6:
         if ((cop <= 6) && (cop >= 2)) {
             /* invalid all tlb */
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
             return;
         }
         break;
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 0a4b214..63c89f8 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -492,7 +492,7 @@ void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
     v = (v & 0xffffff00) | 0x1;
     if (v != env->sregs[RASID]) {
         env->sregs[RASID] = v;
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 }
 
-- 
2.10.1

^ permalink raw reply related

* [Qemu-devel] [RFC 1/2] qom/cpu: move tlb_flush to cpu_common_reset
From: Alex Bennée @ 2016-11-14 17:40 UTC (permalink / raw)
  To: rth
  Cc: qemu-devel, Alex Bennée, Peter Maydell, Edgar E. Iglesias,
	Paolo Bonzini, Eduardo Habkost, Michael Walle, Laurent Vivier,
	Aurelien Jarno, Yongbok Kim, Anthony Green, Jia Liu, David Gibson,
	Alexander Graf, Mark Cave-Ayland, Artyom Tarasenko,
	Bastian Koppelmann, open list:ARM, open list:PowerPC
In-Reply-To: <20161114174010.31040-1-alex.bennee@linaro.org>

It is a common thing amongst the various cpu reset functions want to
flush the SoftMMU's TLB entries. This is done either by calling
tlb_flush directly or by way of a general memset of the CPU
structure (sometimes both).

This moves the tlb_flush call to the common reset function and
additionally ensures it is only done for the CONFIG_SOFTMMU case and
when tcg is enabled.

In some target cases we add an empty end_of_reset_fields structure to the
target vCPU structure so have a clear end point for any memset which
is resetting value in the structure before CPU_COMMON (where the TLB
structures are).

While this is a nice clean-up in general it is also a precursor for
changes coming to cputlb for MTTCG where the clearing of entries
can't be done arbitrarily across vCPUs. Currently the cpu_reset
function is usually called from the context of another vCPU as the
architectural power up sequence is run. By using the cputlb API
functions we can ensure the right behaviour in the future.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 qom/cpu.c                   | 10 ++++++++--
 target-arm/cpu.c            |  5 ++---
 target-arm/cpu.h            |  5 ++++-
 target-cris/cpu.c           |  3 +--
 target-cris/cpu.h           |  9 ++++++---
 target-i386/cpu.c           |  2 --
 target-i386/cpu.h           |  6 ++++--
 target-lm32/cpu.c           |  3 +--
 target-lm32/cpu.h           |  3 +++
 target-m68k/cpu.c           |  3 +--
 target-m68k/cpu.h           |  3 +++
 target-microblaze/cpu.c     |  3 +--
 target-microblaze/cpu.h     |  3 +++
 target-mips/cpu.c           |  3 +--
 target-mips/cpu.h           |  3 +++
 target-moxie/cpu.c          |  4 +---
 target-moxie/cpu.h          |  3 +++
 target-openrisc/cpu.c       |  9 +--------
 target-openrisc/cpu.h       |  3 +++
 target-ppc/translate_init.c |  3 ---
 target-s390x/cpu.c          |  7 ++-----
 target-s390x/cpu.h          |  5 +++--
 target-sh4/cpu.c            |  3 +--
 target-sh4/cpu.h            |  3 +++
 target-sparc/cpu.c          |  3 +--
 target-sparc/cpu.h          |  3 +++
 target-tilegx/cpu.c         |  3 +--
 target-tilegx/cpu.h         |  3 +++
 target-tricore/cpu.c        |  2 --
 29 files changed, 66 insertions(+), 52 deletions(-)

diff --git a/qom/cpu.c b/qom/cpu.c
index 03d9190..61ee0cb 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -270,8 +270,14 @@ static void cpu_common_reset(CPUState *cpu)
     cpu->exception_index = -1;
     cpu->crash_occurred = false;
 
-    for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {
-        atomic_set(&cpu->tb_jmp_cache[i], NULL);
+    if (tcg_enabled()) {
+        for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {
+            atomic_set(&cpu->tb_jmp_cache[i], NULL);
+        }
+
+#ifdef CONFIG_SOFTMMU
+        tlb_flush(cpu, 0);
+#endif
     }
 }
 
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 99f0dbe..fb05d2e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -122,7 +122,8 @@ static void arm_cpu_reset(CPUState *s)
 
     acc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUARMState, features));
+    memset(env, 0, offsetof(CPUARMState, end_reset_fields));
+
     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 
@@ -226,8 +227,6 @@ static void arm_cpu_reset(CPUState *s)
                               &env->vfp.fp_status);
     set_float_detect_tininess(float_tininess_before_rounding,
                               &env->vfp.standard_fp_status);
-    tlb_flush(s, 1);
-
 #ifndef CONFIG_USER_ONLY
     if (kvm_enabled()) {
         kvm_arm_reset_vcpu(cpu);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ca5c849..53e9d55 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -491,9 +491,12 @@ typedef struct CPUARMState {
     struct CPUBreakpoint *cpu_breakpoint[16];
     struct CPUWatchpoint *cpu_watchpoint[16];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
-    /* These fields after the common ones so they are preserved on reset.  */
+    /* Fields after CPU_COMMON are preserved across CPU reset. */
 
     /* Internal CPU feature flags.  */
     uint64_t features;
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 2e9ab97..5f766f0 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -52,9 +52,8 @@ static void cris_cpu_reset(CPUState *s)
     ccc->parent_reset(s);
 
     vr = env->pregs[PR_VR];
-    memset(env, 0, offsetof(CPUCRISState, load_info));
+    memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
     env->pregs[PR_VR] = vr;
-    tlb_flush(s, 1);
 
 #if defined(CONFIG_USER_ONLY)
     /* start in user mode with interrupts enabled.  */
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 43d5f9d..920e1c3 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -167,10 +167,13 @@ typedef struct CPUCRISState {
 	 */
         TLBSet tlbsets[2][4][16];
 
-	CPU_COMMON
+        /* Fields up to this point are cleared by a CPU reset */
+        struct {} end_reset_fields;
 
-    /* Members from load_info on are preserved across resets.  */
-    void *load_info;
+        CPU_COMMON
+
+        /* Members from load_info on are preserved across resets.  */
+        void *load_info;
 } CPUCRISState;
 
 /**
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 6eec5dc..9dbc7fc 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2820,8 +2820,6 @@ static void x86_cpu_reset(CPUState *s)
 
     memset(env, 0, offsetof(CPUX86State, end_reset_fields));
 
-    tlb_flush(s, 1);
-
     env->old_exception = -1;
 
     /* init to reset state */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c605724..95ed91d 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1119,10 +1119,12 @@ typedef struct CPUX86State {
     uint8_t nmi_injected;
     uint8_t nmi_pending;
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
-    /* Fields from here on are preserved across CPU reset. */
-    struct {} end_reset_fields;
+    /* Fields after CPU_COMMON are preserved across CPU reset. */
 
     /* processor features (e.g. for CPUID insn) */
     /* Minimum level/xlevel/xlevel2, based on CPU model + features */
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 8d939a7..2b8c36b 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -128,10 +128,9 @@ static void lm32_cpu_reset(CPUState *s)
     lcc->parent_reset(s);
 
     /* reset cpu state */
-    memset(env, 0, offsetof(CPULM32State, eba));
+    memset(env, 0, offsetof(CPULM32State, end_reset_fields));
 
     lm32_cpu_init_cfg_reg(cpu);
-    tlb_flush(s, 1);
 }
 
 static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index d8a3515..1d972cb 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -165,6 +165,9 @@ struct CPULM32State {
     struct CPUBreakpoint *cpu_breakpoint[4];
     struct CPUWatchpoint *cpu_watchpoint[4];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index ba17480..fa10b6e 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -52,7 +52,7 @@ static void m68k_cpu_reset(CPUState *s)
 
     mcc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUM68KState, features));
+    memset(env, 0, offsetof(CPUM68KState, end_reset_fields));
 #if !defined(CONFIG_USER_ONLY)
     env->sr = 0x2700;
 #endif
@@ -61,7 +61,6 @@ static void m68k_cpu_reset(CPUState *s)
     cpu_m68k_set_ccr(env, 0);
     /* TODO: We should set PC from the interrupt vector.  */
     env->pc = 0;
-    tlb_flush(s, 1);
 }
 
 static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info)
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 6dfb54e..8e7b51b 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -115,6 +115,9 @@ typedef struct CPUM68KState {
 
     uint32_t qregs[MAX_QREGS];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 389c7b6..3d58869 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -103,9 +103,8 @@ static void mb_cpu_reset(CPUState *s)
 
     mcc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUMBState, pvr));
+    memset(env, 0, offsetof(CPUMBState, end_reset_fields));
     env->res_addr = RES_ADDR_NONE;
-    tlb_flush(s, 1);
 
     /* Disable stack protector.  */
     env->shr = ~0;
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index beb75ff..bf6963b 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -267,6 +267,9 @@ struct CPUMBState {
     struct microblaze_mmu mmu;
 #endif
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* These fields are preserved on reset.  */
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 65ca607..1bb66b7 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -100,8 +100,7 @@ static void mips_cpu_reset(CPUState *s)
 
     mcc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUMIPSState, mvp));
-    tlb_flush(s, 1);
+    memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 
     cpu_state_reset(env);
 
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 5182dc7..3146a60 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -607,6 +607,9 @@ struct CPUMIPSState {
     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
     int insn_flags; /* Supported instruction set */
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index b0be4a7..927b1a1 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -45,10 +45,8 @@ static void moxie_cpu_reset(CPUState *s)
 
     mcc->parent_reset(s);
 
-    memset(env, 0, sizeof(CPUMoxieState));
+    memset(env, 0, offsetof(CPUMoxieState, end_reset_fields));
     env->pc = 0x1000;
-
-    tlb_flush(s, 1);
 }
 
 static void moxie_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index 3e880fa..8991aae 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -56,6 +56,9 @@ typedef struct CPUMoxieState {
 
     void *irq[8];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
 } CPUMoxieState;
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 698e87b..422139d 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -44,14 +44,7 @@ static void openrisc_cpu_reset(CPUState *s)
 
     occ->parent_reset(s);
 
-#ifndef CONFIG_USER_ONLY
-    memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb));
-#else
-    memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
-#endif
-
-    tlb_flush(s, 1);
-    /*tb_flush(&cpu->env);    FIXME: Do we need it?  */
+    memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
 
     cpu->env.pc = 0x100;
     cpu->env.sr = SR_FO | SR_SM;
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index aaf1535..508ef56 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -300,6 +300,9 @@ typedef struct CPUOpenRISCState {
                                  in solt so far.  */
     uint32_t btaken;          /* the SR_F bit */
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 208fa1e..9f753ae 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10415,9 +10415,6 @@ static void ppc_cpu_reset(CPUState *s)
         }
         env->spr[i] = spr->default_value;
     }
-
-    /* Flush all TLBs */
-    tlb_flush(s, 1);
 }
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 0a39d31..066dcd1 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -82,7 +82,6 @@ static void s390_cpu_reset(CPUState *s)
     scc->parent_reset(s);
     cpu->env.sigp_order = 0;
     s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
-    tlb_flush(s, 1);
 }
 
 /* S390CPUClass::initial_reset() */
@@ -94,7 +93,7 @@ static void s390_cpu_initial_reset(CPUState *s)
 
     s390_cpu_reset(s);
     /* initial reset does not touch regs,fregs and aregs */
-    memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) -
+    memset(&env->fpc, 0, offsetof(CPUS390XState, end_reset_fields) -
                          offsetof(CPUS390XState, fpc));
 
     /* architectured initial values for CR 0 and 14 */
@@ -118,7 +117,6 @@ static void s390_cpu_initial_reset(CPUState *s)
     if (kvm_enabled()) {
         kvm_s390_reset_vcpu(cpu);
     }
-    tlb_flush(s, 1);
 }
 
 /* CPUClass:reset() */
@@ -133,7 +131,7 @@ static void s390_cpu_full_reset(CPUState *s)
     cpu->env.sigp_order = 0;
     s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
 
-    memset(env, 0, offsetof(CPUS390XState, cpu_num));
+    memset(env, 0, offsetof(CPUS390XState, end_reset_fields));
 
     /* architectured initial values for CR 0 and 14 */
     env->cregs[0] = CR0_RESET;
@@ -156,7 +154,6 @@ static void s390_cpu_full_reset(CPUState *s)
     if (kvm_enabled()) {
         kvm_s390_reset_vcpu(cpu);
     }
-    tlb_flush(s, 1);
 }
 
 #if !defined(CONFIG_USER_ONLY)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index fd36a25..058ddad 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -139,9 +139,10 @@ typedef struct CPUS390XState {
 
     uint8_t riccb[64];
 
-    CPU_COMMON
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
 
-    /* reset does memset(0) up to here */
+    CPU_COMMON
 
     uint32_t cpu_num;
     uint32_t machine_type;
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index a38f6a6..9a481c3 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -56,8 +56,7 @@ static void superh_cpu_reset(CPUState *s)
 
     scc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUSH4State, id));
-    tlb_flush(s, 1);
+    memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
 
     env->pc = 0xA0000000;
 #if defined(CONFIG_USER_ONLY)
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 478ab55..cad8989 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -175,6 +175,9 @@ typedef struct CPUSH4State {
 
     uint32_t ldst;
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved over CPU reset. */
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 4e07b92..d6583f1 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -36,8 +36,7 @@ static void sparc_cpu_reset(CPUState *s)
 
     scc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUSPARCState, version));
-    tlb_flush(s, 1);
+    memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
     env->cwp = 0;
 #ifndef TARGET_SPARC64
     env->wim = 1;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 5fb0ed1..601c018 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -419,6 +419,9 @@ struct CPUSPARCState {
     /* NOTE: we allow 8 more registers to handle wrapping */
     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
index 454793f..d90e38e 100644
--- a/target-tilegx/cpu.c
+++ b/target-tilegx/cpu.c
@@ -84,8 +84,7 @@ static void tilegx_cpu_reset(CPUState *s)
 
     tcc->parent_reset(s);
 
-    memset(env, 0, sizeof(CPUTLGState));
-    tlb_flush(s, 1);
+    memset(env, 0, offsetof(CPUTLGState, end_reset_fields));
 }
 
 static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 1735427..f32be49 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -97,6 +97,9 @@ typedef struct CPUTLGState {
     uint32_t sigcode;                  /* Signal code */
 #endif
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 } CPUTLGState;
 
diff --git a/target-tricore/cpu.c b/target-tricore/cpu.c
index 785b76b..08f50e2 100644
--- a/target-tricore/cpu.c
+++ b/target-tricore/cpu.c
@@ -53,8 +53,6 @@ static void tricore_cpu_reset(CPUState *s)
 
     tcc->parent_reset(s);
 
-    tlb_flush(s, 1);
-
     cpu_state_reset(env);
 }
 
-- 
2.10.1

^ permalink raw reply related

* [RFC 2/2] cputlb: drop flush_global flag from tlb_flush
From: Alex Bennée @ 2016-11-14 17:40 UTC (permalink / raw)
  To: rth
  Cc: qemu-devel, Alex Bennée, Paolo Bonzini, Peter Crosthwaite,
	Aurelien Jarno, Peter Maydell, Eduardo Habkost, Edgar E. Iglesias,
	Yongbok Kim, Jia Liu, David Gibson, Alexander Graf,
	Mark Cave-Ayland, Artyom Tarasenko, Guan Xuetao, Max Filippov,
	open list:ARM, open list:PowerPC
In-Reply-To: <20161114174010.31040-1-alex.bennee@linaro.org>

We have never has the concept of global TLB entries which would avoid
the flush so we never actually use this flag. Drop it and make clear
that tlb_flush is the sledge-hammer it has always been.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 cputlb.c                           | 21 ++++++---------------
 exec.c                             |  4 ++--
 hw/sh4/sh7750.c                    |  2 +-
 include/exec/exec-all.h            | 14 ++++++--------
 target-alpha/cpu.c                 |  2 +-
 target-alpha/sys_helper.c          |  2 +-
 target-arm/helper.c                | 26 +++++++++++++-------------
 target-i386/fpu_helper.c           |  2 +-
 target-i386/helper.c               |  8 ++++----
 target-i386/machine.c              |  2 +-
 target-i386/misc_helper.c          |  2 +-
 target-i386/svm_helper.c           |  2 +-
 target-microblaze/mmu.c            |  2 +-
 target-mips/cpu.h                  |  2 +-
 target-mips/helper.c               |  6 +++---
 target-mips/op_helper.c            |  8 ++++----
 target-openrisc/interrupt.c        |  2 +-
 target-openrisc/interrupt_helper.c |  2 +-
 target-openrisc/sys_helper.c       |  2 +-
 target-ppc/helper_regs.h           |  4 ++--
 target-ppc/misc_helper.c           |  4 ++--
 target-ppc/mmu_helper.c            | 32 ++++++++++++++++----------------
 target-s390x/gdbstub.c             |  2 +-
 target-s390x/mem_helper.c          |  8 ++++----
 target-sh4/helper.c                |  2 +-
 target-sparc/ldst_helper.c         | 12 ++++++------
 target-unicore32/cpu.c             |  2 +-
 target-unicore32/helper.c          |  2 +-
 target-xtensa/op_helper.c          |  2 +-
 29 files changed, 85 insertions(+), 96 deletions(-)

diff --git a/cputlb.c b/cputlb.c
index 813279f..6c39927 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -60,24 +60,15 @@
 /* statistics */
 int tlb_flush_count;
 
-/* NOTE:
- * If flush_global is true (the usual case), flush all tlb entries.
- * If flush_global is false, flush (at least) all tlb entries not
- * marked global.
- *
- * Since QEMU doesn't currently implement a global/not-global flag
- * for tlb entries, at the moment tlb_flush() will also flush all
- * tlb entries in the flush_global == false case. This is OK because
- * CPU architectures generally permit an implementation to drop
- * entries from the TLB at any time, so flushing more entries than
- * required is only an efficiency issue, not a correctness issue.
+/* This is OK because CPU architectures generally permit an
+ * implementation to drop entries from the TLB at any time, so
+ * flushing more entries than required is only an efficiency issue,
+ * not a correctness issue.
  */
-void tlb_flush(CPUState *cpu, int flush_global)
+void tlb_flush(CPUState *cpu)
 {
     CPUArchState *env = cpu->env_ptr;
 
-    tlb_debug("(%d)\n", flush_global);
-
     memset(env->tlb_table, -1, sizeof(env->tlb_table));
     memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
     memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
@@ -144,7 +135,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
                   TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
                   env->tlb_flush_addr, env->tlb_flush_mask);
 
-        tlb_flush(cpu, 1);
+        tlb_flush(cpu);
         return;
     }
 
diff --git a/exec.c b/exec.c
index 3d867f1..55a66da 100644
--- a/exec.c
+++ b/exec.c
@@ -511,7 +511,7 @@ static int cpu_common_post_load(void *opaque, int version_id)
     /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
        version_id is increased. */
     cpu->interrupt_request &= ~0x01;
-    tlb_flush(cpu, 1);
+    tlb_flush(cpu);
 
     return 0;
 }
@@ -2406,7 +2406,7 @@ static void tcg_commit(MemoryListener *listener)
      */
     d = atomic_rcu_read(&cpuas->as->dispatch);
     atomic_rcu_set(&cpuas->memory_dispatch, d);
-    tlb_flush(cpuas->cpu, 1);
+    tlb_flush(cpuas->cpu);
 }
 
 void address_space_init_dispatch(AddressSpace *as)
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 3132d55..166e4bd 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -417,7 +417,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
     case SH7750_PTEH_A7:
         /* If asid changes, clear all registered tlb entries. */
         if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
-            tlb_flush(CPU(s->cpu), 1);
+            tlb_flush(CPU(s->cpu));
         }
         s->cpu->env.pteh = mem_value;
         return;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index a8c13ce..bbc9478 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -95,15 +95,13 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr);
 /**
  * tlb_flush:
  * @cpu: CPU whose TLB should be flushed
- * @flush_global: ignored
  *
- * Flush the entire TLB for the specified CPU.
- * The flush_global flag is in theory an indicator of whether the whole
- * TLB should be flushed, or only those entries not marked global.
- * In practice QEMU does not implement any global/not global flag for
- * TLB entries, and the argument is ignored.
+ * Flush the entire TLB for the specified CPU. Most CPU architectures
+ * allow the implementation to drop entries from the TLB at any time
+ * so this is generally safe. If more selective flushing is required
+ * use one of the other functions for efficiency.
  */
-void tlb_flush(CPUState *cpu, int flush_global);
+void tlb_flush(CPUState *cpu);
 /**
  * tlb_flush_page_by_mmuidx:
  * @cpu: CPU whose TLB should be flushed
@@ -165,7 +163,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 {
 }
 
-static inline void tlb_flush(CPUState *cpu, int flush_global)
+static inline void tlb_flush(CPUState *cpu)
 {
 }
 
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 30d77ce..b4f9798 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -273,7 +273,7 @@ static void alpha_cpu_initfn(Object *obj)
     CPUAlphaState *env = &cpu->env;
 
     cs->env_ptr = env;
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 
     alpha_translate_init();
 
diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
index bec1e17..652195d 100644
--- a/target-alpha/sys_helper.c
+++ b/target-alpha/sys_helper.c
@@ -44,7 +44,7 @@ uint64_t helper_load_pcc(CPUAlphaState *env)
 #ifndef CONFIG_USER_ONLY
 void helper_tbia(CPUAlphaState *env)
 {
-    tlb_flush(CPU(alpha_env_get_cpu(env)), 1);
+    tlb_flush(CPU(alpha_env_get_cpu(env)));
 }
 
 void helper_tbis(CPUAlphaState *env, uint64_t p)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b5b65ca..0b2f689 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -464,7 +464,7 @@ static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
     ARMCPU *cpu = arm_env_get_cpu(env);
 
     raw_write(env, ri, value);
-    tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
+    tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
 }
 
 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -475,7 +475,7 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         /* Unlike real hardware the qemu TLB uses virtual addresses,
          * not modified virtual addresses, so this causes a TLB flush.
          */
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
         raw_write(env, ri, value);
     }
 }
@@ -491,7 +491,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
          * format) this register includes the ASID, so do a TLB flush.
          * For PMSA it is purely a process ID and no action is needed.
          */
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
     raw_write(env, ri, value);
 }
@@ -502,7 +502,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
     /* Invalidate all (TLBIALL) */
     ARMCPU *cpu = arm_env_get_cpu(env);
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -520,7 +520,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
     /* Invalidate by ASID (TLBIASID) */
     ARMCPU *cpu = arm_env_get_cpu(env);
 
-    tlb_flush(CPU(cpu), value == 0);
+    tlb_flush(CPU(cpu));
 }
 
 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -539,7 +539,7 @@ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *other_cs;
 
     CPU_FOREACH(other_cs) {
-        tlb_flush(other_cs, 1);
+        tlb_flush(other_cs);
     }
 }
 
@@ -549,7 +549,7 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *other_cs;
 
     CPU_FOREACH(other_cs) {
-        tlb_flush(other_cs, value == 0);
+        tlb_flush(other_cs);
     }
 }
 
@@ -2310,7 +2310,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 
     u32p += env->cp15.c6_rgnr;
-    tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
     *u32p = value;
 }
 
@@ -2455,7 +2455,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         /* With LPAE the TTBCR could result in a change of ASID
          * via the TTBCR.A1 bit, so do a TLB flush.
          */
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
     vmsa_ttbcr_raw_write(env, ri, value);
 }
@@ -2479,7 +2479,7 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
     TCR *tcr = raw_ptr(env, ri);
 
     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
     tcr->raw_tcr = value;
 }
 
@@ -2492,7 +2492,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     if (cpreg_field_is_64bit(ri)) {
         ARMCPU *cpu = arm_env_get_cpu(env);
 
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
     raw_write(env, ri, value);
 }
@@ -3160,7 +3160,7 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     raw_write(env, ri, value);
     /* ??? Lots of these bits are not implemented.  */
     /* This may enable/disable the MMU, so do a TLB flush.  */
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3628,7 +3628,7 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
      * HCR_DC Disables stage1 and enables stage2 translation
      */
     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
     raw_write(env, ri, value);
 }
diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c
index 2049a8c..66474ad 100644
--- a/target-i386/fpu_helper.c
+++ b/target-i386/fpu_helper.c
@@ -1465,7 +1465,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
         }
         if (env->pkru != old_pkru) {
             CPUState *cs = CPU(x86_env_get_cpu(env));
-            tlb_flush(cs, 1);
+            tlb_flush(cs);
         }
     }
 }
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 4ecc091..20a6dfc 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -586,7 +586,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
 
         /* when a20 is changed, all the MMU mappings are invalid, so
            we must flush everything */
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
         env->a20_mask = ~(1 << 20) | (a20_state << 20);
     }
 }
@@ -599,7 +599,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
     qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
     if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
         (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 
 #ifdef TARGET_X86_64
@@ -641,7 +641,7 @@ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
     if (env->cr[0] & CR0_PG_MASK) {
         qemu_log_mask(CPU_LOG_MMU,
                         "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
-        tlb_flush(CPU(cpu), 0);
+        tlb_flush(CPU(cpu));
     }
 }
 
@@ -656,7 +656,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
     if ((new_cr4 ^ env->cr[4]) &
         (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
          CR4_SMEP_MASK | CR4_SMAP_MASK)) {
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 
     /* Clear bits we're going to recompute.  */
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 760f82b..e002b4f 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -387,7 +387,7 @@ static int cpu_post_load(void *opaque, int version_id)
         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
         cpu_x86_update_dr7(env, dr7);
     }
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 
     if (tcg_enabled()) {
         cpu_smm_update(cpu);
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index 3f666b4..5029efe 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -635,5 +635,5 @@ void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
     }
 
     env->pkru = val;
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 }
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 782b3f1..210f6aa 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -289,7 +289,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
         break;
     case TLB_CONTROL_FLUSH_ALL_ASID:
         /* FIXME: this is not 100% correct but should work for now */
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
         break;
     }
 
diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
index a22a496..a0f0675 100644
--- a/target-microblaze/mmu.c
+++ b/target-microblaze/mmu.c
@@ -255,7 +255,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
             /* Changes to the zone protection reg flush the QEMU TLB.
                Fortunately, these are very uncommon.  */
             if (v != env->mmu.regs[rn]) {
-                tlb_flush(CPU(cpu), 1);
+                tlb_flush(CPU(cpu));
             }
             env->mmu.regs[rn] = v;
             break;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3146a60..e1c78f5 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -1054,7 +1054,7 @@ static inline void compute_hflags(CPUMIPSState *env)
     }
 }
 
-void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global);
+void cpu_mips_tlb_flush(CPUMIPSState *env);
 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
diff --git a/target-mips/helper.c b/target-mips/helper.c
index c864b15..d2e7795 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -223,12 +223,12 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
     return ret;
 }
 
-void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
+void cpu_mips_tlb_flush(CPUMIPSState *env)
 {
     MIPSCPU *cpu = mips_env_get_cpu(env);
 
     /* Flush qemu's TLB and discard all shadowed entries.  */
-    tlb_flush(CPU(cpu), flush_global);
+    tlb_flush(CPU(cpu));
     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
 
@@ -290,7 +290,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
 #if defined(TARGET_MIPS64)
     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
         /* Access to at least one of the 64-bit segments has been disabled */
-        cpu_mips_tlb_flush(env, 1);
+        cpu_mips_tlb_flush(env);
     }
 #endif
     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 7af4c2f..9ba4cb4 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1431,7 +1431,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
     /* If the ASID changes, flush qemu's TLB.  */
     if ((old & env->CP0_EntryHi_ASID_mask) !=
         (val & env->CP0_EntryHi_ASID_mask)) {
-        cpu_mips_tlb_flush(env, 1);
+        cpu_mips_tlb_flush(env);
     }
 }
 
@@ -2021,7 +2021,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env)
             tlb->EHINV = 1;
         }
     }
-    cpu_mips_tlb_flush(env, 1);
+    cpu_mips_tlb_flush(env);
 }
 
 void r4k_helper_tlbinvf(CPUMIPSState *env)
@@ -2031,7 +2031,7 @@ void r4k_helper_tlbinvf(CPUMIPSState *env)
     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
     }
-    cpu_mips_tlb_flush(env, 1);
+    cpu_mips_tlb_flush(env);
 }
 
 void r4k_helper_tlbwi(CPUMIPSState *env)
@@ -2145,7 +2145,7 @@ void r4k_helper_tlbr(CPUMIPSState *env)
 
     /* If this will change the current ASID, flush qemu's TLB.  */
     if (ASID != tlb->ASID)
-        cpu_mips_tlb_flush (env, 1);
+        cpu_mips_tlb_flush (env);
 
     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
 
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 5fe3f11..e43fc84 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -45,7 +45,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
 
     /* For machine-state changed between user-mode and supervisor mode,
        we need flush TLB when we enter&exit EXCP.  */
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 
     env->esr = env->sr;
     env->sr &= ~SR_DME;
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
index 116f9109..0ed5146 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -53,7 +53,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
     }
 
     if (need_flush_tlb) {
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
     }
 #endif
     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index a719e45..daea902 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -47,7 +47,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 17): /* SR */
         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
             (rb & (SR_IME | SR_DME | SR_SM))) {
-            tlb_flush(cs, 1);
+            tlb_flush(cs);
         }
         env->sr = rb;
         env->sr |= SR_FO;      /* FO is const equal to 1 */
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index bb9ce60..22c016b 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -158,7 +158,7 @@ static inline void check_tlb_flush(CPUPPCState *env, bool global)
 {
     CPUState *cs = CPU(ppc_env_get_cpu(env));
     if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
     }
 
@@ -173,7 +173,7 @@ static inline void check_tlb_flush(CPUPPCState *env, bool global)
                 CPUPPCState *other_env = &cpu->env;
 
                 other_env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
-                tlb_flush(other_cs, 1);
+                tlb_flush(other_cs);
             }
         }
         env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
index 1e6e705..ab432ba 100644
--- a/target-ppc/misc_helper.c
+++ b/target-ppc/misc_helper.c
@@ -85,7 +85,7 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
     if (!env->external_htab) {
         if (env->spr[SPR_SDR1] != val) {
             ppc_store_sdr1(env, val);
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
     }
 }
@@ -114,7 +114,7 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
     if (likely(env->pb[num] != value)) {
         env->pb[num] = value;
         /* Should be optimized */
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 }
 
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index d09fc0a..f746f53 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -248,7 +248,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
         tlb = &env->tlb.tlb6[nr];
         pte_invalidate(&tlb->pte0);
     }
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
@@ -661,7 +661,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
         tlb = &env->tlb.tlbe[i];
         tlb->prot &= ~PAGE_VALID;
     }
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
@@ -863,7 +863,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags,
         tlb += booke206_tlb_size(env, i);
     }
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
@@ -1769,7 +1769,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
 #if !defined(FLUSH_ALL_TLBS)
         do_invalidate_BAT(env, env->IBAT[0][nr], mask);
 #else
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
 #endif
     }
 }
@@ -1804,7 +1804,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
 #if !defined(FLUSH_ALL_TLBS)
         do_invalidate_BAT(env, env->DBAT[0][nr], mask);
 #else
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
 #endif
     }
 }
@@ -1852,7 +1852,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
         }
 #if defined(FLUSH_ALL_TLBS)
         if (do_inval) {
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
 #endif
     }
@@ -1892,7 +1892,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
         env->DBAT[1][nr] = value;
 #if defined(FLUSH_ALL_TLBS)
         if (do_inval) {
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
 #endif
     }
@@ -1921,7 +1921,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
         cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
         break;
     case POWERPC_MMU_BOOKE:
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
         break;
     case POWERPC_MMU_BOOKE206:
         booke206_flush_tlb(env, -1, 0);
@@ -1937,7 +1937,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
     case POWERPC_MMU_2_07a:
 #endif /* defined(TARGET_PPC64) */
         env->tlb_need_flush = 0;
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
         break;
     default:
         /* XXX: TODO */
@@ -2433,13 +2433,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
         }
         tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
         if (do_flush_tlbs) {
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
         break;
     case 1:
         RPN = value & 0xFFFFFC0F;
         if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
         tlb->RPN = RPN;
         break;
@@ -2555,7 +2555,7 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
 
     env->spr[pidn] = pid;
     /* changing PIDs mean we're in a different address space now */
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void helper_booke206_tlbwe(CPUPPCState *env)
@@ -2650,7 +2650,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
     if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
         tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
     } else {
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 }
 
@@ -2775,7 +2775,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
         /* flush TLB1 entries */
         booke206_invalidate_ea_tlb(env, 1, address);
         CPU_FOREACH(cs) {
-            tlb_flush(cs, 1);
+            tlb_flush(cs);
         }
     } else {
         /* flush TLB0 entries */
@@ -2811,7 +2811,7 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
         }
         tlb += booke206_tlb_size(env, i);
     }
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
@@ -2852,7 +2852,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
             tlb->mas1 &= ~MAS1_VALID;
         }
     }
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type)
diff --git a/target-s390x/gdbstub.c b/target-s390x/gdbstub.c
index 3d223de..ea4dc22 100644
--- a/target-s390x/gdbstub.c
+++ b/target-s390x/gdbstub.c
@@ -199,7 +199,7 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
     case S390_C0_REGNUM ... S390_C15_REGNUM:
         env->cregs[n] = ldtul_p(mem_buf);
         if (tcg_enabled()) {
-            tlb_flush(ENV_GET_CPU(env), 1);
+            tlb_flush(ENV_GET_CPU(env));
         }
         cpu_synchronize_post_init(ENV_GET_CPU(env));
         return 8;
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 99bc5e2..675aba2 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -872,7 +872,7 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
         s390_cpu_recompute_watchpoints(CPU(cpu));
     }
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
@@ -900,7 +900,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
         s390_cpu_recompute_watchpoints(CPU(cpu));
     }
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
@@ -1036,7 +1036,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
         cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]);
         if (r2 & 0x3) {
             /* flush TLB / ALB */
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
         }
         cc = 0;
     } else {
@@ -1121,7 +1121,7 @@ void HELPER(ptlb)(CPUS390XState *env)
 {
     S390CPU *cpu = s390_env_get_cpu(env);
 
-    tlb_flush(CPU(cpu), 1);
+    tlb_flush(CPU(cpu));
 }
 
 /* load using real address */
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index a33ac69..036c5ca 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -583,7 +583,7 @@ void cpu_load_tlb(CPUSH4State * env)
         entry->v = 0;
     }
 
-    tlb_flush(CPU(sh_env_get_cpu(s)), 1);
+    tlb_flush(CPU(sh_env_get_cpu(s)));
 }
 
 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index de7d53a..a0171f7 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -816,7 +816,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
             case 2: /* flush region (16M) */
             case 3: /* flush context (4G) */
             case 4: /* flush entire */
-                tlb_flush(CPU(cpu), 1);
+                tlb_flush(CPU(cpu));
                 break;
             default:
                 break;
@@ -841,7 +841,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
                    are invalid in normal mode.  */
                 if ((oldreg ^ env->mmuregs[reg])
                     & (MMU_NF | env->def->mmu_bm)) {
-                    tlb_flush(CPU(cpu), 1);
+                    tlb_flush(CPU(cpu));
                 }
                 break;
             case 1: /* Context Table Pointer Register */
@@ -852,7 +852,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
                 if (oldreg != env->mmuregs[reg]) {
                     /* we flush when the MMU context changes because
                        QEMU has no MMU context support */
-                    tlb_flush(CPU(cpu), 1);
+                    tlb_flush(CPU(cpu));
                 }
                 break;
             case 3: /* Synchronous Fault Status Register with Clear */
@@ -1509,13 +1509,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
                 env->dmmu.mmu_primary_context = val;
                 /* can be optimized to only flush MMU_USER_IDX
                    and MMU_KERNEL_IDX entries */
-                tlb_flush(CPU(cpu), 1);
+                tlb_flush(CPU(cpu));
                 break;
             case 2: /* Secondary context */
                 env->dmmu.mmu_secondary_context = val;
                 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
                    and MMU_KERNEL_SECONDARY_IDX entries */
-                tlb_flush(CPU(cpu), 1);
+                tlb_flush(CPU(cpu));
                 break;
             case 5: /* TSB access */
                 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
@@ -1654,7 +1654,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
     /* flush neverland mappings created during no-fault mode,
        so the sequential MMU faults report proper fault types */
     if (env->mmuregs[0] & MMU_NF) {
-        tlb_flush(cs, 1);
+        tlb_flush(cs);
     }
 }
 #else
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index c169972..c9b78ce 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -133,7 +133,7 @@ static void uc32_cpu_initfn(Object *obj)
     env->regs[31] = 0x03000000;
 #endif
 
-    tlb_flush(cs, 1);
+    tlb_flush(cs);
 
     if (tcg_enabled() && !inited) {
         inited = true;
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index d603bde..9454efa 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -116,7 +116,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
     case 6:
         if ((cop <= 6) && (cop >= 2)) {
             /* invalid all tlb */
-            tlb_flush(CPU(cpu), 1);
+            tlb_flush(CPU(cpu));
             return;
         }
         break;
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 0a4b214..63c89f8 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -492,7 +492,7 @@ void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
     v = (v & 0xffffff00) | 0x1;
     if (v != env->sregs[RASID]) {
         env->sregs[RASID] = v;
-        tlb_flush(CPU(cpu), 1);
+        tlb_flush(CPU(cpu));
     }
 }
 
-- 
2.10.1

^ permalink raw reply related

* [RFC 1/2] qom/cpu: move tlb_flush to cpu_common_reset
From: Alex Bennée @ 2016-11-14 17:40 UTC (permalink / raw)
  To: rth
  Cc: qemu-devel, Alex Bennée, Peter Maydell, Edgar E. Iglesias,
	Paolo Bonzini, Eduardo Habkost, Michael Walle, Laurent Vivier,
	Aurelien Jarno, Yongbok Kim, Anthony Green, Jia Liu, David Gibson,
	Alexander Graf, Mark Cave-Ayland, Artyom Tarasenko,
	Bastian Koppelmann, open list:ARM, open list:PowerPC
In-Reply-To: <20161114174010.31040-1-alex.bennee@linaro.org>

It is a common thing amongst the various cpu reset functions want to
flush the SoftMMU's TLB entries. This is done either by calling
tlb_flush directly or by way of a general memset of the CPU
structure (sometimes both).

This moves the tlb_flush call to the common reset function and
additionally ensures it is only done for the CONFIG_SOFTMMU case and
when tcg is enabled.

In some target cases we add an empty end_of_reset_fields structure to the
target vCPU structure so have a clear end point for any memset which
is resetting value in the structure before CPU_COMMON (where the TLB
structures are).

While this is a nice clean-up in general it is also a precursor for
changes coming to cputlb for MTTCG where the clearing of entries
can't be done arbitrarily across vCPUs. Currently the cpu_reset
function is usually called from the context of another vCPU as the
architectural power up sequence is run. By using the cputlb API
functions we can ensure the right behaviour in the future.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 qom/cpu.c                   | 10 ++++++++--
 target-arm/cpu.c            |  5 ++---
 target-arm/cpu.h            |  5 ++++-
 target-cris/cpu.c           |  3 +--
 target-cris/cpu.h           |  9 ++++++---
 target-i386/cpu.c           |  2 --
 target-i386/cpu.h           |  6 ++++--
 target-lm32/cpu.c           |  3 +--
 target-lm32/cpu.h           |  3 +++
 target-m68k/cpu.c           |  3 +--
 target-m68k/cpu.h           |  3 +++
 target-microblaze/cpu.c     |  3 +--
 target-microblaze/cpu.h     |  3 +++
 target-mips/cpu.c           |  3 +--
 target-mips/cpu.h           |  3 +++
 target-moxie/cpu.c          |  4 +---
 target-moxie/cpu.h          |  3 +++
 target-openrisc/cpu.c       |  9 +--------
 target-openrisc/cpu.h       |  3 +++
 target-ppc/translate_init.c |  3 ---
 target-s390x/cpu.c          |  7 ++-----
 target-s390x/cpu.h          |  5 +++--
 target-sh4/cpu.c            |  3 +--
 target-sh4/cpu.h            |  3 +++
 target-sparc/cpu.c          |  3 +--
 target-sparc/cpu.h          |  3 +++
 target-tilegx/cpu.c         |  3 +--
 target-tilegx/cpu.h         |  3 +++
 target-tricore/cpu.c        |  2 --
 29 files changed, 66 insertions(+), 52 deletions(-)

diff --git a/qom/cpu.c b/qom/cpu.c
index 03d9190..61ee0cb 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -270,8 +270,14 @@ static void cpu_common_reset(CPUState *cpu)
     cpu->exception_index = -1;
     cpu->crash_occurred = false;
 
-    for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {
-        atomic_set(&cpu->tb_jmp_cache[i], NULL);
+    if (tcg_enabled()) {
+        for (i = 0; i < TB_JMP_CACHE_SIZE; ++i) {
+            atomic_set(&cpu->tb_jmp_cache[i], NULL);
+        }
+
+#ifdef CONFIG_SOFTMMU
+        tlb_flush(cpu, 0);
+#endif
     }
 }
 
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 99f0dbe..fb05d2e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -122,7 +122,8 @@ static void arm_cpu_reset(CPUState *s)
 
     acc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUARMState, features));
+    memset(env, 0, offsetof(CPUARMState, end_reset_fields));
+
     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 
@@ -226,8 +227,6 @@ static void arm_cpu_reset(CPUState *s)
                               &env->vfp.fp_status);
     set_float_detect_tininess(float_tininess_before_rounding,
                               &env->vfp.standard_fp_status);
-    tlb_flush(s, 1);
-
 #ifndef CONFIG_USER_ONLY
     if (kvm_enabled()) {
         kvm_arm_reset_vcpu(cpu);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ca5c849..53e9d55 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -491,9 +491,12 @@ typedef struct CPUARMState {
     struct CPUBreakpoint *cpu_breakpoint[16];
     struct CPUWatchpoint *cpu_watchpoint[16];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
-    /* These fields after the common ones so they are preserved on reset.  */
+    /* Fields after CPU_COMMON are preserved across CPU reset. */
 
     /* Internal CPU feature flags.  */
     uint64_t features;
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 2e9ab97..5f766f0 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -52,9 +52,8 @@ static void cris_cpu_reset(CPUState *s)
     ccc->parent_reset(s);
 
     vr = env->pregs[PR_VR];
-    memset(env, 0, offsetof(CPUCRISState, load_info));
+    memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
     env->pregs[PR_VR] = vr;
-    tlb_flush(s, 1);
 
 #if defined(CONFIG_USER_ONLY)
     /* start in user mode with interrupts enabled.  */
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 43d5f9d..920e1c3 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -167,10 +167,13 @@ typedef struct CPUCRISState {
 	 */
         TLBSet tlbsets[2][4][16];
 
-	CPU_COMMON
+        /* Fields up to this point are cleared by a CPU reset */
+        struct {} end_reset_fields;
 
-    /* Members from load_info on are preserved across resets.  */
-    void *load_info;
+        CPU_COMMON
+
+        /* Members from load_info on are preserved across resets.  */
+        void *load_info;
 } CPUCRISState;
 
 /**
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 6eec5dc..9dbc7fc 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2820,8 +2820,6 @@ static void x86_cpu_reset(CPUState *s)
 
     memset(env, 0, offsetof(CPUX86State, end_reset_fields));
 
-    tlb_flush(s, 1);
-
     env->old_exception = -1;
 
     /* init to reset state */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c605724..95ed91d 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1119,10 +1119,12 @@ typedef struct CPUX86State {
     uint8_t nmi_injected;
     uint8_t nmi_pending;
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
-    /* Fields from here on are preserved across CPU reset. */
-    struct {} end_reset_fields;
+    /* Fields after CPU_COMMON are preserved across CPU reset. */
 
     /* processor features (e.g. for CPUID insn) */
     /* Minimum level/xlevel/xlevel2, based on CPU model + features */
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 8d939a7..2b8c36b 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -128,10 +128,9 @@ static void lm32_cpu_reset(CPUState *s)
     lcc->parent_reset(s);
 
     /* reset cpu state */
-    memset(env, 0, offsetof(CPULM32State, eba));
+    memset(env, 0, offsetof(CPULM32State, end_reset_fields));
 
     lm32_cpu_init_cfg_reg(cpu);
-    tlb_flush(s, 1);
 }
 
 static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index d8a3515..1d972cb 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -165,6 +165,9 @@ struct CPULM32State {
     struct CPUBreakpoint *cpu_breakpoint[4];
     struct CPUWatchpoint *cpu_watchpoint[4];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index ba17480..fa10b6e 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -52,7 +52,7 @@ static void m68k_cpu_reset(CPUState *s)
 
     mcc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUM68KState, features));
+    memset(env, 0, offsetof(CPUM68KState, end_reset_fields));
 #if !defined(CONFIG_USER_ONLY)
     env->sr = 0x2700;
 #endif
@@ -61,7 +61,6 @@ static void m68k_cpu_reset(CPUState *s)
     cpu_m68k_set_ccr(env, 0);
     /* TODO: We should set PC from the interrupt vector.  */
     env->pc = 0;
-    tlb_flush(s, 1);
 }
 
 static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info)
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 6dfb54e..8e7b51b 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -115,6 +115,9 @@ typedef struct CPUM68KState {
 
     uint32_t qregs[MAX_QREGS];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 389c7b6..3d58869 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -103,9 +103,8 @@ static void mb_cpu_reset(CPUState *s)
 
     mcc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUMBState, pvr));
+    memset(env, 0, offsetof(CPUMBState, end_reset_fields));
     env->res_addr = RES_ADDR_NONE;
-    tlb_flush(s, 1);
 
     /* Disable stack protector.  */
     env->shr = ~0;
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index beb75ff..bf6963b 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -267,6 +267,9 @@ struct CPUMBState {
     struct microblaze_mmu mmu;
 #endif
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* These fields are preserved on reset.  */
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 65ca607..1bb66b7 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -100,8 +100,7 @@ static void mips_cpu_reset(CPUState *s)
 
     mcc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUMIPSState, mvp));
-    tlb_flush(s, 1);
+    memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 
     cpu_state_reset(env);
 
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 5182dc7..3146a60 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -607,6 +607,9 @@ struct CPUMIPSState {
     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
     int insn_flags; /* Supported instruction set */
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index b0be4a7..927b1a1 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -45,10 +45,8 @@ static void moxie_cpu_reset(CPUState *s)
 
     mcc->parent_reset(s);
 
-    memset(env, 0, sizeof(CPUMoxieState));
+    memset(env, 0, offsetof(CPUMoxieState, end_reset_fields));
     env->pc = 0x1000;
-
-    tlb_flush(s, 1);
 }
 
 static void moxie_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index 3e880fa..8991aae 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -56,6 +56,9 @@ typedef struct CPUMoxieState {
 
     void *irq[8];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
 } CPUMoxieState;
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 698e87b..422139d 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -44,14 +44,7 @@ static void openrisc_cpu_reset(CPUState *s)
 
     occ->parent_reset(s);
 
-#ifndef CONFIG_USER_ONLY
-    memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb));
-#else
-    memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
-#endif
-
-    tlb_flush(s, 1);
-    /*tb_flush(&cpu->env);    FIXME: Do we need it?  */
+    memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
 
     cpu->env.pc = 0x100;
     cpu->env.sr = SR_FO | SR_SM;
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index aaf1535..508ef56 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -300,6 +300,9 @@ typedef struct CPUOpenRISCState {
                                  in solt so far.  */
     uint32_t btaken;          /* the SR_F bit */
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 208fa1e..9f753ae 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10415,9 +10415,6 @@ static void ppc_cpu_reset(CPUState *s)
         }
         env->spr[i] = spr->default_value;
     }
-
-    /* Flush all TLBs */
-    tlb_flush(s, 1);
 }
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 0a39d31..066dcd1 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -82,7 +82,6 @@ static void s390_cpu_reset(CPUState *s)
     scc->parent_reset(s);
     cpu->env.sigp_order = 0;
     s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
-    tlb_flush(s, 1);
 }
 
 /* S390CPUClass::initial_reset() */
@@ -94,7 +93,7 @@ static void s390_cpu_initial_reset(CPUState *s)
 
     s390_cpu_reset(s);
     /* initial reset does not touch regs,fregs and aregs */
-    memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) -
+    memset(&env->fpc, 0, offsetof(CPUS390XState, end_reset_fields) -
                          offsetof(CPUS390XState, fpc));
 
     /* architectured initial values for CR 0 and 14 */
@@ -118,7 +117,6 @@ static void s390_cpu_initial_reset(CPUState *s)
     if (kvm_enabled()) {
         kvm_s390_reset_vcpu(cpu);
     }
-    tlb_flush(s, 1);
 }
 
 /* CPUClass:reset() */
@@ -133,7 +131,7 @@ static void s390_cpu_full_reset(CPUState *s)
     cpu->env.sigp_order = 0;
     s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
 
-    memset(env, 0, offsetof(CPUS390XState, cpu_num));
+    memset(env, 0, offsetof(CPUS390XState, end_reset_fields));
 
     /* architectured initial values for CR 0 and 14 */
     env->cregs[0] = CR0_RESET;
@@ -156,7 +154,6 @@ static void s390_cpu_full_reset(CPUState *s)
     if (kvm_enabled()) {
         kvm_s390_reset_vcpu(cpu);
     }
-    tlb_flush(s, 1);
 }
 
 #if !defined(CONFIG_USER_ONLY)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index fd36a25..058ddad 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -139,9 +139,10 @@ typedef struct CPUS390XState {
 
     uint8_t riccb[64];
 
-    CPU_COMMON
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
 
-    /* reset does memset(0) up to here */
+    CPU_COMMON
 
     uint32_t cpu_num;
     uint32_t machine_type;
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index a38f6a6..9a481c3 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -56,8 +56,7 @@ static void superh_cpu_reset(CPUState *s)
 
     scc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUSH4State, id));
-    tlb_flush(s, 1);
+    memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
 
     env->pc = 0xA0000000;
 #if defined(CONFIG_USER_ONLY)
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 478ab55..cad8989 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -175,6 +175,9 @@ typedef struct CPUSH4State {
 
     uint32_t ldst;
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved over CPU reset. */
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 4e07b92..d6583f1 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -36,8 +36,7 @@ static void sparc_cpu_reset(CPUState *s)
 
     scc->parent_reset(s);
 
-    memset(env, 0, offsetof(CPUSPARCState, version));
-    tlb_flush(s, 1);
+    memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
     env->cwp = 0;
 #ifndef TARGET_SPARC64
     env->wim = 1;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 5fb0ed1..601c018 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -419,6 +419,9 @@ struct CPUSPARCState {
     /* NOTE: we allow 8 more registers to handle wrapping */
     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 
     /* Fields from here on are preserved across CPU reset. */
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
index 454793f..d90e38e 100644
--- a/target-tilegx/cpu.c
+++ b/target-tilegx/cpu.c
@@ -84,8 +84,7 @@ static void tilegx_cpu_reset(CPUState *s)
 
     tcc->parent_reset(s);
 
-    memset(env, 0, sizeof(CPUTLGState));
-    tlb_flush(s, 1);
+    memset(env, 0, offsetof(CPUTLGState, end_reset_fields));
 }
 
 static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 1735427..f32be49 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -97,6 +97,9 @@ typedef struct CPUTLGState {
     uint32_t sigcode;                  /* Signal code */
 #endif
 
+    /* Fields up to this point are cleared by a CPU reset */
+    struct {} end_reset_fields;
+
     CPU_COMMON
 } CPUTLGState;
 
diff --git a/target-tricore/cpu.c b/target-tricore/cpu.c
index 785b76b..08f50e2 100644
--- a/target-tricore/cpu.c
+++ b/target-tricore/cpu.c
@@ -53,8 +53,6 @@ static void tricore_cpu_reset(CPUState *s)
 
     tcc->parent_reset(s);
 
-    tlb_flush(s, 1);
-
     cpu_state_reset(env);
 }
 
-- 
2.10.1

^ permalink raw reply related

* [PATCH] glib: remove obsolete gi-exclude patch
From: Ross Burton @ 2016-11-14 17:39 UTC (permalink / raw)
  To: openembedded-core

This patch has been superseded by 2907b1 in gobject-introspection, which we're
now shipping.

Signed-off-by: Ross Burton <ross.burton@intel.com>
---
 .../glib-2.0/glib-2.0/gi-exclude.patch             | 59 ----------------------
 meta/recipes-core/glib-2.0/glib-2.0_2.50.1.bb      |  1 -
 2 files changed, 60 deletions(-)
 delete mode 100644 meta/recipes-core/glib-2.0/glib-2.0/gi-exclude.patch

diff --git a/meta/recipes-core/glib-2.0/glib-2.0/gi-exclude.patch b/meta/recipes-core/glib-2.0/glib-2.0/gi-exclude.patch
deleted file mode 100644
index dc62b92..0000000
--- a/meta/recipes-core/glib-2.0/glib-2.0/gi-exclude.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-The autoptr types should be excluded from gobject-introspection parsing as
-they're not user-facing.
-
-Upstream-Status: Submitted
-Signed-off-by: Ross Burton <ross.burton@intel.com>
-
-diff --git a/gio/gio-autocleanups.h b/gio/gio-autocleanups.h
-index a95ba65..24ccc2d 100644
---- a/gio/gio-autocleanups.h
-+++ b/gio/gio-autocleanups.h
-@@ -21,6 +21,8 @@
- #error "Only <gio/gio.h> can be included directly."
- #endif
- 
-+#ifndef __GI_SCANNER__
-+
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GAction, g_object_unref)
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GActionMap, g_object_unref)
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GAppInfo, g_object_unref)
-@@ -146,3 +148,5 @@ G_DEFINE_AUTOPTR_CLEANUP_FUNC(GVolume, g_object_unref)
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GVolumeMonitor, g_object_unref)
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GZlibCompressor, g_object_unref)
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GZlibDecompressor, g_object_unref)
-+
-+#endif
-diff --git a/glib/glib-autocleanups.h b/glib/glib-autocleanups.h
-index 6355f75..09d28be 100644
---- a/glib/glib-autocleanups.h
-+++ b/glib/glib-autocleanups.h
-@@ -21,6 +21,8 @@
- #error "Only <glib.h> can be included directly."
- #endif
- 
-+#ifndef __GI_SCANNER__
-+
- static inline void
- g_autoptr_cleanup_generic_gfree (void *p)
- {
-@@ -87,3 +89,5 @@ G_DEFINE_AUTOPTR_CLEANUP_FUNC(GVariantDict, g_variant_dict_unref)
- G_DEFINE_AUTO_CLEANUP_CLEAR_FUNC(GVariantDict, g_variant_dict_clear)
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GVariantType, g_variant_type_free)
- G_DEFINE_AUTO_CLEANUP_FREE_FUNC(GStrv, g_strfreev, NULL)
-+
-+#endif
-diff --git a/gobject/gobject-autocleanups.h b/gobject/gobject-autocleanups.h
-index 980203f..a1d4ba1 100644
---- a/gobject/gobject-autocleanups.h
-+++ b/gobject/gobject-autocleanups.h
-@@ -21,6 +21,10 @@
- #error "Only <glib-object.h> can be included directly."
- #endif
- 
-+#ifndef __GI_SCANNER__
-+
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GObject, g_object_unref)
- G_DEFINE_AUTOPTR_CLEANUP_FUNC(GInitiallyUnowned, g_object_unref)
- G_DEFINE_AUTO_CLEANUP_CLEAR_FUNC(GValue, g_value_unset)
-+
-+#endif
diff --git a/meta/recipes-core/glib-2.0/glib-2.0_2.50.1.bb b/meta/recipes-core/glib-2.0/glib-2.0_2.50.1.bb
index 17016c8..e4fccc7 100644
--- a/meta/recipes-core/glib-2.0/glib-2.0_2.50.1.bb
+++ b/meta/recipes-core/glib-2.0/glib-2.0_2.50.1.bb
@@ -13,7 +13,6 @@ SRC_URI = "${GNOME_MIRROR}/glib/${SHRT_VER}/glib-${PV}.tar.xz \
            file://allow-run-media-sdX-drive-mount-if-username-root.patch \
            file://0001-Remove-the-warning-about-deprecated-paths-in-schemas.patch \
            file://Enable-more-tests-while-cross-compiling.patch \
-           file://gi-exclude.patch \
            file://0001-Install-gio-querymodules-as-libexec_PROGRAM.patch \
            file://0001-Do-not-ignore-return-value-of-write.patch \
            file://0001-Test-for-pthread_getname_np-before-using-it.patch \
-- 
2.8.1



^ permalink raw reply related

* [U-Boot] FDT retrived varaibles appear to have different properties fom other u-boot variables - and are corrupted on get, set, get correction
From: dh at synoia.com @ 2016-11-14 17:39 UTC (permalink / raw)
  To: u-boot
In-Reply-To: <1018758449.3321827.1479082103455@mail.yahoo.com>

?Duncan Hare

714 931 7952

     
----- Forwarded Message -----
 From: "dh at synoia.com" <dh@synoia.com>
 To: "u-boot at lists.denx.de" <u-boot@lists.denx.de> 
Cc: C?dric Schieli <cschieli@gmail.com>
 Sent: Sunday, November 13, 2016 4:08 PM
 Subject: FDT retrived varaibles appear to have different properties fom other u-boot variables - and are corrupted on get, set, get sequence
   
C?dric
I move the fdt to 0x100
fdt move ${fdt_addr}? 100
fdt addr 100

then
fdt get value bootargs /chosen bootargs
printenv bootargs 
bootargs=8250.nr_uarts=1 dma.dmachans=........all the boot args....... (note the space after "uarts=1)

?setenv abc $bootargs fails...as does printenv $bootargs

They I tried

fdt set bootargs /chosen bootargsfdt get value bootargs /chosen bootargsbootargs=8250.nr_uarts=1
The bootargs parameter list is truncated after the first blank.

Something is not right in the world of fdt code.
?Duncan Hare

714 931 7952

      From: C?dric Schieli <cschieli@gmail.com>
 To: dh at synoia.com 
 Sent: Sunday, November 13, 2016 2:21 AM
 Subject: Re: Fw: [U-Boot] Fw: FDT pointer value, passed by the PI firmware, is not set in u-boot
  
Hello Duncan,

2016-11-13 3:04 GMT+01:00 <dh@synoia.com>:

> If appending to "/chosen bootargs" (making it longer), does the fdt command
> automatically relocate the fdt, or does the u-boot script have to do that
> itself?
>
> The fdt doc at http://www.denx.de/wiki/view/ DULG/UBootCmdFDT
> Is quite unclear on how the fdt size is managed, especially when the fdt is
> located close to the end of memory.

I'm not an expert here, but looking at cmd/fdt.c I didn't find any kind of relocation code. So I guess the safe bet is to move the blob before making any (growing) change to the tree:

# load the blob from the firmware provided address (at the end of memory)
fdt addr ${fdt_addr}

# move the blob to the (previously) default location (0x100)
fdt move ${fdt_addr_r}

# make needed changes
setenv bootargs "......."

# boot from the new location
bootz ${kernel_addr_r} - ${fdt_addr_r}


Another solution is to force the firmware to load the blob at a fixed location (as before) by updating config.txt:
device_tree_address=0x100

Regards,
C?dric


   

   

^ permalink raw reply

* [PATCH] Reiser4 port for 4.8
From: Edward Shishkin @ 2016-11-14 17:38 UTC (permalink / raw)
  To: reiserfs-devel; +Cc: Edward Shishkin

Signed-off-by: Edward Shishkin <edward.shishkin@gmail.com>
---
 flush_queue.c  |  2 +-
 page_cache.c   |  3 ++-
 page_cache.h   |  2 --
 status_flags.c | 17 +++++++++++------
 wander.c       |  5 +++--
 5 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/flush_queue.c b/flush_queue.c
index 20b94ea..4a3d550 100644
--- a/flush_queue.c
+++ b/flush_queue.c
@@ -402,7 +402,7 @@ static void end_io_handler(struct bio *bio)
 	int nr_errors = 0;
 	flush_queue_t *fq;
 
-	assert("zam-958", bio->bi_rw & WRITE);
+	assert("zam-958", bio_op(bio) == WRITE);
 
 	/* we expect that bio->private is set to NULL or fq object which is used
 	 * for synchronization and error counting. */
diff --git a/page_cache.c b/page_cache.c
index d318d18..099c00a 100644
--- a/page_cache.c
+++ b/page_cache.c
@@ -398,7 +398,8 @@ int reiser4_page_io(struct page *page, jnode *node, int rw, gfp_t gfp)
 			set_page_writeback(page);
 			unlock_page(page);
 		}
-		reiser4_submit_bio(rw, bio);
+		bio_set_op_attrs(bio, rw, 0);
+		submit_bio(bio);
 		result = 0;
 	} else {
 		unlock_page(page);
diff --git a/page_cache.h b/page_cache.h
index b79dec7..32106f1 100644
--- a/page_cache.h
+++ b/page_cache.h
@@ -18,8 +18,6 @@ extern void reiser4_done_formatted_fake(struct super_block *);
 
 extern reiser4_tree *reiser4_tree_by_page(const struct page *);
 
-#define reiser4_submit_bio(rw, bio) submit_bio((rw), (bio))
-
 extern void reiser4_wait_page_writeback(struct page *);
 static inline void lock_and_wait_page_writeback(struct page *page)
 {
diff --git a/status_flags.c b/status_flags.c
index ef89464..96f9a9d 100644
--- a/status_flags.c
+++ b/status_flags.c
@@ -58,8 +58,8 @@ int reiser4_status_init(reiser4_block_nr block)
 		return -ENOMEM;
 	}
 	lock_page(page);
-	submit_bio(READ, bio);
-	//blk_flush_plug(current);
+	bio_set_op_attrs(bio, READ, 0);
+	submit_bio(bio);
 	wait_on_page_locked(page);
 	if (!PageUptodate(page)) {
 		warning("green-2007",
@@ -155,10 +155,15 @@ int reiser4_status_write(__u64 status, __u64 extended_status, char *message)
 	bio->bi_end_io = reiser4_status_endio;
 	lock_page(get_super_private(sb)->status_page);	/* Safe as nobody should
 							 * touch our page. */
-	/* We can block now, but we have no other choice anyway */
-	submit_bio(WRITE, bio);
-	//blk_flush_plug(current);
-	return 0;		/* We do not wait for io to finish. */
+	/*
+	 * We can block now, but we have no other choice anyway
+	 */
+	bio_set_op_attrs(bio, WRITE, 0);
+	submit_bio(bio);
+	/*
+	 * We do not wait for IO completon
+	 */
+	return 0;
 }
 
 /* Frees the page with status and bio structure. Should be called by disk format
diff --git a/wander.c b/wander.c
index 6c0cd71..407bb5e 100644
--- a/wander.c
+++ b/wander.c
@@ -708,7 +708,7 @@ static int write_jnodes_to_disk_extent(
 	flush_queue_t *fq, int flags)
 {
 	struct super_block *super = reiser4_get_current_sb();
-	int write_op = ( flags & WRITEOUT_FLUSH_FUA ) ? WRITE_FLUSH_FUA : WRITE;
+	int op_flags = (flags & WRITEOUT_FLUSH_FUA) ? WRITE_FLUSH_FUA : 0;
 	jnode *cur = first;
 	reiser4_block_nr block;
 
@@ -836,7 +836,8 @@ static int write_jnodes_to_disk_extent(
 			else {
 				add_fq_to_bio(fq, bio);
 				bio_get(bio);
-				reiser4_submit_bio(write_op, bio);
+				bio_set_op_attrs(bio, WRITE, op_flags);
+				submit_bio(bio);
 				bio_put(bio);
 			}
 
-- 
2.7.4


^ permalink raw reply related

* Re: [PATCH v2 2/2] mtd: nand: tango: Enable custom page accessors
From: Boris Brezillon @ 2016-11-14 17:38 UTC (permalink / raw)
  To: Marc Gonzalez; +Cc: Richard Weinberger, linux-mtd, Mason, Sebastian Frias
In-Reply-To: <5829EF25.70202@sigmadesigns.com>

On Mon, 14 Nov 2016 18:06:45 +0100
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> wrote:

> Enable NAND_ECC_CUSTOM_PAGE_ACCESS in tango NFC driver.
> Fixup "raw" page accessors to send proper NAND commands.
> Drop raw_write/raw_read return values (no longer used).

I'd still prefer to have two separate patches:

1/ change the raw_read() raw_write() prototypes
2/ switch to NAND_ECC_CUSTOM_PAGE_ACCESS

> 
> Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
> ---
> v2:
> split from previous v1 patch
> ---
>  drivers/mtd/nand/tango_nand.c | 21 ++++++++++++---------
>  1 file changed, 12 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/mtd/nand/tango_nand.c b/drivers/mtd/nand/tango_nand.c
> index fd8cf414cb2b..7ed35348993e 100644
> --- a/drivers/mtd/nand/tango_nand.c
> +++ b/drivers/mtd/nand/tango_nand.c
> @@ -343,7 +343,7 @@ static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos)
>   * buf = |      PKT_0      | ... |      PKT_N      |
>   *       +-----------------+-----+-----------------+
>   */
> -static int raw_read(struct nand_chip *chip, u8 *buf, u8 *oob)
> +static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob)
>  {
>  	u8 *oob_orig = oob;
>  	const int page_size = chip->mtd.writesize;
> @@ -367,11 +367,9 @@ static int raw_read(struct nand_chip *chip, u8 *buf, u8 *oob)
>  	aux_read(chip, &oob_orig, BBM_SIZE, &pos);
>  	aux_read(chip, &buf, pkt_size - rem, &pos);
>  	aux_read(chip, &oob, ecc_size, &pos);
> -
> -	return 0;
>  }
>  
> -static int raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
> +static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
>  {
>  	const u8 *oob_orig = oob;
>  	const int page_size = chip->mtd.writesize;
> @@ -395,27 +393,31 @@ static int raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
>  	aux_write(chip, &oob_orig, BBM_SIZE, &pos);
>  	aux_write(chip, &buf, pkt_size - rem, &pos);
>  	aux_write(chip, &oob, ecc_size, &pos);
> -
> -	return 0;
>  }
>  
>  static int tango_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
>  			       u8 *buf, int oob_required, int page)
>  {
> -	return raw_read(chip, buf, chip->oob_poi);
> +	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
> +	raw_read(chip, buf, chip->oob_poi);
> +	return 0;
>  }
>  
>  static int tango_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
>  				const u8 *buf, int oob_required, int page)
>  {
> -	return raw_write(chip, buf, chip->oob_poi);
> +	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0, page);
> +	raw_write(chip, buf, chip->oob_poi);
> +	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
> +	return 0;
>  }
>  
>  static int tango_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
>  			  int page)
>  {
>  	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
> -	return raw_read(chip, NULL, chip->oob_poi);
> +	raw_read(chip, NULL, chip->oob_poi);
> +	return 0;
>  }
>  
>  static int tango_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
> @@ -553,6 +555,7 @@ static int chip_init(struct device *dev, struct device_node *np)
>  	ecc->write_page = tango_write_page;
>  	ecc->read_oob = tango_read_oob;
>  	ecc->write_oob = tango_write_oob;
> +	ecc->options = NAND_ECC_CUSTOM_PAGE_ACCESS;
>  
>  	err = nand_scan_tail(mtd);
>  	if (err)

^ permalink raw reply

* Re: Clarification for eth_driver changes
From: Ferruh Yigit @ 2016-11-14 17:38 UTC (permalink / raw)
  To: Shreyansh Jain, David Marchand; +Cc: dev@dpdk.org
In-Reply-To: <DB5PR0401MB2054B1B4C5EC1BA8412E8B4090BA0@DB5PR0401MB2054.eurprd04.prod.outlook.com>

On 11/12/2016 5:44 PM, Shreyansh Jain wrote:
> Hello Ferruh,
> 
> (Please ignore if line wrappings are not correct. Using a possibly
> unconfigured mail client).
> 
>> -----Original Message-----
>> From: Ferruh Yigit [mailto:ferruh.yigit@intel.com]
>> Sent: Saturday, November 12, 2016 12:46 AM
>> To: Shreyansh Jain <shreyansh.jain@nxp.com>; David Marchand
>> <david.marchand@6wind.com>
>> Cc: dev@dpdk.org
>> Subject: Re: [dpdk-dev] Clarification for eth_driver changes
>>
>> On 11/10/2016 11:05 AM, Shreyansh Jain wrote:
>>> Hello David,
>>>
>>> On Thursday 10 November 2016 01:46 PM, David Marchand wrote:
>>>> Hello Shreyansh,
>>>>
>>>> On Thu, Nov 10, 2016 at 8:26 AM, Shreyansh Jain <shreyansh.jain@nxp.com>
>> wrote:
>>>>> I need some help and clarification regarding some changes I am doing to
>>>>> cleanup the EAL code.
>>>>>
>>>>> There are some changes which should be done for eth_driver/rte_eth_device
>>>>> structures:
>>>>>
>>>>> 1. most obvious, eth_driver should be renamed to rte_eth_driver.
>>>>> 2. eth_driver currently has rte_pci_driver embedded in it
>>>>>  - there can be ethernet devices which are _not_ PCI
>>>>>  - in which case, this structure should be removed.
>>>>
>>>> Do we really need to keep a eth_driver ?
>>>
>>> No. As you have rightly mentioned below (as well as in your Jan'16
>>> post), it is a mere convenience.
>>
>> Isn't it good to separate the logic related which bus device connected
>> and what functionality it provides. Because these two can be flexible:
> 
> Indeed. The very idea of a Bus model is to make a hierarchy which allows
> for pluggability/flexibility in terms of devices being used. But, until now I
> have only considered placement hierarchy and not functional hierarchy. (more
> below)
> 
>>
>> device -> virtual_bus -> ethernet_functionality
>> device -> pci_bus     -> crypto_functionality
>> device -> x_bus       -> y_function
>>
> 
> Ok.
> 
>>
>> what about:
>>
>> create generic bus driver/device and all eal level deal with generic
>> bus. different buses inherit from generic bus logic
>  
> From what I had in mind: (and very much similar to what you have already 
>                           mentioned in this email)
>  - a generic bus (not a driver, not a device). I don't know how to categorize
>    a bus. It is certainly not a device, and then handler for a bus (physical)
>    can be considered a 'bus driver'. So, just 'rte_bus'.
>  - there is a bus for each physical implementation (or virtual). So, a rte_bus
>    Object for PCI, VDEV, ABC, DEF and so on.
>  - Buses are registered just like a PMD - RTE_PMD_BUS_REGISTER()
>  -- There is a problem of making sure the constructor for bus registration is
>     executed before drivers. Probably by putting the bus code within lib*
>  - Each registered bus is part of a doubly list.
>  - Each device inherits rte_bus
>  - Each driver inherits rte_bus
>  - Existing Device and Drivers lists would be moved into rte_bus
> 
> (more below)
> 
>>
>> create generic functionality device/driver and pmd level deal with
>> these. different functionalities inherit from generic functionality logic
>>
>> and use rte_device/rte_driver as glue logic for all these.
>>
>> This makes easy to add new bus or functionality device/drivers without
>> breaking existing logic.
>>
>>
>> Something like this:
>>
>> struct rte_device {
>> 	char *name;
>> 	struct rte_driver *drv;
>> 	struct rte_bus_device *bus_dev;
>> 	struct rte_funcional_device *func_dev;
>> 	*devargs
>> }
>>
>> struct rte_bus_device {
>> 	struct rte_device *dev;
>> 	/* generic bus device */
>> }
> 
> This is where you lost me. From what I understood from your text:
> (CMIIW)
> 
> - Most abstract class is 'rte_device'.
> - A bus is a device. So, it points to a rte_device
> - But, a rte_device belongs to a bus, so it points to a rte_bus_device.
> 
> Isn't that contradictory?

What I was thinking is:

rte_device/driver are not abstract classes.

rte_bus device/driver is an abstract class and any bus inherited from
this class.
rte_func device/driver is and abstract class and eth/crypto inherited
from this class.

eal layer only deal with rte_bus
pmd's only deal with functional device/driver

but still, it is required to know device <-> driver, and functional <->
bus, relations. rte_dev/rte_driver are to provide this links.

But yes this add extra layer and with second thought I am not sure if it
is really possible to separate bus and functionality, this was just an
idea ..

> 
> This is how I view the physical layout of devices on which DPDK works:
> 
>          +---------+           +----------+
>          |Driver 1A|           |Driver 2B |
>          |servicing|           |servicing | (*)
>          |Bus A    |           |Bus B     |
>          +---------+           +----------+
>                     \             /
>                   +---------+   +-------+
>                   | bus  A  |---| bus B |--- ...
>                   +---------+   +-------+
>                  / \             \  \
>                 /   \_            \  \
>      +---------+     /            /   \
>      | device 1|    /   +--------+     \
>      | on Bus A|   /    |Device 3|     |
>      +---------+  /     |on bus B|     |
>        +---------+      +--------+     |
>        | device 2|             +--------+
>        | on Bus A|             |Device 4|
>        +---------+             |on bus B|
>                                +--------+
> 
>  (*) Multiple drivers servicing a Bus.
> 
> Now, if we introduce the abstraction for functionality (assuming net/crypto) as
> two functionalities currently applicable:
> 
>          +---------+           +----------+
>          |Driver 1A|           |Driver 2B |
>          |servicing|           |servicing | (*)
>          |Bus A    |           |Bus B     |
>          +---------'           +---.------+
>                     \             /
>                   +---------+   +-------+
>                   | bus  A  |---| bus B |--- ...
>                   +---------+   +-------+
>                  / \             \  \
>                 /   \_            \  \
>      +---------'     /            /   \
>      | device 1|    /   +--------'     \
>      | on Bus A|   /    |Device 3|     |
>      +---------+  /     |on bus B|     |
>     /  +---------'      +-|------+     |
>    |   | device 2|        /    +-------'+
>    |   | on Bus A|       /     |Device 4|
>     \  +--|------+ _____/      |on bus B|
>      \    \_____  /            +--------+
>       |      .--\'            /
>       |     /    \        ___/
>     +-'----'-+   +'------'+
>     |Func X  |   |Func Y  |
>     |(Net)   |   |(Crypto)|
>     +--------|   +--------+
> 
> So that means, a device would be a 'net' or 'crypto' device bases on the
> Functionality it attaches to.
> 
> From a physical layout view, is that correct understanding of your argument?
> 
>>
>> struct rte_pci_device {
>> 	struct rte_bus_device bus_dev;
>> 	/* generic pci bus */
>> }
>>
>> struct rte_vdev_device {
>> 	struct rte_bus_device bus_dev;
>> 	/* generic vdev bus */
>> }
>>
>> struct rte_funcional_device {
>> 	struct rte_device *dev;
>> }
> 
> I understand your point of 'pluggable' functionality. It would be helpful if
> same driver would like to move between being a crypto and net. But is that a
> plausible use case for DPDK right now?
> 
> To me, it seems as one more layer of redirection/abstraction.
> 
> This is what the view I have as of now:
> 
>                                   __ rte_bus_list
>                                  /
>                      +----------'---+
>                      |rte_bus       |
>                      | driver_list  |
>                      | device_list  |
>                      | scan         |
>                      | match        |
>                      | remove       |
>                      | ..some refcnt|
>                      +--|------|----+
>               _________/        \_________
>     +--------/----+                     +-\--------------+
>     |rte_device   |                     |rte_driver      |
>     | rte_bus     |                     | rte_bus        |
>     |  flags (3*) |                     | probe (1*)     |
>     |  init       |                     | remove         |
>     |  uninit     |                     | ...            |
>     +---||--------+                     | drv_flags      |
>         ||                              | intr_handle(2*)|
>         | \                             +----------\\\---+
>         |  \_____________                           \\\
>         |                \                          |||
>  +------|---------+ +----|----------+               |||
>  |rte_pci_device  | |rte_xxx_device | (4*)          |||
>  | PCI specific   | | xxx device    |               |||
>  | info (mem,)    | | specific fns  |              / | \
>  +----------------+ +---------------+             /  |  \
>                             _____________________/  /    \
>                            /                    ___/      \
>             +-------------'--+    +------------'---+    +--'------------+
>             |rte_pci_driver  |    |rte_vdev_driver |    |rte_xxx_driver |
>             | PCI id table,  |    | <probably,     |    | ....          |
>             | other driver   |    |  nothing>      |    +---------------+
>             | data           |    +----------------+
>             +----------------+
>     
>     (1*) Problem is that probe functions have different arguments. So,
>          generalizing them might be some rework in the respective device
>          layers

probe() is now done in bus level, right? pci_probe(), vdev_probe(), ...
And I guess, eth_dev and crypto_dev are created during probe(), how
probe() knows if to create eth_dev or crypto_dev?

>     (2*) Interrupt handling for each driver type might be different. I am not
>          sure how to generalize that either. This is grey area for me.
>     (3*) Probably exposing a bitmask for device capabilities. Nothing similar
>          exists now to relate it. Don't know if that is useful. Allowing
>          applications to question a device about what it supports and what it
>          doesn't - making it more flexible at application layer (but more code
>          as well.)
>     (4*) Even vdev would be an instantiated as a device. It is not being done
>          currently.

I think it is good to add this to be consistent.

> 
> So, unlike your model, rte_bus remains the topmost class which is neither a
> device, not a driver. It is just a class.
> Further, as specific information exists in each specific device and driver,
> that is not generalized.
> 

<...>

> 
> I am not against what you have stated. Creating a functional device is just
> one more layer of abstraction in my view. Mostly abstraction/classification
> makes life easier for applications to visualize underlying hierarchy. If this
> serves a purpose, I am OK with that. At least right now, I think it would
> only end up being like eth_driver which is just a holder.

I agree with you, mine was more like a brain exercise, may have gaps and
I need to think more, thanks for your comments.

Thanks,
ferruh

^ permalink raw reply

* Re: [alsa-devel] [RFC 09/14] SoundWire: Add support to handle Slave status change
From: Pierre-Louis Bossart @ 2016-11-14 17:38 UTC (permalink / raw)
  To: Charles Keepax, Hardik Shah
  Cc: alsa-devel, tiwai, plai, lgirdwood, linux-kernel, patches.audio,
	broonie, Sanyog Kale
In-Reply-To: <20161114160805.GO1575@localhost.localdomain>

On 11/14/16 10:08 AM, Charles Keepax wrote:
> There are some issues with this, as the slave driver only probes
> when the device actually shows up on the bus. However often
> (especially in embedded contexts) some things may need to be
> done to enable the slave. For example it may be held in reset or
> its power supplies switched off until they are need. As such it
> generally helps if the device probe can be called before it shows
> up on the bus, the device probe can then do the necessary actions
> to enable the device at which point it will show up on the bus.

Yes, this point was made at the LPC miniconference. What's not clear to 
me is if you would want the codec driver to be notified that the bus is 
operational and let it handle things like sideband power management for 
that device, or is someone else needs to know.

^ permalink raw reply

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