* Re: [PATCH v2 1/2] phy: rockchip-inno-usb2: correct clk_ops callback
From: Doug Anderson @ 2016-11-14 18:15 UTC (permalink / raw)
To: William Wu
Cc: Kishon Vijay Abraham I, Heiko Stübner,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
open list:ARM/Rockchip SoC..., devicetree@vger.kernel.org,
Rob Herring, Frank Wang, 黄涛, Brian Norris,
Guenter Roeck
In-Reply-To: <1479106911-16049-2-git-send-email-wulf@rock-chips.com>
William
On Sun, Nov 13, 2016 at 11:01 PM, William Wu <wulf@rock-chips.com> wrote:
> Since we needs to delay ~1ms to wait for 480MHz output clock
> of USB2 PHY to become stable after turn on it, the delay time
> is pretty long for something that's supposed to be "atomic"
> like a clk_enable(). Consider that clk_enable() will disable
> interrupt and that a 1ms interrupt latency is not sensible.
>
> The 480MHz output clock should be handled in prepare callbacks
> which support gate a clk if the operation may sleep.
>
> Signed-off-by: William Wu <wulf@rock-chips.com>
> ---
> drivers/phy/phy-rockchip-inno-usb2.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply
* Re: [qemu patch 2/2] kvmclock: reduce kvmclock difference on migration
From: Marcelo Tosatti @ 2016-11-14 18:15 UTC (permalink / raw)
To: Paolo Bonzini
Cc: kvm, qemu-devel, Dr. David Alan Gilbert, Juan Quintela,
Radim Krcmar, Eduardo Habkost
In-Reply-To: <14044cda-054d-94eb-8d91-7ad3a1e0869e@redhat.com>
On Mon, Nov 14, 2016 at 06:20:29PM +0100, Paolo Bonzini wrote:
>
>
> On 14/11/2016 18:13, Marcelo Tosatti wrote:
> > On Mon, Nov 14, 2016 at 05:43:33PM +0100, Paolo Bonzini wrote:
> >>
> >>
> >> On 14/11/2016 16:40, Marcelo Tosatti wrote:
> >>> static bool kvmclock_src_use_reliable_get_clock(void *opaque)
> >>> {
> >>> KVMClockState *s = opaque;
> >>>
> >>> /*
> >>> * On machine types that support reliable KVM_GET_CLOCK,
> >>> * if host kernel does provide reliable KVM_GET_CLOCK,
> >>> * set src_use_reliable_get_clock=true so that destination
> >>> * avoids reading kvmclock from memory.
> >>> */
> >>> if (s->mach_use_reliable_get_clock && kvm_has_adjust_clock_stable())
> >>> {
> >>> s->src_use_reliable_get_clock = true;
> >>> }
> >>>
> >>> return s->mach_use_reliable_get_clock;
> >>> }
> >>>
> >>>
> >>> Ah, OK, done.
> >>
> >> s->src_use_reliable_get_clock should not be set with
> >> KVM_CHECK_EXTENSION, but rather from the flags returned by KVM_GET_CLOCK.
> >
> > Well, thats not right: What matters is the presence of get_kvmclock_ns
> > which returns a value that the guest sees.
> >
> > get_kernel_monotonic_clock() + kvmclock_offset +
> > (rdtsc() - tsc_timestamp)
> >
> > IOW what the guest sees. And you changed that in
> >
> > commit 108b249c453dd7132599ab6dc7e435a7036c193f
> > Author: Paolo Bonzini <pbonzini@redhat.com>
> > Date: Thu Sep 1 14:21:03 2016 +0200
> >
> > KVM: x86: introduce get_kvmclock_ns
> >
> > And the correct behaviour (once KVM_GET_CLOCK is fixed per
> > previous message to return rdtsc - tsc_timestamp for the
> > non masterclock case) depends on this commit above,
> > not on masterclock.
>
> This commit in turn only gets the correct behavior if
> "vcpu->arch.hv_clock.flags & PVCLOCK_TSC_STABLE_BIT" (and it will be
> changed soon to ka->use_masterclock). KVM_CHECK_EXTENSION can still
> return KVM_CLOCK_TSC_STABLE even if the masterclock is disabled,
> because KVM_CHECK_EXTENSION only tells you which flags are known for
> this version of the KVM module.
What QEMU wants is to use KVM_GET_CLOCK at pre_save independently
of whether masterclock is enabled or not... it just depends
on KVM_GET_CLOCK being correct for the masterclock case
(108b249c453dd7132599ab6dc7e435a7036c193f).
So a "reliable KVM_GET_CLOCK" (that does not timebackward
when masterclock is enabled) is much simpler to userspace
than "whether masterclock is enabled or not".
If you have a reason why that should not be the case,
let me know.
> To see if the masterclock is enabled _now_, you need to check what
> KVM_GET_CLOCK sets in the flags. From the KVM_CLOCK_TSC_STABLE patch:
>
> user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
Again, whether masterclock is enable is independent of
being able to use KVM_GET_CLOCK at pre_save.
^ permalink raw reply
* Re: [Qemu-devel] [qemu patch 2/2] kvmclock: reduce kvmclock difference on migration
From: Marcelo Tosatti @ 2016-11-14 18:15 UTC (permalink / raw)
To: Paolo Bonzini
Cc: kvm, qemu-devel, Dr. David Alan Gilbert, Juan Quintela,
Radim Krcmar, Eduardo Habkost
In-Reply-To: <14044cda-054d-94eb-8d91-7ad3a1e0869e@redhat.com>
On Mon, Nov 14, 2016 at 06:20:29PM +0100, Paolo Bonzini wrote:
>
>
> On 14/11/2016 18:13, Marcelo Tosatti wrote:
> > On Mon, Nov 14, 2016 at 05:43:33PM +0100, Paolo Bonzini wrote:
> >>
> >>
> >> On 14/11/2016 16:40, Marcelo Tosatti wrote:
> >>> static bool kvmclock_src_use_reliable_get_clock(void *opaque)
> >>> {
> >>> KVMClockState *s = opaque;
> >>>
> >>> /*
> >>> * On machine types that support reliable KVM_GET_CLOCK,
> >>> * if host kernel does provide reliable KVM_GET_CLOCK,
> >>> * set src_use_reliable_get_clock=true so that destination
> >>> * avoids reading kvmclock from memory.
> >>> */
> >>> if (s->mach_use_reliable_get_clock && kvm_has_adjust_clock_stable())
> >>> {
> >>> s->src_use_reliable_get_clock = true;
> >>> }
> >>>
> >>> return s->mach_use_reliable_get_clock;
> >>> }
> >>>
> >>>
> >>> Ah, OK, done.
> >>
> >> s->src_use_reliable_get_clock should not be set with
> >> KVM_CHECK_EXTENSION, but rather from the flags returned by KVM_GET_CLOCK.
> >
> > Well, thats not right: What matters is the presence of get_kvmclock_ns
> > which returns a value that the guest sees.
> >
> > get_kernel_monotonic_clock() + kvmclock_offset +
> > (rdtsc() - tsc_timestamp)
> >
> > IOW what the guest sees. And you changed that in
> >
> > commit 108b249c453dd7132599ab6dc7e435a7036c193f
> > Author: Paolo Bonzini <pbonzini@redhat.com>
> > Date: Thu Sep 1 14:21:03 2016 +0200
> >
> > KVM: x86: introduce get_kvmclock_ns
> >
> > And the correct behaviour (once KVM_GET_CLOCK is fixed per
> > previous message to return rdtsc - tsc_timestamp for the
> > non masterclock case) depends on this commit above,
> > not on masterclock.
>
> This commit in turn only gets the correct behavior if
> "vcpu->arch.hv_clock.flags & PVCLOCK_TSC_STABLE_BIT" (and it will be
> changed soon to ka->use_masterclock). KVM_CHECK_EXTENSION can still
> return KVM_CLOCK_TSC_STABLE even if the masterclock is disabled,
> because KVM_CHECK_EXTENSION only tells you which flags are known for
> this version of the KVM module.
What QEMU wants is to use KVM_GET_CLOCK at pre_save independently
of whether masterclock is enabled or not... it just depends
on KVM_GET_CLOCK being correct for the masterclock case
(108b249c453dd7132599ab6dc7e435a7036c193f).
So a "reliable KVM_GET_CLOCK" (that does not timebackward
when masterclock is enabled) is much simpler to userspace
than "whether masterclock is enabled or not".
If you have a reason why that should not be the case,
let me know.
> To see if the masterclock is enabled _now_, you need to check what
> KVM_GET_CLOCK sets in the flags. From the KVM_CLOCK_TSC_STABLE patch:
>
> user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
Again, whether masterclock is enable is independent of
being able to use KVM_GET_CLOCK at pre_save.
^ permalink raw reply
* [refpolicy] su_exec
From: Dominick Grift @ 2016-11-14 18:15 UTC (permalink / raw)
To: refpolicy
In-Reply-To: <67130EC7AFA3FE4E9290B03665B351F40669E4@SE-EX022.groupinfra.com>
On 11/14/2016 05:11 PM, Fakim, Walid wrote:
> Hi Guys,
>
> So for this process am trying to confine, the startup script is using su -c rather than runuser and even though I've got su_exec(mydomain_t) in my te file, it's prompting for a password at startup.
>
> Any thoughts or experience of seeing this before?
>
> Thanks.
>
> Best Regards,
>
> Walid Fakim
>
>
Add pam_rootok.so to /etc/pam.d/su maybe?
Also you may need to allow ":passwd rootok;" permission
If it hit that then the event should show up as a "USER_AVC" in
audit.log (ausearch -m USER_AVC -ts today)
In the past there was a problem with PAMs' SELinux awareness and it was
not logging USER_AVC denials. That should now be fixed.
--
Key fingerprint = 5F4D 3CDB D3F8 3652 FBD8 02D5 3B6C 5F1D 2C7B 6B02
https://sks-keyservers.net/pks/lookup?op=get&search=0x3B6C5F1D2C7B6B02
Dominick Grift
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^ permalink raw reply
* Re: [PATCH 1/1] libsemanage: semanage_seuser_key_create: copy name
From: Stephen Smalley @ 2016-11-14 18:16 UTC (permalink / raw)
To: Nicolas Iooss, selinux
In-Reply-To: <20161112120503.2162-1-nicolas.iooss@m4x.org>
On 11/12/2016 07:05 AM, Nicolas Iooss wrote:
> When removing a login using semanage with Python 3 the following error
> occurs:
>
> # semanage login -l | grep my_user
> my_user user_u
>
> # semanage login --delete my_user
> ValueError: Login mapping for my_user is not defined
>
> This is due to a use-after-free in the swig-generated code for python3
> bindings.
>
> Copy the user name in semanage_seuser_key_create() and free it in
> semanage_seuser_key_free(), like commit eac6f1f1b512 ("libsepol:
> sepol_{bool|iface|user}_key_create: copy name") did.
Thanks, applied.
>
> Signed-off-by: Nicolas Iooss <nicolas.iooss@m4x.org>
> ---
> libsemanage/src/seuser_record.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/libsemanage/src/seuser_record.c b/libsemanage/src/seuser_record.c
> index 8823b1ed1c7b..1ed459486228 100644
> --- a/libsemanage/src/seuser_record.c
> +++ b/libsemanage/src/seuser_record.c
> @@ -33,7 +33,7 @@ struct semanage_seuser {
>
> struct semanage_seuser_key {
> /* This user's name */
> - const char *name;
> + char *name;
> };
>
> int semanage_seuser_key_create(semanage_handle_t * handle,
> @@ -48,7 +48,12 @@ int semanage_seuser_key_create(semanage_handle_t * handle,
> ERR(handle, "out of memory, could not create seuser key");
> return STATUS_ERR;
> }
> - tmp_key->name = name;
> + tmp_key->name = strdup(name);
> + if (!tmp_key->name) {
> + ERR(handle, "out of memory, could not create seuser key");
> + free(tmp_key);
> + return STATUS_ERR;
> + }
>
> *key_ptr = tmp_key;
> return STATUS_SUCCESS;
> @@ -75,7 +80,7 @@ hidden_def(semanage_seuser_key_extract)
>
> void semanage_seuser_key_free(semanage_seuser_key_t * key)
> {
> -
> + free(key->name);
> free(key);
> }
>
>
^ permalink raw reply
* ✗ Fi.CI.BAT: warning for drm/i915: A few DP stragglers
From: Patchwork @ 2016-11-14 18:16 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
In-Reply-To: <1479145447-12907-1-git-send-email-ville.syrjala@linux.intel.com>
== Series Details ==
Series: drm/i915: A few DP stragglers
URL : https://patchwork.freedesktop.org/series/15299/
State : warning
== Summary ==
Series 15299v1 drm/i915: A few DP stragglers
https://patchwork.freedesktop.org/api/1.0/series/15299/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b:
pass -> DMESG-WARN (fi-snb-2520m)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-snb-2520m total:244 pass:211 dwarn:1 dfail:0 fail:0 skip:32
fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
8670f0f0d91190e0d090ee910c73ed83c37cfef5 drm-intel-nightly: 2016y-11m-14d-16h-10m-52s UTC integration manifest
1c9d66a drm/i915: Simplify DP port limited color range bit platform checks
73f4bd0 drm/i915: Kill dp_encoder_is_mst
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2987/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: ✓ Fi.CI.BAT: success for drm/i915: Per-plane rotation leftovers
From: Ville Syrjälä @ 2016-11-14 18:16 UTC (permalink / raw)
To: intel-gfx
In-Reply-To: <20161114174719.16476.13804@emeril.freedesktop.org>
On Mon, Nov 14, 2016 at 05:47:19PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Per-plane rotation leftovers
> URL : https://patchwork.freedesktop.org/series/15290/
> State : success
And series pushed to dinq. Thanks for the reviews.
>
> == Summary ==
>
> Series 15290v1 drm/i915: Per-plane rotation leftovers
> https://patchwork.freedesktop.org/api/1.0/series/15290/revisions/1/mbox/
>
>
> fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
> fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
> fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
> fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
> fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
> fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
> fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
> fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
> fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
> fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
> fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
> fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
> fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
> fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
> fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
> fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
> fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
>
> 8670f0f0d91190e0d090ee910c73ed83c37cfef5 drm-intel-nightly: 2016y-11m-14d-16h-10m-52s UTC integration manifest
> 86c7280 drm/i915: Add horizontal mirroring support for CHV pipe B planes
> c2f2b21 drm/i915: Clean up rotation DSPCNTR/DVSCNTR/etc. setup
> 00f1032 drm/i915: Use & instead if == to check for rotations
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2986/
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: [PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time
From: Doug Anderson @ 2016-11-14 18:17 UTC (permalink / raw)
To: William Wu
Cc: Kishon Vijay Abraham I, Heiko Stübner,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
open list:ARM/Rockchip SoC..., devicetree@vger.kernel.org,
Rob Herring, Frank Wang, 黄涛, Brian Norris,
Guenter Roeck
In-Reply-To: <1479115631-20137-3-git-send-email-wulf@rock-chips.com>
William,
On Mon, Nov 14, 2016 at 1:27 AM, William Wu <wulf@rock-chips.com> wrote:
> We found that the system crashed due to 480MHz output clock of
> USB2 PHY was unstable after clock had been enabled by gpu module.
>
> Theoretically, 1 millisecond is a critical value for 480MHz
> output clock stable time, so we try to change the delay time
> to 1.2 millisecond to avoid this issue.
>
> And the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct
> clk_ops callback") used prepare callbacks instead of enable
> callbacks to support gate a clk if the operation may sleep. So
> we can switch from delay to sleep functions.
>
> Signed-off-by: William Wu <wulf@rock-chips.com>
> ---
> Changes in v3:
> - fix kbuild test error: too few arguments to function 'usleep_range'
>
> Changes in v2:
> - use usleep_range() function instead of mdelay()
>
> drivers/phy/phy-rockchip-inno-usb2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
> index 365e077..0e52b25 100644
> --- a/drivers/phy/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/phy-rockchip-inno-usb2.c
> @@ -166,7 +166,7 @@ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
> return ret;
>
> /* waitting for the clk become stable */
> - mdelay(1);
> + usleep_range(1200, 1300);
Sight nit that you could also fix the spelling from "waitting" to "waiting".
...but that's pre-existing, so:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply
* [PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time
From: Doug Anderson @ 2016-11-14 18:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479115631-20137-3-git-send-email-wulf@rock-chips.com>
William,
On Mon, Nov 14, 2016 at 1:27 AM, William Wu <wulf@rock-chips.com> wrote:
> We found that the system crashed due to 480MHz output clock of
> USB2 PHY was unstable after clock had been enabled by gpu module.
>
> Theoretically, 1 millisecond is a critical value for 480MHz
> output clock stable time, so we try to change the delay time
> to 1.2 millisecond to avoid this issue.
>
> And the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct
> clk_ops callback") used prepare callbacks instead of enable
> callbacks to support gate a clk if the operation may sleep. So
> we can switch from delay to sleep functions.
>
> Signed-off-by: William Wu <wulf@rock-chips.com>
> ---
> Changes in v3:
> - fix kbuild test error: too few arguments to function 'usleep_range'
>
> Changes in v2:
> - use usleep_range() function instead of mdelay()
>
> drivers/phy/phy-rockchip-inno-usb2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
> index 365e077..0e52b25 100644
> --- a/drivers/phy/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/phy-rockchip-inno-usb2.c
> @@ -166,7 +166,7 @@ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
> return ret;
>
> /* waitting for the clk become stable */
> - mdelay(1);
> + usleep_range(1200, 1300);
Sight nit that you could also fix the spelling from "waitting" to "waiting".
...but that's pre-existing, so:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply
* Re: Tracing sched_switch events for client application when process is switched back in
From: Milian Wolff @ 2016-11-14 18:17 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo; +Cc: linux-perf-users
In-Reply-To: <20161114153611.GA26543@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 3357 bytes --]
On Monday, November 14, 2016 12:36:11 PM CET Arnaldo Carvalho de Melo wrote:
> Em Mon, Nov 14, 2016 at 03:10:26PM +0100, Milian Wolff escreveu:
> > On Monday, October 10, 2016 9:36:55 PM CET Arnaldo Carvalho de Melo wrote:
> > > Em Thu, Oct 06, 2016 at 06:38:28PM +0200, Milian Wolff escreveu:
> > > > only find 7, whereas tracing sched_switch finds all 100 that actually
> > > > take
> > > > place?
> >
> > Hey there,
> >
> > long delay but I looked at this again today.
> >
> > > This is looking only for the sched switches for the monitored workload,
> > > which in this case is 'sleep 1', this wasn't a system wide session.
> > >
> > > add -a and you'll get those other switches, if I got what you described.
> >
> > I've used the sources of the simple C application I showed in the first
> > email of this thread (still quoted above). Then I try:
> >
> > perf record --switch-events -a ./a.out
> >
> > And indeed, I get all switch events. But I now also profile all
> > applications on the machine, which is not what I want. I want to combine
> > the following
>
> So you remove that '-a' from that command line and gets just the context
> switches for that ./a.out app, no?
>
> Lets see:
<snip>
> 5 out, 5 in, in a lightly loaded machine, plenty of CPUs, looks about right,
> no?
Hm this is odd. Before writing the last mail, and the one from one month ago,
I tried this and it did not work. But now it does seem to work as intended,
even with my simple application code...
perf record --switch-events ./a.out
perf script --show-switch-events | grep -c SWITCH
200
So this clearly works as intended - sorry for the noise.
> But...
>
> > features:
> >
> > - sample CPU events for a given application with backtraces
> >
> > perf record --call-graph dwarf ./foo
> >
> > - record switch-out events with backtraces (`-e
> > sched:sched_switch/fp=dwarf/`) - somehow record the switch-in events,
> > which are associated with a different process and thus currently
> > discarded
>
> You want the backtraces with that, and since this is a meta-event... Humm,
> for the switch in would the above be sufficient? What value would be in
> knowing the backtrace in that case?
Knowing the backtrace would ensure I get the real location that triggered a
switch, i.e. often times that comes from a syscall like futex or the like. Or
would I always get a CPU event (e.g. cycles) with a backtrace before the
switch happens, pointing to the same location?
> So something like would do? Try not looking at the "PERF_RECORD_SWITCH OUT"
> lines, they are generated by the kernel _after_ the corresponding
> sched:sched_switch is registered:
>
> [root@jouet ~]# perf record --call-graph=dwarf --switch-events -e
<snip>
Yes, that seems to work just fine:
perf record -e cycles -e sched:sched_switch \
--call-graph dwarf --switch-events \
./a.out
That gives me all information. With some post-processing one could then turn
this into a really useful profiling tool, as one will only need a single perf
record step to allow both, on-CPU as well as off-CPU profiling for application
developers.
Many thanks for the help, Arnaldo, and sorry again for the confusion on my
side.
Cheers
--
Milian Wolff | milian.wolff@kdab.com | Software Engineer
KDAB (Deutschland) GmbH&Co KG, a KDAB Group company
Tel: +49-30-521325470
KDAB - The Qt Experts
[-- Attachment #2: smime.p7s --]
[-- Type: application/pkcs7-signature, Size: 5903 bytes --]
^ permalink raw reply
* Re: [PATCHSET] Add support for simplified async direct-io
From: Jens Axboe @ 2016-11-14 18:17 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: axboe, linux-block
In-Reply-To: <20161114181119.GA9396@infradead.org>
On 11/14/2016 11:11 AM, Christoph Hellwig wrote:
> On Mon, Nov 14, 2016 at 11:08:46AM -0700, Jens Axboe wrote:
>> It'd be cleaner to loop one level out, and avoid all that 'dio' stuff
>> instead. And then still retain the separate parts of the sync and async.
>> There's nothing to share there imho, and it just makes the code harder
>> to read.
>
> How do you avoid it for the async case? We can only call ki_complete
> once all bios have finished, which means we need a tracking structure
> for it. For the synchronous case we could in theory wait for the
> previous bio before sending the next, but there are plenty of RAID
> arrays that would prefer > 1MB I/O. And we can pretty much reuse the
> async case for this anyway.
Just make the limit reasonable - with a order 1 alloc, we have 256
pages, or 1MB of IO. Loop around that. We could play tricks with bio
reuse and using the ref count for knowing when it'd be done.
--
Jens Axboe
^ permalink raw reply
* Re: [RFC][PATCH 2/7] kref: Add kref_read()
From: Christoph Hellwig @ 2016-11-14 18:16 UTC (permalink / raw)
To: Peter Zijlstra
Cc: gregkh, keescook, will.deacon, elena.reshetova, arnd, tglx, mingo,
hpa, dave, linux-kernel
In-Reply-To: <20161114174446.486581399@infradead.org>
On Mon, Nov 14, 2016 at 06:39:48PM +0100, Peter Zijlstra wrote:
> Since we need to change the implementation, stop exposing internals.
>
> Provide kref_read() to read the current reference count; typically
> used for debug messages.
Can we just provide a printk specifier for a kref value instead as
that is the only valid use case for reading the value?
^ permalink raw reply
* [PATCH v2 0/4] Support PowerISA v3.0 PMU Raw event format
From: Madhavan Srinivasan @ 2016-11-14 18:17 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, Madhavan Srinivasan
Patchset to factor out the PowerISA v2.07 PMU raw event
format encoding and add support to the PowerISA v3.0 PMU
raw event format encoding.
Changelog v1:
1) Initialized "mmcra" variable to avoid compile time errors
2) Made changes to commit message
Madhavan Srinivasan (4):
powerpc/perf: factor out the event format field
powerpc/perf: update attribute_group data structure
powerpc/perf: PowerISA v3.0 raw event format encoding
powerpc/perf: macros for PowerISA v3.0 format encoding
arch/powerpc/perf/isa207-common.c | 124 +++++++++++++++++++++++++++++++++++---
arch/powerpc/perf/isa207-common.h | 27 ++++++++-
arch/powerpc/perf/power8-pmu.c | 39 ++----------
arch/powerpc/perf/power9-pmu.c | 112 +++++++++++++++++++++++++++++++++-
4 files changed, 256 insertions(+), 46 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v2 1/4] powerpc/perf: factor out the event format field
From: Madhavan Srinivasan @ 2016-11-14 18:17 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, Madhavan Srinivasan
In-Reply-To: <1479147435-18665-1-git-send-email-maddy@linux.vnet.ibm.com>
Factor out the format field structure for PowerISA v2.07.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
---
arch/powerpc/perf/isa207-common.c | 34 ++++++++++++++++++++++++++++++++++
arch/powerpc/perf/power8-pmu.c | 39 ++++-----------------------------------
arch/powerpc/perf/power9-pmu.c | 39 ++++-----------------------------------
3 files changed, 42 insertions(+), 70 deletions(-)
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 6143c99f3ec5..2a2040ea5f99 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -12,6 +12,40 @@
*/
#include "isa207-common.h"
+PMU_FORMAT_ATTR(event, "config:0-49");
+PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
+PMU_FORMAT_ATTR(mark, "config:8");
+PMU_FORMAT_ATTR(combine, "config:11");
+PMU_FORMAT_ATTR(unit, "config:12-15");
+PMU_FORMAT_ATTR(pmc, "config:16-19");
+PMU_FORMAT_ATTR(cache_sel, "config:20-23");
+PMU_FORMAT_ATTR(sample_mode, "config:24-28");
+PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
+PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
+PMU_FORMAT_ATTR(thresh_start, "config:36-39");
+PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
+
+struct attribute *isa207_pmu_format_attr[] = {
+ &format_attr_event.attr,
+ &format_attr_pmcxsel.attr,
+ &format_attr_mark.attr,
+ &format_attr_combine.attr,
+ &format_attr_unit.attr,
+ &format_attr_pmc.attr,
+ &format_attr_cache_sel.attr,
+ &format_attr_sample_mode.attr,
+ &format_attr_thresh_sel.attr,
+ &format_attr_thresh_stop.attr,
+ &format_attr_thresh_start.attr,
+ &format_attr_thresh_cmp.attr,
+ NULL,
+};
+
+struct attribute_group isa207_pmu_format_group = {
+ .name = "format",
+ .attrs = isa207_pmu_format_attr,
+};
+
static inline bool event_is_fab_match(u64 event)
{
/* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index ab830d106ec5..d07186382f3a 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -30,6 +30,9 @@ enum {
#define POWER8_MMCRA_IFM2 0x0000000080000000UL
#define POWER8_MMCRA_IFM3 0x00000000C0000000UL
+/* PowerISA v2.07 format attribute structure*/
+extern struct attribute_group isa207_pmu_format_group;
+
/* Table of alternatives, sorted by column 0 */
static const unsigned int event_alternatives[][MAX_ALT] = {
{ PM_MRK_ST_CMPL, PM_MRK_ST_CMPL_ALT },
@@ -175,42 +178,8 @@ static struct attribute_group power8_pmu_events_group = {
.attrs = power8_events_attr,
};
-PMU_FORMAT_ATTR(event, "config:0-49");
-PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
-PMU_FORMAT_ATTR(mark, "config:8");
-PMU_FORMAT_ATTR(combine, "config:11");
-PMU_FORMAT_ATTR(unit, "config:12-15");
-PMU_FORMAT_ATTR(pmc, "config:16-19");
-PMU_FORMAT_ATTR(cache_sel, "config:20-23");
-PMU_FORMAT_ATTR(sample_mode, "config:24-28");
-PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
-PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
-PMU_FORMAT_ATTR(thresh_start, "config:36-39");
-PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
-
-static struct attribute *power8_pmu_format_attr[] = {
- &format_attr_event.attr,
- &format_attr_pmcxsel.attr,
- &format_attr_mark.attr,
- &format_attr_combine.attr,
- &format_attr_unit.attr,
- &format_attr_pmc.attr,
- &format_attr_cache_sel.attr,
- &format_attr_sample_mode.attr,
- &format_attr_thresh_sel.attr,
- &format_attr_thresh_stop.attr,
- &format_attr_thresh_start.attr,
- &format_attr_thresh_cmp.attr,
- NULL,
-};
-
-static struct attribute_group power8_pmu_format_group = {
- .name = "format",
- .attrs = power8_pmu_format_attr,
-};
-
static const struct attribute_group *power8_pmu_attr_groups[] = {
- &power8_pmu_format_group,
+ &isa207_pmu_format_group,
&power8_pmu_events_group,
NULL,
};
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index 8e9a81967ff8..443511b18bc5 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -31,6 +31,9 @@ enum {
#define POWER9_MMCRA_IFM2 0x0000000080000000UL
#define POWER9_MMCRA_IFM3 0x00000000C0000000UL
+/* PowerISA v2.07 format attribute structure*/
+extern struct attribute_group isa207_pmu_format_group;
+
GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC);
GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
@@ -90,42 +93,8 @@ static struct attribute_group power9_pmu_events_group = {
.attrs = power9_events_attr,
};
-PMU_FORMAT_ATTR(event, "config:0-49");
-PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
-PMU_FORMAT_ATTR(mark, "config:8");
-PMU_FORMAT_ATTR(combine, "config:11");
-PMU_FORMAT_ATTR(unit, "config:12-15");
-PMU_FORMAT_ATTR(pmc, "config:16-19");
-PMU_FORMAT_ATTR(cache_sel, "config:20-23");
-PMU_FORMAT_ATTR(sample_mode, "config:24-28");
-PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
-PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
-PMU_FORMAT_ATTR(thresh_start, "config:36-39");
-PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
-
-static struct attribute *power9_pmu_format_attr[] = {
- &format_attr_event.attr,
- &format_attr_pmcxsel.attr,
- &format_attr_mark.attr,
- &format_attr_combine.attr,
- &format_attr_unit.attr,
- &format_attr_pmc.attr,
- &format_attr_cache_sel.attr,
- &format_attr_sample_mode.attr,
- &format_attr_thresh_sel.attr,
- &format_attr_thresh_stop.attr,
- &format_attr_thresh_start.attr,
- &format_attr_thresh_cmp.attr,
- NULL,
-};
-
-static struct attribute_group power9_pmu_format_group = {
- .name = "format",
- .attrs = power9_pmu_format_attr,
-};
-
static const struct attribute_group *power9_pmu_attr_groups[] = {
- &power9_pmu_format_group,
+ &isa207_pmu_format_group,
&power9_pmu_events_group,
NULL,
};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 3/4] powerpc/perf: PowerISA v3.0 raw event format encoding
From: Madhavan Srinivasan @ 2016-11-14 18:17 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, Madhavan Srinivasan
In-Reply-To: <1479147435-18665-1-git-send-email-maddy@linux.vnet.ibm.com>
Patch to update the PowerISA v3.0 raw event encoding format
information and add support for the same in Power9-pmu.c.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
---
arch/powerpc/perf/power9-pmu.c | 134 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index d1782fd644e9..928d0e739ed4 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -16,6 +16,78 @@
#include "isa207-common.h"
/*
+ * Raw event encoding for PowerISA v3.0:
+ *
+ * 60 56 52 48 44 40 36 32
+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
+ * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
+ * | | | | |
+ * | | *- IFM (Linux) | thresh start/stop OR FAB match -*
+ * | *- BHRB (Linux) *sm
+ * *- EBB (Linux)
+ *
+ * 28 24 20 16 12 8 4 0
+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
+ * [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ]
+ * | | | | |
+ * | | | | *- mark
+ * | | *- L1/L2/L3 cache_sel |
+ * | | |
+ * | *- sampling mode for marked events *- combine
+ * |
+ * *- thresh_sel
+ *
+ * Below uses IBM bit numbering.
+ *
+ * MMCR1[x:y] = unit (PMCxUNIT)
+ * MMCR1[24] = pmc1combine[0]
+ * MMCR1[25] = pmc1combine[1]
+ * MMCR1[26] = pmc2combine[0]
+ * MMCR1[27] = pmc2combine[1]
+ * MMCR1[28] = pmc3combine[0]
+ * MMCR1[29] = pmc3combine[1]
+ * MMCR1[30] = pmc4combine[0]
+ * MMCR1[31] = pmc4combine[1]
+ *
+ * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
+ * # PM_MRK_FAB_RSP_MATCH
+ * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
+ * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
+ * # PM_MRK_FAB_RSP_MATCH_CYC
+ * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
+ * else
+ * MMCRA[48:55] = thresh_ctl (THRESH START/END)
+ *
+ * if thresh_sel:
+ * MMCRA[45:47] = thresh_sel
+ *
+ * if thresh_cmp:
+ * MMCRA[9:11] = thresh_cmp[0:2]
+ * MMCRA[12:18] = thresh_cmp[3:9]
+ *
+ * if unit == 6 or unit == 7
+ * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
+ * else if unit == 8 or unit == 9:
+ * if cache_sel[0] == 0: # L3 bank
+ * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
+ * else if cache_sel[0] == 1:
+ * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1)
+ * else if cache_sel[1]: # L1 event
+ * MMCR1[16] = cache_sel[2]
+ * MMCR1[17] = cache_sel[3]
+ *
+ * if mark:
+ * MMCRA[63] = 1 (SAMPLE_ENABLE)
+ * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
+ * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
+ *
+ * if EBB and BHRB:
+ * MMCRA[32:33] = IFM
+ *
+ * MMCRA[SDAR_MODE] = sm
+ */
+
+/*
* Some power9 event codes.
*/
#define EVENT(_name, _code) _name = _code,
@@ -99,6 +171,48 @@ static const struct attribute_group *power9_isa207_pmu_attr_groups[] = {
NULL,
};
+PMU_FORMAT_ATTR(event, "config:0-51");
+PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
+PMU_FORMAT_ATTR(mark, "config:8");
+PMU_FORMAT_ATTR(combine, "config:10-11");
+PMU_FORMAT_ATTR(unit, "config:12-15");
+PMU_FORMAT_ATTR(pmc, "config:16-19");
+PMU_FORMAT_ATTR(cache_sel, "config:20-23");
+PMU_FORMAT_ATTR(sample_mode, "config:24-28");
+PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
+PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
+PMU_FORMAT_ATTR(thresh_start, "config:36-39");
+PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
+PMU_FORMAT_ATTR(sdar_mode, "config:50-51");
+
+static struct attribute *power9_pmu_format_attr[] = {
+ &format_attr_event.attr,
+ &format_attr_pmcxsel.attr,
+ &format_attr_mark.attr,
+ &format_attr_combine.attr,
+ &format_attr_unit.attr,
+ &format_attr_pmc.attr,
+ &format_attr_cache_sel.attr,
+ &format_attr_sample_mode.attr,
+ &format_attr_thresh_sel.attr,
+ &format_attr_thresh_stop.attr,
+ &format_attr_thresh_start.attr,
+ &format_attr_thresh_cmp.attr,
+ &format_attr_sdar_mode.attr,
+ NULL,
+};
+
+static struct attribute_group power9_pmu_format_group = {
+ .name = "format",
+ .attrs = power9_pmu_format_attr,
+};
+
+static const struct attribute_group *power9_pmu_attr_groups[] = {
+ &power9_pmu_format_group,
+ &power9_pmu_events_group,
+ NULL,
+};
+
static int power9_generic_events[] = {
[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
@@ -278,6 +392,24 @@ static struct power_pmu power9_isa207_pmu = {
.bhrb_nr = 32,
};
+static struct power_pmu power9_pmu = {
+ .name = "POWER9",
+ .n_counter = MAX_PMU_COUNTERS,
+ .add_fields = ISA207_ADD_FIELDS,
+ .test_adder = ISA207_TEST_ADDER,
+ .compute_mmcr = isa207_compute_mmcr,
+ .config_bhrb = power9_config_bhrb,
+ .bhrb_filter_map = power9_bhrb_filter_map,
+ .get_constraint = isa207_get_constraint,
+ .disable_pmc = isa207_disable_pmc,
+ .flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
+ .n_generic = ARRAY_SIZE(power9_generic_events),
+ .generic_events = power9_generic_events,
+ .cache_events = &power9_cache_events,
+ .attr_groups = power9_pmu_attr_groups,
+ .bhrb_nr = 32,
+};
+
static int __init init_power9_pmu(void)
{
int rc;
@@ -289,6 +421,8 @@ static int __init init_power9_pmu(void)
if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
rc = register_power_pmu(&power9_isa207_pmu);
+ } else {
+ rc = register_power_pmu(&power9_pmu);
}
if (rc)
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/4] powerpc/perf: update attribute_group data structure
From: Madhavan Srinivasan @ 2016-11-14 18:17 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, Madhavan Srinivasan
In-Reply-To: <1479147435-18665-1-git-send-email-maddy@linux.vnet.ibm.com>
Rename the power_pmu and attribute_group variables that
support PowerISA v2.07. Add a cpu feature flag check to pick
the PowerISA v2.07 format structures to support.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
---
arch/powerpc/perf/power9-pmu.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index 443511b18bc5..d1782fd644e9 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -93,7 +93,7 @@ static struct attribute_group power9_pmu_events_group = {
.attrs = power9_events_attr,
};
-static const struct attribute_group *power9_pmu_attr_groups[] = {
+static const struct attribute_group *power9_isa207_pmu_attr_groups[] = {
&isa207_pmu_format_group,
&power9_pmu_events_group,
NULL,
@@ -260,7 +260,7 @@ static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
#undef C
-static struct power_pmu power9_pmu = {
+static struct power_pmu power9_isa207_pmu = {
.name = "POWER9",
.n_counter = MAX_PMU_COUNTERS,
.add_fields = ISA207_ADD_FIELDS,
@@ -274,7 +274,7 @@ static struct power_pmu power9_pmu = {
.n_generic = ARRAY_SIZE(power9_generic_events),
.generic_events = power9_generic_events,
.cache_events = &power9_cache_events,
- .attr_groups = power9_pmu_attr_groups,
+ .attr_groups = power9_isa207_pmu_attr_groups,
.bhrb_nr = 32,
};
@@ -287,7 +287,10 @@ static int __init init_power9_pmu(void)
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
return -ENODEV;
- rc = register_power_pmu(&power9_pmu);
+ if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
+ rc = register_power_pmu(&power9_isa207_pmu);
+ }
+
if (rc)
return rc;
--
2.7.4
^ permalink raw reply related
* [PATCH v2 4/4] powerpc/perf: macros for PowerISA v3.0 format encoding
From: Madhavan Srinivasan @ 2016-11-14 18:17 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, Madhavan Srinivasan
In-Reply-To: <1479147435-18665-1-git-send-email-maddy@linux.vnet.ibm.com>
Patch to add macros and contants to support the PowerISA v3.0 raw
event encoding format. Couple of functions added since some of the
bits fields like PMCxCOMB and THRESH_CMP has different width and location
within MMCR* in PowerISA v3.0.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
---
arch/powerpc/perf/isa207-common.c | 90 ++++++++++++++++++++++++++++++++++++---
arch/powerpc/perf/isa207-common.h | 27 +++++++++++-
2 files changed, 109 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 2a2040ea5f99..e747bbf06661 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -55,6 +55,81 @@ static inline bool event_is_fab_match(u64 event)
return (event == 0x30056 || event == 0x4f052);
}
+static bool is_event_valid(u64 event)
+{
+ if (cpu_has_feature(CPU_FTR_ARCH_300) &&
+ (cpu_has_feature(CPU_FTR_POWER9_DD1)) &&
+ (event & ~EVENT_VALID_MASK))
+ return false;
+ else if (cpu_has_feature(CPU_FTR_ARCH_300) &&
+ (event & ~ISA300_EVENT_VALID_MASK))
+ return false;
+ else if (event & ~EVENT_VALID_MASK)
+ return false;
+
+ return true;
+}
+
+static u64 mmcra_sdar_mode(u64 event)
+{
+ u64 sm;
+
+ if (cpu_has_feature(CPU_FTR_ARCH_300) &&
+ (cpu_has_feature(CPU_FTR_POWER9_DD1))) {
+ goto sm_tlb;
+ } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
+ sm = (event >> ISA300_SDAR_MODE_SHIFT) & ISA300_SDAR_MODE_MASK;
+ if (sm)
+ return sm<<MMCRA_SDAR_MODE_SHIFT;
+ } else
+ goto sm_tlb;
+
+sm_tlb:
+ return MMCRA_SDAR_MODE_TLB;
+}
+
+static u64 thresh_cmp_val(u64 value)
+{
+ if (cpu_has_feature(CPU_FTR_ARCH_300) &&
+ (cpu_has_feature(CPU_FTR_POWER9_DD1)))
+ goto thr_cmp;
+ else if (cpu_has_feature(CPU_FTR_ARCH_300))
+ return value<<ISA300_MMCRA_THR_CMP_SHIFT;
+ else
+ goto thr_cmp;
+thr_cmp:
+ return value<<MMCRA_THR_CMP_SHIFT;
+}
+
+static unsigned long combine_from_event(u64 event)
+{
+ unsigned long combine;
+
+ if (cpu_has_feature(CPU_FTR_ARCH_300) &&
+ (cpu_has_feature(CPU_FTR_POWER9_DD1)))
+ combine = (event >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
+ else if (cpu_has_feature(CPU_FTR_ARCH_300))
+ combine = (event >> ISA300_EVENT_COMBINE_SHIFT) & ISA300_EVENT_COMBINE_MASK;
+ else
+ combine = (event >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
+
+ return combine;
+}
+
+static unsigned long combine_shift(unsigned long pmc)
+{
+ if (cpu_has_feature(CPU_FTR_ARCH_300) &&
+ (cpu_has_feature(CPU_FTR_POWER9_DD1)))
+ goto comb_shift;
+ else if (cpu_has_feature(CPU_FTR_ARCH_300))
+ return ISA300_MMCR1_COMBINE_SHIFT(pmc);
+ else
+ goto comb_shift;
+
+comb_shift:
+ return MMCR1_COMBINE_SHIFT(pmc);
+}
+
int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
{
unsigned int unit, pmc, cache, ebb;
@@ -62,7 +137,7 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
mask = value = 0;
- if (event & ~EVENT_VALID_MASK)
+ if (!is_event_valid(event))
return -1;
pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
@@ -189,15 +264,13 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
pmc_inuse |= 1 << pmc;
}
- /* In continuous sampling mode, update SDAR on TLB miss */
- mmcra = MMCRA_SDAR_MODE_TLB;
- mmcr1 = mmcr2 = 0;
+ mmcra = mmcr1 = mmcr2 = 0;
/* Second pass: assign PMCs, set all MMCR1 fields */
for (i = 0; i < n_ev; ++i) {
pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
- combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
+ combine = combine_from_event(event[i]);
psel = event[i] & EVENT_PSEL_MASK;
if (!pmc) {
@@ -211,10 +284,13 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
if (pmc <= 4) {
mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
- mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc);
+ mmcr1 |= combine << combine_shift(pmc);
mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
}
+ /* In continuous sampling mode, update SDAR on TLB miss */
+ mmcra |= mmcra_sdar_mode(event[i]);
+
if (event[i] & EVENT_IS_L1) {
cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
@@ -245,7 +321,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
mmcra |= val << MMCRA_THR_SEL_SHIFT;
val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
- mmcra |= val << MMCRA_THR_CMP_SHIFT;
+ mmcra |= thresh_cmp_val(val);
}
if (event[i] & EVENT_WANTS_BHRB) {
diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
index 4d0a4e5017c2..0a240635cf48 100644
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -134,6 +134,24 @@
PERF_SAMPLE_BRANCH_KERNEL |\
PERF_SAMPLE_BRANCH_HV)
+/* Contants to support PowerISA v3.0 encoding format */
+#define ISA300_EVENT_COMBINE_SHIFT 10 /* Combine bit */
+#define ISA300_EVENT_COMBINE_MASK 0x3ull
+#define ISA300_SDAR_MODE_SHIFT 50
+#define ISA300_SDAR_MODE_MASK 0x3ull
+
+#define ISA300_EVENT_VALID_MASK \
+ ((ISA300_SDAR_MODE_MASK<< ISA300_SDAR_MODE_SHIFT | \
+ (EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
+ (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
+ (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
+ (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
+ (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
+ (ISA300_EVENT_COMBINE_MASK << ISA300_EVENT_COMBINE_SHIFT) | \
+ (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
+ EVENT_LINUX_MASK | \
+ EVENT_PSEL_MASK))
+
/*
* Layout of constraint bits:
*
@@ -210,15 +228,22 @@
#define MMCR1_DC_QUAL_SHIFT 47
#define MMCR1_IC_QUAL_SHIFT 46
+/* MMCR1 Combine bits macro for PowerISA v3.0 */
+#define ISA300_MMCR1_COMBINE_SHIFT(pmc) (38 - ((pmc - 1) * 2))
+
/* Bits in MMCRA for PowerISA v2.07 */
#define MMCRA_SAMP_MODE_SHIFT 1
#define MMCRA_SAMP_ELIG_SHIFT 4
#define MMCRA_THR_CTL_SHIFT 8
#define MMCRA_THR_SEL_SHIFT 16
#define MMCRA_THR_CMP_SHIFT 32
-#define MMCRA_SDAR_MODE_TLB (1ull << 42)
+#define MMCRA_SDAR_MODE_SHIFT 42
+#define MMCRA_SDAR_MODE_TLB (1ull << MMCRA_SDAR_MODE_SHIFT)
#define MMCRA_IFM_SHIFT 30
+/* MMCR1 Threshold Compare bit constant for PowerISA v3.0 */
+#define ISA300_MMCRA_THR_CMP_SHIFT 45
+
/* Bits in MMCR2 for PowerISA v2.07 */
#define MMCR2_FCS(pmc) (1ull << (63 - (((pmc) - 1) * 9)))
#define MMCR2_FCP(pmc) (1ull << (62 - (((pmc) - 1) * 9)))
--
2.7.4
^ permalink raw reply related
* Re: linux-next: Tree for Nov 14 (drivers/cpufreq/intel_pstate.c)
From: Srinivas Pandruvada @ 2016-11-14 18:17 UTC (permalink / raw)
To: Randy Dunlap, Stephen Rothwell, linux-next
Cc: linux-kernel, Len Brown, Linux PM list, Viresh Kumar,
Rafael J. Wysocki, Arnd Bergmann
In-Reply-To: <e7f4138c-709a-b60f-e6b8-9ef4dc418d7f@infradead.org>
On Mon, 2016-11-14 at 09:48 -0800, Randy Dunlap wrote:
> On 11/13/16 23:23, Stephen Rothwell wrote:
> >
> > Hi all,
> >
> > Changes since 20161111:
> >
>
> on i386, when CONFIG_ACPI is not enabled:
>
> ../drivers/cpufreq/intel_pstate.c: In function 'copy_cpu_funcs':
> ../drivers/cpufreq/intel_pstate.c:1798:2: error: too few arguments to
> function 'intel_pstate_use_acpi_profile'
> intel_pstate_use_acpi_profile();
> ^
> ../drivers/cpufreq/intel_pstate.c:1782:20: note: declared here
> static inline void intel_pstate_use_acpi_profile(struct pstate_funcs
> *funcs)
>
^
[PATCH] cpufreq: intel_pstate: fix intel_pstate_use_acpi_profile helper
from Arnd Bergmann <arnd@arndb.de>
fixes this.
But I am resubmitting the original patch as this is a compile issue.
Thanks,
Srinivas
^ permalink raw reply
* Re: [Patch net-next] net: fix sleeping for sk_wait_event()
From: David Miller @ 2016-11-14 18:17 UTC (permalink / raw)
To: xiyou.wangcong; +Cc: netdev, eric.dumazet, peterz
In-Reply-To: <1478888450-16985-1-git-send-email-xiyou.wangcong@gmail.com>
From: Cong Wang <xiyou.wangcong@gmail.com>
Date: Fri, 11 Nov 2016 10:20:50 -0800
> Similar to commit 14135f30e33c ("inet: fix sleeping inside inet_wait_for_connect()"),
> sk_wait_event() needs to fix too, because release_sock() is blocking,
> it changes the process state back to running after sleep, which breaks
> the previous prepare_to_wait().
>
> Switch to the new wait API.
>
> Cc: Eric Dumazet <eric.dumazet@gmail.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com>
Applied, thanks.
^ permalink raw reply
* [U-Boot] [PATCH] drivers: SPI: sunxi SPL: fix warning
From: Siarhei Siamashka @ 2016-11-14 18:18 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161114165650.GJ27304@bill-the-cat>
On Mon, 14 Nov 2016 11:56:50 -0500
Tom Rini <trini@konsulko.com> wrote:
> On Mon, Nov 14, 2016 at 04:47:26PM +0000, Andre Przywara wrote:
> > Hi,
> >
> > On 14/11/16 16:30, Jagan Teki wrote:
> > > On Thu, Nov 3, 2016 at 6:28 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> > >> Somehow an int returning function without a return statement sneaked
> > >> in. Fix it.
> > >>
> > >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > >> ---
> > >> drivers/mtd/spi/sunxi_spi_spl.c | 3 ++-
> > >> 1 file changed, 2 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c
> > >> index 67c7edd..7502314 100644
> > >> --- a/drivers/mtd/spi/sunxi_spi_spl.c
> > >> +++ b/drivers/mtd/spi/sunxi_spi_spl.c
> > >> @@ -158,9 +158,10 @@ static void spi0_disable_clock(void)
> > >> (1 << AHB_RESET_SPI0_SHIFT));
> > >> }
> > >>
> > >> -static int spi0_init(void)
> > >> +static void spi0_init(void)
> > >> {
> > >> unsigned int pin_function = SUNXI_GPC_SPI0;
> > >> +
> > >
> > > Space not needed or unrelated, please remove this.
> >
> > This is Linux coding style, which U-Boot adheres to.
> > "WARNING: Missing a blank line after declarations"
> >
> > I thought I should fix this since this is was in the context of this
> > very simple patch and it improves readability.
> > If this is too much, then please remove the line before committing.
>
> Making things checkpatch clean is good, in the future please also
> mention that in commit messages. Thanks!
How can I get this checkpatch warning?
$ scripts/checkpatch.pl 0001-sunxi-Support-booting-from-SPI-flash.patch
total: 0 errors, 0 warnings, 0 checks, 361 lines checked
NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX MULTISTATEMENT_MACRO_USE_DO_WHILE NETWORKING_BLOCK_COMMENT_STYLE PREFER_ETHER_ADDR_COPY USLEEP_RANGE
0001-sunxi-Support-booting-from-SPI-flash.patch has no obvious style problems and is ready for submission.
--
Best regards,
Siarhei Siamashka
^ permalink raw reply
* Re: [PATCH v3 3/3] mwifiex: Enable WoWLAN for both sdio and pcie
From: Brian Norris @ 2016-11-14 18:18 UTC (permalink / raw)
To: Amitkumar Karwar
Cc: linux-wireless, Cathy Luo, Nishant Sarmukadam, rajatja,
dmitry.torokhov
In-Reply-To: <1479127752-23745-3-git-send-email-akarwar@marvell.com>
On Mon, Nov 14, 2016 at 06:19:12PM +0530, Amitkumar Karwar wrote:
> From: Rajat Jain <rajatja@google.com>
>
> Commit ce4f6f0c353b ("mwifiex: add platform specific wakeup interrupt
> support") added WoWLAN feature only for sdio. This patch moves that
> code to the common module so that all the interface drivers can use
> it for free. It enables pcie and sdio for its use currently.
>
> Signed-off-by: Rajat Jain <rajatja@google.com>
> ---
> v2: v1 doesn't apply smoothly on latest code due to recently merged
> patch "mwifiex: report error to PCIe for suspend failure". Minor
> conflict is resolved in v2
> v3: Same as v2
For the whole series:
Reviewed-by: Brian Norris <briannorris@chromium.org>
I think there are some trivial conflicts with one of your/our other
series, but that can be worked out once one of them is accepted. I also
expect you'll send patches to fix the existing bugs I noted already.
Also, this implicitly extends device tree support to PCIe devices. While
that's probably OK, it would be good to promptly update a patch like
this:
[PATCH v6] mwifiex: parse device tree node for PCIe
https://patchwork.kernel.org/patch/9390225/
to check for the appropriate compatible properties before accepting the
device and registering the card. That patch should be just a little bit
simpler on top of this patch set.
Brian
> ---
> drivers/net/wireless/marvell/mwifiex/main.c | 41 ++++++++++++++++
> drivers/net/wireless/marvell/mwifiex/main.h | 25 ++++++++++
> drivers/net/wireless/marvell/mwifiex/pcie.c | 2 +
> drivers/net/wireless/marvell/mwifiex/sdio.c | 72 ++---------------------------
> drivers/net/wireless/marvell/mwifiex/sdio.h | 8 ----
> 5 files changed, 73 insertions(+), 75 deletions(-)
>
> diff --git a/drivers/net/wireless/marvell/mwifiex/main.c b/drivers/net/wireless/marvell/mwifiex/main.c
> index 835d330..948f5c2 100644
> --- a/drivers/net/wireless/marvell/mwifiex/main.c
> +++ b/drivers/net/wireless/marvell/mwifiex/main.c
> @@ -1552,14 +1552,55 @@ void mwifiex_do_flr(struct mwifiex_adapter *adapter, bool prepare)
> }
> EXPORT_SYMBOL_GPL(mwifiex_do_flr);
>
> +static irqreturn_t mwifiex_irq_wakeup_handler(int irq, void *priv)
> +{
> + struct mwifiex_adapter *adapter = priv;
> +
> + if (adapter->irq_wakeup >= 0) {
> + dev_dbg(adapter->dev, "%s: wake by wifi", __func__);
> + adapter->wake_by_wifi = true;
> + disable_irq_nosync(irq);
> + }
> +
> + /* Notify PM core we are wakeup source */
> + pm_wakeup_event(adapter->dev, 0);
> +
> + return IRQ_HANDLED;
> +}
> +
> static void mwifiex_probe_of(struct mwifiex_adapter *adapter)
> {
> + int ret;
> struct device *dev = adapter->dev;
>
> if (!dev->of_node)
> return;
>
> adapter->dt_node = dev->of_node;
> + adapter->irq_wakeup = irq_of_parse_and_map(adapter->dt_node, 0);
> + if (!adapter->irq_wakeup) {
> + dev_info(dev, "fail to parse irq_wakeup from device tree\n");
> + return;
> + }
> +
> + ret = devm_request_irq(dev, adapter->irq_wakeup,
> + mwifiex_irq_wakeup_handler, IRQF_TRIGGER_LOW,
> + "wifi_wake", adapter);
> + if (ret) {
> + dev_err(dev, "Failed to request irq_wakeup %d (%d)\n",
> + adapter->irq_wakeup, ret);
> + goto err_exit;
> + }
> +
> + disable_irq(adapter->irq_wakeup);
> + if (device_init_wakeup(dev, true)) {
> + dev_err(dev, "fail to init wakeup for mwifiex\n");
> + goto err_exit;
> + }
> + return;
> +
> +err_exit:
> + adapter->irq_wakeup = 0;
> }
>
> /*
> diff --git a/drivers/net/wireless/marvell/mwifiex/main.h b/drivers/net/wireless/marvell/mwifiex/main.h
> index 549e1ba..ae5afe5 100644
> --- a/drivers/net/wireless/marvell/mwifiex/main.h
> +++ b/drivers/net/wireless/marvell/mwifiex/main.h
> @@ -1011,6 +1011,10 @@ struct mwifiex_adapter {
> bool usb_mc_setup;
> struct cfg80211_wowlan_nd_info *nd_info;
> struct ieee80211_regdomain *regd;
> +
> + /* Wake-on-WLAN (WoWLAN) */
> + int irq_wakeup;
> + bool wake_by_wifi;
> };
>
> void mwifiex_process_tx_queue(struct mwifiex_adapter *adapter);
> @@ -1410,6 +1414,27 @@ static inline u8 mwifiex_is_tdls_link_setup(u8 status)
> return false;
> }
>
> +/* Disable platform specific wakeup interrupt */
> +static inline void mwifiex_disable_wake(struct mwifiex_adapter *adapter)
> +{
> + if (adapter->irq_wakeup >= 0) {
> + disable_irq_wake(adapter->irq_wakeup);
> + if (!adapter->wake_by_wifi)
> + disable_irq(adapter->irq_wakeup);
> + }
> +}
> +
> +/* Enable platform specific wakeup interrupt */
> +static inline void mwifiex_enable_wake(struct mwifiex_adapter *adapter)
> +{
> + /* Enable platform specific wakeup interrupt */
> + if (adapter->irq_wakeup >= 0) {
> + adapter->wake_by_wifi = false;
> + enable_irq(adapter->irq_wakeup);
> + enable_irq_wake(adapter->irq_wakeup);
> + }
> +}
> +
> int mwifiex_init_shutdown_fw(struct mwifiex_private *priv,
> u32 func_init_shutdown);
> int mwifiex_add_card(void *card, struct semaphore *sem,
> diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c
> index de6939c..7942b28 100644
> --- a/drivers/net/wireless/marvell/mwifiex/pcie.c
> +++ b/drivers/net/wireless/marvell/mwifiex/pcie.c
> @@ -131,6 +131,7 @@ static int mwifiex_pcie_suspend(struct device *dev)
> }
>
> adapter = card->adapter;
> + mwifiex_enable_wake(adapter);
>
> /* Enable the Host Sleep */
> if (!mwifiex_enable_hs(adapter)) {
> @@ -186,6 +187,7 @@ static int mwifiex_pcie_resume(struct device *dev)
>
> mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
> MWIFIEX_ASYNC_CMD);
> + mwifiex_disable_wake(adapter);
>
> return 0;
> }
> diff --git a/drivers/net/wireless/marvell/mwifiex/sdio.c b/drivers/net/wireless/marvell/mwifiex/sdio.c
> index c95f41f..7055282 100644
> --- a/drivers/net/wireless/marvell/mwifiex/sdio.c
> +++ b/drivers/net/wireless/marvell/mwifiex/sdio.c
> @@ -79,67 +79,18 @@
> { }
> };
>
> -static irqreturn_t mwifiex_wake_irq_wifi(int irq, void *priv)
> -{
> - struct mwifiex_plt_wake_cfg *cfg = priv;
> -
> - if (cfg->irq_wifi >= 0) {
> - pr_info("%s: wake by wifi", __func__);
> - cfg->wake_by_wifi = true;
> - disable_irq_nosync(irq);
> - }
> -
> - /* Notify PM core we are wakeup source */
> - pm_wakeup_event(cfg->dev, 0);
> -
> - return IRQ_HANDLED;
> -}
> -
> /* This function parse device tree node using mmc subnode devicetree API.
> * The device node is saved in card->plt_of_node.
> * if the device tree node exist and include interrupts attributes, this
> * function will also request platform specific wakeup interrupt.
> */
> -static int mwifiex_sdio_probe_of(struct device *dev, struct sdio_mmc_card *card)
> +static int mwifiex_sdio_probe_of(struct device *dev)
> {
> - struct mwifiex_plt_wake_cfg *cfg;
> - int ret;
> -
> if (!of_match_node(mwifiex_sdio_of_match_table, dev->of_node)) {
> dev_err(dev, "required compatible string missing\n");
> return -EINVAL;
> }
>
> - card->plt_of_node = dev->of_node;
> - card->plt_wake_cfg = devm_kzalloc(dev, sizeof(*card->plt_wake_cfg),
> - GFP_KERNEL);
> - cfg = card->plt_wake_cfg;
> - if (cfg && card->plt_of_node) {
> - cfg->dev = dev;
> - cfg->irq_wifi = irq_of_parse_and_map(card->plt_of_node, 0);
> - if (!cfg->irq_wifi) {
> - dev_dbg(dev,
> - "fail to parse irq_wifi from device tree\n");
> - } else {
> - ret = devm_request_irq(dev, cfg->irq_wifi,
> - mwifiex_wake_irq_wifi,
> - IRQF_TRIGGER_LOW,
> - "wifi_wake", cfg);
> - if (ret) {
> - dev_dbg(dev,
> - "Failed to request irq_wifi %d (%d)\n",
> - cfg->irq_wifi, ret);
> - card->plt_wake_cfg = NULL;
> - return 0;
> - }
> - disable_irq(cfg->irq_wifi);
> - }
> - }
> -
> - ret = device_init_wakeup(dev, true);
> - if (ret)
> - dev_err(dev, "fail to init wakeup for mwifiex");
> -
> return 0;
> }
>
> @@ -198,11 +149,9 @@ static int mwifiex_sdio_probe_of(struct device *dev, struct sdio_mmc_card *card)
>
> /* device tree node parsing and platform specific configuration*/
> if (func->dev.of_node) {
> - ret = mwifiex_sdio_probe_of(&func->dev, card);
> - if (ret) {
> - dev_err(&func->dev, "SDIO dt node parse failed\n");
> + ret = mwifiex_sdio_probe_of(&func->dev);
> + if (ret)
> goto err_disable;
> - }
> }
>
> ret = mwifiex_add_card(card, &add_remove_card_sem, &sdio_ops,
> @@ -267,12 +216,7 @@ static int mwifiex_sdio_resume(struct device *dev)
> mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
> MWIFIEX_SYNC_CMD);
>
> - /* Disable platform specific wakeup interrupt */
> - if (card->plt_wake_cfg && card->plt_wake_cfg->irq_wifi >= 0) {
> - disable_irq_wake(card->plt_wake_cfg->irq_wifi);
> - if (!card->plt_wake_cfg->wake_by_wifi)
> - disable_irq(card->plt_wake_cfg->irq_wifi);
> - }
> + mwifiex_disable_wake(adapter);
>
> return 0;
> }
> @@ -352,13 +296,7 @@ static int mwifiex_sdio_suspend(struct device *dev)
> }
>
> adapter = card->adapter;
> -
> - /* Enable platform specific wakeup interrupt */
> - if (card->plt_wake_cfg && card->plt_wake_cfg->irq_wifi >= 0) {
> - card->plt_wake_cfg->wake_by_wifi = false;
> - enable_irq(card->plt_wake_cfg->irq_wifi);
> - enable_irq_wake(card->plt_wake_cfg->irq_wifi);
> - }
> + mwifiex_enable_wake(adapter);
>
> /* Enable the Host Sleep */
> if (!mwifiex_enable_hs(adapter)) {
> diff --git a/drivers/net/wireless/marvell/mwifiex/sdio.h b/drivers/net/wireless/marvell/mwifiex/sdio.h
> index 07cdd23..b9fbc5c 100644
> --- a/drivers/net/wireless/marvell/mwifiex/sdio.h
> +++ b/drivers/net/wireless/marvell/mwifiex/sdio.h
> @@ -154,12 +154,6 @@
> a->mpa_rx.start_port = 0; \
> } while (0)
>
> -struct mwifiex_plt_wake_cfg {
> - struct device *dev;
> - int irq_wifi;
> - bool wake_by_wifi;
> -};
> -
> /* data structure for SDIO MPA TX */
> struct mwifiex_sdio_mpa_tx {
> /* multiport tx aggregation buffer pointer */
> @@ -243,8 +237,6 @@ struct mwifiex_sdio_card_reg {
> struct sdio_mmc_card {
> struct sdio_func *func;
> struct mwifiex_adapter *adapter;
> - struct device_node *plt_of_node;
> - struct mwifiex_plt_wake_cfg *plt_wake_cfg;
>
> const char *firmware;
> const struct mwifiex_sdio_card_reg *reg;
> --
> 1.9.1
>
^ permalink raw reply
* Re: [RFC PATCH v3 06/20] x86: Add support to enable SME during early boot processing
From: Tom Lendacky @ 2016-11-14 18:18 UTC (permalink / raw)
To: Borislav Petkov
Cc: linux-arch, linux-efi, kvm, linux-doc, x86, linux-kernel,
kasan-dev, linux-mm, iommu, Rik van Riel,
Radim Krčmář, Arnd Bergmann, Jonathan Corbet,
Matt Fleming, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini,
Larry Woodman, Ingo Molnar, Andy Lutomirski, H. Peter Anvin,
Andrey Ryabinin
In-Reply-To: <20161114172930.27z7p2kytmhtcbsb@pd.tnic>
On 11/14/2016 11:29 AM, Borislav Petkov wrote:
> On Wed, Nov 09, 2016 at 06:35:43PM -0600, Tom Lendacky wrote:
>> This patch adds support to the early boot code to use Secure Memory
>> Encryption (SME). Support is added to update the early pagetables with
>> the memory encryption mask and to encrypt the kernel in place.
>>
>> The routines to set the encryption mask and perform the encryption are
>> stub routines for now with full function to be added in a later patch.
>>
>> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
>> ---
>> arch/x86/kernel/Makefile | 2 ++
>> arch/x86/kernel/head_64.S | 35 ++++++++++++++++++++++++++++++++++-
>> arch/x86/kernel/mem_encrypt_init.c | 29 +++++++++++++++++++++++++++++
>> 3 files changed, 65 insertions(+), 1 deletion(-)
>> create mode 100644 arch/x86/kernel/mem_encrypt_init.c
>>
>> diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
>> index 45257cf..27e22f4 100644
>> --- a/arch/x86/kernel/Makefile
>> +++ b/arch/x86/kernel/Makefile
>> @@ -141,4 +141,6 @@ ifeq ($(CONFIG_X86_64),y)
>>
>> obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o
>> obj-y += vsmp_64.o
>> +
>> + obj-y += mem_encrypt_init.o
>> endif
>> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
>> index c98a559..9a28aad 100644
>> --- a/arch/x86/kernel/head_64.S
>> +++ b/arch/x86/kernel/head_64.S
>> @@ -95,6 +95,17 @@ startup_64:
>> jnz bad_address
>>
>> /*
>> + * Enable Secure Memory Encryption (if available). Save the mask
>> + * in %r12 for later use and add the memory encryption mask to %rbp
>> + * to include it in the page table fixups.
>> + */
>> + push %rsi
>> + call sme_enable
>> + pop %rsi
>
> Why %rsi?
>
> sme_enable() is void so no args in registers and returns in %rax.
>
> /me is confused.
The %rsi register can be clobbered by the called function so I'm saving
it since it points to the real mode data. I might be able to look into
saving it earlier and restoring it before needed, but I though this
might be clearer.
>
>> + movq %rax, %r12
>> + addq %r12, %rbp
>> +
>> + /*
>> * Fixup the physical addresses in the page table
>> */
>> addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
>> @@ -117,6 +128,7 @@ startup_64:
>> shrq $PGDIR_SHIFT, %rax
>>
>> leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
>> + addq %r12, %rdx
>> movq %rdx, 0(%rbx,%rax,8)
>> movq %rdx, 8(%rbx,%rax,8)
>>
>> @@ -133,6 +145,7 @@ startup_64:
>> movq %rdi, %rax
>> shrq $PMD_SHIFT, %rdi
>> addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
>> + addq %r12, %rax
>> leaq (_end - 1)(%rip), %rcx
>> shrq $PMD_SHIFT, %rcx
>> subq %rdi, %rcx
>> @@ -163,9 +176,21 @@ startup_64:
>> cmp %r8, %rdi
>> jne 1b
>>
>> - /* Fixup phys_base */
>> + /*
>> + * Fixup phys_base, remove the memory encryption mask from %rbp
>> + * to obtain the true physical address.
>> + */
>> + subq %r12, %rbp
>> addq %rbp, phys_base(%rip)
>>
>> + /*
>> + * The page tables have been updated with the memory encryption mask,
>> + * so encrypt the kernel if memory encryption is active
>> + */
>> + push %rsi
>> + call sme_encrypt_kernel
>> + pop %rsi
>
> Ditto.
>
>> +
>> movq $(early_level4_pgt - __START_KERNEL_map), %rax
>> jmp 1f
>> ENTRY(secondary_startup_64)
>> @@ -186,9 +211,17 @@ ENTRY(secondary_startup_64)
>> /* Sanitize CPU configuration */
>> call verify_cpu
>>
>> + push %rsi
>> + call sme_get_me_mask
>> + pop %rsi
>
> Ditto.
>
>> + movq %rax, %r12
>> +
>> movq $(init_level4_pgt - __START_KERNEL_map), %rax
>> 1:
>>
>> + /* Add the memory encryption mask to RAX */
>
> I think that should say something like:
>
> /*
> * Add the memory encryption mask to init_level4_pgt's physical address
> */
>
> or so...
Yup, I'll expand on the comment for this.
>
>> + addq %r12, %rax
>> +
>> /* Enable PAE mode and PGE */
>> movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
>> movq %rcx, %cr4
>> diff --git a/arch/x86/kernel/mem_encrypt_init.c b/arch/x86/kernel/mem_encrypt_init.c
>> new file mode 100644
>> index 0000000..388d6fb
>> --- /dev/null
>> +++ b/arch/x86/kernel/mem_encrypt_init.c
>
> So nothing in the commit message explains why we need a separate
> mem_encrypt_init.c file when we already have arch/x86/mm/mem_encrypt.c
> for all memory encryption code...
I can expand on the commit message about that. I was trying to keep the
early boot-related code separate from the main code in arch/x86/mm dir.
Thanks,
Tom
>
>> @@ -0,0 +1,29 @@
>> +/*
>> + * AMD Memory Encryption Support
>> + *
>> + * Copyright (C) 2016 Advanced Micro Devices, Inc.
>> + *
>> + * Author: Tom Lendacky <thomas.lendacky@amd.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/linkage.h>
>> +#include <linux/init.h>
>> +#include <linux/mem_encrypt.h>
>> +
>> +void __init sme_encrypt_kernel(void)
>> +{
>> +}
>> +
>> +unsigned long __init sme_get_me_mask(void)
>> +{
>> + return sme_me_mask;
>> +}
>> +
>> +unsigned long __init sme_enable(void)
>> +{
>> + return sme_me_mask;
>> +}
>
^ permalink raw reply
* Re: [RFC PATCH v3 06/20] x86: Add support to enable SME during early boot processing
From: Tom Lendacky @ 2016-11-14 18:18 UTC (permalink / raw)
To: Borislav Petkov
Cc: linux-arch, linux-efi, kvm, linux-doc, x86, linux-kernel,
kasan-dev, linux-mm, iommu, Rik van Riel,
Radim Krčmář, Arnd Bergmann, Jonathan Corbet,
Matt Fleming, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini,
Larry Woodman, Ingo Molnar, Andy Lutomirski, H. Peter Anvin,
Andrey Ryabinin, Alexander Potapenko, Thomas Gleixner,
Dmitry Vyukov
In-Reply-To: <20161114172930.27z7p2kytmhtcbsb@pd.tnic>
On 11/14/2016 11:29 AM, Borislav Petkov wrote:
> On Wed, Nov 09, 2016 at 06:35:43PM -0600, Tom Lendacky wrote:
>> This patch adds support to the early boot code to use Secure Memory
>> Encryption (SME). Support is added to update the early pagetables with
>> the memory encryption mask and to encrypt the kernel in place.
>>
>> The routines to set the encryption mask and perform the encryption are
>> stub routines for now with full function to be added in a later patch.
>>
>> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
>> ---
>> arch/x86/kernel/Makefile | 2 ++
>> arch/x86/kernel/head_64.S | 35 ++++++++++++++++++++++++++++++++++-
>> arch/x86/kernel/mem_encrypt_init.c | 29 +++++++++++++++++++++++++++++
>> 3 files changed, 65 insertions(+), 1 deletion(-)
>> create mode 100644 arch/x86/kernel/mem_encrypt_init.c
>>
>> diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
>> index 45257cf..27e22f4 100644
>> --- a/arch/x86/kernel/Makefile
>> +++ b/arch/x86/kernel/Makefile
>> @@ -141,4 +141,6 @@ ifeq ($(CONFIG_X86_64),y)
>>
>> obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o
>> obj-y += vsmp_64.o
>> +
>> + obj-y += mem_encrypt_init.o
>> endif
>> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
>> index c98a559..9a28aad 100644
>> --- a/arch/x86/kernel/head_64.S
>> +++ b/arch/x86/kernel/head_64.S
>> @@ -95,6 +95,17 @@ startup_64:
>> jnz bad_address
>>
>> /*
>> + * Enable Secure Memory Encryption (if available). Save the mask
>> + * in %r12 for later use and add the memory encryption mask to %rbp
>> + * to include it in the page table fixups.
>> + */
>> + push %rsi
>> + call sme_enable
>> + pop %rsi
>
> Why %rsi?
>
> sme_enable() is void so no args in registers and returns in %rax.
>
> /me is confused.
The %rsi register can be clobbered by the called function so I'm saving
it since it points to the real mode data. I might be able to look into
saving it earlier and restoring it before needed, but I though this
might be clearer.
>
>> + movq %rax, %r12
>> + addq %r12, %rbp
>> +
>> + /*
>> * Fixup the physical addresses in the page table
>> */
>> addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
>> @@ -117,6 +128,7 @@ startup_64:
>> shrq $PGDIR_SHIFT, %rax
>>
>> leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
>> + addq %r12, %rdx
>> movq %rdx, 0(%rbx,%rax,8)
>> movq %rdx, 8(%rbx,%rax,8)
>>
>> @@ -133,6 +145,7 @@ startup_64:
>> movq %rdi, %rax
>> shrq $PMD_SHIFT, %rdi
>> addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
>> + addq %r12, %rax
>> leaq (_end - 1)(%rip), %rcx
>> shrq $PMD_SHIFT, %rcx
>> subq %rdi, %rcx
>> @@ -163,9 +176,21 @@ startup_64:
>> cmp %r8, %rdi
>> jne 1b
>>
>> - /* Fixup phys_base */
>> + /*
>> + * Fixup phys_base, remove the memory encryption mask from %rbp
>> + * to obtain the true physical address.
>> + */
>> + subq %r12, %rbp
>> addq %rbp, phys_base(%rip)
>>
>> + /*
>> + * The page tables have been updated with the memory encryption mask,
>> + * so encrypt the kernel if memory encryption is active
>> + */
>> + push %rsi
>> + call sme_encrypt_kernel
>> + pop %rsi
>
> Ditto.
>
>> +
>> movq $(early_level4_pgt - __START_KERNEL_map), %rax
>> jmp 1f
>> ENTRY(secondary_startup_64)
>> @@ -186,9 +211,17 @@ ENTRY(secondary_startup_64)
>> /* Sanitize CPU configuration */
>> call verify_cpu
>>
>> + push %rsi
>> + call sme_get_me_mask
>> + pop %rsi
>
> Ditto.
>
>> + movq %rax, %r12
>> +
>> movq $(init_level4_pgt - __START_KERNEL_map), %rax
>> 1:
>>
>> + /* Add the memory encryption mask to RAX */
>
> I think that should say something like:
>
> /*
> * Add the memory encryption mask to init_level4_pgt's physical address
> */
>
> or so...
Yup, I'll expand on the comment for this.
>
>> + addq %r12, %rax
>> +
>> /* Enable PAE mode and PGE */
>> movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
>> movq %rcx, %cr4
>> diff --git a/arch/x86/kernel/mem_encrypt_init.c b/arch/x86/kernel/mem_encrypt_init.c
>> new file mode 100644
>> index 0000000..388d6fb
>> --- /dev/null
>> +++ b/arch/x86/kernel/mem_encrypt_init.c
>
> So nothing in the commit message explains why we need a separate
> mem_encrypt_init.c file when we already have arch/x86/mm/mem_encrypt.c
> for all memory encryption code...
I can expand on the commit message about that. I was trying to keep the
early boot-related code separate from the main code in arch/x86/mm dir.
Thanks,
Tom
>
>> @@ -0,0 +1,29 @@
>> +/*
>> + * AMD Memory Encryption Support
>> + *
>> + * Copyright (C) 2016 Advanced Micro Devices, Inc.
>> + *
>> + * Author: Tom Lendacky <thomas.lendacky@amd.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/linkage.h>
>> +#include <linux/init.h>
>> +#include <linux/mem_encrypt.h>
>> +
>> +void __init sme_encrypt_kernel(void)
>> +{
>> +}
>> +
>> +unsigned long __init sme_get_me_mask(void)
>> +{
>> + return sme_me_mask;
>> +}
>> +
>> +unsigned long __init sme_enable(void)
>> +{
>> + return sme_me_mask;
>> +}
>
^ permalink raw reply
* Re: [RFC PATCH v3 06/20] x86: Add support to enable SME during early boot processing
From: Tom Lendacky @ 2016-11-14 18:18 UTC (permalink / raw)
To: Borislav Petkov
Cc: linux-arch, linux-efi, kvm, linux-doc, x86, linux-kernel,
kasan-dev, linux-mm, iommu, Rik van Riel,
Radim Krčmář, Arnd Bergmann, Jonathan Corbet,
Matt Fleming, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini,
Larry Woodman, Ingo Molnar, Andy Lutomirski, H. Peter Anvin,
Andrey Ryabinin, Alexander Potapenko, Thomas Gleixner,
Dmitry Vyukov
In-Reply-To: <20161114172930.27z7p2kytmhtcbsb@pd.tnic>
On 11/14/2016 11:29 AM, Borislav Petkov wrote:
> On Wed, Nov 09, 2016 at 06:35:43PM -0600, Tom Lendacky wrote:
>> This patch adds support to the early boot code to use Secure Memory
>> Encryption (SME). Support is added to update the early pagetables with
>> the memory encryption mask and to encrypt the kernel in place.
>>
>> The routines to set the encryption mask and perform the encryption are
>> stub routines for now with full function to be added in a later patch.
>>
>> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
>> ---
>> arch/x86/kernel/Makefile | 2 ++
>> arch/x86/kernel/head_64.S | 35 ++++++++++++++++++++++++++++++++++-
>> arch/x86/kernel/mem_encrypt_init.c | 29 +++++++++++++++++++++++++++++
>> 3 files changed, 65 insertions(+), 1 deletion(-)
>> create mode 100644 arch/x86/kernel/mem_encrypt_init.c
>>
>> diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
>> index 45257cf..27e22f4 100644
>> --- a/arch/x86/kernel/Makefile
>> +++ b/arch/x86/kernel/Makefile
>> @@ -141,4 +141,6 @@ ifeq ($(CONFIG_X86_64),y)
>>
>> obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o
>> obj-y += vsmp_64.o
>> +
>> + obj-y += mem_encrypt_init.o
>> endif
>> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
>> index c98a559..9a28aad 100644
>> --- a/arch/x86/kernel/head_64.S
>> +++ b/arch/x86/kernel/head_64.S
>> @@ -95,6 +95,17 @@ startup_64:
>> jnz bad_address
>>
>> /*
>> + * Enable Secure Memory Encryption (if available). Save the mask
>> + * in %r12 for later use and add the memory encryption mask to %rbp
>> + * to include it in the page table fixups.
>> + */
>> + push %rsi
>> + call sme_enable
>> + pop %rsi
>
> Why %rsi?
>
> sme_enable() is void so no args in registers and returns in %rax.
>
> /me is confused.
The %rsi register can be clobbered by the called function so I'm saving
it since it points to the real mode data. I might be able to look into
saving it earlier and restoring it before needed, but I though this
might be clearer.
>
>> + movq %rax, %r12
>> + addq %r12, %rbp
>> +
>> + /*
>> * Fixup the physical addresses in the page table
>> */
>> addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
>> @@ -117,6 +128,7 @@ startup_64:
>> shrq $PGDIR_SHIFT, %rax
>>
>> leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
>> + addq %r12, %rdx
>> movq %rdx, 0(%rbx,%rax,8)
>> movq %rdx, 8(%rbx,%rax,8)
>>
>> @@ -133,6 +145,7 @@ startup_64:
>> movq %rdi, %rax
>> shrq $PMD_SHIFT, %rdi
>> addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
>> + addq %r12, %rax
>> leaq (_end - 1)(%rip), %rcx
>> shrq $PMD_SHIFT, %rcx
>> subq %rdi, %rcx
>> @@ -163,9 +176,21 @@ startup_64:
>> cmp %r8, %rdi
>> jne 1b
>>
>> - /* Fixup phys_base */
>> + /*
>> + * Fixup phys_base, remove the memory encryption mask from %rbp
>> + * to obtain the true physical address.
>> + */
>> + subq %r12, %rbp
>> addq %rbp, phys_base(%rip)
>>
>> + /*
>> + * The page tables have been updated with the memory encryption mask,
>> + * so encrypt the kernel if memory encryption is active
>> + */
>> + push %rsi
>> + call sme_encrypt_kernel
>> + pop %rsi
>
> Ditto.
>
>> +
>> movq $(early_level4_pgt - __START_KERNEL_map), %rax
>> jmp 1f
>> ENTRY(secondary_startup_64)
>> @@ -186,9 +211,17 @@ ENTRY(secondary_startup_64)
>> /* Sanitize CPU configuration */
>> call verify_cpu
>>
>> + push %rsi
>> + call sme_get_me_mask
>> + pop %rsi
>
> Ditto.
>
>> + movq %rax, %r12
>> +
>> movq $(init_level4_pgt - __START_KERNEL_map), %rax
>> 1:
>>
>> + /* Add the memory encryption mask to RAX */
>
> I think that should say something like:
>
> /*
> * Add the memory encryption mask to init_level4_pgt's physical address
> */
>
> or so...
Yup, I'll expand on the comment for this.
>
>> + addq %r12, %rax
>> +
>> /* Enable PAE mode and PGE */
>> movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
>> movq %rcx, %cr4
>> diff --git a/arch/x86/kernel/mem_encrypt_init.c b/arch/x86/kernel/mem_encrypt_init.c
>> new file mode 100644
>> index 0000000..388d6fb
>> --- /dev/null
>> +++ b/arch/x86/kernel/mem_encrypt_init.c
>
> So nothing in the commit message explains why we need a separate
> mem_encrypt_init.c file when we already have arch/x86/mm/mem_encrypt.c
> for all memory encryption code...
I can expand on the commit message about that. I was trying to keep the
early boot-related code separate from the main code in arch/x86/mm dir.
Thanks,
Tom
>
>> @@ -0,0 +1,29 @@
>> +/*
>> + * AMD Memory Encryption Support
>> + *
>> + * Copyright (C) 2016 Advanced Micro Devices, Inc.
>> + *
>> + * Author: Tom Lendacky <thomas.lendacky@amd.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/linkage.h>
>> +#include <linux/init.h>
>> +#include <linux/mem_encrypt.h>
>> +
>> +void __init sme_encrypt_kernel(void)
>> +{
>> +}
>> +
>> +unsigned long __init sme_get_me_mask(void)
>> +{
>> + return sme_me_mask;
>> +}
>> +
>> +unsigned long __init sme_enable(void)
>> +{
>> + return sme_me_mask;
>> +}
>
--
To unsubscribe, send a message with 'unsubscribe linux-mm' in
the body to majordomo@kvack.org. For more info on Linux MM,
see: http://www.linux-mm.org/ .
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^ permalink raw reply
* Re: [PATCH v2 net-next 0/6] bpf: LRU map
From: David Miller @ 2016-11-14 18:19 UTC (permalink / raw)
To: kafai; +Cc: netdev, ast, daniel, kernel-team
In-Reply-To: <1478890511-1346984-1-git-send-email-kafai@fb.com>
From: Martin KaFai Lau <kafai@fb.com>
Date: Fri, 11 Nov 2016 10:55:05 -0800
> This patch set adds LRU map implementation to the existing BPF map
> family.
Alexei and Daniel, can I please get some review of this series?
Thank you.
^ permalink raw reply
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