* [PATCH v2 2/3] i2c: octeon: Fix waiting for operation completion
From: Jan Glauber @ 2016-11-14 18:50 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-i2c, linux-mips, Paul Burton, David Daney, Jan Glauber,
Peter Swain
In-Reply-To: <1479149445-4663-1-git-send-email-jglauber@cavium.com>
From: Paul Burton <paul.burton@imgtec.com>
Commit 1bb1ff3e7c74 ("i2c: octeon: Improve performance if interrupt is
early") modified octeon_i2c_wait() & octeon_i2c_hlc_wait() to attempt to
check for a valid bit being clear & if not to sleep for a while then try
again before waiting on a waitqueue which may time out. However it does
so by sleeping within a function called as the condition provided to
wait_event_timeout() which seems to cause strange behaviour, with the
system hanging during boot with the condition being checked constantly &
the timeout not seeming to have any effect.
Fix this by instead checking for the valid bit being clear in the
octeon_i2c(_hlc)_wait() functions & sleeping there if that condition is
not met, then calling the wait_event_timeout with a condition that does
not sleep.
Tested on a Rhino Labs UTM-8 with Octeon CN7130.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Jan Glauber <jglauber@cavium.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Jan Glauber <jglauber@cavium.com>
[jglauber@cavium.com: removed unused variable]
Cc: Peter Swain <pswain@cavium.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-i2c@vger.kernel.org
---
drivers/i2c/busses/i2c-octeon-core.c | 59 +++++++++---------------------------
1 file changed, 15 insertions(+), 44 deletions(-)
diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c
index 5e63b17..54a9c14 100644
--- a/drivers/i2c/busses/i2c-octeon-core.c
+++ b/drivers/i2c/busses/i2c-octeon-core.c
@@ -36,24 +36,6 @@ static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)
return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
}
-static bool octeon_i2c_test_ready(struct octeon_i2c *i2c, bool *first)
-{
- if (octeon_i2c_test_iflg(i2c))
- return true;
-
- if (*first) {
- *first = false;
- return false;
- }
-
- /*
- * IRQ has signaled an event but IFLG hasn't changed.
- * Sleep and retry once.
- */
- usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
- return octeon_i2c_test_iflg(i2c);
-}
-
/**
* octeon_i2c_wait - wait for the IFLG to be set
* @i2c: The struct octeon_i2c
@@ -63,7 +45,6 @@ static bool octeon_i2c_test_ready(struct octeon_i2c *i2c, bool *first)
static int octeon_i2c_wait(struct octeon_i2c *i2c)
{
long time_left;
- bool first = true;
/*
* Some chip revisions don't assert the irq in the interrupt
@@ -80,8 +61,13 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
}
i2c->int_enable(i2c);
- time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_ready(i2c, &first),
- i2c->adap.timeout);
+ time_left = i2c->adap.timeout;
+ if (!octeon_i2c_test_iflg(i2c)) {
+ usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
+ time_left = wait_event_timeout(i2c->queue,
+ octeon_i2c_test_iflg(i2c),
+ time_left);
+ }
i2c->int_disable(i2c);
if (i2c->broken_irq_check && !time_left &&
@@ -99,26 +85,8 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
{
- return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
-}
-
-static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c, bool *first)
-{
/* check if valid bit is cleared */
- if (octeon_i2c_hlc_test_valid(i2c))
- return true;
-
- if (*first) {
- *first = false;
- return false;
- }
-
- /*
- * IRQ has signaled an event but valid bit isn't cleared.
- * Sleep and retry once.
- */
- usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
- return octeon_i2c_hlc_test_valid(i2c);
+ return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
}
static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
@@ -176,7 +144,6 @@ static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
*/
static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
{
- bool first = true;
int time_left;
/*
@@ -194,9 +161,13 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
}
i2c->hlc_int_enable(i2c);
- time_left = wait_event_timeout(i2c->queue,
- octeon_i2c_hlc_test_ready(i2c, &first),
- i2c->adap.timeout);
+ time_left = i2c->adap.timeout;
+ if (!octeon_i2c_hlc_test_valid(i2c)) {
+ usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
+ time_left = wait_event_timeout(i2c->queue,
+ octeon_i2c_hlc_test_valid(i2c),
+ time_left);
+ }
i2c->hlc_int_disable(i2c);
if (!time_left)
octeon_i2c_hlc_int_clear(i2c);
--
1.9.1
^ permalink raw reply related
* [PATCH v2 3/3] i2c: octeon: thunderx: TWSI software reset in recovery
From: Jan Glauber @ 2016-11-14 18:50 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-i2c, linux-mips, Paul Burton, David Daney, Jan Glauber
In-Reply-To: <1479149445-4663-1-git-send-email-jglauber@cavium.com>
I've seen i2c recovery reporting long loops of:
[ 1035.887818] i2c i2c-4: SCL is stuck low, exit recovery
[ 1037.999748] i2c i2c-4: SCL is stuck low, exit recovery
[ 1040.111694] i2c i2c-4: SCL is stuck low, exit recovery
...
Add a TWSI software reset which clears the status and
STA,STP,IFLG in SW_TWSI_EOP_TWSI_CTL.
With this the recovery works fine and above message is not seen.
Signed-off-by: Jan Glauber <jglauber@cavium.com>
---
drivers/i2c/busses/i2c-octeon-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c
index 54a9c14..c3b63c1 100644
--- a/drivers/i2c/busses/i2c-octeon-core.c
+++ b/drivers/i2c/busses/i2c-octeon-core.c
@@ -760,6 +760,9 @@ static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
struct octeon_i2c *i2c = i2c_get_adapdata(adap);
octeon_i2c_hlc_disable(i2c);
+ octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
+ /* wait for software reset to settle */
+ udelay(5);
/*
* Bring control register to a good state regardless
--
1.9.1
^ permalink raw reply related
* [PATCH] kbuild: Steal gcc's pie from the very beginning
From: Borislav Petkov @ 2016-11-14 18:51 UTC (permalink / raw)
To: linux-kbuild; +Cc: Ben Hutchings, Michal Marek, Sebastian Andrzej Siewior
From: Borislav Petkov <bp@suse.de>
So Sebastian turned off the PIE for kernel builds but that was too late
- Kbuild.include already uses KBUILD_CFLAGS and trying to disable gcc
options with, say cc-disable-warning, fails:
gcc -D__KERNEL__ -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs
...
-Wno-sign-compare -fno-asynchronous-unwind-tables -Wframe-address -c -x c /dev/null -o .31392.tmp
/dev/null:1:0: error: code model kernel does not support PIC mode
because that returns an error and we can't disable the warning. For
example in this case:
KBUILD_CFLAGS += $(call cc-disable-warning,frame-address,)
which leads to gcc issuing all those warnings again.
So let's turn off PIE/PIC at the earliest possible moment, when we
declare KBUILD_CFLAGS so that cc-disable-warning picks it up too.
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Ben Hutchings <ben@decadent.org.uk>
Cc: Michal Marek <mmarek@suse.com>
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
Makefile | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/Makefile b/Makefile
index 3ff1fb26d8b2..5558cc5b1505 100644
--- a/Makefile
+++ b/Makefile
@@ -399,11 +399,12 @@ KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-fno-strict-aliasing -fno-common \
-Werror-implicit-function-declaration \
-Wno-format-security \
- -std=gnu89
+ -std=gnu89 -fno-PIE
+
KBUILD_AFLAGS_KERNEL :=
KBUILD_CFLAGS_KERNEL :=
-KBUILD_AFLAGS := -D__ASSEMBLY__
+KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE
KBUILD_AFLAGS_MODULE := -DMODULE
KBUILD_CFLAGS_MODULE := -DMODULE
KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds
@@ -621,8 +622,6 @@ include arch/$(SRCARCH)/Makefile
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
KBUILD_CFLAGS += $(call cc-disable-warning,frame-address,)
-KBUILD_CFLAGS += $(call cc-option,-fno-PIE)
-KBUILD_AFLAGS += $(call cc-option,-fno-PIE)
ifdef CONFIG_LD_DEAD_CODE_DATA_ELIMINATION
KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,)
--
2.10.0
^ permalink raw reply related
* Re: [PATCH net-next] bpf: fix range arithmetic for bpf map access
From: Josef Bacik @ 2016-11-14 18:52 UTC (permalink / raw)
To: Alexei Starovoitov; +Cc: jannh, ast, daniel, davem, netdev
In-Reply-To: <20161112031338.GA86010@ast-mbp.thefacebook.com>
On 11/11/2016 10:13 PM, Alexei Starovoitov wrote:
> On Fri, Nov 11, 2016 at 04:47:39PM -0500, Josef Bacik wrote:
>> I made some invalid assumptions with BPF_AND and BPF_MOD that could result in
>> invalid accesses to bpf map entries. Fix this up by doing a few things
>>
>> 1) Kill BPF_MOD support. This doesn't actually get used by the compiler in real
>> life and just adds extra complexity.
>>
>> 2) Fix the logic for BPF_AND, don't allow AND of negative numbers and set the
>> minimum value to 0 for positive AND's.
>>
>> 3) Don't do operations on the ranges if they are set to the limits, as they are
>> by definition undefined, and allowing arithmetic operations on those values
>> could make them appear valid when they really aren't.
>>
>> This fixes the testcase provided by Jann as well as a few other theoretical
>> problems.
>>
>> Reported-by: Jann Horn <jannh@google.com>
>> Signed-off-by: Josef Bacik <jbacik@fb.com>
>> ---
>> include/linux/bpf_verifier.h | 3 +-
>> kernel/bpf/verifier.c | 70 +++++++++++++++++++++++++++++---------------
>> 2 files changed, 49 insertions(+), 24 deletions(-)
>>
>> diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h
>> index ac5b393..15ceb7f 100644
>> --- a/include/linux/bpf_verifier.h
>> +++ b/include/linux/bpf_verifier.h
>> @@ -22,7 +22,8 @@ struct bpf_reg_state {
>> * Used to determine if any memory access using this register will
>> * result in a bad access.
>> */
>> - u64 min_value, max_value;
>> + s64 min_value;
>> + u64 max_value;
>> u32 id;
>> union {
>> /* valid when type == CONST_IMM | PTR_TO_STACK | UNKNOWN_VALUE */
>> diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
>> index 89f787c..709fe0e 100644
>> --- a/kernel/bpf/verifier.c
>> +++ b/kernel/bpf/verifier.c
>> @@ -234,8 +234,8 @@ static void print_verifier_state(struct bpf_verifier_state *state)
>> reg->map_ptr->value_size,
>> reg->id);
>> if (reg->min_value != BPF_REGISTER_MIN_RANGE)
>> - verbose(",min_value=%llu",
>> - (unsigned long long)reg->min_value);
>> + verbose(",min_value=%lld",
>> + (long long)reg->min_value);
>> if (reg->max_value != BPF_REGISTER_MAX_RANGE)
>> verbose(",max_value=%llu",
>> (unsigned long long)reg->max_value);
>> @@ -778,7 +778,7 @@ static int check_mem_access(struct bpf_verifier_env *env, u32 regno, int off,
>> * index'es we need to make sure that whatever we use
>> * will have a set floor within our range.
>> */
>> - if ((s64)reg->min_value < 0) {
>> + if (reg->min_value < 0) {
>> verbose("R%d min value is negative, either use unsigned index or do a if (index >=0) check.\n",
>> regno);
>> return -EACCES;
>> @@ -1490,7 +1490,8 @@ static void check_reg_overflow(struct bpf_reg_state *reg)
>> {
>> if (reg->max_value > BPF_REGISTER_MAX_RANGE)
>> reg->max_value = BPF_REGISTER_MAX_RANGE;
>> - if ((s64)reg->min_value < BPF_REGISTER_MIN_RANGE)
>> + if (reg->min_value < BPF_REGISTER_MIN_RANGE ||
>> + reg->min_value > BPF_REGISTER_MAX_RANGE)
>> reg->min_value = BPF_REGISTER_MIN_RANGE;
>> }
>>
>> @@ -1498,7 +1499,8 @@ static void adjust_reg_min_max_vals(struct bpf_verifier_env *env,
>> struct bpf_insn *insn)
>> {
>> struct bpf_reg_state *regs = env->cur_state.regs, *dst_reg;
>> - u64 min_val = BPF_REGISTER_MIN_RANGE, max_val = BPF_REGISTER_MAX_RANGE;
>> + s64 min_val = BPF_REGISTER_MIN_RANGE;
>> + u64 max_val = BPF_REGISTER_MAX_RANGE;
>> u8 opcode = BPF_OP(insn->code);
>>
>> dst_reg = ®s[insn->dst_reg];
>> @@ -1532,22 +1534,43 @@ static void adjust_reg_min_max_vals(struct bpf_verifier_env *env,
>> return;
>> }
>>
>> + /* If one of our values was at the end of our ranges then we can't just
>> + * do our normal operations to the register, we need to set the values
>> + * to the min/max since they are undefined.
>> + */
>> + if (min_val == BPF_REGISTER_MIN_RANGE)
>> + dst_reg->min_value = BPF_REGISTER_MIN_RANGE;
>> + if (max_val == BPF_REGISTER_MAX_RANGE)
>> + dst_reg->max_value = BPF_REGISTER_MAX_RANGE;
>> +
>> switch (opcode) {
>> case BPF_ADD:
>> - dst_reg->min_value += min_val;
>> - dst_reg->max_value += max_val;
>> + if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
>> + dst_reg->min_value += min_val;
>> + if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
>> + dst_reg->max_value += max_val;
>> break;
>> case BPF_SUB:
>> - dst_reg->min_value -= min_val;
>> - dst_reg->max_value -= max_val;
>> + if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
>> + dst_reg->min_value -= min_val;
>> + if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
>> + dst_reg->max_value -= max_val;
>> break;
>> case BPF_MUL:
>> - dst_reg->min_value *= min_val;
>> - dst_reg->max_value *= max_val;
>> + if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
>> + dst_reg->min_value *= min_val;
>
> looks to be few issues here with negative values as well.
> If dst_reg range [-2, 5] and right hand side range is [-2, 10],
> then above will be computed as -2 * -2 == 4
> but even if we do -1 * abs(dst_reg->min) * abs(min), it's still
> incorrect, since dst_reg could be 5 and multiplied by -2 (== -10),
> it will be less than above simple math on min values...
> so I'd suggest to disable negative values everywhere.
>
>> + if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
>> + dst_reg->max_value *= max_val;
>> break;
>> case BPF_AND:
>> - /* & is special since it could end up with 0 bits set. */
>> - dst_reg->min_value &= min_val;
>> + /* Disallow AND'ing of negative numbers, ain't nobody got time
>> + * for that. Otherwise the minimum is 0 and the max is the max
>> + * value we could AND against.
>> + */
>> + if (min_val < 0)
>> + dst_reg->min_value = BPF_REGISTER_MIN_RANGE;
>> + else
>> + dst_reg->min_value = 0;
>> dst_reg->max_value = max_val;
>> break;
>> case BPF_LSH:
>> @@ -1557,24 +1580,25 @@ static void adjust_reg_min_max_vals(struct bpf_verifier_env *env,
>> */
>> if (min_val > ilog2(BPF_REGISTER_MAX_RANGE))
>> dst_reg->min_value = BPF_REGISTER_MIN_RANGE;
>> - else
>> + else if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
>> dst_reg->min_value <<= min_val;
>>
>> if (max_val > ilog2(BPF_REGISTER_MAX_RANGE))
>> dst_reg->max_value = BPF_REGISTER_MAX_RANGE;
>> - else
>> + else if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
>> dst_reg->max_value <<= max_val;
>> break;
>> case BPF_RSH:
>> - dst_reg->min_value >>= min_val;
>> - dst_reg->max_value >>= max_val;
>> - break;
>> - case BPF_MOD:
>> - /* % is special since it is an unsigned modulus, so the floor
>> - * will always be 0.
>> + /* RSH by a negative number is undefined, and the BPF_RSH is an
>> + * unsigned shift, so make the appropriate casts.
>> */
>> - dst_reg->min_value = 0;
>> - dst_reg->max_value = max_val - 1;
>> + if (min_val < 0)
>> + dst_reg->min_value = BPF_REGISTER_MIN_RANGE;
>> + else if (dst_reg->min_value != BPF_REGISTER_MIN_RANGE)
>> + dst_reg->min_value =
>> + (u64)(dst_reg->min_value) >> min_val;
>
> when min_val is negative both >> and << are undefined,
> so we need to avoid negative values for these cases as well.
>
>> + if (dst_reg->max_value != BPF_REGISTER_MAX_RANGE)
>> + dst_reg->max_value >>= max_val;
>
> and for max_val too we need to make sure that max_val >= 0.
Well it's unsigned, so if somebody sets it to a negative value it'll be >
BPF_REGISTER_MAX_RANGE and that'll get caught by the overflow logic above.
>
> To address all of it I'm thinking it will be easier to set
> BPF_REGISTER_MIN_RANGE to -1.
> I don't think we can kill tracking of min_val completely
> and assume valid min starts at zero, since we need either min
> tracking or boolean flag that indicates negative overflow and
> min tracking is imo cleaner (though valid min will always be >=0
> and invalid min is -1)
>
> Also this patch has to go to 'net' tree, so rebasing with net-next
> wasn't necessary.
>
Yeah I'm fine with killing negative values altogether, it does seem a bit silly
to support it and isn't likely to be used in any sort of normal scenario. Thanks,
Josef
^ permalink raw reply
* Re: Freescale Yocto Question - Building imx6dl-riotboard
From: Daiane Angolini @ 2016-11-14 18:53 UTC (permalink / raw)
To: Eric.Zaluzec; +Cc: meta-freescale@yoctoproject.org
In-Reply-To: <12AA5F6040E511488357736B31FF0DAB5B5E61F3@USSTLZ-PMSG009.emrsn.org>
On Mon, Nov 14, 2016 at 4:00 PM, <Eric.Zaluzec@emerson.com> wrote:
> Thanks Daiane, maybe I am getting ahead of myself with the questions.
> Under the FSL Community BSP's "Support Board List", I see the "imx6dl-riotboard / RIotboard / i.MX6S / meta-fsl-arm-extra".
> http://freescale.github.io/doc/release-notes/2.1/index.html#supported-boards
> Is this imx6dl-riotboard BSP and machine configuration file the one that can run on the RIoTboard evaluation platform found on http://riotboard.org/ ?
Yes. I don't have the board so I haven't tested it in a while. Please
test and let us know.
Daiane
> If it is not, do you have reference or a web URL for the one RIoTboard that you support?
>
> Regards,
> -Eric Zaluzec
> (Eric.Zaluzec@Emerson.com)
>
>
> -----Original Message-----
> From: angolini@gmail.com [mailto:angolini@gmail.com] On Behalf Of Daiane Angolini
> Sent: Monday, November 14, 2016 11:20 AM
> To: Zaluzec, Eric [NETPWR/AL]
> Cc: meta-freescale@yoctoproject.org
> Subject: Re: [meta-freescale] Freescale Yocto Question - Building imx6dl-riotboard
>
> On Fri, Nov 11, 2016 at 3:12 PM, <Eric.Zaluzec@emerson.com> wrote:
>> Greeting,
>>
>> I have a quick question concerning the imx6dl-riotboard machine
>> configuration file, maintained by the Yocto Freescale community.
>>
>> We have an upcoming project for which we are considering a i.MX6 Dual
>> Lite processor. But since there are no Dual Lite evaluation boards, at
>> this time, we were provided an i.mx6 solo RIoTboard to use for initial
>> testing, by Avnet and NXP distributors.
>>
>>
>>
>> First off, thank you for providing up-to-date Yocto build repositories
>> and documentation! This makes kicking-off a new Yocto BSP Project much simpler!
>> Cheers.
>>
>> I read the Freescale Yocto User Guide here:
>> http://www.bcmcom.com/CustomerDL/AR6MX/Yocto/Freescale_Yocto_Project_U
>> ser's_Guide.pdf I then read the RIoTboard Yocto build guide here:
>> https://www.element14.com/community/community/designcenter/single-boar
>> d-computers/riotboard/blog/2014/09/22/riotboard-yocto-part1-getting-st
>> arted
>>
>> Using both resources, I successfully built a Yocto image and was able
>> to install onto my RIoTboard.
>>
>>
>>
>>
>>
>> Now, using Yocto, I would like to build a RIoTboard image with a fido
>> or krogoth branch of Yocto, to make use of the updated packages &
>> bitbake recipes, like boost and java, These versions are dependencies
>> to my metadata layer’s packages.
>>
>> I went to the fsl-arm-yocto-bsp git repository site and found the
>> imx-4.1-krogoth branch:
>> http://git.freescale.com/git/cgit.cgi/imx/fsl-arm-yocto-bsp.git/?h=imx
>> -4.1-krogoth
>>
>>
>>
>> I followed the User Guide steps, but this time cloned the
>> imx-4.1-krogoth branch. I noticed the riotboard.conf machine
>> configuration file no longer existed, but a imx6dl-riotboard machine
>> was present in the meta-fsl-arm-extra & meta-freescale-3rdparty
>> metadata layers. I successfully built an image with this machine conf
>> file, but then realized that it was ‘dl’ (Dual Lite?) and would not
>> boot with the solo RIoTboard that I was using.
>>
>>
>>
>> Question :
>>
>> Are there any branches on for the fsl-arm-yocto-bsp repository that
>> are fido/jethro/krogoth compatible, that include the riotboard solo
>> machine configuration file?
>> http://git.freescale.com/git/cgit.cgi/imx/fsl-arm-yocto-bsp.git
>>
>> If not, is it possible for users, like me, to base a riotboard solo
>> machine conf file off the imx6dl-riotboard machine and create a
>> successful BSP image? Or are these unavoidable conflicts?
>>
>>
>>
>> The critical piece here is not necessarily having a v4.1 kernel but
>> just the use of the updated package recipes & the dependency to custom
>> packages trying to be installed & tested on the riotboard!
>>
>>
>>
>> Any help, suggestions, or feedback would greatly be appreciated! Right
>> now I am just tinkering with learning about the riotboard machine conf
>> file to see if I can port it to the imx-4.1-krogoth branch.
>>
>
> I'm not sure you're going to be able to use imx-4.1-krogoth branch with the riot board. Please, take a look at [1]
>
> We have support for one riot board, double check if this is what you are looking for.
>
> [1] http://freescale.github.io/doc/release-notes/2.1/index.html#the-differences-between-project-name-and-freescale-release-name
>
>
> Daiane
>>
>>
>> Thanks!
>> -Eric Zaluzec
>> (Eric.Zaluzec@Emerson.com)
>>
>>
>>
>>
>> --
>> _______________________________________________
>> meta-freescale mailing list
>> meta-freescale@yoctoproject.org
>> https://lists.yoctoproject.org/listinfo/meta-freescale
>>
>
^ permalink raw reply
* Re: [PATCH 1/2] staging: iio: ad7606: replace range/range_available with corresponding scale
From: Lars-Peter Clausen @ 2016-11-14 18:53 UTC (permalink / raw)
To: Linus Walleij, Jonathan Cameron
Cc: Eva Rachel Retuya, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org, Michael Hennerich, Hartmut Knaack,
Peter Meerwald, Greg KH
In-Reply-To: <CACRpkdY6dJGGAZtVNrYwV9uBzGYRH40aqCtL6XZkEQS2uaiK4w@mail.gmail.com>
On 11/14/2016 05:58 PM, Linus Walleij wrote:
> On Sat, Nov 12, 2016 at 3:24 PM, Jonathan Cameron <jic23@kernel.org> wrote:
>
>> Is it just me who thought, we need a fixed GPI like a fixed regulator?
>> Would allow this sort of fixed wiring to be simply defined.
>>
>> Linus, worth exploring?
>
> So if fixed regulator is for a voltage provider, this would be
> pretty much the inverse: deciding for a voltage range by switching
> a GPIO.
It's about figuring out the setting of a "GPIO" that can't be changed from
software.
Devices sometimes, instead of a configuration bus like I2C or SPI, use
simple input pins, that can either be set to high or low, to allow software
the state of the device. The GPIO API is typically used to configure these pins.
This works fine as long as the pin is connected to a GPIO. But sometimes the
system designer decides that a settings does not need to be configurable, in
this case the pin will be tied to logic low or high directly on the PCB
without any GPIO controller being involved.
Sometimes a driver wants to know how the pin is wired up so it can report to
userspace this part runs in the following mode and the mode can't be
changed. In a sense it is like a reverse GPIO hog.
Considering that this is a common usecase the question was how this can be
implemented in a driver independent way to avoid code duplication and
slightly different variations of what is effectively the same DT/ACPI binding.
E.g. lets say for a configurable pin you use
range-gpio = <&gpio ...>;
and for a static pin
range-gpio-fixed = <1>;
Or something similar.
^ permalink raw reply
* [PATCH v2] input: bma150: Only claim to support the bma180 if the separate iio bma180 driver is not build
From: Dmitry Torokhov @ 2016-11-14 18:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114131114.6053-1-hdegoede@redhat.com>
On Mon, Nov 14, 2016 at 02:11:14PM +0100, Hans de Goede wrote:
> commit ef3714fdbc8d ("Input: bma150 - extend chip detection for bma180"),
> adds bma180 chip-ids to the input bma150 driver, assuming that they are
> 100% compatible, but the bma180 is not compatible with the bma150 at all,
> it has 14 bits resolution instead of 10, and it has quite different
> control registers too.
>
> Treating the bma180 as a bma150 wrt its data registers will just result
> in throwing away the lowest 4 bits, which is not too bad. But the ctrl
> registers are a different story. Things happen to just work but supporting
> that certainly does not make treating the bma180 the same as the bma150
> right.
>
> Since some setups depend on the evdev interface the bma150 driver offers
> on top of the bma180, we cannot simply remove the bma180 ids.
>
> So this commit only removes the bma180 id when the bma180 iio driver,
> which does treat the bma180 properly, is enabled.
>
> Cc: Dr. H. Nikolaus Schaller <hns@goldelico.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Applied, thank you.
> ---
> Changes in v2:
> -Use IS_ENABLED(CONFIG_BMA180) instead of #ifdef CONFIG_BMA180
> ---
> drivers/input/misc/bma150.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/input/misc/bma150.c b/drivers/input/misc/bma150.c
> index b0d4453..2124390 100644
> --- a/drivers/input/misc/bma150.c
> +++ b/drivers/input/misc/bma150.c
> @@ -538,8 +538,13 @@ static int bma150_probe(struct i2c_client *client,
> return -EIO;
> }
>
> + /*
> + * Note if the IIO CONFIG_BMA180 driver is enabled we want to fail
> + * the probe for the bma180 as the iio driver is preferred.
> + */
> chip_id = i2c_smbus_read_byte_data(client, BMA150_CHIP_ID_REG);
> - if (chip_id != BMA150_CHIP_ID && chip_id != BMA180_CHIP_ID) {
> + if (chip_id != BMA150_CHIP_ID &&
> + (IS_ENABLED(CONFIG_BMA180) || chip_id != BMA180_CHIP_ID)) {
> dev_err(&client->dev, "BMA150 chip id error: %d\n", chip_id);
> return -EINVAL;
> }
> @@ -643,7 +648,9 @@ static UNIVERSAL_DEV_PM_OPS(bma150_pm, bma150_suspend, bma150_resume, NULL);
>
> static const struct i2c_device_id bma150_id[] = {
> { "bma150", 0 },
> +#if !IS_ENABLED(CONFIG_BMA180)
> { "bma180", 0 },
> +#endif
> { "smb380", 0 },
> { "bma023", 0 },
> { }
> --
> 2.9.3
>
--
Dmitry
^ permalink raw reply
* Re: [PATCH v2] input: bma150: Only claim to support the bma180 if the separate iio bma180 driver is not build
From: Dmitry Torokhov @ 2016-11-14 18:53 UTC (permalink / raw)
To: Hans de Goede; +Cc: linux-input, linux-arm-kernel, Dr . H . Nikolaus Schaller
In-Reply-To: <20161114131114.6053-1-hdegoede@redhat.com>
On Mon, Nov 14, 2016 at 02:11:14PM +0100, Hans de Goede wrote:
> commit ef3714fdbc8d ("Input: bma150 - extend chip detection for bma180"),
> adds bma180 chip-ids to the input bma150 driver, assuming that they are
> 100% compatible, but the bma180 is not compatible with the bma150 at all,
> it has 14 bits resolution instead of 10, and it has quite different
> control registers too.
>
> Treating the bma180 as a bma150 wrt its data registers will just result
> in throwing away the lowest 4 bits, which is not too bad. But the ctrl
> registers are a different story. Things happen to just work but supporting
> that certainly does not make treating the bma180 the same as the bma150
> right.
>
> Since some setups depend on the evdev interface the bma150 driver offers
> on top of the bma180, we cannot simply remove the bma180 ids.
>
> So this commit only removes the bma180 id when the bma180 iio driver,
> which does treat the bma180 properly, is enabled.
>
> Cc: Dr. H. Nikolaus Schaller <hns@goldelico.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Applied, thank you.
> ---
> Changes in v2:
> -Use IS_ENABLED(CONFIG_BMA180) instead of #ifdef CONFIG_BMA180
> ---
> drivers/input/misc/bma150.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/input/misc/bma150.c b/drivers/input/misc/bma150.c
> index b0d4453..2124390 100644
> --- a/drivers/input/misc/bma150.c
> +++ b/drivers/input/misc/bma150.c
> @@ -538,8 +538,13 @@ static int bma150_probe(struct i2c_client *client,
> return -EIO;
> }
>
> + /*
> + * Note if the IIO CONFIG_BMA180 driver is enabled we want to fail
> + * the probe for the bma180 as the iio driver is preferred.
> + */
> chip_id = i2c_smbus_read_byte_data(client, BMA150_CHIP_ID_REG);
> - if (chip_id != BMA150_CHIP_ID && chip_id != BMA180_CHIP_ID) {
> + if (chip_id != BMA150_CHIP_ID &&
> + (IS_ENABLED(CONFIG_BMA180) || chip_id != BMA180_CHIP_ID)) {
> dev_err(&client->dev, "BMA150 chip id error: %d\n", chip_id);
> return -EINVAL;
> }
> @@ -643,7 +648,9 @@ static UNIVERSAL_DEV_PM_OPS(bma150_pm, bma150_suspend, bma150_resume, NULL);
>
> static const struct i2c_device_id bma150_id[] = {
> { "bma150", 0 },
> +#if !IS_ENABLED(CONFIG_BMA180)
> { "bma180", 0 },
> +#endif
> { "smb380", 0 },
> { "bma023", 0 },
> { }
> --
> 2.9.3
>
--
Dmitry
^ permalink raw reply
* Re: [Qemu-devel] [PATCH for-2.8? 0/3] block/curl: Drop TFTP "support"
From: Jeff Cody @ 2016-11-14 18:54 UTC (permalink / raw)
To: Max Reitz; +Cc: Markus Armbruster, Kevin Wolf, qemu-devel, qemu-block
In-Reply-To: <a68090ff-dda6-62eb-704b-1cfbbfde0ad8@redhat.com>
On Fri, Nov 11, 2016 at 08:46:11PM +0100, Max Reitz wrote:
> On 09.11.2016 20:15, Jeff Cody wrote:
> > On Tue, Nov 08, 2016 at 08:14:58AM +0100, Markus Armbruster wrote:
> >> Max Reitz <mreitz@redhat.com> writes:
> >>
> >>> On 07.11.2016 09:20, Markus Armbruster wrote:
> >>>> Max Reitz <mreitz@redhat.com> writes:
> >>>>
> >>>>> On 03.11.2016 08:56, Markus Armbruster wrote:
> >>>>>> Max Reitz <mreitz@redhat.com> writes:
> >>>>>>
> >>>>>>> See patch 3 for the reason why we have actually never supported TFTP at
> >>>>>>> all (except for very small files (i.e. below 256 kB or so)).
> >>>>>>
> >>>>>> Care to explain why it works "for very small files" in a bit more
> >>>>>> detail? PATCH 3 gives a "does not support byte ranges" hint, but to go
> >>>>>> from there to "very small files", you need to know more about how the
> >>>>>> block layer works than I can remember right now.
> >>>>>
> >>>>> Our curl block drivers caches data and uses a readahead cache, which by
> >>>>> default has a size of 256 kB. Therefore, if the start of the file is
> >>>>> read first (which it usually is, if just for format probing), then the
> >>>>> correct data will be read for that size.
> >>>>>
> >>>>> Yes, you can adjust the readahead size. No, I cannot guarantee that
> >>>>> there are no users that just set readahead to the image size and thus
> >>>>> made it work. I can't really imagine that, though, because at that point
> >>>>> you can just copy the file to tmpfs and have the same result.
> >>>>>
> >>>>> Also, if I were a user, I probably wouldn't use 256 kB images, and thus
> >>>>> I would just notice tftp to be broken. I don't think I would experiment
> >>>>> with the readahead option to find out that it works if I set it to the
> >>>>> image size and then just use it that way. I definitely think I would
> >>>>> give up before that and just copy the file to the local system.
> >>>>
> >>>> I'm not trying to make you explain why it's okay to drop TFTP. I'm
> >>>> trying to make you explain what exactly worked and what exactly didn't.
> >>>> Such explanations generally involve a certain degree of "why".
> >>>
> >>> Well, I'm trying to explain both. :-)
> >>>
> >>>> Your first paragraph provides a few more hints, but I'm still guessing.
> >>>> Here's my current best guess:
> >>>>
> >>>> * Commonly, images smaller than 256 KiB work, and larger images don't.
> >>>
> >>> Yes. Unless you set the "readahead" option to something different (it
> >>> just defaults to 256 kB), then it'll commonly work for that images up to
> >>> that size.
> >>>
> >>> Oh, and I just realized it's not called "readahead" for nothing: It gets
> >>> added to the size of the read operation, so if your first read operation
> >>> has a size of 1 GB... Well, then all of that will be correctly cached.
> >>> So both the size and the offset of the first read operation are significant.
> >>>
> >>>> * "Don't work" means the block layer returns garbled data.
> >>>
> >>> Right. It will be data from the image, but not from the offset you want.
> >>>
> >>>> * "Commonly" means when the first read is for offset zero. Begs the
> >>>> question when exactly that's the case. You mentioned format probing.
> >>>> What if the user specified a format? It's okay not to answer this
> >>>> question. I'm not demanding exhaustive analysis, I'm fishing for a
> >>>> better commit message. Such a message may leave some of its questions
> >>>> unanswered.
> >>>
> >>> Well, qcow2 will always start at offset zero anyway (because it reads
> >>> the header first). For raw images, the offset can be anywhere, but if
> >>> you're starting a VM from it, offset zero is obviously likely to be read
> >>> first, too.
> >>>
> >>> (And as a side note, the first read operation for qcow2 images will
> >>> always be 64 kB in size.)
> >>>
> >>> But, yes, for raw images the offset can be anywhere and if it is not
> >>> zero, the answer what works and what doesn't becomes a bit more complicated:
> >>>
> >>> <optional>
> >>> Suppose the first offset read from is 64k. curl will return data from
> >>> offset 0 anyway, so it's pretty much garbage. But if you then do another
> >>> read operation from 0, that will return correct data.
> >>>
> >>> If after that you try to read data from the area that has been covered
> >>> by both read operations... Then it depends on which buffer the curl
> >>> driver sees first, which is most likely the first one, i.e. you'll get
> >>> broken data again.
> >>> </optional>
> >>
> >> There's a lovely addition to your commit message struggling to get out
> >> of your reply.
> >
> > I'm going to go ahead and apply the series; I think the relevant point
> > for the commit message is that TFTP is not usable and never has been. If
> > Max has no objections, I'll pull some wording in from his reply here into
> > his commit message for patch 3, and squash all the patches into one.
> >
> > Max, any objections?
>
> No, that sounds good to me. Thank you very much!
>
> Max
>
Thanks,
Applied to my block branch (squashed, and commit message amended):
git://github.com/codyprime/qemu-kvm-jtc.git block
-Jeff
^ permalink raw reply
* Updates to Documentation (master and morty) in 2016-11-14
From: Daiane Angolini @ 2016-11-14 18:54 UTC (permalink / raw)
To: meta-freescale@yoctoproject.org
commit ccbfddecbba3147ddc505d22e2b89733cdee56fd
Author: Fabio Berton <fabio.berton@ossystems.com.br>
Date: Wed Nov 9 15:30:25 2016 -0200
UG: Update version to 2.2 (Morty)
- Update FSL layers names
- Add DISTRO and MACHINE to run setup-environment
- Update devtasks, nsteps and metadata to use Morty branch and distro
fslc-framebuffer
- Remove qt-in-use-image and qte-in-use-image from image list
- Add FSLC distros description
- Use DISTRO fslc-wayland in weston example
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
commit 4da9ea8a7ad14325f6e3232f597c30b737732ee0
Author: Fabio Berton <fabio.berton@ossystems.com.br>
Date: Wed Nov 9 15:30:24 2016 -0200
RN: Update version to 2.2 (Morty)
- Update FSL layers names
- Update Yocto Project Bugzilla url address
- Add FSLC distros description
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
commit b12aebec37766ec073dd04fc1c8c72b6b13eb59d
Author: Fabio Berton <fabio.berton@ossystems.com.br>
Date: Wed Nov 9 15:30:23 2016 -0200
FAQ: Update version to 2.2 (Morty)
- Update documentation url address to use current realease
- Update Yocto Project Bugzilla url address
- Update copyright year
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
commit 32f16b1625dfd60c1fbec1fb25a0b3ed4e048ad7
Author: Fabio Berton <fabio.berton@ossystems.com.br>
Date: Wed Nov 9 15:30:22 2016 -0200
RN: Updates from bitbake-metadata2doc.sh
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
commit 88e9f62fa34b9da317c859a26e40f09f335c19cd
Author: Fabio Berton <fabio.berton@ossystems.com.br>
Date: Wed Nov 9 15:30:21 2016 -0200
scripts: Update to version 2.2 (Morty)
- Update FSL layers names
- Add DISTRO and MACHINE to run setup-environment
- Update Yocto Project Bugzilla url address
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
^ permalink raw reply
* Re: [PATCH tip/core/rcu 5/7] torture: Trace long read-side delays
From: Josh Triplett @ 2016-11-14 18:54 UTC (permalink / raw)
To: Paul E. McKenney
Cc: linux-kernel, mingo, jiangshanlai, dipankar, akpm,
mathieu.desnoyers, tglx, peterz, rostedt, dhowells, edumazet,
dvhart, fweisbec, oleg, bobby.prani
In-Reply-To: <20161114184421.GP4127@linux.vnet.ibm.com>
On Mon, Nov 14, 2016 at 10:44:21AM -0800, Paul E. McKenney wrote:
> On Mon, Nov 14, 2016 at 09:21:10AM -0800, Josh Triplett wrote:
> > On Mon, Nov 14, 2016 at 08:57:11AM -0800, Paul E. McKenney wrote:
> > > Although rcutorture will occasionally do a 50-millisecond grace-period
> > > delay, these delays are quite rare. And rightly so, because otherwise
> > > the read rate would be quite low. Thie means that it can be important
> > > to identify whether or not a given run contained a long-delay read.
> > > This commit therefore inserts a trace_rcu_torture_read() event to flag
> > > runs containing long delays.
> > >
> > > Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> >
> > A couple of apparent typos below. With those fixed:
> > Reviewed-by: Josh Triplett <josh@joshtriplett.org>
> >
> > > include/trace/events/rcu.h | 5 ++++-
> > > kernel/rcu/rcutorture.c | 11 ++++++++++-
> > > 2 files changed, 14 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/include/trace/events/rcu.h b/include/trace/events/rcu.h
> > > index d3e756539d44..b31e05bc8e26 100644
> > > --- a/include/trace/events/rcu.h
> > > +++ b/include/trace/events/rcu.h
> > > @@ -698,7 +698,10 @@ TRACE_EVENT(rcu_batch_end,
> > > /*
> > > * Tracepoint for rcutorture readers. The first argument is the name
> > > * of the RCU flavor from rcutorture's viewpoint and the second argument
> > > - * is the callback address.
> > > + * is the callback address. The third callback is the start time in
> > > + * seconds, and the last two arguments are the grace period numbers
> > > + * and the beginning and end of the read, respectively. Note that the
> > > + * callback address can be NULL.
> >
> > s/third callback/third argument/?
>
> Good catch, fixed!
>
> > Also, s/and the beginning/of the beginning/?
>
> Let's see... "the last two arguments are the grace period numbers and
> the beginning and end of the read, respectively." -ENONSENSE for sure.
>
> I believe that the "and" needs to become "at" as follows:
>
> "the last two arguments are the grace period numbers at the beginning
> and end of the read, respectively."
>
> Does that help?
That works, yes.
^ permalink raw reply
* [ovmf test] 102229: all pass - PUSHED
From: osstest service owner @ 2016-11-14 18:56 UTC (permalink / raw)
To: xen-devel, osstest-admin
flight 102229 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/102229/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 653bde546200af46573cdfac88257f03b3420d88
baseline version:
ovmf bab82372a9e6ce066fa725a792e71d07191046ca
Last test of basis 102220 2016-11-14 12:26:52 Z 0 days
Testing same since 102229 2016-11-14 16:18:43 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Haojian Zhuang <haojian.zhuang@linaro.org>
Ryan Harkin <ryan.harkin@linaro.org>
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Pushing revision :
+ branch=ovmf
+ revision=653bde546200af46573cdfac88257f03b3420d88
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
++++ getconfig Repos
++++ perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x '!=' x/home/osstest/repos/lock ']'
++ OSSTEST_REPOS_LOCK_LOCKED=/home/osstest/repos/lock
++ exec with-lock-ex -w /home/osstest/repos/lock ./ap-push ovmf 653bde546200af46573cdfac88257f03b3420d88
+ branch=ovmf
+ revision=653bde546200af46573cdfac88257f03b3420d88
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
++++ getconfig Repos
++++ perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x/home/osstest/repos/lock '!=' x/home/osstest/repos/lock ']'
+ . ./cri-common
++ . ./cri-getconfig
++ umask 002
+ select_xenbranch
+ case "$branch" in
+ tree=ovmf
+ xenbranch=xen-unstable
+ '[' xovmf = xlinux ']'
+ linuxbranch=
+ '[' x = x ']'
+ qemuubranch=qemu-upstream-unstable
+ select_prevxenbranch
++ ./cri-getprevxenbranch xen-unstable
+ prevxenbranch=xen-4.7-testing
+ '[' x653bde546200af46573cdfac88257f03b3420d88 = x ']'
+ : tested/2.6.39.x
+ . ./ap-common
++ : osstest@xenbits.xen.org
+++ getconfig OsstestUpstream
+++ perl -e '
use Osstest;
readglobalconfig();
print $c{"OsstestUpstream"} or die $!;
'
++ :
++ : git://xenbits.xen.org/xen.git
++ : osstest@xenbits.xen.org:/home/xen/git/xen.git
++ : git://xenbits.xen.org/qemu-xen-traditional.git
++ : git://git.kernel.org
++ : git://git.kernel.org/pub/scm/linux/kernel/git
++ : git
++ : git://xenbits.xen.org/xtf.git
++ : osstest@xenbits.xen.org:/home/xen/git/xtf.git
++ : git://xenbits.xen.org/xtf.git
++ : git://xenbits.xen.org/libvirt.git
++ : osstest@xenbits.xen.org:/home/xen/git/libvirt.git
++ : git://xenbits.xen.org/libvirt.git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : osstest@xenbits.xen.org:/home/xen/git/osstest/rumprun.git
++ : git://git.seabios.org/seabios.git
++ : osstest@xenbits.xen.org:/home/xen/git/osstest/seabios.git
++ : git://xenbits.xen.org/osstest/seabios.git
++ : https://github.com/tianocore/edk2.git
++ : osstest@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/linux-firmware.git
++ : osstest@xenbits.xen.org:/home/osstest/ext/linux-firmware.git
++ : git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
++ : osstest@xenbits.xen.org:/home/xen/git/linux-pvops.git
++ : git://xenbits.xen.org/linux-pvops.git
++ : tested/linux-3.14
++ : tested/linux-arm-xen
++ '[' xgit://xenbits.xen.org/linux-pvops.git = x ']'
++ '[' x = x ']'
++ : git://xenbits.xen.org/linux-pvops.git
++ : tested/linux-arm-xen
++ : git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen.git
++ : tested/2.6.39.x
++ : daily-cron.ovmf
++ : daily-cron.ovmf
++ : daily-cron.ovmf
++ : daily-cron.ovmf
++ : daily-cron.ovmf
++ : daily-cron.ovmf
++ : daily-cron.ovmf
++ : http://hg.uk.xensource.com/carbon/trunk/linux-2.6.27
++ : git://xenbits.xen.org/qemu-xen.git
++ : osstest@xenbits.xen.org:/home/xen/git/qemu-xen.git
++ : daily-cron.ovmf
++ : git://xenbits.xen.org/qemu-xen.git
++ : git://git.qemu.org/qemu.git
+ TREE_LINUX=osstest@xenbits.xen.org:/home/xen/git/linux-pvops.git
+ TREE_QEMU_UPSTREAM=osstest@xenbits.xen.org:/home/xen/git/qemu-xen.git
+ TREE_XEN=osstest@xenbits.xen.org:/home/xen/git/xen.git
+ TREE_LIBVIRT=osstest@xenbits.xen.org:/home/xen/git/libvirt.git
+ TREE_RUMPRUN=osstest@xenbits.xen.org:/home/xen/git/osstest/rumprun.git
+ TREE_SEABIOS=osstest@xenbits.xen.org:/home/xen/git/osstest/seabios.git
+ TREE_OVMF=osstest@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
+ TREE_XTF=osstest@xenbits.xen.org:/home/xen/git/xtf.git
+ info_linux_tree ovmf
+ case $1 in
+ return 1
+ case "$branch" in
+ cd /home/osstest/repos/ovmf
+ git push osstest@xenbits.xen.org:/home/xen/git/osstest/ovmf.git 653bde546200af46573cdfac88257f03b3420d88:refs/heads/xen-tested-master
To osstest@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
bab8237..653bde5 653bde546200af46573cdfac88257f03b3420d88 -> xen-tested-master
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply
* Re: [PATCH v3 5/6] grep: enable recurse-submodules to work on <tree> objects
From: Junio C Hamano @ 2016-11-14 18:56 UTC (permalink / raw)
To: Jonathan Tan; +Cc: git, sbeller, Brandon Williams
In-Reply-To: <c83066bc-5b2b-998c-7e22-c4fccbaba5de@google.com>
Jonathan Tan <jonathantanmy@google.com> writes:
>>> to:
>>> HEAD:file
>>> HEAD:sub/file
>>>
>>> Signed-off-by: Brandon Williams <bmwill@google.com>
>>> ---
>>
>> Unrelated tangent, but this makes readers wonder what the updated
>> trailer code would do to the last paragraph ;-). Does it behave
>> sensibly (with some sane definition of sensibleness)?
>>
>> I am guessing that it would, because neither To: or HEAD: is what we
>> normally recognize as a known trailer block element.
>
> Yes, it behaves sensibly :-) because "Signed-off-by:" is preceded by a
> blank line, so the trailer block consists only of that line.
Oh, that was not what I was wondering. Imagine Brandon writing his
message that ends in these three questionable lines and then running
"commit -s --amend" to add his sign-off---that was the case I was
wondering.
^ permalink raw reply
* [PATCH v2 1/2] mfd: pm8xxx: add support to pm8821
From: Bjorn Andersson @ 2016-11-14 18:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479145933-9849-1-git-send-email-srinivas.kandagatla@linaro.org>
On Mon 14 Nov 09:52 PST 2016, Srinivas Kandagatla wrote:
> This patch adds support to PM8821 PMIC and interrupt support.
> PM8821 is companion device that supplements primary PMIC PM8921 IC.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> Changes from v1:
> - Removed unnessary locking spotted by Bjorn
> - updated register naming to reflect PM8821
> - lot of cleanups suggested by Bjorn
> - rebased on top of Linus Walleij's pm8xxx namespace
> cleanup patch.
Looks good, just some minor style nits below.
>
> .../devicetree/bindings/mfd/qcom-pm8xxx.txt | 1 +
> drivers/mfd/qcom-pm8xxx.c | 247 ++++++++++++++++++++-
> 2 files changed, 238 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt
> index 37a088f..8f1b4ec 100644
> --- a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt
> +++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt
> @@ -11,6 +11,7 @@ voltages and other various functionality to Qualcomm SoCs.
> Definition: must be one of:
> "qcom,pm8058"
> "qcom,pm8921"
> + "qcom,pm8821"
8 < 9, so move it one step up please.
>
> - #address-cells:
> Usage: required
> diff --git a/drivers/mfd/qcom-pm8xxx.c b/drivers/mfd/qcom-pm8xxx.c
[..]
> +#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
> +#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
> +#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
> +#define PM8821_SSBI_REG(m, b, offset) \
> + ((m == 0) ? \
> + (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
> + (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
> +#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
> +#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
> +#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
> +#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
I like how this cleaned up the rest of the implementation.
[..]
> +static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
> + int master, int block)
> +{
> + int pmirq, irq, i, ret;
> + unsigned int bits;
> +
> + ret = regmap_read(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
> + if (ret) {
> + pr_err("Failed reading %d block ret=%d", block, ret);
"Reading block %d failed ret=%d"
> + return;
> + }
> + if (!bits) {
> + pr_err("block bit set in master but no irqs: %d", block);
This seems more like a debug thing, either showing missbehaving hardware
or something odd in the driver. I think you should drop the print or
make it pr_debug().
> + return;
> + }
I would prefer that you just drop the entire if statement, it's just an
corner case optimization with a info print.
> +
> + /* Convert block offset to global block number */
> + block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
> +
> + /* Check IRQ bits */
> + for (i = 0; i < 8; i++) {
> + if (bits & BIT(i)) {
> + pmirq = block * 8 + i;
> + irq = irq_find_mapping(chip->irqdomain, pmirq);
> + generic_handle_irq(irq);
> + }
> + }
> +
Empty line
> +}
> +
> +static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
> + int master, u8 master_val)
> +{
> + int block;
> +
> + for (block = 1; block < 8; block++)
> + if (master_val & BIT(block))
> + pm8821_irq_block_handler(chip, master, block);
> +
Empty line
> +}
> +
> +static void pm8821_irq_handler(struct irq_desc *desc)
> +{
> + struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
> + struct irq_chip *irq_chip = irq_desc_get_chip(desc);
> + unsigned int master;
> + int ret;
> +
> + chained_irq_enter(irq_chip, desc);
> + ret = regmap_read(chip->regmap,
> + PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
> + if (ret) {
> + pr_err("Failed to re:Qad master 0 ret=%d\n", ret);
^
|
I see you're using vim :)
> + return;
> + }
> +
> + /* bits 1 through 7 marks the first 7 blocks in master 0*/
Indentation
> + if (master & GENMASK(7, 1))
> + pm8821_irq_master_handler(chip, 0, master);
> +
> + /* bit 0 marks if master 1 contains any bits */
Dito
> + if (!(master & BIT(0)))
> + goto done;
> +
> + ret = regmap_read(chip->regmap,
> + PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
> + if (ret) {
> + pr_err("Failed to read master 1 ret=%d\n", ret);
> + return;
"goto done;" so that we pass chained_irq_exit()
> + }
> +
> + pm8821_irq_master_handler(chip, 1, master);
> +
> +done:
> + chained_irq_exit(irq_chip, desc);
> +}
> +
[..]
> +static void pm8821_irq_mask_ack(struct irq_data *d)
> +{
> + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = irqd_to_hwirq(d);
> + u8 block, master;
> + int irq_bit, rc;
> +
> + block = pmirq / 8;
> + master = block / PM8821_BLOCKS_PER_MASTER;
> + irq_bit = pmirq % 8;
> + block %= PM8821_BLOCKS_PER_MASTER;
> +
> + rc = regmap_update_bits(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_MASK(master, block),
> + BIT(irq_bit), BIT(irq_bit));
> +
Empty line
> + if (rc) {
> + pr_err("Failed to read/write mask IRQ:%d rc=%d\n", pmirq, rc);
"Failed to mask IRQ %d rc=%d\n"
> + return;
> + }
> +
> + rc = regmap_update_bits(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
> + BIT(irq_bit), BIT(irq_bit));
> +
Empty line
> + if (rc) {
> + pr_err("Failed to read/write IT_CLEAR IRQ:%d rc=%d\n",
> + pmirq, rc);
"Failed to clear IRQ %d rc=%d\n"
> + }
> +
Empty line
> +}
> +
> +static void pm8821_irq_unmask(struct irq_data *d)
> +{
> + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = irqd_to_hwirq(d);
> + int irq_bit, rc;
> + u8 block, master;
> +
> + block = pmirq / 8;
> + master = block / PM8821_BLOCKS_PER_MASTER;
> + irq_bit = pmirq % 8;
> + block %= PM8821_BLOCKS_PER_MASTER;
> +
> + rc = regmap_update_bits(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_MASK(master, block),
> + BIT(irq_bit), ~BIT(irq_bit));
> +
Empty line
> + if (rc)
> + pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
"Failed to unmask IRQ %d rc=%d\n"
> +
Empty line
> +}
> +
> +static int pm8821_irq_get_irqchip_state(struct irq_data *d,
> + enum irqchip_irq_state which,
> + bool *state)
> +{
> + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + int rc, pmirq = irqd_to_hwirq(d);
> + u8 block, irq_bit, master;
> + unsigned int bits;
> +
> + block = pmirq / 8;
> + master = block / PM8821_BLOCKS_PER_MASTER;
> + irq_bit = pmirq % 8;
> + block %= PM8821_BLOCKS_PER_MASTER;
> +
> + rc = regmap_read(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
> + if (rc) {
> + pr_err("Failed Reading Status rc=%d\n", rc);
Odd capitalization, I suggest that you match it to the other functions
by:
"Reading status of IRQ %d failed rc=%d\n"
> + return rc;
> + }
> +
> + *state = !!(bits & BIT(irq_bit));
> +
> + return rc;
> +}
> +
[..]
>
> static int pm8xxx_probe(struct platform_device *pdev)
> {
> + const struct of_device_id *match;
> + const struct pm_irq_data *data;
> struct regmap *regmap;
> int irq, rc;
> unsigned int val;
> u32 rev;
> struct pm_irq_chip *chip;
> - unsigned int nirqs = PM8XXX_NR_IRQS;
> +
> + match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
> + if (!match) {
> + dev_err(&pdev->dev, "No matching driver data found\n");
> + return -EINVAL;
> + }
> +
> + data = match->data;
data = of_device_get_match_data(&pdev->dev); (from of_device.h)
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH 1/2] ftrace: Provide API to use global filtering for ftrace ops
From: Steven Rostedt @ 2016-11-14 18:56 UTC (permalink / raw)
To: Joel Fernandes; +Cc: linux-kernel, Kees Cook, Ingo Molnar
In-Reply-To: <1476927103-21230-1-git-send-email-joelaf@google.com>
On Wed, 19 Oct 2016 18:31:42 -0700
Joel Fernandes <joelaf@google.com> wrote:
> Currently the global_ops filtering hash is not available to outside
> users registering for function tracing. Provide an API for those
> users to be able to choose global filtering.
>
> This is in preparation for pstore's ftrace feature to be able to
> use the global filters.
>
> Suggested-by: Steven Rostedt <rostedt@goodmis.org>
> Signed-off-by: Joel Fernandes <joelaf@google.com>
> ---
> include/linux/ftrace.h | 2 ++
> kernel/trace/ftrace.c | 13 +++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h
> index 7d565af..653600a 100644
> --- a/include/linux/ftrace.h
> +++ b/include/linux/ftrace.h
> @@ -398,6 +398,7 @@ int ftrace_set_notrace(struct ftrace_ops *ops, unsigned char *buf,
> void ftrace_set_global_filter(unsigned char *buf, int len, int reset);
> void ftrace_set_global_notrace(unsigned char *buf, int len, int reset);
> void ftrace_free_filter(struct ftrace_ops *ops);
> +void ftrace_ops_set_global_filter(struct ftrace_ops *ops);
>
> int register_ftrace_command(struct ftrace_func_command *cmd);
> int unregister_ftrace_command(struct ftrace_func_command *cmd);
> @@ -645,6 +646,7 @@ static inline unsigned long ftrace_location(unsigned long ip)
> #define ftrace_set_filter(ops, buf, len, reset) ({ -ENODEV; })
> #define ftrace_set_notrace(ops, buf, len, reset) ({ -ENODEV; })
> #define ftrace_free_filter(ops) do { } while (0)
> +#define ftrace_ops_set_global_filter(ops) do { } while (0)
>
> static inline ssize_t ftrace_filter_write(struct file *file, const char __user *ubuf,
> size_t cnt, loff_t *ppos) { return -ENODEV; }
> diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
> index 84752c8..c768c7a 100644
> --- a/kernel/trace/ftrace.c
> +++ b/kernel/trace/ftrace.c
> @@ -4233,6 +4233,19 @@ int ftrace_set_filter_ip(struct ftrace_ops *ops, unsigned long ip,
> }
> EXPORT_SYMBOL_GPL(ftrace_set_filter_ip);
>
> +/**
> + * ftrace_ops_set_global_filter - setup ops to use global filters
> + * @ops - the ops which will use the global filters
> + *
> + * ftrace users who need global function trace filtering should call this.
> + */
> +void ftrace_ops_set_global_filter(struct ftrace_ops *ops)
> +{
I think we should add:
if (ops->flags & FTRACE_OPS_FL_INITIALIZED)
return;
This function must only be called if ops hasn't been initialized yet.
Probably need to add that in the comment for the function as well.
But other than that, this looks good. Post an update, and since the
next patch is dependent on this one, It may be best to go through your
tree (after I ack the next version of this patch).
-- Steve
> + ftrace_ops_init(ops);
> + ops->func_hash = &global_ops.local_hash;
> +}
> +EXPORT_SYMBOL_GPL(ftrace_ops_set_global_filter);
> +
> static int
> ftrace_set_regex(struct ftrace_ops *ops, unsigned char *buf, int len,
> int reset, int enable)
^ permalink raw reply
* Re: [PATCH v2 1/2] mfd: pm8xxx: add support to pm8821
From: Bjorn Andersson @ 2016-11-14 18:56 UTC (permalink / raw)
To: Srinivas Kandagatla
Cc: Lee Jones, Rob Herring, Andy Gross, devicetree, linux-kernel,
linux-arm-msm, linux-soc, linux-arm-kernel
In-Reply-To: <1479145933-9849-1-git-send-email-srinivas.kandagatla@linaro.org>
On Mon 14 Nov 09:52 PST 2016, Srinivas Kandagatla wrote:
> This patch adds support to PM8821 PMIC and interrupt support.
> PM8821 is companion device that supplements primary PMIC PM8921 IC.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> Changes from v1:
> - Removed unnessary locking spotted by Bjorn
> - updated register naming to reflect PM8821
> - lot of cleanups suggested by Bjorn
> - rebased on top of Linus Walleij's pm8xxx namespace
> cleanup patch.
Looks good, just some minor style nits below.
>
> .../devicetree/bindings/mfd/qcom-pm8xxx.txt | 1 +
> drivers/mfd/qcom-pm8xxx.c | 247 ++++++++++++++++++++-
> 2 files changed, 238 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt
> index 37a088f..8f1b4ec 100644
> --- a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt
> +++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt
> @@ -11,6 +11,7 @@ voltages and other various functionality to Qualcomm SoCs.
> Definition: must be one of:
> "qcom,pm8058"
> "qcom,pm8921"
> + "qcom,pm8821"
8 < 9, so move it one step up please.
>
> - #address-cells:
> Usage: required
> diff --git a/drivers/mfd/qcom-pm8xxx.c b/drivers/mfd/qcom-pm8xxx.c
[..]
> +#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
> +#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
> +#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
> +#define PM8821_SSBI_REG(m, b, offset) \
> + ((m == 0) ? \
> + (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
> + (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
> +#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
> +#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
> +#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
> +#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
I like how this cleaned up the rest of the implementation.
[..]
> +static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
> + int master, int block)
> +{
> + int pmirq, irq, i, ret;
> + unsigned int bits;
> +
> + ret = regmap_read(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
> + if (ret) {
> + pr_err("Failed reading %d block ret=%d", block, ret);
"Reading block %d failed ret=%d"
> + return;
> + }
> + if (!bits) {
> + pr_err("block bit set in master but no irqs: %d", block);
This seems more like a debug thing, either showing missbehaving hardware
or something odd in the driver. I think you should drop the print or
make it pr_debug().
> + return;
> + }
I would prefer that you just drop the entire if statement, it's just an
corner case optimization with a info print.
> +
> + /* Convert block offset to global block number */
> + block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
> +
> + /* Check IRQ bits */
> + for (i = 0; i < 8; i++) {
> + if (bits & BIT(i)) {
> + pmirq = block * 8 + i;
> + irq = irq_find_mapping(chip->irqdomain, pmirq);
> + generic_handle_irq(irq);
> + }
> + }
> +
Empty line
> +}
> +
> +static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
> + int master, u8 master_val)
> +{
> + int block;
> +
> + for (block = 1; block < 8; block++)
> + if (master_val & BIT(block))
> + pm8821_irq_block_handler(chip, master, block);
> +
Empty line
> +}
> +
> +static void pm8821_irq_handler(struct irq_desc *desc)
> +{
> + struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
> + struct irq_chip *irq_chip = irq_desc_get_chip(desc);
> + unsigned int master;
> + int ret;
> +
> + chained_irq_enter(irq_chip, desc);
> + ret = regmap_read(chip->regmap,
> + PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
> + if (ret) {
> + pr_err("Failed to re:Qad master 0 ret=%d\n", ret);
^
|
I see you're using vim :)
> + return;
> + }
> +
> + /* bits 1 through 7 marks the first 7 blocks in master 0*/
Indentation
> + if (master & GENMASK(7, 1))
> + pm8821_irq_master_handler(chip, 0, master);
> +
> + /* bit 0 marks if master 1 contains any bits */
Dito
> + if (!(master & BIT(0)))
> + goto done;
> +
> + ret = regmap_read(chip->regmap,
> + PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
> + if (ret) {
> + pr_err("Failed to read master 1 ret=%d\n", ret);
> + return;
"goto done;" so that we pass chained_irq_exit()
> + }
> +
> + pm8821_irq_master_handler(chip, 1, master);
> +
> +done:
> + chained_irq_exit(irq_chip, desc);
> +}
> +
[..]
> +static void pm8821_irq_mask_ack(struct irq_data *d)
> +{
> + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = irqd_to_hwirq(d);
> + u8 block, master;
> + int irq_bit, rc;
> +
> + block = pmirq / 8;
> + master = block / PM8821_BLOCKS_PER_MASTER;
> + irq_bit = pmirq % 8;
> + block %= PM8821_BLOCKS_PER_MASTER;
> +
> + rc = regmap_update_bits(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_MASK(master, block),
> + BIT(irq_bit), BIT(irq_bit));
> +
Empty line
> + if (rc) {
> + pr_err("Failed to read/write mask IRQ:%d rc=%d\n", pmirq, rc);
"Failed to mask IRQ %d rc=%d\n"
> + return;
> + }
> +
> + rc = regmap_update_bits(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
> + BIT(irq_bit), BIT(irq_bit));
> +
Empty line
> + if (rc) {
> + pr_err("Failed to read/write IT_CLEAR IRQ:%d rc=%d\n",
> + pmirq, rc);
"Failed to clear IRQ %d rc=%d\n"
> + }
> +
Empty line
> +}
> +
> +static void pm8821_irq_unmask(struct irq_data *d)
> +{
> + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = irqd_to_hwirq(d);
> + int irq_bit, rc;
> + u8 block, master;
> +
> + block = pmirq / 8;
> + master = block / PM8821_BLOCKS_PER_MASTER;
> + irq_bit = pmirq % 8;
> + block %= PM8821_BLOCKS_PER_MASTER;
> +
> + rc = regmap_update_bits(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_MASK(master, block),
> + BIT(irq_bit), ~BIT(irq_bit));
> +
Empty line
> + if (rc)
> + pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
"Failed to unmask IRQ %d rc=%d\n"
> +
Empty line
> +}
> +
> +static int pm8821_irq_get_irqchip_state(struct irq_data *d,
> + enum irqchip_irq_state which,
> + bool *state)
> +{
> + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + int rc, pmirq = irqd_to_hwirq(d);
> + u8 block, irq_bit, master;
> + unsigned int bits;
> +
> + block = pmirq / 8;
> + master = block / PM8821_BLOCKS_PER_MASTER;
> + irq_bit = pmirq % 8;
> + block %= PM8821_BLOCKS_PER_MASTER;
> +
> + rc = regmap_read(chip->regmap,
> + PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
> + if (rc) {
> + pr_err("Failed Reading Status rc=%d\n", rc);
Odd capitalization, I suggest that you match it to the other functions
by:
"Reading status of IRQ %d failed rc=%d\n"
> + return rc;
> + }
> +
> + *state = !!(bits & BIT(irq_bit));
> +
> + return rc;
> +}
> +
[..]
>
> static int pm8xxx_probe(struct platform_device *pdev)
> {
> + const struct of_device_id *match;
> + const struct pm_irq_data *data;
> struct regmap *regmap;
> int irq, rc;
> unsigned int val;
> u32 rev;
> struct pm_irq_chip *chip;
> - unsigned int nirqs = PM8XXX_NR_IRQS;
> +
> + match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
> + if (!match) {
> + dev_err(&pdev->dev, "No matching driver data found\n");
> + return -EINVAL;
> + }
> +
> + data = match->data;
data = of_device_get_match_data(&pdev->dev); (from of_device.h)
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH igt v3 06/11] igt/gem_exec_parse: make basic-rejected version agnostic
From: Matthew Auld @ 2016-11-14 18:57 UTC (permalink / raw)
To: Robert Bragg; +Cc: Intel Graphics Development
In-Reply-To: <20161109161602.2402-7-robert@sixbynine.org>
On 9 November 2016 at 16:15, Robert Bragg <robert@sixbynine.org> wrote:
> This adapts the basic-rejected test to focus on invalid commands that
> will result in an EINVAL errno being returned to userspace even with the
> upcoming version 8 parser change to stop reporting access violations as
> EINVAL errors.
>
> Signed-off-by: Robert Bragg <robert@sixbynine.org>
> ---
> tests/gem_exec_parse.c | 28 +++++++++++++++++-----------
> 1 file changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
> index 368f30b..63f4efe 100644
> --- a/tests/gem_exec_parse.c
> +++ b/tests/gem_exec_parse.c
> @@ -386,33 +386,39 @@ igt_main
> }
>
> igt_subtest("basic-rejected") {
> - uint32_t arb_on_off[] = {
> - MI_ARB_ON_OFF,
> + uint32_t invalid_cmd[] = {
> + (0x7<<29), /* Reserved command type,
> + across all engines */
Maybe make this more clear with something like:
(INSTR_INVALID_CLIENT << INSTR_CLIENT_SHIFT)
Anyway:
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [PATCH 1/2] drm/amd/amdgpu: port of DCE v6 to new headers (v2)
From: Tom St Denis @ 2016-11-14 18:57 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
Port of SI DCE v6 over to new AMDGPU headers. Tested on a
Tahiti with GNOME through various hot plugs/rotations/sizes/fullscreen/windowed and
staging drm/xf86-video-amdgpu.
(v2) Re-factored to remove formatting changes to si_enums.h
as well rename various defines.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 507 +++++++++++----------
drivers/gpu/drm/amd/amdgpu/si_enums.h | 78 ++++
.../gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 12 +
3 files changed, 350 insertions(+), 247 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index b0fdc291bf43..54e309c1eaf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -30,8 +30,19 @@
#include "atombios_encoders.h"
#include "amdgpu_pll.h"
#include "amdgpu_connectors.h"
-#include "si/si_reg.h"
-#include "si/sid.h"
+
+#include "bif/bif_3_0_d.h"
+#include "bif/bif_3_0_sh_mask.h"
+#include "oss/oss_1_0_d.h"
+#include "oss/oss_1_0_sh_mask.h"
+#include "gca/gfx_6_0_d.h"
+#include "gca/gfx_6_0_sh_mask.h"
+#include "gmc/gmc_6_0_d.h"
+#include "gmc/gmc_6_0_sh_mask.h"
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+#include "gca/gfx_7_2_enum.h"
+#include "si_enums.h"
static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -48,12 +59,12 @@ static const u32 crtc_offsets[6] =
static const u32 hpd_offsets[] =
{
- DC_HPD1_INT_STATUS - DC_HPD1_INT_STATUS,
- DC_HPD2_INT_STATUS - DC_HPD1_INT_STATUS,
- DC_HPD3_INT_STATUS - DC_HPD1_INT_STATUS,
- DC_HPD4_INT_STATUS - DC_HPD1_INT_STATUS,
- DC_HPD5_INT_STATUS - DC_HPD1_INT_STATUS,
- DC_HPD6_INT_STATUS - DC_HPD1_INT_STATUS,
+ mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
+ mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
+ mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
+ mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
+ mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
+ mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
};
static const uint32_t dig_offsets[] = {
@@ -73,32 +84,32 @@ static const struct {
uint32_t hpd;
} interrupt_status_offsets[6] = { {
- .reg = DISP_INTERRUPT_STATUS,
+ .reg = mmDISP_INTERRUPT_STATUS,
.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
}, {
- .reg = DISP_INTERRUPT_STATUS_CONTINUE,
+ .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
}, {
- .reg = DISP_INTERRUPT_STATUS_CONTINUE2,
+ .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
}, {
- .reg = DISP_INTERRUPT_STATUS_CONTINUE3,
+ .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
}, {
- .reg = DISP_INTERRUPT_STATUS_CONTINUE4,
+ .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
}, {
- .reg = DISP_INTERRUPT_STATUS_CONTINUE5,
+ .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
@@ -119,7 +130,7 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
{
- if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
+ if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK)
return true;
else
return false;
@@ -129,8 +140,8 @@ static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
{
u32 pos1, pos2;
- pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
- pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
+ pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
+ pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
if (pos1 != pos2)
return true;
@@ -152,7 +163,7 @@ static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
if (crtc >= adev->mode_info.num_crtc)
return;
- if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
+ if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
return;
/* depending on when we hit vblank, we may be close to active; if so,
@@ -180,7 +191,7 @@ static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
if (crtc >= adev->mode_info.num_crtc)
return 0;
else
- return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
+ return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
}
static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
@@ -220,16 +231,16 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
/* flip at hsync for async, default is vsync */
- WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
- EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
+ WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
+ GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
/* update the scanout addresses */
- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(crtc_base));
- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
+ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
(u32)crtc_base);
/* post the write */
- RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
+ RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
}
static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
@@ -237,8 +248,8 @@ static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
{
if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
return -EINVAL;
- *vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + crtc_offsets[crtc]);
- *position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
+ *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
+ *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
return 0;
@@ -261,7 +272,7 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
if (hpd >= adev->mode_info.num_hpd)
return connected;
- if (RREG32(DC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPDx_SENSE)
+ if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
connected = true;
return connected;
@@ -284,12 +295,12 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
if (hpd >= adev->mode_info.num_hpd)
return;
- tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
+ tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
if (connected)
- tmp &= ~DC_HPDx_INT_POLARITY;
+ tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
else
- tmp |= DC_HPDx_INT_POLARITY;
- WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
+ tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
+ WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
}
/**
@@ -312,9 +323,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
continue;
- tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
- tmp |= DC_HPDx_EN;
- WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
+ tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
+ tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
+ WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
@@ -323,9 +334,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
* https://bugzilla.redhat.com/show_bug.cgi?id=726143
* also avoid interrupt storms during dpms.
*/
- tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
- tmp &= ~DC_HPDx_INT_EN;
- WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
+ tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
+ tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
+ WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
continue;
}
@@ -355,9 +366,9 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
continue;
- tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
- tmp &= ~DC_HPDx_EN;
- WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
+ tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
+ tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
+ WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
}
@@ -365,7 +376,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
{
- return SI_DC_GPIO_HPD_A;
+ return mmDC_GPIO_HPD_A;
}
static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)
@@ -380,7 +391,7 @@ static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
if (crtc >= adev->mode_info.num_crtc)
return 0;
else
- return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
+ return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
}
static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
@@ -389,25 +400,25 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
u32 crtc_enabled, tmp, frame_count;
int i, j;
- save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
- save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
+ save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
+ save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
/* disable VGA render */
- WREG32(VGA_RENDER_CONTROL, 0);
+ WREG32(mmVGA_RENDER_CONTROL, 0);
/* blank the display controllers */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
- crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
+ crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK;
if (crtc_enabled) {
save->crtc_enabled[i] = true;
- tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
+ tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
- if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
+ if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) {
dce_v6_0_vblank_wait(adev, i);
- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
- tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
- WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK;
+ WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
}
/* wait for the next frame */
frame_count = evergreen_get_vblank_counter(adev, i);
@@ -418,11 +429,11 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
}
/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
- tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
- tmp &= ~EVERGREEN_CRTC_MASTER_EN;
- WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
+ tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
+ WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
save->crtc_enabled[i] = false;
/* ***** */
} else {
@@ -439,41 +450,41 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
/* update crtc base addresses */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
+ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
upper_32_bits(adev->mc.vram_start));
- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
+ WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
upper_32_bits(adev->mc.vram_start));
- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
+ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
(u32)adev->mc.vram_start);
- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
+ WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
(u32)adev->mc.vram_start);
}
- WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
- WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
+ WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
+ WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
/* unlock regs and wait for update */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
if (save->crtc_enabled[i]) {
- tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
+ tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
if ((tmp & 0x7) != 3) {
tmp &= ~0x7;
tmp |= 0x3;
- WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
+ WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
}
- tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
- if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
- tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
- WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
+ tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
+ if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) {
+ tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
+ WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
}
- tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+ tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
if (tmp & 1) {
tmp &= ~1;
- WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+ WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
}
for (j = 0; j < adev->usec_timeout; j++) {
- tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
- if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
+ tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
+ if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0)
break;
udelay(1);
}
@@ -481,9 +492,9 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
}
/* Unlock vga access */
- WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
+ WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
mdelay(1);
- WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
+ WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
}
@@ -491,8 +502,8 @@ static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
bool render)
{
if (!render)
- WREG32(R_000300_VGA_RENDER_CONTROL,
- RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
+ WREG32(mmVGA_RENDER_CONTROL,
+ RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
}
@@ -526,14 +537,14 @@ void dce_v6_0_disable_dce(struct amdgpu_device *adev)
/*Disable crtc*/
for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
- crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
- EVERGREEN_CRTC_MASTER_EN;
+ crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
+ CRTC_CONTROL__CRTC_MASTER_EN_MASK;
if (crtc_enabled) {
- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
- tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
- tmp &= ~EVERGREEN_CRTC_MASTER_EN;
- WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
+ tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
+ WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
+ WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
}
}
}
@@ -569,19 +580,23 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
case 6:
if (dither == AMDGPU_FMT_DITHER_ENABLE)
/* XXX sort out optimal dither settings */
- tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
- FMT_SPATIAL_DITHER_EN);
+ tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
+ FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
+ FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
else
- tmp |= FMT_TRUNCATE_EN;
+ tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
break;
case 8:
if (dither == AMDGPU_FMT_DITHER_ENABLE)
/* XXX sort out optimal dither settings */
- tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
- FMT_RGB_RANDOM_ENABLE |
- FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
+ tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
+ FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
+ FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
+ FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
+ FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
else
- tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
+ tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
+ FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
break;
case 10:
default:
@@ -589,7 +604,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
break;
}
- WREG32(FMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+ WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
}
/**
@@ -603,7 +618,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
*/
static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
{
- u32 tmp = RREG32(MC_SHARED_CHMAP);
+ u32 tmp = RREG32(mmMC_SHARED_CHMAP);
switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
case 0:
@@ -1100,28 +1115,28 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
}
/* select wm A */
- arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
+ arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
tmp = arb_control3;
tmp &= ~LATENCY_WATERMARK_MASK(3);
tmp |= LATENCY_WATERMARK_MASK(1);
- WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
- WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset,
- (LATENCY_LOW_WATERMARK(latency_watermark_a) |
- LATENCY_HIGH_WATERMARK(line_time)));
+ WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
+ WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
+ ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
+ (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
/* select wm B */
- tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
+ tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
tmp &= ~LATENCY_WATERMARK_MASK(3);
tmp |= LATENCY_WATERMARK_MASK(2);
- WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
- WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset,
- (LATENCY_LOW_WATERMARK(latency_watermark_b) |
- LATENCY_HIGH_WATERMARK(line_time)));
+ WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
+ WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
+ ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
+ (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
/* restore original selection */
- WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
+ WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
/* write the priority marks */
- WREG32(PRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
- WREG32(PRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
+ WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
+ WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
/* save values for DPM */
amdgpu_crtc->line_time = line_time;
@@ -1139,7 +1154,7 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
/*
* Line Buffer Setup
* There are 3 line buffers, each one shared by 2 display controllers.
- * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
+ * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
* the display controllers. The paritioning is done via one of four
* preset allocations specified in bits 21:20:
* 0 - half lb
@@ -1162,14 +1177,14 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
buffer_alloc = 0;
}
- WREG32(DC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
+ WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
DC_LB_MEMORY_CONFIG(tmp));
- WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
- DMIF_BUFFERS_ALLOCATED(buffer_alloc));
+ WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
+ (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
for (i = 0; i < adev->usec_timeout; i++) {
- if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
- DMIF_BUFFERS_ALLOCATED_COMPLETED)
+ if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
+ PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
break;
udelay(1);
}
@@ -1411,12 +1426,12 @@ static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
static const u32 vga_control_regs[6] =
{
- AVIVO_D1VGA_CONTROL,
- AVIVO_D2VGA_CONTROL,
- EVERGREEN_D3VGA_CONTROL,
- EVERGREEN_D4VGA_CONTROL,
- EVERGREEN_D5VGA_CONTROL,
- EVERGREEN_D6VGA_CONTROL,
+ mmD1VGA_CONTROL,
+ mmD2VGA_CONTROL,
+ mmD3VGA_CONTROL,
+ mmD4VGA_CONTROL,
+ mmD5VGA_CONTROL,
+ mmD6VGA_CONTROL,
};
static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
@@ -1436,7 +1451,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
- WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
+ WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
}
static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
@@ -1452,7 +1467,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
struct amdgpu_bo *abo;
uint64_t fb_location, tiling_flags;
uint32_t fb_format, fb_pitch_pixels, pipe_config;
- u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
+ u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
u32 viewport_w, viewport_h;
int r;
bool bypass_lut = false;
@@ -1495,64 +1510,64 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
switch (target_fb->pixel_format) {
case DRM_FORMAT_C8:
- fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
- EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
+ GRPH_FORMAT(GRPH_FORMAT_INDEXED));
break;
case DRM_FORMAT_XRGB4444:
case DRM_FORMAT_ARGB4444:
- fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
- EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
+ GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
#ifdef __BIG_ENDIAN
- fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+ fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
#endif
break;
case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_ARGB1555:
- fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
- EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
+ GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
#ifdef __BIG_ENDIAN
- fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+ fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
#endif
break;
case DRM_FORMAT_BGRX5551:
case DRM_FORMAT_BGRA5551:
- fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
- EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
+ GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
#ifdef __BIG_ENDIAN
- fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+ fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
#endif
break;
case DRM_FORMAT_RGB565:
- fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
- EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
+ GRPH_FORMAT(GRPH_FORMAT_ARGB565));
#ifdef __BIG_ENDIAN
- fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+ fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
#endif
break;
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_ARGB8888:
- fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
- EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
+ GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
#ifdef __BIG_ENDIAN
- fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+ fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
#endif
break;
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_ARGB2101010:
- fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
- EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
+ GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
#ifdef __BIG_ENDIAN
- fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+ fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
#endif
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
case DRM_FORMAT_BGRX1010102:
case DRM_FORMAT_BGRA1010102:
- fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
- EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
+ fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
+ GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
#ifdef __BIG_ENDIAN
- fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+ fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
#endif
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
@@ -1572,75 +1587,75 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
- fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
- fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
- fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
- fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
- fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
- fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
+ fb_format |= GRPH_NUM_BANKS(num_banks);
+ fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
+ fb_format |= GRPH_TILE_SPLIT(tile_split);
+ fb_format |= GRPH_BANK_WIDTH(bankw);
+ fb_format |= GRPH_BANK_HEIGHT(bankh);
+ fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
- fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
+ fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
}
pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
- fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
+ fb_format |= GRPH_PIPE_CONFIG(pipe_config);
dce_v6_0_vga_enable(crtc, false);
/* Make sure surface address is updated at vertical blank rather than
* horizontal blank
*/
- WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(fb_location));
- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+ WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(fb_location));
- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
- (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
- (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
- WREG32(EVERGREEN_GRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
- WREG32(EVERGREEN_GRPH_SWAP_CONTROL + amdgpu_crtc->crtc_offset, fb_swap);
+ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
+ (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
+ WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
+ (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
+ WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
+ WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
/*
* The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
* for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
* retain the full precision throughout the pipeline.
*/
- WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
- (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
- ~EVERGREEN_LUT_10BIT_BYPASS_EN);
+ WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
+ (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
+ ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
if (bypass_lut)
DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
- WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_GRPH_X_START + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_GRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_GRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
- WREG32(EVERGREEN_GRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
+ WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
+ WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
- WREG32(EVERGREEN_GRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
dce_v6_0_grph_enable(crtc, true);
- WREG32(EVERGREEN_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
+ WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
target_fb->height);
x &= ~3;
y &= ~1;
- WREG32(EVERGREEN_VIEWPORT_START + amdgpu_crtc->crtc_offset,
+ WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
(x << 16) | y);
viewport_w = crtc->mode.hdisplay;
viewport_h = (crtc->mode.vdisplay + 1) & ~1;
- WREG32(EVERGREEN_VIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
+ WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
(viewport_w << 16) | viewport_h);
/* set pageflip to happen only at start of vblank interval (front porch) */
- WREG32(EVERGREEN_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
+ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
if (!atomic && fb && fb != crtc->primary->fb) {
amdgpu_fb = to_amdgpu_framebuffer(fb);
@@ -1667,10 +1682,10 @@ static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset,
- EVERGREEN_INTERLEAVE_EN);
+ WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
+ INTERLEAVE_EN);
else
- WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
}
static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
@@ -1683,54 +1698,52 @@ static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
- WREG32(NI_INPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
- (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
- NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
- WREG32(NI_PRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
- NI_GRPH_PRESCALE_BYPASS);
- WREG32(NI_PRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
- NI_OVL_PRESCALE_BYPASS);
- WREG32(NI_INPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
- (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
- NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
-
-
+ WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
+ ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
+ (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
+ WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
+ PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
+ WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
+ PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
+ WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
+ ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
+ (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
- WREG32(EVERGREEN_DC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
- WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
- WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
+ WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
+ WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
+ WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
- WREG32(EVERGREEN_DC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
- WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
+ WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
- WREG32(EVERGREEN_DC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
+ WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
for (i = 0; i < 256; i++) {
- WREG32(EVERGREEN_DC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
+ WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
(amdgpu_crtc->lut_r[i] << 20) |
(amdgpu_crtc->lut_g[i] << 10) |
(amdgpu_crtc->lut_b[i] << 0));
}
- WREG32(NI_DEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
- (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
- NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
- NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
- NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
- WREG32(NI_GAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
- (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
- NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
- WREG32(NI_REGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
- (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
- NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
- WREG32(NI_OUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
- (NI_OUTPUT_CSC_GRPH_MODE(0) |
- NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
+ WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
+ ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
+ (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
+ ICON_DEGAMMA_MODE(0) |
+ (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
+ WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
+ ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
+ (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
+ WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
+ ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
+ (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
+ WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
+ ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
+ (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
/* XXX match this to the depth of the crtc fmt block, move to modeset? */
WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
@@ -1809,12 +1822,12 @@ static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
uint32_t cur_lock;
- cur_lock = RREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset);
+ cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
if (lock)
- cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
+ cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
else
- cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
- WREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
+ cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
+ WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
}
static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
@@ -1822,9 +1835,9 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
- WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset,
- EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
- EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
+ WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
+ (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
+ (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
}
@@ -1834,15 +1847,15 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
- WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+ WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(amdgpu_crtc->cursor_addr));
- WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
+ WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
lower_32_bits(amdgpu_crtc->cursor_addr));
- WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset,
- EVERGREEN_CURSOR_EN |
- EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
- EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
+ WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
+ CUR_CONTROL__CURSOR_EN_MASK |
+ (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
+ (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
}
@@ -1869,9 +1882,9 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
y = 0;
}
- WREG32(EVERGREEN_CUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
- WREG32(EVERGREEN_CUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
- WREG32(EVERGREEN_CUR_SIZE + amdgpu_crtc->crtc_offset,
+ WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
+ WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
+ WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
amdgpu_crtc->cursor_x = x;
@@ -2475,14 +2488,14 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
- interrupt_mask = RREG32(INT_MASK + reg_block);
+ interrupt_mask = RREG32(mmINT_MASK + reg_block);
interrupt_mask &= ~VBLANK_INT_MASK;
- WREG32(INT_MASK + reg_block, interrupt_mask);
+ WREG32(mmINT_MASK + reg_block, interrupt_mask);
break;
case AMDGPU_IRQ_STATE_ENABLE:
- interrupt_mask = RREG32(INT_MASK + reg_block);
+ interrupt_mask = RREG32(mmINT_MASK + reg_block);
interrupt_mask |= VBLANK_INT_MASK;
- WREG32(INT_MASK + reg_block, interrupt_mask);
+ WREG32(mmINT_MASK + reg_block, interrupt_mask);
break;
default:
break;
@@ -2510,14 +2523,14 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
- dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
+ dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
- WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
+ WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
break;
case AMDGPU_IRQ_STATE_ENABLE:
- dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
+ dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
dc_hpd_int_cntl |= DC_HPDx_INT_EN;
- WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
+ WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
break;
default:
break;
@@ -2585,7 +2598,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
switch (entry->src_data) {
case 0: /* vblank */
if (disp_int & interrupt_status_offsets[crtc].vblank)
- WREG32(VBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
+ WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
else
DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
@@ -2596,7 +2609,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
break;
case 1: /* vline */
if (disp_int & interrupt_status_offsets[crtc].vline)
- WREG32(VLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
+ WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
else
DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
@@ -2622,12 +2635,12 @@ static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
return -EINVAL;
}
- reg = RREG32(GRPH_INT_CONTROL + crtc_offsets[type]);
+ reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
if (state == AMDGPU_IRQ_STATE_DISABLE)
- WREG32(GRPH_INT_CONTROL + crtc_offsets[type],
+ WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
else
- WREG32(GRPH_INT_CONTROL + crtc_offsets[type],
+ WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
return 0;
@@ -2650,9 +2663,9 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
return -EINVAL;
}
- if (RREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id]) &
+ if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
- WREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id],
+ WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
/* IRQ could occur when in initial stage */
@@ -2703,9 +2716,9 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
mask = interrupt_status_offsets[hpd].hpd;
if (disp_int & mask) {
- tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
+ tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
- WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
+ WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
schedule_work(&adev->hotplug_work);
DRM_INFO("IH: HPD%d\n", hpd + 1);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
index 3ecd36f30e2a..fde2086246fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
@@ -23,6 +23,84 @@
#ifndef SI_ENUMS_H
#define SI_ENUMS_H
+#define VBLANK_INT_MASK (1 << 0)
+#define DC_HPDx_INT_EN (1 << 16)
+#define VBLANK_ACK (1 << 4)
+#define VLINE_ACK (1 << 4)
+
+#define CURSOR_WIDTH 64
+#define CURSOR_HEIGHT 64
+
+#define VGA_VSTATUS_CNTL 0xFFFCFFFF
+#define PRIORITY_MARK_MASK 0x7fff
+#define PRIORITY_OFF (1 << 16)
+#define PRIORITY_ALWAYS_ON (1 << 20)
+#define INTERLEAVE_EN (1 << 0)
+
+#define LATENCY_WATERMARK_MASK(x) ((x) << 16)
+#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
+#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
+
+#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
+#define GRPH_ENDIAN_NONE 0
+#define GRPH_ENDIAN_8IN16 1
+#define GRPH_ENDIAN_8IN32 2
+#define GRPH_ENDIAN_8IN64 3
+
+#define GRPH_DEPTH(x) (((x) & 0x3) << 0)
+#define GRPH_DEPTH_8BPP 0
+#define GRPH_DEPTH_16BPP 1
+#define GRPH_DEPTH_32BPP 2
+
+#define GRPH_FORMAT(x) (((x) & 0x7) << 8)
+#define GRPH_FORMAT_INDEXED 0
+#define GRPH_FORMAT_ARGB1555 0
+#define GRPH_FORMAT_ARGB565 1
+#define GRPH_FORMAT_ARGB4444 2
+#define GRPH_FORMAT_AI88 3
+#define GRPH_FORMAT_MONO16 4
+#define GRPH_FORMAT_BGRA5551 5
+#define GRPH_FORMAT_ARGB8888 0
+#define GRPH_FORMAT_ARGB2101010 1
+#define GRPH_FORMAT_32BPP_DIG 2
+#define GRPH_FORMAT_8B_ARGB2101010 3
+#define GRPH_FORMAT_BGRA1010102 4
+#define GRPH_FORMAT_8B_BGRA1010102 5
+#define GRPH_FORMAT_RGB111110 6
+#define GRPH_FORMAT_BGR101111 7
+
+#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
+#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
+#define GRPH_ARRAY_LINEAR_GENERAL 0
+#define GRPH_ARRAY_LINEAR_ALIGNED 1
+#define GRPH_ARRAY_1D_TILED_THIN1 2
+#define GRPH_ARRAY_2D_TILED_THIN1 4
+#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
+#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
+#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
+#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
+#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
+#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
+
+#define CURSOR_EN (1 << 0)
+#define CURSOR_MODE(x) (((x) & 0x3) << 8)
+#define CURSOR_MONO 0
+#define CURSOR_24_1 1
+#define CURSOR_24_8_PRE_MULT 2
+#define CURSOR_24_8_UNPRE_MULT 3
+#define CURSOR_2X_MAGNIFY (1 << 16)
+#define CURSOR_FORCE_MC_ON (1 << 20)
+#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
+#define CURSOR_URGENT_ALWAYS 0
+#define CURSOR_URGENT_1_8 1
+#define CURSOR_URGENT_1_4 2
+#define CURSOR_URGENT_3_8 3
+#define CURSOR_URGENT_1_2 4
+#define CURSOR_UPDATE_PENDING (1 << 0)
+#define CURSOR_UPDATE_TAKEN (1 << 1)
+#define CURSOR_UPDATE_LOCK (1 << 16)
+#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
+
#define AMDGPU_NUM_OF_VMIDS 8
#define SI_CRTC0_REGISTER_OFFSET 0
#define SI_CRTC1_REGISTER_OFFSET 0x300
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
index a17973bb63a6..ae798f768853 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
@@ -4442,4 +4442,16 @@
#define mmXDMA_TEST_DEBUG_DATA 0x041D
#define mmXDMA_TEST_DEBUG_INDEX 0x041C
+/* Registers that spilled out of sid.h */
+#define mmDATA_FORMAT 0x1AC0
+#define mmDESKTOP_HEIGHT 0x1AC1
+#define mmDC_LB_MEMORY_SPLIT 0x1AC3
+#define mmPRIORITY_A_CNT 0x1AC6
+#define mmPRIORITY_B_CNT 0x1AC7
+#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32
+#define mmINT_MASK 0x1AD0
+#define mmVLINE_STATUS 0x1AEE
+#define mmVBLANK_STATUS 0x1AEF
+
+
#endif
--
2.10.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related
* [PATCH 2/2] drm/amd/amdgpu: Tidy up formatting in si_enums.h
From: Tom St Denis @ 2016-11-14 18:57 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
In-Reply-To: <20161114185746.18225-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
Clean up formatting/alignment in si_enums.h to make it
more presentable.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
drivers/gpu/drm/amd/amdgpu/si_enums.h | 241 +++++++++++++++++-----------------
1 file changed, 121 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
index fde2086246fa..8fd54f6cd4f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
@@ -146,127 +146,128 @@
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
-#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
- (((op) & 0xFF) << 8) | \
+#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
+ (((op) & 0xFF) << 8) | \
((n) & 0x3FFF) << 16)
+
#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
-#define PACKET3_NOP 0x10
-#define PACKET3_SET_BASE 0x11
-#define PACKET3_BASE_INDEX(x) ((x) << 0)
-#define PACKET3_CLEAR_STATE 0x12
-#define PACKET3_INDEX_BUFFER_SIZE 0x13
-#define PACKET3_DISPATCH_DIRECT 0x15
-#define PACKET3_DISPATCH_INDIRECT 0x16
-#define PACKET3_ALLOC_GDS 0x1B
-#define PACKET3_WRITE_GDS_RAM 0x1C
-#define PACKET3_ATOMIC_GDS 0x1D
-#define PACKET3_ATOMIC 0x1E
-#define PACKET3_OCCLUSION_QUERY 0x1F
-#define PACKET3_SET_PREDICATION 0x20
-#define PACKET3_REG_RMW 0x21
-#define PACKET3_COND_EXEC 0x22
-#define PACKET3_PRED_EXEC 0x23
-#define PACKET3_DRAW_INDIRECT 0x24
-#define PACKET3_DRAW_INDEX_INDIRECT 0x25
-#define PACKET3_INDEX_BASE 0x26
-#define PACKET3_DRAW_INDEX_2 0x27
-#define PACKET3_CONTEXT_CONTROL 0x28
-#define PACKET3_INDEX_TYPE 0x2A
-#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
-#define PACKET3_DRAW_INDEX_AUTO 0x2D
-#define PACKET3_DRAW_INDEX_IMMD 0x2E
-#define PACKET3_NUM_INSTANCES 0x2F
-#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
-#define PACKET3_INDIRECT_BUFFER_CONST 0x31
-#define PACKET3_INDIRECT_BUFFER 0x3F
-#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
-#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
-#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
-#define PACKET3_WRITE_DATA 0x37
-#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
-#define PACKET3_MEM_SEMAPHORE 0x39
-#define PACKET3_MPEG_INDEX 0x3A
-#define PACKET3_COPY_DW 0x3B
-#define PACKET3_WAIT_REG_MEM 0x3C
-#define PACKET3_MEM_WRITE 0x3D
-#define PACKET3_COPY_DATA 0x40
-#define PACKET3_CP_DMA 0x41
-# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
-# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
-# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
-# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
-# define PACKET3_CP_DMA_DIS_WC (1 << 21)
-# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
-# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
-# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
-# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
-# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
-# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
-# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
-#define PACKET3_PFP_SYNC_ME 0x42
-#define PACKET3_SURFACE_SYNC 0x43
-# define PACKET3_DEST_BASE_0_ENA (1 << 0)
-# define PACKET3_DEST_BASE_1_ENA (1 << 1)
-# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
-# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
-# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
-# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
-# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
-# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
-# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
-# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
-# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
-# define PACKET3_DEST_BASE_2_ENA (1 << 19)
-# define PACKET3_DEST_BASE_3_ENA (1 << 21)
-# define PACKET3_TCL1_ACTION_ENA (1 << 22)
-# define PACKET3_TC_ACTION_ENA (1 << 23)
-# define PACKET3_CB_ACTION_ENA (1 << 25)
-# define PACKET3_DB_ACTION_ENA (1 << 26)
-# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
-# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
-#define PACKET3_ME_INITIALIZE 0x44
-#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
-#define PACKET3_COND_WRITE 0x45
-#define PACKET3_EVENT_WRITE 0x46
-#define PACKET3_EVENT_WRITE_EOP 0x47
-#define PACKET3_EVENT_WRITE_EOS 0x48
-#define PACKET3_PREAMBLE_CNTL 0x4A
-# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
-# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
-#define PACKET3_ONE_REG_WRITE 0x57
-#define PACKET3_LOAD_CONFIG_REG 0x5F
-#define PACKET3_LOAD_CONTEXT_REG 0x60
-#define PACKET3_LOAD_SH_REG 0x61
-#define PACKET3_SET_CONFIG_REG 0x68
-#define PACKET3_SET_CONFIG_REG_START 0x00002000
-#define PACKET3_SET_CONFIG_REG_END 0x00002c00
-#define PACKET3_SET_CONTEXT_REG 0x69
-#define PACKET3_SET_CONTEXT_REG_START 0x000a000
-#define PACKET3_SET_CONTEXT_REG_END 0x000a400
-#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
-#define PACKET3_SET_RESOURCE_INDIRECT 0x74
-#define PACKET3_SET_SH_REG 0x76
-#define PACKET3_SET_SH_REG_START 0x00002c00
-#define PACKET3_SET_SH_REG_END 0x00003000
-#define PACKET3_SET_SH_REG_OFFSET 0x77
-#define PACKET3_ME_WRITE 0x7A
-#define PACKET3_SCRATCH_RAM_WRITE 0x7D
-#define PACKET3_SCRATCH_RAM_READ 0x7E
-#define PACKET3_CE_WRITE 0x7F
-#define PACKET3_LOAD_CONST_RAM 0x80
-#define PACKET3_WRITE_CONST_RAM 0x81
-#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
-#define PACKET3_DUMP_CONST_RAM 0x83
-#define PACKET3_INCREMENT_CE_COUNTER 0x84
-#define PACKET3_INCREMENT_DE_COUNTER 0x85
-#define PACKET3_WAIT_ON_CE_COUNTER 0x86
-#define PACKET3_WAIT_ON_DE_COUNTER 0x87
-#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
-#define PACKET3_SET_CE_DE_COUNTERS 0x89
-#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
-#define PACKET3_SWITCH_BUFFER 0x8B
-#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
-#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
-#define PACKET3_SEM_SEL_WAIT (0x7 << 29)
+#define PACKET3_NOP 0x10
+#define PACKET3_SET_BASE 0x11
+#define PACKET3_BASE_INDEX(x) ((x) << 0)
+#define PACKET3_CLEAR_STATE 0x12
+#define PACKET3_INDEX_BUFFER_SIZE 0x13
+#define PACKET3_DISPATCH_DIRECT 0x15
+#define PACKET3_DISPATCH_INDIRECT 0x16
+#define PACKET3_ALLOC_GDS 0x1B
+#define PACKET3_WRITE_GDS_RAM 0x1C
+#define PACKET3_ATOMIC_GDS 0x1D
+#define PACKET3_ATOMIC 0x1E
+#define PACKET3_OCCLUSION_QUERY 0x1F
+#define PACKET3_SET_PREDICATION 0x20
+#define PACKET3_REG_RMW 0x21
+#define PACKET3_COND_EXEC 0x22
+#define PACKET3_PRED_EXEC 0x23
+#define PACKET3_DRAW_INDIRECT 0x24
+#define PACKET3_DRAW_INDEX_INDIRECT 0x25
+#define PACKET3_INDEX_BASE 0x26
+#define PACKET3_DRAW_INDEX_2 0x27
+#define PACKET3_CONTEXT_CONTROL 0x28
+#define PACKET3_INDEX_TYPE 0x2A
+#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
+#define PACKET3_DRAW_INDEX_AUTO 0x2D
+#define PACKET3_DRAW_INDEX_IMMD 0x2E
+#define PACKET3_NUM_INSTANCES 0x2F
+#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
+#define PACKET3_INDIRECT_BUFFER_CONST 0x31
+#define PACKET3_INDIRECT_BUFFER 0x3F
+#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
+#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
+#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
+#define PACKET3_WRITE_DATA 0x37
+#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
+#define PACKET3_MEM_SEMAPHORE 0x39
+#define PACKET3_MPEG_INDEX 0x3A
+#define PACKET3_COPY_DW 0x3B
+#define PACKET3_WAIT_REG_MEM 0x3C
+#define PACKET3_MEM_WRITE 0x3D
+#define PACKET3_COPY_DATA 0x40
+#define PACKET3_CP_DMA 0x41
+#define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
+#define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
+#define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
+#define PACKET3_CP_DMA_CP_SYNC (1 << 31)
+#define PACKET3_CP_DMA_DIS_WC (1 << 21)
+#define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
+#define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
+#define PACKET3_CP_DMA_CMD_SAS (1 << 26)
+#define PACKET3_CP_DMA_CMD_DAS (1 << 27)
+#define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
+#define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
+#define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
+#define PACKET3_PFP_SYNC_ME 0x42
+#define PACKET3_SURFACE_SYNC 0x43
+#define PACKET3_DEST_BASE_0_ENA (1 << 0)
+#define PACKET3_DEST_BASE_1_ENA (1 << 1)
+#define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
+#define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
+#define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
+#define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
+#define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
+#define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
+#define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
+#define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
+#define PACKET3_DB_DEST_BASE_ENA (1 << 14)
+#define PACKET3_DEST_BASE_2_ENA (1 << 19)
+#define PACKET3_DEST_BASE_3_ENA (1 << 21)
+#define PACKET3_TCL1_ACTION_ENA (1 << 22)
+#define PACKET3_TC_ACTION_ENA (1 << 23)
+#define PACKET3_CB_ACTION_ENA (1 << 25)
+#define PACKET3_DB_ACTION_ENA (1 << 26)
+#define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
+#define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
+#define PACKET3_ME_INITIALIZE 0x44
+#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
+#define PACKET3_COND_WRITE 0x45
+#define PACKET3_EVENT_WRITE 0x46
+#define PACKET3_EVENT_WRITE_EOP 0x47
+#define PACKET3_EVENT_WRITE_EOS 0x48
+#define PACKET3_PREAMBLE_CNTL 0x4A
+#define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
+#define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
+#define PACKET3_ONE_REG_WRITE 0x57
+#define PACKET3_LOAD_CONFIG_REG 0x5F
+#define PACKET3_LOAD_CONTEXT_REG 0x60
+#define PACKET3_LOAD_SH_REG 0x61
+#define PACKET3_SET_CONFIG_REG 0x68
+#define PACKET3_SET_CONFIG_REG_START 0x00002000
+#define PACKET3_SET_CONFIG_REG_END 0x00002c00
+#define PACKET3_SET_CONTEXT_REG 0x69
+#define PACKET3_SET_CONTEXT_REG_START 0x000a000
+#define PACKET3_SET_CONTEXT_REG_END 0x000a400
+#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
+#define PACKET3_SET_RESOURCE_INDIRECT 0x74
+#define PACKET3_SET_SH_REG 0x76
+#define PACKET3_SET_SH_REG_START 0x00002c00
+#define PACKET3_SET_SH_REG_END 0x00003000
+#define PACKET3_SET_SH_REG_OFFSET 0x77
+#define PACKET3_ME_WRITE 0x7A
+#define PACKET3_SCRATCH_RAM_WRITE 0x7D
+#define PACKET3_SCRATCH_RAM_READ 0x7E
+#define PACKET3_CE_WRITE 0x7F
+#define PACKET3_LOAD_CONST_RAM 0x80
+#define PACKET3_WRITE_CONST_RAM 0x81
+#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
+#define PACKET3_DUMP_CONST_RAM 0x83
+#define PACKET3_INCREMENT_CE_COUNTER 0x84
+#define PACKET3_INCREMENT_DE_COUNTER 0x85
+#define PACKET3_WAIT_ON_CE_COUNTER 0x86
+#define PACKET3_WAIT_ON_DE_COUNTER 0x87
+#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
+#define PACKET3_SET_CE_DE_COUNTERS 0x89
+#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
+#define PACKET3_SWITCH_BUFFER 0x8B
+#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
+#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
+#define PACKET3_SEM_SEL_WAIT (0x7 << 29)
#endif
--
2.10.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related
* [Qemu-devel] Qemu 2.6 => Qemu 2.7 migration: error while loading state for instance 0x0 of device '0000:00:03.0/virtio-balloon'
From: Stefan Priebe - Profihost AG @ 2016-11-14 18:57 UTC (permalink / raw)
To: qemu-devel
Hello,
today i did a first live migration from Qemu 2.6.2 to Qemu 2.7.0. The VM
is running windows and virtio-balloon and with machine type pc-i440fx-2.5.
The output of the target qemu process was:
kvm_apic_post_load: Yeh
kvm_apic_post_load: Yeh
kvm_apic_post_load: Yeh
kvm_apic_post_load: Yeh
kvm: VQ 2 size 0x80 < last_avail_idx 0x1 - used_idx 0x4
kvm: error while loading state for instance 0x0 of device
'0000:00:03.0/virtio-balloon'
kvm: load of migration failed: Operation not permitted
Greets,
Stefan
^ permalink raw reply
* [U-Boot] [PATCH 4/7] tools: sunxi: Add spl image builder
From: Maxime Ripard @ 2016-11-14 18:58 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161114152527.GH27304@bill-the-cat>
Hi,
On Mon, Nov 14, 2016 at 10:25:27AM -0500, Tom Rini wrote:
> On Mon, Nov 14, 2016 at 04:20:49PM +0100, Maxime Ripard wrote:
> > On Fri, Nov 11, 2016 at 11:20:47AM -0500, Tom Rini wrote:
> > > On Tue, Nov 08, 2016 at 05:21:14PM +0100, Maxime Ripard wrote:
> > >
> > > > This program generates raw SPL images that can be flashed on the NAND with
> > > > the ECC and randomizer properly set up.
> > > >
> > > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > > [snip]
> > > > +++ b/tools/sunxi-spl-image-builder.c
> > > > @@ -0,0 +1,1113 @@
> > > > +/*
> > > > + * Generic binary BCH encoding/decoding library
> > >
> > > OK, but this is also lib/bch.c and re-using lib/ code for tools is a
> > > normal best practice. I'd suggest re-factoring this code in sunxi-tools
> > > sot that it too borrows lib/bch.c from the kernel (and can re-sync
> > > bugfixes if needed). Thanks!
> >
> > I finally figured that out.
> >
> > It turns out that the driver was doing a modulo by 0. I guess gcc's
> > and our libgcc don't have the same behaviour in this case, but in
> > U-boot's case, the function was simply returning (which is kind of
> > odd).
> >
> > I'll send a fix for the driver.
>
> So it's something in how lib/bch.c and lib1funcs.S interact? Please CC
> me on these when fixing whatever side of this it is in the kernel,
> thanks!
Hmm, no, sorry, I meant to reply on the cover letter. The issue isn't
in lib/bch.c, it was really in our NAND driver. No changes required in
the kernel, just an extra patch in this serie :)
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [Qemu-devel] [PATCH v4 0/6] jobs: fix transactional race condition
From: John Snow @ 2016-11-14 18:58 UTC (permalink / raw)
To: jcody; +Cc: qemu-block, kwolf, vsementsov, qemu-devel, stefanha, pbonzini
In-Reply-To: <1478587839-9834-1-git-send-email-jsnow@redhat.com>
Jeff, where did we leave off on this?
--js
On 11/08/2016 01:50 AM, John Snow wrote:
> There are a few problems with transactional job completion right now.
>
> First, if jobs complete so quickly they complete before remaining jobs
> get a chance to join the transaction, the completion mode can leave well
> known state and the QLIST can get corrupted and the transactional jobs
> can complete in batches or phases instead of all together.
>
> Second, if two or more jobs defer to the main loop at roughly the same
> time, it's possible for one job's cleanup to directly invoke the other
> job's cleanup from within the same thread, leading to a situation that
> will deadlock the entire transaction.
>
> Thanks to Vladimir for pointing out these modes of failure.
>
> ===
> v4:
> ===
>
> Key:
> [----] : patches are identical
> [####] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences, respectively
>
> 001/6:[----] [--] 'blockjob: fix dead pointer in txn list'
> 002/6:[----] [--] 'blockjob: add .clean property'
> 003/6:[----] [--] 'blockjob: add .start field'
> 004/6:[0021] [FC] 'blockjob: add block_job_start'
> 005/6:[0010] [FC] 'blockjob: refactor backup_start as backup_job_create'
> 006/6:[----] [--] 'iotests: add transactional failure race test'
>
> 04: Fix command tracers (Kevin)
> Implement the ability to 'start' a 'paused' job (Kevin, Jeff)
> 05: Replace superfluous conditionals with assertions. (Kevin, Jeff)
>
> ===
> v3:
> ===
>
> - Rebase to origin/master, requisite patches now upstream.
>
> ===
> v2:
> ===
>
> - Correct Vladimir's email (Sorry!)
> - Add test as a variant of an existing test [Vladimir]
>
> ________________________________________________________________________________
>
> For convenience, this branch is available at:
> https://github.com/jnsnow/qemu.git branch job-fix-race-condition
> https://github.com/jnsnow/qemu/tree/job-fix-race-condition
>
> This version is tagged job-fix-race-condition-v4:
> https://github.com/jnsnow/qemu/releases/tag/job-fix-race-condition-v4
>
> John Snow (5):
> blockjob: add .clean property
> blockjob: add .start field
> blockjob: add block_job_start
> blockjob: refactor backup_start as backup_job_create
> iotests: add transactional failure race test
>
> Vladimir Sementsov-Ogievskiy (1):
> blockjob: fix dead pointer in txn list
>
> block/backup.c | 63 +++++++++++++++++++---------------
> block/commit.c | 6 ++--
> block/mirror.c | 7 ++--
> block/replication.c | 12 ++++---
> block/stream.c | 6 ++--
> block/trace-events | 6 ++--
> blockdev.c | 81 ++++++++++++++++++++++++++++----------------
> blockjob.c | 58 ++++++++++++++++++++++++-------
> include/block/block_int.h | 23 +++++++------
> include/block/blockjob.h | 9 +++++
> include/block/blockjob_int.h | 11 ++++++
> tests/qemu-iotests/124 | 53 +++++++++++++++++++----------
> tests/qemu-iotests/124.out | 4 +--
> tests/test-blockjob-txn.c | 12 +++----
> 14 files changed, 228 insertions(+), 123 deletions(-)
>
--
—js
^ permalink raw reply
* Re: [PATCH 2/2] sched/autogroup: a zombie thread must not use autogroup->tg
From: Oleg Nesterov @ 2016-11-14 18:58 UTC (permalink / raw)
To: Ingo Molnar, Linus Torvalds, Mike Galbraith, Peter Zijlstra
Cc: hartsjc, vbendel, vlovejoy, linux-kernel
In-Reply-To: <20161114184612.GA15968@redhat.com>
On 11/14, Oleg Nesterov wrote:
>
> +void sched_autogroup_exit_task(struct task_struct *p)
> +{
> + /*
> + * We are going to call exit_notify() and autogroup_move_group() can't
> + * see this thread after that: we can no longer use signal->autogroup.
> + * See the PF_EXITING check in task_wants_autogroup().
> + */
> + sched_move_task(p);
We only need it if task_group_is_autogroup(task_group(p)) but then this code
will need even more comments, lets keep it simple.
Oleg.
^ permalink raw reply
* base64 mail with plain text appendage
From: Benjamin Coddington @ 2016-11-14 18:46 UTC (permalink / raw)
To: linux-nfs
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^ permalink raw reply
* Re: [PATCH 3/3] backports: empty define for __ro_after_init
From: Luis R. Rodriguez @ 2016-11-14 18:59 UTC (permalink / raw)
To: Johannes Berg, Kees Cook; +Cc: Arend van Spriel, Luis R. Rodriguez, backports
In-Reply-To: <1478984842.4226.1.camel@sipsolutions.net>
On Sat, Nov 12, 2016 at 10:07:22PM +0100, Johannes Berg wrote:
> On Sat, 2016-11-12 at 20:18 +0000, Arend van Spriel wrote:
> > nl80211 now uses section qualifier __ro_after_init. However, this
> > is not available in kernels before v4.6. Neither is the section
> > itself hence adding an empty define in backports.
>
> > +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0))
> > +#define __ro_after_init
> > +#endif
>
> Due to how __ro_after_init works, it *has* to be a macro originally, so
> you could just ifndef on itself:
>
> #ifndef __ro_after_init
> #define __ro_after_init
> #endif
>
> and be slightly more compatible in case somebody ever backports it.
Agreed.
> Don't think it really matters much, but why not.
Distributions that do wish to backport the __ro_after_init
mechanism will have this defined, so indeed what you suggest
seems appropriate.
When backporting things like these please try to Cc the original
authors as they can easily provide feedback about issues they can think
of if you backport things one way or another. I've Cc'd Kees but
I think this backport is straight forward -- for older kernels we
just cannot backport this for modules running old kernels where we
cannot modify the kernels, making this a no-op for old kernels
is the best we can then.
Luis
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