* Re: [PATCH nft 0/3] src: add nft log flags support
From: Pablo Neira Ayuso @ 2016-11-14 22:21 UTC (permalink / raw)
To: Liping Zhang; +Cc: netfilter-devel, Liping Zhang
In-Reply-To: <1474794421-5365-1-git-send-email-zlpnobody@163.com>
[-- Attachment #1: Type: text/plain, Size: 1099 bytes --]
On Sun, Sep 25, 2016 at 05:06:58PM +0800, Liping Zhang wrote:
> From: Liping Zhang <liping.zhang@spreadtrum.com>
>
> After NF_LOG_XXX is exposed to the userspace, we can set log flags to
> log more things. The following iptables rule:
> # iptables -A OUTPUT -j LOG --log-tcp-sequence --log-tcp-options \
> --log-ip-options --log-uid --log-macdecode
> is equal to the following nft rule:
> # nft add rule filter OUTPUT log tcpseq,tcpopt,ipopt,uid,macdecode
Sorry, I wanted to have a closer look at this but time has been
running up and I didn't manage to get back to this.
So basically, I would like to explore different syntax for this, eg.
log flags tcp sequence,options
log flags ip options
log flags skuid
log flags ether
I think syntax would be larger, but it would look more consistent to
what we have. Worst case is to get them all set. We can provide a
compact version for this:
log flags all
Please, see sketch patch attached for brainstorming.
Would you have a look into this? Thanks and again sorry for not
getting any sooner on this.
[-- Attachment #2: x.patch --]
[-- Type: text/x-diff, Size: 1416 bytes --]
diff --git a/src/parser_bison.y b/src/parser_bison.y
index 91955c187f3f..286290341ffb 100644
--- a/src/parser_bison.y
+++ b/src/parser_bison.y
@@ -201,6 +201,8 @@ static void location_update(struct location *loc, struct location *rhs, int n)
%token EXPORT "export"
%token MONITOR "monitor"
+%token ALL "all"
+
%token ACCEPT "accept"
%token DROP "drop"
%token CONTINUE "continue"
@@ -268,6 +270,8 @@ static void location_update(struct location *loc, struct location *rhs, int n)
%token GATEWAY "gateway"
%token MTU "mtu"
+%token OPTIONS "options"
+
%token IP6 "ip6"
%token PRIORITY "priority"
%token FLOWLABEL "flowlabel"
@@ -1530,6 +1534,25 @@ log_arg : PREFIX string
$<stmt>0->log.level = $2;
$<stmt>0->log.flags |= STMT_LOG_LEVEL;
}
+ | FLAGS log_flags
+ {
+ ;
+ }
+ ;
+
+log_flags : TCP log_flags_tcp
+ | IP OPTIONS
+ | SKUID
+ | ETHER
+ | ALL
+ ;
+
+log_flags_tcp : log_flags_tcp COMMA log_flag_tcp
+ | log_flag_tcp
+ ;
+
+log_flag_tcp : SEQUENCE
+ | OPTIONS
;
level_type : string
diff --git a/src/scanner.l b/src/scanner.l
index cd7398b4e534..625023f5257c 100644
--- a/src/scanner.l
+++ b/src/scanner.l
@@ -469,6 +469,9 @@ addrstring ({macaddr}|{ip4addr}|{ip6addr})
"notrack" { return NOTRACK; }
+"options" { return OPTIONS; }
+"all" { return ALL; }
+
"xml" { return XML; }
"json" { return JSON; }
^ permalink raw reply related
* Re: Mic detection on Mackbook Pro 12,1 (CS4208)
From: Paulo Fidalgo @ 2016-11-14 22:21 UTC (permalink / raw)
To: Takashi Iwai; +Cc: alsa-devel
In-Reply-To: <s5h1syhg3h9.wl-tiwai@suse.de>
Thanks Takashi for point out, but that document is overwhelming.
I understand that developing drivers for unknown hardware should be
like running in the woods with our eyes covered, but I don't feel I
have the enough knowledge and time to be able to do it.
If helps, when I connect the headset running hda-analyzer tool in
monitor mode I only have events related to the OUTPUT:
Watching 2 cards
======================================
Diff for codec 1/0 (0x10134208):
---
+++
@@ -7,17 +7,17 @@
No Modem Function Group found
Default PCM:
rates [0x0]:
bits [0x0]:
formats [0x0]:
Default Amp-In caps: N/A
Default Amp-Out caps: N/A
GPIO: io=6, o=2, i=0, unsolicited=1, wake=1
- IO[0]: enable=1, dir=1, wake=0, sticky=0, data=1, unsol=0
+ IO[0]: enable=1, dir=1, wake=0, sticky=0, data=0, unsol=0
IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0
IO[2]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0
IO[3]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0
IO[4]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0
IO[5]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0
Node 0x02 [Audio Output] wcaps 0xd043d: Stereo Amp-Out Stripe
Control: name="Headphone Playback Volume", index=0, device=0
ControlAmp: chs=3, dir=1, idx=0, ofs=0
@@ -225,26 +225,24 @@
Power: setting=D3, actual=D3
Connection: 1
0x02
Node 0x12 [Pin Complex] wcaps 0x400501: Stereo
Pincap 0x00000050: OUT Balance
Pin Default 0x90170011: [Fixed] Speaker at Int N/A
Conn = Analog, Color = Unknown
DefAssociation = 0x1, Sequence = 0x1
- Pin-ctls: 0x40: OUT
Power: setting=D3, actual=D3
Connection: 1
0x03
Node 0x13 [Pin Complex] wcaps 0x400501: Stereo
Pincap 0x00000050: OUT Balance
Pin Default 0x90170012: [Fixed] Speaker at Int N/A
Conn = Analog, Color = Unknown
DefAssociation = 0x1, Sequence = 0x2
- Pin-ctls: 0x40: OUT
Power: setting=D3, actual=D3
Connection: 1
0x04
Node 0x14 [Pin Complex] wcaps 0x400501: Stereo
Pincap 0x00000050: OUT Balance
Pin Default 0x90170014: [Fixed] Speaker at Int N/A
Conn = Analog, Color = Unknown
DefAssociation = 0x1, Sequence = 0x4
Is there any other info I can provide to help?
Kind regards,
Paulo Fidalgo
On 11 November 2016 at 20:34, Takashi Iwai <tiwai@suse.de> wrote:
> On Thu, 10 Nov 2016 22:52:52 +0100,
> Paulo Fidalgo wrote:
>>
>> Hi,
>>
>> After reporting the issue on bugzilla
>> (https://bugzilla.kernel.org/show_bug.cgi?id=155601) I felt I could do
>> more in order to try to get a patch to fix the issue.
>>
>> Basically when I plug an headset(mic+headphone), it only detects the
>> headphone not the mic.
>>
>> Since I assumed the "memory address" of the 0x18 pin is wrong, I've
>> tried to change some values in order to get it working.
>
> The value you're referring to isn't a "memory address" at all.
> It's a "pin configuration" value, containing the information like
> the location, purpose, sequence number of the given pin, and it's
> encoded in 32bit integer. Basically it's merely a hint for drivers to
> configure the system properly.
>
> Refer to the HD-audio specification document for more details.
>
>
> Takashi
^ permalink raw reply
* Re: [RESEND/PATCH v6 3/3] clk: qcom: Add A53 clock driver
From: Stephen Boyd @ 2016-11-14 22:21 UTC (permalink / raw)
To: Georgi Djakov
Cc: Bjorn Andersson, mturquette, linux-clk, linux-kernel,
linux-arm-msm, devicetree, Rob Herring
In-Reply-To: <549f87fe-7be9-14b4-8e34-86f7f8dad94e@linaro.org>
On 11/11, Georgi Djakov wrote:
> On 11/03/2016 08:28 PM, Bjorn Andersson wrote:
> >On Wed 02 Nov 15:55 PDT 2016, Stephen Boyd wrote:
> >
> >>On 11/02, Bjorn Andersson wrote:
> >>>On Thu 27 Oct 18:54 PDT 2016, Stephen Boyd wrote:
> >>>
> >>>>On 10/19, Georgi Djakov wrote:
> >>>>>Add a driver for the A53 Clock Controller. It is a hardware block that
> >>>>>implements a combined mux and half integer divider functionality. It can
> >>>>>choose between a fixed-rate clock or the dedicated A53 PLL. The source
> >>>>>and the divider can be set both at the same time.
> >>>>>
> >>>>>This is required for enabling CPU frequency scaling on platforms like
> >>>>>MSM8916.
> >>>>>
> >>>>
> >>>>Please Cc DT reviewers.
> >>>>
> >>>>>Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> >>>>>---
> >>>>> .../devicetree/bindings/clock/qcom,a53cc.txt | 22 +++
> >>>>> drivers/clk/qcom/Kconfig | 8 ++
> >>>>> drivers/clk/qcom/Makefile | 1 +
> >>>>> drivers/clk/qcom/a53cc.c | 155 +++++++++++++++++++++
> >>>>> 4 files changed, 186 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> >>>>> create mode 100644 drivers/clk/qcom/a53cc.c
> >>>>>
> >>>>>diff --git a/Documentation/devicetree/bindings/clock/qcom,a53cc.txt b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> >>>>>new file mode 100644
> >>>>>index 000000000000..a025f062f177
> >>>>>--- /dev/null
> >>>>>+++ b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> >>>>>@@ -0,0 +1,22 @@
> >>>>>+Qualcomm A53 CPU Clock Controller Binding
> >>>>>+------------------------------------------------
> >>>>>+The A53 CPU Clock Controller is hardware, which provides a combined
> >>>>>+mux and divider functionality for the CPU clocks. It can choose between
> >>>>>+a fixed rate clock and the dedicated A53 PLL.
> >>>>>+
> >>>>>+Required properties :
> >>>>>+- compatible : shall contain:
> >>>>>+
> >>>>>+ "qcom,a53cc"
> >>>>>+
> >>>>>+- reg : shall contain base register location and length
> >>>>>+ of the APCS region
> >>>>>+- #clock-cells : shall contain 1
> >>>>>+
> >>>>>+Example:
> >>>>>+
> >>>>>+ apcs: syscon@b011000 {
> >>>>>+ compatible = "qcom,a53cc", "syscon";
> >>>>
> >>>>Why is it a syscon? Is that part used?
> >>>>
> >>>
> >>>I use the register at offset 8 for interrupting the other subsystems, so
> >>>this must be available as something I can poke.
> >>>
> >>>Which makes me think that this should be described as a "simple-mfd" and
> >>>"syscon" with the a53cc node as a child - grabbing the regmap of the
> >>>syscon parent, rather then ioremapping the same region again.
> >>>
> >>
> >>That's sort of a question for DT reviewers. The register space
> >>certainly seems like a free for all with a tilt toward power
> >>management of the CPU, similar to how this was done on Krait
> >>based designs.
> >>
> >
> >Right. But this kind of mashup blocks was the reason why simple-mfd was
> >put in place.
> >
>
> Ok, thanks for the comments. Then i will make it look like this:
>
> apcs: syscon@b011000 {
> compatible = "syscon", "simple-mfd";
> reg = <0x0b011000 0x1000>;
>
> a53mux: clock {
> compatible = "qcom,msm8916-a53cc";
> #clock-cells = <1>;
> };
> };
>
> Thanks,
> Georgi
>
> >>I wonder why we didn't make up some provider/consumer binding for
> >>the "kicking" feature used by SMD/RPM code. Then this could be a
> >>clock provider and a "kick" provider (haha #kick-cells) and the
> >>usage of syscon/regmap wouldn't be mandatory.
> >>
> >
> >I did consider doing that, but had enough dependencies to put in place
> >as it was.
> >
> >I'm in favour of us inventing a kicker API and it's found outside out
> >use cases as well (e.g. virtio/rpmsg).
> >
I'd rather we did this kicker API as well. That way we don't need
to make a syscon and a simple-mfd to get software to work
properly. Don't other silicon vendors need a kicker API as well?
How are they kicking remote processors in other places? GPIOs?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [RESEND/PATCH v6 3/3] clk: qcom: Add A53 clock driver
From: Stephen Boyd @ 2016-11-14 22:21 UTC (permalink / raw)
To: Georgi Djakov
Cc: Bjorn Andersson, mturquette-rdvid1DuHRBWk0Htik3J/w,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring
In-Reply-To: <549f87fe-7be9-14b4-8e34-86f7f8dad94e-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On 11/11, Georgi Djakov wrote:
> On 11/03/2016 08:28 PM, Bjorn Andersson wrote:
> >On Wed 02 Nov 15:55 PDT 2016, Stephen Boyd wrote:
> >
> >>On 11/02, Bjorn Andersson wrote:
> >>>On Thu 27 Oct 18:54 PDT 2016, Stephen Boyd wrote:
> >>>
> >>>>On 10/19, Georgi Djakov wrote:
> >>>>>Add a driver for the A53 Clock Controller. It is a hardware block that
> >>>>>implements a combined mux and half integer divider functionality. It can
> >>>>>choose between a fixed-rate clock or the dedicated A53 PLL. The source
> >>>>>and the divider can be set both at the same time.
> >>>>>
> >>>>>This is required for enabling CPU frequency scaling on platforms like
> >>>>>MSM8916.
> >>>>>
> >>>>
> >>>>Please Cc DT reviewers.
> >>>>
> >>>>>Signed-off-by: Georgi Djakov <georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >>>>>---
> >>>>> .../devicetree/bindings/clock/qcom,a53cc.txt | 22 +++
> >>>>> drivers/clk/qcom/Kconfig | 8 ++
> >>>>> drivers/clk/qcom/Makefile | 1 +
> >>>>> drivers/clk/qcom/a53cc.c | 155 +++++++++++++++++++++
> >>>>> 4 files changed, 186 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> >>>>> create mode 100644 drivers/clk/qcom/a53cc.c
> >>>>>
> >>>>>diff --git a/Documentation/devicetree/bindings/clock/qcom,a53cc.txt b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> >>>>>new file mode 100644
> >>>>>index 000000000000..a025f062f177
> >>>>>--- /dev/null
> >>>>>+++ b/Documentation/devicetree/bindings/clock/qcom,a53cc.txt
> >>>>>@@ -0,0 +1,22 @@
> >>>>>+Qualcomm A53 CPU Clock Controller Binding
> >>>>>+------------------------------------------------
> >>>>>+The A53 CPU Clock Controller is hardware, which provides a combined
> >>>>>+mux and divider functionality for the CPU clocks. It can choose between
> >>>>>+a fixed rate clock and the dedicated A53 PLL.
> >>>>>+
> >>>>>+Required properties :
> >>>>>+- compatible : shall contain:
> >>>>>+
> >>>>>+ "qcom,a53cc"
> >>>>>+
> >>>>>+- reg : shall contain base register location and length
> >>>>>+ of the APCS region
> >>>>>+- #clock-cells : shall contain 1
> >>>>>+
> >>>>>+Example:
> >>>>>+
> >>>>>+ apcs: syscon@b011000 {
> >>>>>+ compatible = "qcom,a53cc", "syscon";
> >>>>
> >>>>Why is it a syscon? Is that part used?
> >>>>
> >>>
> >>>I use the register at offset 8 for interrupting the other subsystems, so
> >>>this must be available as something I can poke.
> >>>
> >>>Which makes me think that this should be described as a "simple-mfd" and
> >>>"syscon" with the a53cc node as a child - grabbing the regmap of the
> >>>syscon parent, rather then ioremapping the same region again.
> >>>
> >>
> >>That's sort of a question for DT reviewers. The register space
> >>certainly seems like a free for all with a tilt toward power
> >>management of the CPU, similar to how this was done on Krait
> >>based designs.
> >>
> >
> >Right. But this kind of mashup blocks was the reason why simple-mfd was
> >put in place.
> >
>
> Ok, thanks for the comments. Then i will make it look like this:
>
> apcs: syscon@b011000 {
> compatible = "syscon", "simple-mfd";
> reg = <0x0b011000 0x1000>;
>
> a53mux: clock {
> compatible = "qcom,msm8916-a53cc";
> #clock-cells = <1>;
> };
> };
>
> Thanks,
> Georgi
>
> >>I wonder why we didn't make up some provider/consumer binding for
> >>the "kicking" feature used by SMD/RPM code. Then this could be a
> >>clock provider and a "kick" provider (haha #kick-cells) and the
> >>usage of syscon/regmap wouldn't be mandatory.
> >>
> >
> >I did consider doing that, but had enough dependencies to put in place
> >as it was.
> >
> >I'm in favour of us inventing a kicker API and it's found outside out
> >use cases as well (e.g. virtio/rpmsg).
> >
I'd rather we did this kicker API as well. That way we don't need
to make a syscon and a simple-mfd to get software to work
properly. Don't other silicon vendors need a kicker API as well?
How are they kicking remote processors in other places? GPIOs?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v6 2/9] tpm: replace symbolic permission with octal for securityfs files
From: Jarkko Sakkinen @ 2016-11-14 22:21 UTC (permalink / raw)
To: Nayna Jain
Cc: tpmdd-devel, peterhuewe, tpmdd, jgunthorpe, linux-kernel,
linux-security-module
In-Reply-To: <1479117656-12403-3-git-send-email-nayna@linux.vnet.ibm.com>
On Mon, Nov 14, 2016 at 05:00:49AM -0500, Nayna Jain wrote:
> checkpatch.pl flags warning for symbolic permissions and suggests
> to replace with octal value.
>
> This patch changes securityfs pseudo files permission
> to octal values in tpm_bios_log_setup().
>
> Signed-off-by: Nayna Jain <nayna@linux.vnet.ibm.com>
Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
/Jarkko
> ---
> drivers/char/tpm/tpm_eventlog.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm_eventlog.c b/drivers/char/tpm/tpm_eventlog.c
> index 42b49c4..9467e31 100644
> --- a/drivers/char/tpm/tpm_eventlog.c
> +++ b/drivers/char/tpm/tpm_eventlog.c
> @@ -378,7 +378,7 @@ struct dentry **tpm_bios_log_setup(const char *name)
>
> bin_file =
> securityfs_create_file("binary_bios_measurements",
> - S_IRUSR | S_IRGRP, tpm_dir,
> + 0440, tpm_dir,
> (void *)&tpm_binary_b_measurements_seqops,
> &tpm_bios_measurements_ops);
> if (is_bad(bin_file))
> @@ -386,7 +386,7 @@ struct dentry **tpm_bios_log_setup(const char *name)
>
> ascii_file =
> securityfs_create_file("ascii_bios_measurements",
> - S_IRUSR | S_IRGRP, tpm_dir,
> + 0440, tpm_dir,
> (void *)&tpm_ascii_b_measurements_seqops,
> &tpm_bios_measurements_ops);
> if (is_bad(ascii_file))
> --
> 2.5.0
>
^ permalink raw reply
* Re: [PATCH v6 2/9] tpm: replace symbolic permission with octal for securityfs files
From: Jarkko Sakkinen @ 2016-11-14 22:21 UTC (permalink / raw)
To: Nayna Jain
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-security-module-u79uwXL29TY76Z2rM5mHXA,
tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
In-Reply-To: <1479117656-12403-3-git-send-email-nayna-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
On Mon, Nov 14, 2016 at 05:00:49AM -0500, Nayna Jain wrote:
> checkpatch.pl flags warning for symbolic permissions and suggests
> to replace with octal value.
>
> This patch changes securityfs pseudo files permission
> to octal values in tpm_bios_log_setup().
>
> Signed-off-by: Nayna Jain <nayna-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
/Jarkko
> ---
> drivers/char/tpm/tpm_eventlog.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm_eventlog.c b/drivers/char/tpm/tpm_eventlog.c
> index 42b49c4..9467e31 100644
> --- a/drivers/char/tpm/tpm_eventlog.c
> +++ b/drivers/char/tpm/tpm_eventlog.c
> @@ -378,7 +378,7 @@ struct dentry **tpm_bios_log_setup(const char *name)
>
> bin_file =
> securityfs_create_file("binary_bios_measurements",
> - S_IRUSR | S_IRGRP, tpm_dir,
> + 0440, tpm_dir,
> (void *)&tpm_binary_b_measurements_seqops,
> &tpm_bios_measurements_ops);
> if (is_bad(bin_file))
> @@ -386,7 +386,7 @@ struct dentry **tpm_bios_log_setup(const char *name)
>
> ascii_file =
> securityfs_create_file("ascii_bios_measurements",
> - S_IRUSR | S_IRGRP, tpm_dir,
> + 0440, tpm_dir,
> (void *)&tpm_ascii_b_measurements_seqops,
> &tpm_bios_measurements_ops);
> if (is_bad(ascii_file))
> --
> 2.5.0
>
------------------------------------------------------------------------------
^ permalink raw reply
* Re: [PATCH v15 02/27] bisect: rewrite `check_term_format` shell function in C
From: Stephan Beyer @ 2016-11-14 22:20 UTC (permalink / raw)
To: Pranit Bauva; +Cc: git
In-Reply-To: <01020157c38b1a74-ad2bcaff-0c92-4af4-9aa0-72d98f4945fc-000000@eu-west-1.amazonses.com>
Hi,
I saw in the recent "What's cooking" mail that this is still waiting
for review, so I thought I could interfere and help reviewing it from a
non-git-developer point of view.
But only two commits for today. The first one seems fine. The second
one makes me write this mail ;-)
On 10/14/2016 04:14 PM, Pranit Bauva wrote:
> +static int check_term_format(const char *term, const char *orig_term)
> +{
[...]
> + if (one_of(term, "help", "start", "skip", "next", "reset",
> + "visualize", "replay", "log", "run", NULL))
[... vs ...]
> -check_term_format () {
> - term=$1
> - git check-ref-format refs/bisect/"$term" ||
> - die "$(eval_gettext "'\$term' is not a valid term")"
> - case "$term" in
> - help|start|terms|skip|next|reset|visualize|replay|log|run)
Is there a reasons why "terms" has been dropped from the list?
Best
Stephan
^ permalink raw reply
* Re: ceph v10.2.4 QE validation status
From: Yuri Weinstein @ 2016-11-14 22:20 UTC (permalink / raw)
To: Ceph Development, Abhishek Varshney, Dachary, Loic, Dachary, Loic,
Weil, Sage, Dillaman, Jason, Nathan Cutler, Ilya Dryomov,
John Spray, Durgin, Josh
In-Reply-To: <CAMMFjmEkMUBCnZFqMr_kcfZgB5jm3CjVNfXpSAXT7ZCwMLQEfg@mail.gmail.com>
See updated status - http://tracker.ceph.com/issues/17487#note-32
Outstanding issues:
knfs - http://tracker.ceph.com/issues/16397 (same as in v10.2.3, Greg
pls review/approve, assumed Approved ?)
upgrade/hammer-x (jewel) - http://tracker.ceph.com/issues/17847 ((Sage
pls review/approve, seems persistent, but maybe not a showstopper)
upgrade/infernalis-x (jewel) - deprecated (Nathan is still working
to make it pass, see issues in the tacker summary above)
Sage, jewel 10.2.4 can be released as soon as you agree with the
findings/summary.
Thx
YuriW
On Fri, Nov 11, 2016 at 8:47 AM, Yuri Weinstein <yweinste@redhat.com> wrote:
> Detailed summary of the QE Validation can be found here
> http://tracker.ceph.com/issues/17487#note-32
>
> The following suites were in scope of this point release validation:
>
> rados (subset 35/50 297 jobs)
> rbd
> rgw
> fs
> krbd
> kcephfs
> knfs
> rest
> hadoop
> samba
> ceph-deploy
> ceph-disk
> upgrade/client-upgrade
> upgrade/hammer-x (jewel)
> upgrade/infernalis-x (jewel) - deprecated
> powercycle
> (please let me know if any suites are missing from this ^ list)
>
> ==============================
> Issues requiring approval/decision:
>
> fs - http://tracker.ceph.com/issues/17832 (Greg pls review/approve)
>
> krbd - http://tracker.ceph.com/issues/17221 (Jason, Ilya pls review/approve)
>
> knfs - http://tracker.ceph.com/issues/16397 (same as in v10.2.3, Greg
> pls review/approve)
>
> upgrade/hammer-x (jewel) - http://tracker.ceph.com/issues/17847 ((Sage
> pls review/approve)
>
> upgrade/infernalis-x (jewel) - deprecated, but Nathan is still working
> to make it pass (Sage pls review/approve)
>
> powercycle - in progress
>
> Thx
> YuriW
^ permalink raw reply
* [patch] netlink.7: srcfix Change buffer size in example code about reading netlink message.
From: dwilder @ 2016-11-14 22:20 UTC (permalink / raw)
To: mtk.manpages; +Cc: linux-man, netdev
The example code in netlink(7) (for reading netlink message) suggests
using
a 4k read buffer with recvmsg. This can cause truncated messages on
systems
using a page size is >4096. Please see:
linux/include/linux/netlink.h (in the kernel source)
<snip>
/*
* skb should fit one page. This choice is good for headerless
malloc.
* But we should limit to 8K so that userspace does not have to
* use enormous buffer sizes on recvmsg() calls just to avoid
* MSG_TRUNC when PAGE_SIZE is very large.
*/
#if PAGE_SIZE < 8192UL
#define NLMSG_GOODSIZE SKB_WITH_OVERHEAD(PAGE_SIZE)
#else
#define NLMSG_GOODSIZE SKB_WITH_OVERHEAD(8192UL)
#endif
#define NLMSG_DEFAULT_SIZE (NLMSG_GOODSIZE - NLMSG_HDRLEN)
<snip>
I was troubleshooting some up-stream code on a ppc64le system
(page:size of 64k) This code had duplicated the example from netlink(7)
and
was using a 4k buffer. On x86-64 with a 4k page size this is not a
problem,
however on the 64k page system some messages were truncated. Using an
8k buffer
as implied in netlink.h prevents problems with any page size.
Lets change the example so others don't propagate the problem further.
Signed-off-by David Wilder <dwilder@us.ibm.com>
--- man7/netlink.7.orig 2016-11-14 13:30:36.522101156 -0800
+++ man7/netlink.7 2016-11-14 13:30:51.002086354 -0800
@@ -511,7 +511,7 @@
.in +4n
.nf
int len;
-char buf[4096];
+char buf[8192];
struct iovec iov = { buf, sizeof(buf) };
struct sockaddr_nl sa;
struct msghdr msg;
^ permalink raw reply
* [PATCH v3 07/25] pci: Add pci_bar_set_addr()
From: Peter Xu @ 2016-11-14 22:19 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
Because the counterpart to pci_bar_set_addr() setter is
pci_bar_addr() getter, these names become inconsistent.
Rename pci_bar_addr() to pci_bar_get_addr() also to make
the resulting names conform to each other.
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.c | 12 +++++++++++-
lib/pci.h | 3 ++-
x86/vmexit.c | 4 ++--
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/lib/pci.c b/lib/pci.c
index 3bf45fb..74936f3 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -32,7 +32,7 @@ static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
}
-phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
+phys_addr_t pci_bar_get_addr(pcidevaddr_t dev, int bar_num)
{
uint32_t bar = pci_bar_get(dev, bar_num);
uint32_t mask = pci_bar_mask(bar);
@@ -44,6 +44,16 @@ phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
return pci_translate_addr(dev, addr);
}
+void pci_bar_set_addr(pcidevaddr_t dev, int bar_num, phys_addr_t addr)
+{
+ int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
+
+ pci_config_writel(dev, off, (uint32_t)addr);
+
+ if (pci_bar_is64(dev, bar_num))
+ pci_config_writel(dev, off + 4, (uint32_t)(addr >> 32));
+}
+
/*
* To determine the amount of address space needed by a PCI device,
* one must save the original value of the BAR, write a value of
diff --git a/lib/pci.h b/lib/pci.h
index 8eec236..1c20308 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -29,7 +29,8 @@ extern pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
* It is expected the caller is aware of the device BAR layout and never
* tries to address the middle of a 64-bit register.
*/
-extern phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num);
+extern phys_addr_t pci_bar_get_addr(pcidevaddr_t dev, int bar_num);
+extern void pci_bar_set_addr(pcidevaddr_t dev, int bar_num, phys_addr_t addr);
extern phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
extern bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
extern bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
diff --git a/x86/vmexit.c b/x86/vmexit.c
index c2e1e49..2d99d5f 100644
--- a/x86/vmexit.c
+++ b/x86/vmexit.c
@@ -392,10 +392,10 @@ int main(int ac, char **av)
continue;
}
if (pci_bar_is_memory(pcidev, i)) {
- membar = pci_bar_addr(pcidev, i);
+ membar = pci_bar_get_addr(pcidev, i);
pci_test.memaddr = ioremap(membar, PAGE_SIZE);
} else {
- pci_test.iobar = pci_bar_addr(pcidev, i);
+ pci_test.iobar = pci_bar_get_addr(pcidev, i);
}
}
printf("pci-testdev at 0x%x membar %lx iobar %x\n",
--
2.7.4
^ permalink raw reply related
* [PATCH v3 05/25] pci: Factor out pci_bar_get()
From: Peter Xu @ 2016-11-14 22:19 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/lib/pci.c b/lib/pci.c
index b05ecfa..ce481bb 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -21,9 +21,14 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
return PCIDEVADDR_INVALID;
}
+static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
+{
+ return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+}
+
unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
{
- uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+ uint32_t bar = pci_bar_get(dev, bar_num);
if (bar & PCI_BASE_ADDRESS_SPACE_IO)
return bar & PCI_BASE_ADDRESS_IO_MASK;
@@ -33,12 +38,12 @@ unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
{
- uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+ uint32_t bar = pci_bar_get(dev, bar_num);
return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
}
bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
{
- return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+ return pci_bar_get(dev, bar_num);
}
--
2.7.4
^ permalink raw reply related
* [PATCH v3 09/25] pci: Add pci_print()
From: Peter Xu @ 2016-11-14 22:19 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Suggested-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
lib/pci.h | 3 +++
2 files changed, 92 insertions(+)
diff --git a/lib/pci.c b/lib/pci.c
index 42f47d9..e03c67c 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -126,3 +126,92 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64;
}
+
+static void pci_bar_print(pcidevaddr_t dev, int bar_num)
+{
+ phys_addr_t size, start, end;
+ uint32_t bar;
+
+ size = pci_bar_size(dev, bar_num);
+ if (!size)
+ return;
+
+ bar = pci_bar_get(dev, bar_num);
+ start = pci_bar_get_addr(dev, bar_num);
+ end = start + size - 1;
+
+ if (pci_bar_is64(dev, bar_num)) {
+ printf("BAR#%d,%d [%" PRIx64 "-%" PRIx64 " ",
+ bar_num, bar_num + 1, start, end);
+ } else {
+ printf("BAR#%d [%02x-%02x ",
+ bar_num, (uint32_t)start, (uint32_t)end);
+ }
+
+ if (bar & PCI_BASE_ADDRESS_SPACE_IO) {
+ printf("PIO");
+ } else {
+ printf("MEM");
+ switch (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
+ case PCI_BASE_ADDRESS_MEM_TYPE_32:
+ printf("32");
+ break;
+ case PCI_BASE_ADDRESS_MEM_TYPE_1M:
+ printf("1M");
+ break;
+ case PCI_BASE_ADDRESS_MEM_TYPE_64:
+ printf("64");
+ break;
+ default:
+ assert(0);
+ }
+ }
+
+ if (bar & PCI_BASE_ADDRESS_MEM_PREFETCH)
+ printf("/p");
+
+ printf("]");
+}
+
+static void pci_dev_print_id(pcidevaddr_t dev)
+{
+ printf("00.%02x.%1x %04x:%04x", dev / 8, dev % 8,
+ pci_config_readw(dev, PCI_VENDOR_ID),
+ pci_config_readw(dev, PCI_DEVICE_ID));
+}
+
+static void pci_dev_print(pcidevaddr_t dev)
+{
+ uint8_t header = pci_config_readb(dev, PCI_HEADER_TYPE);
+ uint8_t progif = pci_config_readb(dev, PCI_CLASS_PROG);
+ uint8_t subclass = pci_config_readb(dev, PCI_CLASS_DEVICE);
+ uint8_t class = pci_config_readb(dev, PCI_CLASS_DEVICE + 1);
+ int i;
+
+ pci_dev_print_id(dev);
+ printf(" type %02x progif %02x class %02x subclass %02x\n",
+ header, progif, class, subclass);
+
+ if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
+ return;
+
+ for (i = 0; i < 6; i++) {
+ if (pci_bar_size(dev, i)) {
+ printf("\t");
+ pci_bar_print(dev, i);
+ printf("\n");
+ }
+ if (pci_bar_is64(dev, i))
+ i++;
+ }
+}
+
+void pci_print(void)
+{
+ pcidevaddr_t dev;
+
+ for (dev = 0; dev < 256; ++dev) {
+ if (pci_dev_exists(dev))
+ pci_dev_print(dev);
+ }
+}
diff --git a/lib/pci.h b/lib/pci.h
index 1462aa2..fc0940a 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -15,6 +15,7 @@ enum {
PCIDEVADDR_INVALID = 0xffff,
};
+extern void pci_print(void);
extern bool pci_dev_exists(pcidevaddr_t dev);
extern pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
@@ -57,4 +58,6 @@ struct pci_test_dev_hdr {
uint8_t name[];
};
+#define PCI_HEADER_TYPE_MASK 0x7f
+
#endif /* PCI_H */
--
2.7.4
^ permalink raw reply related
* [PATCH v3 08/25] pci: Add pci_dev_exists()
From: Peter Xu @ 2016-11-14 22:19 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.c | 6 ++++++
lib/pci.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/lib/pci.c b/lib/pci.c
index 74936f3..42f47d9 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -7,6 +7,12 @@
#include "pci.h"
#include "asm/pci.h"
+bool pci_dev_exists(pcidevaddr_t dev)
+{
+ return (pci_config_readw(dev, PCI_VENDOR_ID) != 0xffff &&
+ pci_config_readw(dev, PCI_DEVICE_ID) != 0xffff);
+}
+
/* Scan bus look for a specific device. Only bus 0 scanned for now. */
pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
{
diff --git a/lib/pci.h b/lib/pci.h
index 1c20308..1462aa2 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -15,6 +15,7 @@ enum {
PCIDEVADDR_INVALID = 0xffff,
};
+extern bool pci_dev_exists(pcidevaddr_t dev);
extern pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
/*
--
2.7.4
^ permalink raw reply related
* [PATCH v3 06/25] pci: Rework pci_bar_addr()
From: Peter Xu @ 2016-11-14 22:19 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
This update makes pci_bar_addr() interface 64 bit BARs aware and
introduces a concept of PCI address translation.
An architecutre should implement pci_translate_addr() interface
in order to provide mapping between PCI bus address and CPU
physical address.
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++----
lib/pci.h | 17 ++++++++++++-
lib/x86/asm/pci.h | 6 +++++
3 files changed, 90 insertions(+), 6 deletions(-)
diff --git a/lib/pci.c b/lib/pci.c
index ce481bb..3bf45fb 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -21,19 +21,71 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
return PCIDEVADDR_INVALID;
}
+static uint32_t pci_bar_mask(uint32_t bar)
+{
+ return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
+ PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
+}
+
static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
{
return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
}
-unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
+phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
{
uint32_t bar = pci_bar_get(dev, bar_num);
+ uint32_t mask = pci_bar_mask(bar);
+ uint64_t addr = bar & mask;
- if (bar & PCI_BASE_ADDRESS_SPACE_IO)
- return bar & PCI_BASE_ADDRESS_IO_MASK;
- else
- return bar & PCI_BASE_ADDRESS_MEM_MASK;
+ if (pci_bar_is64(dev, bar_num))
+ addr |= (uint64_t)pci_bar_get(dev, bar_num + 1) << 32;
+
+ return pci_translate_addr(dev, addr);
+}
+
+/*
+ * To determine the amount of address space needed by a PCI device,
+ * one must save the original value of the BAR, write a value of
+ * all 1's to the register, and then read it back. The amount of
+ * memory can be then determined by masking the information bits,
+ * performing a bitwise NOT, and incrementing the value by 1.
+ *
+ * The following pci_bar_size_helper() and pci_bar_size() functions
+ * implement the algorithm.
+ */
+static uint32_t pci_bar_size_helper(pcidevaddr_t dev, int bar_num)
+{
+ int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
+ uint32_t bar, val;
+
+ bar = pci_config_readl(dev, off);
+ pci_config_writel(dev, off, ~0u);
+ val = pci_config_readl(dev, off);
+ pci_config_writel(dev, off, bar);
+
+ return val;
+}
+
+phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num)
+{
+ uint32_t bar, size;
+
+ size = pci_bar_size_helper(dev, bar_num);
+ if (!size)
+ return 0;
+
+ bar = pci_bar_get(dev, bar_num);
+ size &= pci_bar_mask(bar);
+
+ if (pci_bar_is64(dev, bar_num)) {
+ phys_addr_t size64 = pci_bar_size_helper(dev, bar_num + 1);
+ size64 = (size64 << 32) | size;
+
+ return ~size64 + 1;
+ } else {
+ return ~size + 1;
+ }
}
bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
@@ -47,3 +99,14 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
{
return pci_bar_get(dev, bar_num);
}
+
+bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
+{
+ uint32_t bar = pci_bar_get(dev, bar_num);
+
+ if (bar & PCI_BASE_ADDRESS_SPACE_IO)
+ return false;
+
+ return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64;
+}
diff --git a/lib/pci.h b/lib/pci.h
index 066fac7..8eec236 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -16,7 +16,22 @@ enum {
};
extern pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
-extern unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
+
+/*
+ * @bar_num in all BAR access functions below is the index of the 32-bit
+ * register starting from the PCI_BASE_ADDRESS_0 offset.
+ *
+ * In cases where the BAR size is 64-bit, a caller should still provide
+ * @bar_num in terms of 32-bit words. For example, if a device has a 64-bit
+ * BAR#0 and a 32-bit BAR#1, then caller should provide 2 to address BAR#1,
+ * not 1.
+ *
+ * It is expected the caller is aware of the device BAR layout and never
+ * tries to address the middle of a 64-bit register.
+ */
+extern phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num);
+extern phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
+extern bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
extern bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
extern bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h
index 4862ab5..c937e5c 100644
--- a/lib/x86/asm/pci.h
+++ b/lib/x86/asm/pci.h
@@ -50,4 +50,10 @@ static inline void pci_config_writel(pcidevaddr_t dev, uint8_t reg,
outl(val, 0xCFC);
}
+static inline
+phys_addr_t pci_translate_addr(pcidevaddr_t dev __unused, uint64_t addr)
+{
+ return addr;
+}
+
#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v3 04/25] pci: x86: Add remaining PCI configuration space accessors
From: Peter Xu @ 2016-11-14 22:19 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.c | 5 ++---
lib/x86/asm/pci.h | 38 ++++++++++++++++++++++++++++++++++++--
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/lib/pci.c b/lib/pci.c
index e0b4514..b05ecfa 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -13,9 +13,8 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
pcidevaddr_t dev;
for (dev = 0; dev < 256; ++dev) {
- uint32_t id = pci_config_readl(dev, 0);
-
- if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id)
+ if (pci_config_readw(dev, PCI_VENDOR_ID) == vendor_id &&
+ pci_config_readw(dev, PCI_DEVICE_ID) == device_id)
return dev;
}
diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h
index d00438f..4862ab5 100644
--- a/lib/x86/asm/pci.h
+++ b/lib/x86/asm/pci.h
@@ -9,11 +9,45 @@
#include "pci.h"
#include "x86/asm/io.h"
+#define PCI_CONF1_ADDRESS(dev, reg) ((0x1 << 31) | (dev << 8) | reg)
+
+static inline uint8_t pci_config_readb(pcidevaddr_t dev, uint8_t reg)
+{
+ outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
+ return inb(0xCFC);
+}
+
+static inline uint16_t pci_config_readw(pcidevaddr_t dev, uint8_t reg)
+{
+ outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
+ return inw(0xCFC);
+}
+
static inline uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg)
{
- uint32_t index = reg | (dev << 8) | (0x1 << 31);
- outl(index, 0xCF8);
+ outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
return inl(0xCFC);
}
+static inline void pci_config_writeb(pcidevaddr_t dev, uint8_t reg,
+ uint8_t val)
+{
+ outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
+ outb(val, 0xCFC);
+}
+
+static inline void pci_config_writew(pcidevaddr_t dev, uint8_t reg,
+ uint16_t val)
+{
+ outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
+ outw(val, 0xCFC);
+}
+
+static inline void pci_config_writel(pcidevaddr_t dev, uint8_t reg,
+ uint32_t val)
+{
+ outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
+ outl(val, 0xCFC);
+}
+
#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v3 03/25] pci: Add 'extern' to public function declarations
From: Peter Xu @ 2016-11-14 22:18 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/pci.h b/lib/pci.h
index 54fbf22..066fac7 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -15,10 +15,10 @@ enum {
PCIDEVADDR_INVALID = 0xffff,
};
-pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
-unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
-bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
-bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
+extern pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
+extern unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
+extern bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
+extern bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
/*
* pci-testdev is a driver for the pci-testdev qemu pci device. The
--
2.7.4
^ permalink raw reply related
* [PATCH v3 02/25] pci: x86: Rename pci_config_read() to pci_config_readl()
From: Peter Xu @ 2016-11-14 22:18 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.c | 8 ++++----
lib/x86/asm/pci.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/lib/pci.c b/lib/pci.c
index 43cd0ea..e0b4514 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -13,7 +13,7 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
pcidevaddr_t dev;
for (dev = 0; dev < 256; ++dev) {
- uint32_t id = pci_config_read(dev, 0);
+ uint32_t id = pci_config_readl(dev, 0);
if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id)
return dev;
@@ -24,7 +24,7 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
{
- uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+ uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
if (bar & PCI_BASE_ADDRESS_SPACE_IO)
return bar & PCI_BASE_ADDRESS_IO_MASK;
@@ -34,12 +34,12 @@ unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
{
- uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+ uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
}
bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
{
- return pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+ return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
}
diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h
index cddde41..d00438f 100644
--- a/lib/x86/asm/pci.h
+++ b/lib/x86/asm/pci.h
@@ -9,7 +9,7 @@
#include "pci.h"
#include "x86/asm/io.h"
-static inline uint32_t pci_config_read(pcidevaddr_t dev, uint8_t reg)
+static inline uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg)
{
uint32_t index = reg | (dev << 8) | (0x1 << 31);
outl(index, 0xCF8);
--
2.7.4
^ permalink raw reply related
* [PATCH v3 00/25] VT-d unit test
From: Peter Xu @ 2016-11-14 22:18 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
This is v3 of vt-d unit test series.
Patch "libcflat: add IS_ALIGNED() macro, and page sizes" is picked up
by Drew in the ARM GIC framework series, so please feel free to drop
it when needed.
Online repo:
https://github.com/xzpeter/kvm-unit-tests.git iommu-ut-v3
Please review. Thanks,
v3:
- is_power_of_2(): remove outer "()" [Drew]
- fix indent for vtd_root_table() [Drew]
- pci_find_dev(): keep {} to avoid touching more codes [Drew]
- pci_scan_bars(): check whether bar is 64bits [Drew]
- pci_enable_defaults(): make it return nothing [Drew]
- fix strnang blanks in lib/x86/intel-iommu.h [Drew]
- pci_setup_msi(): fix correct assert() inside [Drew]
- squash patches: 03+17 08+09 10+11 12+14 [Drew]
- remove all "()" for raw defines (numbers) in macros [Drew]
v2:
- move cpu_relax patch to the beginning, and use them in all places
[Drew]
- replace all corresponding 256 into PCI_DEVFN_MAX, as well for
PCI_BAR_NUM [Drew]
- adding is_power_of_2() to replace ONE_BIT_ONLY() [Drew]
- add SZ_64K macro [Drew]
- declare pci_config_write[wb] in lib/asm-generic/pci-host-bridge.h [Alex]
- edu_reg_read/write() add "l" in func name [Drew]
- drop pci_set_master(), instead, provide pci_cmd_set_clr() [Drew]
- change return code into bool (always) for functions that apply
[Drew]
- keep old pci_find_dev() interface [Drew/Alex]
- use __raw_{read|write}*() for both vt-d and edu register read/writes
[Alex]
- remove pci_ prefix for all pci_dev fields [Drew]
- replace 0xff in cap_handlers[0xff] into (PCI_CAP_ID_MAX + 1) [Drew]
- make x86/unittest.cfg simpler by using q35 directly with eim=off
[Drew]
RFC -> v1:
- when init edu device fail, report_skip() rather than return error
[Radim]
- use asserts rather than "static bool inited" to avoid multiple init
of components (affects patch 1/2) [Drew]
- moving the first two patches out of the series [Drew]
- int vtd_init(), do not setup_idt() since smp_init() did it [Drew]
- when edu do not have MSI enabled, skip interrupt test [Radim]
- rename vtd_reg_*() into vtd_{read|write}[lq](), and move them to
header file [Drew]
- use PAGE_MASK when able [Drew]
- use "&" instead of "|" in intel-iommu init test (three places)
[Drew]
- use "vtd_init()" in unit test [Drew]
- mention that where intel-iommu.h comes from [Drew]
- re-written vtd_gcmd_or(), make it also work on even hardware [Drew]
- remove most of the oneline wrapper for VT-d registers, instead, use
vtd_{read|write}* with register names [Drew]
- remove useless BDF helpers [Drew]
- move edu device macros into header file [Drew]
- make edu_check_alive static inline [Drew]
- remove all useless wrappers in pci-edu.c [Drew]
- remove pci_dma_dir_t and all its users, instead, use "bool
from_device" [Drew]
- not use typedef for structs, to follow Linux/kvm-unit-tests coding
style [Drew]
- let pci_dev_init() clean and simple, then provide
pci_enable_defaults() for more complicated things [Drew]
- add one more patch to add intel-iommu test into x86/unittest [Radim]
- use 0x60 intr request instead of factorial to trigger edu device
interrupt [Drew]
- ...and some other changes I just forgot to note down...
Currently only a very small test scope is covered:
* VT-d init
* DMAR: 4 bytes copy
* IR: MSI
However this series could be a base point to add more test cases for
VT-d. The problem is, there are many IOMMU error conditions which are
very hard to be triggered in a real guest (IOMMU has merely no
interface for guest user, and it's totally running in the background).
This piece of work can be a start point if we want to do more
complicated things and play around with Intel IOMMU devices (also for
IOMMU regression tests).
Please review. Thanks,
=================
To run the test:
./x86/run ./x86/intel-iommu.flat \
-M q35,kernel-irqchip=split -global ioapic.version=0x20 \
-device intel-iommu,intremap=on -device edu
Sample output:
pxdev:kvm-unit-tests [new-iommu-ut]# ./iommu_run.sh
/root/git/qemu/bin/x86_64-softmmu/qemu-system-x86_64 -enable-kvm -device pc-testdev -device isa-debug-exit,iobase=0xf4,iosize=0x4 -vnc none -serial stdio
+-device pci-testdev -kernel ./x86/intel-iommu.flat -M q35,kernel-irqchip=split -global ioapic.version=0x20 -device intel-iommu,intremap=on -device edu
enabling apic
paging enabled
cr0 = 80010011
cr3 = 7fff000
cr4 = 20
VT-d version: 0x10
cap: 0x0012008c22260206
ecap: 0x0000000000f00f1a
PASS: init status check
PASS: fault status check
PASS: QI enablement
DMAR table address: 0x0000000007ff9000
PASS: DMAR table setup
IR table address: 0x0000000007ff8000
PASS: IR table setup
PASS: DMAR enablement
PASS: IR enablement
PASS: DMAR support 39 bits address width
PASS: DMAR support huge pages
PCI: init dev 0x0020 BAR 0 [MEM] addr 0xfea00000
PCI detected cap 0x5
Detected MSI for device 0x20 offset 0x40
allocated vt-d root entry for PCI bus 0
allocated vt-d context entry for devfn 0x20
map 4K page IOVA 0x0 to 0x7ff7000 (sid=0x0020)
edu device DMA start TO addr 0x0 size 0x4 off 0x0
edu device DMA start FROM addr 0x4 size 0x4 off 0x0
PASS: DMAR 4B memcpy test
INTR: setup IRTE index 0
MSI: dev 0x20 init 64bit address: addr=0xfee00010, data=0x0
PASS: EDU factorial INTR test
Alexander Gordeev (12):
pci: Fix coding style in generic PCI files
pci: x86: Rename pci_config_read() to pci_config_readl()
pci: Add 'extern' to public function declarations
pci: x86: Add remaining PCI configuration space accessors
pci: Factor out pci_bar_get()
pci: Rework pci_bar_addr()
pci: Add pci_bar_set_addr()
pci: Add pci_dev_exists()
pci: Add pci_print()
pci: Add generic ECAM host support
pci: Add pci-testdev PCI bus test device
arm/arm64: pci: Add pci-testdev PCI device operation test
Peter Xu (13):
x86/asm: add cpu_relax()
libcflat: introduce is_power_of_2()
x86: intel-iommu: add vt-d init test
libcflat: add IS_ALIGNED() macro, and page sizes
libcflat: moving MIN/MAX here
vm/page: provide PGDIR_OFFSET() macro
pci: introduce struct pci_dev
pci: provide pci_scan_bars()
pci: provide pci_enable_defaults()
pci: edu: introduce pci-edu helpers
x86: intel-iommu: add dmar test
pci: add msi support for 32/64bit address
x86: intel-iommu: add IR MSI test
arm/Makefile.common | 6 +-
arm/pci-test.c | 27 ++++
arm/run | 7 +-
arm/unittests.cfg | 4 +
lib/alloc.c | 3 -
lib/arm/asm/pci.h | 1 +
lib/arm64/asm/pci.h | 1 +
lib/asm-generic/pci-host-bridge.h | 28 ++++
lib/libcflat.h | 14 ++
lib/pci-edu.c | 73 +++++++++
lib/pci-edu.h | 83 ++++++++++
lib/pci-host-generic.c | 321 +++++++++++++++++++++++++++++++++++++
lib/pci-host-generic.h | 46 ++++++
lib/pci-testdev.c | 194 ++++++++++++++++++++++
lib/pci.c | 327 +++++++++++++++++++++++++++++++++++---
lib/pci.h | 66 +++++++-
lib/x86/asm/barrier.h | 11 ++
lib/x86/asm/page.h | 3 +
lib/x86/asm/pci.h | 46 +++++-
lib/x86/intel-iommu.c | 313 ++++++++++++++++++++++++++++++++++++
lib/x86/intel-iommu.h | 142 +++++++++++++++++
lib/x86/vm.c | 4 +-
x86/Makefile.common | 1 +
x86/Makefile.x86_64 | 2 +
x86/intel-iommu.c | 120 ++++++++++++++
x86/unittests.cfg | 7 +
x86/vmexit.c | 27 ++--
27 files changed, 1826 insertions(+), 51 deletions(-)
create mode 100644 arm/pci-test.c
create mode 100644 lib/arm/asm/pci.h
create mode 100644 lib/arm64/asm/pci.h
create mode 100644 lib/asm-generic/pci-host-bridge.h
create mode 100644 lib/pci-edu.c
create mode 100644 lib/pci-edu.h
create mode 100644 lib/pci-host-generic.c
create mode 100644 lib/pci-host-generic.h
create mode 100644 lib/pci-testdev.c
create mode 100644 lib/x86/intel-iommu.c
create mode 100644 lib/x86/intel-iommu.h
create mode 100644 x86/intel-iommu.c
--
2.7.4
^ permalink raw reply
* [PATCH v3 01/25] pci: Fix coding style in generic PCI files
From: Peter Xu @ 2016-11-14 22:18 UTC (permalink / raw)
To: kvm; +Cc: drjones, agordeev, jan.kiszka, rkrcmar, pbonzini, peterx
In-Reply-To: <1479161961-20304-1-git-send-email-peterx@redhat.com>
From: Alexander Gordeev <agordeev@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
lib/pci.c | 38 ++++++++++++++++++++------------------
lib/pci.h | 3 ++-
2 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/lib/pci.c b/lib/pci.c
index 0058d70..43cd0ea 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -10,34 +10,36 @@
/* Scan bus look for a specific device. Only bus 0 scanned for now. */
pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
{
- unsigned dev;
- for (dev = 0; dev < 256; ++dev) {
- uint32_t id = pci_config_read(dev, 0);
- if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id) {
- return dev;
- }
- }
- return PCIDEVADDR_INVALID;
+ pcidevaddr_t dev;
+
+ for (dev = 0; dev < 256; ++dev) {
+ uint32_t id = pci_config_read(dev, 0);
+
+ if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id)
+ return dev;
+ }
+
+ return PCIDEVADDR_INVALID;
}
unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
{
- uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
- if (bar & PCI_BASE_ADDRESS_SPACE_IO) {
- return bar & PCI_BASE_ADDRESS_IO_MASK;
- } else {
- return bar & PCI_BASE_ADDRESS_MEM_MASK;
- }
+ uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+
+ if (bar & PCI_BASE_ADDRESS_SPACE_IO)
+ return bar & PCI_BASE_ADDRESS_IO_MASK;
+ else
+ return bar & PCI_BASE_ADDRESS_MEM_MASK;
}
bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
{
- uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
- return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
+ uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+
+ return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
}
bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
{
- uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
- return bar;
+ return pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
}
diff --git a/lib/pci.h b/lib/pci.h
index 9160cfb..54fbf22 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -12,8 +12,9 @@
typedef uint16_t pcidevaddr_t;
enum {
- PCIDEVADDR_INVALID = 0xffff,
+ PCIDEVADDR_INVALID = 0xffff,
};
+
pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v6 2/9] tpm: replace symbolic permission with octal for securityfs files
From: Jarkko Sakkinen @ 2016-11-14 22:18 UTC (permalink / raw)
To: Nayna Jain
Cc: tpmdd-devel, peterhuewe, tpmdd, jgunthorpe, linux-kernel,
linux-security-module
In-Reply-To: <1479117656-12403-3-git-send-email-nayna@linux.vnet.ibm.com>
On Mon, Nov 14, 2016 at 05:00:49AM -0500, Nayna Jain wrote:
> checkpatch.pl flags warning for symbolic permissions and suggests
> to replace with octal value.
>
> This patch changes securityfs pseudo files permission
> to octal values in tpm_bios_log_setup().
>
> Signed-off-by: Nayna Jain <nayna@linux.vnet.ibm.com>
Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
/Jarkko
> ---
> drivers/char/tpm/tpm_eventlog.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm_eventlog.c b/drivers/char/tpm/tpm_eventlog.c
> index 42b49c4..9467e31 100644
> --- a/drivers/char/tpm/tpm_eventlog.c
> +++ b/drivers/char/tpm/tpm_eventlog.c
> @@ -378,7 +378,7 @@ struct dentry **tpm_bios_log_setup(const char *name)
>
> bin_file =
> securityfs_create_file("binary_bios_measurements",
> - S_IRUSR | S_IRGRP, tpm_dir,
> + 0440, tpm_dir,
> (void *)&tpm_binary_b_measurements_seqops,
> &tpm_bios_measurements_ops);
> if (is_bad(bin_file))
> @@ -386,7 +386,7 @@ struct dentry **tpm_bios_log_setup(const char *name)
>
> ascii_file =
> securityfs_create_file("ascii_bios_measurements",
> - S_IRUSR | S_IRGRP, tpm_dir,
> + 0440, tpm_dir,
> (void *)&tpm_ascii_b_measurements_seqops,
> &tpm_bios_measurements_ops);
> if (is_bad(ascii_file))
> --
> 2.5.0
>
^ permalink raw reply
* Re: [PATCH v6 2/9] tpm: replace symbolic permission with octal for securityfs files
From: Jarkko Sakkinen @ 2016-11-14 22:18 UTC (permalink / raw)
To: Nayna Jain
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-security-module-u79uwXL29TY76Z2rM5mHXA,
tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
In-Reply-To: <1479117656-12403-3-git-send-email-nayna-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
On Mon, Nov 14, 2016 at 05:00:49AM -0500, Nayna Jain wrote:
> checkpatch.pl flags warning for symbolic permissions and suggests
> to replace with octal value.
>
> This patch changes securityfs pseudo files permission
> to octal values in tpm_bios_log_setup().
>
> Signed-off-by: Nayna Jain <nayna-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
/Jarkko
> ---
> drivers/char/tpm/tpm_eventlog.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm_eventlog.c b/drivers/char/tpm/tpm_eventlog.c
> index 42b49c4..9467e31 100644
> --- a/drivers/char/tpm/tpm_eventlog.c
> +++ b/drivers/char/tpm/tpm_eventlog.c
> @@ -378,7 +378,7 @@ struct dentry **tpm_bios_log_setup(const char *name)
>
> bin_file =
> securityfs_create_file("binary_bios_measurements",
> - S_IRUSR | S_IRGRP, tpm_dir,
> + 0440, tpm_dir,
> (void *)&tpm_binary_b_measurements_seqops,
> &tpm_bios_measurements_ops);
> if (is_bad(bin_file))
> @@ -386,7 +386,7 @@ struct dentry **tpm_bios_log_setup(const char *name)
>
> ascii_file =
> securityfs_create_file("ascii_bios_measurements",
> - S_IRUSR | S_IRGRP, tpm_dir,
> + 0440, tpm_dir,
> (void *)&tpm_ascii_b_measurements_seqops,
> &tpm_bios_measurements_ops);
> if (is_bad(ascii_file))
> --
> 2.5.0
>
------------------------------------------------------------------------------
^ permalink raw reply
* [PATCH V2] devshell: list commands when throwing NoSupportedTerminals
From: Stephano Cetola @ 2016-11-14 22:16 UTC (permalink / raw)
To: openembedded-core
In-Reply-To: <20161114221616.70170-1-stephano.cetola@linux.intel.com>
When attempting to run devshell, if no terminal is available, the
error being thrown was not very specific. This adds a list of
commands that failed, informing the user of what they can install to
fix the error.
Signed-off-by: Stephano Cetola <stephano.cetola@linux.intel.com>
---
meta/classes/terminal.bbclass | 8 ++++++--
meta/lib/oe/terminal.py | 13 +++++++++++--
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/meta/classes/terminal.bbclass b/meta/classes/terminal.bbclass
index a94f755..cd8d124 100644
--- a/meta/classes/terminal.bbclass
+++ b/meta/classes/terminal.bbclass
@@ -88,8 +88,12 @@ def oe_terminal(command, title, d):
try:
oe.terminal.spawn_preferred(command, title, None, d)
- except oe.terminal.NoSupportedTerminals:
- bb.fatal('No valid terminal found, unable to open devshell')
+ except oe.terminal.NoSupportedTerminals as nosup:
+ nosup.terms.remove("false")
+ cmds = '\n\t'.join(nosup.terms).replace("{command}",
+ "do_terminal").replace("{title}", title)
+ bb.fatal('No valid terminal found, unable to open devshell.\n' +
+ 'Tried the following commands:\n\t%s' % cmds)
except oe.terminal.ExecutionError as exc:
bb.fatal('Unable to spawn terminal %s: %s' % (terminal, exc))
diff --git a/meta/lib/oe/terminal.py b/meta/lib/oe/terminal.py
index 7446c44..38e66ce 100644
--- a/meta/lib/oe/terminal.py
+++ b/meta/lib/oe/terminal.py
@@ -11,7 +11,8 @@ class UnsupportedTerminal(Exception):
pass
class NoSupportedTerminals(Exception):
- pass
+ def __init__(self, terms):
+ self.terms = terms
class Registry(oe.classutils.ClassRegistry):
@@ -209,6 +210,14 @@ class Custom(Terminal):
def prioritized():
return Registry.prioritized()
+def get_cmd_list():
+ terms = Registry.prioritized()
+ cmds = []
+ for term in terms:
+ if term.command:
+ cmds.append(term.command)
+ return cmds
+
def spawn_preferred(sh_cmd, title=None, env=None, d=None):
"""Spawn the first supported terminal, by priority"""
for terminal in prioritized():
@@ -218,7 +227,7 @@ def spawn_preferred(sh_cmd, title=None, env=None, d=None):
except UnsupportedTerminal:
continue
else:
- raise NoSupportedTerminals()
+ raise NoSupportedTerminals(get_cmd_list())
def spawn(name, sh_cmd, title=None, env=None, d=None):
"""Spawn the specified terminal, by name"""
--
2.10.2
^ permalink raw reply related
* [PATCH V2] devshell: list commands when throwing NoSupportedTerminals
From: Stephano Cetola @ 2016-11-14 22:16 UTC (permalink / raw)
To: openembedded-core
Changes since V1:
Remove the placeholder "false" for custom terminal rather than
changing it to None. That change would break the custom terminal.
Stephano Cetola (1):
devshell: list commands when throwing NoSupportedTerminals
meta/classes/terminal.bbclass | 8 ++++++--
meta/lib/oe/terminal.py | 13 +++++++++++--
2 files changed, 17 insertions(+), 4 deletions(-)
--
2.10.2
^ permalink raw reply
* Re: [PATCH v2 2/2] of: changesets: Introduce changeset helper methods
From: Rob Herring @ 2016-11-14 22:16 UTC (permalink / raw)
To: Frank Rowand
Cc: Hans de Goede, Pantelis Antoniou,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <582A060D.50800-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Nov 14, 2016 at 12:44 PM, Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On 11/14/16 03:04, Hans de Goede wrote:
>> Hi,
>>
>> On 14-11-16 08:34, Frank Rowand wrote:
>>> Hi Hans, Pantelis,
>>>
>>> On 11/12/16 18:15, Frank Rowand wrote:
>>>> On 11/04/16 07:42, Hans de Goede wrote:
>>>>> From: Pantelis Antoniou <pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>
>>>>>
>>>>> Changesets are very powerful, but the lack of a helper API
>>>>> makes using them cumbersome. Introduce a simple copy based
>>>>> API that makes things considerably easier.
>>>>>
>>>>> To wit, adding a property using the raw API.
>>>>>
>>>>> struct property *prop;
>>>>> prop = kzalloc(sizeof(*prop)), GFP_KERNEL);
>>>>> prop->name = kstrdup("compatible");
>>>>> prop->value = kstrdup("foo,bar");
>>>>> prop->length = strlen(prop->value) + 1;
>>>>> of_changeset_add_property(ocs, np, prop);
>>>>>
>>>>> while using the helper API
>>>>>
>>>>> of_changeset_add_property_string(ocs, np, "compatible",
>>>>> "foo,bar");
>>>>>
>>>>> Signed-off-by: Pantelis Antoniou <pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>
>>>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>>> ---
>>>>> Changes in v2 (hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org):
>>>>> -Address review comments from:
>>>>> https://www.spinics.net/lists/kernel/msg2252845.html
>>>>
>>>> That points to the May 9 version 1 patches from Pantelis (as expected),
>>>> but containing 4, not 2, patches. Patch 1/4 was applied. Patch 4/4
>>>> seems to have disappeared?
>>>>
>>>> Pantelis then sent a version 2 set of the patches on May 16.
>>>>
>>>> Your version is a modification of the May 9 patches (as would be expected
>>>> of a version 2). It is confusing to have two different version 2 patch
>>>> sets. I don't have any brilliant ideas on how this patch set could have
>>>> been named differently to avoid that confusion.
>>>>
>>>> The point of this little side-track is simply to note the existence of two
>>>> different version 2 series so I won't be confused when I revisit this
>>>> thread in the future.
>>>>
>>>>> -Simplify (and fix) __of_changeset_add_update_property_copy OOM handling
>>>>> -Remove (by manual inlining) these 2 static helpers:
>>>>> __of_changeset_add_update_property_u32
>>>>> __of_changeset_add_update_property_bool
>>>>> -Remove the following exported helper method:
>>>>> of_changeset_node_move_to
>>>>
>>>> Not all comments were addressed.
>>>>
>>>> There are some other changes made that are not noted in the changelog.
>>>>
>>>> I am still reading through the patches. I will reply again either with
>>>> a reviewed-by or specific comments when I finish.
>>>
>>> Replying here for the entire patchset (there was no patch 0 to reply to).
>>>
>>> After reading through the patches, my reply is meta instead of specific
>>> comments about the code.
>>>
>>> There are very few users of change sets in tree. I do not see the need to
>>> add these helpers until such users are likely to appear.
>>>
>>> I would expect change sets to be _mostly_ used internally by the device tree
>>> overlay framework, not directly by drivers. If change sets are an attractive
>>> technology for drivers, I want to approach that usage very carefully to avoid
>>> inappropriate use, which could be very difficult to reign in after the fact.
>>>
>>> Even if helpers should be added, this seems to be an overly complex approach.
>>> If the need for these helpers becomes apparent I can provide review comments
>>> with the specifics about how it appears to be overly complex.
>>>
>>> Can you please provide some more insights into the needs driving the desire
>>> to have change set helpers and the expected use cases of them? Please put
>>> your architect's hat on when replying to this question.
>>
>> My use case for this is discussed in this thread:
>> https://www.spinics.net/lists/arm-kernel/msg536111.html
>>
>> With the dt-bindings for the hardware-manager I want to add here:
>> https://www.spinics.net/lists/arm-kernel/msg536109.html
>>
>> Note that there is a lot of discussion in this thread whether or
>> not this belongs in the kernel. I strongly believe though that
>> some functionality like this will be needed in the kernel for
>> ARM+dt devices going forward, just like there is plenty of x86
>> code which adjusts itself to specific hardware, because whether
>> we like it or not hardware (revisions) will always have quirks.
>
> Thanks! That context should have been provided with the patches.
>
> The use case discussion is important and I am paying a lot of
> attention to that discussion and many other discussions about
> dynamic device trees. I don't think it makes sense to apply the
> change set helper patches yet, given the unsettled state of the
> various dynamic device tree discussions.
These helpers are useful and easier to use than the existing API
independent of any issues to sort out with how we use overlays. So I
plan to take them whether there's a user right away or not.
Rob
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^ permalink raw reply
* [PATCH v1 3/3] kvm: svm: Use the hardware provided GPA instead of page walk
From: Brijesh Singh @ 2016-11-14 22:16 UTC (permalink / raw)
To: kvm
Cc: Thomas.Lendacky, brijesh.singh, rkrcmar, joro, x86, linux-kernel,
mingo, hpa, pbonzini, tglx, bp
In-Reply-To: <147916172660.16347.15695649975899246333.stgit@brijesh-build-machine>
From: Tom Lendacky <thomas.lendacky@amd.com>
When a guest causes a NPF which requires emulation, KVM sometimes walks
the guest page tables to translate the GVA to a GPA. This is unnecessary
most of the time on AMD hardware since the hardware provides the GPA in
EXITINFO2.
The only exception cases involve string operations involving rep or
operations that use two memory locations. With rep, the GPA will only be
the value of the initial NPF and with dual memory locations we won't know
which memory address was translated into EXITINFO2.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
arch/x86/include/asm/kvm_emulate.h | 3 +++
arch/x86/include/asm/kvm_host.h | 3 +++
arch/x86/kvm/svm.c | 9 ++++++++-
arch/x86/kvm/x86.c | 17 ++++++++++++++++-
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index e9cd7be..2d1ac09 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -344,6 +344,9 @@ struct x86_emulate_ctxt {
struct read_cache mem_read;
};
+/* String operation identifier (matches the definition in emulate.c) */
+#define CTXT_STRING_OP (1 << 13)
+
/* Repeat String Operation Prefix */
#define REPE_PREFIX 0xf3
#define REPNE_PREFIX 0xf2
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 77cb3f9..fd5b1c8 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -668,6 +668,9 @@ struct kvm_vcpu_arch {
int pending_ioapic_eoi;
int pending_external_vector;
+
+ /* GPA available (AMD only) */
+ bool gpa_available;
};
struct kvm_lpage_info {
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 5e64e656..b442c5a 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -275,6 +275,9 @@ static int avic;
module_param(avic, int, S_IRUGO);
#endif
+/* EXITINFO2 contains valid GPA */
+static bool gpa_avail = true;
+
/* AVIC VM ID bit masks and lock */
static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
static DEFINE_SPINLOCK(avic_vm_id_lock);
@@ -1055,8 +1058,10 @@ static __init int svm_hardware_setup(void)
goto err;
}
- if (!boot_cpu_has(X86_FEATURE_NPT))
+ if (!boot_cpu_has(X86_FEATURE_NPT)) {
npt_enabled = false;
+ gpa_avail = false;
+ }
if (npt_enabled && !npt) {
printk(KERN_INFO "kvm: Nested Paging disabled\n");
@@ -4192,6 +4197,8 @@ static int handle_exit(struct kvm_vcpu *vcpu)
vcpu->arch.cr0 = svm->vmcb->save.cr0;
if (npt_enabled)
vcpu->arch.cr3 = svm->vmcb->save.cr3;
+ if (gpa_avail)
+ vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
if (unlikely(svm->nested.exit_required)) {
nested_svm_vmexit(svm);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index d02aeff..c290794 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -4420,7 +4420,19 @@ static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
return 1;
}
- *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
+ /*
+ * If the exit was due to a NPF we may already have a GPA.
+ * If the GPA is present, use it to avoid the GVA to GPA table
+ * walk. Note, this cannot be used on string operations since
+ * string operation using rep will only have the initial GPA
+ * from when the NPF occurred.
+ */
+ if (vcpu->arch.gpa_available &&
+ !(vcpu->arch.emulate_ctxt.d & CTXT_STRING_OP))
+ *gpa = exception->address;
+ else
+ *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access,
+ exception);
if (*gpa == UNMAPPED_GVA)
return -1;
@@ -5542,6 +5554,9 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu,
}
restart:
+ /* Save the faulting GPA (cr2) in the address field */
+ ctxt->exception.address = cr2;
+
r = x86_emulate_insn(ctxt);
if (r == EMULATION_INTERCEPTED)
^ permalink raw reply related
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