* [PATCH v6 22/25] usb: chipidea: Drop lock across event_notify during gadget stop
From: Peter Chen @ 2017-01-03 6:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161228225711.698-23-stephen.boyd@linaro.org>
On Wed, Dec 28, 2016 at 02:57:08PM -0800, Stephen Boyd wrote:
> The CI_HDRC_CONTROLLER_STOPPED_EVENT may want to call sleeping
> APIs similar to how _gadget_stop_activity() may. Let's drop the
> lock across the event so that glue drivers can make sleeping
> calls.
>
> Cc: Peter Chen <peter.chen@nxp.com>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> ---
> drivers/usb/chipidea/udc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index 0db56fb7e9e9..0d532a724d48 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -1793,10 +1793,10 @@ static int ci_udc_stop(struct usb_gadget *gadget)
>
> if (ci->vbus_active) {
> hw_device_state(ci, 0);
> + spin_unlock_irqrestore(&ci->lock, flags);
> if (ci->platdata->notify_event)
> ci->platdata->notify_event(ci,
> CI_HDRC_CONTROLLER_STOPPED_EVENT);
> - spin_unlock_irqrestore(&ci->lock, flags);
> _gadget_stop_activity(&ci->gadget);
> spin_lock_irqsave(&ci->lock, flags);
> pm_runtime_put(&ci->gadget.dev);
> --
Acked-by: Peter Chen <peter.chen@nxp.com>
--
Best Regards,
Peter Chen
^ permalink raw reply
* Re: [PATCH v6 22/25] usb: chipidea: Drop lock across event_notify during gadget stop
From: Peter Chen @ 2017-01-03 6:46 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-usb, linux-arm-kernel, linux-kernel, linux-arm-msm,
Andy Gross, Bjorn Andersson, Neil Armstrong, Arnd Bergmann,
Felipe Balbi, Peter Chen, Greg Kroah-Hartman
In-Reply-To: <20161228225711.698-23-stephen.boyd@linaro.org>
On Wed, Dec 28, 2016 at 02:57:08PM -0800, Stephen Boyd wrote:
> The CI_HDRC_CONTROLLER_STOPPED_EVENT may want to call sleeping
> APIs similar to how _gadget_stop_activity() may. Let's drop the
> lock across the event so that glue drivers can make sleeping
> calls.
>
> Cc: Peter Chen <peter.chen@nxp.com>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> ---
> drivers/usb/chipidea/udc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index 0db56fb7e9e9..0d532a724d48 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -1793,10 +1793,10 @@ static int ci_udc_stop(struct usb_gadget *gadget)
>
> if (ci->vbus_active) {
> hw_device_state(ci, 0);
> + spin_unlock_irqrestore(&ci->lock, flags);
> if (ci->platdata->notify_event)
> ci->platdata->notify_event(ci,
> CI_HDRC_CONTROLLER_STOPPED_EVENT);
> - spin_unlock_irqrestore(&ci->lock, flags);
> _gadget_stop_activity(&ci->gadget);
> spin_lock_irqsave(&ci->lock, flags);
> pm_runtime_put(&ci->gadget.dev);
> --
Acked-by: Peter Chen <peter.chen@nxp.com>
--
Best Regards,
Peter Chen
^ permalink raw reply
* [PATCH v2 1/1] usb: xhci: clear EINT bit in status correctly
From: Lu Baolu @ 2017-01-03 6:45 UTC (permalink / raw)
To: Mathias Nyman; +Cc: linux-usb, linux-kernel, Lu Baolu, stable, Felipe Balbi
EINT(Event Interrupt) is a write-1-to-clear type of bit in xhci
status register. It should be cleared by writing a 1. Writing 0
to this bit has no effect.
Xhci driver tries to clear this bit by writing 0 to it. This is
not the right way to go. This patch corrects this by reading the
register first, then clearing all RO/RW1C/RsvZ bits and setting
the clearing bit, and writing back the new value at last.
Xhci spec requires that software that uses EINT shall clear it
prior to clearing any IP flags in section 5.4.2. This is the
reason why this patch is CC'ed stable as well.
Cc: <stable@vger.kernel.org> # v3.14+
Cc: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
Change log:
v1->v2:
- Fixed a warning reported by 0-day kbuild robot.
drivers/usb/host/xhci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 1cd5641..bb08c6b 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -721,7 +721,7 @@ void xhci_stop(struct usb_hcd *hcd)
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
"// Disabling event ring interrupts");
temp = readl(&xhci->op_regs->status);
- writel(temp & ~STS_EINT, &xhci->op_regs->status);
+ writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
temp = readl(&xhci->ir_set->irq_pending);
writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
xhci_print_ir_set(xhci, 0);
@@ -1054,7 +1054,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
xhci_dbg(xhci, "// Disabling event ring interrupts\n");
temp = readl(&xhci->op_regs->status);
- writel(temp & ~STS_EINT, &xhci->op_regs->status);
+ writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
temp = readl(&xhci->ir_set->irq_pending);
writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
xhci_print_ir_set(xhci, 0);
--
2.1.4
^ permalink raw reply related
* Re: [PATCH v6 8/9] dt-bindings: mux-adg792a: document devicetree bindings for ADG792A/G mux
From: Peter Rosin @ 2017-01-03 6:44 UTC (permalink / raw)
To: Jonathan Cameron, Jonathan Cameron, linux-kernel
Cc: Wolfram Sang, Rob Herring, Mark Rutland, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jonathan Corbet,
Arnd Bergmann, Greg Kroah-Hartman, linux-i2c, devicetree,
linux-iio, linux-doc
In-Reply-To: <90A8A4B3-670B-4409-B7AB-47BF4B2ABDDA@jic23.retrosnub.co.uk>
On 2017-01-02 22:13, Jonathan Cameron wrote:
>
>
> On 2 January 2017 20:47:58 GMT+00:00, Peter Rosin <peda@axentia.se> wrote:
>> On 2017-01-02 19:05, Jonathan Cameron wrote:
>>> On 02/01/17 16:01, Peter Rosin wrote:
>>>> On 2017-01-01 12:00, Jonathan Cameron wrote:
>>>>> On 30/11/16 08:17, Peter Rosin wrote:
>>>>>> Analog Devices ADG792A/G is a triple 4:1 mux.
>>>>>>
>>>>>> Signed-off-by: Peter Rosin <peda@axentia.se>
>>>>> Few comments inline. Worth adding anything about the gpio (output pins) to
>>>>> the binding at this stage as well? Would certainly be nice to support
>>>>> them.
>>>>
>>>> I'll add optional properties "gpio-controller;" and "#gpio-cells = <2>;"
>>>> with the usual interpretation in v7 (but no implementation...) Is that
>>>> enough?
>>>>
>>>>> Jonathan
>>>>>> ---
>>>>>> .../devicetree/bindings/misc/mux-adg792a.txt | 64 ++++++++++++++++++++++
>>>>>> 1 file changed, 64 insertions(+)
>>>>>> create mode 100644 Documentation/devicetree/bindings/misc/mux-adg792a.txt
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/misc/mux-adg792a.txt b/Documentation/devicetree/bindings/misc/mux-adg792a.txt
>>>>>> new file mode 100644
>>>>>> index 000000000000..4677f9ab1c55
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/misc/mux-adg792a.txt
>>>>>> @@ -0,0 +1,64 @@
>>>>>> +Bindings for Analog Devices ADG792A/G Triple 4:1 Multiplexers
>>>>>> +
>>>>>> +Required properties:
>>>>>> +- compatible : "adi,adg792a" or "adi,adg792g"
>>>>>> +- #mux-control-cells : <0> if parallel, or <1> if not.
>>>>>> +* Standard mux-controller bindings as decribed in mux-controller.txt
>>>>>> +
>>>>>> +Optional properties:
>>>>>> +- adi,parallel : if present, the three muxes are bound together with a single
>>>>>> + mux controller, controlling all three muxes in parallel.
>>>>>> +- adi,idle-state : if present, array of states the three mux controllers will
>>>>>> + have when idle (or, if parallel, a single idle-state).
>>>>> Hmm. These are actually a policy decision. As only one policy will make
>>>>> sense for a given set of hardware probably fine to have it in here I guess.
>>>>> Might be worth adding a note to say this though.
>>>>
>>>> I don't really know what you want me to add, do you have a suggestion for the
>>>> wording?
>>>>
>>>>>> +
>>>>>> +Mux controller states 0 through 3 correspond to signals A through D in the
>>>>>> +datasheet. Mux controller states 4 and 5 are only available as possible idle
>>>>>> +states. State 4 represents that nothing is connected, and state 5 represents
>>>>>> +that the mux controller keeps the mux in its previously selected state during
>>>>>> +the idle period. State 5 is the default idle state.
>>>>> I'm never a great fan of magic numbers. Can we represent this more cleanly by
>>>>> breaking it into multiple properties?
>>>>> Optional:
>>>>> adi,idle-switch-to-channel : switch to this channel when idle.
>>>>> adi,idle-high-impedance : <boolean> the nothing connected state?
>>>>>
>>>>> If neither present leaves it in previous state?
>>>>
>>>> It's not that easy. adi,idle-state is an array when there are three single
>>>> pole quadruple throw muxes, so there really needs to be a number for each
>>>> desired idle-behavior. Unless you have a better idea for how to describe
>>>> that?
>>> The above with arrays for each of the two parameters?
>>> Though then you need a priority documented - I'd say high impedance overrides
>>> the channel selection if both are present.
>>
>> How would you specify that the first mux should idle in "state 5", the second
>> should idle in "state 4" and the third in "state 0"? (original state numbering)
>>
>> You'd still need a magic number for the default idle state (state 5) so that
>> you can skip entries in the arrays. Or am I missing something?
> Ah I had missed state 5. Hmm would need explicit control for that as well. Not nice...
>
> Perhaps 3 state control (magic number but with channel nums separate)
>
> Idle-state array of <switchtostate, currentstate, highimpedance>
>
> Idle-state array of states to switch to if so set?
>
> Slight nicer than a mess of the two things perhaps?
Perhaps making adi,idle-state an array of tuples <mux-number state> and
add adi,idle-high-impedance as an array of mux-numbers, so that my example
above would come out as:
adi,idle-high-impedance = <1>; /* mux 1 idles with high imp */
adi,idle-state = <2 0>; /* mux 2 idles in state 0 (signal A) */
mux 0 is not mentioned and idles in its previously selected state.
If you want mux 0 to idle with high impedance:
adi,idle-high-impedance = <0 1>;
adi,idle-state = <2 0>;
If you want mux 0 to idle with signal C:
adi,idle-high-impedance = <1>;
adi,idle-state = <0 3>, <2 0>;
>>>>>> +
>>>>>> +Example:
>>>>>> +
>>>>>> + /* three independent mux controllers (of which one is used) */
>>>>>> + &i2c0 {
>>>>>> + mux: adg792a@50 {
>>>>>> + compatible = "adi,adg792a";
>>>>>> + reg = <0x50>;
>>>>>> + #mux-control-cells = <1>;
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> + adc-mux {
>>>>>> + compatible = "iio-mux";
>>>>>> + io-channels = <&adc 0>;
>>>>>> + io-channel-names = "parent";
>>>>>> +
>>>>>> + mux-controls = <&mux 1>;
>>>>>> +
>>>>>> + channels = "sync-1", "", "out";
>>>>>> + };
>>>>>> +
>>>>>> +
>>>>>> + /*
>>>>>> + * Three parallel muxes with one mux controller, useful e.g. if
>>>>>> + * the adc is differential, thus needing two signals to be muxed
>>>>>> + * simultaneously for correct operation.
>>>>>> + */
>>>>>> + &i2c0 {
>>>>>> + pmux: adg792a@50 {
>>>>>> + compatible = "adi,adg792a";
>>>>>> + reg = <0x50>;
>>>>>> + #mux-control-cells = <0>;
>>>>>> + adi,parallel;
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> + diff-adc-mux {
>>>>>> + compatible = "iio-mux";
>>>>>> + io-channels = <&adc 0>;
>>>>>> + io-channel-names = "parent";
>>>>>> +
>>>>>> + mux-controls = <&pmux>;
>>>>>> +
>>>>>> + channels = "sync-1", "", "out";
>>>>>> + };
>>>>>>
>>>>>
>>>>
>>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: [PATCH v6 8/9] dt-bindings: mux-adg792a: document devicetree bindings for ADG792A/G mux
From: Peter Rosin @ 2017-01-03 6:44 UTC (permalink / raw)
To: Jonathan Cameron, Jonathan Cameron,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Wolfram Sang, Rob Herring, Mark Rutland, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Jonathan Corbet,
Arnd Bergmann, Greg Kroah-Hartman,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <90A8A4B3-670B-4409-B7AB-47BF4B2ABDDA-tko9wxEg+fIOOJlXag/Snyp2UmYkHbXO@public.gmane.org>
On 2017-01-02 22:13, Jonathan Cameron wrote:
>
>
> On 2 January 2017 20:47:58 GMT+00:00, Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org> wrote:
>> On 2017-01-02 19:05, Jonathan Cameron wrote:
>>> On 02/01/17 16:01, Peter Rosin wrote:
>>>> On 2017-01-01 12:00, Jonathan Cameron wrote:
>>>>> On 30/11/16 08:17, Peter Rosin wrote:
>>>>>> Analog Devices ADG792A/G is a triple 4:1 mux.
>>>>>>
>>>>>> Signed-off-by: Peter Rosin <peda-koto5C5qi+TLoDKTGw+V6w@public.gmane.org>
>>>>> Few comments inline. Worth adding anything about the gpio (output pins) to
>>>>> the binding at this stage as well? Would certainly be nice to support
>>>>> them.
>>>>
>>>> I'll add optional properties "gpio-controller;" and "#gpio-cells = <2>;"
>>>> with the usual interpretation in v7 (but no implementation...) Is that
>>>> enough?
>>>>
>>>>> Jonathan
>>>>>> ---
>>>>>> .../devicetree/bindings/misc/mux-adg792a.txt | 64 ++++++++++++++++++++++
>>>>>> 1 file changed, 64 insertions(+)
>>>>>> create mode 100644 Documentation/devicetree/bindings/misc/mux-adg792a.txt
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/misc/mux-adg792a.txt b/Documentation/devicetree/bindings/misc/mux-adg792a.txt
>>>>>> new file mode 100644
>>>>>> index 000000000000..4677f9ab1c55
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/misc/mux-adg792a.txt
>>>>>> @@ -0,0 +1,64 @@
>>>>>> +Bindings for Analog Devices ADG792A/G Triple 4:1 Multiplexers
>>>>>> +
>>>>>> +Required properties:
>>>>>> +- compatible : "adi,adg792a" or "adi,adg792g"
>>>>>> +- #mux-control-cells : <0> if parallel, or <1> if not.
>>>>>> +* Standard mux-controller bindings as decribed in mux-controller.txt
>>>>>> +
>>>>>> +Optional properties:
>>>>>> +- adi,parallel : if present, the three muxes are bound together with a single
>>>>>> + mux controller, controlling all three muxes in parallel.
>>>>>> +- adi,idle-state : if present, array of states the three mux controllers will
>>>>>> + have when idle (or, if parallel, a single idle-state).
>>>>> Hmm. These are actually a policy decision. As only one policy will make
>>>>> sense for a given set of hardware probably fine to have it in here I guess.
>>>>> Might be worth adding a note to say this though.
>>>>
>>>> I don't really know what you want me to add, do you have a suggestion for the
>>>> wording?
>>>>
>>>>>> +
>>>>>> +Mux controller states 0 through 3 correspond to signals A through D in the
>>>>>> +datasheet. Mux controller states 4 and 5 are only available as possible idle
>>>>>> +states. State 4 represents that nothing is connected, and state 5 represents
>>>>>> +that the mux controller keeps the mux in its previously selected state during
>>>>>> +the idle period. State 5 is the default idle state.
>>>>> I'm never a great fan of magic numbers. Can we represent this more cleanly by
>>>>> breaking it into multiple properties?
>>>>> Optional:
>>>>> adi,idle-switch-to-channel : switch to this channel when idle.
>>>>> adi,idle-high-impedance : <boolean> the nothing connected state?
>>>>>
>>>>> If neither present leaves it in previous state?
>>>>
>>>> It's not that easy. adi,idle-state is an array when there are three single
>>>> pole quadruple throw muxes, so there really needs to be a number for each
>>>> desired idle-behavior. Unless you have a better idea for how to describe
>>>> that?
>>> The above with arrays for each of the two parameters?
>>> Though then you need a priority documented - I'd say high impedance overrides
>>> the channel selection if both are present.
>>
>> How would you specify that the first mux should idle in "state 5", the second
>> should idle in "state 4" and the third in "state 0"? (original state numbering)
>>
>> You'd still need a magic number for the default idle state (state 5) so that
>> you can skip entries in the arrays. Or am I missing something?
> Ah I had missed state 5. Hmm would need explicit control for that as well. Not nice...
>
> Perhaps 3 state control (magic number but with channel nums separate)
>
> Idle-state array of <switchtostate, currentstate, highimpedance>
>
> Idle-state array of states to switch to if so set?
>
> Slight nicer than a mess of the two things perhaps?
Perhaps making adi,idle-state an array of tuples <mux-number state> and
add adi,idle-high-impedance as an array of mux-numbers, so that my example
above would come out as:
adi,idle-high-impedance = <1>; /* mux 1 idles with high imp */
adi,idle-state = <2 0>; /* mux 2 idles in state 0 (signal A) */
mux 0 is not mentioned and idles in its previously selected state.
If you want mux 0 to idle with high impedance:
adi,idle-high-impedance = <0 1>;
adi,idle-state = <2 0>;
If you want mux 0 to idle with signal C:
adi,idle-high-impedance = <1>;
adi,idle-state = <0 3>, <2 0>;
>>>>>> +
>>>>>> +Example:
>>>>>> +
>>>>>> + /* three independent mux controllers (of which one is used) */
>>>>>> + &i2c0 {
>>>>>> + mux: adg792a@50 {
>>>>>> + compatible = "adi,adg792a";
>>>>>> + reg = <0x50>;
>>>>>> + #mux-control-cells = <1>;
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> + adc-mux {
>>>>>> + compatible = "iio-mux";
>>>>>> + io-channels = <&adc 0>;
>>>>>> + io-channel-names = "parent";
>>>>>> +
>>>>>> + mux-controls = <&mux 1>;
>>>>>> +
>>>>>> + channels = "sync-1", "", "out";
>>>>>> + };
>>>>>> +
>>>>>> +
>>>>>> + /*
>>>>>> + * Three parallel muxes with one mux controller, useful e.g. if
>>>>>> + * the adc is differential, thus needing two signals to be muxed
>>>>>> + * simultaneously for correct operation.
>>>>>> + */
>>>>>> + &i2c0 {
>>>>>> + pmux: adg792a@50 {
>>>>>> + compatible = "adi,adg792a";
>>>>>> + reg = <0x50>;
>>>>>> + #mux-control-cells = <0>;
>>>>>> + adi,parallel;
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> + diff-adc-mux {
>>>>>> + compatible = "iio-mux";
>>>>>> + io-channels = <&adc 0>;
>>>>>> + io-channel-names = "parent";
>>>>>> +
>>>>>> + mux-controls = <&pmux>;
>>>>>> +
>>>>>> + channels = "sync-1", "", "out";
>>>>>> + };
>>>>>>
>>>>>
>>>>
>>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* RE: [PATCH 1/2] arm64:dt:ls1046a: Add TMU device tree support for LS1046A
From: Troy Jia @ 2017-01-03 6:44 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Scott Wood, edubezval@gmail.com, Y.T. Tang, robh+dt@kernel.org,
rui.zhang@intel.com, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20170103062633.GR20956@dragon>
>
> On Tue, Jan 03, 2017 at 03:49:33AM +0000, Troy Jia wrote:
> > > > @@ -279,6 +282,82 @@
> > > > clocks = <&sysclk>;
> > > > };
> > > >
> > > > + tmu: tmu@1f00000 {
> > > > + compatible = "fsl,qoriq-tmu";
> > > > + reg = <0x0 0x1f00000 0x0 0x10000>;
> > > > + interrupts = <0 33 0x4>;
> > > > + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
> > > > + fsl,tmu-calibration = <0x00000000 0x00000026
> > > > + 0x00000001 0x0000002d
> > > > + 0x00000002 0x00000032
> > > > + 0x00000003 0x00000039
> > > > + 0x00000004 0x0000003f
> > > > + 0x00000005 0x00000046
> > > > + 0x00000006 0x0000004d
> > > > + 0x00000007 0x00000054
> > > > + 0x00000008 0x0000005a
> > > > + 0x00000009 0x00000061
> > > > + 0x0000000a 0x0000006a
> > > > + 0x0000000b 0x00000071
> > > > +
> > >
> > > Instead of a newline, can we have a single line comment here to tell
> > > how these calibration data is grouped?
> >
> > Each group represent one temperature range. It's a good idea to add comment
> here.
> > Could I just add one comment like below to clarify all four groups?
> > /* Each calibration data group represent one temperature range. There
> > are four ranges in total */
>
> Probably the following form?
>
> /* Calibration data group 1 */
> ...
> /* Calibration data group 2 */
> ...
> /* Calibration data group 3 */
> ...
> /* Calibration data group 4 */
> ...
>
It's good for me.
>
> >
> > >
> > > > + 0x00010000 0x00000025
> > > > + 0x00010001 0x0000002c
> > > > + 0x00010002 0x00000035
> > > > + 0x00010003 0x0000003d
> > > > + 0x00010004 0x00000045
> > > > + 0x00010005 0x0000004e
> > > > + 0x00010006 0x00000057
> > > > + 0x00010007 0x00000061
> > > > + 0x00010008 0x0000006b
> > > > + 0x00010009 0x00000076
> > > > +
> > > > + 0x00020000 0x00000029
> > > > + 0x00020001 0x00000033
> > > > + 0x00020002 0x0000003d
> > > > + 0x00020003 0x00000049
> > > > + 0x00020004 0x00000056
> > > > + 0x00020005 0x00000061
> > > > + 0x00020006 0x0000006d
> > > > +
> > > > + 0x00030000 0x00000021
> > > > + 0x00030001 0x0000002a
> > > > + 0x00030002 0x0000003c
> > > > + 0x00030003 0x0000004e>;
> > > > + big-endian;
> > > > + #thermal-sensor-cells = <1>;
> > > > + };
> > > > +
> > > > + thermal-zones {
> > > > + cpu_thermal: cpu-thermal {
> > > > + polling-delay-passive = <1000>;
> > > > + polling-delay = <5000>;
> > > > +
> > >
> > > We usually do not have newline between properties but nodes, or
> > > between property list and child node.
> >
> > I just follow the style of thermal binding of
> > Documentation/devicetree/bindings/thermal/thermal.txt.
>
> Different subsystem or binding examples use different style, but when we put
> things together in the platform dts, we would like to have them in a unified style.
Good point here.
I will fix it and send the new version.
Thanks.
-Hongtao.
^ permalink raw reply
* RE: [PATCH 1/2] arm64:dt:ls1046a: Add TMU device tree support for LS1046A
From: Troy Jia @ 2017-01-03 6:44 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Scott Wood,
edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, Y.T. Tang,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <20170103062633.GR20956@dragon>
>
> On Tue, Jan 03, 2017 at 03:49:33AM +0000, Troy Jia wrote:
> > > > @@ -279,6 +282,82 @@
> > > > clocks = <&sysclk>;
> > > > };
> > > >
> > > > + tmu: tmu@1f00000 {
> > > > + compatible = "fsl,qoriq-tmu";
> > > > + reg = <0x0 0x1f00000 0x0 0x10000>;
> > > > + interrupts = <0 33 0x4>;
> > > > + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
> > > > + fsl,tmu-calibration = <0x00000000 0x00000026
> > > > + 0x00000001 0x0000002d
> > > > + 0x00000002 0x00000032
> > > > + 0x00000003 0x00000039
> > > > + 0x00000004 0x0000003f
> > > > + 0x00000005 0x00000046
> > > > + 0x00000006 0x0000004d
> > > > + 0x00000007 0x00000054
> > > > + 0x00000008 0x0000005a
> > > > + 0x00000009 0x00000061
> > > > + 0x0000000a 0x0000006a
> > > > + 0x0000000b 0x00000071
> > > > +
> > >
> > > Instead of a newline, can we have a single line comment here to tell
> > > how these calibration data is grouped?
> >
> > Each group represent one temperature range. It's a good idea to add comment
> here.
> > Could I just add one comment like below to clarify all four groups?
> > /* Each calibration data group represent one temperature range. There
> > are four ranges in total */
>
> Probably the following form?
>
> /* Calibration data group 1 */
> ...
> /* Calibration data group 2 */
> ...
> /* Calibration data group 3 */
> ...
> /* Calibration data group 4 */
> ...
>
It's good for me.
>
> >
> > >
> > > > + 0x00010000 0x00000025
> > > > + 0x00010001 0x0000002c
> > > > + 0x00010002 0x00000035
> > > > + 0x00010003 0x0000003d
> > > > + 0x00010004 0x00000045
> > > > + 0x00010005 0x0000004e
> > > > + 0x00010006 0x00000057
> > > > + 0x00010007 0x00000061
> > > > + 0x00010008 0x0000006b
> > > > + 0x00010009 0x00000076
> > > > +
> > > > + 0x00020000 0x00000029
> > > > + 0x00020001 0x00000033
> > > > + 0x00020002 0x0000003d
> > > > + 0x00020003 0x00000049
> > > > + 0x00020004 0x00000056
> > > > + 0x00020005 0x00000061
> > > > + 0x00020006 0x0000006d
> > > > +
> > > > + 0x00030000 0x00000021
> > > > + 0x00030001 0x0000002a
> > > > + 0x00030002 0x0000003c
> > > > + 0x00030003 0x0000004e>;
> > > > + big-endian;
> > > > + #thermal-sensor-cells = <1>;
> > > > + };
> > > > +
> > > > + thermal-zones {
> > > > + cpu_thermal: cpu-thermal {
> > > > + polling-delay-passive = <1000>;
> > > > + polling-delay = <5000>;
> > > > +
> > >
> > > We usually do not have newline between properties but nodes, or
> > > between property list and child node.
> >
> > I just follow the style of thermal binding of
> > Documentation/devicetree/bindings/thermal/thermal.txt.
>
> Different subsystem or binding examples use different style, but when we put
> things together in the platform dts, we would like to have them in a unified style.
Good point here.
I will fix it and send the new version.
Thanks.
-Hongtao.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/2] arm64:dt:ls1046a: Add TMU device tree support for LS1046A
From: Troy Jia @ 2017-01-03 6:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103062633.GR20956@dragon>
>
> On Tue, Jan 03, 2017 at 03:49:33AM +0000, Troy Jia wrote:
> > > > @@ -279,6 +282,82 @@
> > > > clocks = <&sysclk>;
> > > > };
> > > >
> > > > + tmu: tmu at 1f00000 {
> > > > + compatible = "fsl,qoriq-tmu";
> > > > + reg = <0x0 0x1f00000 0x0 0x10000>;
> > > > + interrupts = <0 33 0x4>;
> > > > + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
> > > > + fsl,tmu-calibration = <0x00000000 0x00000026
> > > > + 0x00000001 0x0000002d
> > > > + 0x00000002 0x00000032
> > > > + 0x00000003 0x00000039
> > > > + 0x00000004 0x0000003f
> > > > + 0x00000005 0x00000046
> > > > + 0x00000006 0x0000004d
> > > > + 0x00000007 0x00000054
> > > > + 0x00000008 0x0000005a
> > > > + 0x00000009 0x00000061
> > > > + 0x0000000a 0x0000006a
> > > > + 0x0000000b 0x00000071
> > > > +
> > >
> > > Instead of a newline, can we have a single line comment here to tell
> > > how these calibration data is grouped?
> >
> > Each group represent one temperature range. It's a good idea to add comment
> here.
> > Could I just add one comment like below to clarify all four groups?
> > /* Each calibration data group represent one temperature range. There
> > are four ranges in total */
>
> Probably the following form?
>
> /* Calibration data group 1 */
> ...
> /* Calibration data group 2 */
> ...
> /* Calibration data group 3 */
> ...
> /* Calibration data group 4 */
> ...
>
It's good for me.
>
> >
> > >
> > > > + 0x00010000 0x00000025
> > > > + 0x00010001 0x0000002c
> > > > + 0x00010002 0x00000035
> > > > + 0x00010003 0x0000003d
> > > > + 0x00010004 0x00000045
> > > > + 0x00010005 0x0000004e
> > > > + 0x00010006 0x00000057
> > > > + 0x00010007 0x00000061
> > > > + 0x00010008 0x0000006b
> > > > + 0x00010009 0x00000076
> > > > +
> > > > + 0x00020000 0x00000029
> > > > + 0x00020001 0x00000033
> > > > + 0x00020002 0x0000003d
> > > > + 0x00020003 0x00000049
> > > > + 0x00020004 0x00000056
> > > > + 0x00020005 0x00000061
> > > > + 0x00020006 0x0000006d
> > > > +
> > > > + 0x00030000 0x00000021
> > > > + 0x00030001 0x0000002a
> > > > + 0x00030002 0x0000003c
> > > > + 0x00030003 0x0000004e>;
> > > > + big-endian;
> > > > + #thermal-sensor-cells = <1>;
> > > > + };
> > > > +
> > > > + thermal-zones {
> > > > + cpu_thermal: cpu-thermal {
> > > > + polling-delay-passive = <1000>;
> > > > + polling-delay = <5000>;
> > > > +
> > >
> > > We usually do not have newline between properties but nodes, or
> > > between property list and child node.
> >
> > I just follow the style of thermal binding of
> > Documentation/devicetree/bindings/thermal/thermal.txt.
>
> Different subsystem or binding examples use different style, but when we put
> things together in the platform dts, we would like to have them in a unified style.
Good point here.
I will fix it and send the new version.
Thanks.
-Hongtao.
^ permalink raw reply
* [PATCH] ARM: imx: Add rtc support to i.MX31 PDK board.
From: Shawn Guo @ 2017-01-03 6:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483352282-28970-1-git-send-email-lilja.magnus@gmail.com>
On Mon, Jan 02, 2017 at 11:18:02AM +0100, Magnus Lilja wrote:
> Enable support for i.MX31 RTC on the PDK board.
>
> Tested on actual hardware.
>
> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
> ---
> arch/arm/mach-imx/mach-mx31_3ds.c | 1 +
> 1 file changed, 1 insertion(+)
We do not take any more patches on legacy board files, except cleanup
ones. Please help get i.MX31 DT support better.
Shawn
>
> diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
> index 12b8a52..c6a12ac 100644
> --- a/arch/arm/mach-imx/mach-mx31_3ds.c
> +++ b/arch/arm/mach-imx/mach-mx31_3ds.c
> @@ -710,6 +710,7 @@ static void __init mx31_3ds_init(void)
> imx31_add_imx_keypad(&mx31_3ds_keymap_data);
>
> imx31_add_imx2_wdt();
> + imx31_add_mxc_rtc();
> imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
>
> imx31_add_spi_imx0(&spi0_pdata);
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 1/2] drm: Add new DRM_IOCTL_MODE_GETPLANE2
From: Daniel Kurtz @ 2017-01-03 6:42 UTC (permalink / raw)
To: Kristian H. Kristensen
Cc: Kristian H . Kristensen, Kristian H. Kristensen, ben, dri-devel
In-Reply-To: <20161221001222.21864-1-hoegsberg@gmail.com>
Hi Kristian,
On Wed, Dec 21, 2016 at 8:12 AM, Kristian H. Kristensen
<hoegsberg@gmail.com> wrote:
> From: "Kristian H. Kristensen" <hoegsberg@google.com>
>
> This new ioctl exctends DRM_IOCTL_MODE_GETPLANE, by returning
> information about the modifiers that will work with each format.
>
> Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
> ---
> drivers/gpu/drm/arm/hdlcd_crtc.c | 1 +
> drivers/gpu/drm/armada/armada_crtc.c | 1 +
> drivers/gpu/drm/armada/armada_overlay.c | 1 +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 4 ++-
> drivers/gpu/drm/drm_ioctl.c | 2 +-
> drivers/gpu/drm/drm_modeset_helper.c | 1 +
> drivers/gpu/drm/drm_plane.c | 40 +++++++++++++++++++++++--
> drivers/gpu/drm/drm_simple_kms_helper.c | 5 ++++
> drivers/gpu/drm/exynos/exynos_drm_plane.c | 2 +-
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 5 +++-
> drivers/gpu/drm/imx/ipuv3-plane.c | 4 +--
Looks like this missed drivers/gpu/drm/mediatek.
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 2 +-
> drivers/gpu/drm/nouveau/nv50_display.c | 5 ++--
> drivers/gpu/drm/omapdrm/omap_plane.c | 3 +-
> drivers/gpu/drm/rcar-du/rcar_du_plane.c | 4 +--
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 +--
> drivers/gpu/drm/sti/sti_cursor.c | 1 +
> drivers/gpu/drm/sti/sti_gdp.c | 2 +-
> drivers/gpu/drm/sti/sti_hqvdp.c | 2 +-
> drivers/gpu/drm/tegra/dc.c | 12 ++++----
> drivers/gpu/drm/vc4/vc4_plane.c | 2 +-
> drivers/gpu/drm/virtio/virtgpu_plane.c | 2 +-
> include/drm/drm_plane.h | 7 ++++-
> include/drm/drm_simple_kms_helper.h | 2 ++
> include/uapi/drm/drm.h | 1 +
> include/uapi/drm/drm_mode.h | 27 +++++++++++++++++
> 27 files changed, 116 insertions(+), 28 deletions(-)
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH V2] arm64:dts:ls1046a: Add TMU device tree support
From: Jia Hongtao @ 2017-01-03 6:42 UTC (permalink / raw)
To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
edubezval-Re5JQEeQqe8AvxtiuMwx3w, yuantian.tang-3arQi8VN3Tc,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, scott.wood-3arQi8VN3Tc
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
hongtao.jia-3arQi8VN3Tc
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao.jia-3arQi8VN3Tc@public.gmane.org>
---
Changes for V2:
* Update the subject title according to Shawn Guo's comment.
* Add comments for calibration data groups.
* Update "thermal-zones" property in a unified style with platform dts.
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 83 ++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..df53a4a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +68,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -279,6 +281,87 @@
clocks = <&sysclk>;
};
+ tmu: tmu@1f00000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f00000 0x0 0x10000>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration =
+ /* Calibration data group 1*/
+ <0x00000000 0x00000026
+ 0x00000001 0x0000002d
+ 0x00000002 0x00000032
+ 0x00000003 0x00000039
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000046
+ 0x00000006 0x0000004d
+ 0x00000007 0x00000054
+ 0x00000008 0x0000005a
+ 0x00000009 0x00000061
+ 0x0000000a 0x0000006a
+ 0x0000000b 0x00000071
+
+ /* Calibration data group 2*/
+ 0x00010000 0x00000025
+ 0x00010001 0x0000002c
+ 0x00010002 0x00000035
+ 0x00010003 0x0000003d
+ 0x00010004 0x00000045
+ 0x00010005 0x0000004e
+ 0x00010006 0x00000057
+ 0x00010007 0x00000061
+ 0x00010008 0x0000006b
+ 0x00010009 0x00000076
+
+ /* Calibration data group 3*/
+ 0x00020000 0x00000029
+ 0x00020001 0x00000033
+ 0x00020002 0x0000003d
+ 0x00020003 0x00000049
+ 0x00020004 0x00000056
+ 0x00020005 0x00000061
+ 0x00020006 0x0000006d
+
+ /* Calibration data group 4*/
+ 0x00030000 0x00000021
+ 0x00030001 0x0000002a
+ 0x00030002 0x0000003c
+ 0x00030003 0x0000004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
dspi: dspi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
--
2.1.0.27.g96db324
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH V2] arm64:dts:ls1046a: Add TMU device tree support
From: Jia Hongtao @ 2017-01-03 6:42 UTC (permalink / raw)
To: linux-arm-kernel
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
---
Changes for V2:
* Update the subject title according to Shawn Guo's comment.
* Add comments for calibration data groups.
* Update "thermal-zones" property in a unified style with platform dts.
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 83 ++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..df53a4a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +68,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu at 1 {
@@ -279,6 +281,87 @@
clocks = <&sysclk>;
};
+ tmu: tmu at 1f00000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f00000 0x0 0x10000>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration =
+ /* Calibration data group 1*/
+ <0x00000000 0x00000026
+ 0x00000001 0x0000002d
+ 0x00000002 0x00000032
+ 0x00000003 0x00000039
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000046
+ 0x00000006 0x0000004d
+ 0x00000007 0x00000054
+ 0x00000008 0x0000005a
+ 0x00000009 0x00000061
+ 0x0000000a 0x0000006a
+ 0x0000000b 0x00000071
+
+ /* Calibration data group 2*/
+ 0x00010000 0x00000025
+ 0x00010001 0x0000002c
+ 0x00010002 0x00000035
+ 0x00010003 0x0000003d
+ 0x00010004 0x00000045
+ 0x00010005 0x0000004e
+ 0x00010006 0x00000057
+ 0x00010007 0x00000061
+ 0x00010008 0x0000006b
+ 0x00010009 0x00000076
+
+ /* Calibration data group 3*/
+ 0x00020000 0x00000029
+ 0x00020001 0x00000033
+ 0x00020002 0x0000003d
+ 0x00020003 0x00000049
+ 0x00020004 0x00000056
+ 0x00020005 0x00000061
+ 0x00020006 0x0000006d
+
+ /* Calibration data group 4*/
+ 0x00030000 0x00000021
+ 0x00030001 0x0000002a
+ 0x00030002 0x0000003c
+ 0x00030003 0x0000004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
dspi: dspi at 2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH] ARM: imx_v6_v7_defconfig: Select wireless extensions option
From: Shawn Guo @ 2017-01-03 6:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483204559-22166-1-git-send-email-festevam@gmail.com>
On Sat, Dec 31, 2016 at 03:15:59PM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> Select CONFIG_CFG80211_WEXT so that wireless can work out of the box
> when using userspace tools such as 'iwconfig'.
>
> Generated by manually selecting CONFIG_CFG80211_WEXT and
> then running:
>
> make savedefconfig
> cp defconfig arch/arm/configs/imx_v6_v7_defconfig
>
> , which results in additional cleanup.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Applied, thanks.
^ permalink raw reply
* Re: [RFC PATCH] ACPI/PCI: Fix bus range comparation in pci_mcfg_lookup
From: Tomasz Nowicki @ 2017-01-03 6:39 UTC (permalink / raw)
To: Zhou Wang, Rafael J. Wysocki, Len Brown, Jayachandran C,
Lorenzo Pieralisi, jorn Helgaas
Cc: liudongdong3, gabriele.paoloni, linux-acpi, linux-pci,
linux-kernel
In-Reply-To: <1482397663-98715-1-git-send-email-wangzhou1@hisilicon.com>
On 22.12.2016 10:07, Zhou Wang wrote:
> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each
> host bridge should be in the coverage of bus range of related PCIe segment.
>
> This patch will support this kind of scenario:
>
> MCFG:
> bus range: 0x00~0xff.
> segment: 0.
> DSDT:
> host bridge 1:
> bus range: 0x00~0x1f.
> segment: 0.
> host bridge 2:
> bus range: 0x20~0x4f.
> segment: 0.
>
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
> ---
> drivers/acpi/pci_mcfg.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index b5b376e..46a3e32 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -40,11 +40,10 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res)
> struct mcfg_entry *e;
>
> /*
> - * We expect exact match, unless MCFG entry end bus covers more than
> - * specified by caller.
> + * We expect the range in bus_res in the coverage of MCFG bus range.
> */
> list_for_each_entry(e, &pci_mcfg_list, list) {
> - if (e->segment == seg && e->bus_start == bus_res->start &&
> + if (e->segment == seg && e->bus_start <= bus_res->start &&
> e->bus_end >= bus_res->end)
> return e->addr;
> }
>
Looks good to me.
Reviewed-by: Tomasz Nowicki <tn@semihalf.com>
Thanks,
Tomasz
^ permalink raw reply
* Re: [TOOL] wg-config graduates to src/tools, becomes wg-auto-config
From: Daniel Kahn Gillmor @ 2017-01-03 6:46 UTC (permalink / raw)
To: Jason A. Donenfeld, WireGuard mailing list
In-Reply-To: <CAHmME9q1RQ_Z3tikOkOECsw5xNx5Mttwm5=MPV7PRqu+DcipkA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1338 bytes --]
On Mon 2017-01-02 10:17:30 -0500, Jason A. Donenfeld wrote:
> On Mon, Jan 2, 2017 at 5:57 AM, Jason A. Donenfeld <Jason@zx2c4.com> wrote:
>> Check out the man page, read the script --
>> https://git.zx2c4.com/WireGuard/tree/src/tools/wg-auto-config -- and
>> please let me know what you think before I cut the next snapshot.
> Renamed:
> https://git.zx2c4.com/WireGuard/tree/src/tools/wg-auto-config.bash
debian is unlikely to install this if it is expected to be named with a
.bash suffix:
https://www.debian.org/doc/debian-policy/ch-files.html#s-scripts
>>> When scripts are installed into a directory in the system PATH, the
>>> script name should not include an extension such as .sh or .pl that
>>> denotes the scripting language currently used to implement it.
That said, i'm not sure what you want with this. If the ultimate goal
is to have systemd-style .network files, you should ask for these
changes in systemd itself. That's likely the cleanest approach. If you
do this, please post a link here to the systemd github issue or pull
request. :)
If it's just "we want a configuration for wg, but with some common/handy
wrappers around /bin/ip", you could (a) fork and exec ip from wg itself
when running "wg setconf", or (b) name the wrapper something like
/usr/bin/wg+ip
--dkg
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 832 bytes --]
^ permalink raw reply
* [PATCH 8/8] ARM: dts: imx6q-evi: Fix onboard hub reset line
From: Peter Chen @ 2017-01-03 6:33 UTC (permalink / raw)
To: gregkh, stern, ulf.hansson, broonie, sre, robh+dt, shawnguo, rjw,
dbaryshkov
Cc: heiko, linux-arm-kernel, p.zabel, devicetree, pawel.moll,
mark.rutland, linux-usb, arnd, s.hauer, mail, troy.kisky,
festevam, oscar, stephen.boyd, linux-pm, stillcompiling,
linux-kernel, mka, vaibhav.hiremath, gary.bisson, hverkuil, krzk,
Peter Chen
In-Reply-To: <1483425211-14473-1-git-send-email-peter.chen@nxp.com>
From: Joshua Clayton <stillcompiling@gmail.com>
Previously the onboard hub was made to work by treating its
reset gpio as a regulator enable.
Get rid of that kludge now that pwseq has added reset gpio support
Move pin muxing the hub reset pin into the usbh1 group
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
---
arch/arm/boot/dts/imx6q-evi.dts | 25 +++++++------------------
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 7c7c1a8..79a0bd5 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -54,18 +54,6 @@
reg = <0x10000000 0x40000000>;
};
- reg_usbh1_vbus: regulator-usbhubreset {
- compatible = "regulator-fixed";
- regulator-name = "usbh1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- startup-delay-us = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh1_hubreset>;
- gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
- };
-
reg_usb_otg_vbus: regulator-usbotgvbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
@@ -207,12 +195,18 @@
};
&usbh1 {
- vbus-supply = <®_usbh1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
dr_mode = "host";
disable-over-current;
status = "okay";
+
+ usb2415host: hub@1 {
+ compatible = "usb424,2513";
+ reg = <1>;
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ reset-duration-us = <3000>;
+ };
};
&usbotg {
@@ -468,11 +462,6 @@
MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0
/* usbh1_b OC */
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
- >;
- };
-
- pinctrl_usbh1_hubreset: usbh1hubresetgrp {
- fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v1 1/1] Input: adxl34x - Make it enumerable in ACPI environment
From: Dmitry Torokhov @ 2017-01-03 6:35 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: linux-input, Mika Westerberg, Jarkko Nikula
In-Reply-To: <20170102120624.178283-1-andriy.shevchenko@linux.intel.com>
On Mon, Jan 02, 2017 at 02:06:23PM +0200, Andy Shevchenko wrote:
> The ACPI-enabled platform may contain _DSD method to enable this driver using
> compatible string.
>
> Remove OF specifics to re-use existing code on ACPI-enabled platforms.
Is there an x86 box that uses this device?
Thanks.
>
> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/input/misc/adxl34x-i2c.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/input/misc/adxl34x-i2c.c b/drivers/input/misc/adxl34x-i2c.c
> index a8b0a2eec344..7fed92fb8cc1 100644
> --- a/drivers/input/misc/adxl34x-i2c.c
> +++ b/drivers/input/misc/adxl34x-i2c.c
> @@ -136,7 +136,6 @@ static const struct i2c_device_id adxl34x_id[] = {
>
> MODULE_DEVICE_TABLE(i2c, adxl34x_id);
>
> -#ifdef CONFIG_OF
> static const struct of_device_id adxl34x_of_id[] = {
> /*
> * The ADXL346 is backward-compatible with the ADXL345. Differences are
> @@ -153,13 +152,12 @@ static const struct of_device_id adxl34x_of_id[] = {
> };
>
> MODULE_DEVICE_TABLE(of, adxl34x_of_id);
> -#endif
>
> static struct i2c_driver adxl34x_driver = {
> .driver = {
> .name = "adxl34x",
> .pm = &adxl34x_i2c_pm,
> - .of_match_table = of_match_ptr(adxl34x_of_id),
> + .of_match_table = adxl34x_of_id,
> },
> .probe = adxl34x_i2c_probe,
> .remove = adxl34x_i2c_remove,
> --
> 2.11.0
>
--
Dmitry
^ permalink raw reply
* [PATCH 4/6] PCI/ASPM: Calculate and save the L1.2 timing parameters
From: Rajat Jain @ 2017-01-03 6:34 UTC (permalink / raw)
To: Bjorn Helgaas, Keith Busch, Andreas Ziegler, Jonathan Yong,
Shawn Lin, David Daney, Julia Lawall, Ram Amrani, Doug Ledford,
Wang Sheng-Hui, linux-pci, linux-kernel
Cc: Rajat Jain, Rajat Jain, Brian Norris
In-Reply-To: <1483425255-101923-1-git-send-email-rajatja@google.com>
Calculate and save the timing parameters that need to be programmed
if we need to enable L1.2 substates later.
We use the same logic (and a constant value for 1 of the
parameters) as used by Intel's coreboot:
https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
https://review.coreboot.org/#/c/8832/
Signed-off-by: Rajat Jain <rajatja@google.com>
---
drivers/pci/pcie/aspm.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 7a3ad85..a70afdf 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -42,6 +42,18 @@
#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
ASPM_STATE_L1SS)
+/*
+ * When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter
+ * that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details).
+ * Not sure is there is a way to "calculate" this on the fly, but may be we
+ * could turn it into a parameter in future. This value has been taken from
+ * the following files from Intel's coreboot (which is the only code I found
+ * to have used this):
+ * https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
+ * https://review.coreboot.org/#/c/8832/
+ */
+#define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30))
+
struct aspm_latency {
u32 l0s; /* L0s latency (nsec) */
u32 l1; /* L1 latency (nsec) */
@@ -76,6 +88,14 @@ struct pcie_link_state {
* has one slot under it, so at most there are 8 functions.
*/
struct aspm_latency acceptable[8];
+
+ /* L1 PM Substate info */
+ struct {
+ u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
+ u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
+ u32 ctl1; /* value to be programmed in ctl1 */
+ u32 ctl2; /* value to be programmed in ctl2 */
+ } l1ss;
};
static int aspm_disabled, aspm_force;
@@ -296,6 +316,22 @@ static u32 calc_l1_acceptable(u32 encoding)
return (1000 << encoding);
}
+/* Convert L1SS T_pwr encoding to usec */
+static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
+{
+ switch (scale) {
+ case 0:
+ return val * 2;
+ case 1:
+ return val * 10;
+ case 2:
+ return val * 100;
+ }
+ dev_err(&pdev->dev, "%s: Invalid T_PwrOn scale: %u\n",
+ __func__, scale);
+ return 0;
+}
+
struct aspm_register_info {
u32 support:2;
u32 enabled:2;
@@ -392,6 +428,46 @@ static inline struct pci_dev *pci_function_0(struct pci_bus *linkbus)
return NULL;
}
+/* Calculate L1.2 PM substate timing parameters */
+static void aspm_calc_l1ss_info(struct pcie_link_state *link,
+ struct aspm_register_info *upreg,
+ struct aspm_register_info *dwreg)
+{
+ u32 val1, val2, scale1, scale2;
+
+ link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
+ link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
+ link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
+
+ if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
+ return;
+
+ /* Choose the greater of the two T_cmn_mode_rstr_time */
+ val1 = (upreg->l1ss_cap >> 8) & 0xFF;
+ val2 = (upreg->l1ss_cap >> 8) & 0xFF;
+ if (val1 > val2)
+ link->l1ss.ctl1 |= val1 << 8;
+ else
+ link->l1ss.ctl1 |= val2 << 8;
+ /*
+ * We currently use LTR L1.2 threshold to be fixed constant picked from
+ * Intel's coreboot.
+ */
+ link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
+
+ /* Choose the greater of the two T_pwr_on */
+ val1 = (upreg->l1ss_cap >> 19) & 0x1F;
+ scale1 = (upreg->l1ss_cap >> 16) & 0x03;
+ val2 = (dwreg->l1ss_cap >> 19) & 0x1F;
+ scale2 = (dwreg->l1ss_cap >> 16) & 0x03;
+
+ if (calc_l1ss_pwron(link->pdev, scale1, val1) >
+ calc_l1ss_pwron(link->downstream, scale2, val2))
+ link->l1ss.ctl2 |= scale1 | (val1 << 3);
+ else
+ link->l1ss.ctl2 |= scale2 | (val2 << 3);
+}
+
static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
{
struct pci_dev *child, *parent = link->pdev;
@@ -471,6 +547,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
+ if (link->aspm_support & ASPM_STATE_L1SS)
+ aspm_calc_l1ss_info(link, &upreg, &dwreg);
+
/* Save default state */
link->aspm_default = link->aspm_enabled;
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* [PATCH 6/6] PCI/ASPM: Add comment about L1 substate latency
From: Rajat Jain @ 2017-01-03 6:34 UTC (permalink / raw)
To: Bjorn Helgaas, Keith Busch, Andreas Ziegler, Jonathan Yong,
Shawn Lin, David Daney, Julia Lawall, Ram Amrani, Doug Ledford,
Wang Sheng-Hui, linux-pci, linux-kernel
Cc: Rajat Jain, Rajat Jain, Brian Norris
In-Reply-To: <1483425255-101923-1-git-send-email-rajatja@google.com>
Since the exit latencies for L1 substates are not advertised by
a device, it is not clear in spec how to do a L1 substate exit
latency check. We assume that the L1 exit latencies advertised
by a device include L1 substate latencies (and hence do not do any
check). If that is not true, we should do some sort of check here.
(I'm not clear about what that check should like currenlty. I'd be
glad to take up any suggestions).
Signed-off-by: Rajat Jain <rajatja@google.com>
---
drivers/pci/pcie/aspm.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 6735f38..cb5602c 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -403,6 +403,14 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
* Check L1 latency.
* Every switch on the path to root complex need 1
* more microsecond for L1. Spec doesn't mention L0s.
+ *
+ * The exit latencies for L1 substates are not advertised
+ * by a device. Since the spec also doesn't mention a way
+ * to determine max latencies introduced by enabling L1
+ * substates on the components, it is not clear how to do
+ * a L1 substate exit latency check. We assume that the
+ * L1 exit latencies advertised by a device include L1
+ * substate latencies (and hence do not do any check)
*/
latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
if ((link->aspm_capable & ASPM_STATE_L1) &&
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* [PATCH 6/8] ARM: dts: imx6qdl: Enable usb node children with <reg>
From: Peter Chen @ 2017-01-03 6:33 UTC (permalink / raw)
To: gregkh, stern, ulf.hansson, broonie, sre, robh+dt, shawnguo, rjw,
dbaryshkov
Cc: heiko, linux-arm-kernel, p.zabel, devicetree, pawel.moll,
mark.rutland, linux-usb, arnd, s.hauer, mail, troy.kisky,
festevam, oscar, stephen.boyd, linux-pm, stillcompiling,
linux-kernel, mka, vaibhav.hiremath, gary.bisson, hverkuil, krzk,
Peter Chen
In-Reply-To: <1483425211-14473-1-git-send-email-peter.chen@nxp.com>
From: Joshua Clayton <stillcompiling@gmail.com>
Give usb nodes #address and #size attributes, so that a child node
representing a permanently connected device such as an onboard hub may
be addressed with a <reg> attribute
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 53e6e63..e6725f1 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -936,6 +936,8 @@
usbh1: usb@02184200 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x02184200 0x200>;
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
@@ -950,6 +952,8 @@
usbh2: usb@02184400 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x02184400 0x200>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
@@ -963,6 +967,8 @@
usbh3: usb@02184600 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x02184600 0x200>;
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
--
2.7.4
^ permalink raw reply related
* [PATCH 5/6] PCI/ASPM: Actually configure the L1 substate settings to the device
From: Rajat Jain @ 2017-01-03 6:34 UTC (permalink / raw)
To: Bjorn Helgaas, Keith Busch, Andreas Ziegler, Jonathan Yong,
Shawn Lin, David Daney, Julia Lawall, Ram Amrani, Doug Ledford,
Wang Sheng-Hui, linux-pci, linux-kernel
Cc: Rajat Jain, Rajat Jain, Brian Norris
In-Reply-To: <1483425255-101923-1-git-send-email-rajatja@google.com>
Add code to actually configure the L1 substate settigns on the
upstream and downstream device, while taking care of the rules
dictated by the PCIe spec.
Signed-off-by: Rajat Jain <rajatja@google.com>
---
drivers/pci/pcie/aspm.c | 106 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 104 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index a70afdf..6735f38 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -588,6 +588,92 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
}
}
+static inline void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
+ u32 clear, u32 set)
+{
+ u32 val;
+
+ pci_read_config_dword(pdev, pos, &val);
+ val &= ~clear;
+ val |= set;
+ pci_write_config_dword(pdev, pos, val);
+}
+
+/* Configure the ASPM L1 substates */
+static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
+{
+ u32 val, enable_req;
+ struct pci_dev *child = link->downstream, *parent = link->pdev;
+ u32 up_cap_ptr = link->l1ss.up_cap_ptr;
+ u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
+
+ enable_req = (link->aspm_enabled ^ state) & state;
+
+ /*
+ * Here are the rules specified in the PCIe spec for enabling L1SS:
+ * - When enabling L1.x, enable bit at parent first, then at child
+ * - When disabling L1.x, disable bit at child first, then at parent
+ * - When enabling ASPM L1.x, need to disable L1
+ * (at child followed by parent).
+ * - The ASPM/PCIPM L1.2 must be disabled while programming timin
+ * parameters
+ *
+ * To keep it simple, disable all L1SS bits first, and later enable
+ * what is needed.
+ */
+
+ /* Disable all L1 substates */
+ pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
+ PCI_L1SS_CTL1_L1SS_MASK, 0);
+ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
+ PCI_L1SS_CTL1_L1SS_MASK, 0);
+ /*
+ * If needed, disable L1, and it gets enabled later
+ * in pcie_config_aspm_link().
+ */
+ if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
+ pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
+ PCI_EXP_LNKCTL_ASPM_L1, 0);
+ pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
+ PCI_EXP_LNKCTL_ASPM_L1, 0);
+ }
+
+ if (enable_req & ASPM_STATE_L1_2_MASK) {
+
+ /* Program T_pwr_on in both ports */
+ pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
+ link->l1ss.ctl2);
+ pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
+ link->l1ss.ctl2);
+
+ /* Program T_cmn_mode in parent */
+ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
+ 0xFF00, link->l1ss.ctl1);
+
+ /* Program LTR L1.2 threshold in both ports */
+ pci_clear_and_set_dword(parent, dw_cap_ptr + PCI_L1SS_CTL1,
+ 0xE3FF0000, link->l1ss.ctl1);
+ pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
+ 0xE3FF0000, link->l1ss.ctl1);
+ }
+
+ val = 0;
+ if (state & ASPM_STATE_L1_1)
+ val |= PCI_L1SS_CTL1_ASPM_L1_1;
+ if (state & ASPM_STATE_L1_2)
+ val |= PCI_L1SS_CTL1_ASPM_L1_2;
+ if (state & ASPM_STATE_L1_1_PCIPM)
+ val |= PCI_L1SS_CTL1_PCIPM_L1_1;
+ if (state & ASPM_STATE_L1_2_PCIPM)
+ val |= PCI_L1SS_CTL1_PCIPM_L1_2;
+
+ /* Enable what we need to enable */
+ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
+ PCI_L1SS_CAP_L1_PM_SS, val);
+ pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
+ PCI_L1SS_CAP_L1_PM_SS, val);
+}
+
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
{
pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
@@ -597,11 +683,23 @@ static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
{
u32 upstream = 0, dwstream = 0;
- struct pci_dev *child, *parent = link->pdev;
+ struct pci_dev *child = link->downstream, *parent = link->pdev;
struct pci_bus *linkbus = parent->subordinate;
- /* Nothing to do if the link is already in the requested state */
+ /* Enable only the states that were not explicitly disabled */
state &= (link->aspm_capable & ~link->aspm_disable);
+
+ /* Can't enable any substates if L1 is not enabled */
+ if (!(state & ASPM_STATE_L1))
+ state &= ~ASPM_STATE_L1SS;
+
+ /* Spec says both ports must be in D0 before enabling PCI PM substates*/
+ if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
+ state &= ~ASPM_STATE_L1_SS_PCIPM;
+ state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
+ }
+
+ /* Nothing to do if the link is already in the requested state */
if (link->aspm_enabled == state)
return;
/* Convert ASPM state to upstream/downstream ASPM register state */
@@ -613,6 +711,10 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
upstream |= PCI_EXP_LNKCTL_ASPM_L1;
dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
}
+
+ if (link->aspm_capable & ASPM_STATE_L1SS)
+ pcie_config_aspm_l1ss(link, state);
+
/*
* Spec 2.0 suggests all functions should be configured the
* same setting for ASPM. Enabling ASPM L1 should be done in
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* [PATCH 2/6] PCI/ASPM: Introduce L1 substates and a Kconfig for it
From: Rajat Jain @ 2017-01-03 6:34 UTC (permalink / raw)
To: Bjorn Helgaas, Keith Busch, Andreas Ziegler, Jonathan Yong,
Shawn Lin, David Daney, Julia Lawall, Ram Amrani, Doug Ledford,
Wang Sheng-Hui, linux-pci, linux-kernel
Cc: Rajat Jain, Rajat Jain, Brian Norris
In-Reply-To: <1483425255-101923-1-git-send-email-rajatja@google.com>
Introduce the L1 sub states. (For details about L1 substates,
please refer to:
https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf)
This patch adds macros for the 4 new L1 substates, and adds
a new ASPM "POWER_SUPERSAVE" policy that can be used to enable
L1 substates on a system if desired. The new policy is in a sense,
a super set of the existing POWERSAVE policy. The 4 policies are now:
DEFAULT: Reads and uses whatever ASPM states BIOS enabled
PERFORMANCE: Everything except L0 disabled.
POWERSAVE: L0s and L1 enabled (but not L1 substates)
POWER_SUPERSAVE: L0s + L1 + L1 substates also enabled.
Signed-off-by: Rajat Jain <rajatja@google.com>
---
drivers/pci/pcie/Kconfig | 8 ++++++++
drivers/pci/pcie/aspm.c | 39 +++++++++++++++++++++++++++++----------
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 7ce7763..ac53edb 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -71,6 +71,14 @@ config PCIEASPM_POWERSAVE
Enable PCI Express ASPM L0s and L1 where possible, even if the
BIOS did not.
+config PCIEASPM_POWER_SUPERSAVE
+ bool "Power Supersave"
+ depends on PCIEASPM
+ help
+ Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
+ possible. This would result in higher power savings while staying in L1
+ where the components support it.
+
config PCIEASPM_PERFORMANCE
bool "Performance"
depends on PCIEASPM
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 17ac1dc..402c229 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -30,8 +30,17 @@
#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
#define ASPM_STATE_L1 (4) /* L1 state */
+#define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
+#define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
+#define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
+#define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
+#define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
+#define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
+#define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
+ ASPM_STATE_L1_2_MASK)
#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
-#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
+#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
+ ASPM_STATE_L1SS)
struct aspm_latency {
u32 l0s; /* L0s latency (nsec) */
@@ -47,11 +56,11 @@ struct pcie_link_state {
struct list_head link; /* node in parent's children list */
/* ASPM state */
- u32 aspm_support:3; /* Supported ASPM state */
- u32 aspm_enabled:3; /* Enabled ASPM state */
- u32 aspm_capable:3; /* Capable ASPM state with latency */
- u32 aspm_default:3; /* Default ASPM state by BIOS */
- u32 aspm_disable:3; /* Disabled ASPM state */
+ u32 aspm_support:7; /* Supported ASPM state */
+ u32 aspm_enabled:7; /* Enabled ASPM state */
+ u32 aspm_capable:7; /* Capable ASPM state with latency */
+ u32 aspm_default:7; /* Default ASPM state by BIOS */
+ u32 aspm_disable:7; /* Disabled ASPM state */
/* Clock PM state */
u32 clkpm_capable:1; /* Clock PM capable? */
@@ -76,11 +85,14 @@ static LIST_HEAD(link_list);
#define POLICY_DEFAULT 0 /* BIOS default setting */
#define POLICY_PERFORMANCE 1 /* high performance */
#define POLICY_POWERSAVE 2 /* high power saving */
+#define POLICY_POWER_SUPERSAVE 3 /* Possibly Even higher power saving */
#ifdef CONFIG_PCIEASPM_PERFORMANCE
static int aspm_policy = POLICY_PERFORMANCE;
#elif defined CONFIG_PCIEASPM_POWERSAVE
static int aspm_policy = POLICY_POWERSAVE;
+#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
+static int aspm_policy = POLICY_POWER_SUPERSAVE;
#else
static int aspm_policy;
#endif
@@ -88,7 +100,8 @@ static int aspm_policy;
static const char *policy_str[] = {
[POLICY_DEFAULT] = "default",
[POLICY_PERFORMANCE] = "performance",
- [POLICY_POWERSAVE] = "powersave"
+ [POLICY_POWERSAVE] = "powersave",
+ [POLICY_POWER_SUPERSAVE] = "powersupersave"
};
#define LINK_RETRAIN_TIMEOUT HZ
@@ -101,6 +114,9 @@ static int policy_to_aspm_state(struct pcie_link_state *link)
return 0;
case POLICY_POWERSAVE:
/* Enable ASPM L0s/L1 */
+ return (ASPM_STATE_L0S | ASPM_STATE_L1);
+ case POLICY_POWER_SUPERSAVE:
+ /* Enable Everything */
return ASPM_STATE_ALL;
case POLICY_DEFAULT:
return link->aspm_default;
@@ -115,7 +131,8 @@ static int policy_to_clkpm_state(struct pcie_link_state *link)
/* Disable ASPM and Clock PM */
return 0;
case POLICY_POWERSAVE:
- /* Disable Clock PM */
+ case POLICY_POWER_SUPERSAVE:
+ /* Enable Clock PM */
return 1;
case POLICY_DEFAULT:
return link->clkpm_default;
@@ -612,7 +629,8 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
* the BIOS's expectation, we'll do so once pci_enable_device() is
* called.
*/
- if (aspm_policy != POLICY_POWERSAVE) {
+ if (aspm_policy != POLICY_POWERSAVE &&
+ aspm_policy != POLICY_POWER_SUPERSAVE) {
pcie_config_aspm_path(link);
pcie_set_clkpm(link, policy_to_clkpm_state(link));
}
@@ -712,7 +730,8 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
if (aspm_disabled || !link)
return;
- if (aspm_policy != POLICY_POWERSAVE)
+ if (aspm_policy != POLICY_POWERSAVE &&
+ aspm_policy != POLICY_POWER_SUPERSAVE)
return;
down_read(&pci_bus_sem);
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* [PATCH 7/8] ARM: dts: imx6qdl-udoo.dtsi: fix onboard USB HUB property
From: Peter Chen @ 2017-01-03 6:33 UTC (permalink / raw)
To: gregkh, stern, ulf.hansson, broonie, sre, robh+dt, shawnguo, rjw,
dbaryshkov
Cc: heiko, linux-arm-kernel, p.zabel, devicetree, pawel.moll,
mark.rutland, linux-usb, arnd, s.hauer, mail, troy.kisky,
festevam, oscar, stephen.boyd, linux-pm, stillcompiling,
linux-kernel, mka, vaibhav.hiremath, gary.bisson, hverkuil, krzk,
Peter Chen
In-Reply-To: <1483425211-14473-1-git-send-email-peter.chen@nxp.com>
The current dts describes USB HUB's property at USB controller's
entry, it is improper. The USB HUB should be the child node
under USB controller, and power sequence properties are under
it. Besides, using gpio pinctrl setting for USB2415's reset pin.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Tested-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
---
arch/arm/boot/dts/imx6qdl-udoo.dtsi | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index c96c91d..a173de2 100644
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -9,6 +9,8 @@
*
*/
+#include <dt-bindings/gpio/gpio.h>
+
/ {
aliases {
backlight = &backlight;
@@ -58,17 +60,6 @@
#address-cells = <1>;
#size-cells = <0>;
- reg_usb_h1_vbus: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_h1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
- gpio = <&gpio7 12 0>;
- };
-
reg_panel: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
@@ -188,7 +179,7 @@
pinctrl_usbh: usbhgrp {
fsl,pins = <
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
>;
};
@@ -259,9 +250,16 @@
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh>;
- vbus-supply = <®_usb_h1_vbus>;
- clocks = <&clks IMX6QDL_CLK_CKO>;
status = "okay";
+
+ usb2415: hub@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ reset-duration-us = <3000>;
+ };
};
&usdhc3 {
--
2.7.4
^ permalink raw reply related
* [PATCH 0/6] PCI/ASPM: Add PCIe L1 PM substate support
From: Rajat Jain @ 2017-01-03 6:34 UTC (permalink / raw)
To: Bjorn Helgaas, Keith Busch, Andreas Ziegler, Jonathan Yong,
Shawn Lin, David Daney, Julia Lawall, Ram Amrani, Doug Ledford,
Wang Sheng-Hui, linux-pci, linux-kernel
Cc: Rajat Jain, Rajat Jain, Brian Norris
This patchset adds the PCIe L1 PM substate support to the kernel.
The feature is described at:
https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf
Its all logically one patch (and may be some of them should be
squashed later) , but I've broken down into smaller patches for
ease of review.
This is currently rebased on top of Bjorn's master branch.
Rajat Jain (6):
PCI: Add L1 substate capability structure register definitions
PCI/ASPM: Introduce L1 substates and a Kconfig for it
PCI/ASPM: Read and setup L1 substate capabilities
PCI/ASPM: Calculate and save the L1.2 timing parameters
PCI/ASPM: Actually configure the L1 substate settings to the device
PCI/ASPM: Add comment about L1 substate latency
drivers/pci/pcie/Kconfig | 8 ++
drivers/pci/pcie/aspm.c | 291 ++++++++++++++++++++++++++++++++++++++++--
include/uapi/linux/pci_regs.h | 16 +++
3 files changed, 302 insertions(+), 13 deletions(-)
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply
* [PATCH 4/8] usb: core: add power sequence handling for USB devices
From: Peter Chen @ 2017-01-03 6:33 UTC (permalink / raw)
To: gregkh, stern, ulf.hansson, broonie, sre, robh+dt, shawnguo, rjw,
dbaryshkov
Cc: heiko, linux-arm-kernel, p.zabel, devicetree, pawel.moll,
mark.rutland, linux-usb, arnd, s.hauer, mail, troy.kisky,
festevam, oscar, stephen.boyd, linux-pm, stillcompiling,
linux-kernel, mka, vaibhav.hiremath, gary.bisson, hverkuil, krzk,
Peter Chen
In-Reply-To: <1483425211-14473-1-git-send-email-peter.chen@nxp.com>
Some hard-wired USB devices need to do power sequence to let the
device work normally, the typical power sequence like: enable USB
PHY clock, toggle reset pin, etc. But current Linux USB driver
lacks of such code to do it, it may cause some hard-wired USB devices
works abnormal or can't be recognized by controller at all.
In this patch, it calls power sequence library APIs to finish
the power sequence events. It will do power on sequence at hub's
probe for all devices under this hub (includes root hub).
At hub_disconnect, it will do power off sequence which is at powered
on list.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Tested-by Joshua Clayton <stillcompiling@gmail.com>
Tested-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Reviewed-by: Vaibhav Hiremath <hvaibhav.linux@gmail.com>
---
drivers/usb/Kconfig | 1 +
drivers/usb/core/hub.c | 48 ++++++++++++++++++++++++++++++++++++++++++++----
drivers/usb/core/hub.h | 1 +
3 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index fbe493d..706f261 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -40,6 +40,7 @@ config USB
tristate "Support for Host-side USB"
depends on USB_ARCH_HAS_HCD
select USB_COMMON
+ select POWER_SEQUENCE
select NLS # for UTF-8 strings
---help---
Universal Serial Bus (USB) is a specification for a serial bus
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 1fa5c0f..cec2fad 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -28,6 +28,7 @@
#include <linux/mutex.h>
#include <linux/random.h>
#include <linux/pm_qos.h>
+#include <linux/power/pwrseq.h>
#include <linux/uaccess.h>
#include <asm/byteorder.h>
@@ -1645,6 +1646,7 @@ static void hub_disconnect(struct usb_interface *intf)
hub->error = 0;
hub_quiesce(hub, HUB_DISCONNECT);
+ of_pwrseq_off_list(&hub->pwrseq_on_list);
mutex_lock(&usb_port_peer_mutex);
/* Avoid races with recursively_mark_NOTATTACHED() */
@@ -1672,12 +1674,41 @@ static void hub_disconnect(struct usb_interface *intf)
kref_put(&hub->kref, hub_release);
}
+#ifdef CONFIG_OF
+static int hub_of_pwrseq_on(struct usb_hub *hub)
+{
+ struct device *parent;
+ struct usb_device *hdev = hub->hdev;
+ struct device_node *np;
+ int ret;
+
+ if (hdev->parent)
+ parent = &hdev->dev;
+ else
+ parent = bus_to_hcd(hdev->bus)->self.controller;
+
+ for_each_child_of_node(parent->of_node, np) {
+ ret = of_pwrseq_on_list(np, &hub->pwrseq_on_list);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#else
+static int hub_of_pwrseq_on(struct usb_hub *hub)
+{
+ return 0;
+}
+#endif
+
static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
{
struct usb_host_interface *desc;
struct usb_endpoint_descriptor *endpoint;
struct usb_device *hdev;
struct usb_hub *hub;
+ int ret = -ENODEV;
desc = intf->cur_altsetting;
hdev = interface_to_usbdev(intf);
@@ -1782,6 +1813,7 @@ static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
INIT_DELAYED_WORK(&hub->leds, led_work);
INIT_DELAYED_WORK(&hub->init_work, NULL);
INIT_WORK(&hub->events, hub_event);
+ INIT_LIST_HEAD(&hub->pwrseq_on_list);
usb_get_intf(intf);
usb_get_dev(hdev);
@@ -1795,11 +1827,14 @@ static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
if (id->driver_info & HUB_QUIRK_CHECK_PORT_AUTOSUSPEND)
hub->quirk_check_port_auto_suspend = 1;
- if (hub_configure(hub, endpoint) >= 0)
- return 0;
+ if (hub_configure(hub, endpoint) >= 0) {
+ ret = hub_of_pwrseq_on(hub);
+ if (!ret)
+ return 0;
+ }
hub_disconnect(intf);
- return -ENODEV;
+ return ret;
}
static int
@@ -3613,14 +3648,19 @@ static int hub_suspend(struct usb_interface *intf, pm_message_t msg)
/* stop hub_wq and related activity */
hub_quiesce(hub, HUB_SUSPEND);
- return 0;
+ return pwrseq_suspend_list(&hub->pwrseq_on_list);
}
static int hub_resume(struct usb_interface *intf)
{
struct usb_hub *hub = usb_get_intfdata(intf);
+ int ret;
dev_dbg(&intf->dev, "%s\n", __func__);
+ ret = pwrseq_resume_list(&hub->pwrseq_on_list);
+ if (ret)
+ return ret;
+
hub_activate(hub, HUB_RESUME);
return 0;
}
diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h
index 34c1a7e..cd86f91 100644
--- a/drivers/usb/core/hub.h
+++ b/drivers/usb/core/hub.h
@@ -78,6 +78,7 @@ struct usb_hub {
struct delayed_work init_work;
struct work_struct events;
struct usb_port **ports;
+ struct list_head pwrseq_on_list; /* powered pwrseq node list */
};
/**
--
2.7.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.