* Re: [PATCH] virtio_blk: avoid DMA to stack for the sense buffer
From: Jason Wang @ 2017-01-04 7:44 UTC (permalink / raw)
To: Christoph Hellwig, axboe, mst; +Cc: linux-block, linux-kernel, virtualization
In-Reply-To: <1483507505-26797-2-git-send-email-hch@lst.de>
On 2017年01月04日 13:25, Christoph Hellwig wrote:
> Most users of BLOCK_PC requests allocate the sense buffer on the stack,
> so to avoid DMA to the stack copy them to a field in the heap allocated
> virtblk_req structure. Without that any attempt at SCSI passthrough I/O,
> including the SG_IO ioctl from userspace will crash the kernel. Note that
> this includes running tools like hdparm even when the host does not have
> SCSI passthrough enabled.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> drivers/block/virtio_blk.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c
> index 5545a67..3c3b8f6 100644
> --- a/drivers/block/virtio_blk.c
> +++ b/drivers/block/virtio_blk.c
> @@ -56,6 +56,7 @@ struct virtblk_req {
> struct virtio_blk_outhdr out_hdr;
> struct virtio_scsi_inhdr in_hdr;
> u8 status;
> + u8 sense[SCSI_SENSE_BUFFERSIZE];
> struct scatterlist sg[];
> };
>
> @@ -102,7 +103,8 @@ static int __virtblk_add_req(struct virtqueue *vq,
> }
>
> if (type == cpu_to_virtio32(vq->vdev, VIRTIO_BLK_T_SCSI_CMD)) {
> - sg_init_one(&sense, vbr->req->sense, SCSI_SENSE_BUFFERSIZE);
> + memcpy(vbr->sense, vbr->req->sense, SCSI_SENSE_BUFFERSIZE);
> + sg_init_one(&sense, vbr->sense, SCSI_SENSE_BUFFERSIZE);
> sgs[num_out + num_in++] = &sense;
> sg_init_one(&inhdr, &vbr->in_hdr, sizeof(vbr->in_hdr));
> sgs[num_out + num_in++] = &inhdr;
Acked-by: Jason Wang <jasowang@redhat.com>
_______________________________________________
Virtualization mailing list
Virtualization@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/virtualization
^ permalink raw reply
* Re: [PATCH] virtio_blk: avoid DMA to stack for the sense buffer
From: Jason Wang @ 2017-01-04 7:44 UTC (permalink / raw)
To: Christoph Hellwig, axboe, mst; +Cc: linux-block, virtualization, linux-kernel
In-Reply-To: <1483507505-26797-2-git-send-email-hch@lst.de>
On 2017年01月04日 13:25, Christoph Hellwig wrote:
> Most users of BLOCK_PC requests allocate the sense buffer on the stack,
> so to avoid DMA to the stack copy them to a field in the heap allocated
> virtblk_req structure. Without that any attempt at SCSI passthrough I/O,
> including the SG_IO ioctl from userspace will crash the kernel. Note that
> this includes running tools like hdparm even when the host does not have
> SCSI passthrough enabled.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> drivers/block/virtio_blk.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c
> index 5545a67..3c3b8f6 100644
> --- a/drivers/block/virtio_blk.c
> +++ b/drivers/block/virtio_blk.c
> @@ -56,6 +56,7 @@ struct virtblk_req {
> struct virtio_blk_outhdr out_hdr;
> struct virtio_scsi_inhdr in_hdr;
> u8 status;
> + u8 sense[SCSI_SENSE_BUFFERSIZE];
> struct scatterlist sg[];
> };
>
> @@ -102,7 +103,8 @@ static int __virtblk_add_req(struct virtqueue *vq,
> }
>
> if (type == cpu_to_virtio32(vq->vdev, VIRTIO_BLK_T_SCSI_CMD)) {
> - sg_init_one(&sense, vbr->req->sense, SCSI_SENSE_BUFFERSIZE);
> + memcpy(vbr->sense, vbr->req->sense, SCSI_SENSE_BUFFERSIZE);
> + sg_init_one(&sense, vbr->sense, SCSI_SENSE_BUFFERSIZE);
> sgs[num_out + num_in++] = &sense;
> sg_init_one(&inhdr, &vbr->in_hdr, sizeof(vbr->in_hdr));
> sgs[num_out + num_in++] = &inhdr;
Acked-by: Jason Wang <jasowang@redhat.com>
^ permalink raw reply
* Re: [Lsf-pc] [LSF/MM ATTEND AND AGENDA TOPIC] request to attend the summit
From: Jan Kara @ 2017-01-04 7:41 UTC (permalink / raw)
To: Paolo Valente
Cc: Bart Van Assche, linux-block@vger.kernel.org,
ulf.hansson@linaro.org, lsf-pc@lists.linux-foundation.org,
linus.walleij@linaro.org, broonie@linaro.org
In-Reply-To: <AB3AF3AB-B6BC-47E7-A67D-793411F46B31@linaro.org>
On Tue 03-01-17 18:23:17, Paolo Valente wrote:
>
> > Il giorno 03 gen 2017, alle ore 13:00, Bart Van Assche <bart.vanassche@sandisk.com> ha scritto:
> >
> > On Tue, 2017-01-03 at 10:39 +0100, Paolo Valente wrote:
> >> In this respect, I hope that the committee does not meet too soon.
> >
> > Hello Paolo,
> >
>
> Hi
>
> > I don't know when the program committee will meet. However, what I
> > remember from previous editions of the LSF/MM is that changes of the
> > agenda happened not only during the weeks before the LSF/MM but even
> > during the LSF/MM.
> >
>
> That would be perfectly fine. The only piece of information that I
> would need in advance is whether my request to attend is accepted, so
> that I can organize my travel and really participate.
We certainly notify selected people (and also rejected ones) enough in
advance.
Honza
--
Jan Kara <jack@suse.com>
SUSE Labs, CR
^ permalink raw reply
* Re: [PATCH v2 1/1] remoteproc: core: probe subdevices before booting coprocessor
From: Patrice Chotard @ 2017-01-04 7:40 UTC (permalink / raw)
To: Loic Pallardy, bjorn.andersson, ohad, lee.jones; +Cc: linux-remoteproc, kernel
In-Reply-To: <1481143768-16377-1-git-send-email-loic.pallardy@st.com>
On 12/07/2016 09:49 PM, Loic Pallardy wrote:
> With subdevice support introduction, coprocessor boot sequence has
> changed. Related coprocessor subdevices are now starting after firmware
> and resource table loading and coprocessor boot.
>
> But some subdevices can resources to allocate before coprocessor start,
> like rpmsg buffers allocation for example.
>
> This patch probes subdevices just before loading resource table,
> to keep backward compatibility with existing firmwares.
>
> Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
> ---
> v2: remove unused stop_rproc label
>
> drivers/remoteproc/remoteproc_core.c | 18 ++++++++----------
> 1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
> index f0f6ec1..61f06a7 100644
> --- a/drivers/remoteproc/remoteproc_core.c
> +++ b/drivers/remoteproc/remoteproc_core.c
> @@ -913,6 +913,14 @@ static int rproc_fw_boot(struct rproc *rproc, const struct firmware *fw)
> goto clean_up_resources;
> }
>
> + /* probe any subdevices for the remote processor */
> + ret = rproc_probe_subdevices(rproc);
> + if (ret) {
> + dev_err(dev, "failed to probe subdevices for %s: %d\n",
> + rproc->name, ret);
> + goto clean_up_resources;
> + }
> +
> /*
> * The starting device has been given the rproc->table_ptr as the
> * resource table. The address of the vring along with the other
> @@ -932,22 +940,12 @@ static int rproc_fw_boot(struct rproc *rproc, const struct firmware *fw)
> goto clean_up_resources;
> }
>
> - /* probe any subdevices for the remote processor */
> - ret = rproc_probe_subdevices(rproc);
> - if (ret) {
> - dev_err(dev, "failed to probe subdevices for %s: %d\n",
> - rproc->name, ret);
> - goto stop_rproc;
> - }
> -
> rproc->state = RPROC_RUNNING;
>
> dev_info(dev, "remote processor %s is now up\n", rproc->name);
>
> return 0;
>
> -stop_rproc:
> - rproc->ops->stop(rproc);
> clean_up_resources:
> rproc_resource_cleanup(rproc);
> clean_up:
>
Hi Loic
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Patrice
^ permalink raw reply
* Re: [PATCH v1 0/3] remoteproc: st: add virtio_rpmsg support
From: Patrice Chotard @ 2017-01-04 7:40 UTC (permalink / raw)
To: Loic Pallardy, bjorn.andersson, ohad, lee.jones; +Cc: linux-remoteproc, kernel
In-Reply-To: <1481142826-15528-1-git-send-email-loic.pallardy@st.com>
On 12/07/2016 09:33 PM, Loic Pallardy wrote:
> Goal of this series is:
> - to add vring based communication link (virtio_rpmsg)
> - to add rproc_da_to_va translation function to allow firmware loading in
> pre-reserved carveout memory region
>
> Loic Pallardy (3):
> remoteproc: st: add virtio communication support
> remoteproc: st: add da to va support
> remoteproc: core: don't allocate carveout if pa or da are defined
>
> drivers/remoteproc/Kconfig | 3 +
> drivers/remoteproc/remoteproc_core.c | 5 ++
> drivers/remoteproc/st_remoteproc.c | 161 +++++++++++++++++++++++++++++++++--
> 3 files changed, 163 insertions(+), 6 deletions(-)
>
Hi Loic
For the entire series
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Patrice
^ permalink raw reply
* [RFC 0/4] net-next: dsa: add support for multiple cpu ports
From: John Crispin @ 2017-01-04 7:38 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Florian Fainelli, Vivien Didelot
Cc: netdev, John Crispin
This series is based on work from Andrew. I have rebased his patches to
work on the latest kernel. The main problem is probably the fact that the
cpu port to user port mapping happens inside the devicetree.
Andrew Lunn (3):
Documentation: devicetree: add multiple cpu port DSA binding
net-next: dsa: Refactor DT probing of a switch port
net-next: dsa: Add support for multiple cpu ports.
John Crispin (1):
net-next: dsa: qca8k: add support for multiple cpu ports
Documentation/devicetree/bindings/net/dsa/dsa.txt | 67 +++++++++-
drivers/net/dsa/qca8k.c | 135 +++++++++++---------
drivers/net/dsa/qca8k.h | 2 -
include/net/dsa.h | 21 +++-
net/dsa/dsa.c | 138 +++++++++++++++------
net/dsa/dsa2.c | 36 +++++-
net/dsa/dsa_priv.h | 5 +
net/dsa/slave.c | 27 ++--
8 files changed, 317 insertions(+), 114 deletions(-)
--
1.7.10.4
^ permalink raw reply
* [RFC 3/4] net-next: dsa: Add support for multiple cpu ports.
From: John Crispin @ 2017-01-04 7:38 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Florian Fainelli, Vivien Didelot
Cc: netdev, John Crispin
In-Reply-To: <1483515484-21793-1-git-send-email-john@phrozen.org>
From: Andrew Lunn <andrew@lunn.ch>
Some boards have two CPU interfaces connected to the switch, e.g. WiFi
access points, with 1 port labeled WAN, 4 ports labeled lan1-lan4, and
two port connected to the SoC.
This patch extends DSA to allows both CPU ports to be used. The "cpu"
node in the DSA tree can now have a phandle to the host interface it
connects to. Each user port can have a phandle to a cpu port which
should be used for traffic between the port and the CPU. Thus simple
load sharing over the two CPU ports can be achieved.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
include/net/dsa.h | 21 ++++++++++++++++++++-
net/dsa/dsa2.c | 36 ++++++++++++++++++++++++++++++------
net/dsa/dsa_priv.h | 5 +++++
net/dsa/slave.c | 27 ++++++++++++++++-----------
4 files changed, 71 insertions(+), 18 deletions(-)
diff --git a/include/net/dsa.h b/include/net/dsa.h
index b122196..f68180b 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -60,6 +60,8 @@ struct dsa_chip_data {
*/
char *port_names[DSA_MAX_PORTS];
struct device_node *port_dn[DSA_MAX_PORTS];
+ struct net_device *port_ethernet[DSA_MAX_PORTS];
+ int port_cpu[DSA_MAX_PORTS];
/*
* An array of which element [a] indicates which port on this
@@ -204,7 +206,7 @@ struct dsa_switch {
static inline bool dsa_is_cpu_port(struct dsa_switch *ds, int p)
{
- return !!(ds->index == ds->dst->cpu_switch && p == ds->dst->cpu_port);
+ return !!(ds->cpu_port_mask & (1 << p));
}
static inline bool dsa_is_dsa_port(struct dsa_switch *ds, int p)
@@ -217,6 +219,11 @@ static inline bool dsa_is_port_initialized(struct dsa_switch *ds, int p)
return ds->enabled_port_mask & (1 << p) && ds->ports[p].netdev;
}
+static inline bool dsa_is_upstream_port(struct dsa_switch *ds, int p)
+{
+ return dsa_is_cpu_port(ds, p) || dsa_is_dsa_port(ds, p);
+}
+
static inline u8 dsa_upstream_port(struct dsa_switch *ds)
{
struct dsa_switch_tree *dst = ds->dst;
@@ -233,6 +240,18 @@ static inline u8 dsa_upstream_port(struct dsa_switch *ds)
return ds->rtable[dst->cpu_switch];
}
+static inline u8 dsa_port_upstream_port(struct dsa_switch *ds, int port)
+{
+ /*
+ * If this port has a specific upstream cpu port, use it,
+ * otherwise use the switch default.
+ */
+ if (ds->cd->port_cpu[port])
+ return ds->cd->port_cpu[port];
+ else
+ return dsa_upstream_port(ds);
+}
+
struct switchdev_trans;
struct switchdev_obj;
struct switchdev_obj_port_fdb;
diff --git a/net/dsa/dsa2.c b/net/dsa/dsa2.c
index 5fff951..1763cd4 100644
--- a/net/dsa/dsa2.c
+++ b/net/dsa/dsa2.c
@@ -258,7 +258,7 @@ static void dsa_cpu_port_unapply(struct device_node *port, u32 index,
{
dsa_cpu_dsa_destroy(port);
ds->cpu_port_mask &= ~BIT(index);
-
+ dev_put(ds->cd->port_ethernet[index]);
}
static int dsa_user_port_apply(struct device_node *port, u32 index,
@@ -475,6 +475,28 @@ static int dsa_cpu_parse(struct device_node *port, u32 index,
dst->rcv = dst->tag_ops->rcv;
+ dev_hold(ethernet_dev);
+ ds->cd->port_ethernet[index] = ethernet_dev;
+
+ return 0;
+}
+
+static int dsa_user_parse(struct device_node *port, u32 index,
+ struct dsa_switch *ds)
+{
+ struct device_node *cpu_port;
+ const unsigned int *cpu_port_reg;
+ int cpu_port_index;
+
+ cpu_port = of_parse_phandle(port, "cpu", 0);
+ if (cpu_port) {
+ cpu_port_reg = of_get_property(cpu_port, "reg", NULL);
+ if (!cpu_port_reg)
+ return -EINVAL;
+ cpu_port_index = be32_to_cpup(cpu_port_reg);
+ ds->cd->port_cpu[index] = cpu_port_index;
+ }
+
return 0;
}
@@ -482,18 +504,20 @@ static int dsa_ds_parse(struct dsa_switch_tree *dst, struct dsa_switch *ds)
{
struct device_node *port;
u32 index;
- int err;
+ int err = 0;
for (index = 0; index < DSA_MAX_PORTS; index++) {
port = ds->ports[index].dn;
if (!port)
continue;
- if (dsa_port_is_cpu(port)) {
+ if (dsa_port_is_cpu(port))
err = dsa_cpu_parse(port, index, dst, ds);
- if (err)
- return err;
- }
+ else if (!dsa_port_is_dsa(port))
+ err = dsa_user_parse(port, index, ds);
+
+ if (err)
+ return err;
}
pr_info("DSA: switch %d %d parsed\n", dst->tree, ds->index);
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 6cfd738..7e1e62c 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -24,6 +24,11 @@ struct dsa_device_ops {
struct dsa_slave_priv {
struct sk_buff * (*xmit)(struct sk_buff *skb,
struct net_device *dev);
+ /*
+ * Which host device do we used to send packets to the switch
+ * for this port.
+ */
+ struct net_device *master;
/*
* Which switch this port is a part of, and the port index
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index ffd91969..260d4a9 100644
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -61,7 +61,7 @@ static int dsa_slave_get_iflink(const struct net_device *dev)
{
struct dsa_slave_priv *p = netdev_priv(dev);
- return p->parent->dst->master_netdev->ifindex;
+ return p->master->ifindex;
}
static inline bool dsa_port_is_bridged(struct dsa_slave_priv *p)
@@ -96,7 +96,7 @@ static void dsa_port_set_stp_state(struct dsa_switch *ds, int port, u8 state)
static int dsa_slave_open(struct net_device *dev)
{
struct dsa_slave_priv *p = netdev_priv(dev);
- struct net_device *master = p->parent->dst->master_netdev;
+ struct net_device *master = p->master;
struct dsa_switch *ds = p->parent;
u8 stp_state = dsa_port_is_bridged(p) ?
BR_STATE_BLOCKING : BR_STATE_FORWARDING;
@@ -151,7 +151,7 @@ static int dsa_slave_open(struct net_device *dev)
static int dsa_slave_close(struct net_device *dev)
{
struct dsa_slave_priv *p = netdev_priv(dev);
- struct net_device *master = p->parent->dst->master_netdev;
+ struct net_device *master = p->master;
struct dsa_switch *ds = p->parent;
if (p->phy)
@@ -178,7 +178,7 @@ static int dsa_slave_close(struct net_device *dev)
static void dsa_slave_change_rx_flags(struct net_device *dev, int change)
{
struct dsa_slave_priv *p = netdev_priv(dev);
- struct net_device *master = p->parent->dst->master_netdev;
+ struct net_device *master = p->master;
if (change & IFF_ALLMULTI)
dev_set_allmulti(master, dev->flags & IFF_ALLMULTI ? 1 : -1);
@@ -189,7 +189,7 @@ static void dsa_slave_change_rx_flags(struct net_device *dev, int change)
static void dsa_slave_set_rx_mode(struct net_device *dev)
{
struct dsa_slave_priv *p = netdev_priv(dev);
- struct net_device *master = p->parent->dst->master_netdev;
+ struct net_device *master = p->master;
dev_mc_sync(master, dev);
dev_uc_sync(master, dev);
@@ -198,7 +198,7 @@ static void dsa_slave_set_rx_mode(struct net_device *dev)
static int dsa_slave_set_mac_address(struct net_device *dev, void *a)
{
struct dsa_slave_priv *p = netdev_priv(dev);
- struct net_device *master = p->parent->dst->master_netdev;
+ struct net_device *master = p->master;
struct sockaddr *addr = a;
int err;
@@ -633,7 +633,7 @@ static netdev_tx_t dsa_slave_xmit(struct sk_buff *skb, struct net_device *dev)
/* Queue the SKB for transmission on the parent interface, but
* do not modify its EtherType
*/
- nskb->dev = p->parent->dst->master_netdev;
+ nskb->dev = p->master;
dev_queue_xmit(nskb);
return NETDEV_TX_OK;
@@ -947,7 +947,7 @@ static int dsa_slave_netpoll_setup(struct net_device *dev,
{
struct dsa_slave_priv *p = netdev_priv(dev);
struct dsa_switch *ds = p->parent;
- struct net_device *master = ds->dst->master_netdev;
+ struct net_device *master = p->master;
struct netpoll *netpoll;
int err = 0;
@@ -1247,12 +1247,16 @@ int dsa_slave_create(struct dsa_switch *ds, struct device *parent,
struct net_device *master;
struct net_device *slave_dev;
struct dsa_slave_priv *p;
+ int port_cpu = ds->cd->port_cpu[port];
int ret;
- master = ds->dst->master_netdev;
- if (ds->master_netdev)
+ if (port_cpu && ds->cd->port_ethernet[port_cpu])
+ master = ds->cd->port_ethernet[port_cpu];
+ else if (ds->master_netdev)
master = ds->master_netdev;
-
+ else
+ master = ds->dst->master_netdev;
+ master->dsa_ptr = (void *)ds->dst;
slave_dev = alloc_netdev(sizeof(struct dsa_slave_priv), name,
NET_NAME_UNKNOWN, ether_setup);
if (slave_dev == NULL)
@@ -1279,6 +1283,7 @@ int dsa_slave_create(struct dsa_switch *ds, struct device *parent,
p->parent = ds;
p->port = port;
p->xmit = dst->tag_ops->xmit;
+ p->master = master;
p->old_pause = -1;
p->old_link = -1;
--
1.7.10.4
^ permalink raw reply related
* [RFC 4/4] net-next: dsa: qca8k: add support for multiple cpu ports
From: John Crispin @ 2017-01-04 7:38 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Florian Fainelli, Vivien Didelot
Cc: netdev, John Crispin
In-Reply-To: <1483515484-21793-1-git-send-email-john@phrozen.org>
With the subsystem now supporting multiple cpu ports, we need to make some
changes to the driver as it currently has the cpu port hardcoded as port0.
The patch moves the setup logic for the cpu port into one loop which
iterates over all cpu ports and sets them up. Additionally the bridge
join/leave logic needs a small fix to work with having a cpu port other
than 0.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/dsa/qca8k.c | 135 +++++++++++++++++++++++++++--------------------
drivers/net/dsa/qca8k.h | 2 -
2 files changed, 78 insertions(+), 59 deletions(-)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index b3df70d..1693388 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -486,11 +486,25 @@
qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
}
+static void
+qca8k_setup_flooding(struct qca8k_priv *priv, int port_mask, int enable)
+{
+ u32 mask = (port_mask << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S) |
+ (port_mask << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S) |
+ (port_mask << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S) |
+ (port_mask << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
+
+ if (enable)
+ qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL1, mask);
+ else
+ qca8k_reg_clear(priv, QCA8K_REG_GLOBAL_FW_CTRL1, mask);
+}
+
static int
qca8k_setup(struct dsa_switch *ds)
{
struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
- int ret, i, phy_mode = -1;
+ int ret, i;
/* Make sure that port 0 is the cpu port */
if (!dsa_is_cpu_port(ds, 0)) {
@@ -506,29 +520,49 @@
if (IS_ERR(priv->regmap))
pr_warn("regmap initialization failed");
- /* Initialize CPU port pad mode (xMII type, delays...) */
- phy_mode = of_get_phy_mode(ds->ports[ds->dst->cpu_port].dn);
- if (phy_mode < 0) {
- pr_err("Can't find phy-mode for master device\n");
- return phy_mode;
- }
- ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
- if (ret < 0)
- return ret;
-
- /* Enable CPU Port */
+ /* Tell the switch that port0 is a cpu port */
qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
- qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
- priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
/* Enable MIB counters */
qca8k_mib_init(priv);
- /* Enable QCA header mode on the cpu port */
- qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
+ /* Setup the cpu ports */
+ for (i = 0; i < DSA_MAX_PORTS; i++) {
+ struct net_device *netdev;
+ int phy_mode = -1;
+
+ if (!dsa_is_cpu_port(ds, i))
+ continue;
+
+ netdev = ds->dst->pd->chip->port_ethernet[i];
+ if (!netdev) {
+ pr_err("Can't find netdev for port%d\n", i);
+ return -ENODEV;
+ }
+
+ /* Initialize CPU port pad mode (xMII type, delays...) */
+ phy_mode = of_get_phy_mode(netdev->dev.parent->of_node);
+ if (phy_mode < 0) {
+ pr_err("Can't find phy-mode for port:%d\n", i);
+ return phy_mode;
+ }
+ ret = qca8k_set_pad_ctrl(priv, i, phy_mode);
+ if (ret < 0)
+ return ret;
+
+ /* Enable QCA header mode on the cpu port */
+ qca8k_write(priv,
+ QCA8K_REG_PORT_HDR_CTRL(i),
+ QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
+ QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
+
+ qca8k_port_set_status(priv, i, 1);
+ priv->port_sts[i].enabled = 1;
+
+ /* Forward all unknown frames to CPU port for Linux processing */
+ qca8k_setup_flooding(priv, BIT(i), 1);
+ }
/* Disable forwarding by default on all ports */
for (i = 0; i < QCA8K_NUM_PORTS; i++)
@@ -540,43 +574,30 @@
if (ds->enabled_port_mask & BIT(i))
qca8k_port_set_status(priv, i, 0);
- /* Forward all unknown frames to CPU port for Linux processing */
- qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
-
- /* Setup connection between CPU port & user ports */
+ /* Setup user ports and connections to CPU ports */
for (i = 0; i < DSA_MAX_PORTS; i++) {
- /* CPU port gets connected to all user ports of the switch */
- if (dsa_is_cpu_port(ds, i)) {
- qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
- QCA8K_PORT_LOOKUP_MEMBER,
- ds->enabled_port_mask);
- }
+ int shift = 16 * (i % 2);
+ int cpu_port;
- /* Invividual user ports get connected to CPU port only */
- if (ds->enabled_port_mask & BIT(i)) {
- int shift = 16 * (i % 2);
-
- qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
- QCA8K_PORT_LOOKUP_MEMBER,
- BIT(QCA8K_CPU_PORT));
-
- /* Enable ARP Auto-learning by default */
- qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
- QCA8K_PORT_LOOKUP_LEARN);
-
- /* For port based vlans to work we need to set the
- * default egress vid
- */
- qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
- 0xffff << shift, 1 << shift);
- qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
- QCA8K_PORT_VLAN_CVID(1) |
- QCA8K_PORT_VLAN_SVID(1));
- }
+ if (!(ds->enabled_port_mask & BIT(i)))
+ continue;
+
+ cpu_port = dsa_port_upstream_port(ds, i);
+ qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), BIT(cpu_port));
+ qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port), BIT(i));
+
+ /* Enable ARP Auto-learning by default */
+ qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
+ QCA8K_PORT_LOOKUP_LEARN);
+
+ /* For port based vlans to work we need to set the
+ * default egress vid
+ */
+ qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
+ 0xffff << shift, 1 << shift);
+ qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
+ QCA8K_PORT_VLAN_CVID(1) |
+ QCA8K_PORT_VLAN_SVID(1));
}
/* Flush the FDB table */
@@ -750,7 +771,7 @@
struct net_device *bridge)
{
struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
- int port_mask = BIT(QCA8K_CPU_PORT);
+ int port_mask = 0;
int i;
priv->port_sts[port].bridge_dev = bridge;
@@ -768,8 +789,7 @@
port_mask |= BIT(i);
}
/* Add all other ports to this ports portvlan mask */
- qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
- QCA8K_PORT_LOOKUP_MEMBER, port_mask);
+ qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(port), port_mask);
return 0;
}
@@ -796,7 +816,8 @@
* this port
*/
qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
- QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
+ QCA8K_PORT_LOOKUP_MEMBER,
+ BIT(dsa_port_upstream_port(ds, i)));
}
static int
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 2014647..aca6abb 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -26,8 +26,6 @@
#define QCA8K_NUM_FDB_RECORDS 2048
-#define QCA8K_CPU_PORT 0
-
/* Global control registers */
#define QCA8K_REG_MASK_CTRL 0x000
#define QCA8K_MASK_CTRL_ID_M 0xff
--
1.7.10.4
^ permalink raw reply related
* [RFC 2/4] net-next: dsa: Refactor DT probing of a switch port
From: John Crispin @ 2017-01-04 7:38 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Florian Fainelli, Vivien Didelot; +Cc: netdev
In-Reply-To: <1483515484-21793-1-git-send-email-john@phrozen.org>
From: Andrew Lunn <andrew@lunn.ch>
Move the DT probing of a switch port into a function of its own, since
it is about to get more complex. Add better error handling as well.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
net/dsa/dsa.c | 138 ++++++++++++++++++++++++++++++++++++++++++---------------
1 file changed, 102 insertions(+), 36 deletions(-)
diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
index 7899919..0e0621c 100644
--- a/net/dsa/dsa.c
+++ b/net/dsa/dsa.c
@@ -326,14 +326,10 @@ static int dsa_switch_setup_one(struct dsa_switch *ds, struct device *parent)
continue;
if (!strcmp(name, "cpu")) {
- if (dst->cpu_switch != -1) {
- netdev_err(dst->master_netdev,
- "multiple cpu ports?!\n");
- ret = -EINVAL;
- goto out;
+ if (dst->cpu_switch == -1) {
+ dst->cpu_switch = index;
+ dst->cpu_port = i;
}
- dst->cpu_switch = index;
- dst->cpu_port = i;
ds->cpu_port_mask |= 1 << i;
} else if (!strcmp(name, "dsa")) {
ds->dsa_port_mask |= 1 << i;
@@ -709,11 +705,15 @@ static void dsa_of_free_platform_data(struct dsa_platform_data *pd)
{
int i;
int port_index;
+ struct dsa_chip_data *cd;
for (i = 0; i < pd->nr_chips; i++) {
+ cd = &pd->chip[i];
port_index = 0;
while (port_index < DSA_MAX_PORTS) {
- kfree(pd->chip[i].port_names[port_index]);
+ kfree(cd->port_names[port_index]);
+ if (cd->port_ethernet[port_index])
+ dev_put(cd->port_ethernet[port_index]);
port_index++;
}
@@ -724,6 +724,94 @@ static void dsa_of_free_platform_data(struct dsa_platform_data *pd)
kfree(pd->chip);
}
+static int dsa_of_probe_cpu_port(struct dsa_chip_data *cd,
+ struct device_node *port,
+ int port_index)
+{
+ struct net_device *ethernet_dev;
+ struct device_node *ethernet;
+
+ ethernet = of_parse_phandle(port, "ethernet", 0);
+ if (ethernet) {
+ ethernet_dev = of_find_net_device_by_node(ethernet);
+ if (!ethernet_dev)
+ return -EPROBE_DEFER;
+
+ dev_hold(ethernet_dev);
+ cd->port_ethernet[port_index] = ethernet_dev;
+ }
+
+ return 0;
+}
+
+static int dsa_of_probe_user_port(struct dsa_chip_data *cd,
+ struct device_node *port,
+ int port_index)
+{
+ struct device_node *cpu_port;
+ const unsigned int *cpu_port_reg;
+ int cpu_port_index;
+
+ cpu_port = of_parse_phandle(port, "cpu", 0);
+ if (cpu_port) {
+ cpu_port_reg = of_get_property(cpu_port, "reg", NULL);
+ if (!cpu_port_reg)
+ return -EINVAL;
+ cpu_port_index = be32_to_cpup(cpu_port_reg);
+ cd->port_cpu[port_index] = cpu_port_index;
+ }
+
+ return 0;
+}
+
+static int dsa_of_probe_port(struct dsa_platform_data *pd,
+ struct dsa_chip_data *cd,
+ int chip_index,
+ struct device_node *port)
+{
+ bool is_cpu_port = false, is_dsa_port = false;
+ bool is_user_port = false;
+ const unsigned int *port_reg;
+ const char *port_name;
+ int port_index, ret = 0;
+
+ port_reg = of_get_property(port, "reg", NULL);
+ if (!port_reg)
+ return -EINVAL;
+
+ port_index = be32_to_cpup(port_reg);
+
+ port_name = of_get_property(port, "label", NULL);
+ if (!port_name)
+ return -EINVAL;
+
+ if (!strcmp(port_name, "cpu"))
+ is_cpu_port = true;
+ if (!strcmp(port_name, "dsa"))
+ is_dsa_port = true;
+ if (!is_cpu_port && !is_dsa_port)
+ is_user_port = true;
+
+ cd->port_dn[port_index] = port;
+
+ cd->port_names[port_index] = kstrdup(port_name,
+ GFP_KERNEL);
+ if (!cd->port_names[port_index])
+ return -ENOMEM;
+
+ if (is_dsa_port)
+ ret = dsa_of_probe_links(pd, cd, chip_index,
+ port_index, port, port_name);
+ if (is_cpu_port)
+ ret = dsa_of_probe_cpu_port(cd, port, port_index);
+ if (is_user_port)
+ ret = dsa_of_probe_user_port(cd, port, port_index);
+ if (ret)
+ return ret;
+
+ return port_index;
+}
+
static int dsa_of_probe(struct device *dev)
{
struct device_node *np = dev->of_node;
@@ -732,9 +820,8 @@ static int dsa_of_probe(struct device *dev)
struct net_device *ethernet_dev;
struct dsa_platform_data *pd;
struct dsa_chip_data *cd;
- const char *port_name;
- int chip_index, port_index;
- const unsigned int *sw_addr, *port_reg;
+ int chip_index;
+ const unsigned int *sw_addr;
u32 eeprom_len;
int ret;
@@ -821,32 +908,11 @@ static int dsa_of_probe(struct device *dev)
}
for_each_available_child_of_node(child, port) {
- port_reg = of_get_property(port, "reg", NULL);
- if (!port_reg)
- continue;
-
- port_index = be32_to_cpup(port_reg);
- if (port_index >= DSA_MAX_PORTS)
- break;
-
- port_name = of_get_property(port, "label", NULL);
- if (!port_name)
- continue;
-
- cd->port_dn[port_index] = port;
-
- cd->port_names[port_index] = kstrdup(port_name,
- GFP_KERNEL);
- if (!cd->port_names[port_index]) {
- ret = -ENOMEM;
+ ret = dsa_of_probe_port(pd, cd, chip_index, port);
+ if (ret < 0)
goto out_free_chip;
- }
-
- ret = dsa_of_probe_links(pd, cd, chip_index,
- port_index, port, port_name);
- if (ret)
- goto out_free_chip;
-
+ if (ret == DSA_MAX_PORTS)
+ break;
}
}
--
1.7.10.4
^ permalink raw reply related
* [RFC 1/4] Documentation: devicetree: add multiple cpu port DSA binding
From: John Crispin @ 2017-01-04 7:38 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Florian Fainelli, Vivien Didelot
Cc: netdev, Rob Herring, devicetree
In-Reply-To: <1483515484-21793-1-git-send-email-john@phrozen.org>
From: Andrew Lunn <andrew@lunn.ch>
Extend the DSA binding documentation, adding the new properties required
when there is more than one CPU port attached to the switch.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
Documentation/devicetree/bindings/net/dsa/dsa.txt | 67 ++++++++++++++++++++-
1 file changed, 66 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt
index a4a570f..fc901cf 100644
--- a/Documentation/devicetree/bindings/net/dsa/dsa.txt
+++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt
@@ -337,13 +337,25 @@ Optional property:
This mii-bus will be used in preference to the
global dsa,mii-bus defined above, for this switch.
+- ethernet : Optional for "cpu" ports. A phandle to an ethernet
+ device which will be used by this CPU port for
+ passing packets to/from the host. If not present,
+ the port will use the "dsa,ethernet" property
+ defined above.
+
+- cpu : Option for non "cpu"/"dsa" ports. A phandle to a
+ "cpu" port, which will be used for passing packets
+ from this port to the host. If not present, the first
+ "cpu" port will be used.
+
+
Optional subnodes:
- fixed-link : Fixed-link subnode describing a link to a non-MDIO
managed entity. See
Documentation/devicetree/bindings/net/fixed-link.txt
for details.
-Example:
+Examples:
dsa@0 {
compatible = "marvell,dsa";
@@ -416,3 +428,56 @@ Example:
};
};
};
+
+ dsa@1 {
+ compatible = "marvell,dsa";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ dsa,ethernet = <ð0port>;
+ dsa,mii-bus = <&mdio>;
+
+ switch@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0>; /* MDIO address 0, switch 0 in tree */
+
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ cpu = <&cpu1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ cpu = <&cpu1>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ };
+
+ cpu1: port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <ð1port>;
+ };
+ };
+ };
--
1.7.10.4
^ permalink raw reply related
* Re: build failure if --with-xtables [WAS: nftables 0.7 release]
From: Arturo Borrero Gonzalez @ 2017-01-04 7:35 UTC (permalink / raw)
To: Robby Workman; +Cc: Netfilter Development Mailing list
In-Reply-To: <20170103155614.40273a5e.robby@rlworkman.net>
On 3 January 2017 at 22:56, Robby Workman <robby@rlworkman.net> wrote:
> On Tue, 20 Dec 2016 21:46:36 +0100
> Pablo Neira Ayuso <pablo@netfilter.org> wrote:
>
>> Hi!
>>
>> The Netfilter project proudly presents:
>>
>> nftables 0.7
>>
>> This release contains many accumulated bug fixes and new features
>> available up to the (upcoming) Linux 4.10-rc1 kernel release.
>>
>> * Facilitate migration from iptables to nftables:
>>
>> At compilation time, you have to pass this option.
>>
>> # ./configure --with-xtables
>
>
> I get a build failure with this option - bug filed with some details:
> https://bugzilla.netfilter.org/show_bug.cgi?id=1110
the required xlate methods of iptables have not been released so far.
They are not present in iptables 1.6.0.
^ permalink raw reply
* Re: Add ALC299 support
From: Takashi Iwai @ 2017-01-04 7:34 UTC (permalink / raw)
To: Kailang; +Cc: (alsa-devel@alsa-project.org)
In-Reply-To: <6FAB7C47BCF00940BB0999A99BE3547A17A4A4A0@RTITMBSV09.realtek.com.tw>
On Wed, 04 Jan 2017 08:09:36 +0100,
Kailang wrote:
>
> Hi Takashi,
>
> We had new codec ALC299.
> It was similar as ALC225.
> Attach was the patch.
Thanks, applied.
Takashi
^ permalink raw reply
* RE: [PATCH v2 2/3] dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdma
From: Appana Durga Kedareswara Rao @ 2017-01-04 6:57 UTC (permalink / raw)
To: Jose Abreu, dan.j.williams@intel.com, vinod.koul@intel.com,
michal.simek@xilinx.com, Soren Brinkmann,
moritz.fischer@ettus.com, laurent.pinchart@ideasonboard.com,
luis@debethencourt.com
Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <a8f5c216-cac0-daf9-a880-3820ae9b5e13@synopsys.com>
Hi Jose Miguel Abreu,
Thanks for the review...
> >> If so then there is no race condition, but the HW image that I have
> >> does not have this register enabled so I was getting this result
> >> (memory corruption because not all framebuffers had addresses set).
> > Thanks for the explanation.
> > Agree the issue that you mentioned won't come when
> > XILINX_DMA_REG_FRMSTORE
> > (C_ENABLE_DEBUG_INFO_5 and C_ENABLE_DEBUG_INFO_13) Register is
> enabled in the IP.
> > But this register won't get enabled with the default IP configuration
> (C_ENABLE_DEBUG_INFO_5 and C_ENABLE_DEBUG_INFO_13).
> >
> > When user is not enabled XILINX_DMA_REG_FRMSTORE in the h/w and
> submits frames less than h/w capable.
> > The solution that I am thinking is to throw an error in the driver
> > saying that either enable the num frame store feature in the IP or submit the
> frames up to h/w capable what do you think???
>
> Sounds fine by me.
Thanks posted the v3 series please review when you have some time...
Regards,
Kedar.
>
> Best regards,
> Jose Miguel Abreu
>
> >
> > Regards,
> > Kedar.
> >
> >> Best regards,
> >> Jose Miguel Abreu
> >>
> >>> Regards,
> >>> Kedar.
> >>>
> >>>> Best regards,
> >>>> Jose Miguel Abreu
> >>>>
^ permalink raw reply
* Re: ext4 filesystem corruption with 4.10-rc2 on ppc64le
From: luigi burdo @ 2017-01-04 7:34 UTC (permalink / raw)
To: Anton Blanchard, jack@suse.cz, Michael Ellerman,
Benjamin Herrenschmidt, Paul Mackerras, Stephen Rothwell,
axboe@fb.com
Cc: linux-fsdevel@vger.kernel.org, linux-ext4@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <20170104161808.5ad7b4fd@kryten>
[-- Attachment #1: Type: text/plain, Size: 1264 bytes --]
Hi,
it is present on ppc not le too.
found it on Ubuntu Mate 16.10 PPC with kernel 4.9 rc6 PPC64 on P5020/P5040
Thanks
Luigi
________________________________
Da: Linuxppc-dev <linuxppc-dev-bounces+intermediadc=hotmail.com@lists.ozlabs.org> per conto di Anton Blanchard <anton@samba.org>
Inviato: mercoledì 4 gennaio 2017 06.18
A: jack@suse.cz; Michael Ellerman; Benjamin Herrenschmidt; Paul Mackerras; Stephen Rothwell; axboe@fb.com
Cc: linux-fsdevel@vger.kernel.org; linux-ext4@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-kernel@vger.kernel.org
Oggetto: ext4 filesystem corruption with 4.10-rc2 on ppc64le
Hi,
I'm consistently seeing ext4 filesystem corruption using a mainline
kernel. It doesn't take much to trigger it - download a ppc64le Ubuntu
cloud image, boot it in KVM and run:
sudo apt-get update
sudo apt-get dist-upgrade
sudo reboot
And it never makes it back up, dying with rather severe filesystem
corruption.
I've narrowed it down to:
64e1c57fa474 ("ext4: Use clean_bdev_aliases() instead of iteration")
e64855c6cfaa ("fs: Add helper to clean bdev aliases under a bh and use it")
ce98321bf7d2 ("fs: Remove unmap_underlying_metadata")
Backing these patches out fixes the issue.
Anton
[-- Attachment #2: Type: text/html, Size: 2205 bytes --]
^ permalink raw reply
* [U-Boot] am335x board i2c_probe fails from nand boot
From: matti kaasinen @ 2017-01-04 7:33 UTC (permalink / raw)
To: u-boot
In-Reply-To: <5f15e470-d12f-e3ea-d393-5cb6e0c700cd@ti.com>
2017-01-04 6:46 GMT+02:00 Lokesh Vutla <lokeshvutla@ti.com>:
> > "Card did not respond to voltage select!" is coming from:
> > drivers/mmc/mmc.c
>
> Can you check if mmc mux is being done properly?
>
I think this message is coming because I have ejected mmc (sd card) in
order to boot from nand.
However, I went through include/configs/am335x_evm.h that I have patched
very moderately - ionly two changes:
1) disable card detect
2) feed own fdt file.
I noticed some nand related values that I'm not sure if they are correct. I
get following nand partition listed from mmc boot:
[ 1.230539] Creating 10 MTD partitions on "8000000.nand":
[ 1.236229] 0x000000000000-0x000000020000 : "NAND.SPL"
[ 1.243121] 0x000000020000-0x000000040000 : "NAND.SPL.backup1"
[ 1.250614] 0x000000040000-0x000000060000 : "NAND.SPL.backup2"
[ 1.258121] 0x000000060000-0x000000080000 : "NAND.SPL.backup3"
[ 1.265515] 0x000000080000-0x0000000c0000 : "NAND.u-boot-spl-os"
[ 1.273167] 0x0000000c0000-0x0000001c0000 : "NAND.u-boot"
[ 1.280890] 0x0000001c0000-0x0000001e0000 : "NAND.u-boot-env"
[ 1.288255] 0x0000001e0000-0x000000200000 : "NAND.u-boot-env.backup1"
[ 1.296430] 0x000000200000-0x000000a00000 : "NAND.kernel"
[ 1.309941] 0x000000a00000-0x000010000000 : "NAND.file-system"
In am335x_evm.h there are following definitions:
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
So, this is pointing to NAND.u-boot-spl-os, i.e os parameters in nand, not
u-boot
#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
This is pointing to NAND.SPL.backup3
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
This is pointing to NAND.u-boot-env.backup1, not kernel
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
0x2000 does not match with 0x80000 that is reserved for NAND.u-boot-spl-os
partition.
As you told, u-boot starts, so most likely these don't matter this time.
Thanks,
Matti
^ permalink raw reply
* Re: [PATCH 08/12] libmultipath: wait one seconds for more uevents in uevent_listen() in uevents burst situations
From: tang.junhui @ 2017-01-04 7:32 UTC (permalink / raw)
To: Benjamin Marzinski
Cc: tang.wenjun3, zhang.kai16, dm-devel-bounces, dm-devel,
bart.vanassche, mwilck
In-Reply-To: <20170103223106.GE2732@octiron.msp.redhat.com>
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Hello Ben,
I know the issue of socket's buffer fills up,
but I think uevent_can_discard() totally process in memory,
it is light-weight and low cpu consumption, and it reduce the
iteration count in merging, the test result is also good in
massive multipath devices scene.
But if you still stick to it, I will revert it to uevents
processing thread, and call it in uevent_dispatch() before
calling merge_uevq(), actually, I'm going to do that.
Regards
Tang Junhui
发件人: "Benjamin Marzinski" <bmarzins@redhat.com>
收件人: tang.junhui@zte.com.cn,
抄送: tang.wenjun3@zte.com.cn, zhang.kai16@zte.com.cn,
dm-devel@redhat.com, bart.vanassche@sandisk.com, mwilck@suse.com
日期: 2017/01/04 06:38
主题: Re: [dm-devel] [PATCH 08/12] libmultipath: wait one seconds for
more uevents in uevent_listen() in uevents burst situations
发件人: dm-devel-bounces@redhat.com
On Tue, Dec 27, 2016 at 04:03:25PM +0800, tang.junhui@zte.com.cn wrote:
> From: tang.junhui <tang.junhui@zte.com.cn>
>
> The more uevents are merged, the higher efficiency program will
performs.
> So, do not process uevents after receiving immediately in uevents burst
> situations, but continue wait 1 seconds for more uevents except that too
> much uevents (2048) have already been received or too much time eclipse
> (60 seconds).
The issue I have with doing this in uevent_listen is that we seperated
receiving the uevents from servicing the uevents specificially to make
sure what we received them as fast as possible. The udev monitor code
is all based on a NETLINK socket. If our socket's receive buffer fills
up, there is no flow control. Events just start getting dropped, which
does cut down on processing time, but not in a way we would like.
This issue applies to a lesser extent to you previous two patches. I
don't really see the benefit of making sure that we drop the uevents
as soon as possible. As long as we don't process them, that should
be good enough, right?
Now, maybe you put a lot of thought into your timeouts, and feel
confident that we will start processing well before the receive buffer
fills up. But if so, some comments on that would be reassuring, because
from the commit message, they seem fairly arbitrary to me.
-Ben
>
> Change-Id: I763d491540e8114a81d12d603281540a81502742
> Signed-off-by: tang.junhui <tang.junhui@zte.com.cn>
> ---
> libmultipath/uevent.c | 35 +++++++++++++++++++++++++++++++++--
> 1 file changed, 33 insertions(+), 2 deletions(-)
>
> diff --git a/libmultipath/uevent.c b/libmultipath/uevent.c
> index cc10d65..b0b05e9 100644
> --- a/libmultipath/uevent.c
> +++ b/libmultipath/uevent.c
> @@ -39,6 +39,7 @@
> #include <linux/netlink.h>
> #include <pthread.h>
> #include <sys/mman.h>
> +#include <sys/time.h>
> #include <libudev.h>
> #include <errno.h>
>
> @@ -490,11 +491,37 @@ struct uevent *uevent_from_udev_device(struct
udev_device *dev)
> return uev;
> }
>
> +bool uevent_burst(struct timeval *start_time, int events)
> +{
> + struct timeval diff_time, end_time;
> + unsigned long speed;
> + unsigned long eclipse_ms;
> +
> + gettimeofday(&end_time, NULL);
> + timersub(&end_time, start_time, &diff_time);
> +
> + eclipse_ms = diff_time.tv_sec * 1000 + diff_time.tv_usec
/ 1000;
> + if (eclipse_ms == 0)
> + return true;
> + /* max wait 60s */
> + if (eclipse_ms > 60*1000) {
> + condlog(1, "burst continued =%lu ms,
stoped", eclipse_ms);
> + return false;
> + }
> +
> + speed = (events * 1000) / eclipse_ms;
> + if (speed > 10)
> + return true;
> +
> + return false;
> +}
> +
> int uevent_listen(struct udev *udev)
> {
> int err = 2;
> struct udev_monitor *monitor = NULL;
> int fd, socket_flags, events;
> + struct timeval start_time;
> int need_failback = 1;
> int timeout = 30;
> LIST_HEAD(uevlisten_tmp);
> @@ -548,6 +575,7 @@ int uevent_listen(struct udev *udev)
> }
>
> events = 0;
> + gettimeofday(&start_time, NULL);
> while (1) {
> struct uevent *uev;
> struct udev_device *dev;
> @@ -562,7 +590,8 @@ int uevent_listen(struct udev *udev)
> errno = 0;
> fdcount = poll(&ev_poll, 1,
poll_timeout);
> if (fdcount && ev_poll.revents & POLLIN)
{
> - timeout = 0;
> + timeout =
uevent_burst(&start_time, events + 1) ? 1:0;
> +
> dev =
udev_monitor_receive_device(monitor);
> if (!dev) {
> condlog(0, "failed getting udev device");
> @@ -578,7 +607,8 @@ int uevent_listen(struct udev *udev)
> }
> list_add_tail(&uev->node,
&uevlisten_tmp);
> events++;
> - continue;
> + if(events < 2048)
> + continue;
> }
> if (fdcount < 0) {
> if (errno == EINTR)
> @@ -600,6 +630,7 @@ int uevent_listen(struct udev *udev)
> pthread_mutex_unlock(uevq_lockp);
> events = 0;
> }
> + gettimeofday(&start_time, NULL);
> timeout = 30;
> }
> need_failback = 0;
> --
> 2.8.1.windows.1
>
--
dm-devel mailing list
dm-devel@redhat.com
https://www.redhat.com/mailman/listinfo/dm-devel
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^ permalink raw reply
* Re: bootx_init.c:88: undefined reference to `__stack_chk_fail_local'
From: Christophe LEROY @ 2017-01-04 7:32 UTC (permalink / raw)
To: Christian Kujau; +Cc: Michael Ellerman, linuxppc-dev
In-Reply-To: <alpine.DEB.2.20.99.1701030715390.31470@trent.utfs.org>
Le 03/01/2017 à 16:25, Christian Kujau a écrit :
> Hi,
>
> when compiling v4.10-rc2 with CONFIG_CC_STACKPROTECTOR_STRONG=y, the
> linker fails with:
>
> ================================
> + ld -EB -m elf32ppc -Bstatic --build-id -X -o .tmp_vmlinux1 -T
> ./arch/powerpc/kernel/vmlinux.lds arch/powerpc/kernel/head_32.o
> arch/powerpc/kernel/fpu.o arch/powerpc/kernel/vector.o
> arch/powerpc/kernel/prom_init.o init/built-in.o --start-group
> usr/built-in.o arch/powerpc/kernel/built-in.o arch/powerpc/mm/built-in.o
> arch/powerpc/lib/built-in.o arch/powerpc/sysdev/built-in.o
> arch/powerpc/platforms/built-in.o arch/powerpc/math-emu/built-in.o
> arch/powerpc/crypto/built-in.o arch/powerpc/net/built-in.o
> kernel/built-in.o certs/built-in.o mm/built-in.o fs/built-in.o
> ipc/built-in.o security/built-in.o crypto/built-in.o block/built-in.o
> lib/lib.a lib/built-in.o drivers/built-in.o sound/built-in.o
> firmware/built-in.o net/built-in.o virt/built-in.o --end-group
> arch/powerpc/platforms/built-in.o: In function `bootx_printf':
> /usr/local/src/linux-git/arch/powerpc/platforms/powermac/bootx_init.c:88: undefined reference to `__stack_chk_fail_local'
> arch/powerpc/platforms/built-in.o: In function `bootx_add_display_props':
> /usr/local/src/linux-git/arch/powerpc/platforms/powermac/bootx_init.c:211: undefined reference to `__stack_chk_fail_local'
> arch/powerpc/platforms/built-in.o: In function
> `bootx_scan_dt_build_struct':
> /usr/local/src/linux-git/arch/powerpc/platforms/powermac/bootx_init.c:350: undefined reference to `__stack_chk_fail_local'
> arch/powerpc/platforms/built-in.o: In function `bootx_init':
> /usr/local/src/linux-git/arch/powerpc/platforms/powermac/bootx_init.c:596: undefined reference to `__stack_chk_fail_local'
> /usr/bin/ld.bfd.real: .tmp_vmlinux1: hidden symbol `__stack_chk_fail_local' isn't defined
> /usr/bin/ld.bfd.real: final link failed: Bad value
> ================================
>
>
> $ ld --version | head -1
> GNU ld (GNU Binutils for Debian) 2.25
>
> $ gcc --version | head -1
> gcc-4.9.real (Debian 4.9.2-10) 4.9.2
>
>
> I'm regularly compiling userspace programs with -fstack-protector w/o
> problems. I suspect it's either 6533b7c16ee5712041b4e324100550e02a9a5dda
> ("powerpc: Initial stack protector (-fstack-protector) support") or
> 902e06eb86cd62753974c249bd1dedae2825b430 ("powerpc/32: Change the stack
> protector canary value per task") or both but I haven't started the
> bisection yet.
>
> Any other ideas?
>
> Thanks,
> Christian.
>
Using GCC 5.4.0, I don't have that issue. bootx_init.o only contains
reference to __stack_chk_fail
Looking a bit over internet, some people have reported having
encountered that issue due to old object files not properly cleaned.
Have you tried a 'make clean' or 'distclean' ?
Christophe
^ permalink raw reply
* Re: [PATCH v4 1/3] drm/exynos: mic: Add mode_set callback function
From: Inki Dae @ 2017-01-04 7:29 UTC (permalink / raw)
To: Hoegeun Kwon, robh, thierry.reding, airlied, kgene, krzk
Cc: dri-devel, linux-kernel, devicetree, linux-samsung-soc, a.hajda,
cw00.choi, jh80.chung
In-Reply-To: <1483513115-3068-2-git-send-email-hoegeun.kwon@samsung.com>
2017년 01월 04일 15:58에 Hoegeun Kwon 이(가) 쓴 글:
> Before applying the patch, used the of_get_videomode function to
> parse the display-timings in the panel which is the child driver
> of dsi in the devicetree. this is wrong. So removed the
> of_get_videomode and fixed to get videomode struct through
> mode_set callback function.
>
> Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
> ---
> drivers/gpu/drm/exynos/exynos_drm_mic.c | 33 ++++++++++++++++++++++-----------
> 1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c
> index a0def0b..9a50ceb 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_mic.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_mic.c
> @@ -286,13 +286,6 @@ static int parse_dt(struct exynos_mic *mic)
> }
> nodes[j++] = remote_node;
>
> - ret = of_get_videomode(remote_node,
> - &mic->vm, 0);
> - if (ret) {
> - DRM_ERROR("mic: failed to get videomode");
> - goto exit;
> - }
> -
> break;
> default:
> DRM_ERROR("mic: Unknown endpoint from MIC");
> @@ -329,6 +322,27 @@ static void mic_post_disable(struct drm_bridge *bridge)
> mutex_unlock(&mic_mutex);
> }
>
> +static void mic_mode_set(struct drm_bridge *bridge,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + struct exynos_mic *mic = bridge->driver_private;
> +
> + mutex_lock(&mic_mutex);
> + if (mic->enabled)
> + goto already_enabled;
mode setting should be performed every time mode_set callback is called so remove above two lines.
> +
> + drm_display_mode_to_videomode(mode, &mic->vm);
> +
> + if (!mic->i80_mode)
> + mic_set_porch_timing(mic);
> + mic_set_img_size(mic);
> + mic_set_output_timing(mic);
> +
> +already_enabled:
So this label is unnecessary.
> + mutex_unlock(&mic_mutex);
> +}
> +
> static void mic_pre_enable(struct drm_bridge *bridge)
> {
> struct exynos_mic *mic = bridge->driver_private;
> @@ -355,10 +369,6 @@ static void mic_pre_enable(struct drm_bridge *bridge)
> goto turn_off_clks;
> }
>
> - if (!mic->i80_mode)
> - mic_set_porch_timing(mic);
> - mic_set_img_size(mic);
> - mic_set_output_timing(mic);
> mic_set_reg_on(mic, 1);
> mic->enabled = 1;
> mutex_unlock(&mic_mutex);
> @@ -377,6 +387,7 @@ static void mic_enable(struct drm_bridge *bridge) { }
> static const struct drm_bridge_funcs mic_bridge_funcs = {
> .disable = mic_disable,
> .post_disable = mic_post_disable,
> + .mode_set = mic_mode_set,
> .pre_enable = mic_pre_enable,
> .enable = mic_enable,
> };
>
^ permalink raw reply
* Re: [PATCH v4 07/12] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
From: Adrian Hunter @ 2017-01-04 7:26 UTC (permalink / raw)
To: Gregory CLEMENT, Ulf Hansson, linux-mmc
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
Thomas Petazzoni, linux-arm-kernel, Ziji Hu, Jimmy Xu,
Jisheng Zhang, Nadav Haklai, Ryan Gao, Doug Jones, Victor Gu,
Wei(SOCP) Liu, Wilson Ding, Yehuda Yitschak, Marcin Wojtas,
Hanna Hawa, Kostya Porotchkin
In-Reply-To: <f48940626343ca9cf68b32b7324b243e76a11960.1481651244.git-series.gregory.clement@free-electrons.com>
[-- Attachment #1: Type: text/plain, Size: 24362 bytes --]
On 13/12/16 19:48, Gregory CLEMENT wrote:
> From: Hu Ziji <huziji@marvell.com>
>
> Add Xenon eMMC/SD/SDIO host controller core functionality.
> Add Xenon specific intialization process.
> Add Xenon specific mmc_host_ops APIs.
> Add Xenon specific register definitions.
>
> Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
>
> Marvell Xenon SDHC conforms to SD Physical Layer Specification
> Version 3.01 and is designed according to the guidelines provided
> in the SD Host Controller Standard Specification Version 3.00.
>
> Signed-off-by: Hu Ziji <huziji@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> MAINTAINERS | 1 +-
> drivers/mmc/host/Kconfig | 9 +-
> drivers/mmc/host/Makefile | 3 +-
> drivers/mmc/host/sdhci-xenon.c | 612 ++++++++++++++++++++++++++++++++++-
> drivers/mmc/host/sdhci-xenon.h | 70 ++++-
> 5 files changed, 695 insertions(+)
> create mode 100644 drivers/mmc/host/sdhci-xenon.c
> create mode 100644 drivers/mmc/host/sdhci-xenon.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 850a0afb0c8d..bb33286aeb48 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7608,6 +7608,7 @@ MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
> M: Ziji Hu <huziji@marvell.com>
> L: linux-mmc@vger.kernel.org
> S: Supported
> +F: drivers/mmc/host/sdhci-xenon*
> F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
>
> MATROX FRAMEBUFFER DRIVER
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 5274f503a39a..85a53623526a 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -798,3 +798,12 @@ config MMC_SDHCI_BRCMSTB
> Broadcom STB SoCs.
>
> If unsure, say Y.
> +
> +config MMC_SDHCI_XENON
> + tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
> + depends on MMC_SDHCI && MMC_SDHCI_PLTFM
> + help
> + This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
> + If you have a machine with integrated Marvell Xenon SDHC IP,
> + say Y or M here.
> + If unsure, say N.
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index e2bdaaf43184..75eaf743486c 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -80,3 +80,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o
> ifeq ($(CONFIG_CB710_DEBUG),y)
> CFLAGS-cb710-mmc += -DDEBUG
> endif
> +
> +obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
> +sdhci-xenon-driver-y += sdhci-xenon.o
> diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
> new file mode 100644
> index 000000000000..c71439fbc308
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-xenon.c
> @@ -0,0 +1,612 @@
> +/*
> + * Driver for Marvell Xenon SDHC as a platform device
> + *
> + * Copyright (C) 2016 Marvell, All Rights Reserved.
> + *
> + * Author: Hu Ziji <huziji@marvell.com>
> + * Date: 2016-8-24
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * Inspired by Jisheng Zhang <jszhang@marvell.com>
> + * Special thanks to Video BG4 project team.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +
> +#include "sdhci-pltfm.h"
> +#include "sdhci-xenon.h"
> +
> +static int enable_xenon_internal_clk(struct sdhci_host *host)
> +{
> + u32 reg;
> + u8 timeout;
> +
> + reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> + reg |= SDHCI_CLOCK_INT_EN;
> + sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
> + /* Wait max 20 ms */
> + timeout = 20;
> + while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
> + & SDHCI_CLOCK_INT_STABLE)) {
> + if (timeout == 0) {
> + pr_err("%s: Internal clock never stabilised.\n",
> + mmc_hostname(host->mmc));
> + return -ETIMEDOUT;
> + }
> + timeout--;
> + mdelay(1);
> + }
> +
> + return 0;
> +}
> +
> +/* Set SDCLK-off-while-idle */
> +static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
> + unsigned char sdhc_id, bool enable)
> +{
> + u32 reg;
> + u32 mask;
> +
> + reg = sdhci_readl(host, SDHCI_SYS_OP_CTRL);
> + /* Get the bit shift basing on the SDHC index */
> + mask = (0x1 << (SDHCI_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
> + if (enable)
> + reg |= mask;
> + else
> + reg &= ~mask;
> +
> + sdhci_writel(host, reg, SDHCI_SYS_OP_CTRL);
> +}
> +
> +/* Enable/Disable the Auto Clock Gating function */
> +static void xenon_set_acg(struct sdhci_host *host, bool enable)
> +{
> + u32 reg;
> +
> + reg = sdhci_readl(host, SDHCI_SYS_OP_CTRL);
> + if (enable)
> + reg &= ~SDHCI_AUTO_CLKGATE_DISABLE_MASK;
> + else
> + reg |= SDHCI_AUTO_CLKGATE_DISABLE_MASK;
> + sdhci_writel(host, reg, SDHCI_SYS_OP_CTRL);
> +}
> +
> +/* Enable this SDHC */
> +static void xenon_enable_sdhc(struct sdhci_host *host,
> + unsigned char sdhc_id)
> +{
> + u32 reg;
> +
> + reg = sdhci_readl(host, SDHCI_SYS_OP_CTRL);
> + reg |= (BIT(sdhc_id) << SDHCI_SLOT_ENABLE_SHIFT);
> + sdhci_writel(host, reg, SDHCI_SYS_OP_CTRL);
> +
> + /*
> + * Manually set the flag which all the card types require,
> + * including SD, eMMC, SDIO
> + */
> + host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
> +}
> +
> +/* Disable this SDHC */
> +static void xenon_disable_sdhc(struct sdhci_host *host,
> + unsigned char sdhc_id)
> +{
> + u32 reg;
> +
> + reg = sdhci_readl(host, SDHCI_SYS_OP_CTRL);
> + reg &= ~(BIT(sdhc_id) << SDHCI_SLOT_ENABLE_SHIFT);
> + sdhci_writel(host, reg, SDHCI_SYS_OP_CTRL);
> +}
> +
> +/* Enable Parallel Transfer Mode */
> +static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
> + unsigned char sdhc_id)
> +{
> + u32 reg;
> +
> + reg = sdhci_readl(host, SDHCI_SYS_EXT_OP_CTRL);
> + reg |= BIT(sdhc_id);
> + sdhci_writel(host, reg, SDHCI_SYS_EXT_OP_CTRL);
> +}
> +
> +static void xenon_sdhc_tuning_setup(struct sdhci_host *host)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> + u32 reg;
> +
> + /* Disable the Re-Tuning Request functionality */
> + reg = sdhci_readl(host, SDHCI_SLOT_RETUNING_REQ_CTRL);
> + reg &= ~SDHCI_RETUNING_COMPATIBLE;
> + sdhci_writel(host, reg, SDHCI_SLOT_RETUNING_REQ_CTRL);
> +
> + /* Disable the Re-tuning Event Signal Enable */
> + reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
> + reg &= ~SDHCI_INT_RETUNE;
> + sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
> +
> + /* Force to use Tuning Mode 1 */
> + host->tuning_mode = SDHCI_TUNING_MODE_1;
> + /* Set re-tuning period */
> + host->tuning_count = 1 << (priv->tuning_count - 1);
host->tuning_mode and host->tuning_count get overwritten in
sdhci_setup_host() called by sdhci_add_host()
> +}
> +
> +/*
> + * Operations inside struct sdhci_ops
> + */
> +/* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
> +static void sdhci_xenon_reset_exit(struct sdhci_host *host,
> + unsigned char sdhc_id, u8 mask)
> +{
> + /* Only SOFTWARE RESET ALL will clear the register setting */
> + if (!(mask & SDHCI_RESET_ALL))
> + return;
> +
> + /* Disable tuning request and auto-retuning again */
> + xenon_sdhc_tuning_setup(host);
> +
> + xenon_set_acg(host, true);
> +
> + xenon_set_sdclk_off_idle(host, sdhc_id, false);
> +}
> +
> +static void sdhci_xenon_reset(struct sdhci_host *host, u8 mask)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +
> + sdhci_reset(host, mask);
> + sdhci_xenon_reset_exit(host, priv->sdhc_id, mask);
> +}
> +
> +/*
> + * Xenon defines different values for HS200 and HS400
> + * in Host_Control_2
> + */
> +static void xenon_set_uhs_signaling(struct sdhci_host *host,
> + unsigned int timing)
> +{
> + u16 ctrl_2;
> +
> + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> + /* Select Bus Speed Mode for host */
> + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
> + if (timing == MMC_TIMING_MMC_HS200)
> + ctrl_2 |= SDHCI_XENON_CTRL_HS200;
> + else if (timing == MMC_TIMING_UHS_SDR104)
> + ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
> + else if (timing == MMC_TIMING_UHS_SDR12)
> + ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
> + else if (timing == MMC_TIMING_UHS_SDR25)
> + ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
> + else if (timing == MMC_TIMING_UHS_SDR50)
> + ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
> + else if ((timing == MMC_TIMING_UHS_DDR50) ||
> + (timing == MMC_TIMING_MMC_DDR52))
> + ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
> + else if (timing == MMC_TIMING_MMC_HS400)
> + ctrl_2 |= SDHCI_XENON_CTRL_HS400;
> + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> +}
> +
> +static const struct sdhci_ops sdhci_xenon_ops = {
> + .set_clock = sdhci_set_clock,
> + .set_bus_width = sdhci_set_bus_width,
> + .reset = sdhci_xenon_reset,
> + .set_uhs_signaling = xenon_set_uhs_signaling,
> + .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> +};
> +
> +static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
> + .ops = &sdhci_xenon_ops,
> + .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
> + SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
> + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> +};
> +
> +/*
> + * Xenon Specific Operations in mmc_host_ops
> + */
> +static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> + unsigned long flags;
> + u32 reg;
> +
> + /*
> + * HS400/HS200/eMMC HS doesn't have Preset Value register.
> + * However, sdhci_set_ios will read HS400/HS200 Preset register.
> + * Disable Preset Value register for HS400/HS200.
> + * eMMC HS with preset_enabled set will trigger a bug in
> + * get_preset_value().
> + */
> + spin_lock_irqsave(&host->lock, flags);
> + if ((ios->timing == MMC_TIMING_MMC_HS400) ||
> + (ios->timing == MMC_TIMING_MMC_HS200) ||
> + (ios->timing == MMC_TIMING_MMC_HS)) {
> + host->preset_enabled = false;
> + host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
> +
> + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> + reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
> + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
> + } else {
> + host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
> + }
> + spin_unlock_irqrestore(&host->lock, flags);
At some point we will have to get rid of SDHCI_QUIRK2_PRESET_VALUE_BROKEN
and add a callback instead.
> +
> + sdhci_set_ios(mmc, ios);
> +
> + if (host->clock > SDHCI_DEFAULT_SDCLK_FREQ) {
> + spin_lock_irqsave(&host->lock, flags);
> + xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
> + spin_unlock_irqrestore(&host->lock, flags);
> + }
> +}
> +
> +static int xenon_emmc_signal_voltage_switch(struct mmc_host *mmc,
> + struct mmc_ios *ios)
> +{
> + unsigned char voltage = ios->signal_voltage;
> + struct sdhci_host *host = mmc_priv(mmc);
> + unsigned char voltage_code;
> + u32 ctrl;
> +
> + if ((voltage == MMC_SIGNAL_VOLTAGE_330) ||
> + (voltage == MMC_SIGNAL_VOLTAGE_180)) {
> + if (voltage == MMC_SIGNAL_VOLTAGE_330)
> + voltage_code = SDHCI_EMMC_VCCQ_3_3V;
> + else if (voltage == MMC_SIGNAL_VOLTAGE_180)
> + voltage_code = SDHCI_EMMC_VCCQ_1_8V;
> +
> + /*
> + * This host is for eMMC, XENON self-defined
> + * eMMC control register should be accessed
> + * instead of Host Control 2
> + */
> + ctrl = sdhci_readl(host, SDHCI_SLOT_EMMC_CTRL);
> + ctrl &= ~SDHCI_EMMC_VCCQ_MASK;
> + ctrl |= voltage_code;
> + sdhci_writel(host, ctrl, SDHCI_SLOT_EMMC_CTRL);
> +
> + /* There is no standard to determine this waiting period */
> + usleep_range(1000, 2000);
> +
> + /* Check whether io voltage switch is done */
> + ctrl = sdhci_readl(host, SDHCI_SLOT_EMMC_CTRL);
> + ctrl &= SDHCI_EMMC_VCCQ_MASK;
> + /*
> + * This bit is set only when regulator feeds back
> + * the voltage switch results to Xenon SDHC.
> + * However, in actaul implementation, regulator might not
> + * provide this feedback.
> + * Thus we shall not rely on this bit to determine
> + * if switch failed.
> + * If the bit is not set, just throw a message.
> + * Besides, error code should not be returned.
> + */
> + if (ctrl != voltage_code)
> + dev_info(mmc_dev(mmc), "fail to detect eMMC signal voltage stable\n");
> + return 0;
> + }
> +
> + dev_err(mmc_dev(mmc), "Unsupported signal voltage: %d\n", voltage);
> + return -EINVAL;
> +}
> +
> +static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
> + struct mmc_ios *ios)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +
> + /*
> + * Before SD/SDIO set signal voltage, SD bus clock should be
> + * disabled. However, sdhci_set_clock will also disable the Internal
> + * clock in mmc_set_signal_voltage().
> + * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
> + * Thus here manually enable internal clock.
> + *
> + * After switch completes, it is unnecessary to disable internal clock,
> + * since keeping internal clock active obeys SD spec.
> + */
> + enable_xenon_internal_clk(host);
We could try the attached patch.
> +
> + if (priv->init_card_type == MMC_TYPE_MMC)
> + return xenon_emmc_signal_voltage_switch(mmc, ios);
> +
> + return sdhci_start_signal_voltage_switch(mmc, ios);
> +}
> +
> +/*
> + * Update card type.
> + * priv->init_card_type will be used in PHY timing adjustment.
> + */
> +static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +
> + /* Update card type*/
> + priv->init_card_type = card->type;
> +}
> +
> +static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> +
> + if (host->timing == MMC_TIMING_UHS_DDR50)
> + return 0;
> +
> + return sdhci_execute_tuning(mmc, opcode);
> +}
> +
> +static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> + u32 reg;
> + u8 sdhc_id = priv->sdhc_id;
> +
> + sdhci_enable_sdio_irq(mmc, enable);
> +
> + if (enable) {
> + /*
> + * Set SDIO Card Inserted indication
> + * to enable detecting SDIO async irq.
> + */
> + reg = sdhci_readl(host, SDHCI_SYS_CFG_INFO);
> + reg |= (1 << (sdhc_id + SDHCI_SLOT_TYPE_SDIO_SHIFT));
> + sdhci_writel(host, reg, SDHCI_SYS_CFG_INFO);
> + } else {
> + /* Clear SDIO Card Inserted indication */
> + reg = sdhci_readl(host, SDHCI_SYS_CFG_INFO);
> + reg &= ~(1 << (sdhc_id + SDHCI_SLOT_TYPE_SDIO_SHIFT));
> + sdhci_writel(host, reg, SDHCI_SYS_CFG_INFO);
> + }
> +}
> +
> +static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
> +{
> + host->mmc_host_ops.set_ios = xenon_set_ios;
> + host->mmc_host_ops.start_signal_voltage_switch =
> + xenon_start_signal_voltage_switch;
> + host->mmc_host_ops.init_card = xenon_init_card;
> + host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
> + host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
> +}
> +
> +/*
> + * Parse child node in Xenon DT.
> + * Search for the following item(s):
> + * - eMMC card type
> + */
> +static int xenon_child_node_of_parse(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct sdhci_host *host = platform_get_drvdata(pdev);
> + struct mmc_host *mmc = host->mmc;
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> + struct device_node *child;
> + int nr_child;
> +
> + priv->init_card_type = SDHCI_CARD_TYPE_UNKNOWN;
> +
> + nr_child = of_get_child_count(np);
> + if (!nr_child)
> + return 0;
> +
> + for_each_child_of_node(np, child) {
> + if (of_device_is_compatible(child, "mmc-card")) {
> + priv->init_card_type = MMC_TYPE_MMC;
> + mmc->caps |= MMC_CAP_NONREMOVABLE;
> +
> + /*
> + * Force to clear BUS_TEST to
> + * skip bus_test_pre and bus_test_post
> + */
> + mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
> + mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ |
> + MMC_CAP2_PACKED_CMD |
> + MMC_CAP2_NO_SD |
> + MMC_CAP2_NO_SDIO;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int xenon_probe_dt(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct sdhci_host *host = platform_get_drvdata(pdev);
> + struct mmc_host *mmc = host->mmc;
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> + int err;
> + u32 sdhc_id, nr_sdhc;
> + u32 tuning_count;
> +
> + /* Standard MMC property */
> + err = mmc_of_parse(mmc);
> + if (err)
> + return err;
> +
> + /* Standard SDHCI property */
> + sdhci_get_of_property(pdev);
> +
> + /*
> + * Xenon Specific property:
> + * init_card_type: check whether this SDHC is for eMMC
> + * sdhc-id: the index of current SDHC.
> + * Refer to SDHCI_SYS_CFG_INFO register
> + * tun-count: the interval between re-tuning
> + */
> + /* Parse child node, including checking emmc type */
> + err = xenon_child_node_of_parse(pdev);
> + if (err)
> + return err;
> +
> + priv->sdhc_id = 0x0;
> + if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
> + nr_sdhc = sdhci_readl(host, SDHCI_SYS_CFG_INFO);
> + nr_sdhc &= SDHCI_NR_SUPPORTED_SLOT_MASK;
> + if (unlikely(sdhc_id > nr_sdhc)) {
> + dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
> + sdhc_id, nr_sdhc);
> + return -EINVAL;
> + }
> + }
> +
> + tuning_count = SDHCI_DEF_TUNING_COUNT;
> + if (!of_property_read_u32(np, "marvell,xenon-tun-count",
> + &tuning_count)) {
> + if (unlikely(tuning_count >= SDHCI_TMR_RETUN_NO_PRESENT)) {
> + dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
> + SDHCI_DEF_TUNING_COUNT);
> + tuning_count = SDHCI_DEF_TUNING_COUNT;
> + }
> + }
> + priv->tuning_count = tuning_count;
> +
> + return err;
> +}
> +
> +static int xenon_sdhc_probe(struct sdhci_host *host)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> + u8 sdhc_id = priv->sdhc_id;
> +
> + /* Enable SDHC */
> + xenon_enable_sdhc(host, sdhc_id);
> +
> + /* Enable ACG */
> + xenon_set_acg(host, true);
> +
> + /* Enable Parallel Transfer Mode */
> + xenon_enable_sdhc_parallel_tran(host, sdhc_id);
> +
> + /* Set tuning functionality of this SDHC */
> + xenon_sdhc_tuning_setup(host);
> +
> + return 0;
> +}
> +
> +static void xenon_sdhc_remove(struct sdhci_host *host)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
> + u8 sdhc_id = priv->sdhc_id;
> +
> + /* disable SDHC */
> + xenon_disable_sdhc(host, sdhc_id);
> +}
> +
> +static int sdhci_xenon_probe(struct platform_device *pdev)
> +{
> + struct sdhci_pltfm_host *pltfm_host;
> + struct sdhci_host *host;
> + struct sdhci_xenon_priv *priv;
> + int err;
> +
> + host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
> + sizeof(struct sdhci_xenon_priv));
> + if (IS_ERR(host))
> + return PTR_ERR(host);
> +
> + pltfm_host = sdhci_priv(host);
> + priv = sdhci_pltfm_priv(pltfm_host);
> +
> + xenon_set_acg(host, false);
> +
> + /*
> + * Link Xenon specific mmc_host_ops function,
> + * to replace standard ones in sdhci_ops.
> + */
> + xenon_replace_mmc_host_ops(host);
> +
> + pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(pltfm_host->clk)) {
> + err = PTR_ERR(pltfm_host->clk);
> + dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
> + goto free_pltfm;
> + }
> + err = clk_prepare_enable(pltfm_host->clk);
> + if (err)
> + goto free_pltfm;
> +
> + err = xenon_probe_dt(pdev);
> + if (err)
> + goto err_clk;
> +
> + err = xenon_sdhc_probe(host);
> + if (err)
> + goto err_clk;
> +
> + err = sdhci_add_host(host);
> + if (err)
> + goto remove_sdhc;
> +
> + return 0;
> +
> +remove_sdhc:
> + xenon_sdhc_remove(host);
> +err_clk:
> + clk_disable_unprepare(pltfm_host->clk);
> +free_pltfm:
> + sdhci_pltfm_free(pdev);
> + return err;
> +}
> +
> +static int sdhci_xenon_remove(struct platform_device *pdev)
> +{
> + struct sdhci_host *host = platform_get_drvdata(pdev);
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xFFFFFFFF);
This 'dead' check was originally for PCI I think. Unless you know it makes
sense for your device, I would leave it out. i.e. just do
sdhci_remove_host(host, 0);
> +
> + xenon_sdhc_remove(host);
> +
> + sdhci_remove_host(host, dead);
> +
> + clk_disable_unprepare(pltfm_host->clk);
> +
> + sdhci_pltfm_free(pdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id sdhci_xenon_dt_ids[] = {
> + { .compatible = "marvell,armada-7000-sdhci",},
> + { .compatible = "marvell,armada-3700-sdhci",},
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
> +
> +static struct platform_driver sdhci_xenon_driver = {
> + .driver = {
> + .name = "xenon-sdhci",
> + .of_match_table = sdhci_xenon_dt_ids,
> + .pm = &sdhci_pltfm_pmops,
> + },
> + .probe = sdhci_xenon_probe,
> + .remove = sdhci_xenon_remove,
> +};
> +
> +module_platform_driver(sdhci_xenon_driver);
> +
> +MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
> +MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
> new file mode 100644
> index 000000000000..d50cd663a265
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-xenon.h
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright (C) 2016 Marvell, All Rights Reserved.
> + *
> + * Author: Hu Ziji <huziji@marvell.com>
> + * Date: 2016-8-24
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + */
> +#ifndef SDHCI_XENON_H_
> +#define SDHCI_XENON_H_
> +
> +
Double blank line
> +/* Register Offset of Xenon SDHC self-defined register */
> +#define SDHCI_SYS_CFG_INFO 0x0104
A lot of these defines look like they could be just in sdhci-xenon.c or
sdhci-xenon-phy.c. It is also a little odd that they are prefixed by
"SDHCI" because they are not standard. "XENON" would be better.
> +#define SDHCI_SLOT_TYPE_SDIO_SHIFT 24
> +#define SDHCI_NR_SUPPORTED_SLOT_MASK 0x7
> +
> +#define SDHCI_SYS_OP_CTRL 0x0108
> +#define SDHCI_AUTO_CLKGATE_DISABLE_MASK BIT(20)
> +#define SDHCI_SDCLK_IDLEOFF_ENABLE_SHIFT 8
> +#define SDHCI_SLOT_ENABLE_SHIFT 0
> +
> +#define SDHCI_SYS_EXT_OP_CTRL 0x010C
> +
> +#define SDHCI_SLOT_EMMC_CTRL 0x0130
> +#define SDHCI_EMMC_VCCQ_MASK 0x3
> +#define SDHCI_EMMC_VCCQ_1_8V 0x1
> +#define SDHCI_EMMC_VCCQ_3_3V 0x3
> +
> +#define SDHCI_SLOT_RETUNING_REQ_CTRL 0x0144
> +/* retuning compatible */
> +#define SDHCI_RETUNING_COMPATIBLE 0x1
> +
> +/* Tuning Parameter */
> +#define SDHCI_TMR_RETUN_NO_PRESENT 0xF
> +#define SDHCI_DEF_TUNING_COUNT 0x9
> +
> +#define SDHCI_DEFAULT_SDCLK_FREQ (400000)
Unnecessary ()
> +
> +/* Xenon specific Mode Select value */
> +#define SDHCI_XENON_CTRL_HS200 0x5
> +#define SDHCI_XENON_CTRL_HS400 0x6
> +
> +/* Indicate Card Type is not clear yet */
> +#define SDHCI_CARD_TYPE_UNKNOWN 0xF
> +
> +struct sdhci_xenon_priv {
> + unsigned char tuning_count;
> + /* idx of SDHC */
> + u8 sdhc_id;
> +
> + /*
> + * eMMC/SD/SDIO require different PHY settings or
> + * voltage control. It's necessary for Xenon driver to
> + * recognize card type during, or even before initialization.
> + * However, mmc_host->card is not available yet at that time.
> + * This field records the card type during init.
> + * For eMMC, it is updated in dt parse. For SD/SDIO, it is
> + * updated in xenon_init_card().
> + *
> + * It is only valid during initialization after it is updated.
> + * Do not access this variable in normal transfers after
> + * initialization completes.
> + */
> + unsigned int init_card_type;
> +};
> +
> +#endif
>
[-- Attachment #2: 0001-mmc-sdhci-Leave-internal-clock-on-when-bus-power-is-.patch --]
[-- Type: text/x-patch, Size: 1423 bytes --]
>From 9a23bf1292e33d3d91a1ee2d7f269c9079d9c1be Mon Sep 17 00:00:00 2001
From: Adrian Hunter <adrian.hunter@intel.com>
Date: Fri, 25 Nov 2016 16:25:05 +0200
Subject: [PATCH] mmc: sdhci: Leave internal clock on when bus power is on
According to the SDHCI specification, "Internal Clock Enable" is expected
to remain on while "SD Clock Enable" is off during voltage switching. Do
that by keeping the internal clock on if the bus power is on.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 9a4fda81ff81..aeb001e7cc63 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1372,14 +1372,20 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
- u16 clk;
+ u16 clk = 0;
host->mmc->actual_clock = 0;
- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
-
- if (clock == 0)
+ if (clock == 0) {
+ if (host->mmc->ios.power_mode != MMC_POWER_OFF) {
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~SDHCI_CLOCK_CARD_EN;
+ }
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
return;
+ }
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
sdhci_enable_clk(host, clk);
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v2 5/9] net/virtio: setup rxq interrupts
From: Tan, Jianfeng @ 2017-01-04 7:30 UTC (permalink / raw)
To: Yuanhan Liu; +Cc: dev@dpdk.org, stephen@networkplumber.org
In-Reply-To: <20170104072256.GK21228@yliu-dev.sh.intel.com>
> -----Original Message-----
> From: Yuanhan Liu [mailto:yuanhan.liu@linux.intel.com]
> Sent: Wednesday, January 4, 2017 3:23 PM
> To: Tan, Jianfeng
> Cc: dev@dpdk.org; stephen@networkplumber.org
> Subject: Re: [PATCH v2 5/9] net/virtio: setup rxq interrupts
>
> On Wed, Jan 04, 2017 at 02:56:50PM +0800, Tan, Jianfeng wrote:
> >
> >
> > [...]
> > >>+
> > >>+ if (virtio_queues_bind_intr(dev) < 0) {
> > >>+ PMD_INIT_LOG(ERR, "Failed to bind queue/interrupt");
> > >>+ return -1;
> > >You have to free intr_handle->intr_vec, otherwise, memory leak occurs.
> >
> > It's freed at dev_close(). Do you mean freeing and reallocating here? As
>
> The typical way is free the resources have been allocated when errors
> happens.
>
> > nr_rx_queues is not a changeable value, I don't see the necessity here. I
> > miss something?
>
> No. nb_rx_queues does change, when people reconfigure the queue
> number.
> However, the MAX queues the virito supports does not change. You could
> use that number for allocation.
Oh yes. I will fix it.
Thanks,
Jianfeng
>
> --yliu
^ permalink raw reply
* [Buildroot] [autobuild.buildroot.net] Build results for 2017-01-03
From: Thomas Petazzoni @ 2017-01-04 7:30 UTC (permalink / raw)
To: buildroot
Hello,
Build statistics for 2017-01-03
================================
successes : 161
failures : 79
timeouts : 0
TOTAL : 240
Classification of failures by reason
====================================
collectd-5.7.0 | 25
libglib2-2.50.2 | 12
sdl2_ttf-2.0.14 | 10
gnutls-3.4.17 | 4
tcpreplay-4.1.2 | 3
kmod-23 | 2
libraw-0.17.1 | 2
lttng-libust-2.9.0 | 2
boost-1.61.0 | 1
cmake-3.7.1 | 1
cups-2.1.4 | 1
espeak-1.48.04 | 1
kmsxx-bd5f6471e619a6ba2987b... | 1
libnss-3.27.1 | 1
libsvg-0.1.4 | 1
luasql-sqlite3-2.3.0-1 | 1
mpd-mpc-0.28 | 1
mpv-0.22.0 | 1
openocd-0.9.0 | 1
polarssl-1.2.19 | 1
qwt-6.1.3 | 1
rabbitmq-c-v0.8.0 | 1
rsyslog-8.22.0 | 1
ruby-2.3.3 | 1
squid-3.5.23 | 1
stunnel-5.36 | 1
vlc-2.2.4 | 1
Detail of failures
===================
i586 | boost-1.61.0 | NOK | http://autobuild.buildroot.net/results/e8bf1804917171e53210affcaa91b0209808ab03
x86_64 | cmake-3.7.1 | NOK | http://autobuild.buildroot.net/results/fb1fe2abc6628d16939afa9be515530e9240cd94
mips64el | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/658fb37e42d3bc8ce074549e5a32d6e2f41155cf
x86_64 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/d3921474cb4ece9f0b769606fc9271327edbbc71
arm | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/7f2f6460790293913a3e26ad7c9e4b4976709b45
x86_64 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/0adebbd53e4bf3ba16ec331a8bcba82084f4cb4f
arm | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/5af1fe388e99e9bf6ba256f66ecd2ea163000cb0
arm | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/88e3f4db0e5fad44476b064773e9e95ca379f7fa
sparc | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/8e3b6c435b3581270001f215e25bf5d325129d30
x86_64 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/f012bed97f9e8ff9febf7737eb6fd24a3e87eed4
arm | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/d661891c7a111a22473ba6423e555b9d3b7c5d2b
aarch64 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/8ad7a8dfc864c3308b7421a0291026ee5255c501
i686 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/e3fa8f954303105fd1df96c5fd13831730d80a18
sh4a | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/2a4420c49cb875871fe4a5582dc8108aac1159e4
microblazeel | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/4c9a10bc3223f006fe0c1a3e1b8cc3d9cf611107
mips64el | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/ccf2c17c5cd21a9ca7a13b1bccef3774ec582a68
x86_64 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/8bfe2b9ba2291415eb94e8395275471d2a6d99fa
sh4a | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/c92a64f0ef76bbf041a70701b1c7c001b7a2d491
x86_64 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/350319fc31801044b42213a3ca2c6002106ef6b0
powerpc64 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/70c5d9ded19d2b632b4dff3472be328831fa4bcb
nios2 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/df8d91b7901e6fb8eb55014d5911b34af48ff791
nios2 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/2223ea5ad2f54a6804564ee5c26e024a8ee7bb3c
powerpc | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/e633be48d0ccd075c8dbb95b04cc2fe30b6d65bc
nios2 | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/282a31c6648e5635c580cd2087f7891ea6d53dc8
mipsel | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/aa7fd9cc585539cdbf401b620e38948412d799ab
arm | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/5c361151322b02872571131b7a3d46ebdaf93598
sh4a | collectd-5.7.0 | NOK | http://autobuild.buildroot.net/results/01877432e7c6469447284919b9e91bbb5310169f
i586 | cups-2.1.4 | NOK | http://autobuild.buildroot.net/results/24b5efc7769020b942c657af037af72f2f1a7164
nios2 | espeak-1.48.04 | NOK | http://autobuild.buildroot.net/results/0c90584f26530eded3f3ef12c0af2214e2399438
arc | gnutls-3.4.17 | NOK | http://autobuild.buildroot.net/results/c2d35c281f86799a3287aa1ca3cf40f7e2edd9f4
arc | gnutls-3.4.17 | NOK | http://autobuild.buildroot.net/results/d0ddd8d28fe05d8b22210b37d27d73f02e010e00
powerpc | gnutls-3.4.17 | NOK | http://autobuild.buildroot.net/results/19e8d316ee356bc8a22b39a4166a19d938669b5c
arm | gnutls-3.4.17 | NOK | http://autobuild.buildroot.net/results/6ff7774e1eea406467507a296f6d29f66dc0bcff
microblazeel | kmod-23 | NOK | http://autobuild.buildroot.net/results/fc7efeef20c56311ddd4f8bbbf6a912ecc60965e
microblazeel | kmod-23 | NOK | http://autobuild.buildroot.net/results/582fc94b3e27f912e353886223e8252de9f39842
m68k | kmsxx-bd5f6471e619a6ba2987b... | NOK | http://autobuild.buildroot.net/results/6772c98e7e20a3beabc25ac83dc31acf628a3a96
powerpc | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/f3465d29570c150a58df213b123652d8a2081e15
powerpc | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/2cf40ea802617729123f1d68495251c685701bf8
arm | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/730c507e78ec35e5e66cd2f53f8a8e73086c0e58
arm | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/c2b1c6d789b2df3db40bbc63e3cbcc849644125a
arm | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/b7ce266582079d84ea9c19a24dbc496f3af58e01
xtensa | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/67aee5600b20ab66fc6b2565782ac78449d8e05c
powerpc | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/ed86b3d6d948062c597e8ad949fe5db08d69e7df
arc | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/266988a8ea533bc17f3e4b473b7b98c9bdcbc709
arm | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/f2389336b01079ba850ece040dcb8470ad8b7c02
xtensa | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/c8ac66af307362c6355e4b55865581bd68d5d9f4
arc | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/8347d1f898e0574ad2fecdd90b344442a0eb16d1
arc | libglib2-2.50.2 | NOK | http://autobuild.buildroot.net/results/7f6c616c0abcdcf40edaf5fe050a364a0ab0c7b3
microblazeel | libnss-3.27.1 | NOK | http://autobuild.buildroot.net/results/efba3911588f32cc92cbc5d2122d66068186babd
i686 | libraw-0.17.1 | NOK | http://autobuild.buildroot.net/results/54be575498a25c6348ad067d3872dc9956fd0d06
sh4a | libraw-0.17.1 | NOK | http://autobuild.buildroot.net/results/b21aecfc94af7ce9904a858eb34766632214f33a
powerpc64 | libsvg-0.1.4 | NOK | http://autobuild.buildroot.net/results/eb2cad8bf10efe95db2027ff5fc9e95b77988012
x86_64 | lttng-libust-2.9.0 | NOK | http://autobuild.buildroot.net/results/0e9156c40ba10c98c8bdcd3133e463130346c48c
x86_64 | lttng-libust-2.9.0 | NOK | http://autobuild.buildroot.net/results/a240c7b188152009d9328665d0cfa78e0407cd30
x86_64 | luasql-sqlite3-2.3.0-1 | NOK | http://autobuild.buildroot.net/results/0a47f30c59246b2376232c0eea3bdacd7806f5e6
powerpc | mpd-mpc-0.28 | NOK | http://autobuild.buildroot.net/results/d5fa3578eba54945aa965dc4f95ee8eedab9df47
powerpc64 | mpv-0.22.0 | NOK | http://autobuild.buildroot.net/results/12659a06211b475e2a427931eb472b18e05a7bf9
powerpc64 | openocd-0.9.0 | NOK | http://autobuild.buildroot.net/results/15423295bfca4157407728ade2e5aba656910ad0
arm | polarssl-1.2.19 | NOK | http://autobuild.buildroot.net/results/2030b306c6c6c287cbc5595534cc4480643484dc
sh4 | qwt-6.1.3 | NOK | http://autobuild.buildroot.net/results/0ce69d90ce599076766a8ee43f5ade9d87b8046e
m68k | rabbitmq-c-v0.8.0 | NOK | http://autobuild.buildroot.net/results/3cbad0097d262c0da62289072a7bc580101c2fba
arm | rsyslog-8.22.0 | NOK | http://autobuild.buildroot.net/results/527a06828dd73e55d013ef49ee6083d875a17ba7
mipsel | ruby-2.3.3 | NOK | http://autobuild.buildroot.net/results/e680f42b7f69698b358e03f20ecde39a5b52e923
mipsel | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/9600a6568a2b898727227b8db39188908cd4b9b4
arm | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/350907e6b379b6ba7e77b83c5981a7c6f6cc3df3
x86_64 | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/ae4ca8cdec793b52f3a0311a9c37e06c55c4fb09
arc | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/cca04909b7839f0ae92d6241f0f0c982743b9d3c
arm | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/3e29534f041caac3bae3d40ea898699147090cb7
nios2 | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/15a9f74482781a522772f23e05763926140a1364
arm | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/66ecbc1c7d9c2dad11b99ff56ea0636ddee485a2
xtensa | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/c5466b186e058240fd9eaf60727786a47e3c2dfa
powerpc | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/161e6880a41efb2356f8bb4e48dcdcebb3fc7646
mips64el | sdl2_ttf-2.0.14 | NOK | http://autobuild.buildroot.net/results/880899b249dd62b0eff82ed6cee371de3d891cba
arm | squid-3.5.23 | NOK | http://autobuild.buildroot.net/results/d83792d4e0ed7ab0f3b8932246d65fd20b6a542b
i586 | stunnel-5.36 | NOK | http://autobuild.buildroot.net/results/e0289b25cca5933b188af57be0cf559cce46fe12
x86_64 | tcpreplay-4.1.2 | NOK | http://autobuild.buildroot.net/results/95e3b404609fceb904072bb1359ecd8b8e46553a
arm | tcpreplay-4.1.2 | NOK | http://autobuild.buildroot.net/results/d157ceda959c5ef5618c944383a7f0948fa02159
arm | tcpreplay-4.1.2 | NOK | http://autobuild.buildroot.net/results/454d1a180e6dc4ece0c94ca533dfc041f0f1ebfa
microblazeel | vlc-2.2.4 | NOK | http://autobuild.buildroot.net/results/33165ace9141d1de68466df2c0e80429d2e4763b
--
http://autobuild.buildroot.net
^ permalink raw reply
* [libvirt test] 104021: regressions - FAIL
From: osstest service owner @ 2017-01-04 7:29 UTC (permalink / raw)
To: xen-devel, osstest-admin
flight 104021 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/104021/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-libvirt-vhd 9 debian-di-install fail REGR. vs. 104005
Regressions which are regarded as allowable (not blocking):
test-armhf-armhf-libvirt-xsm 13 saverestore-support-check fail like 104005
test-armhf-armhf-libvirt 13 saverestore-support-check fail like 104005
test-armhf-armhf-libvirt-qcow2 12 saverestore-support-check fail like 104005
test-armhf-armhf-libvirt-raw 12 saverestore-support-check fail like 104005
Tests which did not succeed, but are not blocking:
test-amd64-amd64-libvirt 12 migrate-support-check fail never pass
test-amd64-amd64-libvirt-xsm 12 migrate-support-check fail never pass
test-amd64-i386-libvirt-xsm 12 migrate-support-check fail never pass
test-amd64-i386-libvirt 12 migrate-support-check fail never pass
test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass
test-armhf-armhf-libvirt-xsm 12 migrate-support-check fail never pass
test-armhf-armhf-libvirt 12 migrate-support-check fail never pass
test-armhf-armhf-libvirt-qcow2 11 migrate-support-check fail never pass
test-armhf-armhf-libvirt-raw 11 migrate-support-check fail never pass
version targeted for testing:
libvirt 7f7d99048350935a394d07b98a13d7da9c4b0502
baseline version:
libvirt 0735ddf744f95cd9f88c5f8465b1a64883710d37
Last test of basis 104005 2017-01-03 04:20:30 Z 1 days
Testing same since 104021 2017-01-04 04:20:15 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
John Ferlan <jferlan@redhat.com>
jobs:
build-amd64-xsm pass
build-armhf-xsm pass
build-i386-xsm pass
build-amd64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-amd64-libvirt-xsm pass
test-armhf-armhf-libvirt-xsm pass
test-amd64-i386-libvirt-xsm pass
test-amd64-amd64-libvirt pass
test-armhf-armhf-libvirt pass
test-amd64-i386-libvirt pass
test-amd64-amd64-libvirt-pair pass
test-amd64-i386-libvirt-pair pass
test-armhf-armhf-libvirt-qcow2 pass
test-armhf-armhf-libvirt-raw pass
test-amd64-amd64-libvirt-vhd fail
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Not pushing.
------------------------------------------------------------
commit 7f7d99048350935a394d07b98a13d7da9c4b0502
Author: John Ferlan <jferlan@redhat.com>
Date: Thu Dec 22 07:12:49 2016 -0500
qemu: Don't assume secret provided for LUKS encryption
https://bugzilla.redhat.com/show_bug.cgi?id=1405269
If a secret was not provided for what was determined to be a LUKS
encrypted disk (during virStorageFileGetMetadata processing when
called from qemuDomainDetermineDiskChain as a result of hotplug
attach qemuDomainAttachDeviceDiskLive), then do not attempt to
look it up (avoiding a libvirtd crash) and do not alter the format
to "luks" when adding the disk; otherwise, the device_add would
fail with a message such as:
"unable to execute QEMU command 'device_add': Property 'scsi-hd.drive'
can't find value 'drive-scsi0-0-0-0'"
because of assumptions that when the format=luks that libvirt would have
provided the secret to decrypt the volume.
Access to unlock the volume will thus be left to the application.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply
* Re: [PATCH v4 1/3] drm/exynos: mic: Add mode_set callback function
From: Inki Dae @ 2017-01-04 7:29 UTC (permalink / raw)
To: Hoegeun Kwon, robh, thierry.reding, airlied, kgene, krzk
Cc: devicetree, linux-samsung-soc, linux-kernel, dri-devel,
jh80.chung, cw00.choi
In-Reply-To: <1483513115-3068-2-git-send-email-hoegeun.kwon@samsung.com>
2017년 01월 04일 15:58에 Hoegeun Kwon 이(가) 쓴 글:
> Before applying the patch, used the of_get_videomode function to
> parse the display-timings in the panel which is the child driver
> of dsi in the devicetree. this is wrong. So removed the
> of_get_videomode and fixed to get videomode struct through
> mode_set callback function.
>
> Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
> ---
> drivers/gpu/drm/exynos/exynos_drm_mic.c | 33 ++++++++++++++++++++++-----------
> 1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c
> index a0def0b..9a50ceb 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_mic.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_mic.c
> @@ -286,13 +286,6 @@ static int parse_dt(struct exynos_mic *mic)
> }
> nodes[j++] = remote_node;
>
> - ret = of_get_videomode(remote_node,
> - &mic->vm, 0);
> - if (ret) {
> - DRM_ERROR("mic: failed to get videomode");
> - goto exit;
> - }
> -
> break;
> default:
> DRM_ERROR("mic: Unknown endpoint from MIC");
> @@ -329,6 +322,27 @@ static void mic_post_disable(struct drm_bridge *bridge)
> mutex_unlock(&mic_mutex);
> }
>
> +static void mic_mode_set(struct drm_bridge *bridge,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + struct exynos_mic *mic = bridge->driver_private;
> +
> + mutex_lock(&mic_mutex);
> + if (mic->enabled)
> + goto already_enabled;
mode setting should be performed every time mode_set callback is called so remove above two lines.
> +
> + drm_display_mode_to_videomode(mode, &mic->vm);
> +
> + if (!mic->i80_mode)
> + mic_set_porch_timing(mic);
> + mic_set_img_size(mic);
> + mic_set_output_timing(mic);
> +
> +already_enabled:
So this label is unnecessary.
> + mutex_unlock(&mic_mutex);
> +}
> +
> static void mic_pre_enable(struct drm_bridge *bridge)
> {
> struct exynos_mic *mic = bridge->driver_private;
> @@ -355,10 +369,6 @@ static void mic_pre_enable(struct drm_bridge *bridge)
> goto turn_off_clks;
> }
>
> - if (!mic->i80_mode)
> - mic_set_porch_timing(mic);
> - mic_set_img_size(mic);
> - mic_set_output_timing(mic);
> mic_set_reg_on(mic, 1);
> mic->enabled = 1;
> mutex_unlock(&mic_mutex);
> @@ -377,6 +387,7 @@ static void mic_enable(struct drm_bridge *bridge) { }
> static const struct drm_bridge_funcs mic_bridge_funcs = {
> .disable = mic_disable,
> .post_disable = mic_post_disable,
> + .mode_set = mic_mode_set,
> .pre_enable = mic_pre_enable,
> .enable = mic_enable,
> };
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v6 06/14] irqchip: gicv3-its: platform-msi: refactor its_pmsi_init() to prepare for ACPI
From: Tomasz Nowicki @ 2017-01-04 7:29 UTC (permalink / raw)
To: Hanjun Guo, Marc Zyngier, Rafael J. Wysocki, Lorenzo Pieralisi
Cc: linux-acpi, linux-arm-kernel, linux-kernel, linuxarm,
Thomas Gleixner, Greg KH, Ma Jun, Kefeng Wang, Agustin Vega-Frias,
Sinan Kaya, charles.garcia-tobin, huxinwei, yimin, Jon Masters
In-Reply-To: <601cbdf2-823d-8bde-bbd9-fcc6a1c67f2c@linaro.org>
On 04.01.2017 08:02, Hanjun Guo wrote:
> Hi Tomasz,
>
> On 2017/1/3 15:41, Tomasz Nowicki wrote:
>> Hi,
>>
>> Can we merge patch 4 & 6 into one patch so that we keep refactoring part
>> as one piece ? I do not see a reason to keep them separate or have patch
>> 5 in between. You can refactor what needs to be refactored, add
>> necessary functions to iort.c and then support ACPI for
>> irq-gic-v3-its-platform-msi.c
>
> There are two functions here,
> - retrieve the dev id from IORT which was DT based only;
>
> - init the platform msi domain from MADT;
>
> For each of them split it into two steps,
> - refactor the code for ACPI later and it's easy for review
> because wen can easily to figure out it has functional
> change or not
>
> - add ACPI functionality
>
> Does it make sense?
It is up to Marc, but personally I prefer:
1. Refactor dev id retrieving and init function in one patch and
highlight no functional changes in changelog
2. Crate necessary infrastructure in iort.c
3. Then add ACPI support to irq-gic-v3-its-platform-msi.c
Thanks,
Tomasz
^ permalink raw reply
* [PATCH v6 06/14] irqchip: gicv3-its: platform-msi: refactor its_pmsi_init() to prepare for ACPI
From: Tomasz Nowicki @ 2017-01-04 7:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <601cbdf2-823d-8bde-bbd9-fcc6a1c67f2c@linaro.org>
On 04.01.2017 08:02, Hanjun Guo wrote:
> Hi Tomasz,
>
> On 2017/1/3 15:41, Tomasz Nowicki wrote:
>> Hi,
>>
>> Can we merge patch 4 & 6 into one patch so that we keep refactoring part
>> as one piece ? I do not see a reason to keep them separate or have patch
>> 5 in between. You can refactor what needs to be refactored, add
>> necessary functions to iort.c and then support ACPI for
>> irq-gic-v3-its-platform-msi.c
>
> There are two functions here,
> - retrieve the dev id from IORT which was DT based only;
>
> - init the platform msi domain from MADT;
>
> For each of them split it into two steps,
> - refactor the code for ACPI later and it's easy for review
> because wen can easily to figure out it has functional
> change or not
>
> - add ACPI functionality
>
> Does it make sense?
It is up to Marc, but personally I prefer:
1. Refactor dev id retrieving and init function in one patch and
highlight no functional changes in changelog
2. Crate necessary infrastructure in iort.c
3. Then add ACPI support to irq-gic-v3-its-platform-msi.c
Thanks,
Tomasz
^ permalink raw reply
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