* + mm-readahead-increase-maximum-readahead-window.patch added to -mm tree
From: akpm @ 2017-10-04 22:21 UTC (permalink / raw)
To: jack, darrick.wong, david, torvalds, mm-commits
The patch titled
Subject: mm: readahead: increase maximum readahead window
has been added to the -mm tree. Its filename is
mm-readahead-increase-maximum-readahead-window.patch
This patch should soon appear at
http://ozlabs.org/~akpm/mmots/broken-out/mm-readahead-increase-maximum-readahead-window.patch
and later at
http://ozlabs.org/~akpm/mmotm/broken-out/mm-readahead-increase-maximum-readahead-window.patch
Before you just go and hit "reply", please:
a) Consider who else should be cc'ed
b) Prefer to cc a suitable mailing list as well
c) Ideally: find the original patch on the mailing list and do a
reply-to-all to that, adding suitable additional cc's
*** Remember to use Documentation/SubmitChecklist when testing your code ***
The -mm tree is included into linux-next and is updated
there every 3-4 working days
------------------------------------------------------
From: Jan Kara <jack@suse.cz>
Subject: mm: readahead: increase maximum readahead window
Increase default maximum allowed readahead window from 128 KB to 512 KB.
This improves performance for some workloads (see below for details) where
ability to scale readahead window to larger sizes allows for better total
throughput while chances for regression are rather low given readahead
window size is dynamically computed based on observation (and thus it
never grows large for workloads with a random read pattern).
Note that the same tuning can be done using udev rules or by manually
setting the sysctl parameter however we believe the new value is a better
default most users will want to use. As a data point we carry this patch
in SUSE kernels for over 8 years.
Some data from the last evaluation of this patch (on 4.4-based kernel, I
can rerun those tests on a newer kernel but nothing has changed in the
readahead area since 4.4). The patch was evaluated on two machines o a
UMA machine, 8 cores and rotary storage o A NUMA machine, 4 socket, 48
cores and SSD storage
Five basic tests were conducted;
1. paralleldd-single
paralleldd uses different instances of dd to access a single file and
write the contents to /dev/null. The performance of it depends on how
well readahead works for a single file. It's mostly sequential IO.
2. paralleldd-multi
Similar to test 1 except each instance of dd accesses a different file
so each instance of dd is accessing data sequentially but the timing
makes it look like random read IO.
3. pgbench-small
A standard init of pgbench and execution with a small data set
4. pgbench-large
A standard init of pgbench and execution with a large data set
5. bonnie++ with dataset sizes 2X RAM and in asyncronous mode
UMA paralleldd-single on ext3
4.4.0 4.4.0
vanilla readahead-v1r1
Amean Elapsd-1 5.42 ( 0.00%) 5.40 ( 0.50%)
Amean Elapsd-3 7.51 ( 0.00%) 5.54 ( 26.25%)
Amean Elapsd-5 7.15 ( 0.00%) 5.90 ( 17.46%)
Amean Elapsd-7 5.81 ( 0.00%) 5.61 ( 3.42%)
Amean Elapsd-8 6.05 ( 0.00%) 5.73 ( 5.36%)
Results speak for themselves, readahead is a major boost when there
are multiple readers of data. It's not displayed but system CPU
usage is overall. The IO stats support the results
4.4.0 4.4.0
vanillareadahead-v1r1
Mean sda-avgqusz 7.44 8.59
Mean sda-avgrqsz 279.77 722.52
Mean sda-await 31.95 48.82
Mean sda-r_await 3.32 11.58
Mean sda-w_await 127.51 119.60
Mean sda-svctm 1.47 3.46
Mean sda-rrqm 27.82 23.52
Mean sda-wrqm 4.52 5.00
It shows that the average request size is 2.5 times larger even
though the merging stats are similar. It's also interesting to
note that average wait times are higher but more IO is being
initiated per dd instance.
It's interesting to note that this is specific to ext3 and that xfs showed
a small regression with larger readahead.
UMA paralleldd-single on xfs
4.4.0 4.4.0
vanilla readahead-v1r1
Min Elapsd-1 6.91 ( 0.00%) 7.10 ( -2.75%)
Min Elapsd-3 6.77 ( 0.00%) 6.93 ( -2.36%)
Min Elapsd-5 6.82 ( 0.00%) 7.00 ( -2.64%)
Min Elapsd-7 6.84 ( 0.00%) 7.05 ( -3.07%)
Min Elapsd-8 7.02 ( 0.00%) 7.04 ( -0.28%)
Amean Elapsd-1 7.08 ( 0.00%) 7.20 ( -1.68%)
Amean Elapsd-3 7.03 ( 0.00%) 7.12 ( -1.40%)
Amean Elapsd-5 7.22 ( 0.00%) 7.38 ( -2.34%)
Amean Elapsd-7 7.07 ( 0.00%) 7.19 ( -1.75%)
Amean Elapsd-8 7.23 ( 0.00%) 7.23 ( -0.10%)
The IO stats are not displayed but show a similar ratio to ext3 and system
CPU usage is also lower. Hence, this slowdown is unexplained but may be
due to differences in XFS in the read path and how it locks even though
direct IO is not a factor. Tracing was not enabled to see what flags are
passed into xfs_ilock to see if the IO is all behind one lock but it's one
potential explanation.
UMA paralleldd-single on ext3
This showed nothing interesting as the test was too short-lived to draw
any conclusions. There was some difference in the kernels but it was
within the noise. The same applies for XFS.
UMA pgbench-small on ext3
This showed very little that was interesting. The database load time was
slower but by a very small margin. The actual transaction times were
highly variable and inconclusive.
NUMA pgbench-small on ext3
Load times are not reported but they completed 1.5% faster.
4.4.0 4.4.0
vanilla readahead-v1r1
Hmean 1 3000.54 ( 0.00%) 2895.28 ( -3.51%)
Hmean 8 20596.33 ( 0.00%) 19291.92 ( -6.33%)
Hmean 12 30760.68 ( 0.00%) 30019.58 ( -2.41%)
Hmean 24 74383.22 ( 0.00%) 73580.80 ( -1.08%)
Hmean 32 88377.30 ( 0.00%) 88928.70 ( 0.62%)
Hmean 48 88133.53 ( 0.00%) 96099.16 ( 9.04%)
Hmean 80 55981.37 ( 0.00%) 76886.10 ( 37.34%)
Hmean 112 74060.29 ( 0.00%) 87632.95 ( 18.33%)
Hmean 144 51331.50 ( 0.00%) 66135.77 ( 28.84%)
Hmean 172 44256.92 ( 0.00%) 63521.73 ( 43.53%)
Hmean 192 35942.74 ( 0.00%) 71121.35 ( 97.87%)
The impact here is substantial particularly for higher thread-counts.
It's interesting to note that there is an apparent regression for low
thread counts. In general, there was a high degree of variability but the
gains were all outside of the noise. In general, the io stats did not
show any particular pattern about request size as the workload is mostly
resident in memory. The real curiousity is that readahead should have had
little or no impact here as the data is mostly resident in memory.
Observing the transactions over time, there was a lot of variability and
the performance is likely dominated by whether the data happened to be
local or not. In itself, this test does not push for inclusion of the
patch due to the lack of IO but is included for completeness.
UMA pgbench-small on xfs
Similar observations to ext3 on the load times. The transaction times
were stable but showed no significant performance difference.
UMA pgbench-large on ext3
Database load times were slightly faster (3.36%). The transaction times
were slower on average, more variable but still very close to the noise.
UMA pgbench-large on xfs
No significant difference on either database load times or transactions.
UMA bonnie on ext3
4.4.0 4.4.0
vanilla readahead-v1r1
Hmean SeqOut Char 81079.98 ( 0.00%) 81172.05 ( 0.11%)
Hmean SeqOut Block 104416.12 ( 0.00%) 104116.24 ( -0.29%)
Hmean SeqOut Rewrite 44153.34 ( 0.00%) 44596.23 ( 1.00%)
Hmean SeqIn Char 88144.56 ( 0.00%) 91702.67 ( 4.04%)
Hmean SeqIn Block 134581.06 ( 0.00%) 137245.71 ( 1.98%)
Hmean Random seeks 258.46 ( 0.00%) 280.82 ( 8.65%)
Hmean SeqCreate ops 2.25 ( 0.00%) 2.25 ( 0.00%)
Hmean SeqCreate read 2.25 ( 0.00%) 2.25 ( 0.00%)
Hmean SeqCreate del 911.29 ( 0.00%) 880.24 ( -3.41%)
Hmean RandCreate ops 2.25 ( 0.00%) 2.25 ( 0.00%)
Hmean RandCreate read 2.00 ( 0.00%) 2.25 ( 12.50%)
Hmean RandCreate del 911.89 ( 0.00%) 878.80 ( -3.63%)
The difference in headline performance figures is marginal and well within noise.
The system CPU usage tells a slightly different story
4.4.0 4.4.0
vanillareadahead-v1r1
User 1817.53 1798.89
System 499.40 420.65
Elapsed 10692.67 10588.08
As do the IO stats
4.4.0 4.4.0
vanillareadahead-v1r1
Mean sda-avgqusz 1079.16 1083.35
Mean sda-avgrqsz 807.95 1225.08
Mean sda-await 7308.06 9647.13
Mean sda-r_await 119.04 133.27
Mean sda-w_await 19106.20 20255.41
Mean sda-svctm 4.67 7.02
Mean sda-rrqm 1.80 0.99
Mean sda-wrqm 5597.12 5723.32
NUMA bonnie on ext3
bonnie
4.4.0 4.4.0
vanilla readahead-v1r1
Hmean SeqOut Char 58660.72 ( 0.00%) 58930.39 ( 0.46%)
Hmean SeqOut Block 253950.92 ( 0.00%) 261466.37 ( 2.96%)
Hmean SeqOut Rewrite 151960.60 ( 0.00%) 161300.48 ( 6.15%)
Hmean SeqIn Char 57015.41 ( 0.00%) 55699.16 ( -2.31%)
Hmean SeqIn Block 600448.14 ( 0.00%) 627565.09 ( 4.52%)
Hmean Random seeks 0.00 ( 0.00%) 0.00 ( 0.00%)
Hmean SeqCreate ops 1.00 ( 0.00%) 1.00 ( 0.00%)
Hmean SeqCreate read 3.00 ( 0.00%) 3.00 ( 0.00%)
Hmean SeqCreate del 90.91 ( 0.00%) 79.88 (-12.14%)
Hmean RandCreate ops 1.00 ( 0.00%) 1.50 ( 50.00%)
Hmean RandCreate read 3.00 ( 0.00%) 3.00 ( 0.00%)
Hmean RandCreate del 92.95 ( 0.00%) 93.97 ( 1.10%)
The impact is small but in line with the UMA machine in a number of
details. As before, the CPU usage is lower even if the iostats show very
little differences overall.
Overall, the headline performance figures are mostly improved or show
little difference. There is a small anomaly with XFS that indicates it
may not always win there due to other factors. There is also the
possibility that a mostly random read workload that was larger than memory
with each read spanning multiple pages but less than the max readahead
window would suffer but the probability is low as the readahead window
should scale properly. On balance, this is a win -- particularly on the
large read workloads.
Link: http://lkml.kernel.org/r/20171004091205.468-1-jack@suse.cz
Signed-off-by: Jan Kara <jack@suse.cz>
Cc: "Darrick J. Wong" <darrick.wong@oracle.com>
Cc: Dave Chinner <david@fromorbit.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
include/linux/mm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -puN include/linux/mm.h~mm-readahead-increase-maximum-readahead-window include/linux/mm.h
--- a/include/linux/mm.h~mm-readahead-increase-maximum-readahead-window
+++ a/include/linux/mm.h
@@ -2248,7 +2248,7 @@ int __must_check write_one_page(struct p
void task_dirty_inc(struct task_struct *tsk);
/* readahead.c */
-#define VM_MAX_READAHEAD 128 /* kbytes */
+#define VM_MAX_READAHEAD 512 /* kbytes */
#define VM_MIN_READAHEAD 16 /* kbytes (includes current page) */
int force_page_cache_readahead(struct address_space *mapping, struct file *filp,
_
Patches currently in -mm which might be from jack@suse.cz are
mm-readahead-increase-maximum-readahead-window.patch
^ permalink raw reply
* Re: Maturity of GRUB on powerpc/ppc64?
From: Gabriel Paubert @ 2017-10-04 18:10 UTC (permalink / raw)
To: John Paul Adrian Glaubitz
Cc: Lennart Sorensen, Frank Scheiner, grub-devel,
debian-powerpc@lists.debian.org
In-Reply-To: <5643489a-d5d7-e508-c7a3-5a85deb4dbf1@physik.fu-berlin.de>
On Wed, Oct 04, 2017 at 06:36:33PM +0200, John Paul Adrian Glaubitz wrote:
> On 10/04/2017 06:23 PM, Lennart Sorensen wrote:
> > It is not a flag, it is a partition type. PPC PReP Boot is partition
> > type 0x41. Similar to how Linux is type 0x83 and Linux swap is type 0x82.
> >
> > I don't remember if it wants the boot flag set on it or not.
>
> Are you sure? The parted manual seems to say otherwise:
Of what? That it is partition type 0x41, 100%.
sudo fdisk -l (trimmed) on my machine:
Disk /dev/sdb: 931.5 GiB, 1000204886016 bytes, 1953525168 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: dos
Disk identifier: 0x75609d99
Device Boot Start End Sectors Size Id Type
/dev/sdb1 * 2048 18431 16384 8M 41 PPC PReP Boot
/dev/sdb2 18432 40978431 40960000 19.5G fd Linux raid autodetect
/dev/sdb3 40978432 1925138431 1884160000 898.4G fd Linux raid autodetect
/dev/sdb4 1925138432 1953523711 28385280 13.5G 82 Linux swap / Solaris
Disk /dev/sda: 931.5 GiB, 1000204886016 bytes, 1953525168 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: dos
Disk identifier: 0x1aa95e8f
Device Boot Start End Sectors Size Id Type
/dev/sda1 * 2048 18431 16384 8M 41 PPC PReP Boot
/dev/sda2 18432 40978431 40960000 19.5G fd Linux raid autodetect
/dev/sda3 40978432 1925138431 1884160000 898.4G fd Linux raid autodetect
/dev/sda4 1925138432 1953523711 28385280 13.5G 82 Linux swap / Solaris
(Both disks are in a RAID1 setup).
I believe it needs the boot flag, but some firmwares might decide to not
care about it.
Gabriel
^ permalink raw reply
* Re: [PATCH] nfp: convert nfp_eth_set_bit_config() into a macro
From: Jakub Kicinski @ 2017-10-04 22:22 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Joe Perches, David S . Miller, Simon Horman, Dirk van der Merwe,
oss-drivers, netdev, linux-kernel, Renato Golin, Manoj Gupta,
Guenter Roeck, Doug Anderson
In-Reply-To: <20171004184957.GO173745@google.com>
On Wed, 4 Oct 2017 11:49:57 -0700, Matthias Kaehlcke wrote:
> Hi Joe,
>
> El Wed, Oct 04, 2017 at 11:07:19AM -0700 Joe Perches ha dit:
>
> > On Tue, 2017-10-03 at 13:05 -0700, Matthias Kaehlcke wrote:
> > > nfp_eth_set_bit_config() is marked as __always_inline to allow gcc to
> > > identify the 'mask' parameter as known to be constant at compile time,
> > > which is required to use the FIELD_GET() macro.
> > >
> > > The forced inlining does the trick for gcc, but for kernel builds with
> > > clang it results in undefined symbols:
> >
> > Can't you use local different FIELD_PREP/FIELD_GET macros
> > with a different name without the BUILD_BUG tests?
> >
> > i.e.:
> >
> > #define NFP_FIELD_PREP(_mask, _val) \
> > ({ \
> > ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
> > })
> >
> > #define NFP_FIELD_GET(_mask, _reg) \
> > ({ \
> > (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
> > })
> >
> > Then the __always_inline can be removed from
> > nfp_eth_set_bit_config too.
>
> Thanks for the suggestion. This seems a viable alternative if David
> and the NFP owners can live without the extra checking provided by
> __BF_FIELD_CHECK.
The reason the __BF_FIELD_CHECK refuses to compile non-constant masks
is that it will require runtime ffs on the mask, which is potentially
costly. I would also feel quite stupid adding those macros to the nfp
driver, given that I specifically created the bitfield.h header to not
have to reimplement these in every driver I write/maintain.
Can you please test the patch I provided in the other reply?
^ permalink raw reply
* [Qemu-trivial] [PATCH] linux-user: Add random ioctls
From: Marco A L Barbosa @ 2017-10-04 22:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-trivial
[-- Attachment #1: Type: text/plain, Size: 2861 bytes --]
I don't know how (and if it is necessary) to add buf field to
rand_pool_info struct. See
https://github.com/torvalds/linux/blob/5924bbecd0267d87c24110cbe2041b5075173a25/include/uapi/linux/random.h#L17
Signed-off-by: Marco A L Barbosa <malbarbo@gmail.com>
---
linux-user/ioctls.h | 7 +++++++
linux-user/syscall.c | 1 +
linux-user/syscall_defs.h | 9 +++++++++
linux-user/syscall_types.h | 4 ++++
4 files changed, 21 insertions(+)
diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index e6997ff230..9240a83f30 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -173,6 +173,13 @@
IOCTL(SIOCGSTAMP, IOC_R, MK_PTR(MK_STRUCT(STRUCT_timeval)))
IOCTL(SIOCGSTAMPNS, IOC_R, MK_PTR(MK_STRUCT(STRUCT_timespec)))
+ IOCTL(RNDGETENTCNT, IOC_R, MK_PTR(TYPE_INT))
+ IOCTL(RNDADDTOENTCNT, IOC_W, MK_PTR(MK_STRUCT(STRUCT_rand_pool_info)))
+ IOCTL(RNDGETPOOL, IOC_R, MK_PTR(TYPE_INT))
+ IOCTL(RNDADDENTROPY, IOC_W, MK_PTR(MK_STRUCT(STRUCT_rand_pool_info)))
+ IOCTL(RNDZAPENTCNT, 0, TYPE_NULL)
+ IOCTL(RNDCLEARPOOL, 0, TYPE_NULL)
+
IOCTL(CDROMPAUSE, 0, TYPE_NULL)
IOCTL(CDROMSTART, 0, TYPE_NULL)
IOCTL(CDROMSTOP, 0, TYPE_NULL)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 9b6364a266..d4c21a557c 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -59,6 +59,7 @@ int __clone2(int (*fn)(void *), void *child_stack_base,
#include <linux/icmp.h>
#include <linux/icmpv6.h>
#include <linux/errqueue.h>
+#include <linux/random.h>
#include "qemu-common.h"
#ifdef CONFIG_TIMERFD
#include <sys/timerfd.h>
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 40c5027e93..d14fdd82ce 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -1060,6 +1060,15 @@ struct target_pollfd {
#define TARGET_SIOCGIWNAME 0x8B01 /* get name == wireless
protocol */
+/* From <linux/random.h> */
+
+#define TARGET_RNDGETENTCNT TARGET_IOR('R', 0x00, int)
+#define TARGET_RNDADDTOENTCNT TARGET_IOW('R', 0x01, int)
+#define TARGET_RNDGETPOOL TARGET_IOR('R', 0x02, struct rand_pool_info)
+#define TARGET_RNDADDENTROPY TARGET_IOW('R', 0x03, struct rand_pool_info)
+#define TARGET_RNDZAPENTCNT TARGET_IO('R', 0x04)
+#define TARGET_RNDCLEARPOOL TARGET_IO('R', 0x06)
+
/* From <linux/fs.h> */
#define TARGET_BLKROSET TARGET_IO(0x12,93) /* set device read-only (0 =
read-write) */
diff --git a/linux-user/syscall_types.h b/linux-user/syscall_types.h
index 24631b09be..2e2e000424 100644
--- a/linux-user/syscall_types.h
+++ b/linux-user/syscall_types.h
@@ -266,3 +266,7 @@ STRUCT(blkpg_ioctl_arg,
TYPE_INT, /* flags */
TYPE_INT, /* datalen */
TYPE_PTRVOID) /* data */
+
+STRUCT(rand_pool_info,
+ TYPE_INT, /* entropy_count */
+ TYPE_INT) /* buf_size */
--
2.11.0
--
Marco A L Barbosa
http://malbarbo.pro.br
--
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^ permalink raw reply related
* Re: [RFC 4/5] ext4: add fs freezing support on suspend/hibernation
From: Dave Chinner @ 2017-10-04 22:22 UTC (permalink / raw)
To: Theodore Ts'o, Luis R. Rodriguez, viro, bart.vanassche,
ming.lei, darrick.wong, jikos, rjw, pavel, len.brown,
linux-fsdevel, boris.ostrovsky, jgross, todd.e.brandt, nborisov,
jack, martin.petersen, ONeukum, oleksandr, oleg.b.antonyan,
linux-pm, linux-block, linux-xfs, linux-kernel
In-Reply-To: <20171004164839.zyfpx64qmmfv2jtx@thunk.org>
On Wed, Oct 04, 2017 at 12:48:39PM -0400, Theodore Ts'o wrote:
> On Wed, Oct 04, 2017 at 06:05:23PM +1100, Dave Chinner wrote:
> > Basically, before thawing filesystems the rest of the kernel
> > infrastructure needs to have been restarted. i.e. the order
> > needs to be:
> >
> > freeze userspace
> > freeze filesystems
> > freeze kernel threads
> > freeze workqueues
> >
> > thaw workqueues
> > thaw kernel threads
> > thaw filesystems
> > thaw userspace
> >
> > and it should end up that way.
> >
> > > Or if we have a network block device, or
> > > something else in the storage stack that needs to run a kernel thread
> > > context (or a workqueue, etc.) --- is the fact that userspace is
> > > frozen mean the scheduler is going to refuse to schedule()?
> >
> > No.
>
> Well, that's what the answer *should* be. I was asking what this
> patch series does, and given that Luis reported that with this patch
> series ext4_commit_super(sb, 1) is hanging, I have my suspicions about
> what the answer might be with this patch set. (Especially since the
> claimed goal of the patch set is, "kthread freezing with filesystem
> freeze/thaw".
There are know bugs in the patchset w.r.t. workqueues and kernel
threads, and IO completion requires workqueues and kernel threads to
be running correctly. Hence filesystem thaw needs to occur after
workqueues and kernel threads are thawed.
The existing code has this assumption - that filesystem will start
working again the moment workqueues and kernel threads are thawed,
but trying to do IO before that will not work. So it's the same
with freeze/thaw of filesystems - thaw of filesystems will not work
if the rest of the kernel machinery is still frozen...
Cheers,
Dave.
--
Dave Chinner
david@fromorbit.com
^ permalink raw reply
* Re: [PATCH] glib-2.0: Remove recommend shared-mime-info for MinGW
From: Burton, Ross @ 2017-10-04 22:23 UTC (permalink / raw)
To: Alistair Francis; +Cc: OE-core
In-Reply-To: <CAKmqyKN2b3nHMOTD-QS1-MchR6prLJAtr8_tn7-umWKm=6HB_Q@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1447 bytes --]
Already queued for master and probably rocko.
Ross
On 4 October 2017 at 22:50, Alistair Francis <alistair23@gmail.com> wrote:
> On Mon, Sep 25, 2017 at 3:56 PM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
> > Commit glib-2.0: recommend shared-mime-info
> > (51e4f9ca5368af5cefa26f4ca50b282e858982f8) broke compilation when cross
> > compiling for Windows. This patch removes the recommendation for
> > shared-mime-info when using MinGW cross compile.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> > Cc: Ross Burton <ross.burton@intel.com>
> > Cc: Richard Purdie <richard.purdie@linuxfoundation.org>
>
> Ping!
>
> Thanks,
> Alistair
>
> > ---
> > meta/recipes-core/glib-2.0/glib.inc | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/meta/recipes-core/glib-2.0/glib.inc
> b/meta/recipes-core/glib-2.0/glib.inc
> > index ce15ccefc3..8434b7dae3 100644
> > --- a/meta/recipes-core/glib-2.0/glib.inc
> > +++ b/meta/recipes-core/glib-2.0/glib.inc
> > @@ -74,6 +74,8 @@ FILES_${PN}-codegen = "${datadir}/glib-2.0/codegen/*.py
> \
> > FILES_${PN}-utils = "${bindir}/*"
> >
> > RRECOMMENDS_${PN} += "shared-mime-info"
> > +# When cross compiling for Windows we don't want to include this
> > +RRECOMMENDS_${PN}_remove_mingw32 = "shared-mime-info"
> >
> > ARM_INSTRUCTION_SET_armv4 = "arm"
> > ARM_INSTRUCTION_SET_armv5 = "arm"
> > --
> > 2.11.0
> >
>
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^ permalink raw reply
* RE: [PATCH v4 rdma-next 17/18] IB/core: Define 'ib' and 'roce' rdma_ah_attr types
From: Parav Pandit @ 2017-10-04 22:24 UTC (permalink / raw)
To: Don Hiatt, Dasaratharaman Chandramouli, Doug Ledford; +Cc: linux-rdma
In-Reply-To: <73561590-0d5e-54ba-a98a-d8c45f869955-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 2047 bytes --]
> -----Original Message-----
> From: Don Hiatt [mailto:don.hiatt@intel.com]
> Sent: Wednesday, October 04, 2017 5:15 PM
> To: Parav Pandit <parav@mellanox.com>; Dasaratharaman Chandramouli
> <dasaratharaman.chandramouli@intel.com>; Doug Ledford
> <dledford@redhat.com>
> Cc: linux-rdma <linux-rdma@vger.kernel.org>
> Subject: Re: [PATCH v4 rdma-next 17/18] IB/core: Define 'ib' and 'roce'
> rdma_ah_attr types
>
>
>
> On 10/4/2017 2:24 PM, Parav Pandit wrote:
> >> -----Original Message-----
> >> From: linux-rdma-owner@vger.kernel.org [mailto:linux-rdma-
> >> owner@vger.kernel.org] On Behalf Of Dasaratharaman Chandramouli
> >> Sent: Saturday, April 29, 2017 1:41 PM
> >> To: Doug Ledford <dledford@redhat.com>
> >> Cc: linux-rdma <linux-rdma@vger.kernel.org>
> >> Subject: [PATCH v4 rdma-next 17/18] IB/core: Define 'ib' and 'roce'
> >> rdma_ah_attr types
> >> +/*Get AH type */
> >> +static inline enum rdma_ah_attr_type rdma_ah_find_type(struct
> >> +ib_device
> >> *dev,
> >> + u32 port_num)
> >> +{
> >> + if ((rdma_protocol_roce(dev, port_num)) ||
> >> + (rdma_protocol_iwarp(dev, port_num)))
> >> + return RDMA_AH_ATTR_TYPE_ROCE;
> > Check for iWarp to define AH attribute type as RoCE appears error to me.
> > Taking quick look at i40iw and nes drivers appears to return -ENOSYS for
> i40iw_create_ah(), nes_create_ah.
> > Will you please submit a fix that avoids above iWarp check?
> >
> >
> i40iw_port_immutable sets the RDMA_CORE_PORT_IWARP immutable flag,
But when would someone create or initialize ah for iWarp port, given than create_ah is unsupported.
AH type of RoCE for iWarp, doesn't sound correct.
Is RoCE type of AH used on QP in iWarp that needs this check?
> hence the check. Are you having an issue?
No. I am refactoring some code and noticed this check.
This check can wrongly detects RoCE AH on iwarp port, isn't it?
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^ permalink raw reply
* Re: [PATCH v1] pci: introduce for_each_pci_bridge() helper
From: Bjorn Helgaas @ 2017-10-04 22:24 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Rafael J. Wysocki, linux-acpi, Bjorn Helgaas, linux-pci,
Scott Murray, Lukas Wunner, Keith Busch, Mika Westerberg
In-Reply-To: <20170929192123.24817-1-andriy.shevchenko@linux.intel.com>
On Fri, Sep 29, 2017 at 10:21:23PM +0300, Andy Shevchenko wrote:
> It seems often the following pattern has been used
>
> list_for_each_entry(dev, &bus->devices, bus_list) {
> if (pci_is_bridge(dev)) {
> ...
> }
> }
>
> Here for_each_pci_bridge() helper is introduced to make that code better
> to write and read by lowing indentation level. It also saves one or few
> lines of code in each occurrence.
>
> Convert PCI core parts here at the same time.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Applied to pci/misc for v4.15, thanks!
> ---
> drivers/pci/hotplug/acpiphp_glue.c | 15 ++++++---------
> drivers/pci/hotplug/cpci_hotplug_pci.c | 7 ++-----
> drivers/pci/hotplug/pciehp_pci.c | 5 ++---
> drivers/pci/hotplug/shpchp_pci.c | 6 ++----
> drivers/pci/probe.c | 6 ++----
> drivers/pci/setup-bus.c | 7 +++----
> include/linux/pci.h | 4 ++++
> 7 files changed, 21 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
> index 5ed2dcaa8e27..5db6f1839dad 100644
> --- a/drivers/pci/hotplug/acpiphp_glue.c
> +++ b/drivers/pci/hotplug/acpiphp_glue.c
> @@ -462,18 +462,15 @@ static void enable_slot(struct acpiphp_slot *slot)
> acpiphp_rescan_slot(slot);
> max = acpiphp_max_busnr(bus);
> for (pass = 0; pass < 2; pass++) {
> - list_for_each_entry(dev, &bus->devices, bus_list) {
> + for_each_pci_bridge(dev, bus) {
> if (PCI_SLOT(dev->devfn) != slot->device)
> continue;
>
> - if (pci_is_bridge(dev)) {
> - max = pci_scan_bridge(bus, dev, max, pass);
> - if (pass && dev->subordinate) {
> - check_hotplug_bridge(slot, dev);
> - pcibios_resource_survey_bus(dev->subordinate);
> - __pci_bus_size_bridges(dev->subordinate,
> - &add_list);
> - }
> + max = pci_scan_bridge(bus, dev, max, pass);
> + if (pass && dev->subordinate) {
> + check_hotplug_bridge(slot, dev);
> + pcibios_resource_survey_bus(dev->subordinate);
> + __pci_bus_size_bridges(dev->subordinate, &add_list);
> }
> }
> }
> diff --git a/drivers/pci/hotplug/cpci_hotplug_pci.c b/drivers/pci/hotplug/cpci_hotplug_pci.c
> index 80c80017197d..f616358fa938 100644
> --- a/drivers/pci/hotplug/cpci_hotplug_pci.c
> +++ b/drivers/pci/hotplug/cpci_hotplug_pci.c
> @@ -286,14 +286,11 @@ int cpci_configure_slot(struct slot *slot)
> }
> parent = slot->dev->bus;
>
> - list_for_each_entry(dev, &parent->devices, bus_list) {
> - if (PCI_SLOT(dev->devfn) != PCI_SLOT(slot->devfn))
> - continue;
> - if (pci_is_bridge(dev))
> + for_each_pci_bridge(dev, parent) {
> + if (PCI_SLOT(dev->devfn) == PCI_SLOT(slot->devfn))
> pci_hp_add_bridge(dev);
> }
>
> -
> pci_assign_unassigned_bridge_resources(parent->self);
>
> pci_bus_add_devices(parent);
> diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
> index 19f30a9f461d..c3af027ee1a6 100644
> --- a/drivers/pci/hotplug/pciehp_pci.c
> +++ b/drivers/pci/hotplug/pciehp_pci.c
> @@ -60,9 +60,8 @@ int pciehp_configure_device(struct slot *p_slot)
> goto out;
> }
>
> - list_for_each_entry(dev, &parent->devices, bus_list)
> - if (pci_is_bridge(dev))
> - pci_hp_add_bridge(dev);
> + for_each_pci_bridge(dev, parent)
> + pci_hp_add_bridge(dev);
>
> pci_assign_unassigned_bridge_resources(bridge);
> pcie_bus_configure_settings(parent);
> diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c
> index f8cd3a27e351..ea63db58b4b1 100644
> --- a/drivers/pci/hotplug/shpchp_pci.c
> +++ b/drivers/pci/hotplug/shpchp_pci.c
> @@ -61,10 +61,8 @@ int shpchp_configure_device(struct slot *p_slot)
> goto out;
> }
>
> - list_for_each_entry(dev, &parent->devices, bus_list) {
> - if (PCI_SLOT(dev->devfn) != p_slot->device)
> - continue;
> - if (pci_is_bridge(dev))
> + for_each_pci_bridge(dev, parent) {
> + if (PCI_SLOT(dev->devfn) == p_slot->device)
> pci_hp_add_bridge(dev);
> }
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index ff94b69738a8..cdc2f83c11c5 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -2421,10 +2421,8 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
> }
>
> for (pass = 0; pass < 2; pass++)
> - list_for_each_entry(dev, &bus->devices, bus_list) {
> - if (pci_is_bridge(dev))
> - max = pci_scan_bridge(bus, dev, max, pass);
> - }
> + for_each_pci_bridge(dev, bus)
> + max = pci_scan_bridge(bus, dev, max, pass);
>
> /*
> * Make sure a hotplug bridge has at least the minimum requested
> diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
> index 958da7db9033..7ca03407404c 100644
> --- a/drivers/pci/setup-bus.c
> +++ b/drivers/pci/setup-bus.c
> @@ -1921,10 +1921,9 @@ void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
> want additional resources */
>
> down_read(&pci_bus_sem);
> - list_for_each_entry(dev, &bus->devices, bus_list)
> - if (pci_is_bridge(dev) && pci_has_subordinate(dev))
> - __pci_bus_size_bridges(dev->subordinate,
> - &add_list);
> + for_each_pci_bridge(dev, bus)
> + if (pci_has_subordinate(dev))
> + __pci_bus_size_bridges(dev->subordinate, &add_list);
> up_read(&pci_bus_sem);
> __pci_bus_assign_resources(bus, &add_list, NULL);
> BUG_ON(!list_empty(&add_list));
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index f4f8ee5a7362..3dbe947b4152 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -596,6 +596,10 @@ static inline bool pci_is_bridge(struct pci_dev *dev)
> dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
> }
>
> +#define for_each_pci_bridge(dev, bus) \
> + list_for_each_entry(dev, &bus->devices, bus_list) \
> + if (!pci_is_bridge(dev)) {} else
> +
> static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
> {
> dev = pci_physfn(dev);
> --
> 2.14.2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [RESEND][PATCH 0/7] Fix i.MX7D OCOTP write support
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: linux-arm-kernel
(Resend: I may have missed Philip Zabel on the first send - apologies if
that is the case Philip.)
The current OCOTP driver added support for i.MX7 read access and then added
support for i.MX6 write access. Between the two commits the fact that the
added write routine was only appropriate for i.MX6 was missed.
As a result its certain that attempting to write i.MX7 OTP fuses on Linux
would fail as the destination address on i.MX7 is different to i.MX6.
Without the update to the i.MX7 setup and hold timings it's not clear that
a write operation would actually do any writing which means the bad
addressing on i.MX7 might not actually destroy the wrong OTP fuses, it
probably would just fail to do anything, understandably I haven't
experimented with knowingly bad values for one-time-programmable fuses.
This series fixes the gap by:
1. Switching off OTP writing for i.MX7
2. Adding in support for the i.MX7 way of doing things
3. Switching OTP write support back on for i.MX7
There's an additional small fix for the naming of the module then to
indicate it works for i.MX7 as well as for i.MX6.
Bryan O'Donoghue (7):
nvmem: imx-ocotp: Restrict OTP write to IMX6 processors
nvmem: imx-ocotp: Pass parameters via a struct
nvmem: imx-ocotp: Add support for banked OTP addressing
nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated function
nvmem: imx-ocotp: Add i.MX7D timing write clock setup support
nvmem: imx-ocotp: Enable i.MX7D OTP write support
nvmem: imx-ocotp: Update module description
drivers/nvmem/imx-ocotp.c | 191 +++++++++++++++++++++++++++++++++++++---------
1 file changed, 156 insertions(+), 35 deletions(-)
--
2.7.4
^ permalink raw reply
* [RESEND][PATCH 1/7] nvmem: imx-ocotp: Restrict OTP write to IMX6 processors
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
i.MX7S/D have a different scheme for addressing the OTP registers inside
the OCOTP block. Currently it's possible to address the wrong OTP registers
given the disparity between IMX6 and IMX7 OTP addressing.
Since OTP programming is one-time destructive its important we restrict
this interface ASAP.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 193ca8f..17d160f 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -347,6 +347,8 @@ static int imx_ocotp_probe(struct platform_device *pdev)
imx_ocotp_nvmem_config.dev = dev;
imx_ocotp_nvmem_config.priv = priv;
priv->config = &imx_ocotp_nvmem_config;
+ if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx7d-ocotp"))
+ imx_ocotp_nvmem_config.read_only = true;
nvmem = nvmem_register(&imx_ocotp_nvmem_config);
if (IS_ERR(nvmem))
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 2/7] nvmem: imx-ocotp: Pass parameters via a struct
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
It will be useful in later patches to know the register access mode and
bit-shift to apply to a given input offset.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 17d160f..fed76a4 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -53,11 +53,15 @@
static DEFINE_MUTEX(ocotp_mutex);
+struct octp_params {
+ unsigned int nregs;
+};
+
struct ocotp_priv {
struct device *dev;
struct clk *clk;
void __iomem *base;
- unsigned int nregs;
+ struct octp_params *params;
struct nvmem_config *config;
};
@@ -121,8 +125,8 @@ static int imx_ocotp_read(void *context, unsigned int offset,
index = offset >> 2;
count = bytes >> 2;
- if (count > (priv->nregs - index))
- count = priv->nregs - index;
+ if (count > (priv->params->nregs - index))
+ count = priv->params->nregs - index;
mutex_lock(&ocotp_mutex);
@@ -308,12 +312,20 @@ static struct nvmem_config imx_ocotp_nvmem_config = {
.reg_write = imx_ocotp_write,
};
+static const struct octp_params params[] = {
+ { .nregs = 128},
+ { .nregs = 64},
+ { .nregs = 128},
+ { .nregs = 128},
+ { .nregs = 64},
+};
+
static const struct of_device_id imx_ocotp_dt_ids[] = {
- { .compatible = "fsl,imx6q-ocotp", (void *)128 },
- { .compatible = "fsl,imx6sl-ocotp", (void *)64 },
- { .compatible = "fsl,imx6sx-ocotp", (void *)128 },
- { .compatible = "fsl,imx6ul-ocotp", (void *)128 },
- { .compatible = "fsl,imx7d-ocotp", (void *)64 },
+ { .compatible = "fsl,imx6q-ocotp", (void *)¶ms[0] },
+ { .compatible = "fsl,imx6sl-ocotp", (void *)¶ms[1] },
+ { .compatible = "fsl,imx6sx-ocotp", (void *)¶ms[2] },
+ { .compatible = "fsl,imx6ul-ocotp", (void *)¶ms[3] },
+ { .compatible = "fsl,imx7d-ocotp", (void *)¶ms[4] },
{ },
};
MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
@@ -342,8 +354,8 @@ static int imx_ocotp_probe(struct platform_device *pdev)
return PTR_ERR(priv->clk);
of_id = of_match_device(imx_ocotp_dt_ids, dev);
- priv->nregs = (unsigned long)of_id->data;
- imx_ocotp_nvmem_config.size = 4 * priv->nregs;
+ priv->params = (struct octp_params *)of_id->data;
+ imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
imx_ocotp_nvmem_config.dev = dev;
imx_ocotp_nvmem_config.priv = priv;
priv->config = &imx_ocotp_nvmem_config;
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 3/7] nvmem: imx-ocotp: Add support for banked OTP addressing
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
The i.MX7S/D takes the bank address in the CTRLn.ADDR field and the data
value in one of the DATAx {0, 1, 2, 3} register fields. The current write
routine is based on writing the CTRLn.ADDR field and writing a single DATA
register only.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 71 +++++++++++++++++++++++++++++++++++++++++------
1 file changed, 62 insertions(+), 9 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index fed76a4..8034937 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -40,7 +40,10 @@
#define IMX_OCOTP_ADDR_CTRL_SET 0x0004
#define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
#define IMX_OCOTP_ADDR_TIMING 0x0010
-#define IMX_OCOTP_ADDR_DATA 0x0020
+#define IMX_OCOTP_ADDR_DATA0 0x0020
+#define IMX_OCOTP_ADDR_DATA1 0x0030
+#define IMX_OCOTP_ADDR_DATA2 0x0040
+#define IMX_OCOTP_ADDR_DATA3 0x0050
#define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F
#define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
@@ -55,6 +58,8 @@ static DEFINE_MUTEX(ocotp_mutex);
struct octp_params {
unsigned int nregs;
+ bool banked;
+ unsigned int regs_per_bank;
};
struct ocotp_priv {
@@ -176,6 +181,7 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
u32 timing = 0;
u32 ctrl;
u8 waddr;
+ u8 word = 0;
/* allow only writing one complete OTP word at a time */
if ((bytes != priv->config->word_size) ||
@@ -228,8 +234,22 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
* description. Both the unlock code and address can be written in the
* same operation.
*/
- /* OTP write/read address specifies one of 128 word address locations */
- waddr = offset / 4;
+ if (priv->params->banked) {
+ /*
+ * In banked mode the OTP register bank goes into waddr see
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
+ * 6.4.3.1
+ */
+ offset = offset / priv->config->word_size;
+ waddr = offset / priv->params->regs_per_bank;
+ word = offset & (priv->params->regs_per_bank - 1);
+ } else {
+ /*
+ * OTP write/read address specifies one of 128 word address
+ * locations
+ */
+ waddr = offset / 4;
+ }
ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR;
@@ -255,8 +275,41 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
* shift right (with zero fill). This shifting is required to program
* the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
* modified.
+ * Note: on i.MX7 there are four data fields to write for banked write
+ * with the fuse blowing operation only taking place after data0
+ * has been written. This is why data0 must always be the last
+ * register written.
*/
- writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA);
+ if (!priv->params->banked) {
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
+ } else {
+ switch (word) {
+ case 0:
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
+ break;
+ case 1:
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
+ break;
+ case 2:
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
+ break;
+ case 3:
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
+ break;
+ }
+ }
/* 47.4.1.4.5
* Once complete, the controller will clear BUSY. A write request to a
@@ -313,11 +366,11 @@ static struct nvmem_config imx_ocotp_nvmem_config = {
};
static const struct octp_params params[] = {
- { .nregs = 128},
- { .nregs = 64},
- { .nregs = 128},
- { .nregs = 128},
- { .nregs = 64},
+ { .nregs = 128, .banked = false, .regs_per_bank = 0},
+ { .nregs = 64, .banked = false, .regs_per_bank = 0},
+ { .nregs = 128, .banked = false, .regs_per_bank = 0},
+ { .nregs = 128, .banked = false, .regs_per_bank = 0},
+ { .nregs = 64, .banked = true, .regs_per_bank = 4},
};
static const struct of_device_id imx_ocotp_dt_ids[] = {
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 4/7] nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated function
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
The i.MX7S/D has a different set of timing requirements, as a pre-cursor to
adding the i.MX7 timing parameters, move the i.MX6 stuff to a dedicated
function.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 47 +++++++++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 8034937..0cd7e03 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -169,6 +169,31 @@ static int imx_ocotp_read(void *context, unsigned int offset,
return ret;
}
+static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
+{
+ unsigned long clk_rate = 0;
+ unsigned long strobe_read, relax, strobe_prog;
+ u32 timing = 0;
+
+ /* 47.3.1.3.1
+ * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
+ * fields with timing values to match the current frequency of the
+ * ipg_clk. OTP writes will work at maximum bus frequencies as long
+ * as the HW_OCOTP_TIMING parameters are set correctly.
+ */
+ clk_rate = clk_get_rate(priv->clk);
+
+ relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
+ strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
+ strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
+
+ timing = strobe_prog & 0x00000FFF;
+ timing |= (relax << 12) & 0x0000F000;
+ timing |= (strobe_read << 16) & 0x003F0000;
+
+ writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
+}
+
static int imx_ocotp_write(void *context, unsigned int offset, void *val,
size_t bytes)
{
@@ -176,9 +201,6 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
u32 *buf = val;
int ret;
- unsigned long clk_rate = 0;
- unsigned long strobe_read, relax, strobe_prog;
- u32 timing = 0;
u32 ctrl;
u8 waddr;
u8 word = 0;
@@ -197,23 +219,8 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
return ret;
}
- /* 47.3.1.3.1
- * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
- * fields with timing values to match the current frequency of the
- * ipg_clk. OTP writes will work at maximum bus frequencies as long
- * as the HW_OCOTP_TIMING parameters are set correctly.
- */
- clk_rate = clk_get_rate(priv->clk);
-
- relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
- strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
- strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
-
- timing = strobe_prog & 0x00000FFF;
- timing |= (relax << 12) & 0x0000F000;
- timing |= (strobe_read << 16) & 0x003F0000;
-
- writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
+ /* Setup the write timing values */
+ imx_ocotp_set_imx6_timing(priv);
/* 47.3.1.3.2
* Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 5/7] nvmem: imx-ocotp: Add i.MX7D timing write clock setup support
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
This patch adds logic to correctly setup the write timing parameters
when blowing an OTP fuse for the i.MX7S/D.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 61 ++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 55 insertions(+), 6 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 0cd7e03..40a1669 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -51,6 +51,7 @@
#define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
#define DEF_RELAX 20 /* > 16.5ns */
+#define DEF_FSOURCE 1001
#define IMX_OCOTP_WR_UNLOCK 0x3E770000
#define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
@@ -60,6 +61,7 @@ struct octp_params {
unsigned int nregs;
bool banked;
unsigned int regs_per_bank;
+ bool mx7_timing;
};
struct ocotp_priv {
@@ -194,6 +196,25 @@ static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
}
+static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
+{
+ unsigned long clk_rate = 0;
+ unsigned long fsource, strobe_prog;
+ u32 timing = 0;
+
+ /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
+ * 6.4.3.3
+ */
+ clk_rate = clk_get_rate(priv->clk);
+ fsource = DIV_ROUND_UP(((clk_rate / 1000) * DEF_FSOURCE), 1000000) + 1;
+ strobe_prog = ((clk_rate * 10) / 1000000) + 1;
+
+ timing = strobe_prog & 0x00000FFF;
+ timing |= (fsource << 12) & 0x000FF000;
+
+ writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
+}
+
static int imx_ocotp_write(void *context, unsigned int offset, void *val,
size_t bytes)
{
@@ -220,7 +241,10 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
}
/* Setup the write timing values */
- imx_ocotp_set_imx6_timing(priv);
+ if (priv->params->mx7_timing)
+ imx_ocotp_set_imx7_timing(priv);
+ else
+ imx_ocotp_set_imx6_timing(priv);
/* 47.3.1.3.2
* Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
@@ -373,11 +397,36 @@ static struct nvmem_config imx_ocotp_nvmem_config = {
};
static const struct octp_params params[] = {
- { .nregs = 128, .banked = false, .regs_per_bank = 0},
- { .nregs = 64, .banked = false, .regs_per_bank = 0},
- { .nregs = 128, .banked = false, .regs_per_bank = 0},
- { .nregs = 128, .banked = false, .regs_per_bank = 0},
- { .nregs = 64, .banked = true, .regs_per_bank = 4},
+ {
+ .nregs = 128,
+ .banked = false,
+ .regs_per_bank = 0,
+ .mx7_timing = false
+ },
+ {
+ .nregs = 64,
+ .banked = false,
+ .regs_per_bank = 0,
+ .mx7_timing = false
+ },
+ {
+ .nregs = 128,
+ .banked = false,
+ .regs_per_bank = 0,
+ .mx7_timing = false
+ },
+ {
+ .nregs = 128,
+ .banked = false,
+ .regs_per_bank = 0,
+ .mx7_timing = false
+ },
+ {
+ .nregs = 64,
+ .banked = true,
+ .regs_per_bank = 4,
+ .mx7_timing = true
+ },
};
static const struct of_device_id imx_ocotp_dt_ids[] = {
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 6/7] nvmem: imx-ocotp: Enable i.MX7D OTP write support
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
After applying patches for both banked access and write timings we can
re-enable the OTP write interface on i.MX7D processors.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 40a1669..5b0f7b5 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -468,8 +468,6 @@ static int imx_ocotp_probe(struct platform_device *pdev)
imx_ocotp_nvmem_config.dev = dev;
imx_ocotp_nvmem_config.priv = priv;
priv->config = &imx_ocotp_nvmem_config;
- if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx7d-ocotp"))
- imx_ocotp_nvmem_config.read_only = true;
nvmem = nvmem_register(&imx_ocotp_nvmem_config);
if (IS_ERR(nvmem))
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 7/7] nvmem: imx-ocotp: Update module description
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
This imx-ocotp driver encapsulates support for a subset of both i.MX6 and
i.MX7 processors. Update the module description to reflect.
Fixes: 711d45477931 ("nvmem: octop: Add i.MX7D support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 5b0f7b5..a58a80b 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -496,5 +496,5 @@ static struct platform_driver imx_ocotp_driver = {
module_platform_driver(imx_ocotp_driver);
MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
-MODULE_DESCRIPTION("i.MX6 OCOTP fuse box driver");
+MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 0/7] Fix i.MX7D OCOTP write support
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: richard.leitner, srinivas.kandagatla, axel.lin, ping.bai,
d.schultz, peng.fan, van.freenix, p.zabel
Cc: linux-kernel, linux-arm-kernel, pure.logic
(Resend: I may have missed Philip Zabel on the first send - apologies if
that is the case Philip.)
The current OCOTP driver added support for i.MX7 read access and then added
support for i.MX6 write access. Between the two commits the fact that the
added write routine was only appropriate for i.MX6 was missed.
As a result its certain that attempting to write i.MX7 OTP fuses on Linux
would fail as the destination address on i.MX7 is different to i.MX6.
Without the update to the i.MX7 setup and hold timings it's not clear that
a write operation would actually do any writing which means the bad
addressing on i.MX7 might not actually destroy the wrong OTP fuses, it
probably would just fail to do anything, understandably I haven't
experimented with knowingly bad values for one-time-programmable fuses.
This series fixes the gap by:
1. Switching off OTP writing for i.MX7
2. Adding in support for the i.MX7 way of doing things
3. Switching OTP write support back on for i.MX7
There's an additional small fix for the naming of the module then to
indicate it works for i.MX7 as well as for i.MX6.
Bryan O'Donoghue (7):
nvmem: imx-ocotp: Restrict OTP write to IMX6 processors
nvmem: imx-ocotp: Pass parameters via a struct
nvmem: imx-ocotp: Add support for banked OTP addressing
nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated function
nvmem: imx-ocotp: Add i.MX7D timing write clock setup support
nvmem: imx-ocotp: Enable i.MX7D OTP write support
nvmem: imx-ocotp: Update module description
drivers/nvmem/imx-ocotp.c | 191 +++++++++++++++++++++++++++++++++++++---------
1 file changed, 156 insertions(+), 35 deletions(-)
--
2.7.4
^ permalink raw reply
* [RESEND][PATCH 1/7] nvmem: imx-ocotp: Restrict OTP write to IMX6 processors
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: richard.leitner, srinivas.kandagatla, axel.lin, ping.bai,
d.schultz, peng.fan, van.freenix, p.zabel
Cc: linux-kernel, linux-arm-kernel, pure.logic
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
i.MX7S/D have a different scheme for addressing the OTP registers inside
the OCOTP block. Currently it's possible to address the wrong OTP registers
given the disparity between IMX6 and IMX7 OTP addressing.
Since OTP programming is one-time destructive its important we restrict
this interface ASAP.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 193ca8f..17d160f 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -347,6 +347,8 @@ static int imx_ocotp_probe(struct platform_device *pdev)
imx_ocotp_nvmem_config.dev = dev;
imx_ocotp_nvmem_config.priv = priv;
priv->config = &imx_ocotp_nvmem_config;
+ if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx7d-ocotp"))
+ imx_ocotp_nvmem_config.read_only = true;
nvmem = nvmem_register(&imx_ocotp_nvmem_config);
if (IS_ERR(nvmem))
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 2/7] nvmem: imx-ocotp: Pass parameters via a struct
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: richard.leitner, srinivas.kandagatla, axel.lin, ping.bai,
d.schultz, peng.fan, van.freenix, p.zabel
Cc: linux-kernel, linux-arm-kernel, pure.logic
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
It will be useful in later patches to know the register access mode and
bit-shift to apply to a given input offset.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 17d160f..fed76a4 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -53,11 +53,15 @@
static DEFINE_MUTEX(ocotp_mutex);
+struct octp_params {
+ unsigned int nregs;
+};
+
struct ocotp_priv {
struct device *dev;
struct clk *clk;
void __iomem *base;
- unsigned int nregs;
+ struct octp_params *params;
struct nvmem_config *config;
};
@@ -121,8 +125,8 @@ static int imx_ocotp_read(void *context, unsigned int offset,
index = offset >> 2;
count = bytes >> 2;
- if (count > (priv->nregs - index))
- count = priv->nregs - index;
+ if (count > (priv->params->nregs - index))
+ count = priv->params->nregs - index;
mutex_lock(&ocotp_mutex);
@@ -308,12 +312,20 @@ static struct nvmem_config imx_ocotp_nvmem_config = {
.reg_write = imx_ocotp_write,
};
+static const struct octp_params params[] = {
+ { .nregs = 128},
+ { .nregs = 64},
+ { .nregs = 128},
+ { .nregs = 128},
+ { .nregs = 64},
+};
+
static const struct of_device_id imx_ocotp_dt_ids[] = {
- { .compatible = "fsl,imx6q-ocotp", (void *)128 },
- { .compatible = "fsl,imx6sl-ocotp", (void *)64 },
- { .compatible = "fsl,imx6sx-ocotp", (void *)128 },
- { .compatible = "fsl,imx6ul-ocotp", (void *)128 },
- { .compatible = "fsl,imx7d-ocotp", (void *)64 },
+ { .compatible = "fsl,imx6q-ocotp", (void *)¶ms[0] },
+ { .compatible = "fsl,imx6sl-ocotp", (void *)¶ms[1] },
+ { .compatible = "fsl,imx6sx-ocotp", (void *)¶ms[2] },
+ { .compatible = "fsl,imx6ul-ocotp", (void *)¶ms[3] },
+ { .compatible = "fsl,imx7d-ocotp", (void *)¶ms[4] },
{ },
};
MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
@@ -342,8 +354,8 @@ static int imx_ocotp_probe(struct platform_device *pdev)
return PTR_ERR(priv->clk);
of_id = of_match_device(imx_ocotp_dt_ids, dev);
- priv->nregs = (unsigned long)of_id->data;
- imx_ocotp_nvmem_config.size = 4 * priv->nregs;
+ priv->params = (struct octp_params *)of_id->data;
+ imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
imx_ocotp_nvmem_config.dev = dev;
imx_ocotp_nvmem_config.priv = priv;
priv->config = &imx_ocotp_nvmem_config;
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 5/7] nvmem: imx-ocotp: Add i.MX7D timing write clock setup support
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: richard.leitner, srinivas.kandagatla, axel.lin, ping.bai,
d.schultz, peng.fan, van.freenix, p.zabel
Cc: linux-kernel, linux-arm-kernel, pure.logic
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
This patch adds logic to correctly setup the write timing parameters
when blowing an OTP fuse for the i.MX7S/D.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 61 ++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 55 insertions(+), 6 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 0cd7e03..40a1669 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -51,6 +51,7 @@
#define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
#define DEF_RELAX 20 /* > 16.5ns */
+#define DEF_FSOURCE 1001
#define IMX_OCOTP_WR_UNLOCK 0x3E770000
#define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
@@ -60,6 +61,7 @@ struct octp_params {
unsigned int nregs;
bool banked;
unsigned int regs_per_bank;
+ bool mx7_timing;
};
struct ocotp_priv {
@@ -194,6 +196,25 @@ static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
}
+static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
+{
+ unsigned long clk_rate = 0;
+ unsigned long fsource, strobe_prog;
+ u32 timing = 0;
+
+ /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
+ * 6.4.3.3
+ */
+ clk_rate = clk_get_rate(priv->clk);
+ fsource = DIV_ROUND_UP(((clk_rate / 1000) * DEF_FSOURCE), 1000000) + 1;
+ strobe_prog = ((clk_rate * 10) / 1000000) + 1;
+
+ timing = strobe_prog & 0x00000FFF;
+ timing |= (fsource << 12) & 0x000FF000;
+
+ writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
+}
+
static int imx_ocotp_write(void *context, unsigned int offset, void *val,
size_t bytes)
{
@@ -220,7 +241,10 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
}
/* Setup the write timing values */
- imx_ocotp_set_imx6_timing(priv);
+ if (priv->params->mx7_timing)
+ imx_ocotp_set_imx7_timing(priv);
+ else
+ imx_ocotp_set_imx6_timing(priv);
/* 47.3.1.3.2
* Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
@@ -373,11 +397,36 @@ static struct nvmem_config imx_ocotp_nvmem_config = {
};
static const struct octp_params params[] = {
- { .nregs = 128, .banked = false, .regs_per_bank = 0},
- { .nregs = 64, .banked = false, .regs_per_bank = 0},
- { .nregs = 128, .banked = false, .regs_per_bank = 0},
- { .nregs = 128, .banked = false, .regs_per_bank = 0},
- { .nregs = 64, .banked = true, .regs_per_bank = 4},
+ {
+ .nregs = 128,
+ .banked = false,
+ .regs_per_bank = 0,
+ .mx7_timing = false
+ },
+ {
+ .nregs = 64,
+ .banked = false,
+ .regs_per_bank = 0,
+ .mx7_timing = false
+ },
+ {
+ .nregs = 128,
+ .banked = false,
+ .regs_per_bank = 0,
+ .mx7_timing = false
+ },
+ {
+ .nregs = 128,
+ .banked = false,
+ .regs_per_bank = 0,
+ .mx7_timing = false
+ },
+ {
+ .nregs = 64,
+ .banked = true,
+ .regs_per_bank = 4,
+ .mx7_timing = true
+ },
};
static const struct of_device_id imx_ocotp_dt_ids[] = {
--
2.7.4
^ permalink raw reply related
* + kbuild-fix-optimization-level-choice-default.patch added to -mm tree
From: akpm @ 2017-10-04 22:25 UTC (permalink / raw)
To: ulfalizer, arnd, daniel, keescook, nicolas.pitre, paulmck, tglx,
tj, mm-commits
The patch titled
Subject: kbuild: fix optimization level choice default
has been added to the -mm tree. Its filename is
kbuild-fix-optimization-level-choice-default.patch
This patch should soon appear at
http://ozlabs.org/~akpm/mmots/broken-out/kbuild-fix-optimization-level-choice-default.patch
and later at
http://ozlabs.org/~akpm/mmotm/broken-out/kbuild-fix-optimization-level-choice-default.patch
Before you just go and hit "reply", please:
a) Consider who else should be cc'ed
b) Prefer to cc a suitable mailing list as well
c) Ideally: find the original patch on the mailing list and do a
reply-to-all to that, adding suitable additional cc's
*** Remember to use Documentation/SubmitChecklist when testing your code ***
The -mm tree is included into linux-next and is updated
there every 3-4 working days
------------------------------------------------------
From: Ulf Magnusson <ulfalizer@gmail.com>
Subject: kbuild: fix optimization level choice default
The choice containing the CC_OPTIMIZE_FOR_PERFORMANCE symbol accidentally
added a "CONFIG_" prefix when trying to make it the default, selecting an
undefined symbol as the default.
The mistake is harmless here: Since the default symbol is not visible, the
choice falls back on using the visible symbol as the default instead,
which is CC_OPTIMIZE_FOR_PERFORMANCE, as intended.
A patch that makes Kconfig print a warning in this case has been submitted
separately: http://www.spinics.net/lists/linux-kbuild/msg15566.html
Link: http://lkml.kernel.org/r/1507074806-21577-1-git-send-email-ulfalizer@gmail.com
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Paul E . McKenney <paulmck@linux.vnet.ibm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Tejun Heo <tj@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kees Cook <keescook@chromium.org>
Cc: Daniel Mack <daniel@zonque.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
init/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -puN init/Kconfig~kbuild-fix-optimization-level-choice-default init/Kconfig
--- a/init/Kconfig~kbuild-fix-optimization-level-choice-default
+++ a/init/Kconfig
@@ -1033,7 +1033,7 @@ endif
choice
prompt "Compiler optimization level"
- default CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE
+ default CC_OPTIMIZE_FOR_PERFORMANCE
config CC_OPTIMIZE_FOR_PERFORMANCE
bool "Optimize for performance"
_
Patches currently in -mm which might be from ulfalizer@gmail.com are
kbuild-fix-optimization-level-choice-default.patch
^ permalink raw reply
* [RESEND][PATCH 6/7] nvmem: imx-ocotp: Enable i.MX7D OTP write support
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: richard.leitner, srinivas.kandagatla, axel.lin, ping.bai,
d.schultz, peng.fan, van.freenix, p.zabel
Cc: linux-kernel, linux-arm-kernel, pure.logic
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
After applying patches for both banked access and write timings we can
re-enable the OTP write interface on i.MX7D processors.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 40a1669..5b0f7b5 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -468,8 +468,6 @@ static int imx_ocotp_probe(struct platform_device *pdev)
imx_ocotp_nvmem_config.dev = dev;
imx_ocotp_nvmem_config.priv = priv;
priv->config = &imx_ocotp_nvmem_config;
- if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx7d-ocotp"))
- imx_ocotp_nvmem_config.read_only = true;
nvmem = nvmem_register(&imx_ocotp_nvmem_config);
if (IS_ERR(nvmem))
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 7/7] nvmem: imx-ocotp: Update module description
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: richard.leitner, srinivas.kandagatla, axel.lin, ping.bai,
d.schultz, peng.fan, van.freenix, p.zabel
Cc: linux-kernel, linux-arm-kernel, pure.logic
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
This imx-ocotp driver encapsulates support for a subset of both i.MX6 and
i.MX7 processors. Update the module description to reflect.
Fixes: 711d45477931 ("nvmem: octop: Add i.MX7D support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 5b0f7b5..a58a80b 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -496,5 +496,5 @@ static struct platform_driver imx_ocotp_driver = {
module_platform_driver(imx_ocotp_driver);
MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
-MODULE_DESCRIPTION("i.MX6 OCOTP fuse box driver");
+MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 4/7] nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated function
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: richard.leitner, srinivas.kandagatla, axel.lin, ping.bai,
d.schultz, peng.fan, van.freenix, p.zabel
Cc: linux-kernel, linux-arm-kernel, pure.logic
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
The i.MX7S/D has a different set of timing requirements, as a pre-cursor to
adding the i.MX7 timing parameters, move the i.MX6 stuff to a dedicated
function.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 47 +++++++++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 8034937..0cd7e03 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -169,6 +169,31 @@ static int imx_ocotp_read(void *context, unsigned int offset,
return ret;
}
+static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
+{
+ unsigned long clk_rate = 0;
+ unsigned long strobe_read, relax, strobe_prog;
+ u32 timing = 0;
+
+ /* 47.3.1.3.1
+ * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
+ * fields with timing values to match the current frequency of the
+ * ipg_clk. OTP writes will work at maximum bus frequencies as long
+ * as the HW_OCOTP_TIMING parameters are set correctly.
+ */
+ clk_rate = clk_get_rate(priv->clk);
+
+ relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
+ strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
+ strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
+
+ timing = strobe_prog & 0x00000FFF;
+ timing |= (relax << 12) & 0x0000F000;
+ timing |= (strobe_read << 16) & 0x003F0000;
+
+ writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
+}
+
static int imx_ocotp_write(void *context, unsigned int offset, void *val,
size_t bytes)
{
@@ -176,9 +201,6 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
u32 *buf = val;
int ret;
- unsigned long clk_rate = 0;
- unsigned long strobe_read, relax, strobe_prog;
- u32 timing = 0;
u32 ctrl;
u8 waddr;
u8 word = 0;
@@ -197,23 +219,8 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
return ret;
}
- /* 47.3.1.3.1
- * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
- * fields with timing values to match the current frequency of the
- * ipg_clk. OTP writes will work at maximum bus frequencies as long
- * as the HW_OCOTP_TIMING parameters are set correctly.
- */
- clk_rate = clk_get_rate(priv->clk);
-
- relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
- strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
- strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
-
- timing = strobe_prog & 0x00000FFF;
- timing |= (relax << 12) & 0x0000F000;
- timing |= (strobe_read << 16) & 0x003F0000;
-
- writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
+ /* Setup the write timing values */
+ imx_ocotp_set_imx6_timing(priv);
/* 47.3.1.3.2
* Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
--
2.7.4
^ permalink raw reply related
* [RESEND][PATCH 3/7] nvmem: imx-ocotp: Add support for banked OTP addressing
From: Bryan O'Donoghue @ 2017-10-04 22:25 UTC (permalink / raw)
To: richard.leitner, srinivas.kandagatla, axel.lin, ping.bai,
d.schultz, peng.fan, van.freenix, p.zabel
Cc: linux-kernel, linux-arm-kernel, pure.logic
In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie>
The i.MX7S/D takes the bank address in the CTRLn.ADDR field and the data
value in one of the DATAx {0, 1, 2, 3} register fields. The current write
routine is based on writing the CTRLn.ADDR field and writing a single DATA
register only.
Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
drivers/nvmem/imx-ocotp.c | 71 +++++++++++++++++++++++++++++++++++++++++------
1 file changed, 62 insertions(+), 9 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index fed76a4..8034937 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -40,7 +40,10 @@
#define IMX_OCOTP_ADDR_CTRL_SET 0x0004
#define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
#define IMX_OCOTP_ADDR_TIMING 0x0010
-#define IMX_OCOTP_ADDR_DATA 0x0020
+#define IMX_OCOTP_ADDR_DATA0 0x0020
+#define IMX_OCOTP_ADDR_DATA1 0x0030
+#define IMX_OCOTP_ADDR_DATA2 0x0040
+#define IMX_OCOTP_ADDR_DATA3 0x0050
#define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F
#define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
@@ -55,6 +58,8 @@ static DEFINE_MUTEX(ocotp_mutex);
struct octp_params {
unsigned int nregs;
+ bool banked;
+ unsigned int regs_per_bank;
};
struct ocotp_priv {
@@ -176,6 +181,7 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
u32 timing = 0;
u32 ctrl;
u8 waddr;
+ u8 word = 0;
/* allow only writing one complete OTP word at a time */
if ((bytes != priv->config->word_size) ||
@@ -228,8 +234,22 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
* description. Both the unlock code and address can be written in the
* same operation.
*/
- /* OTP write/read address specifies one of 128 word address locations */
- waddr = offset / 4;
+ if (priv->params->banked) {
+ /*
+ * In banked mode the OTP register bank goes into waddr see
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
+ * 6.4.3.1
+ */
+ offset = offset / priv->config->word_size;
+ waddr = offset / priv->params->regs_per_bank;
+ word = offset & (priv->params->regs_per_bank - 1);
+ } else {
+ /*
+ * OTP write/read address specifies one of 128 word address
+ * locations
+ */
+ waddr = offset / 4;
+ }
ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR;
@@ -255,8 +275,41 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
* shift right (with zero fill). This shifting is required to program
* the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
* modified.
+ * Note: on i.MX7 there are four data fields to write for banked write
+ * with the fuse blowing operation only taking place after data0
+ * has been written. This is why data0 must always be the last
+ * register written.
*/
- writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA);
+ if (!priv->params->banked) {
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
+ } else {
+ switch (word) {
+ case 0:
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
+ break;
+ case 1:
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
+ break;
+ case 2:
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
+ break;
+ case 3:
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
+ writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
+ writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
+ break;
+ }
+ }
/* 47.4.1.4.5
* Once complete, the controller will clear BUSY. A write request to a
@@ -313,11 +366,11 @@ static struct nvmem_config imx_ocotp_nvmem_config = {
};
static const struct octp_params params[] = {
- { .nregs = 128},
- { .nregs = 64},
- { .nregs = 128},
- { .nregs = 128},
- { .nregs = 64},
+ { .nregs = 128, .banked = false, .regs_per_bank = 0},
+ { .nregs = 64, .banked = false, .regs_per_bank = 0},
+ { .nregs = 128, .banked = false, .regs_per_bank = 0},
+ { .nregs = 128, .banked = false, .regs_per_bank = 0},
+ { .nregs = 64, .banked = true, .regs_per_bank = 4},
};
static const struct of_device_id imx_ocotp_dt_ids[] = {
--
2.7.4
^ permalink raw reply related
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