* [Qemu-devel] [PATCH 11/99] configure: recognize more rpmbuild macros
From: Michael Roth @ 2018-07-23 20:16 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable, Olaf Hering, Paolo Bonzini
In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com>
From: Olaf Hering <olaf@aepfle.de>
Extend the list of recognized, but ignored options from rpms %configure
macro. This fixes build on hosts running SUSE Linux.
Cc: qemu-stable@nongnu.org
Signed-off-by: Olaf Hering <olaf@aepfle.de>
Message-Id: <20180418075045.27393-1-olaf@aepfle.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 181ce1d05c6d4f1c80f0e7ebb41e489c2b541edf)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
---
configure | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configure b/configure
index 0a19b033bc..44bf1fef04 100755
--- a/configure
+++ b/configure
@@ -959,6 +959,8 @@ for opt do
;;
--firmwarepath=*) firmwarepath="$optarg"
;;
+ --host=*|--build=*|\
+ --disable-dependency-tracking|\
--sbindir=*|--sharedstatedir=*|\
--oldincludedir=*|--datarootdir=*|--infodir=*|--localedir=*|\
--htmldir=*|--dvidir=*|--pdfdir=*|--psdir=*)
--
2.17.1
^ permalink raw reply related
* [Qemu-devel] [PATCH 10/99] qxl: fix local renderer crash
From: Michael Roth @ 2018-07-23 20:16 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable, Gerd Hoffmann
In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com>
From: Gerd Hoffmann <kraxel@redhat.com>
Make sure we only ask the spice local renderer for display updates in
case we have a valid primary surface. Without that spice is confused
and throws errors in case a display update request (triggered by
screendump for example) happens in parallel to a mode switch and hits
the race window where the old primary surface is gone and the new isn't
establisted yet.
Cc: qemu-stable@nongnu.org
Fixes: https://bugzilla.redhat.com//show_bug.cgi?id=1567733
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 20180427115528.345-1-kraxel@redhat.com
(cherry picked from commit 5bd5c27c7d284d01477c5cc022ce22438c46bf9f)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
---
hw/display/qxl-render.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/display/qxl-render.c b/hw/display/qxl-render.c
index e7ac4f8789..c62b9a5e75 100644
--- a/hw/display/qxl-render.c
+++ b/hw/display/qxl-render.c
@@ -169,7 +169,8 @@ void qxl_render_update(PCIQXLDevice *qxl)
qemu_mutex_lock(&qxl->ssd.lock);
- if (!runstate_is_running() || !qxl->guest_primary.commands) {
+ if (!runstate_is_running() || !qxl->guest_primary.commands ||
+ qxl->mode == QXL_MODE_UNDEFINED) {
qxl_render_update_area_unlocked(qxl);
qemu_mutex_unlock(&qxl->ssd.lock);
return;
--
2.17.1
^ permalink raw reply related
* [Qemu-devel] [PATCH 09/99] spapr: don't advertise radix GTSE if max-compat-cpu < power9
From: Michael Roth @ 2018-07-23 20:16 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable, Greg Kurz, David Gibson
In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com>
From: Greg Kurz <groug@kaod.org>
On a POWER9 host, if a guest runs in pre POWER9 compat mode, it necessarily
uses the hash MMU mode. In this case, we shouldn't advertise radix GTSE in
the ibm,arch-vec-5-platform-support DT property as the current code does.
The first reason is that it doesn't make sense, and the second one is that
causes the CAS-negotiated options subsection to be migrated. This breaks
backward migration to QEMU 2.7 and older versions on POWER8 hosts:
qemu-system-ppc64: error while loading state for instance 0x0 of device
'spapr'
qemu-system-ppc64: load of migration failed: No such file or directory
This patch hence initialize CPUs a bit earlier so that we can check the
requested compat mode, and don't set OV5_MMU_RADIX_GTSE for power8 and
older.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
(cherry picked from commit 0550b1206a91d66051a21441a02c4ff126b531fe)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
---
hw/ppc/spapr.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a81570e7c8..092ec2498c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2392,6 +2392,7 @@ static void spapr_machine_init(MachineState *machine)
long load_limit, fw_size;
char *filename;
Error *resize_hpt_err = NULL;
+ PowerPCCPU *first_ppc_cpu;
msi_nonbroken = true;
@@ -2484,11 +2485,6 @@ static void spapr_machine_init(MachineState *machine)
}
spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
- if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
- /* KVM and TCG always allow GTSE with radix... */
- spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
- }
- /* ... but not with hash (currently). */
/* advertise support for dedicated HP event source to guests */
if (spapr->use_hotplug_event_source) {
@@ -2503,6 +2499,15 @@ static void spapr_machine_init(MachineState *machine)
/* init CPUs */
spapr_init_cpus(spapr);
+ first_ppc_cpu = POWERPC_CPU(first_cpu);
+ if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
+ ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
+ spapr->max_compat_pvr)) {
+ /* KVM and TCG always allow GTSE with radix... */
+ spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
+ }
+ /* ... but not with hash (currently). */
+
if (kvm_enabled()) {
/* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
kvmppc_enable_logical_ci_hcalls();
--
2.17.1
^ permalink raw reply related
* [Qemu-devel] [PATCH 99/99] tcg/i386: Mark xmm registers call-clobbered
From: Michael Roth @ 2018-07-23 20:17 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable, Richard Henderson
In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com>
From: Richard Henderson <richard.henderson@linaro.org>
When host vector registers and operations were introduced, I failed
to mark the registers call clobbered as required by the ABI.
Fixes: 770c2fc7bb7
Cc: qemu-stable@nongnu.org
Reported-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
(cherry picked from commit 672189cd586ea38a2c1d8ab91eb1f9dcff5ceb05)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
---
tcg/i386/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index ccde8801a5..5727999bb3 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -3529,7 +3529,7 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
}
- tcg_target_call_clobber_regs = 0;
+ tcg_target_call_clobber_regs = ALL_VECTOR_REGS;
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);
--
2.17.1
^ permalink raw reply related
* [PATCH 5/9] fetch2/git: throw error when no up to date sources were found during unpack
From: Urs Fässler @ 2018-07-23 15:42 UTC (permalink / raw)
To: bitbake-devel
In-Reply-To: <20180723154259.9076-1-urs.fassler@bbv.ch>
Check if the fullshallow tarball exists before unpacking it. If no
source to unpack is found, an error is thrown. The readability of the
logic to decide which source should be used is increased.
Signed-off-by: Urs Fässler <urs.fassler@bbv.ch>
Signed-off-by: Pascal Bach <pascal.bach@siemens.com>
---
lib/bb/fetch2/git.py | 6 ++++--
lib/bb/tests/fetch.py | 27 +++++++++++++++++++++++++++
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/lib/bb/fetch2/git.py b/lib/bb/fetch2/git.py
index 3364bbf9..13b9b9d8 100644
--- a/lib/bb/fetch2/git.py
+++ b/lib/bb/fetch2/git.py
@@ -477,11 +477,13 @@ class Git(FetchMethod):
if os.path.exists(destdir):
bb.utils.prunedir(destdir)
- if ud.shallow and not self.__has_up_to_date_clonedir(ud, d):
+ if self.__has_up_to_date_clonedir(ud, d):
+ runfetchcmd("%s clone %s %s/ %s" % (ud.basecmd, ud.cloneflags, ud.clonedir, destdir), d)
+ elif ud.shallow and os.path.exists(ud.fullshallow):
bb.utils.mkdirhier(destdir)
runfetchcmd("tar -xzf %s" % ud.fullshallow, d, workdir=destdir)
else:
- runfetchcmd("%s clone %s %s/ %s" % (ud.basecmd, ud.cloneflags, ud.clonedir, destdir), d)
+ bb.fatal("no up to date source found")
repourl = self._get_repo_url(ud)
runfetchcmd("%s remote set-url origin %s" % (ud.basecmd, repourl), d, workdir=destdir)
diff --git a/lib/bb/tests/fetch.py b/lib/bb/tests/fetch.py
index 83cc4f6c..fedc3b73 100644
--- a/lib/bb/tests/fetch.py
+++ b/lib/bb/tests/fetch.py
@@ -28,6 +28,7 @@ import os
from bb.fetch2 import URI
from bb.fetch2 import FetchMethod
import bb
+from bb.tests.logrecord import LogRecord, logContains
def skipIfNoNetwork():
if os.environ.get("BB_SKIP_NETTESTS") == "yes":
@@ -1678,3 +1679,29 @@ class GitShallowTest(FetcherTest):
self.assertNotEqual(orig_revs, revs)
self.assertRefs(['master', 'origin/master'])
self.assertRevCount(orig_revs - 1758)
+
+ def test_that_unpack_throws_an_error_when_the_git_clone_nor_shallow_tarball_exist(self):
+ self.add_empty_file('a')
+ fetcher, ud = self.fetch()
+ bb.utils.remove(self.gitdir, recurse=True)
+ bb.utils.remove(self.dldir, recurse=True)
+
+ with LogRecord() as logs:
+ with self.assertRaises(Exception) as context:
+ fetcher.unpack(self.d.getVar('WORKDIR'))
+
+ self.assertTrue(logContains("no up to date source found", logs))
+
+ @skipIfNoNetwork()
+ def test_that_unpack_does_work_when_using_git_shallow_tarball_and_mirror_rewrite_rules(self):
+ self.d.setVar('SRCREV', 'e5939ff608b95cdd4d0ab0e1935781ab9a276ac0')
+ self.d.setVar('BB_GIT_SHALLOW', '1')
+ self.d.setVar('BB_GENERATE_SHALLOW_TARBALLS', '1')
+ self.d.setVar('PREMIRRORS', 'git://git.yoctoproject.org/.* git://git.yoctoproject.org/git/PATH;protocol=https \n')
+
+ fetcher = bb.fetch.Fetch(["git://git.yoctoproject.org/fstests"], self.d)
+ fetcher.download()
+ fetcher.unpack(self.unpackdir)
+
+ dir = os.listdir(self.unpackdir + "/git/")
+ self.assertIn("fstests.doap", dir)
--
2.18.0
^ permalink raw reply related
* [PATCH 9/9] fetch2/git: name the shallow tarball according to the url specified in the recipe rather than the mirrored url
From: Urs Fässler @ 2018-07-23 15:42 UTC (permalink / raw)
To: bitbake-devel
In-Reply-To: <20180723154259.9076-1-urs.fassler@bbv.ch>
Unpacking a git shallow tarball does not work when using mirror rewrite
rules that alter the path of the remote url. With this patch we always
use to remote url from the recipe to generate the local shallow tarball
name.
Signed-off-by: Urs Fässler <urs.fassler@bbv.ch>
Signed-off-by: Pascal Bach <pascal.bach@siemens.com>
---
lib/bb/fetch2/git.py | 7 +++++--
lib/bb/tests/fetch.py | 26 ++++++++++++++++++++------
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/lib/bb/fetch2/git.py b/lib/bb/fetch2/git.py
index f9e31d2b..c1fec614 100644
--- a/lib/bb/fetch2/git.py
+++ b/lib/bb/fetch2/git.py
@@ -79,7 +79,7 @@ import subprocess
import tempfile
import bb
import bb.progress
-from bb.fetch2 import FetchMethod
+from bb.fetch2 import FetchMethod, decodeurl
from bb.fetch2 import runfetchcmd
from bb.fetch2 import logger
@@ -259,7 +259,10 @@ class Git(FetchMethod):
ud.fullmirror = os.path.join(dl_dir, mirrortarball)
ud.mirrortarballs = [mirrortarball]
if ud.shallow:
- tarballname = gitsrcname
+ _, original_host, original_path, _, _, _ = decodeurl(d.expand(original_url))
+ tarballname = self.__build_git_source_name(original_host, original_path, ud.rebaseable, ud.names,
+ ud.revisions)
+
if ud.bareclone:
tarballname = "%s_bare" % tarballname
diff --git a/lib/bb/tests/fetch.py b/lib/bb/tests/fetch.py
index fedc3b73..6b7df874 100644
--- a/lib/bb/tests/fetch.py
+++ b/lib/bb/tests/fetch.py
@@ -522,7 +522,6 @@ class GitShallowTarballNamingTest(FetcherTest):
self.__recipe_url = "git://git.openembedded.org/bitbake"
self.__recipe_tarball = "gitshallow_git.openembedded.org.bitbake_82ea737-1_master.tar.gz"
self.__mirror_url = "git://github.com/openembedded/bitbake.git"
- self.__mirror_tarball = "gitshallow_github.com.openembedded.bitbake.git_82ea737-1_master.tar.gz"
self.d.setVar('BB_GIT_SHALLOW', '1')
self.d.setVar('BB_GENERATE_SHALLOW_TARBALLS', '1')
@@ -532,7 +531,7 @@ class GitShallowTarballNamingTest(FetcherTest):
self.d.setVar("PREMIRRORS", self.__recipe_url + " " + self.__mirror_url + " \n")
@skipIfNoNetwork()
- def test_that_the_tarball_is_named_after_recipe_url_when_no_mirroring_is_used(self):
+ def test_that_the_recipe_tarball_is_created_when_no_mirroring_is_used(self):
fetcher = bb.fetch.Fetch([self.__recipe_url], self.d)
fetcher.download()
@@ -541,17 +540,17 @@ class GitShallowTarballNamingTest(FetcherTest):
self.assertIn(self.__recipe_tarball, dir)
@skipIfNoNetwork()
- def test_that_the_mirror_tarball_is_created_when_mirroring_is_used(self):
+ def test_that_the_recipe_tarball_is_created_when_mirroring_is_used(self):
self.__setup_mirror_rewrite()
fetcher = bb.fetch.Fetch([self.__recipe_url], self.d)
fetcher.download()
dir = os.listdir(self.dldir)
- self.assertIn(self.__mirror_tarball, dir)
+ self.assertIn(self.__recipe_tarball, dir)
@skipIfNoNetwork()
- def test_that_the_mirror_tarball_still_exists_when_mirroring_is_used_and_the_mirrored_tarball_already_exists(self):
+ def test_that_the_recipe_tarball_is_created_when_mirroring_is_used_and_the_mirrored_tarball_already_exists(self):
self.__setup_mirror_rewrite()
fetcher = bb.fetch.Fetch([self.__mirror_url], self.d)
fetcher.download()
@@ -562,7 +561,7 @@ class GitShallowTarballNamingTest(FetcherTest):
fetcher.download()
dir = os.listdir(self.dldir)
- self.assertIn(self.__mirror_tarball, dir)
+ self.assertIn(self.__recipe_tarball, dir)
class FetcherLocalTest(FetcherTest):
@@ -1705,3 +1704,18 @@ class GitShallowTest(FetcherTest):
dir = os.listdir(self.unpackdir + "/git/")
self.assertIn("fstests.doap", dir)
+
+ @skipIfNoNetwork()
+ def test_that_unpack_uses_the_git_shallow_tarball_when_using_mirror_rewrite_rules_and_the_git_clone_does_not_exist(self):
+ self.d.setVar('SRCREV', 'e5939ff608b95cdd4d0ab0e1935781ab9a276ac0')
+ self.d.setVar('BB_GIT_SHALLOW', '1')
+ self.d.setVar('BB_GENERATE_SHALLOW_TARBALLS', '1')
+ self.d.setVar('PREMIRRORS', 'git://git.yoctoproject.org/.* git://git.yoctoproject.org/git/PATH;protocol=https \n')
+ fetcher = bb.fetch.Fetch(["git://git.yoctoproject.org/fstests"], self.d)
+ fetcher.download()
+ bb.utils.remove(self.dldir + '/git2', recurse=True)
+
+ fetcher.unpack(self.unpackdir)
+
+ dir = os.listdir(self.unpackdir + "/git/")
+ self.assertIn("fstests.doap", dir)
--
2.18.0
^ permalink raw reply related
* Re: [PATCH 05/11] touchscreen: elants: Use octal permissions
From: Harshit Jain @ 2018-07-23 20:17 UTC (permalink / raw)
To: Joe Perches
Cc: Guenter Roeck, Dmitry Torokhov, Greg Kroah-Hartman, trivial,
Simon Budig, Andi Shyti, Luca Ceresoli, linux-input, linux-kernel
In-Reply-To: <5ac390c1cdf14656624dcc1f2816ab4d694d0d4f.camel@perches.com>
[-- Attachment #1: Type: text/plain, Size: 842 bytes --]
I ran a treewide script and changed them all to octal and built a kernel
which i am currently running on my machine, I have used DEVICE_ATTR_RO()
for 0444's where possible if i dont find any regressions I will post a
patch for review. I think i will be testing it at least for a week.
On Tue, Jul 24, 2018 at 12:00 AM, Joe Perches <joe@perches.com> wrote:
> On Mon, 2018-07-23 at 11:24 -0700, Guenter Roeck wrote:
> > There are much more urgent issues to fix there (such as, for example,
> > converting the "offending" drivers to the latest API, which would
> > magically cause most of the offenders to disappear).
>
> Perhaps posting a list of desired hwmon changes could help.
>
> Documentation/hwmon/submitting-patches does not seem to specify
> what the "latest API" is nor describe what changes would be
> required in older drivers.
>
[-- Attachment #2: Type: text/html, Size: 1222 bytes --]
^ permalink raw reply
* [PATCH 7/9] fetch2: provide original url in addition to the mirrored url to FetchData.__init__ and FetchMethod.urldata_init
From: Urs Fässler @ 2018-07-23 15:42 UTC (permalink / raw)
To: bitbake-devel
In-Reply-To: <20180723154259.9076-1-urs.fassler@bbv.ch>
When a mirror rewrite rule is used, it can happen that the downloaded
file is named differently depending on the used mirror. In preparation
to a consistent naming, we provide the original url to the fetcher.
Signed-off-by: Urs Fässler <urs.fassler@bbv.ch>
Signed-off-by: Pascal Bach <pascal.bach@siemens.com>
---
lib/bb/fetch2/__init__.py | 12 +++++++-----
lib/bb/fetch2/bzr.py | 2 +-
lib/bb/fetch2/clearcase.py | 2 +-
lib/bb/fetch2/cvs.py | 2 +-
lib/bb/fetch2/git.py | 2 +-
lib/bb/fetch2/gitannex.py | 4 ++--
lib/bb/fetch2/hg.py | 2 +-
lib/bb/fetch2/local.py | 2 +-
lib/bb/fetch2/npm.py | 2 +-
lib/bb/fetch2/osc.py | 2 +-
lib/bb/fetch2/perforce.py | 2 +-
lib/bb/fetch2/repo.py | 2 +-
lib/bb/fetch2/s3.py | 2 +-
lib/bb/fetch2/sftp.py | 2 +-
lib/bb/fetch2/ssh.py | 2 +-
lib/bb/fetch2/svn.py | 2 +-
lib/bb/fetch2/wget.py | 2 +-
17 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/lib/bb/fetch2/__init__.py b/lib/bb/fetch2/__init__.py
index c8653d62..61009e43 100644
--- a/lib/bb/fetch2/__init__.py
+++ b/lib/bb/fetch2/__init__.py
@@ -932,7 +932,7 @@ def build_mirroruris(origud, mirrors, ld):
localmirrors.remove(line)
try:
- newud = FetchData(newuri, ld)
+ newud = FetchData(newuri, ld, origud.url)
newud.setup_localpath(ld)
except bb.fetch2.BBFetchException as e:
logger.debug(1, "Mirror fetch failure for url %s (original url: %s)" % (newuri, origud.url))
@@ -1202,7 +1202,7 @@ class FetchData(object):
"""
A class which represents the fetcher state for a given URI.
"""
- def __init__(self, url, d, localonly = False):
+ def __init__(self, url, d, original_url = None, localonly = False):
# localpath is the location of a downloaded result. If not set, the file is local.
self.donestamp = None
self.needdonestamp = True
@@ -1213,6 +1213,8 @@ class FetchData(object):
self.basename = None
self.basepath = None
(self.type, self.host, self.path, self.user, self.pswd, self.parm) = decodeurl(d.expand(url))
+ if not original_url:
+ original_url = url
self.date = self.getSRCDate(d)
self.url = url
if not self.user and "user" in self.parm:
@@ -1259,7 +1261,7 @@ class FetchData(object):
logger.warning('Consider updating %s recipe to use "protocol" not "proto" in SRC_URI.', d.getVar('PN'))
self.parm["protocol"] = self.parm.get("proto", None)
- self.method.urldata_init(self, d)
+ self.method.urldata_init(self, d, original_url)
if "localpath" in self.parm:
# if user sets localpath for file, use it instead.
@@ -1348,7 +1350,7 @@ class FetchMethod(object):
return True
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
init method specific variable within url data
"""
@@ -1594,7 +1596,7 @@ class Fetch(object):
for url in urls:
if url not in self.ud:
try:
- self.ud[url] = FetchData(url, d, localonly)
+ self.ud[url] = FetchData(url, d, localonly = localonly)
except NonLocalMethod:
if localonly:
self.ud[url] = None
diff --git a/lib/bb/fetch2/bzr.py b/lib/bb/fetch2/bzr.py
index 658502f9..4be73320 100644
--- a/lib/bb/fetch2/bzr.py
+++ b/lib/bb/fetch2/bzr.py
@@ -36,7 +36,7 @@ class Bzr(FetchMethod):
def supports(self, ud, d):
return ud.type in ['bzr']
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
init bzr specific variable within url data
"""
diff --git a/lib/bb/fetch2/clearcase.py b/lib/bb/fetch2/clearcase.py
index 3a6573d0..ef1db138 100644
--- a/lib/bb/fetch2/clearcase.py
+++ b/lib/bb/fetch2/clearcase.py
@@ -84,7 +84,7 @@ class ClearCase(FetchMethod):
def debug(self, msg):
logger.debug(1, "ClearCase: %s", msg)
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
init ClearCase specific variable within url data
"""
diff --git a/lib/bb/fetch2/cvs.py b/lib/bb/fetch2/cvs.py
index 0e0a3196..7c5296fb 100644
--- a/lib/bb/fetch2/cvs.py
+++ b/lib/bb/fetch2/cvs.py
@@ -42,7 +42,7 @@ class Cvs(FetchMethod):
"""
return ud.type in ['cvs']
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
if not "module" in ud.parm:
raise MissingParameterError("module", ud.url)
ud.module = ud.parm["module"]
diff --git a/lib/bb/fetch2/git.py b/lib/bb/fetch2/git.py
index 13b9b9d8..7f7951f7 100644
--- a/lib/bb/fetch2/git.py
+++ b/lib/bb/fetch2/git.py
@@ -141,7 +141,7 @@ class Git(FetchMethod):
def supports_checksum(self, urldata):
return False
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
init git specific variable within url data
so that the git method like latest_revision() can work
diff --git a/lib/bb/fetch2/gitannex.py b/lib/bb/fetch2/gitannex.py
index a9b69caa..187e6b2e 100644
--- a/lib/bb/fetch2/gitannex.py
+++ b/lib/bb/fetch2/gitannex.py
@@ -33,8 +33,8 @@ class GitANNEX(Git):
"""
return ud.type in ['gitannex']
- def urldata_init(self, ud, d):
- super(GitANNEX, self).urldata_init(ud, d)
+ def urldata_init(self, ud, d, original_url):
+ super(GitANNEX, self).urldata_init(ud, d, original_url)
if ud.shallow:
ud.shallow_extra_refs += ['refs/heads/git-annex', 'refs/heads/synced/*']
diff --git a/lib/bb/fetch2/hg.py b/lib/bb/fetch2/hg.py
index 936d0431..5fe08e80 100644
--- a/lib/bb/fetch2/hg.py
+++ b/lib/bb/fetch2/hg.py
@@ -50,7 +50,7 @@ class Hg(FetchMethod):
"""
return False
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
init hg specific variable within url data
"""
diff --git a/lib/bb/fetch2/local.py b/lib/bb/fetch2/local.py
index a114ac12..9e1b918c 100644
--- a/lib/bb/fetch2/local.py
+++ b/lib/bb/fetch2/local.py
@@ -39,7 +39,7 @@ class Local(FetchMethod):
"""
return urldata.type in ['file']
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
# We don't set localfile as for this fetcher the file is already local!
ud.decodedurl = urllib.parse.unquote(ud.url.split("://")[1].split(";")[0])
ud.basename = os.path.basename(ud.decodedurl)
diff --git a/lib/bb/fetch2/npm.py b/lib/bb/fetch2/npm.py
index 408dfc3d..cab792d4 100644
--- a/lib/bb/fetch2/npm.py
+++ b/lib/bb/fetch2/npm.py
@@ -60,7 +60,7 @@ class Npm(FetchMethod):
bb.utils.remove(ud.pkgdatadir, True)
bb.utils.remove(ud.fullmirror, False)
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
init NPM specific variable within url data
"""
diff --git a/lib/bb/fetch2/osc.py b/lib/bb/fetch2/osc.py
index 6c60456b..18dd6047 100644
--- a/lib/bb/fetch2/osc.py
+++ b/lib/bb/fetch2/osc.py
@@ -25,7 +25,7 @@ class Osc(FetchMethod):
"""
return ud.type in ['osc']
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
if not "module" in ud.parm:
raise MissingParameterError('module', ud.url)
diff --git a/lib/bb/fetch2/perforce.py b/lib/bb/fetch2/perforce.py
index 903a8e61..3a15754a 100644
--- a/lib/bb/fetch2/perforce.py
+++ b/lib/bb/fetch2/perforce.py
@@ -37,7 +37,7 @@ class Perforce(FetchMethod):
""" Check to see if a given url can be fetched with perforce. """
return ud.type in ['p4']
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
Initialize perforce specific variables within url data. If P4CONFIG is
provided by the env, use it. If P4PORT is specified by the recipe, use
diff --git a/lib/bb/fetch2/repo.py b/lib/bb/fetch2/repo.py
index 8c7e8185..c56df7e1 100644
--- a/lib/bb/fetch2/repo.py
+++ b/lib/bb/fetch2/repo.py
@@ -37,7 +37,7 @@ class Repo(FetchMethod):
"""
return ud.type in ["repo"]
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
We don"t care about the git rev of the manifests repository, but
we do care about the manifest to use. The default is "default".
diff --git a/lib/bb/fetch2/s3.py b/lib/bb/fetch2/s3.py
index 16292886..e00f7072 100644
--- a/lib/bb/fetch2/s3.py
+++ b/lib/bb/fetch2/s3.py
@@ -47,7 +47,7 @@ class S3(FetchMethod):
def recommends_checksum(self, urldata):
return True
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
if 'downloadfilename' in ud.parm:
ud.basename = ud.parm['downloadfilename']
else:
diff --git a/lib/bb/fetch2/sftp.py b/lib/bb/fetch2/sftp.py
index 81884a6a..f68cbca1 100644
--- a/lib/bb/fetch2/sftp.py
+++ b/lib/bb/fetch2/sftp.py
@@ -78,7 +78,7 @@ class SFTP(FetchMethod):
def recommends_checksum(self, urldata):
return True
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
if 'protocol' in ud.parm and ud.parm['protocol'] == 'git':
raise bb.fetch2.ParameterError(
"Invalid protocol - if you wish to fetch from a " +
diff --git a/lib/bb/fetch2/ssh.py b/lib/bb/fetch2/ssh.py
index 6047ee41..4f9e0853 100644
--- a/lib/bb/fetch2/ssh.py
+++ b/lib/bb/fetch2/ssh.py
@@ -77,7 +77,7 @@ class SSH(FetchMethod):
def supports_checksum(self, urldata):
return False
- def urldata_init(self, urldata, d):
+ def urldata_init(self, urldata, d, original_url):
if 'protocol' in urldata.parm and urldata.parm['protocol'] == 'git':
raise bb.fetch2.ParameterError(
"Invalid protocol - if you wish to fetch from a git " +
diff --git a/lib/bb/fetch2/svn.py b/lib/bb/fetch2/svn.py
index ed70bcf8..be0e9eeb 100644
--- a/lib/bb/fetch2/svn.py
+++ b/lib/bb/fetch2/svn.py
@@ -42,7 +42,7 @@ class Svn(FetchMethod):
"""
return ud.type in ['svn']
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
"""
init svn specific variable within url data
"""
diff --git a/lib/bb/fetch2/wget.py b/lib/bb/fetch2/wget.py
index 8f505b6d..bd2a0c6b 100644
--- a/lib/bb/fetch2/wget.py
+++ b/lib/bb/fetch2/wget.py
@@ -74,7 +74,7 @@ class Wget(FetchMethod):
def recommends_checksum(self, urldata):
return True
- def urldata_init(self, ud, d):
+ def urldata_init(self, ud, d, original_url):
if 'protocol' in ud.parm:
if ud.parm['protocol'] == 'git':
raise bb.fetch2.ParameterError("Invalid protocol - if you wish to fetch from a git repository using http, you need to instead use the git:// prefix with protocol=http", ud.url)
--
2.18.0
^ permalink raw reply related
* [PATCH 2/9] fetch2/git: add tests to capture existing behavior wrt. naming of git shallow tarball
From: Urs Fässler @ 2018-07-23 15:42 UTC (permalink / raw)
To: bitbake-devel
In-Reply-To: <20180723154259.9076-1-urs.fassler@bbv.ch>
The mapping of the URLs to the local shallow tarballs is not obvious. For
easier understanding, we add this tests to explicit showing the mapping.
Signed-off-by: Urs Fässler <urs.fassler@bbv.ch>
Signed-off-by: Pascal Bach <pascal.bach@siemens.com>
---
lib/bb/tests/fetch.py | 49 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/lib/bb/tests/fetch.py b/lib/bb/tests/fetch.py
index 5bce1bf8..83cc4f6c 100644
--- a/lib/bb/tests/fetch.py
+++ b/lib/bb/tests/fetch.py
@@ -515,6 +515,55 @@ class GitDownloadDirectoryNamingTest(FetcherTest):
self.assertTrue(path.endswith("/" + self.__mirror_dir))
+class GitShallowTarballNamingTest(FetcherTest):
+ def setUp(self):
+ super(GitShallowTarballNamingTest, self).setUp()
+ self.__recipe_url = "git://git.openembedded.org/bitbake"
+ self.__recipe_tarball = "gitshallow_git.openembedded.org.bitbake_82ea737-1_master.tar.gz"
+ self.__mirror_url = "git://github.com/openembedded/bitbake.git"
+ self.__mirror_tarball = "gitshallow_github.com.openembedded.bitbake.git_82ea737-1_master.tar.gz"
+
+ self.d.setVar('BB_GIT_SHALLOW', '1')
+ self.d.setVar('BB_GENERATE_SHALLOW_TARBALLS', '1')
+ self.d.setVar('SRCREV', '82ea737a0b42a8b53e11c9cde141e9e9c0bd8c40')
+
+ def __setup_mirror_rewrite(self):
+ self.d.setVar("PREMIRRORS", self.__recipe_url + " " + self.__mirror_url + " \n")
+
+ @skipIfNoNetwork()
+ def test_that_the_tarball_is_named_after_recipe_url_when_no_mirroring_is_used(self):
+ fetcher = bb.fetch.Fetch([self.__recipe_url], self.d)
+
+ fetcher.download()
+
+ dir = os.listdir(self.dldir)
+ self.assertIn(self.__recipe_tarball, dir)
+
+ @skipIfNoNetwork()
+ def test_that_the_mirror_tarball_is_created_when_mirroring_is_used(self):
+ self.__setup_mirror_rewrite()
+ fetcher = bb.fetch.Fetch([self.__recipe_url], self.d)
+
+ fetcher.download()
+
+ dir = os.listdir(self.dldir)
+ self.assertIn(self.__mirror_tarball, dir)
+
+ @skipIfNoNetwork()
+ def test_that_the_mirror_tarball_still_exists_when_mirroring_is_used_and_the_mirrored_tarball_already_exists(self):
+ self.__setup_mirror_rewrite()
+ fetcher = bb.fetch.Fetch([self.__mirror_url], self.d)
+ fetcher.download()
+ bb.utils.prunedir(self.dldir + '/git2')
+ bb.utils.prunedir(self.unpackdir)
+ fetcher = bb.fetch.Fetch([self.__recipe_url], self.d)
+
+ fetcher.download()
+
+ dir = os.listdir(self.dldir)
+ self.assertIn(self.__mirror_tarball, dir)
+
+
class FetcherLocalTest(FetcherTest):
def setUp(self):
def touch(fn):
--
2.18.0
^ permalink raw reply related
* [PATCH 6/9] fetch2: declare urldata_init in base class
From: Urs Fässler @ 2018-07-23 15:42 UTC (permalink / raw)
To: bitbake-devel
In-Reply-To: <20180723154259.9076-1-urs.fassler@bbv.ch>
Declare urldata_init in FetchMethod since it is implemented by every
fetcher anyway. Always call urldata_init in FetchData init.
Signed-off-by: Urs Fässler <urs.fassler@bbv.ch>
Signed-off-by: Pascal Bach <pascal.bach@siemens.com>
---
lib/bb/fetch2/__init__.py | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/lib/bb/fetch2/__init__.py b/lib/bb/fetch2/__init__.py
index a83526a5..c8653d62 100644
--- a/lib/bb/fetch2/__init__.py
+++ b/lib/bb/fetch2/__init__.py
@@ -1259,8 +1259,7 @@ class FetchData(object):
logger.warning('Consider updating %s recipe to use "protocol" not "proto" in SRC_URI.', d.getVar('PN'))
self.parm["protocol"] = self.parm.get("proto", None)
- if hasattr(self.method, "urldata_init"):
- self.method.urldata_init(self, d)
+ self.method.urldata_init(self, d)
if "localpath" in self.parm:
# if user sets localpath for file, use it instead.
@@ -1349,6 +1348,12 @@ class FetchMethod(object):
return True
+ def urldata_init(self, ud, d):
+ """
+ init method specific variable within url data
+ """
+ pass
+
def recommends_checksum(self, urldata):
"""
Is the backend on where checksumming is recommended (should warnings
--
2.18.0
^ permalink raw reply related
* ✓ Fi.CI.BAT: success for drm/i915: Skip repeated calls to i915_gem_set_wedged() (rev3)
From: Patchwork @ 2018-07-23 20:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
In-Reply-To: <20180723145335.24579-1-chris@chris-wilson.co.uk>
== Series Details ==
Series: drm/i915: Skip repeated calls to i915_gem_set_wedged() (rev3)
URL : https://patchwork.freedesktop.org/series/47067/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4530 -> Patchwork_9751 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/47067/revisions/3/mbox/
== Known issues ==
Here are the changes found in Patchwork_9751 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: PASS -> DMESG-FAIL (fdo#107292)
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: PASS -> DMESG-WARN (fdo#107139, fdo#105128)
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-j4005: PASS -> FAIL (fdo#100368)
igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
fi-glk-j4005: PASS -> FAIL (fdo#103481)
==== Possible fixes ====
igt@drv_selftest@live_workarounds:
fi-skl-6700hq: DMESG-FAIL (fdo#107292) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: FAIL (fdo#103841) -> PASS
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-dsi: FAIL (fdo#100368) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
== Participating hosts (50 -> 43) ==
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-skl-caroline fi-byt-clapper
== Build changes ==
* Linux: CI_DRM_4530 -> Patchwork_9751
CI_DRM_4530: d27cc4a37a5cc1ef14a3aafdcb6682e5f6a85d09 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4571: 65fccc149b85968cdce4737266b056059c1510f3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9751: fbfeaf105d2509bfd9333dfe8779b143b0dbd14a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fbfeaf105d25 drm/i915: Skip repeated calls to i915_gem_set_wedged()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9751/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Fwd: New Defects reported by Coverity Scan for Linux
From: Bjorn Helgaas @ 2018-07-23 19:12 UTC (permalink / raw)
To: Honghui Zhang; +Cc: Sergei Shtylyov, Lorenzo Pieralisi, linux-pci
In-Reply-To: <5b5555e19b5af_5e922b08291e2f60744cb@node1.mail>
Hi Honghui,
Would you consider doing a minor patch to fix the issue Coverity
reported below (not checking the return value from
devm_pci_remap_iospace())?
Thanks,
Bjorn
---------- Forwarded message ---------
From: <scan-admin@coverity.com>
Date: Sun, Jul 22, 2018 at 11:13 PM
Subject: New Defects reported by Coverity Scan for Linux
To: <bhelgaas@google.com>
...
** CID 1438089: Error handling issues (CHECKED_RETURN)
/drivers/pci/controller/pcie-mediatek.c: 1112 in mtk_pcie_request_resources()
________________________________________________________________________________________________________
*** CID 1438089: Error handling issues (CHECKED_RETURN)
/drivers/pci/controller/pcie-mediatek.c: 1112 in mtk_pcie_request_resources()
1106 pci_add_resource(windows, &pcie->busn);
1107
1108 err = devm_request_pci_bus_resources(dev, windows);
1109 if (err < 0)
1110 return err;
1111
>>> CID 1438089: Error handling issues (CHECKED_RETURN)
>>> Calling "devm_pci_remap_iospace" without checking return value (as is done elsewhere 5 out of 6 times).
1112 devm_pci_remap_iospace(dev, &pcie->pio, pcie->io.start);
1113
1114 return 0;
1115 }
1116
1117 static int mtk_pcie_register_host(struct pci_host_bridge *host)
^ permalink raw reply
* [Qemu-devel] Virtual IOMMU + Virtio-net devices in a Windows VM doesn't work
From: Jintack Lim @ 2018-07-23 20:13 UTC (permalink / raw)
To: QEMU Devel Mailing List
Hi,
I'm running a Windows VM on top of KVM on x86, and one of virtio-net
device in the Windows VM doesn't seem to work. I provided virtual
IOMMU and two virtio-net devices to the VM: one bypassing the virtual
IOMMU and the other one behind the virtual IOMMU[1]. It turned out
that the virtio-net device behind virtual IOMMU didn't work while the
one bypassing the virtual IOMMU worked well. In a linux VM with the
same configuration, both of virtio-net device worked well.
I found that there is a subtle difference between virtio-net devices
bypassing and behind virtual IOMMU in a Linux VM. The lscpu command in
the Linux VM shows different device names for them; the first line is
for the bypassing one, and the second line is for the one behind the
virtual IOMMU
00:03.0 Ethernet controller: Red Hat, Inc Virtio network device
01:00.0 Ethernet controller: Red Hat, Inc Device 1041 (rev 01)
I wonder if this difference somehow caused the problem in the Windows
VM. I've installed the latest virtio drivers (0.1.149) from the fedora
project [2]
Any thoughts?
I'm using v4.15 Linux kernel as a host, and QEMU 2.11.0.
Thanks,
Jintack
[1] https://wiki.qemu.org/Features/VT-d
[2] https://docs.fedoraproject.org/quick-docs/en-US/creating-windows-virtual-machines-using-virtio-drivers.html
^ permalink raw reply
* Re: Consolidating RCU-bh, RCU-preempt, and RCU-sched
From: Steven Rostedt @ 2018-07-23 20:10 UTC (permalink / raw)
To: Lai Jiangshan
Cc: Paul E. McKenney, Josh Triplett, Mathieu Desnoyers, LKML,
Ingo Molnar, Linus Torvalds, Peter Zijlstra, oleg, Eric Dumazet,
davem, Thomas Gleixner
In-Reply-To: <CAJhGHyCYxPNSM9fZgUHW7jFR0M3DFGn4HdQGfpRnzfnrL2yyYA@mail.gmail.com>
Sorry for the late reply, just came back from the Caribbean :-) :-) :-)
On Fri, 13 Jul 2018 11:47:18 +0800
Lai Jiangshan <jiangshanlai@gmail.com> wrote:
> On Fri, Jul 13, 2018 at 8:02 AM, Paul E. McKenney
> <paulmck@linux.vnet.ibm.com> wrote:
> > Hello!
> >
> > I now have a semi-reasonable prototype of changes consolidating the
> > RCU-bh, RCU-preempt, and RCU-sched update-side APIs in my -rcu tree.
> > There are likely still bugs to be fixed and probably other issues as well,
> > but a prototype does exist.
What's the rational for all this churn? Linus's complaining that there
are too many RCU variants?
> >
> > Assuming continued good rcutorture results and no objections, I am
> > thinking in terms of this timeline:
> >
> > o Preparatory work and cleanups are slated for the v4.19 merge window.
> >
> > o The actual consolidation and post-consolidation cleanup is slated
> > for the merge window after v4.19 (v5.0?). These cleanups include
> > the replacements called out below within the RCU implementation
> > itself (but excluding kernel/rcu/sync.c, see question below).
> >
> > o Replacement of now-obsolete update APIs is slated for the second
> > merge window after v4.19 (v5.1?). The replacements are currently
> > expected to be as follows:
> >
> > synchronize_rcu_bh() -> synchronize_rcu()
> > synchronize_rcu_bh_expedited() -> synchronize_rcu_expedited()
> > call_rcu_bh() -> call_rcu()
> > rcu_barrier_bh() -> rcu_barrier()
> > synchronize_sched() -> synchronize_rcu()
> > synchronize_sched_expedited() -> synchronize_rcu_expedited()
> > call_rcu_sched() -> call_rcu()
> > rcu_barrier_sched() -> rcu_barrier()
> > get_state_synchronize_sched() -> get_state_synchronize_rcu()
> > cond_synchronize_sched() -> cond_synchronize_rcu()
> > synchronize_rcu_mult() -> synchronize_rcu()
> >
> > I have done light testing of these replacements with good results.
> >
> > Any objections to this timeline?
> >
> > I also have some questions on the ultimate end point. I have default
> > choices, which I will likely take if there is no discussion.
> >
> > o
> > Currently, I am thinking in terms of keeping the per-flavor
> > read-side functions. For example, rcu_read_lock_bh() would
> > continue to disable softirq, and would also continue to tell
> > lockdep about the RCU-bh read-side critical section. However,
> > synchronize_rcu() will wait for all flavors of read-side critical
> > sections, including those introduced by (say) preempt_disable(),
> > so there will no longer be any possibility of mismatching (say)
> > RCU-bh readers with RCU-sched updaters.
> >
> > I could imagine other ways of handling this, including:
> >
> > a. Eliminate rcu_read_lock_bh() in favor of
> > local_bh_disable() and so on. Rely on lockdep
> > instrumentation of these other functions to identify RCU
> > readers, introducing such instrumentation as needed. I am
> > not a fan of this approach because of the large number of
> > places in the Linux kernel where interrupts, preemption,
> > and softirqs are enabled or disabled "behind the scenes".
> >
> > b. Eliminate rcu_read_lock_bh() in favor of rcu_read_lock(),
> > and required callers to also disable softirqs, preemption,
> > or whatever as needed. I am not a fan of this approach
> > because it seems a lot less convenient to users of RCU-bh
> > and RCU-sched.
> >
> > At the moment, I therefore favor keeping the RCU-bh and RCU-sched
> > read-side APIs. But are there better approaches?
>
> Hello, Paul
>
> Since local_bh_disable() will be guaranteed to be protected by RCU
> and more general. I'm afraid it will be preferred over
> rcu_read_lock_bh() which will be gradually being phased out.
>
> In other words, keeping the RCU-bh read-side APIs will be a slower
> version of the option A. So will the same approach for the RCU-sched.
> But it'll still be better than the hurrying option A, IMHO.
Now when all this gets done, is synchronize_rcu() going to just wait
for everything to pass? (scheduling, RCU readers, softirqs, etc) Is
there any worry about lengthening the time of synchronize_rcu?
-- Steve
> >
> > o How should kernel/rcu/sync.c be handled? Here are some
> > possibilities:
> >
> > a. Leave the full gp_ops[] array and simply translate
> > the obsolete update-side functions to their RCU
> > equivalents.
> >
> > b. Leave the current gp_ops[] array, but only have
> > the RCU_SYNC entry. The __INIT_HELD field would
> > be set to a function that was OK with being in an
> > RCU read-side critical section, an interrupt-disabled
> > section, etc.
> >
> > This allows for possible addition of SRCU functionality.
> > It is also a trivial change. Note that the sole user
> > of sync.c uses RCU_SCHED_SYNC, and this would need to
> > be changed to RCU_SYNC.
> >
> > But is it likely that we will ever add SRCU?
> >
> > c. Eliminate that gp_ops[] array, hard-coding the function
> > pointers into their call sites.
> >
> > I don't really have a preference. Left to myself, I will be lazy
> > and take option #a. Are there better approaches?
> >
> > o Currently, if a lock related to the scheduler's rq or pi locks is
> > held across rcu_read_unlock(), that lock must be held across the
> > entire read-side critical section in order to avoid deadlock.
> > Now that the end of the RCU read-side critical section is
> > deferred until sometime after interrupts are re-enabled, this
> > requirement could be lifted. However, because the end of the RCU
> > read-side critical section is detected sometime after interrupts
> > are re-enabled, this means that a low-priority RCU reader might
> > remain priority-boosted longer than need be, which could be a
> > problem when running real-time workloads.
> >
> > My current thought is therefore to leave this constraint in
> > place. Thoughts?
> >
> > Anything else that I should be worried about? ;-)
> >
> > Thanx, Paul
> >
^ permalink raw reply
* Re: [PATCHv3 2/2] mtd: m25p80: restore the status of SPI flash when exiting
From: Boris Brezillon @ 2018-07-23 20:10 UTC (permalink / raw)
To: Brian Norris
Cc: Zhiqiang Hou, linux-mtd, linux-kernel, dwmw2, boris.brezillon,
marek.vasut, richard, cyrille.pitchen
In-Reply-To: <20180723181350.GA58212@ban.mtv.corp.google.com>
Hi Brian,
On Mon, 23 Jul 2018 11:13:50 -0700
Brian Norris <computersforpeace@gmail.com> wrote:
> Hello,
>
> I noticed this got merged, but I wanted to put my 2 cents in here:
I wish you had replied to this thread when it was posted (more than
6 months ago). Reverting the patch now implies making some people
unhappy because they'll have to resort to their old out-of-tree
hacks :-(.
>
> On Wed, Dec 06, 2017 at 10:53:42AM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Restore the status to be compatible with legacy devices.
> > Take Freescale eSPI boot for example, it copies (in 3 Byte
> > addressing mode) the RCW and bootloader images from SPI flash
> > without firing a reset signal previously, so the reboot command
> > will fail without reseting the addressing mode of SPI flash.
> > This patch implement .shutdown function to restore the status
> > in reboot process, and add the same operation to the .remove
> > function.
>
> We have previously rejected this patch multiple times, because the above
> comment demonstrates a broken product.
If we were to only support working HW parts, I fear Linux would not
support a lot of HW (that's even more true when it comes to flashes :P).
> You cannot guarantee that all
> reboots will invoke the .shutdown() method -- what about crashes? What
> about watchdog resets? IIUC, those will hit the same broken behavior,
> and have unexepcted behavior in your bootloader.
Yes, there are corner cases that are not addressed with this approach,
but it still seems to improve things. Of course, that means the
user should try to re-route all HW reset sources to SW ones (RESET input
pin muxed to the GPIO controller, watchdog generating an interrupt
instead of directly asserting the RESET output pin), which is not always
possible, but even when it's not, isn't it better to have a setup that
works fine 99% of the time instead of 50% of the time?
>
> I suppose one could argue for doing this in remove(), but AIUI you're
> just papering over system bugs by introducing the shutdown() function
> here. Thus, I'd prefer we drop the shutdown() method to avoid misleading
> other users of this driver.
I understand your point. But if the problem is about making sure people
designing new boards get that right, why not complaining at probe time
when things are wrong?
I mean, spi_nor_restore() seems to only do something on very specific
NORs (those on which a SW RESET does not resets the addressing
mode). So, how about adding a flag that says "my board has the NOR HW
RESET pin wired" (there would be a DT props to set that flag). Then you
add a WARN_ON() when this flag is not set and a NOR chip impacted by
this bug is detected. This way you make sure people are informed that
they're doing something wrong, and for those who can't change their HW
(because it's already widely deployed), you have a fix that improve
things.
Regards,
Boris
^ permalink raw reply
* [PATCH] drm/amdgpu: implement harvesting support for UVD 7.2
From: Alex Deucher @ 2018-07-23 20:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Properly handle cases where one or more instance of the IP
block may be harvested.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c | 13 +++++--
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 11 +++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 5 +++
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 56 +++++++++++++++++++++++++--
5 files changed, 86 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 258b6f73cbdf..f4d379cd4e47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -348,8 +348,11 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
break;
case AMDGPU_HW_IP_UVD:
type = AMD_IP_BLOCK_TYPE_UVD;
- for (i = 0; i < adev->uvd.num_uvd_inst; i++)
+ for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i);
+ }
ib_start_alignment = 64;
ib_size_alignment = 64;
break;
@@ -362,11 +365,14 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
break;
case AMDGPU_HW_IP_UVD_ENC:
type = AMD_IP_BLOCK_TYPE_UVD;
- for (i = 0; i < adev->uvd.num_uvd_inst; i++)
+ for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
for (j = 0; j < adev->uvd.num_enc_rings; j++)
ring_mask |=
((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) <<
(j + i * adev->uvd.num_enc_rings));
+ }
ib_start_alignment = 64;
ib_size_alignment = 64;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index ea9850c9224d..bb88411d7c35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -219,7 +219,7 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
u32 hw_ip, u32 instance, u32 ring,
struct amdgpu_ring **out_ring)
{
- int r, ip_num_rings;
+ int i, r, ip_num_rings;
struct amdgpu_queue_mapper *mapper = &mgr->mapper[hw_ip];
if (!adev || !mgr || !out_ring)
@@ -248,14 +248,21 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
ip_num_rings = adev->sdma.num_instances;
break;
case AMDGPU_HW_IP_UVD:
- ip_num_rings = adev->uvd.num_uvd_inst;
+ for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+ if (!(adev->uvd.harvest_config & (1 << i)))
+ ip_num_rings++;
+ }
break;
case AMDGPU_HW_IP_VCE:
ip_num_rings = adev->vce.num_rings;
break;
case AMDGPU_HW_IP_UVD_ENC:
+ for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+ if (!(adev->uvd.harvest_config & (1 << i)))
+ ip_num_rings++;
+ }
ip_num_rings =
- adev->uvd.num_enc_rings * adev->uvd.num_uvd_inst;
+ adev->uvd.num_enc_rings * ip_num_rings;
break;
case AMDGPU_HW_IP_VCN_DEC:
ip_num_rings = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 80b5c453f8c1..a07548c99ab8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -255,7 +255,8 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
-
+ if (adev->uvd.harvest_config & (1 << j))
+ continue;
r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
&adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
@@ -309,6 +310,8 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
&adev->uvd.entity);
for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+ if (adev->uvd.harvest_config & (1 << j))
+ continue;
kfree(adev->uvd.inst[j].saved_bo);
amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
@@ -344,6 +347,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
}
for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+ if (adev->uvd.harvest_config & (1 << j))
+ continue;
if (adev->uvd.inst[j].vcpu_bo == NULL)
continue;
@@ -366,6 +371,8 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
int i;
for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
if (adev->uvd.inst[i].vcpu_bo == NULL)
return -EINVAL;
@@ -1160,6 +1167,8 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
unsigned fences = 0, i, j;
for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index 66872286ab12..9cf42454ba81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -46,8 +46,12 @@ struct amdgpu_uvd_inst {
struct amdgpu_ring ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];
struct amdgpu_irq_src irq;
uint32_t srbm_soft_reset;
+ uint32_t instance;
};
+#define AMDGPU_UVD_HARVEST_UVD0 (1 << 0)
+#define AMDGPU_UVD_HARVEST_UVD1 (1 << 1)
+
struct amdgpu_uvd {
const struct firmware *fw; /* UVD firmware */
unsigned fw_version;
@@ -61,6 +65,7 @@ struct amdgpu_uvd {
atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
struct drm_sched_entity entity;
struct delayed_work idle_work;
+ unsigned harvest_config;
};
int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index db5f3d78ab12..8179317be750 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -41,6 +41,12 @@
#include "mmhub/mmhub_1_0_sh_mask.h"
#include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
+#define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7
+#define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1
+//UVD_PG0_CC_UVD_HARVESTING
+#define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1
+#define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L
+
#define UVD7_MAX_HW_INSTANCES_VEGA20 2
static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
@@ -370,10 +376,25 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
static int uvd_v7_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->asic_type == CHIP_VEGA20)
+
+ if (adev->asic_type == CHIP_VEGA20) {
+ u32 harvest;
+ int i;
+
adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
- else
+ for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+ harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);
+ if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) {
+ adev->uvd.harvest_config |= 1 << i;
+ }
+ }
+ if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 |
+ AMDGPU_UVD_HARVEST_UVD1))
+ /* both instances are harvested, disable the block */
+ return -ENOENT;
+ } else {
adev->uvd.num_uvd_inst = 1;
+ }
if (amdgpu_sriov_vf(adev))
adev->uvd.num_enc_rings = 1;
@@ -393,6 +414,8 @@ static int uvd_v7_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+ if (adev->uvd.harvest_config & (1 << j))
+ continue;
/* UVD TRAP */
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
if (r)
@@ -425,6 +448,8 @@ static int uvd_v7_0_sw_init(void *handle)
return r;
for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+ if (adev->uvd.harvest_config & (1 << j))
+ continue;
if (!amdgpu_sriov_vf(adev)) {
ring = &adev->uvd.inst[j].ring;
sprintf(ring->name, "uvd<%d>", j);
@@ -472,6 +497,8 @@ static int uvd_v7_0_sw_fini(void *handle)
return r;
for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+ if (adev->uvd.harvest_config & (1 << j))
+ continue;
for (i = 0; i < adev->uvd.num_enc_rings; ++i)
amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
}
@@ -500,6 +527,8 @@ static int uvd_v7_0_hw_init(void *handle)
goto done;
for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+ if (adev->uvd.harvest_config & (1 << j))
+ continue;
ring = &adev->uvd.inst[j].ring;
if (!amdgpu_sriov_vf(adev)) {
@@ -579,8 +608,11 @@ static int uvd_v7_0_hw_fini(void *handle)
DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
}
- for (i = 0; i < adev->uvd.num_uvd_inst; ++i)
+ for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
adev->uvd.inst[i].ring.ready = false;
+ }
return 0;
}
@@ -623,6 +655,8 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
int i;
for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
@@ -695,6 +729,8 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
adev->uvd.inst[i].ring_enc[0].wptr = 0;
@@ -751,6 +787,8 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
init_table += header->uvd_table_offset;
for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
ring = &adev->uvd.inst[i].ring;
ring->wptr = 0;
size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
@@ -890,6 +928,8 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
int i, j, k, r;
for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
+ if (adev->uvd.harvest_config & (1 << k))
+ continue;
/* disable DPG */
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
@@ -902,6 +942,8 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
uvd_v7_0_mc_resume(adev);
for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
+ if (adev->uvd.harvest_config & (1 << k))
+ continue;
ring = &adev->uvd.inst[k].ring;
/* disable clock gating */
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
@@ -1069,6 +1111,8 @@ static void uvd_v7_0_stop(struct amdgpu_device *adev)
uint8_t i = 0;
for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
/* force RBC into idle state */
WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
@@ -1756,6 +1800,8 @@ static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
int i;
for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
adev->uvd.inst[i].ring.me = i;
DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
@@ -1767,6 +1813,8 @@ static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
int i, j;
for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+ if (adev->uvd.harvest_config & (1 << j))
+ continue;
for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
adev->uvd.inst[j].ring_enc[i].me = j;
@@ -1786,6 +1834,8 @@ static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
int i;
for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+ if (adev->uvd.harvest_config & (1 << i))
+ continue;
adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
}
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related
* [PATCH v9 1/2] regulator: dt-bindings: add QCOM RPMh regulator bindings
From: Doug Anderson @ 2018-07-23 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <56b9d5c38cfe46da1228c54f001a49773c3e31dc.1531531808.git.collinsd@codeaurora.org>
Hi Mark,
On Fri, Jul 13, 2018 at 6:50 PM, David Collins <collinsd@codeaurora.org> wrote:
> Introduce bindings for RPMh regulator devices found on some
> Qualcomm Technlogies, Inc. SoCs. These devices allow a given
> processor within the SoC to make PMIC regulator requests which
> are aggregated within the RPMh hardware block along with requests
> from other processors in the SoC to determine the final PMIC
> regulator hardware state.
>
> Signed-off-by: David Collins <collinsd@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> ---
> .../bindings/regulator/qcom,rpmh-regulator.txt | 160 +++++++++++++++++++++
> .../dt-bindings/regulator/qcom,rpmh-regulator.h | 36 +++++
> 2 files changed, 196 insertions(+)
I know you are still looking for time to review the RPMh-regulator
driver and that's fine. One idea I had though: if the bindings look
OK to you and are less controversial, is there any chance they could
land in the meantime?
Specifically it would be very handy to be able to post up device tree
files that refer to regulators and even get those landed, but they
can't land without the bindings.
If that's not possible then no worries, but I figured I'd check.
-Doug
^ permalink raw reply
* Re: [PATCH v9 1/2] regulator: dt-bindings: add QCOM RPMh regulator bindings
From: Doug Anderson @ 2018-07-23 20:09 UTC (permalink / raw)
To: Mark Brown, David Collins
Cc: Liam Girdwood, Rob Herring, Mark Rutland, linux-arm-msm,
Linux ARM, devicetree, LKML, Rajendra Nayak, Stephen Boyd,
Matthias Kaehlcke
In-Reply-To: <56b9d5c38cfe46da1228c54f001a49773c3e31dc.1531531808.git.collinsd@codeaurora.org>
Hi Mark,
On Fri, Jul 13, 2018 at 6:50 PM, David Collins <collinsd@codeaurora.org> wrote:
> Introduce bindings for RPMh regulator devices found on some
> Qualcomm Technlogies, Inc. SoCs. These devices allow a given
> processor within the SoC to make PMIC regulator requests which
> are aggregated within the RPMh hardware block along with requests
> from other processors in the SoC to determine the final PMIC
> regulator hardware state.
>
> Signed-off-by: David Collins <collinsd@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> ---
> .../bindings/regulator/qcom,rpmh-regulator.txt | 160 +++++++++++++++++++++
> .../dt-bindings/regulator/qcom,rpmh-regulator.h | 36 +++++
> 2 files changed, 196 insertions(+)
I know you are still looking for time to review the RPMh-regulator
driver and that's fine. One idea I had though: if the bindings look
OK to you and are less controversial, is there any chance they could
land in the meantime?
Specifically it would be very handy to be able to post up device tree
files that refer to regulators and even get those landed, but they
can't land without the bindings.
If that's not possible then no worries, but I figured I'd check.
-Doug
^ permalink raw reply
* Re: [PATCH] ethdev: move sanity checks to non-debug paths
From: Andrew Rybchenko @ 2018-07-23 20:07 UTC (permalink / raw)
To: Ananyev, Konstantin, Matan Azrad, Aaron Conole
Cc: dev@dpdk.org, Yigit, Ferruh, Marcelo Leitner, Shahaf Shuler,
Ori Kam, Thomas Monjalon
In-Reply-To: <2601191342CEEE43887BDE71AB977258DF51B4D9@irsmsx105.ger.corp.intel.com>
On 23.07.2018 17:19, Ananyev, Konstantin wrote:
>> -----Original Message-----
>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Matan Azrad
>> Sent: Monday, July 23, 2018 1:14 PM
>> To: Aaron Conole <aconole@redhat.com>
>> Cc: dev@dpdk.org; Yigit, Ferruh <ferruh.yigit@intel.com>; Marcelo Leitner <mleitner@redhat.com>; Shahaf Shuler
>> <shahafs@mellanox.com>; Ori Kam <orika@mellanox.com>; Thomas Monjalon <thomas@monjalon.net>
>> Subject: Re: [dpdk-dev] [PATCH] ethdev: move sanity checks to non-debug paths
>>
>>
>> Hi Aaron
>> From: Aaron Conole
>>> Sent: Monday, July 23, 2018 2:52 PM
>>> To: Matan Azrad <matan@mellanox.com>
>>> Cc: dev@dpdk.org; Ferruh Yigit <ferruh.yigit@intel.com>; Marcelo Leitner
>>> <mleitner@redhat.com>; Shahaf Shuler <shahafs@mellanox.com>; Ori Kam
>>> <orika@mellanox.com>; Thomas Monjalon <thomas@monjalon.net>
>>> Subject: Re: [dpdk-dev] [PATCH] ethdev: move sanity checks to non-debug paths
>>>
>>> Matan Azrad <matan@mellanox.com> writes:
>>>
>>>> Hi Aaron
>>>>
>>>> From: Aaron Conole
>>>>> These checks would have prevented a reported crash in the field. If
>>>>> a user builds without ETHDEV_DEBUG, it should make their application
>>>>> more stable, not less.
>>>>>
>>>>> Many of these functions immediately dereference arrays based on the
>>>>> passed in values, so the sanity checks are quite important.
>>>>>
>>>> These functions are datapath functions.
>>>> Do you really want to add more 3 checks + calculations per each burst call?
>>>> Did you check the performance impact?
>>>> I think that performance numbers must be added for the discussion of this
>>> patch.
>>>
>>> I'll dig up performance numbers - but performance doesn't mean anything if
>>> the application isn't running any longer due to crash.
>> Yes, I understand your point, but think about that, if we are going to defend each user mistake it will cost a lot.
>> For example in Tx path, Adding checks for each mbuf pointer and mbuf data validity will be very expensive.
>>
>> I think the best way is to check the common user mistakes in DEBUG mode to help for application debugging and that's it.
> +1
> The problem is that user provided an invalid input parameters.
> Adding just extra checks inside data-path functions wouldn't solve it.
> Konstantin
+1, I agree with Matan and Konstantin
So, NACK
>>>>> The logs are left as DEBUG only.
>>>>>
>>>>> Cc: Marcelo Leitner <mleitner@redhat.com>
>>>>> Signed-off-by: Aaron Conole <aconole@redhat.com>
>>>>> ---
>>>>> lib/librte_ethdev/rte_ethdev.h | 29 +++++++++++++----------------
>>>>> 1 file changed, 13 insertions(+), 16 deletions(-)
>>>>>
>>>>> diff --git a/lib/librte_ethdev/rte_ethdev.h
>>>>> b/lib/librte_ethdev/rte_ethdev.h index f5f593b31..bfd6a3406 100644
>>>>> --- a/lib/librte_ethdev/rte_ethdev.h
>>>>> +++ b/lib/librte_ethdev/rte_ethdev.h
>>>>> @@ -3805,15 +3805,16 @@ rte_eth_rx_burst(uint16_t port_id, uint16_t
>>>>> queue_id,
>>>>> struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>>>>> uint16_t nb_rx;
>>>>>
>>>>> -#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
>>>>> RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, 0);
>>>>>
>>>>> if (queue_id >= dev->data->nb_rx_queues) {
>>>>> +#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n",
>>> queue_id);
>>>>> +#endif
>>>>> return 0;
>>>>> }
>>>>> -#endif
>>>>> +
>>>>> nb_rx = (*dev->rx_pkt_burst)(dev->data->rx_queues[queue_id],
>>>>> rx_pkts, nb_pkts);
>>>>>
>>>>> @@ -3928,14 +3929,12 @@ rte_eth_rx_descriptor_status(uint16_t
>>>>> port_id, uint16_t queue_id,
>>>>> struct rte_eth_dev *dev;
>>>>> void *rxq;
>>>>>
>>>>> -#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); -#endif
>>>>> dev = &rte_eth_devices[port_id];
>>>>> -#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> +
>>>>> if (queue_id >= dev->data->nb_rx_queues)
>>>>> return -ENODEV;
>>>>> -#endif
>>>>> +
>>>>> RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_descriptor_status, -
>>>>> ENOTSUP);
>>>>> rxq = dev->data->rx_queues[queue_id];
>>>>>
>>>>> @@ -3985,14 +3984,12 @@ static inline int
>>>>> rte_eth_tx_descriptor_status(uint16_t port_id,
>>>>> struct rte_eth_dev *dev;
>>>>> void *txq;
>>>>>
>>>>> -#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); -#endif
>>>>> dev = &rte_eth_devices[port_id];
>>>>> -#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> +
>>>>> if (queue_id >= dev->data->nb_tx_queues)
>>>>> return -ENODEV;
>>>>> -#endif
>>>>> +
>>>>> RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_descriptor_status, -
>>>>> ENOTSUP);
>>>>> txq = dev->data->tx_queues[queue_id];
>>>>>
>>>>> @@ -4071,15 +4068,15 @@ rte_eth_tx_burst(uint16_t port_id, uint16_t
>>>>> queue_id, {
>>>>> struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>>>>>
>>>>> -#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
>>>>> RTE_FUNC_PTR_OR_ERR_RET(*dev->tx_pkt_burst, 0);
>>>>>
>>>>> if (queue_id >= dev->data->nb_tx_queues) {
>>>>> +#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n",
>>> queue_id);
>>>>> +#endif
>>>>> return 0;
>>>>> }
>>>>> -#endif
>>>>>
>>>>> #ifdef RTE_ETHDEV_RXTX_CALLBACKS
>>>>> struct rte_eth_rxtx_callback *cb = dev->pre_tx_burst_cbs[queue_id];
>>>>> @@ -4160,23 +4157,23 @@ rte_eth_tx_prepare(uint16_t port_id, uint16_t
>>>>> queue_id, {
>>>>> struct rte_eth_dev *dev;
>>>>>
>>>>> -#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> if (!rte_eth_dev_is_valid_port(port_id)) {
>>>>> +#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> RTE_ETHDEV_LOG(ERR, "Invalid TX port_id=%u\n", port_id);
>>>>> +#endif
>>>>> rte_errno = -EINVAL;
>>>>> return 0;
>>>>> }
>>>>> -#endif
>>>>>
>>>>> dev = &rte_eth_devices[port_id];
>>>>>
>>>>> -#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> if (queue_id >= dev->data->nb_tx_queues) {
>>>>> +#ifdef RTE_LIBRTE_ETHDEV_DEBUG
>>>>> RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n",
>>> queue_id);
>>>>> +#endif
>>>>> rte_errno = -EINVAL;
>>>>> return 0;
>>>>> }
>>>>> -#endif
>>>>>
>>>>> if (!dev->tx_pkt_prepare)
>>>>> return nb_pkts;
>>>>> --
>>>>> 2.14.3
^ permalink raw reply
* [PATCH i-g-t 4/4] igt/gem_exec_capture: Capture many, many objects
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
In-Reply-To: <20180723200736.29508-1-chris@chris-wilson.co.uk>
Exercise O(N^2) behaviour in reading the error state, and push it to the
extreme.
Reported-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_capture.c | 156 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 153 insertions(+), 3 deletions(-)
diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
index 2dc06ce43..6cc175551 100644
--- a/tests/gem_exec_capture.c
+++ b/tests/gem_exec_capture.c
@@ -23,6 +23,7 @@
#include "igt.h"
#include "igt_device.h"
+#include "igt_rand.h"
#include "igt_sysfs.h"
#define LOCAL_OBJECT_CAPTURE (1 << 7)
@@ -57,7 +58,7 @@ static void check_error_state(int dir, struct drm_i915_gem_exec_object2 *obj)
igt_assert(found);
}
-static void __capture(int fd, int dir, unsigned ring, uint32_t target)
+static void __capture1(int fd, int dir, unsigned ring, uint32_t target)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[4];
@@ -167,10 +168,149 @@ static void capture(int fd, int dir, unsigned ring)
uint32_t handle;
handle = gem_create(fd, 4096);
- __capture(fd, dir, ring, handle);
+ __capture1(fd, dir, ring, handle);
gem_close(fd, handle);
}
+static void __captureN(int fd, int dir, unsigned ring,
+ unsigned int size, int count, unsigned int flags)
+#define RANDOM 0x1
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 *obj;
+ struct drm_i915_gem_relocation_entry reloc[2];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ uint32_t *batch, *seqno;
+ int i;
+
+ obj = calloc(count + 2, sizeof(*obj));
+ igt_assert(obj);
+
+ obj[0].handle = gem_create(fd, 4096);
+ for (i = 0; i < count; i++) {
+ obj[i + 1].handle = gem_create(fd, size);
+ obj[i + 1].flags =
+ LOCAL_OBJECT_CAPTURE | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ if (flags & RANDOM) {
+ uint32_t *ptr;
+
+ ptr = gem_mmap__cpu(fd, obj[i + 1].handle,
+ 0, size, PROT_WRITE);
+ for (unsigned int n = 0; n < size / sizeof(*ptr); n++)
+ ptr[n] = hars_petruska_f54_1_random_unsafe();
+ munmap(ptr, size);
+ }
+ }
+
+ obj[count + 1].handle = gem_create(fd, 4096);
+ obj[count + 1].relocs_ptr = (uintptr_t)reloc;
+ obj[count + 1].relocation_count = ARRAY_SIZE(reloc);
+
+ memset(reloc, 0, sizeof(reloc));
+ reloc[0].target_handle = obj[count + 1].handle; /* recurse */
+ reloc[0].presumed_offset = 0;
+ reloc[0].offset = 5*sizeof(uint32_t);
+ reloc[0].delta = 0;
+ reloc[0].read_domains = I915_GEM_DOMAIN_COMMAND;
+ reloc[0].write_domain = 0;
+
+ reloc[1].target_handle = obj[0].handle; /* breadcrumb */
+ reloc[1].presumed_offset = 0;
+ reloc[1].offset = sizeof(uint32_t);
+ reloc[1].delta = 0;
+ reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[1].write_domain = I915_GEM_DOMAIN_RENDER;
+
+ seqno = gem_mmap__wc(fd, obj[0].handle, 0, 4096, PROT_READ);
+ gem_set_domain(fd, obj[0].handle,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+ batch = gem_mmap__cpu(fd, obj[count + 1].handle, 0, 4096, PROT_WRITE);
+ gem_set_domain(fd, obj[count + 1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ i = 0;
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ batch[++i] = 0;
+ batch[++i] = 0;
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = 0;
+ reloc[1].offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = 0;
+ }
+ batch[++i] = 0xc0ffee;
+ if (gen < 3)
+ batch[++i] = MI_NOOP;
+
+ batch[++i] = MI_BATCH_BUFFER_START; /* not crashed? try again! */
+ if (gen >= 8) {
+ batch[i] |= 1 << 8 | 1;
+ batch[++i] = 0;
+ batch[++i] = 0;
+ } else if (gen >= 6) {
+ batch[i] |= 1 << 8;
+ batch[++i] = 0;
+ } else {
+ batch[i] |= 2 << 6;
+ batch[++i] = 0;
+ if (gen < 4) {
+ batch[i] |= 1;
+ reloc[0].delta = 1;
+ }
+ }
+ munmap(batch, 4096);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = (uintptr_t)obj;
+ execbuf.buffer_count = count + 2;
+ execbuf.flags = ring;
+ if (gen > 3 && gen < 6)
+ execbuf.flags |= I915_EXEC_SECURE;
+ gem_execbuf(fd, &execbuf);
+
+ /* Wait for the request to start */
+ while (*(volatile uint32_t *)seqno != 0xc0ffee)
+ igt_assert(gem_bo_busy(fd, obj[0].handle));
+ munmap(seqno, 4096);
+
+ igt_force_gpu_reset(fd);
+
+ gem_sync(fd, obj[count + 1].handle);
+ gem_close(fd, obj[count + 1].handle);
+ for (i = 0; i < count; i++)
+ gem_close(fd, obj[i + 1].handle);
+ gem_close(fd, obj[0].handle);
+}
+
+static void many(int fd, int dir, unsigned int flags)
+{
+ uint64_t ram, gtt;
+ unsigned long count;
+ char *error;
+
+ gtt = (gem_aperture_size(fd) >> 20) / 4;
+ ram = intel_get_avail_ram_mb() / 4;
+ igt_debug("Available objects in GTT:%"PRIu64", RAM:%"PRIu64"\n",
+ gtt, ram);
+
+ count = min(gtt, ram);
+ igt_require(count > 1);
+
+ intel_require_memory(count, 2 << 20, CHECK_RAM);
+
+ __captureN(fd, dir, 0, 2 << 20, count, flags);
+
+ error = igt_sysfs_get(dir, "error");
+ igt_sysfs_set(dir, "error", "Begone!");
+
+ igt_assert(error);
+ igt_debug("%s\n", error);
+}
+
static void userptr(int fd, int dir)
{
uint32_t handle;
@@ -179,7 +319,7 @@ static void userptr(int fd, int dir)
igt_assert(posix_memalign(&ptr, 4096, 4096) == 0);
igt_require(__gem_userptr(fd, ptr, 4096, 0, 0, &handle) == 0);
- __capture(fd, dir, 0, handle);
+ __capture1(fd, dir, 0, handle);
gem_close(fd, handle);
free(ptr);
@@ -236,6 +376,16 @@ igt_main
}
}
+ igt_subtest_f("many-zero") {
+ igt_require(gem_can_store_dword(fd, 0));
+ many(fd, dir, 0);
+ }
+
+ igt_subtest_f("many-random") {
+ igt_require(gem_can_store_dword(fd, 0));
+ many(fd, dir, RANDOM);
+ }
+
/* And check we can read from different types of objects */
igt_subtest_f("userptr") {
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [Intel-gfx] [PATCH i-g-t 4/4] igt/gem_exec_capture: Capture many, many objects
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
In-Reply-To: <20180723200736.29508-1-chris@chris-wilson.co.uk>
Exercise O(N^2) behaviour in reading the error state, and push it to the
extreme.
Reported-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_capture.c | 156 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 153 insertions(+), 3 deletions(-)
diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
index 2dc06ce43..6cc175551 100644
--- a/tests/gem_exec_capture.c
+++ b/tests/gem_exec_capture.c
@@ -23,6 +23,7 @@
#include "igt.h"
#include "igt_device.h"
+#include "igt_rand.h"
#include "igt_sysfs.h"
#define LOCAL_OBJECT_CAPTURE (1 << 7)
@@ -57,7 +58,7 @@ static void check_error_state(int dir, struct drm_i915_gem_exec_object2 *obj)
igt_assert(found);
}
-static void __capture(int fd, int dir, unsigned ring, uint32_t target)
+static void __capture1(int fd, int dir, unsigned ring, uint32_t target)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[4];
@@ -167,10 +168,149 @@ static void capture(int fd, int dir, unsigned ring)
uint32_t handle;
handle = gem_create(fd, 4096);
- __capture(fd, dir, ring, handle);
+ __capture1(fd, dir, ring, handle);
gem_close(fd, handle);
}
+static void __captureN(int fd, int dir, unsigned ring,
+ unsigned int size, int count, unsigned int flags)
+#define RANDOM 0x1
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 *obj;
+ struct drm_i915_gem_relocation_entry reloc[2];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ uint32_t *batch, *seqno;
+ int i;
+
+ obj = calloc(count + 2, sizeof(*obj));
+ igt_assert(obj);
+
+ obj[0].handle = gem_create(fd, 4096);
+ for (i = 0; i < count; i++) {
+ obj[i + 1].handle = gem_create(fd, size);
+ obj[i + 1].flags =
+ LOCAL_OBJECT_CAPTURE | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ if (flags & RANDOM) {
+ uint32_t *ptr;
+
+ ptr = gem_mmap__cpu(fd, obj[i + 1].handle,
+ 0, size, PROT_WRITE);
+ for (unsigned int n = 0; n < size / sizeof(*ptr); n++)
+ ptr[n] = hars_petruska_f54_1_random_unsafe();
+ munmap(ptr, size);
+ }
+ }
+
+ obj[count + 1].handle = gem_create(fd, 4096);
+ obj[count + 1].relocs_ptr = (uintptr_t)reloc;
+ obj[count + 1].relocation_count = ARRAY_SIZE(reloc);
+
+ memset(reloc, 0, sizeof(reloc));
+ reloc[0].target_handle = obj[count + 1].handle; /* recurse */
+ reloc[0].presumed_offset = 0;
+ reloc[0].offset = 5*sizeof(uint32_t);
+ reloc[0].delta = 0;
+ reloc[0].read_domains = I915_GEM_DOMAIN_COMMAND;
+ reloc[0].write_domain = 0;
+
+ reloc[1].target_handle = obj[0].handle; /* breadcrumb */
+ reloc[1].presumed_offset = 0;
+ reloc[1].offset = sizeof(uint32_t);
+ reloc[1].delta = 0;
+ reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[1].write_domain = I915_GEM_DOMAIN_RENDER;
+
+ seqno = gem_mmap__wc(fd, obj[0].handle, 0, 4096, PROT_READ);
+ gem_set_domain(fd, obj[0].handle,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+ batch = gem_mmap__cpu(fd, obj[count + 1].handle, 0, 4096, PROT_WRITE);
+ gem_set_domain(fd, obj[count + 1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ i = 0;
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ batch[++i] = 0;
+ batch[++i] = 0;
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = 0;
+ reloc[1].offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = 0;
+ }
+ batch[++i] = 0xc0ffee;
+ if (gen < 3)
+ batch[++i] = MI_NOOP;
+
+ batch[++i] = MI_BATCH_BUFFER_START; /* not crashed? try again! */
+ if (gen >= 8) {
+ batch[i] |= 1 << 8 | 1;
+ batch[++i] = 0;
+ batch[++i] = 0;
+ } else if (gen >= 6) {
+ batch[i] |= 1 << 8;
+ batch[++i] = 0;
+ } else {
+ batch[i] |= 2 << 6;
+ batch[++i] = 0;
+ if (gen < 4) {
+ batch[i] |= 1;
+ reloc[0].delta = 1;
+ }
+ }
+ munmap(batch, 4096);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = (uintptr_t)obj;
+ execbuf.buffer_count = count + 2;
+ execbuf.flags = ring;
+ if (gen > 3 && gen < 6)
+ execbuf.flags |= I915_EXEC_SECURE;
+ gem_execbuf(fd, &execbuf);
+
+ /* Wait for the request to start */
+ while (*(volatile uint32_t *)seqno != 0xc0ffee)
+ igt_assert(gem_bo_busy(fd, obj[0].handle));
+ munmap(seqno, 4096);
+
+ igt_force_gpu_reset(fd);
+
+ gem_sync(fd, obj[count + 1].handle);
+ gem_close(fd, obj[count + 1].handle);
+ for (i = 0; i < count; i++)
+ gem_close(fd, obj[i + 1].handle);
+ gem_close(fd, obj[0].handle);
+}
+
+static void many(int fd, int dir, unsigned int flags)
+{
+ uint64_t ram, gtt;
+ unsigned long count;
+ char *error;
+
+ gtt = (gem_aperture_size(fd) >> 20) / 4;
+ ram = intel_get_avail_ram_mb() / 4;
+ igt_debug("Available objects in GTT:%"PRIu64", RAM:%"PRIu64"\n",
+ gtt, ram);
+
+ count = min(gtt, ram);
+ igt_require(count > 1);
+
+ intel_require_memory(count, 2 << 20, CHECK_RAM);
+
+ __captureN(fd, dir, 0, 2 << 20, count, flags);
+
+ error = igt_sysfs_get(dir, "error");
+ igt_sysfs_set(dir, "error", "Begone!");
+
+ igt_assert(error);
+ igt_debug("%s\n", error);
+}
+
static void userptr(int fd, int dir)
{
uint32_t handle;
@@ -179,7 +319,7 @@ static void userptr(int fd, int dir)
igt_assert(posix_memalign(&ptr, 4096, 4096) == 0);
igt_require(__gem_userptr(fd, ptr, 4096, 0, 0, &handle) == 0);
- __capture(fd, dir, 0, handle);
+ __capture1(fd, dir, 0, handle);
gem_close(fd, handle);
free(ptr);
@@ -236,6 +376,16 @@ igt_main
}
}
+ igt_subtest_f("many-zero") {
+ igt_require(gem_can_store_dword(fd, 0));
+ many(fd, dir, 0);
+ }
+
+ igt_subtest_f("many-random") {
+ igt_require(gem_can_store_dword(fd, 0));
+ many(fd, dir, RANDOM);
+ }
+
/* And check we can read from different types of objects */
igt_subtest_f("userptr") {
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [PATCH i-g-t 3/4] igt/gem_exec_schedule: Trim deep runtime
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
In-Reply-To: <20180723200736.29508-1-chris@chris-wilson.co.uk>
Time the runtime for emitting deep dependency tree, while keeping it
full of umpteen thousand requests.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_schedule.c | 83 +++++++++++++++++++++++++++++++++------
1 file changed, 70 insertions(+), 13 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 43ea97e61..0462ce84f 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -748,21 +748,29 @@ static void preemptive_hang(int fd, unsigned ring)
static void deep(int fd, unsigned ring)
{
#define XS 8
- const unsigned int nreq = MAX_PRIO - MIN_PRIO;
- const unsigned size = ALIGN(4*nreq, 4096);
+ const unsigned int max_req = MAX_PRIO - MIN_PRIO;
+ const unsigned size = ALIGN(4*max_req, 4096);
struct timespec tv = {};
IGT_CORK_HANDLE(cork);
+ unsigned int nreq;
uint32_t plug;
uint32_t result, dep[XS];
uint32_t expected = 0;
uint32_t *ptr;
uint32_t *ctx;
+ int dep_nreq;
+ int n;
ctx = malloc(sizeof(*ctx) * MAX_CONTEXTS);
- for (int n = 0; n < MAX_CONTEXTS; n++) {
+ for (n = 0; n < MAX_CONTEXTS; n++) {
ctx[n] = gem_context_create(fd);
}
+ nreq = gem_measure_ring_inflight(fd, ring, 0) / (4 * XS) * MAX_CONTEXTS;
+ if (nreq > max_req)
+ nreq = max_req;
+ igt_info("Using %d requests (prio range %d)\n", nreq, max_req);
+
result = gem_create(fd, size);
for (int m = 0; m < XS; m ++)
dep[m] = gem_create(fd, size);
@@ -774,7 +782,7 @@ static void deep(int fd, unsigned ring)
const uint32_t bbe = MI_BATCH_BUFFER_END;
memset(obj, 0, sizeof(obj));
- for (int n = 0; n < XS; n++)
+ for (n = 0; n < XS; n++)
obj[n].handle = dep[n];
obj[XS].handle = result;
obj[XS+1].handle = gem_create(fd, 4096);
@@ -784,7 +792,7 @@ static void deep(int fd, unsigned ring)
execbuf.buffers_ptr = to_user_pointer(obj);
execbuf.buffer_count = XS + 2;
execbuf.flags = ring;
- for (int n = 0; n < MAX_CONTEXTS; n++) {
+ for (n = 0; n < MAX_CONTEXTS; n++) {
execbuf.rsvd1 = ctx[n];
gem_execbuf(fd, &execbuf);
}
@@ -795,15 +803,62 @@ static void deep(int fd, unsigned ring)
plug = igt_cork_plug(&cork, fd);
/* Create a deep dependency chain, with a few branches */
- for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 8; n++) {
- uint32_t context = ctx[n % MAX_CONTEXTS];
- gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
+ for (n = 0; n < nreq && igt_seconds_elapsed(&tv) < 2; n++) {
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 obj[3];
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffers_ptr = to_user_pointer(obj),
+ .buffer_count = 3,
+ .flags = ring | (gen < 6 ? I915_EXEC_SECURE : 0),
+ .rsvd1 = ctx[n % MAX_CONTEXTS],
+ };
+ uint32_t batch[16];
+ int i;
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = plug;
+
+ memset(&reloc, 0, sizeof(reloc));
+ reloc.presumed_offset = 0;
+ reloc.offset = sizeof(uint32_t);
+ reloc.delta = sizeof(uint32_t) * n;
+ reloc.read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc.write_domain = I915_GEM_DOMAIN_RENDER;
+ obj[2].handle = gem_create(fd, 4096);
+ obj[2].relocs_ptr = to_user_pointer(&reloc);
+ obj[2].relocation_count = 1;
+
+ i = 0;
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ batch[++i] = reloc.delta;
+ batch[++i] = 0;
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = reloc.delta;
+ reloc.offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = reloc.delta;
+ }
+ batch[++i] = eb.rsvd1;
+ batch[++i] = MI_BATCH_BUFFER_END;
+ gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
- for (int m = 0; m < XS; m++)
- store_dword(fd, context, ring, dep[m], 4*n, context, plug, I915_GEM_DOMAIN_INSTRUCTION);
+ gem_context_set_priority(fd, eb.rsvd1, MAX_PRIO - nreq + n);
+ for (int m = 0; m < XS; m++) {
+ obj[1].handle = dep[m];
+ reloc.target_handle = obj[1].handle;
+ gem_execbuf(fd, &eb);
+ }
+ gem_close(fd, obj[2].handle);
}
+ igt_info("First deptree: %d requests [%.3fs]\n",
+ n * XS, 1e-9*igt_nsec_elapsed(&tv));
+ dep_nreq = n;
- for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 6; n++) {
+ for (n = 0; n < nreq && igt_seconds_elapsed(&tv) < 4; n++) {
uint32_t context = ctx[n % MAX_CONTEXTS];
gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
@@ -813,12 +868,14 @@ static void deep(int fd, unsigned ring)
}
expected = context;
}
+ igt_info("Second deptree: %d requests [%.3fs]\n",
+ n * XS, 1e-9*igt_nsec_elapsed(&tv));
unplug_show_queue(fd, &cork, ring);
gem_close(fd, plug);
igt_require(expected); /* too slow */
- for (int n = 0; n < MAX_CONTEXTS; n++)
+ for (n = 0; n < MAX_CONTEXTS; n++)
gem_context_destroy(fd, ctx[n]);
for (int m = 0; m < XS; m++) {
@@ -827,7 +884,7 @@ static void deep(int fd, unsigned ring)
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
gem_close(fd, dep[m]);
- for (int n = 0; n < nreq; n++)
+ for (n = 0; n < dep_nreq; n++)
igt_assert_eq_u32(ptr[n], ctx[n % MAX_CONTEXTS]);
munmap(ptr, size);
}
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [Intel-gfx] [PATCH i-g-t 3/4] igt/gem_exec_schedule: Trim deep runtime
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
In-Reply-To: <20180723200736.29508-1-chris@chris-wilson.co.uk>
Time the runtime for emitting deep dependency tree, while keeping it
full of umpteen thousand requests.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_schedule.c | 83 +++++++++++++++++++++++++++++++++------
1 file changed, 70 insertions(+), 13 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 43ea97e61..0462ce84f 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -748,21 +748,29 @@ static void preemptive_hang(int fd, unsigned ring)
static void deep(int fd, unsigned ring)
{
#define XS 8
- const unsigned int nreq = MAX_PRIO - MIN_PRIO;
- const unsigned size = ALIGN(4*nreq, 4096);
+ const unsigned int max_req = MAX_PRIO - MIN_PRIO;
+ const unsigned size = ALIGN(4*max_req, 4096);
struct timespec tv = {};
IGT_CORK_HANDLE(cork);
+ unsigned int nreq;
uint32_t plug;
uint32_t result, dep[XS];
uint32_t expected = 0;
uint32_t *ptr;
uint32_t *ctx;
+ int dep_nreq;
+ int n;
ctx = malloc(sizeof(*ctx) * MAX_CONTEXTS);
- for (int n = 0; n < MAX_CONTEXTS; n++) {
+ for (n = 0; n < MAX_CONTEXTS; n++) {
ctx[n] = gem_context_create(fd);
}
+ nreq = gem_measure_ring_inflight(fd, ring, 0) / (4 * XS) * MAX_CONTEXTS;
+ if (nreq > max_req)
+ nreq = max_req;
+ igt_info("Using %d requests (prio range %d)\n", nreq, max_req);
+
result = gem_create(fd, size);
for (int m = 0; m < XS; m ++)
dep[m] = gem_create(fd, size);
@@ -774,7 +782,7 @@ static void deep(int fd, unsigned ring)
const uint32_t bbe = MI_BATCH_BUFFER_END;
memset(obj, 0, sizeof(obj));
- for (int n = 0; n < XS; n++)
+ for (n = 0; n < XS; n++)
obj[n].handle = dep[n];
obj[XS].handle = result;
obj[XS+1].handle = gem_create(fd, 4096);
@@ -784,7 +792,7 @@ static void deep(int fd, unsigned ring)
execbuf.buffers_ptr = to_user_pointer(obj);
execbuf.buffer_count = XS + 2;
execbuf.flags = ring;
- for (int n = 0; n < MAX_CONTEXTS; n++) {
+ for (n = 0; n < MAX_CONTEXTS; n++) {
execbuf.rsvd1 = ctx[n];
gem_execbuf(fd, &execbuf);
}
@@ -795,15 +803,62 @@ static void deep(int fd, unsigned ring)
plug = igt_cork_plug(&cork, fd);
/* Create a deep dependency chain, with a few branches */
- for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 8; n++) {
- uint32_t context = ctx[n % MAX_CONTEXTS];
- gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
+ for (n = 0; n < nreq && igt_seconds_elapsed(&tv) < 2; n++) {
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 obj[3];
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffers_ptr = to_user_pointer(obj),
+ .buffer_count = 3,
+ .flags = ring | (gen < 6 ? I915_EXEC_SECURE : 0),
+ .rsvd1 = ctx[n % MAX_CONTEXTS],
+ };
+ uint32_t batch[16];
+ int i;
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = plug;
+
+ memset(&reloc, 0, sizeof(reloc));
+ reloc.presumed_offset = 0;
+ reloc.offset = sizeof(uint32_t);
+ reloc.delta = sizeof(uint32_t) * n;
+ reloc.read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc.write_domain = I915_GEM_DOMAIN_RENDER;
+ obj[2].handle = gem_create(fd, 4096);
+ obj[2].relocs_ptr = to_user_pointer(&reloc);
+ obj[2].relocation_count = 1;
+
+ i = 0;
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ batch[++i] = reloc.delta;
+ batch[++i] = 0;
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = reloc.delta;
+ reloc.offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = reloc.delta;
+ }
+ batch[++i] = eb.rsvd1;
+ batch[++i] = MI_BATCH_BUFFER_END;
+ gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
- for (int m = 0; m < XS; m++)
- store_dword(fd, context, ring, dep[m], 4*n, context, plug, I915_GEM_DOMAIN_INSTRUCTION);
+ gem_context_set_priority(fd, eb.rsvd1, MAX_PRIO - nreq + n);
+ for (int m = 0; m < XS; m++) {
+ obj[1].handle = dep[m];
+ reloc.target_handle = obj[1].handle;
+ gem_execbuf(fd, &eb);
+ }
+ gem_close(fd, obj[2].handle);
}
+ igt_info("First deptree: %d requests [%.3fs]\n",
+ n * XS, 1e-9*igt_nsec_elapsed(&tv));
+ dep_nreq = n;
- for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 6; n++) {
+ for (n = 0; n < nreq && igt_seconds_elapsed(&tv) < 4; n++) {
uint32_t context = ctx[n % MAX_CONTEXTS];
gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
@@ -813,12 +868,14 @@ static void deep(int fd, unsigned ring)
}
expected = context;
}
+ igt_info("Second deptree: %d requests [%.3fs]\n",
+ n * XS, 1e-9*igt_nsec_elapsed(&tv));
unplug_show_queue(fd, &cork, ring);
gem_close(fd, plug);
igt_require(expected); /* too slow */
- for (int n = 0; n < MAX_CONTEXTS; n++)
+ for (n = 0; n < MAX_CONTEXTS; n++)
gem_context_destroy(fd, ctx[n]);
for (int m = 0; m < XS; m++) {
@@ -827,7 +884,7 @@ static void deep(int fd, unsigned ring)
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
gem_close(fd, dep[m]);
- for (int n = 0; n < nreq; n++)
+ for (n = 0; n < dep_nreq; n++)
igt_assert_eq_u32(ptr[n], ctx[n % MAX_CONTEXTS]);
munmap(ptr, size);
}
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [PATCH i-g-t 2/4] igt/gem_tiled_fence_blits: Remove libdrm_intel dependence
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
In-Reply-To: <20180723200736.29508-1-chris@chris-wilson.co.uk>
Modernise the test to use igt's ioctl library as opposed to the
antiquated libdrm_intel.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_tiled_fence_blits.c | 188 ++++++++++++++++++++--------------
1 file changed, 110 insertions(+), 78 deletions(-)
diff --git a/tests/gem_tiled_fence_blits.c b/tests/gem_tiled_fence_blits.c
index 693e96cec..5c1e1a68a 100644
--- a/tests/gem_tiled_fence_blits.c
+++ b/tests/gem_tiled_fence_blits.c
@@ -42,54 +42,38 @@
*/
#include "igt.h"
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <errno.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-
-#include <drm.h>
-
-#include "intel_bufmgr.h"
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-enum {width=512, height=512};
-static const int bo_size = width * height * 4;
+#include "igt_x86.h"
+
+enum { width = 512, height = 512 };
static uint32_t linear[width * height];
+static const int bo_size = sizeof(linear);
-static drm_intel_bo *
-create_bo(int fd, uint32_t start_val)
+static uint32_t create_bo(int fd, uint32_t start_val)
{
- drm_intel_bo *bo;
- uint32_t tiling = I915_TILING_X;
- int ret, i;
+ uint32_t handle;
+ uint32_t *ptr;
- bo = drm_intel_bo_alloc(bufmgr, "tiled bo", bo_size, 4096);
- ret = drm_intel_bo_set_tiling(bo, &tiling, width * 4);
- igt_assert_eq(ret, 0);
- igt_assert(tiling == I915_TILING_X);
+ handle = gem_create(fd, bo_size);
+ gem_set_tiling(fd, handle, I915_TILING_X, width * 4);
/* Fill the BO with dwords starting at start_val */
- for (i = 0; i < width * height; i++)
- linear[i] = start_val++;
-
- gem_write(fd, bo->handle, 0, linear, sizeof(linear));
+ ptr = gem_mmap__gtt(fd, handle, bo_size, PROT_WRITE);
+ for (int i = 0; i < width * height; i++)
+ ptr[i] = start_val++;
+ munmap(ptr, bo_size);
- return bo;
+ return handle;
}
-static void
-check_bo(int fd, drm_intel_bo *bo, uint32_t start_val)
+static void check_bo(int fd, uint32_t handle, uint32_t start_val)
{
- int i;
+ uint32_t *ptr;
- gem_read(fd, bo->handle, 0, linear, sizeof(linear));
+ ptr = gem_mmap__gtt(fd, handle, bo_size, PROT_READ);
+ igt_memcpy_from_wc(linear, ptr, bo_size);
+ munmap(ptr, bo_size);
- for (i = 0; i < width * height; i++) {
+ for (int i = 0; i < width * height; i++) {
igt_assert_f(linear[i] == start_val,
"Expected 0x%08x, found 0x%08x "
"at offset 0x%08x\n",
@@ -98,73 +82,122 @@ check_bo(int fd, drm_intel_bo *bo, uint32_t start_val)
}
}
+static uint32_t
+create_batch(int fd, struct drm_i915_gem_relocation_entry *reloc)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ const bool has_64b_reloc = gen >= 8;
+ uint32_t *batch;
+ uint32_t handle;
+ uint32_t pitch;
+ int i = 0;
+
+ handle = gem_create(fd, 4096);
+ batch = gem_mmap__cpu(fd, handle, 0, 4096, PROT_WRITE);
+
+ batch[i] = (XY_SRC_COPY_BLT_CMD |
+ XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB);
+ if (gen >= 4) {
+ batch[i] |= (XY_SRC_COPY_BLT_SRC_TILED |
+ XY_SRC_COPY_BLT_DST_TILED);
+ pitch = width;
+ } else {
+ pitch = 4 * width;
+ }
+ batch[i++] |= 6 + 2 * has_64b_reloc;
+
+ batch[i++] = 3 << 24 | 0xcc << 16 | pitch;
+ batch[i++] = 0; /* dst (x1, y1) */
+ batch[i++] = height << 16 | width; /* dst (x2 y2) */
+ reloc[0].offset = sizeof(*batch) * i;
+ reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+ batch[i++] = 0;
+ if (has_64b_reloc)
+ batch[i++] = 0;
+
+ batch[i++] = 0; /* src (x1, y1) */
+ batch[i++] = pitch;
+ reloc[1].offset = sizeof(*batch) * i;
+ reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+ batch[i++] = 0;
+ if (has_64b_reloc)
+ batch[i++] = 0;
+
+ batch[i++] = MI_BATCH_BUFFER_END;
+ munmap(batch, 4096);
+
+ return handle;
+}
+
static void run_test(int fd, int count)
{
- drm_intel_bo **bo;
- uint32_t *bo_start_val;
+ struct drm_i915_gem_relocation_entry reloc[2];
+ struct drm_i915_gem_exec_object2 obj[3];
+ struct drm_i915_gem_execbuffer2 eb;
+ uint32_t *bo, *bo_start_val;
uint32_t start = 0;
- int i;
+
+ memset(reloc, 0, sizeof(reloc));
+ memset(obj, 0, sizeof(obj));
+ obj[2].handle = create_batch(fd, reloc);
+ obj[2].relocs_ptr = to_user_pointer(reloc);
+ obj[2].relocation_count = ARRAY_SIZE(reloc);
+
+ memset(&eb, 0, sizeof(eb));
+ eb.buffers_ptr = to_user_pointer(obj);
+ eb.buffer_count = ARRAY_SIZE(obj);
+ if (intel_gen(intel_get_drm_devid(fd)) >= 6)
+ eb.flags = I915_EXEC_BLT;
count |= 1;
igt_info("Using %d 1MiB buffers\n", count);
- bo = malloc(count * sizeof(*bo));
- bo_start_val = malloc(count * sizeof(*bo_start_val));
- igt_assert(bo && bo_start_val);
-
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- drm_intel_bufmgr_gem_enable_reuse(bufmgr);
- batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+ bo = malloc(count * (sizeof(*bo) + sizeof(*bo_start_val)));
+ igt_assert(bo);
+ bo_start_val = bo + count;
- for (i = 0; i < count; i++) {
+ for (int i = 0; i < count; i++) {
bo[i] = create_bo(fd, start);
bo_start_val[i] = start;
-
- /*
- igt_info("Creating bo %d\n", i);
- check_bo(bo[i], bo_start_val[i]);
- */
-
start += width * height;
}
- for (i = 0; i < count; i++) {
- int src = count - i - 1;
- intel_copy_bo(batch, bo[i], bo[src], bo_size);
- bo_start_val[i] = bo_start_val[src];
+ for (int dst = 0; dst < count; dst++) {
+ int src = count - dst - 1;
+
+ if (src == dst)
+ continue;
+
+ reloc[0].target_handle = obj[0].handle = bo[dst];
+ reloc[1].target_handle = obj[1].handle = bo[src];
+
+ gem_execbuf(fd, &eb);
+ bo_start_val[dst] = bo_start_val[src];
}
- for (i = 0; i < count * 4; i++) {
+ for (int i = 0; i < count * 4; i++) {
int src = random() % count;
int dst = random() % count;
if (src == dst)
continue;
- intel_copy_bo(batch, bo[dst], bo[src], bo_size);
- bo_start_val[dst] = bo_start_val[src];
+ reloc[0].target_handle = obj[0].handle = bo[dst];
+ reloc[1].target_handle = obj[1].handle = bo[src];
- /*
- check_bo(bo[dst], bo_start_val[dst]);
- igt_info("%d: copy bo %d to %d\n", i, src, dst);
- */
+ gem_execbuf(fd, &eb);
+ bo_start_val[dst] = bo_start_val[src];
}
- for (i = 0; i < count; i++) {
- /*
- igt_info("check %d\n", i);
- */
+ for (int i = 0; i < count; i++) {
check_bo(fd, bo[i], bo_start_val[i]);
-
- drm_intel_bo_unreference(bo[i]);
- bo[i] = NULL;
+ gem_close(fd, bo[i]);
}
-
- intel_batchbuffer_free(batch);
- drm_intel_bufmgr_destroy(bufmgr);
-
- free(bo_start_val);
free(bo);
+
+ gem_close(fd, obj[2].handle);
}
#define MAX_32b ((1ull << 32) - 4096)
@@ -178,9 +211,8 @@ igt_main
igt_require_gem(fd);
}
- igt_subtest("basic") {
+ igt_subtest("basic")
run_test (fd, 2);
- }
/* the rest of the tests are too long for simulation */
igt_skip_on_simulation();
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [Intel-gfx] [PATCH i-g-t 2/4] igt/gem_tiled_fence_blits: Remove libdrm_intel dependence
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
In-Reply-To: <20180723200736.29508-1-chris@chris-wilson.co.uk>
Modernise the test to use igt's ioctl library as opposed to the
antiquated libdrm_intel.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_tiled_fence_blits.c | 188 ++++++++++++++++++++--------------
1 file changed, 110 insertions(+), 78 deletions(-)
diff --git a/tests/gem_tiled_fence_blits.c b/tests/gem_tiled_fence_blits.c
index 693e96cec..5c1e1a68a 100644
--- a/tests/gem_tiled_fence_blits.c
+++ b/tests/gem_tiled_fence_blits.c
@@ -42,54 +42,38 @@
*/
#include "igt.h"
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <errno.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-
-#include <drm.h>
-
-#include "intel_bufmgr.h"
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-enum {width=512, height=512};
-static const int bo_size = width * height * 4;
+#include "igt_x86.h"
+
+enum { width = 512, height = 512 };
static uint32_t linear[width * height];
+static const int bo_size = sizeof(linear);
-static drm_intel_bo *
-create_bo(int fd, uint32_t start_val)
+static uint32_t create_bo(int fd, uint32_t start_val)
{
- drm_intel_bo *bo;
- uint32_t tiling = I915_TILING_X;
- int ret, i;
+ uint32_t handle;
+ uint32_t *ptr;
- bo = drm_intel_bo_alloc(bufmgr, "tiled bo", bo_size, 4096);
- ret = drm_intel_bo_set_tiling(bo, &tiling, width * 4);
- igt_assert_eq(ret, 0);
- igt_assert(tiling == I915_TILING_X);
+ handle = gem_create(fd, bo_size);
+ gem_set_tiling(fd, handle, I915_TILING_X, width * 4);
/* Fill the BO with dwords starting at start_val */
- for (i = 0; i < width * height; i++)
- linear[i] = start_val++;
-
- gem_write(fd, bo->handle, 0, linear, sizeof(linear));
+ ptr = gem_mmap__gtt(fd, handle, bo_size, PROT_WRITE);
+ for (int i = 0; i < width * height; i++)
+ ptr[i] = start_val++;
+ munmap(ptr, bo_size);
- return bo;
+ return handle;
}
-static void
-check_bo(int fd, drm_intel_bo *bo, uint32_t start_val)
+static void check_bo(int fd, uint32_t handle, uint32_t start_val)
{
- int i;
+ uint32_t *ptr;
- gem_read(fd, bo->handle, 0, linear, sizeof(linear));
+ ptr = gem_mmap__gtt(fd, handle, bo_size, PROT_READ);
+ igt_memcpy_from_wc(linear, ptr, bo_size);
+ munmap(ptr, bo_size);
- for (i = 0; i < width * height; i++) {
+ for (int i = 0; i < width * height; i++) {
igt_assert_f(linear[i] == start_val,
"Expected 0x%08x, found 0x%08x "
"at offset 0x%08x\n",
@@ -98,73 +82,122 @@ check_bo(int fd, drm_intel_bo *bo, uint32_t start_val)
}
}
+static uint32_t
+create_batch(int fd, struct drm_i915_gem_relocation_entry *reloc)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ const bool has_64b_reloc = gen >= 8;
+ uint32_t *batch;
+ uint32_t handle;
+ uint32_t pitch;
+ int i = 0;
+
+ handle = gem_create(fd, 4096);
+ batch = gem_mmap__cpu(fd, handle, 0, 4096, PROT_WRITE);
+
+ batch[i] = (XY_SRC_COPY_BLT_CMD |
+ XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB);
+ if (gen >= 4) {
+ batch[i] |= (XY_SRC_COPY_BLT_SRC_TILED |
+ XY_SRC_COPY_BLT_DST_TILED);
+ pitch = width;
+ } else {
+ pitch = 4 * width;
+ }
+ batch[i++] |= 6 + 2 * has_64b_reloc;
+
+ batch[i++] = 3 << 24 | 0xcc << 16 | pitch;
+ batch[i++] = 0; /* dst (x1, y1) */
+ batch[i++] = height << 16 | width; /* dst (x2 y2) */
+ reloc[0].offset = sizeof(*batch) * i;
+ reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+ batch[i++] = 0;
+ if (has_64b_reloc)
+ batch[i++] = 0;
+
+ batch[i++] = 0; /* src (x1, y1) */
+ batch[i++] = pitch;
+ reloc[1].offset = sizeof(*batch) * i;
+ reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+ batch[i++] = 0;
+ if (has_64b_reloc)
+ batch[i++] = 0;
+
+ batch[i++] = MI_BATCH_BUFFER_END;
+ munmap(batch, 4096);
+
+ return handle;
+}
+
static void run_test(int fd, int count)
{
- drm_intel_bo **bo;
- uint32_t *bo_start_val;
+ struct drm_i915_gem_relocation_entry reloc[2];
+ struct drm_i915_gem_exec_object2 obj[3];
+ struct drm_i915_gem_execbuffer2 eb;
+ uint32_t *bo, *bo_start_val;
uint32_t start = 0;
- int i;
+
+ memset(reloc, 0, sizeof(reloc));
+ memset(obj, 0, sizeof(obj));
+ obj[2].handle = create_batch(fd, reloc);
+ obj[2].relocs_ptr = to_user_pointer(reloc);
+ obj[2].relocation_count = ARRAY_SIZE(reloc);
+
+ memset(&eb, 0, sizeof(eb));
+ eb.buffers_ptr = to_user_pointer(obj);
+ eb.buffer_count = ARRAY_SIZE(obj);
+ if (intel_gen(intel_get_drm_devid(fd)) >= 6)
+ eb.flags = I915_EXEC_BLT;
count |= 1;
igt_info("Using %d 1MiB buffers\n", count);
- bo = malloc(count * sizeof(*bo));
- bo_start_val = malloc(count * sizeof(*bo_start_val));
- igt_assert(bo && bo_start_val);
-
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- drm_intel_bufmgr_gem_enable_reuse(bufmgr);
- batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+ bo = malloc(count * (sizeof(*bo) + sizeof(*bo_start_val)));
+ igt_assert(bo);
+ bo_start_val = bo + count;
- for (i = 0; i < count; i++) {
+ for (int i = 0; i < count; i++) {
bo[i] = create_bo(fd, start);
bo_start_val[i] = start;
-
- /*
- igt_info("Creating bo %d\n", i);
- check_bo(bo[i], bo_start_val[i]);
- */
-
start += width * height;
}
- for (i = 0; i < count; i++) {
- int src = count - i - 1;
- intel_copy_bo(batch, bo[i], bo[src], bo_size);
- bo_start_val[i] = bo_start_val[src];
+ for (int dst = 0; dst < count; dst++) {
+ int src = count - dst - 1;
+
+ if (src == dst)
+ continue;
+
+ reloc[0].target_handle = obj[0].handle = bo[dst];
+ reloc[1].target_handle = obj[1].handle = bo[src];
+
+ gem_execbuf(fd, &eb);
+ bo_start_val[dst] = bo_start_val[src];
}
- for (i = 0; i < count * 4; i++) {
+ for (int i = 0; i < count * 4; i++) {
int src = random() % count;
int dst = random() % count;
if (src == dst)
continue;
- intel_copy_bo(batch, bo[dst], bo[src], bo_size);
- bo_start_val[dst] = bo_start_val[src];
+ reloc[0].target_handle = obj[0].handle = bo[dst];
+ reloc[1].target_handle = obj[1].handle = bo[src];
- /*
- check_bo(bo[dst], bo_start_val[dst]);
- igt_info("%d: copy bo %d to %d\n", i, src, dst);
- */
+ gem_execbuf(fd, &eb);
+ bo_start_val[dst] = bo_start_val[src];
}
- for (i = 0; i < count; i++) {
- /*
- igt_info("check %d\n", i);
- */
+ for (int i = 0; i < count; i++) {
check_bo(fd, bo[i], bo_start_val[i]);
-
- drm_intel_bo_unreference(bo[i]);
- bo[i] = NULL;
+ gem_close(fd, bo[i]);
}
-
- intel_batchbuffer_free(batch);
- drm_intel_bufmgr_destroy(bufmgr);
-
- free(bo_start_val);
free(bo);
+
+ gem_close(fd, obj[2].handle);
}
#define MAX_32b ((1ull << 32) - 4096)
@@ -178,9 +211,8 @@ igt_main
igt_require_gem(fd);
}
- igt_subtest("basic") {
+ igt_subtest("basic")
run_test (fd, 2);
- }
/* the rest of the tests are too long for simulation */
igt_skip_on_simulation();
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.