* [PATCH] dm-verity: Use message limit for data block corruption message.
From: Milan Broz @ 2019-06-20 11:00 UTC (permalink / raw)
To: dm-devel; +Cc: Milan Broz
The dm-verity already uses DMERR_LIMIT on other places, so it
should also limit repeated data block corruption messages.
Signed-off-by: Milan Broz <gmazyland@gmail.com>
---
drivers/md/dm-verity-target.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/md/dm-verity-target.c b/drivers/md/dm-verity-target.c
index 720d06531aa3..08f83e160ad5 100644
--- a/drivers/md/dm-verity-target.c
+++ b/drivers/md/dm-verity-target.c
@@ -235,7 +235,7 @@ static int verity_handle_err(struct dm_verity *v, enum verity_block_type type,
BUG();
}
- DMERR("%s: %s block %llu is corrupted", v->data_dev->name, type_str,
+ DMERR_LIMIT("%s: %s block %llu is corrupted", v->data_dev->name, type_str,
block);
if (v->corrupted_errs == DM_VERITY_MAX_CORRUPTED_ERRS)
--
2.20.1
^ permalink raw reply related
* git fetch --shallow-since hangs
From: Yuri D'Elia @ 2019-06-20 10:59 UTC (permalink / raw)
To: git
I'm trying to run git fetch using --shallow-since with a date range that
results in no commits to be selected.
In this scenario the command hangs indefinitely:
git fetch --shallow-since=2019-05-20 -vv
Server supports multi_ack_detailed
Server supports side-band-64k
Server supports ofs-delta
Server version is git/2.21.0
want 33eeead1a93fed4d25ff90b0b45acec5d822c13c (refs/heads/B-2012-04)
want 49455fcb45a950adf7702d96a2be0ff70cd06577 (refs/heads/B-2012-07)
want c9964f78fd7d1a43db7abca9d2ed2d04ffc7d9a3 (refs/heads/B-2012-08)
want bb8869e3c2697c901b27658cadeb994dd8193897 (refs/heads/B-2012-11)
want 386210eb1ed98abeaa678cc90de639a7773d0802 (refs/heads/B-2013-04)
want b1828494a89fe4532549df31ff93a7816b7c6341 (refs/heads/B-2013-07)
want ff6829912631132fe9b6d8880a6ea8a14676b5c9 (refs/heads/B-2013-09)
want 4c59a0e2317b3bbd6a8bfdad89dbc2c8ca172f8d (refs/heads/B-2013-12)
want ce9729b1c2f26f5a1eab6c623d710df50b4e87fc (refs/heads/B-2014-03)
want 39db34fc97fcafb43faaaba25618473cb2fa8ed6 (refs/heads/B-2014-08)
want f710bb0552db364c40cac542fb591af3b384210c (refs/heads/B-2014-12)
want d6569610cf5da4aced818ba246aa9bc3ad4d7c4a (refs/heads/B-2015-04)
want 3333479999a695f07c30ffca319fa38fc74e01e3 (refs/heads/B-2017-05)
want 111801742054e910a214fca96531824e6f806bd8 (refs/heads/V-2012-04)
want e64b751dd156ee7ee06521b9670284fbe2b79b8e (refs/heads/V-2012-04.1)
want 8bf4adb022e39d06872758d68672fc6f327513cb (refs/heads/V-2012-04.2)
want 31254791e193524c634e19dbcd766b0254f0f21b (refs/heads/V-2012-07)
want 245045e41db2e87c9467830d8fdb570a17b321ed (refs/heads/V-2012-07.1)
want 6ae10ad37c9083e83a43b1679d5514302ce0355d (refs/heads/V-2012-07.2)
want f07291acd0eddddb168d322e27c9425ca084f239 (refs/heads/V-2012-08.1)
want 4a5e3ab5f4eb412b905ddb7e91e0db70bd6cd17f (refs/heads/V-2012-11.1)
want 4b36f254523dbc1d2a80f29886d96cb9a6851584 (refs/heads/V-2013-04)
want f2040101186b31bc99e0f8d4c370101ad0f45ac8 (refs/heads/V-2013-07)
want ba38be154fb9b5627e8c74b2cd75df628961d998 (refs/heads/V-2013-07.1)
want 6029a5638a486886be507c78cc876f266dca2cc7 (refs/heads/V-2013-09)
want 370adcc9a4e82b75a83a999f6cf08d83cba31ce8 (refs/heads/V-2013-09.1)
want d89488b9e3dbd53e4b96bb00f1075901306fcf58 (refs/heads/V-2013-12)
want 86f8eb18bc5657566793ce7ec9c3c05de9de994b (refs/heads/V-2014-03)
want da6f1539444152bff219732ce694454a33444457 (refs/heads/V-2014-03.1)
want b68d4411d16d293817127856f396d460894e8978 (refs/heads/V-2014-03.2)
want d11d83083b31d44940ff78b0a8e656f21473ab46 (refs/heads/V-2014-08)
want 6d81e7ce60bf125c1cd5528a943e73164f8d3bbe (refs/heads/V-2014-08.1)
want 648f93cab60e4525b4278aa172b50740040ce817 (refs/heads/V-2014-12)
want baf41800559a7a3b0d0c6963f01c04bbd4d65be5 (refs/heads/V-2015-04)
want 619d51d2592cd8dc572c252f4c7b169c04aad6fb (refs/heads/V-2017-05)
want ef021b04df54a5f94e164b79133f1e64b9edc02e (refs/heads/master)
fatal: no commits selected for shallow requests
<hangs here>
I reproduced this on the client side using git 2.20.1 and git
2.22.0.455.g172b71a6c5 (the latest debian unstable package).
^ permalink raw reply
* Re: [PATCH v2 43/52] powerpc/64s/exception: machine check early only runs in HV mode
From: Mahesh Jagannath Salgaonkar @ 2019-06-20 10:57 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: linuxppc-dev
In-Reply-To: <1561025688.p6bobskuv9.astroid@bobo.none>
On 6/20/19 3:46 PM, Nicholas Piggin wrote:
> Mahesh J Salgaonkar's on June 20, 2019 7:53 pm:
>> On 2019-06-20 15:14:50 Thu, Nicholas Piggin wrote:
>>> machine_check_common_early and machine_check_handle_early only run in
>>> HVMODE. Remove dead code.
>>
>> That's not true. For pseries guest with FWNMI enabled hypervisor,
>> machine_check_common_early gets called in non-HV mode as well.
>>
>> machine_check_fwnmi
>> machine_check_common_early
>> machine_check_handle_early
>> machine_check_early
>> pseries_machine_check_realmode
>
> Yep, yep I was confused by the earlier patch. So we're only doing the
> early machine check path for the FWNMI case?
yes.
>
> Thanks,
> Nick
>
^ permalink raw reply
* [U-Boot] [PATCH v4.1 4/6] rockchip: rk3399: Get bl31.elf via BL31
From: Jagan Teki @ 2019-06-20 10:59 UTC (permalink / raw)
To: u-boot
Right now rockchip platform need to copy bl31.elf into u-boot
source directory to make use of building u-boot.itb.
So, add environment variable BL31 like Allwinner SoC so-that the
bl31.elf would available via BL31.
If the builds are not exporting BL31 env, the make_fit_atf.py
explicitly create dummy bl31.elf in u-boot root directory to
satisfy travis builds and it will show the warning on console as
WARNING: BL31 file bl31.elf NOT found, resulting binary is non-functional
WARNING: Please read Building section in doc/README.rockchip
Note, that the dummy bl31 files were created during not exporting
BL31 case would be removed via clean target in Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v4.1:
- Check BL31 env first instead of bl31.elf PWD.
Makefile | 2 +-
arch/arm/mach-rockchip/make_fit_atf.py | 19 +++++++++++++++++--
doc/README.rockchip | 4 ++--
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/Makefile b/Makefile
index a503ab9fc1..3ede10ff68 100644
--- a/Makefile
+++ b/Makefile
@@ -1848,7 +1848,7 @@ clean: $(clean-dirs)
-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f \
- bl31_*.bin image.map
+ bl31.c bl31.elf bl31_*.bin image.map
# mrproper - Delete all generated files, including .config
#
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py
index 212bd0a854..45ec105887 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -12,6 +12,7 @@
import os
import sys
import getopt
+import logging
# pip install pyelftools
from elftools.elf.elffile import ELFFile
@@ -89,13 +90,17 @@ def append_conf_section(file, cnt, dtname, segments):
file.write('\t\tconfig_%d {\n' % cnt)
file.write('\t\t\tdescription = "%s";\n' % dtname)
file.write('\t\t\tfirmware = "atf_1";\n')
- file.write('\t\t\tloadables = "uboot",')
+ file.write('\t\t\tloadables = "uboot"')
+ if segments != 0:
+ file.write(',')
for i in range(1, segments):
file.write('"atf_%d"' % (i))
if i != (segments - 1):
file.write(',')
else:
file.write(';\n')
+ if segments == 0:
+ file.write(';\n')
file.write('\t\t\tfdt = "fdt_1";\n')
file.write('\t\t};\n')
file.write('\n')
@@ -171,8 +176,18 @@ def generate_atf_binary(bl31_file_name):
def main():
uboot_elf = "./u-boot"
- bl31_elf = "./bl31.elf"
fit_its = sys.stdout
+ if "BL31" in os.environ:
+ bl31_elf=os.getenv("BL31");
+ elif os.path.isfile("./bl31.elf"):
+ bl31_elf = "./bl31.elf"
+ else:
+ os.system("echo 'int main(){}' > bl31.c")
+ os.system("${CROSS_COMPILE}gcc -c bl31.c -o bl31.elf")
+ bl31_elf = "./bl31.elf"
+ logging.basicConfig(format='%(levelname)s:%(message)s', level=logging.DEBUG)
+ logging.warning(' BL31 file bl31.elf NOT found, resulting binary is non-functional')
+ logging.warning(' Please read Building section in doc/README.rockchip')
opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h")
for opt, val in opts:
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 264f7e4994..5680c075fa 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -149,8 +149,8 @@ For example:
=> make realclean
=> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
- (copy bl31.elf into U-Boot root dir)
- => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot
+ (export bl31.elf)
+ => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
- Compile PMU M0 firmware
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related
* [PATCH v4.1 4/6] rockchip: rk3399: Get bl31.elf via BL31
From: Jagan Teki @ 2019-06-20 10:59 UTC (permalink / raw)
To: Simon Glass, Philipp Tomsich, Kever Yang,
u-boot-0aAXYlwwYIKGBzrmiIFOJg
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/, Jagan Teki
Right now rockchip platform need to copy bl31.elf into u-boot
source directory to make use of building u-boot.itb.
So, add environment variable BL31 like Allwinner SoC so-that the
bl31.elf would available via BL31.
If the builds are not exporting BL31 env, the make_fit_atf.py
explicitly create dummy bl31.elf in u-boot root directory to
satisfy travis builds and it will show the warning on console as
WARNING: BL31 file bl31.elf NOT found, resulting binary is non-functional
WARNING: Please read Building section in doc/README.rockchip
Note, that the dummy bl31 files were created during not exporting
BL31 case would be removed via clean target in Makefile.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
Changes for v4.1:
- Check BL31 env first instead of bl31.elf PWD.
Makefile | 2 +-
arch/arm/mach-rockchip/make_fit_atf.py | 19 +++++++++++++++++--
doc/README.rockchip | 4 ++--
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/Makefile b/Makefile
index a503ab9fc1..3ede10ff68 100644
--- a/Makefile
+++ b/Makefile
@@ -1848,7 +1848,7 @@ clean: $(clean-dirs)
-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f \
- bl31_*.bin image.map
+ bl31.c bl31.elf bl31_*.bin image.map
# mrproper - Delete all generated files, including .config
#
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py
index 212bd0a854..45ec105887 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -12,6 +12,7 @@
import os
import sys
import getopt
+import logging
# pip install pyelftools
from elftools.elf.elffile import ELFFile
@@ -89,13 +90,17 @@ def append_conf_section(file, cnt, dtname, segments):
file.write('\t\tconfig_%d {\n' % cnt)
file.write('\t\t\tdescription = "%s";\n' % dtname)
file.write('\t\t\tfirmware = "atf_1";\n')
- file.write('\t\t\tloadables = "uboot",')
+ file.write('\t\t\tloadables = "uboot"')
+ if segments != 0:
+ file.write(',')
for i in range(1, segments):
file.write('"atf_%d"' % (i))
if i != (segments - 1):
file.write(',')
else:
file.write(';\n')
+ if segments == 0:
+ file.write(';\n')
file.write('\t\t\tfdt = "fdt_1";\n')
file.write('\t\t};\n')
file.write('\n')
@@ -171,8 +176,18 @@ def generate_atf_binary(bl31_file_name):
def main():
uboot_elf = "./u-boot"
- bl31_elf = "./bl31.elf"
fit_its = sys.stdout
+ if "BL31" in os.environ:
+ bl31_elf=os.getenv("BL31");
+ elif os.path.isfile("./bl31.elf"):
+ bl31_elf = "./bl31.elf"
+ else:
+ os.system("echo 'int main(){}' > bl31.c")
+ os.system("${CROSS_COMPILE}gcc -c bl31.c -o bl31.elf")
+ bl31_elf = "./bl31.elf"
+ logging.basicConfig(format='%(levelname)s:%(message)s', level=logging.DEBUG)
+ logging.warning(' BL31 file bl31.elf NOT found, resulting binary is non-functional')
+ logging.warning(' Please read Building section in doc/README.rockchip')
opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h")
for opt, val in opts:
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 264f7e4994..5680c075fa 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -149,8 +149,8 @@ For example:
=> make realclean
=> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
- (copy bl31.elf into U-Boot root dir)
- => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot
+ (export bl31.elf)
+ => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
- Compile PMU M0 firmware
--
2.18.0.321.gffc6fa0e3
^ permalink raw reply related
* Re: [PATCH 5/5] media: venus: Update core selection
From: amasule @ 2019-06-20 10:59 UTC (permalink / raw)
To: Stanimir Varbanov; +Cc: linux-media, linux-kernel, linux-arm-msm, vgarodia
In-Reply-To: <8f2e1cf4-9d9c-088b-740f-d8bf1c9028df@linaro.org>
On 2019-06-17 14:37, Stanimir Varbanov wrote:
> Hi Aniket,
>
> On 6/11/19 9:05 AM, Aniket Masule wrote:
>> Present core assignment is static. Introduced load balancing
>> across the cores. Load on earch core is calculated and core
>> with minimum load is assigned to given instance.
>>
>> Signed-off-by: Aniket Masule <amasule@codeaurora.org>
>> ---
>> drivers/media/platform/qcom/venus/helpers.c | 50
>> +++++++++++++++++++++++++----
>> drivers/media/platform/qcom/venus/helpers.h | 2 +-
>> drivers/media/platform/qcom/venus/vdec.c | 5 +--
>> drivers/media/platform/qcom/venus/venc.c | 4 ++-
>> 4 files changed, 51 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/venus/helpers.c
>> b/drivers/media/platform/qcom/venus/helpers.c
>> index edb653e..38d617b 100644
>> --- a/drivers/media/platform/qcom/venus/helpers.c
>> +++ b/drivers/media/platform/qcom/venus/helpers.c
>> @@ -497,6 +497,16 @@ static int load_scale_clocks(struct venus_inst
>> *inst)
>> return scale_clocks_vpu4(inst);
>> }
>>
>> +int set_core_usage(struct venus_inst *inst, u32 usage)
>> +{
>> + const u32 ptype = HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE;
>> + struct hfi_videocores_usage_type cu;
>> +
>> + cu.video_core_enable_mask = usage;
>> +
>> + return hfi_session_set_property(inst, ptype, &cu);
>> +}
>> +
>> static void fill_buffer_desc(const struct venus_buffer *buf,
>> struct hfi_buffer_desc *bd, bool response)
>> {
>> @@ -800,19 +810,47 @@ int venus_helper_set_work_mode(struct venus_inst
>> *inst, u32 mode)
>> }
>> EXPORT_SYMBOL_GPL(venus_helper_set_work_mode);
>>
>> -int venus_helper_set_core_usage(struct venus_inst *inst, u32 usage)
>> +int venus_helper_decide_core(struct venus_inst *inst, u32 cores_max)
>
> I think venus_helper_set_core is better?
>
Sure Stan.
>> {
>> - const u32 ptype = HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE;
>> - struct hfi_videocores_usage_type cu;
>> + struct venus_core *core = inst->core;
>> + u32 min_core_id = 0, core0_load = 0, core1_load = 0;
>> + unsigned long min_load, max_freq, cur_inst_load;
>> + int ret;
>>
>> if (!IS_V4(inst->core))
>> return 0;
>>
>> - cu.video_core_enable_mask = usage;
>> + core0_load = load_per_core(core, VIDC_CORE_ID_1);
>> + core1_load = load_per_core(core, VIDC_CORE_ID_2);
>>
>> - return hfi_session_set_property(inst, ptype, &cu);
>> + min_core_id = core0_load < core1_load ? VIDC_CORE_ID_1 :
>> VIDC_CORE_ID_2;
>> + min_load = min(core0_load, core1_load);
>> +
>> + if (cores_max < VIDC_CORE_ID_1) {
>> + min_core_id = VIDC_CORE_ID_1;
>> + min_load = core0_load;
>> + }
>
> could you please move that fragment just after IS_V4 check and return
> an
> error if cores_max < VIDC_CORE_ID_1.
>
Instead of "if cores_max < VIDC_CORE_ID_1", we need to check if
cores_max < VIDC_CORE_ID_2
and set core the single core as minimum load core. I can't return after
this check immidiately
as it needs to be checked whether load can be accommodated or not.
>> +
>> + cur_inst_load = load_per_instance(inst) *
>> + inst->clk_data.codec_data->vpp_cycles;
>> + max_freq = core->res->freq_tbl[0].freq;
>> +
>> + if ((cur_inst_load + min_load) > max_freq) {
>> + dev_warn(core->dev, "HW is overloaded, needed: %lu max: %lu\n",
>> + cur_inst_load, max_freq);
>> + return -EINVAL;
>> + }
>> +
>> + ret = set_core_usage(inst, min_core_id);
>> +
>> + if (ret)
>> + return ret;
>> +
>> + inst->clk_data.core_id = min_core_id;
>> +
>> + return 0;
>> }
>> -EXPORT_SYMBOL_GPL(venus_helper_set_core_usage);
>> +EXPORT_SYMBOL_GPL(venus_helper_decide_core);
>>
>> int venus_helper_init_codec_data(struct venus_inst *inst)
>> {
>> diff --git a/drivers/media/platform/qcom/venus/helpers.h
>> b/drivers/media/platform/qcom/venus/helpers.h
>> index f9360a8..c41ceb3 100644
>> --- a/drivers/media/platform/qcom/venus/helpers.h
>> +++ b/drivers/media/platform/qcom/venus/helpers.h
>> @@ -42,7 +42,7 @@ int venus_helper_set_output_resolution(struct
>> venus_inst *inst,
>> u32 buftype);
>> int venus_helper_set_work_mode(struct venus_inst *inst, u32 mode);
>> int venus_helper_init_codec_data(struct venus_inst *inst);
>> -int venus_helper_set_core_usage(struct venus_inst *inst, u32 usage);
>> +int venus_helper_decide_core(struct venus_inst *inst, u32 cores_max);
>> int venus_helper_set_num_bufs(struct venus_inst *inst, unsigned int
>> input_bufs,
>> unsigned int output_bufs,
>> unsigned int output2_bufs);
>> diff --git a/drivers/media/platform/qcom/venus/vdec.c
>> b/drivers/media/platform/qcom/venus/vdec.c
>> index 51795fd..9f988ba 100644
>> --- a/drivers/media/platform/qcom/venus/vdec.c
>> +++ b/drivers/media/platform/qcom/venus/vdec.c
>> @@ -544,14 +544,15 @@ static int vdec_output_conf(struct venus_inst
>> *inst)
>> u32 height = inst->out_height;
>> u32 out_fmt, out2_fmt;
>> bool ubwc = false;
>> - u32 ptype;
>> + u32 ptype, cores_max;
>> int ret;
>>
>> ret = venus_helper_set_work_mode(inst, VIDC_WORK_MODE_2);
>> if (ret)
>> return ret;
>>
>> - ret = venus_helper_set_core_usage(inst, VIDC_CORE_ID_1);
>> + cores_max = core_num_max(inst);
>
> please move core_max calculation in the venus_helper_decide_core() here
> and below.
>
Yes Stan.
>> + ret = venus_helper_decide_core(inst, cores_max);
>> if (ret)
>> return ret;
>>
>> diff --git a/drivers/media/platform/qcom/venus/venc.c
>> b/drivers/media/platform/qcom/venus/venc.c
>> index 792cdce..ed39efd 100644
>> --- a/drivers/media/platform/qcom/venus/venc.c
>> +++ b/drivers/media/platform/qcom/venus/venc.c
>> @@ -654,13 +654,15 @@ static int venc_set_properties(struct venus_inst
>> *inst)
>> struct hfi_quantization quant;
>> struct hfi_quantization_range quant_range;
>> u32 ptype, rate_control, bitrate, profile = 0, level = 0;
>> + u32 cores_max;
>> int ret;
>>
>> ret = venus_helper_set_work_mode(inst, VIDC_WORK_MODE_2);
>> if (ret)
>> return ret;
>>
>> - ret = venus_helper_set_core_usage(inst, VIDC_CORE_ID_2);
>> + cores_max = core_num_max(inst);
>> + ret = venus_helper_decide_core(inst, cores_max);
>> if (ret)
>> return ret;
>>
>>
^ permalink raw reply
* Re: [Qemu-devel] [PATCH v1 02/17] tests/vm: avoid image presence check and removal
From: Philippe Mathieu-Daudé @ 2019-06-20 10:29 UTC (permalink / raw)
To: Alex Bennée, qemu-devel; +Cc: Fam Zheng, Cleber Rosa
In-Reply-To: <20190619194021.8240-3-alex.bennee@linaro.org>
On 6/19/19 9:40 PM, Alex Bennée wrote:
> From: Cleber Rosa <crosa@redhat.com>
>
> Python's os.rename() will silently replace an existing file,
> so there's no need for the extra check and removal.
>
> Reference: https://docs.python.org/3/library/os.html#os.rename
> Signed-off-by: Cleber Rosa <crosa@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Message-Id: <20190613130718.3763-3-crosa@redhat.com>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> tests/vm/centos | 2 --
> tests/vm/freebsd | 2 --
> tests/vm/netbsd | 2 --
> tests/vm/openbsd | 2 --
> tests/vm/ubuntu.i386 | 2 --
> 5 files changed, 10 deletions(-)
>
> diff --git a/tests/vm/centos b/tests/vm/centos
> index b00b46a8dc..53976f1c4c 100755
> --- a/tests/vm/centos
> +++ b/tests/vm/centos
> @@ -77,8 +77,6 @@ class CentosVM(basevm.BaseVM):
> self.ssh_root_check("systemctl enable docker")
> self.ssh_root("poweroff")
> self.wait()
> - if os.path.exists(img):
> - os.remove(img)
> os.rename(img_tmp, img)
> return 0
>
> diff --git a/tests/vm/freebsd b/tests/vm/freebsd
> index 5575c23a6f..091be1a065 100755
> --- a/tests/vm/freebsd
> +++ b/tests/vm/freebsd
> @@ -36,8 +36,6 @@ class FreeBSDVM(basevm.BaseVM):
> sys.stderr.write("Extracting the image...\n")
> subprocess.check_call(["ln", "-f", cimg, img_tmp_xz])
> subprocess.check_call(["xz", "--keep", "-dvf", img_tmp_xz])
> - if os.path.exists(img):
> - os.remove(img)
> os.rename(img_tmp, img)
>
> if __name__ == "__main__":
> diff --git a/tests/vm/netbsd b/tests/vm/netbsd
> index d0508f4465..ee9eaeab50 100755
> --- a/tests/vm/netbsd
> +++ b/tests/vm/netbsd
> @@ -36,8 +36,6 @@ class NetBSDVM(basevm.BaseVM):
> sys.stderr.write("Extracting the image...\n")
> subprocess.check_call(["ln", "-f", cimg, img_tmp_xz])
> subprocess.check_call(["xz", "--keep", "-dvf", img_tmp_xz])
> - if os.path.exists(img):
> - os.remove(img)
> os.rename(img_tmp, img)
>
> if __name__ == "__main__":
> diff --git a/tests/vm/openbsd b/tests/vm/openbsd
> index 87ec982489..28c7d25e29 100755
> --- a/tests/vm/openbsd
> +++ b/tests/vm/openbsd
> @@ -38,8 +38,6 @@ class OpenBSDVM(basevm.BaseVM):
> sys.stderr.write("Extracting the image...\n")
> subprocess.check_call(["ln", "-f", cimg, img_tmp_xz])
> subprocess.check_call(["xz", "--keep", "-dvf", img_tmp_xz])
> - if os.path.exists(img):
> - os.remove(img)
> os.rename(img_tmp, img)
>
> if __name__ == "__main__":
> diff --git a/tests/vm/ubuntu.i386 b/tests/vm/ubuntu.i386
> index a22d137e76..12867b193f 100755
> --- a/tests/vm/ubuntu.i386
> +++ b/tests/vm/ubuntu.i386
> @@ -80,8 +80,6 @@ class UbuntuX86VM(basevm.BaseVM):
> self.ssh_root_check("apt-get install -y libfdt-dev flex bison")
> self.ssh_root("poweroff")
> self.wait()
> - if os.path.exists(img):
> - os.remove(img)
> os.rename(img_tmp, img)
> return 0
>
>
^ permalink raw reply
* Re: [PATCH V10 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
From: Thierry Reding @ 2019-06-20 10:55 UTC (permalink / raw)
To: Vidya Sagar
Cc: mark.rutland, devicetree, lorenzo.pieralisi, mperttunen,
mmaddireddy, linux-pci, catalin.marinas, will.deacon,
linux-kernel, kthota, kishon, linux-tegra, robh+dt,
gustavo.pimentel, jingoohan1, bhelgaas, digetx, jonathanh,
linux-arm-kernel, sagar.tv
In-Reply-To: <20190612095339.20118-12-vidyas@nvidia.com>
[-- Attachment #1.1: Type: text/plain, Size: 17022 bytes --]
On Wed, Jun 12, 2019 at 03:23:35PM +0530, Vidya Sagar wrote:
> Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
> The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
> grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
> and NVIDIA High Speed (NVHS-8 P2Us) respectively.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> Changes since [v9]:
> * None
>
> Changes since [v8]:
> * None
>
> Changes since [v7]:
> * Replaced 'core_apb' with 'apb' in reset names
> * Used macros instead of hardcoded numbers in 'interrupt-map' property
> * Aligned 'ranges' entries
>
> Changes since [v6]:
> * Removed properties "nvidia,disable-aspm-states" & "nvidia,controller-id".
> * Modified property "nvidia,bpmp" to include controller-id as well.
>
> Changes since [v5]:
> * Changes 'p2u@xxxxxxxx' to 'phy@xxxxxxxx'
> * Arranged all PCIe nodes in the order of their addresses
>
> Changes since [v4]:
> * None
>
> Changes since [v3]:
> * None
>
> Changes since [v2]:
> * Included 'hsio' or 'nvhs' in P2U node's label names to reflect which brick
> they belong to
> * Removed leading zeros in unit address
>
> Changes since [v1]:
> * Flattened all P2U nodes by removing 'hsio-p2u' and 'nvhs-p2u' super nodes
> * Changed P2U nodes compatible string from 'nvidia,tegra194-phy-p2u' to 'nvidia,tegra194-p2u'
> * Changed reg-name from 'base' to 'ctl'
> * Updated all PCIe nodes according to the changes made to DT documentation file
>
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 437 +++++++++++++++++++++++
> 1 file changed, 437 insertions(+)
Applied to for-5.3/arm64/dt, thanks.
I did end up sorting the new nodes differently so that they are ordered
according to the general rules (sort by unit-address, then
alphabetically). That's slightly complicated by the fact that the PCI
controllers have registers that seem to be right in the middle of the
host1x aperture, so I had to bend the rules a little.
Thierry
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index c77ca211fa8f..feba034f26f0 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -884,6 +884,166 @@
> nvidia,interface = <3>;
> };
> };
> +
> + p2u_hsio_0: phy@3e10000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e10000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_1: phy@3e20000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e20000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_2: phy@3e30000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e30000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_3: phy@3e40000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e40000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_4: phy@3e50000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e50000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_5: phy@3e60000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e60000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_6: phy@3e70000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e70000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_7: phy@3e80000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e80000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_8: phy@3e90000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e90000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_9: phy@3ea0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ea0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_0: phy@3eb0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03eb0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_1: phy@3ec0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ec0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_2: phy@3ed0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ed0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_3: phy@3ee0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ee0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_4: phy@3ef0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ef0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_5: phy@3f00000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f00000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_6: phy@3f10000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f10000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_7: phy@3f20000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f20000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_10: phy@3f30000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f30000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_11: phy@3f40000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f40000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> };
>
> sysram@40000000 {
> @@ -1054,4 +1214,281 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> };
> +
> + pcie@14100000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
> + reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <1>;
> + num-viewport = <8>;
> + linux,pci-domain = <1>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 1>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
> + 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
> + };
> +
> + pcie@14120000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
> + reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <1>;
> + num-viewport = <8>;
> + linux,pci-domain = <2>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 2>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
> + 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
> + };
> +
> + pcie@14140000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
> + reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <1>;
> + num-viewport = <8>;
> + linux,pci-domain = <3>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 3>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
> + 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
> + };
> +
> + pcie@14160000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
> + reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + num-viewport = <8>;
> + linux,pci-domain = <4>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 4>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
> + 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> + };
> +
> + pcie@14180000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
> + reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <8>;
> + num-viewport = <8>;
> + linux,pci-domain = <0>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 0>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
> + 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> + };
> +
> + pcie@141a0000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
> + reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <8>;
> + num-viewport = <8>;
> + linux,pci-domain = <5>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
> + <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
> + clock-names = "core", "core_m";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
> + <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + nvidia,bpmp = <&bpmp 5>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
> + 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> + };
> };
> --
> 2.17.1
>
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^ permalink raw reply
* Re: [PATCH V10 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
From: Thierry Reding @ 2019-06-20 10:55 UTC (permalink / raw)
To: Vidya Sagar
Cc: lorenzo.pieralisi, bhelgaas, robh+dt, mark.rutland, jonathanh,
kishon, catalin.marinas, will.deacon, jingoohan1,
gustavo.pimentel, digetx, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-arm-kernel, kthota, mmaddireddy,
sagar.tv
In-Reply-To: <20190612095339.20118-12-vidyas@nvidia.com>
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On Wed, Jun 12, 2019 at 03:23:35PM +0530, Vidya Sagar wrote:
> Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
> The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
> grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
> and NVIDIA High Speed (NVHS-8 P2Us) respectively.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> Changes since [v9]:
> * None
>
> Changes since [v8]:
> * None
>
> Changes since [v7]:
> * Replaced 'core_apb' with 'apb' in reset names
> * Used macros instead of hardcoded numbers in 'interrupt-map' property
> * Aligned 'ranges' entries
>
> Changes since [v6]:
> * Removed properties "nvidia,disable-aspm-states" & "nvidia,controller-id".
> * Modified property "nvidia,bpmp" to include controller-id as well.
>
> Changes since [v5]:
> * Changes 'p2u@xxxxxxxx' to 'phy@xxxxxxxx'
> * Arranged all PCIe nodes in the order of their addresses
>
> Changes since [v4]:
> * None
>
> Changes since [v3]:
> * None
>
> Changes since [v2]:
> * Included 'hsio' or 'nvhs' in P2U node's label names to reflect which brick
> they belong to
> * Removed leading zeros in unit address
>
> Changes since [v1]:
> * Flattened all P2U nodes by removing 'hsio-p2u' and 'nvhs-p2u' super nodes
> * Changed P2U nodes compatible string from 'nvidia,tegra194-phy-p2u' to 'nvidia,tegra194-p2u'
> * Changed reg-name from 'base' to 'ctl'
> * Updated all PCIe nodes according to the changes made to DT documentation file
>
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 437 +++++++++++++++++++++++
> 1 file changed, 437 insertions(+)
Applied to for-5.3/arm64/dt, thanks.
I did end up sorting the new nodes differently so that they are ordered
according to the general rules (sort by unit-address, then
alphabetically). That's slightly complicated by the fact that the PCI
controllers have registers that seem to be right in the middle of the
host1x aperture, so I had to bend the rules a little.
Thierry
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index c77ca211fa8f..feba034f26f0 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -884,6 +884,166 @@
> nvidia,interface = <3>;
> };
> };
> +
> + p2u_hsio_0: phy@3e10000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e10000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_1: phy@3e20000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e20000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_2: phy@3e30000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e30000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_3: phy@3e40000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e40000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_4: phy@3e50000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e50000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_5: phy@3e60000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e60000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_6: phy@3e70000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e70000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_7: phy@3e80000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e80000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_8: phy@3e90000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03e90000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_9: phy@3ea0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ea0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_0: phy@3eb0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03eb0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_1: phy@3ec0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ec0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_2: phy@3ed0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ed0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_3: phy@3ee0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ee0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_4: phy@3ef0000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03ef0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_5: phy@3f00000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f00000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_6: phy@3f10000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f10000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_7: phy@3f20000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f20000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_10: phy@3f30000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f30000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_11: phy@3f40000 {
> + compatible = "nvidia,tegra194-p2u";
> + reg = <0x03f40000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> };
>
> sysram@40000000 {
> @@ -1054,4 +1214,281 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> };
> +
> + pcie@14100000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
> + reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <1>;
> + num-viewport = <8>;
> + linux,pci-domain = <1>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 1>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
> + 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
> + };
> +
> + pcie@14120000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
> + reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <1>;
> + num-viewport = <8>;
> + linux,pci-domain = <2>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 2>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
> + 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
> + };
> +
> + pcie@14140000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
> + reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <1>;
> + num-viewport = <8>;
> + linux,pci-domain = <3>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 3>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
> + 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
> + };
> +
> + pcie@14160000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
> + reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + num-viewport = <8>;
> + linux,pci-domain = <4>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 4>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
> + 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> + };
> +
> + pcie@14180000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
> + reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <8>;
> + num-viewport = <8>;
> + linux,pci-domain = <0>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 0>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
> + 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> + };
> +
> + pcie@141a0000 {
> + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
> + reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
> + 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
> + 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> + 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <8>;
> + num-viewport = <8>;
> + linux,pci-domain = <5>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
> + <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
> + clock-names = "core", "core_m";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
> + <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + nvidia,bpmp = <&bpmp 5>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
> + 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> + };
> };
> --
> 2.17.1
>
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^ permalink raw reply
* Re: [PATCH v2 4/5] mm: introduce MADV_PAGEOUT
From: Michal Hocko @ 2019-06-20 10:55 UTC (permalink / raw)
To: Minchan Kim
Cc: Andrew Morton, linux-mm, LKML, linux-api, Johannes Weiner,
Tim Murray, Joel Fernandes, Suren Baghdasaryan, Daniel Colascione,
Shakeel Butt, Sonny Rao, Brian Geffon, jannh, oleg, christian,
oleksandr, hdanton, lizeb
In-Reply-To: <20190620103215.GF105727@google.com>
On Thu 20-06-19 19:32:15, Minchan Kim wrote:
[...]
> Then, okay, I will add can_do_mincore similar check for the MADV_PAGEOUT syscall
> if others have different ideas.
Great that we are on the same page. We can simply skip over those pages.
--
Michal Hocko
SUSE Labs
^ permalink raw reply
* [igt-dev] ✓ Fi.CI.BAT: success for Chamelium port mapping auto-discovery (rev2)
From: Patchwork @ 2019-06-20 10:53 UTC (permalink / raw)
To: Simon Ser; +Cc: igt-dev
In-Reply-To: <20190619155518.25129-1-simon.ser@intel.com>
== Series Details ==
Series: Chamelium port mapping auto-discovery (rev2)
URL : https://patchwork.freedesktop.org/series/62393/
State : success
== Summary ==
CI Bug Log - changes from IGT_5062 -> IGTPW_3180
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/62393/revisions/2/mbox/
Known issues
------------
Here are the changes found in IGTPW_3180 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5062/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_basic@basic-all:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5062/fi-icl-u2/igt@gem_exec_basic@basic-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/fi-icl-u2/igt@gem_exec_basic@basic-all.html
- fi-cml-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#110566])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5062/fi-cml-u2/igt@gem_exec_basic@basic-all.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/fi-cml-u2/igt@gem_exec_basic@basic-all.html
* igt@gem_exec_suspend@basic-s3:
- fi-cfl-8109u: [PASS][7] -> [FAIL][8] ([fdo#103375])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5062/fi-cfl-8109u/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/fi-cfl-8109u/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [PASS][9] -> [DMESG-FAIL][10] ([fdo#110235])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5062/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
#### Possible fixes ####
* igt@gem_ctx_switch@basic-default:
- fi-icl-guc: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5062/fi-icl-guc/igt@gem_ctx_switch@basic-default.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/fi-icl-guc/igt@gem_ctx_switch@basic-default.html
* igt@gem_mmap_gtt@basic-read-no-prefault:
- fi-glk-dsi: [INCOMPLETE][13] ([fdo#103359] / [k.org#198133]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5062/fi-glk-dsi/igt@gem_mmap_gtt@basic-read-no-prefault.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/fi-glk-dsi/igt@gem_mmap_gtt@basic-read-no-prefault.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [DMESG-WARN][15] ([fdo#106387]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5062/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (51 -> 45)
------------------------------
Additional (2): fi-byt-j1900 fi-bxt-j4205
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* IGT: IGT_5062 -> IGTPW_3180
CI_DRM_6312: 034e3ac6a2d180d188da927388b60c7e62c5655b @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3180: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/
IGT_5062: 771cd83f4ae4299cebfb09b89b4d044835c6ea80 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3180/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply
* Re: [Qemu-devel] [PATCH 0/2] target/mips: Improve MSA tests
From: Aleksandar Rikalo @ 2019-06-20 10:28 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel@nongnu.org; +Cc: Aleksandar Markovic
In-Reply-To: <1560969232-23283-1-git-send-email-aleksandar.markovic@rt-rk.com>
> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
> Sent: Wednesday, June 19, 2019 8:33 PM
> To: qemu-devel@nongnu.org
> Cc: Aleksandar Markovic; Aleksandar Rikalo
> Subject: [PATCH 0/2] target/mips: Improve MSA tests
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> This series contains various improvements and additions of MSA ASE
> TCG tests.
>
> Aleksandar Markovic (2):
> tests/tcg: target/mips: Introduce isa/ase name and group name
> tests/tcg: target/mips: Amend tests for MSA pack instructions
>
> tests/tcg/mips/include/test_utils_128.h | 17 +++---
> tests/tcg/mips/include/test_utils_64.h | 9 ++-
> tests/tcg/mips/include/wrappers_msa.h | 24 ++++++++
> .../mips/user/ase/msa/bit-count/test_msa_nloc_b.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_nloc_d.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_nloc_h.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_nloc_w.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_nlzc_b.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_nlzc_d.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_nlzc_h.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_nlzc_w.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_pcnt_b.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_pcnt_d.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_pcnt_h.c | 9 ++-
> .../mips/user/ase/msa/bit-count/test_msa_pcnt_w.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bclr_b.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bclr_d.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bclr_h.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bclr_w.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bneg_b.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bneg_d.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bneg_h.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bneg_w.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bset_b.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bset_d.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bset_h.c | 9 ++-
> .../mips/user/ase/msa/bit-set/test_msa_bset_w.c | 9 ++-
> .../user/ase/msa/fixed-multiply/test_msa_mul_q_h.c | 9 ++-
> .../user/ase/msa/fixed-multiply/test_msa_mul_q_w.c | 9 ++-
> .../ase/msa/fixed-multiply/test_msa_mulr_q_h.c | 9 ++-
> .../ase/msa/fixed-multiply/test_msa_mulr_q_w.c | 9 ++-
> .../user/ase/msa/float-max-min/test_msa_fmax_a_d.c | 9 ++-
> .../user/ase/msa/float-max-min/test_msa_fmax_a_w.c | 9 ++-
> .../user/ase/msa/float-max-min/test_msa_fmax_d.c | 9 ++-
> .../user/ase/msa/float-max-min/test_msa_fmax_w.c | 9 ++-
> .../user/ase/msa/float-max-min/test_msa_fmin_a_d.c | 9 ++-
> .../user/ase/msa/float-max-min/test_msa_fmin_a_w.c | 9 ++-
> .../user/ase/msa/float-max-min/test_msa_fmin_d.c | 9 ++-
> .../user/ase/msa/float-max-min/test_msa_fmin_w.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_add_a_b.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_add_a_d.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_add_a_h.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_add_a_w.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_a_b.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_a_d.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_a_h.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_a_w.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_s_b.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_s_d.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_s_h.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_s_w.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_u_b.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_u_d.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_u_h.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_adds_u_w.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_addv_b.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_addv_d.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_addv_h.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_addv_w.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_hadd_s_d.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_hadd_s_h.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_hadd_s_w.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_hadd_u_d.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_hadd_u_h.c | 9 ++-
> .../mips/user/ase/msa/int-add/test_msa_hadd_u_w.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_ave_s_b.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_ave_s_d.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_ave_s_h.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_ave_s_w.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_ave_u_b.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_ave_u_d.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_ave_u_h.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_ave_u_w.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_aver_s_b.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_aver_s_d.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_aver_s_h.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_aver_s_w.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_aver_u_b.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_aver_u_d.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_aver_u_h.c | 9 ++-
> .../user/ase/msa/int-average/test_msa_aver_u_w.c | 9 ++-
> .../mips/user/ase/msa/int-compare/test_msa_ceq_b.c | 9 ++-
> .../mips/user/ase/msa/int-compare/test_msa_ceq_d.c | 9 ++-
> .../mips/user/ase/msa/int-compare/test_msa_ceq_h.c | 9 ++-
> .../mips/user/ase/msa/int-compare/test_msa_ceq_w.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_cle_s_b.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_cle_s_d.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_cle_s_h.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_cle_s_w.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_cle_u_b.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_cle_u_d.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_cle_u_h.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_cle_u_w.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_clt_s_b.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_clt_s_d.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_clt_s_h.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_clt_s_w.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_clt_u_b.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_clt_u_d.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_clt_u_h.c | 9 ++-
> .../user/ase/msa/int-compare/test_msa_clt_u_w.c | 9 ++-
> .../user/ase/msa/int-divide/test_msa_div_s_b.c | 9 ++-
> .../user/ase/msa/int-divide/test_msa_div_s_d.c | 9 ++-
> .../user/ase/msa/int-divide/test_msa_div_s_h.c | 9 ++-
> .../user/ase/msa/int-divide/test_msa_div_s_w.c | 9 ++-
> .../user/ase/msa/int-divide/test_msa_div_u_b.c | 9 ++-
> .../user/ase/msa/int-divide/test_msa_div_u_d.c | 9 ++-
> .../user/ase/msa/int-divide/test_msa_div_u_h.c | 9 ++-
> .../user/ase/msa/int-divide/test_msa_div_u_w.c | 9 ++-
> .../ase/msa/int-dot-product/test_msa_dotp_s_d.c | 9 ++-
> .../ase/msa/int-dot-product/test_msa_dotp_s_h.c | 9 ++-
> .../ase/msa/int-dot-product/test_msa_dotp_s_w.c | 9 ++-
> .../ase/msa/int-dot-product/test_msa_dotp_u_d.c | 9 ++-
> .../ase/msa/int-dot-product/test_msa_dotp_u_h.c | 9 ++-
> .../ase/msa/int-dot-product/test_msa_dotp_u_w.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_a_b.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_a_d.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_a_h.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_a_w.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_s_b.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_s_d.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_s_h.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_s_w.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_u_b.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_u_d.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_u_h.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_max_u_w.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_a_b.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_a_d.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_a_h.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_a_w.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_s_b.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_s_d.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_s_h.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_s_w.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_u_b.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_u_d.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_u_h.c | 9 ++-
> .../user/ase/msa/int-max-min/test_msa_min_u_w.c | 9 ++-
> .../user/ase/msa/int-modulo/test_msa_mod_s_b.c | 9 ++-
> .../user/ase/msa/int-modulo/test_msa_mod_s_d.c | 9 ++-
> .../user/ase/msa/int-modulo/test_msa_mod_s_h.c | 9 ++-
> .../user/ase/msa/int-modulo/test_msa_mod_s_w.c | 9 ++-
> .../user/ase/msa/int-modulo/test_msa_mod_u_b.c | 9 ++-
> .../user/ase/msa/int-modulo/test_msa_mod_u_d.c | 9 ++-
> .../user/ase/msa/int-modulo/test_msa_mod_u_h.c | 9 ++-
> .../user/ase/msa/int-modulo/test_msa_mod_u_w.c | 9 ++-
> .../user/ase/msa/int-multiply/test_msa_mulv_b.c | 9 ++-
> .../user/ase/msa/int-multiply/test_msa_mulv_d.c | 9 ++-
> .../user/ase/msa/int-multiply/test_msa_mulv_h.c | 9 ++-
> .../user/ase/msa/int-multiply/test_msa_mulv_w.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_asub_s_b.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_asub_s_d.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_asub_s_h.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_asub_s_w.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_asub_u_b.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_asub_u_d.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_asub_u_h.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_asub_u_w.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_hsub_s_d.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_hsub_s_h.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_hsub_s_w.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_hsub_u_d.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_hsub_u_h.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_hsub_u_w.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subs_s_b.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subs_s_d.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subs_s_h.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subs_s_w.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subs_u_b.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subs_u_d.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subs_u_h.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subs_u_w.c | 9 ++-
> .../ase/msa/int-subtract/test_msa_subsus_u_b.c | 9 ++-
> .../ase/msa/int-subtract/test_msa_subsus_u_d.c | 9 ++-
> .../ase/msa/int-subtract/test_msa_subsus_u_h.c | 9 ++-
> .../ase/msa/int-subtract/test_msa_subsus_u_w.c | 9 ++-
> .../ase/msa/int-subtract/test_msa_subsuu_s_b.c | 9 ++-
> .../ase/msa/int-subtract/test_msa_subsuu_s_d.c | 9 ++-
> .../ase/msa/int-subtract/test_msa_subsuu_s_h.c | 9 ++-
> .../ase/msa/int-subtract/test_msa_subsuu_s_w.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subv_b.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subv_d.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subv_h.c | 9 ++-
> .../user/ase/msa/int-subtract/test_msa_subv_w.c | 9 ++-
> .../user/ase/msa/interleave/test_msa_ilvev_b.c | 9 ++-
> .../user/ase/msa/interleave/test_msa_ilvev_d.c | 9 ++-
> .../user/ase/msa/interleave/test_msa_ilvev_h.c | 9 ++-
> .../user/ase/msa/interleave/test_msa_ilvev_w.c | 9 ++-
> .../mips/user/ase/msa/interleave/test_msa_ilvl_b.c | 9 ++-
> .../mips/user/ase/msa/interleave/test_msa_ilvl_d.c | 9 ++-
> .../mips/user/ase/msa/interleave/test_msa_ilvl_h.c | 9 ++-
> .../mips/user/ase/msa/interleave/test_msa_ilvl_w.c | 9 ++-
> .../user/ase/msa/interleave/test_msa_ilvod_b.c | 9 ++-
> .../user/ase/msa/interleave/test_msa_ilvod_d.c | 9 ++-
> .../user/ase/msa/interleave/test_msa_ilvod_h.c | 9 ++-
> .../user/ase/msa/interleave/test_msa_ilvod_w.c | 9 ++-
> .../mips/user/ase/msa/interleave/test_msa_ilvr_b.c | 9 ++-
> .../mips/user/ase/msa/interleave/test_msa_ilvr_d.c | 9 ++-
> .../mips/user/ase/msa/interleave/test_msa_ilvr_h.c | 9 ++-
> .../mips/user/ase/msa/interleave/test_msa_ilvr_w.c | 9 ++-
> tests/tcg/mips/user/ase/msa/logic/test_msa_and_v.c | 9 ++-
> tests/tcg/mips/user/ase/msa/logic/test_msa_nor_v.c | 9 ++-
> tests/tcg/mips/user/ase/msa/logic/test_msa_or_v.c | 9 ++-
> tests/tcg/mips/user/ase/msa/logic/test_msa_xor_v.c | 9 ++-
> .../tcg/mips/user/ase/msa/pack/test_msa_pckev_b.c | 67 ++++++++++++++++++++--
> .../tcg/mips/user/ase/msa/pack/test_msa_pckev_d.c | 67 ++++++++++++++++++++--
> .../tcg/mips/user/ase/msa/pack/test_msa_pckev_h.c | 67 ++++++++++++++++++++--
> .../tcg/mips/user/ase/msa/pack/test_msa_pckev_w.c | 67 ++++++++++++++++++++--
> .../tcg/mips/user/ase/msa/pack/test_msa_pckod_b.c | 67 ++++++++++++++++++++--
> .../tcg/mips/user/ase/msa/pack/test_msa_pckod_d.c | 67 ++++++++++++++++++++--
> .../tcg/mips/user/ase/msa/pack/test_msa_pckod_h.c | 67 ++++++++++++++++++++--
> .../tcg/mips/user/ase/msa/pack/test_msa_pckod_w.c | 67 ++++++++++++++++++++--
> tests/tcg/mips/user/ase/msa/pack/test_msa_vshf_b.c | 67 ++++++++++++++++++++--
> tests/tcg/mips/user/ase/msa/pack/test_msa_vshf_d.c | 67 ++++++++++++++++++++--
> tests/tcg/mips/user/ase/msa/pack/test_msa_vshf_h.c | 67 ++++++++++++++++++++--
> tests/tcg/mips/user/ase/msa/pack/test_msa_vshf_w.c | 67 ++++++++++++++++++++--
> tests/tcg/mips/user/ase/msa/shift/test_msa_sll_b.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_sll_d.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_sll_h.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_sll_w.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_sra_b.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_sra_d.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_sra_h.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_sra_w.c | 9 ++-
> .../tcg/mips/user/ase/msa/shift/test_msa_srar_b.c | 9 ++-
> .../tcg/mips/user/ase/msa/shift/test_msa_srar_d.c | 9 ++-
> .../tcg/mips/user/ase/msa/shift/test_msa_srar_h.c | 9 ++-
> .../tcg/mips/user/ase/msa/shift/test_msa_srar_w.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_srl_b.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_srl_d.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_srl_h.c | 9 ++-
> tests/tcg/mips/user/ase/msa/shift/test_msa_srl_w.c | 9 ++-
> .../tcg/mips/user/ase/msa/shift/test_msa_srlr_b.c | 9 ++-
> .../tcg/mips/user/ase/msa/shift/test_msa_srlr_d.c | 9 ++-
> .../tcg/mips/user/ase/msa/shift/test_msa_srlr_h.c | 9 ++-
> .../tcg/mips/user/ase/msa/shift/test_msa_srlr_w.c | 9 ++-
> .../isa/mips64r6/bit-count/test_mips64r6_clo.c | 4 +-
> .../isa/mips64r6/bit-count/test_mips64r6_clz.c | 4 +-
> .../isa/mips64r6/bit-count/test_mips64r6_dclo.c | 4 +-
> .../isa/mips64r6/bit-count/test_mips64r6_dclz.c | 4 +-
> .../isa/mips64r6/bit-swap/test_mips64r6_bitswap.c | 4 +-
> .../isa/mips64r6/bit-swap/test_mips64r6_dbitswap.c | 4 +-
> .../isa/mips64r6/int-multiply/test_mips64r6_dmuh.c | 4 +-
> .../mips64r6/int-multiply/test_mips64r6_dmuhu.c | 4 +-
> .../isa/mips64r6/int-multiply/test_mips64r6_dmul.c | 4 +-
> .../mips64r6/int-multiply/test_mips64r6_dmulu.c | 4 +-
> .../isa/mips64r6/int-multiply/test_mips64r6_muh.c | 4 +-
> .../isa/mips64r6/int-multiply/test_mips64r6_muhu.c | 4 +-
> .../isa/mips64r6/int-multiply/test_mips64r6_mul.c | 4 +-
> .../isa/mips64r6/int-multiply/test_mips64r6_mulu.c | 4 +-
> .../user/isa/mips64r6/logic/test_mips64r6_and.c | 4 +-
> .../user/isa/mips64r6/logic/test_mips64r6_nor.c | 4 +-
> .../user/isa/mips64r6/logic/test_mips64r6_or.c | 4 +-
> .../user/isa/mips64r6/logic/test_mips64r6_xor.c | 4 +-
> .../user/isa/mips64r6/shift/test_mips64r6_dsllv.c | 4 +-
> .../user/isa/mips64r6/shift/test_mips64r6_dsrav.c | 4 +-
> .../user/isa/mips64r6/shift/test_mips64r6_dsrlv.c | 4 +-
> .../user/isa/mips64r6/shift/test_mips64r6_sllv.c | 4 +-
> .../user/isa/mips64r6/shift/test_mips64r6_srav.c | 4 +-
> .../user/isa/mips64r6/shift/test_mips64r6_srlv.c | 4 +-
> 261 files changed, 2200 insertions(+), 748 deletions(-)
>
> --
> 2.7.4
It would be also nice to add instructions how to build tests for
mips32r5 for example, since this architecture can also support MSA.
For the whole series.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
^ permalink raw reply
* Re: [Qemu-devel] [PATCH 0/4] target/mips: Fix some issues of MSA emulation on big endian hosts
From: Aleksandar Rikalo @ 2019-06-20 10:25 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel@nongnu.org; +Cc: Aleksandar Markovic
In-Reply-To: <1561021082-15383-1-git-send-email-aleksandar.markovic@rt-rk.com>
> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
> Sent: Thursday, June 20, 2019 10:57 AM
> To: qemu-devel@nongnu.org
> Cc: Aleksandar Markovic; Aleksandar Rikalo
> Subject: [PATCH 0/4] target/mips: Fix some issues of MSA emulation on big endian hosts
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Fix some issues of MSA emulation on big endian hosts.
>
> Aleksandar Markovic (4):
> target/mips: Fix emulation of ILVEV.<B|H|W> on big endian host
> target/mips: Fix emulation of ILVOD.<B|H|W> on big endian host
> target/mips: Fix emulation of ILVL.<B|H|W> on big endian host
> target/mips: Fix emulation of ILVR.<B|H|W> on big endian host
>
> target/mips/msa_helper.c | 148 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 148 insertions(+)
>
> --
> 2.7.4
For the whole series.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
^ permalink raw reply
* Re: [PATCH V6 00/27] Enable Tegra PCIe root port features
From: Lorenzo Pieralisi @ 2019-06-20 10:53 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Manikanta Maddireddy, robh+dt, mark.rutland,
jonathanh, vidyas, linux-tegra, linux-pci, devicetree
In-Reply-To: <20190620102552.GB28703@ulmo>
On Thu, Jun 20, 2019 at 12:25:52PM +0200, Thierry Reding wrote:
> On Tue, Jun 18, 2019 at 11:31:39PM +0530, Manikanta Maddireddy wrote:
> > This series of patches adds,
> > - Tegra root port features like Gen2, AER, etc
> > - Power and perf optimizations
> > - Fixes like "power up sequence", "dev_err prints", etc
> >
> > This series of patches are tested on Tegra186 based Jetson-TX2, Tegra210
> > based Jetson-TX1, T124 based Jetson-TK1, Tegra20 and Tegra30 platforms.
> >
> > Changes from V5 to V6:
> > - Patch [V4, 20/27]: Replaced pcie_pme_disable_msi() with no_msi quirk
> >
> > Changes from V4 to V5:
> > - Patch [V4, 4/28]: Added blank line before block style comment
> > - Patch [V4, 22/28]: "Access endpoint config only if PCIe link is up"
> > patch is dropped
> > - Patch [V4, 27/28]:
> > * Updated reset gpio toggle logic to reflect active low usage
> > * Replaced kasprintf() with devm_kasprintf()
> > * Updated commit message with more information.
> >
> > Changes from V3 to V4:
> > - Patch [V3,27/29] is dropped
> > - Patch [V3,28/29]: devm_gpiod_get_from_of_node() is directly used in
> > pci-tegra driver instead of of_get_pci* wrapper function defined in
> > Patch [V3,27/29].
> >
> > Manikanta Maddireddy (27):
> > soc/tegra: pmc: Export tegra_powergate_power_on()
> > PCI: tegra: Handle failure cases in tegra_pcie_power_on()
> > PCI: tegra: Rearrange Tegra PCIe driver functions
> > PCI: tegra: Mask AFI_INTR in runtime suspend
> > PCI: tegra: Fix PCIe host power up sequence
> > PCI: tegra: Add PCIe Gen2 link speed support
> > PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability
> > PCI: tegra: Program UPHY electrical settings for Tegra210
> > PCI: tegra: Enable opportunistic UpdateFC and ACK
> > PCI: tegra: Disable AFI dynamic clock gating
> > PCI: tegra: Process pending DLL transactions before entering L1 or L2
> > PCI: tegra: Enable PCIe xclk clock clamping
> > PCI: tegra: Increase the deskew retry time
> > PCI: tegra: Add SW fixup for RAW violations
> > PCI: tegra: Update flow control timer frequency in Tegra210
> > PCI: tegra: Set target speed as Gen1 before starting LTSSM
> > PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal
> > PCI: tegra: Program AFI_CACHE* registers only for Tegra20
> > PCI: tegra: Change PRSNT_SENSE IRQ log to debug
> > PCI: tegra: Disable MSI for Tegra PCIe root port
> > PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct
> > dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop
> > arm64: tegra: Add PEX DPD states as pinctrl properties
> > PCI: tegra: Put PEX CLK & BIAS pads in DPD mode
> > PCI: Add DT binding for "reset-gpios" property
> > PCI: tegra: Add support for GPIO based PERST#
> > PCI: tegra: Change link retry log level to debug
>
> Hi Lorenzo, Bjorn,
>
> There's a build-time dependency from the PCI patches on patch 1 of this
> series. I've already Acked that, so I think you should take it through
> the PCI tree along with the rest of the series.
>
> The only patch that I picked up is the DT change in patch 23, which is
> decoupled from the others via DT, though the data that it adds to DT
> will be used in patch 24.
>
> Does that sound good to you?
Yes, I will drop patch 20 too as requested. Is there a merge ordering
dependency between patch 23 and 24 ? If yes we should let Bjorn know
or you drop patch 23 and I will merge it via PCI, let us know.
Lorenzo
> Thierry
>
> >
> > .../bindings/pci/nvidia,tegra20-pcie.txt | 8 +
> > Documentation/devicetree/bindings/pci/pci.txt | 3 +
> > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +
> > drivers/pci/controller/pci-tegra.c | 578 +++++++++++++++---
> > drivers/pci/quirks.c | 39 ++
> > drivers/soc/tegra/pmc.c | 1 +
> > 6 files changed, 568 insertions(+), 80 deletions(-)
> >
> > --
> > 2.17.1
> >
^ permalink raw reply
* Re: [igt-dev] [PATCH i-g-t 5/5] docs: Embed subtest descriptions in the documentation
From: Arkadiusz Hiler @ 2019-06-20 10:52 UTC (permalink / raw)
To: igt-dev, Daniel Vetter
In-Reply-To: <20190620082018.GC22949@platvala-desk.ger.corp.intel.com>
On Thu, Jun 20, 2019 at 11:20:18AM +0300, Petri Latvala wrote:
> On Mon, Jun 17, 2019 at 01:54:43PM +0300, Arkadiusz Hiler wrote:
> > This rewrites generate_description_xml in Python, so that we generate
> > properly escaped XML. The switch also makes the code more manageable.
> >
> > Changes in the generated docbook:
> >
> > 1. subtests are not simply listed anymore, they are now another (sub)section
> >
> > 2. subtests are now linkable,
> > e.g. docs/igt-kms-tests.html#kms_hdmi_inject@inject-4k
> >
> > 3. subtest's section now includes output of --describe
> >
> > Python is required already by gtk-doc and we are not using anything
> > other than the standard library.
>
> Python yes, but what about python3? My Debian installation is ancient
> even on Debian standards and gtk-doc-tools depends on python2. I'm too
> lazy to check if the version used by gitlab-CI depends on python3, so
> asking instead: Do you have a fork in gitlab for this? :P
It works on Fedora:
% head -n 1 $(which gtkdoc-mkhtml)
#!/usr/bin/python3
https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/.gitlab-ci.yml#L174
But for explicitness I can squash in:
diff --git a/docs/reference/igt-gpu-tools/meson.build b/docs/reference/igt-gpu-tools/meson.build
index e2bdc495..b3a4c0bd 100644
--- a/docs/reference/igt-gpu-tools/meson.build
+++ b/docs/reference/igt-gpu-tools/meson.build
@@ -45,6 +45,7 @@ test_groups = [
'vgem',
]
+find_program('python3') # required by doc generators
gen_description = find_program('generate_description_xml.py')
gen_programs = find_program('generate_programs_xml.sh')
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related
* Re: use exact allocation for dma coherent memory
From: Christoph Hellwig @ 2019-06-20 10:51 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Maxime Ripard, Joonas Lahtinen, dri-devel, linux-mm,
Christoph Hellwig, devel, linux-s390, linux-rdma, David Airlie,
Potnuri Bharat Teja, Dan Carpenter, linux-media,
Intel Linux Wireless, intel-gfx, Maarten Lankhorst, Jani Nikula,
Ian Abbott, Rodrigo Vivi, Sean Paul, moderated list:ARM PORT,
netdev, linux-wireless, linux-kernel, H Hartley Sweeten, iommu,
Daniel Vetter
In-Reply-To: <20190619162903.GF9360@ziepe.ca>
On Wed, Jun 19, 2019 at 01:29:03PM -0300, Jason Gunthorpe wrote:
> > Yes. This will blow up badly on many platforms, as sq->queue
> > might be vmapped, ioremapped, come from a pool without page backing.
>
> Gah, this addr gets fed into io_remap_pfn_range/remap_pfn_range too..
>
> Potnuri, you should fix this..
>
> You probably need to use dma_mmap_from_dev_coherent() in the mmap ?
The function to use is dma_mmap_coherent, dma_mmap_from_dev_coherent is
just an internal helper.
That beiŋ said the drivers/infiniband code has a lot of
*remap_pfn_range, and a lot of them look like they might be for
DMA memory.
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: use exact allocation for dma coherent memory
From: Christoph Hellwig @ 2019-06-20 10:51 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Maxime Ripard, Joonas Lahtinen, dri-devel, linux-mm,
Christoph Hellwig, devel, linux-s390, linux-rdma, David Airlie,
Potnuri Bharat Teja, Dan Carpenter, linux-media,
Intel Linux Wireless, intel-gfx, Maarten Lankhorst, Jani Nikula,
Ian Abbott, Rodrigo Vivi, Sean Paul, moderated list:ARM PORT,
netdev, linux-wireless, linux-kernel, H Hartley Sweeten, iommu,
Daniel Vetter
In-Reply-To: <20190619162903.GF9360@ziepe.ca>
On Wed, Jun 19, 2019 at 01:29:03PM -0300, Jason Gunthorpe wrote:
> > Yes. This will blow up badly on many platforms, as sq->queue
> > might be vmapped, ioremapped, come from a pool without page backing.
>
> Gah, this addr gets fed into io_remap_pfn_range/remap_pfn_range too..
>
> Potnuri, you should fix this..
>
> You probably need to use dma_mmap_from_dev_coherent() in the mmap ?
The function to use is dma_mmap_coherent, dma_mmap_from_dev_coherent is
just an internal helper.
That beiŋ said the drivers/infiniband code has a lot of
*remap_pfn_range, and a lot of them look like they might be for
DMA memory.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* Re: use exact allocation for dma coherent memory
From: Christoph Hellwig @ 2019-06-20 10:51 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Christoph Hellwig, Potnuri Bharat Teja, Dan Carpenter,
Maarten Lankhorst, Maxime Ripard, Sean Paul, David Airlie,
Daniel Vetter, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ian Abbott, H Hartley Sweeten, devel, linux-s390,
Intel Linux Wireless, linux-rdma, netdev, intel-gfx,
linux-wireless, linux-kernel, dri-devel, linux-mm, iommu,
moderated list:ARM PORT, linux-media
In-Reply-To: <20190619162903.GF9360@ziepe.ca>
On Wed, Jun 19, 2019 at 01:29:03PM -0300, Jason Gunthorpe wrote:
> > Yes. This will blow up badly on many platforms, as sq->queue
> > might be vmapped, ioremapped, come from a pool without page backing.
>
> Gah, this addr gets fed into io_remap_pfn_range/remap_pfn_range too..
>
> Potnuri, you should fix this..
>
> You probably need to use dma_mmap_from_dev_coherent() in the mmap ?
The function to use is dma_mmap_coherent, dma_mmap_from_dev_coherent is
just an internal helper.
That beiŋ said the drivers/infiniband code has a lot of
*remap_pfn_range, and a lot of them look like they might be for
DMA memory.
^ permalink raw reply
* Re: use exact allocation for dma coherent memory
From: Christoph Hellwig @ 2019-06-20 10:51 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Christoph Hellwig, Potnuri Bharat Teja, Dan Carpenter,
Maarten Lankhorst, Maxime Ripard, Sean Paul, David Airlie,
Daniel Vetter, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
Ian Abbott, H Hartley Sweeten, devel, linux-s390,
Intel Linux Wireless, linux-rdma, netdev, intel-gfx,
linux-wireless, linux-kernel
In-Reply-To: <20190619162903.GF9360@ziepe.ca>
On Wed, Jun 19, 2019 at 01:29:03PM -0300, Jason Gunthorpe wrote:
> > Yes. This will blow up badly on many platforms, as sq->queue
> > might be vmapped, ioremapped, come from a pool without page backing.
>
> Gah, this addr gets fed into io_remap_pfn_range/remap_pfn_range too..
>
> Potnuri, you should fix this..
>
> You probably need to use dma_mmap_from_dev_coherent() in the mmap ?
The function to use is dma_mmap_coherent, dma_mmap_from_dev_coherent is
just an internal helper.
That beiŋ said the drivers/infiniband code has a lot of
*remap_pfn_range, and a lot of them look like they might be for
DMA memory.
^ permalink raw reply
* Re: [PATCH] genirq: Remove warning on preemptible in prepare_percpu_nmi()
From: Lecopzer Chen @ 2019-06-20 10:50 UTC (permalink / raw)
To: julien.thierry, marc.zyngier
Cc: peterz, tglx, yj.chiang, linux-arm-kernel, linux-kernel
In-Reply-To: <20190620091233.22731-1-lecopzer.chen@mediatek.com>
Thanks a lot for reply!!
I just misunderstood how a PPI is registered and thought
I have a chance to eliminate the code.
This patch seems nonsense now, please ignore it.
Sorry to disturb you guys.
Thanks,
Lecopzer
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v2 6/6] drivers/base/memory.c: Get rid of find_memory_block_hinted()
From: David Hildenbrand @ 2019-06-20 10:35 UTC (permalink / raw)
To: linux-kernel
Cc: Stephen Rothwell, Pavel Tatashin, David Hildenbrand,
mike.travis@hpe.com, Greg Kroah-Hartman, Rafael J. Wysocki,
linux-mm, linux-acpi, Dan Williams, linuxppc-dev, Andrew Morton
In-Reply-To: <20190620103520.23481-1-david@redhat.com>
No longer needed, let's remove it. Also, drop the "hint" parameter
completely from "find_memory_block_by_id", as nobody needs it anymore.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Pavel Tatashin <pasha.tatashin@soleen.com>
Cc: "mike.travis@hpe.com" <mike.travis@hpe.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
drivers/base/memory.c | 32 ++++++++++----------------------
include/linux/memory.h | 2 --
2 files changed, 10 insertions(+), 24 deletions(-)
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 0204384b4d1d..fefb64d3588e 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -592,26 +592,12 @@ int __weak arch_get_memory_phys_device(unsigned long start_pfn)
* A reference for the returned object is held and the reference for the
* hinted object is released.
*/
-static struct memory_block *find_memory_block_by_id(unsigned long block_id,
- struct memory_block *hint)
+static struct memory_block *find_memory_block_by_id(unsigned long block_id)
{
- struct device *hintdev = hint ? &hint->dev : NULL;
struct device *dev;
- dev = subsys_find_device_by_id(&memory_subsys, block_id, hintdev);
- if (hint)
- put_device(&hint->dev);
- if (!dev)
- return NULL;
- return to_memory_block(dev);
-}
-
-struct memory_block *find_memory_block_hinted(struct mem_section *section,
- struct memory_block *hint)
-{
- unsigned long block_id = base_memory_block_id(__section_nr(section));
-
- return find_memory_block_by_id(block_id, hint);
+ dev = subsys_find_device_by_id(&memory_subsys, block_id, NULL);
+ return dev ? to_memory_block(dev) : NULL;
}
/*
@@ -624,7 +610,9 @@ struct memory_block *find_memory_block_hinted(struct mem_section *section,
*/
struct memory_block *find_memory_block(struct mem_section *section)
{
- return find_memory_block_hinted(section, NULL);
+ unsigned long block_id = base_memory_block_id(__section_nr(section));
+
+ return find_memory_block_by_id(block_id);
}
static struct attribute *memory_memblk_attrs[] = {
@@ -675,7 +663,7 @@ static int init_memory_block(struct memory_block **memory,
unsigned long start_pfn;
int ret = 0;
- mem = find_memory_block_by_id(block_id, NULL);
+ mem = find_memory_block_by_id(block_id);
if (mem) {
put_device(&mem->dev);
return -EEXIST;
@@ -755,7 +743,7 @@ int create_memory_block_devices(unsigned long start, unsigned long size)
end_block_id = block_id;
for (block_id = start_block_id; block_id != end_block_id;
block_id++) {
- mem = find_memory_block_by_id(block_id, NULL);
+ mem = find_memory_block_by_id(block_id);
mem->section_count = 0;
unregister_memory(mem);
}
@@ -782,7 +770,7 @@ void remove_memory_block_devices(unsigned long start, unsigned long size)
mutex_lock(&mem_sysfs_mutex);
for (block_id = start_block_id; block_id != end_block_id; block_id++) {
- mem = find_memory_block_by_id(block_id, NULL);
+ mem = find_memory_block_by_id(block_id);
if (WARN_ON_ONCE(!mem))
continue;
mem->section_count = 0;
@@ -882,7 +870,7 @@ int walk_memory_blocks(unsigned long start, unsigned long size,
int ret = 0;
for (block_id = start_block_id; block_id <= end_block_id; block_id++) {
- mem = find_memory_block_by_id(block_id, NULL);
+ mem = find_memory_block_by_id(block_id);
if (!mem)
continue;
diff --git a/include/linux/memory.h b/include/linux/memory.h
index b3b388775a30..02e633f3ede0 100644
--- a/include/linux/memory.h
+++ b/include/linux/memory.h
@@ -116,8 +116,6 @@ void remove_memory_block_devices(unsigned long start, unsigned long size);
extern int memory_dev_init(void);
extern int memory_notify(unsigned long val, void *v);
extern int memory_isolate_notify(unsigned long val, void *v);
-extern struct memory_block *find_memory_block_hinted(struct mem_section *,
- struct memory_block *);
extern struct memory_block *find_memory_block(struct mem_section *);
typedef int (*walk_memory_blocks_func_t)(struct memory_block *, void *);
extern int walk_memory_blocks(unsigned long start, unsigned long size,
--
2.21.0
^ permalink raw reply related
* Re: [PATCH v3 0/7] Hexdump Enhancements
From: Jani Nikula @ 2019-06-20 10:50 UTC (permalink / raw)
To: Joe Perches, Alastair D'Silva
Cc: Joonas Lahtinen, Rodrigo Vivi, David Airlie, Daniel Vetter,
Dan Carpenter, Karsten Keil, Jassi Brar, Tom Lendacky,
David S. Miller, Jose Abreu, Kalle Valo, Stanislaw Gruszka,
Benson Leung, Enric Balletbo i Serra, James E.J. Bottomley,
Martin K. Petersen, Greg Kroah-Hartman, Alexander Viro, Petr
In-Reply-To: <fcf57339aea60fb1744cea2a2593656c728c4ec4.camel@perches.com>
On Wed, 19 Jun 2019, Joe Perches <joe@perches.com> wrote:
> On Thu, 2019-06-20 at 11:14 +1000, Alastair D'Silva wrote:
>> On Wed, 2019-06-19 at 17:35 -0700, Joe Perches wrote:
>> > On Thu, 2019-06-20 at 09:15 +1000, Alastair D'Silva wrote:
>> > > On Wed, 2019-06-19 at 09:31 -0700, Joe Perches wrote:
>> > > > On Mon, 2019-06-17 at 12:04 +1000, Alastair D'Silva wrote:
>> > > > > From: Alastair D'Silva <alastair@d-silva.org>
>> > > > >
>> > > > > Apologies for the large CC list, it's a heads up for those
>> > > > > responsible
>> > > > > for subsystems where a prototype change in generic code causes
>> > > > > a
>> > > > > change
>> > > > > in those subsystems.
>> > > > >
>> > > > > This series enhances hexdump.
>> > > >
>> > > > Still not a fan of these patches.
>> > >
>> > > I'm afraid there's not too much action I can take on that, I'm
>> > > happy to
>> > > address specific issues though.
>> > >
>> > > > > These improve the readability of the dumped data in certain
>> > > > > situations
>> > > > > (eg. wide terminals are available, many lines of empty bytes
>> > > > > exist,
>> > > > > etc).
>> >
>> > I think it's generally overkill for the desired uses.
>>
>> I understand where you're coming from, however, these patches make it a
>> lot easier to work with large chucks of binary data. I think it makes
>> more sense to have these patches upstream, even though committed code
>> may not necessarily have all the features enabled, as it means that
>> devs won't have to apply out-of-tree patches during development to make
>> larger dumps manageable.
>>
>> > > > Changing hexdump's last argument from bool to int is odd.
>> > > >
>> > >
>> > > Think of it as replacing a single boolean with many booleans.
>> >
>> > I understand it. It's odd.
>> >
>> > I would rather not have a mixture of true, false, and apparently
>> > random collections of bitfields like 0xd or 0b1011 or their
>> > equivalent or'd defines.
>> >
>>
>> Where's the mixture? What would you propose instead?
>
> create a hex_dump_to_buffer_ext with a new argument
> and a new static inline for the old hex_dump_to_buffer
> without modifying the argument list that calls
> hex_dump_to_buffer with whatever added argument content
> you need.
>
> Something like:
>
> static inline
> int hex_dump_to_buffer(const void *buf, size_t len, int rowsize,
> int groupsize, char *linebuf, size_t linebuflen,
> bool ascii)
> {
> return hex_dump_to_buffer_ext(buf, len, rowsize, groupsize,
> linebuf, linebuflen, ascii, 0);
> }
>
> and remove EXPORT_SYMBOL(hex_dump_to_buffer)
If you decide to do something like this, I'd actually suggest you drop
the bool ascii parameter from hex_dump_to_buffer() altogether, and
replace the callers that do require ascii with
hex_dump_to_buffer_ext(..., HEXDUMP_ASCII). Even if that also requires
touching all callers.
But no strong opinions, really.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply
* Re: [PATCH v3 0/7] Hexdump Enhancements
From: Jani Nikula @ 2019-06-20 10:50 UTC (permalink / raw)
To: Joe Perches, Alastair D'Silva
Cc: Joonas Lahtinen, Rodrigo Vivi, David Airlie, Daniel Vetter,
Dan Carpenter, Karsten Keil, Jassi Brar, Tom Lendacky,
David S. Miller, Jose Abreu, Kalle Valo, Stanislaw Gruszka,
Benson Leung, Enric Balletbo i Serra, James E.J. Bottomley,
Martin K. Petersen, Greg Kroah-Hartman, Alexander Viro, Petr
In-Reply-To: <fcf57339aea60fb1744cea2a2593656c728c4ec4.camel@perches.com>
On Wed, 19 Jun 2019, Joe Perches <joe@perches.com> wrote:
> On Thu, 2019-06-20 at 11:14 +1000, Alastair D'Silva wrote:
>> On Wed, 2019-06-19 at 17:35 -0700, Joe Perches wrote:
>> > On Thu, 2019-06-20 at 09:15 +1000, Alastair D'Silva wrote:
>> > > On Wed, 2019-06-19 at 09:31 -0700, Joe Perches wrote:
>> > > > On Mon, 2019-06-17 at 12:04 +1000, Alastair D'Silva wrote:
>> > > > > From: Alastair D'Silva <alastair@d-silva.org>
>> > > > >
>> > > > > Apologies for the large CC list, it's a heads up for those
>> > > > > responsible
>> > > > > for subsystems where a prototype change in generic code causes
>> > > > > a
>> > > > > change
>> > > > > in those subsystems.
>> > > > >
>> > > > > This series enhances hexdump.
>> > > >
>> > > > Still not a fan of these patches.
>> > >
>> > > I'm afraid there's not too much action I can take on that, I'm
>> > > happy to
>> > > address specific issues though.
>> > >
>> > > > > These improve the readability of the dumped data in certain
>> > > > > situations
>> > > > > (eg. wide terminals are available, many lines of empty bytes
>> > > > > exist,
>> > > > > etc).
>> >
>> > I think it's generally overkill for the desired uses.
>>
>> I understand where you're coming from, however, these patches make it a
>> lot easier to work with large chucks of binary data. I think it makes
>> more sense to have these patches upstream, even though committed code
>> may not necessarily have all the features enabled, as it means that
>> devs won't have to apply out-of-tree patches during development to make
>> larger dumps manageable.
>>
>> > > > Changing hexdump's last argument from bool to int is odd.
>> > > >
>> > >
>> > > Think of it as replacing a single boolean with many booleans.
>> >
>> > I understand it. It's odd.
>> >
>> > I would rather not have a mixture of true, false, and apparently
>> > random collections of bitfields like 0xd or 0b1011 or their
>> > equivalent or'd defines.
>> >
>>
>> Where's the mixture? What would you propose instead?
>
> create a hex_dump_to_buffer_ext with a new argument
> and a new static inline for the old hex_dump_to_buffer
> without modifying the argument list that calls
> hex_dump_to_buffer with whatever added argument content
> you need.
>
> Something like:
>
> static inline
> int hex_dump_to_buffer(const void *buf, size_t len, int rowsize,
> int groupsize, char *linebuf, size_t linebuflen,
> bool ascii)
> {
> return hex_dump_to_buffer_ext(buf, len, rowsize, groupsize,
> linebuf, linebuflen, ascii, 0);
> }
>
> and remove EXPORT_SYMBOL(hex_dump_to_buffer)
If you decide to do something like this, I'd actually suggest you drop
the bool ascii parameter from hex_dump_to_buffer() altogether, and
replace the callers that do require ascii with
hex_dump_to_buffer_ext(..., HEXDUMP_ASCII). Even if that also requires
touching all callers.
But no strong opinions, really.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply
* Re: [PATCH] genirq: Remove warning on preemptible in prepare_percpu_nmi()
From: Lecopzer Chen @ 2019-06-20 10:50 UTC (permalink / raw)
To: julien.thierry, marc.zyngier
Cc: linux-arm-kernel, tglx, peterz, yj.chiang, linux-kernel
In-Reply-To: <20190620091233.22731-1-lecopzer.chen@mediatek.com>
Thanks a lot for reply!!
I just misunderstood how a PPI is registered and thought
I have a chance to eliminate the code.
This patch seems nonsense now, please ignore it.
Sorry to disturb you guys.
Thanks,
Lecopzer
^ permalink raw reply
* Re: [igt-dev] [PATCH i-g-t v2] Add Arm drivers as supported drivers by igt.
From: Petri Latvala @ 2019-06-20 10:50 UTC (permalink / raw)
To: Liviu Dudau; +Cc: IGT GPU Tool
In-Reply-To: <20190620092842.GE17204@e110455-lin.cambridge.arm.com>
On Thu, Jun 20, 2019 at 10:28:42AM +0100, Liviu Dudau wrote:
> On Thu, Jun 20, 2019 at 11:00:24AM +0300, Petri Latvala wrote:
> > On Wed, Jun 19, 2019 at 04:13:58PM +0100, Liviu Dudau wrote:
> > > Add the drivers maintained by Arm developers to the igt.
> > >
> > > v2: Order the modules array entries alphabetically, as per
> > > Petri Latvala's suggestion.
> > >
> > > Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
> > > ---
> > > lib/drmtest.c | 3 +++
> > > lib/drmtest.h | 4 ++++
> > > 2 files changed, 7 insertions(+)
> > >
> > > diff --git a/lib/drmtest.c b/lib/drmtest.c
> > > index 25f203530..17bb87d1f 100644
> > > --- a/lib/drmtest.c
> > > +++ b/lib/drmtest.c
> > > @@ -205,7 +205,10 @@ static const struct module {
> > > void (*modprobe)(const char *name);
> > > } modules[] = {
> > > { DRIVER_AMDGPU, "amdgpu" },
> > > + { DRIVER_HDLCD, "hdlcd" },
> > > { DRIVER_INTEL, "i915", modprobe_i915 },
> > > + { DRIVER_KOMEDA, "komeda" },
> > > + { DRIVER_MALIDP, "mali_dp" },
> >
>
> Hi Petri,
>
> >
> > Should this be "mali-dp" instead?
> >
>
> insmod/modprobe places some equivalence between dashes and underscores. The
> platform driver structure in the kernel is called "mali-dp", but the module
> is called "mali_dp" (confusing, I know, but at least that is what lsmod shows
> after inserting "mali-dp" module).
>
> Not sure what the correct answer is here, I thought we're using module names.
It's both :P
The string is compared to the driver_name field (or what was the name)
to see if the device is DRIVER_MALIDP, and if the function pointer is
not set, the string is also used for modprobe().
So the string should be the device's driver_name, and the function
pointer set to a function that loads the .ko if the module name is
different.
--
Petri Latvala
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply
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