* Re: [PATCH] arm64: dts: qcom: qcs404-evb: fix vdd_apc supply
From: Niklas Cassel @ 2019-06-20 13:50 UTC (permalink / raw)
To: Jorge Ramirez-Ortiz
Cc: agross, david.brown, robh+dt, mark.rutland, bjorn.andersson,
linux-arm-msm, devicetree, linux-kernel, jeffrey.l.hugo
In-Reply-To: <20190619181653.29407-1-jorge.ramirez-ortiz@linaro.org>
On Wed, Jun 19, 2019 at 08:16:53PM +0200, Jorge Ramirez-Ortiz wrote:
> The invalid definition in the supply causes the Qualcomm's EVB-1000
> and EVB-4000 not to boot.
>
> Fix the boot issue by correctly defining the supply: vdd_s3 (namely
> "vdd_apc") is actually connected to vph_pwr.
>
> Reported-by: Niklas Cassel <niklas.cassel@linaro.org>
> Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> index b6092a742675..11c0a7137823 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> @@ -65,7 +65,7 @@
> };
>
> &pms405_spmi_regulators {
> - vdd_s3-supply = <&pms405_s3>;
> + vdd_s3-supply = <&vph_pwr>;
>
> pms405_s3: s3 {
> regulator-always-on;
> --
> 2.21.0
>
Tested-by: Niklas Cassel <niklas.cassel@linaro.org>
^ permalink raw reply
* Re: [PATCH V3 0/3] mmc: mmci: add busy detect for stm32 sdmmc variant
From: Ulf Hansson @ 2019-06-20 13:50 UTC (permalink / raw)
To: Ludovic BARRE
Cc: Rob Herring, Srinivas Kandagatla, Maxime Coquelin,
Alexandre Torgue, Linux ARM, Linux Kernel Mailing List, DTML,
linux-mmc@vger.kernel.org, linux-stm32
In-Reply-To: <CAPDyKFrULRk=cHzVodU9aa6LDX9ip-VPHNwG7QXhmNZrMpPjGw@mail.gmail.com>
Hi Ludovic,
On Thu, 13 Jun 2019 at 15:13, Ulf Hansson <ulf.hansson@linaro.org> wrote:
>
> On Thu, 13 Jun 2019 at 15:02, Ludovic BARRE <ludovic.barre@st.com> wrote:
> >
> > hi Ulf
> >
> > Just a "gentleman ping" about this series.
> > I know you are busy, it's just to be sure you do not forget me :-)
>
> Thanks! I started briefly to review, but got distracted again. I will
> come to it, but it just seems to take more time than it should, my
> apologies.
Alright, so I planned to review this this week - but failed. I have
been overwhelmed with work lately (as usual when vacation is getting
closer).
I need to gently request to come back to this as of week 28, when I
will give this the highest prio. Again apologize for the delays!
Kind regards
Uffe
>
> Br
> Uffe
>
> >
> > Regards
> > Ludo
> >
> > On 6/3/19 5:55 PM, Ludovic Barre wrote:
> > > From: Ludovic Barre <ludovic.barre@st.com>
> > >
> > > This patch series adds busy detect for stm32 sdmmc variant.
> > > Some adaptations are required:
> > > -Clear busy status bit if busy_detect_flag and busy_detect_mask are
> > > different.
> > > -Add hardware busy timeout with MMCIDATATIMER register.
> > >
> > > V3:
> > > -rebase on latest mmc next
> > > -replace re-read by status parameter.
> > >
> > > V2:
> > > -mmci_cmd_irq cleanup in separate patch.
> > > -simplify the busy_detect_flag exclude
> > > -replace sdmmc specific comment in
> > > "mmc: mmci: avoid fake busy polling in mmci_irq"
> > > to focus on common behavior
> > >
> > > Ludovic Barre (3):
> > > mmc: mmci: fix read status for busy detect
> > > mmc: mmci: add hardware busy timeout feature
> > > mmc: mmci: add busy detect for stm32 sdmmc variant
> > >
> > > drivers/mmc/host/mmci.c | 49 +++++++++++++++++++++++++++++++++++++++++--------
> > > drivers/mmc/host/mmci.h | 3 +++
> > > 2 files changed, 44 insertions(+), 8 deletions(-)
> > >
^ permalink raw reply
* [Buildroot] [PATCH v2 1/2] configs/qemu_riscv64_virt: Update to 5.1 kernel
From: Thomas Petazzoni @ 2019-06-20 13:50 UTC (permalink / raw)
To: buildroot
In-Reply-To: <20190619165406.19615-1-alistair.francis@wdc.com>
On Wed, 19 Jun 2019 09:54:05 -0700
Alistair Francis <alistair.francis@wdc.com> wrote:
> Update the 64-bit defconfig to use the latest kernel.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> v2:
> - Keep kernel version hard coded
Applied to master, thanks.
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v7 5/6] drm: sun4i: Add support for enabling DDC I2C bus to sun8i_dw_hdmi glue
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Ondrej Jirman, Mark Rutland, Alexandre Torgue, devicetree,
David Airlie, netdev, linux-kernel, dri-devel, linux-stm32,
Jose Abreu, linux-arm-kernel, Daniel Vetter, Giuseppe Cavallaro,
David S. Miller, Maxime Coquelin
In-Reply-To: <20190620134748.17866-1-megous@megous.com>
From: Ondrej Jirman <megous@megous.com>
Orange Pi 3 board requires enabling a voltage shifting circuit via GPIO
for the DDC bus to be usable.
Add support for hdmi-connector node's optional ddc-en-gpios property to
support this use case.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 54 +++++++++++++++++++++++++--
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +
2 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index 39d8509d96a0..6733bfc9c2d6 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -98,10 +98,34 @@ static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm,
return crtcs;
}
+static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev,
+ struct platform_device **pdev_out)
+{
+ struct platform_device *pdev;
+ struct device_node *remote;
+
+ remote = of_graph_get_remote_node(dev->of_node, 1, -1);
+ if (!remote)
+ return -ENODEV;
+
+ if (!of_device_is_compatible(remote, "hdmi-connector")) {
+ of_node_put(remote);
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(remote);
+ of_node_put(remote);
+ if (!pdev)
+ return -ENODEV;
+
+ *pdev_out = pdev;
+ return 0;
+}
+
static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
void *data)
{
- struct platform_device *pdev = to_platform_device(dev);
+ struct platform_device *pdev = to_platform_device(dev), *connector_pdev;
struct dw_hdmi_plat_data *plat_data;
struct drm_device *drm = data;
struct device_node *phy_node;
@@ -151,16 +175,30 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
return PTR_ERR(hdmi->regulator);
}
+ ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev);
+ if (!ret) {
+ hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev,
+ "ddc-en", GPIOD_OUT_HIGH);
+ platform_device_put(connector_pdev);
+
+ if (IS_ERR(hdmi->ddc_en)) {
+ dev_err(dev, "Couldn't get ddc-en gpio\n");
+ return PTR_ERR(hdmi->ddc_en);
+ }
+ }
+
ret = regulator_enable(hdmi->regulator);
if (ret) {
dev_err(dev, "Failed to enable regulator\n");
- return ret;
+ goto err_unref_ddc_en;
}
+ gpiod_set_value(hdmi->ddc_en, 1);
+
ret = reset_control_deassert(hdmi->rst_ctrl);
if (ret) {
dev_err(dev, "Could not deassert ctrl reset control\n");
- goto err_disable_regulator;
+ goto err_disable_ddc_en;
}
ret = clk_prepare_enable(hdmi->clk_tmds);
@@ -213,8 +251,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
clk_disable_unprepare(hdmi->clk_tmds);
err_assert_ctrl_reset:
reset_control_assert(hdmi->rst_ctrl);
-err_disable_regulator:
+err_disable_ddc_en:
+ gpiod_set_value(hdmi->ddc_en, 0);
regulator_disable(hdmi->regulator);
+err_unref_ddc_en:
+ if (hdmi->ddc_en)
+ gpiod_put(hdmi->ddc_en);
return ret;
}
@@ -228,7 +270,11 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
sun8i_hdmi_phy_remove(hdmi);
clk_disable_unprepare(hdmi->clk_tmds);
reset_control_assert(hdmi->rst_ctrl);
+ gpiod_set_value(hdmi->ddc_en, 0);
regulator_disable(hdmi->regulator);
+
+ if (hdmi->ddc_en)
+ gpiod_put(hdmi->ddc_en);
}
static const struct component_ops sun8i_dw_hdmi_ops = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index 720c5aa8adc1..d707c9171824 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -9,6 +9,7 @@
#include <drm/bridge/dw_hdmi.h>
#include <drm/drm_encoder.h>
#include <linux/clk.h>
+#include <linux/gpio/consumer.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -190,6 +191,7 @@ struct sun8i_dw_hdmi {
struct regulator *regulator;
const struct sun8i_dw_hdmi_quirks *quirks;
struct reset_control *rst_ctrl;
+ struct gpio_desc *ddc_en;
};
static inline struct sun8i_dw_hdmi *
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH] ath11k: fix extended stats update issue
From: Kalle Valo @ 2019-06-20 13:49 UTC (permalink / raw)
To: Karthikeyan Periyasamy; +Cc: ath11k
In-Reply-To: <1560832537-22777-1-git-send-email-periyasa@codeaurora.org>
Karthikeyan Periyasamy <periyasa@codeaurora.org> wrote:
> user not able to see the valid tx stats. htt stats update
> process get failed due to the wrong argument pass to
> ath11k_get_ar_by_pdev_id API. Expected argument is pdev_id not
> the pdev index. so avoid the conversion logic of pdev id to pdev
> index in htt stats update process.
>
> Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org>
This was already applied, right?
error: patch failed: drivers/net/wireless/ath/ath11k/dp_rx.c:1294
error: drivers/net/wireless/ath/ath11k/dp_rx.c: patch does not apply
stg import: Diff does not apply cleanly
Patch set to Rejected.
--
https://patchwork.kernel.org/patch/11000877/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
_______________________________________________
ath11k mailing list
ath11k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath11k
^ permalink raw reply
* [PATCH v7 6/6] arm64: dts: allwinner: orange-pi-3: Enable HDMI output
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Ondrej Jirman, Mark Rutland, Alexandre Torgue, devicetree,
David Airlie, netdev, linux-kernel, dri-devel, linux-stm32,
Jose Abreu, linux-arm-kernel, Daniel Vetter, Giuseppe Cavallaro,
David S. Miller, Maxime Coquelin
In-Reply-To: <20190620134748.17866-1-megous@megous.com>
From: Ondrej Jirman <megous@megous.com>
Orange Pi 3 has a DDC_CEC_EN signal connected to PH2, that enables the DDC
I2C bus voltage shifter. Before EDID can be read, we need to pull PH2 high.
This is realized by the ddc-en-gpios property.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 2c6807b74ff6..01bb1bafe284 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -22,6 +22,18 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -72,6 +84,10 @@
cpu-supply = <®_dcdca>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -91,6 +107,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [tip:x86/urgent] x86/resctrl: Prevent possible overrun during bitmap operations
From: tip-bot for Reinette Chatre @ 2019-06-20 13:49 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, mingo, mingo, fenghua.yu, tony.luck, tglx, bp,
stable, hpa, x86, reinette.chatre
In-Reply-To: <58c9b6081fd9bf599af0dfc01a6fdd335768efef.1560975645.git.reinette.chatre@intel.com>
Commit-ID: 32f010deab575199df4ebe7b6aec20c17bb7eccd
Gitweb: https://git.kernel.org/tip/32f010deab575199df4ebe7b6aec20c17bb7eccd
Author: Reinette Chatre <reinette.chatre@intel.com>
AuthorDate: Wed, 19 Jun 2019 13:27:16 -0700
Committer: Borislav Petkov <bp@suse.de>
CommitDate: Thu, 20 Jun 2019 15:39:19 +0200
x86/resctrl: Prevent possible overrun during bitmap operations
While the DOC at the beginning of lib/bitmap.c explicitly states that
"The number of valid bits in a given bitmap does _not_ need to be an
exact multiple of BITS_PER_LONG.", some of the bitmap operations do
indeed access BITS_PER_LONG portions of the provided bitmap no matter
the size of the provided bitmap.
For example, if find_first_bit() is provided with an 8 bit bitmap the
operation will access BITS_PER_LONG bits from the provided bitmap. While
the operation ensures that these extra bits do not affect the result,
the memory is still accessed.
The capacity bitmasks (CBMs) are typically stored in u32 since they
can never exceed 32 bits. A few instances exist where a bitmap_*
operation is performed on a CBM by simply pointing the bitmap operation
to the stored u32 value.
The consequence of this pattern is that some bitmap_* operations will
access out-of-bounds memory when interacting with the provided CBM.
This same issue has previously been addressed with commit 49e00eee0061
("x86/intel_rdt: Fix out-of-bounds memory access in CBM tests")
but at that time not all instances of the issue were fixed.
Fix this by using an unsigned long to store the capacity bitmask data
that is passed to bitmap functions.
Fixes: e651901187ab ("x86/intel_rdt: Introduce "bit_usage" to display cache allocations details")
Fixes: f4e80d67a527 ("x86/intel_rdt: Resctrl files reflect pseudo-locked information")
Fixes: 95f0b77efa57 ("x86/intel_rdt: Initialize new resource group with sane defaults")
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: stable <stable@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/58c9b6081fd9bf599af0dfc01a6fdd335768efef.1560975645.git.reinette.chatre@intel.com
---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 35 ++++++++++++++++------------------
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 869cbef5da81..f9d8ed6ab03b 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -804,8 +804,12 @@ static int rdt_bit_usage_show(struct kernfs_open_file *of,
struct seq_file *seq, void *v)
{
struct rdt_resource *r = of->kn->parent->priv;
- u32 sw_shareable = 0, hw_shareable = 0;
- u32 exclusive = 0, pseudo_locked = 0;
+ /*
+ * Use unsigned long even though only 32 bits are used to ensure
+ * test_bit() is used safely.
+ */
+ unsigned long sw_shareable = 0, hw_shareable = 0;
+ unsigned long exclusive = 0, pseudo_locked = 0;
struct rdt_domain *dom;
int i, hwb, swb, excl, psl;
enum rdtgrp_mode mode;
@@ -850,10 +854,10 @@ static int rdt_bit_usage_show(struct kernfs_open_file *of,
}
for (i = r->cache.cbm_len - 1; i >= 0; i--) {
pseudo_locked = dom->plr ? dom->plr->cbm : 0;
- hwb = test_bit(i, (unsigned long *)&hw_shareable);
- swb = test_bit(i, (unsigned long *)&sw_shareable);
- excl = test_bit(i, (unsigned long *)&exclusive);
- psl = test_bit(i, (unsigned long *)&pseudo_locked);
+ hwb = test_bit(i, &hw_shareable);
+ swb = test_bit(i, &sw_shareable);
+ excl = test_bit(i, &exclusive);
+ psl = test_bit(i, &pseudo_locked);
if (hwb && swb)
seq_putc(seq, 'X');
else if (hwb && !swb)
@@ -2494,26 +2498,19 @@ out_destroy:
*/
static void cbm_ensure_valid(u32 *_val, struct rdt_resource *r)
{
- /*
- * Convert the u32 _val to an unsigned long required by all the bit
- * operations within this function. No more than 32 bits of this
- * converted value can be accessed because all bit operations are
- * additionally provided with cbm_len that is initialized during
- * hardware enumeration using five bits from the EAX register and
- * thus never can exceed 32 bits.
- */
- unsigned long *val = (unsigned long *)_val;
+ unsigned long val = *_val;
unsigned int cbm_len = r->cache.cbm_len;
unsigned long first_bit, zero_bit;
- if (*val == 0)
+ if (val == 0)
return;
- first_bit = find_first_bit(val, cbm_len);
- zero_bit = find_next_zero_bit(val, cbm_len, first_bit);
+ first_bit = find_first_bit(&val, cbm_len);
+ zero_bit = find_next_zero_bit(&val, cbm_len, first_bit);
/* Clear any remaining bits to ensure contiguous region */
- bitmap_clear(val, zero_bit, cbm_len - zero_bit);
+ bitmap_clear(&val, zero_bit, cbm_len - zero_bit);
+ *_val = (u32)val;
}
/*
^ permalink raw reply related
* Re: [PATCH 1/2] drm/amdgpu: update df_v3_6 for xgmi perfmons
From: Alex Deucher @ 2019-06-20 13:49 UTC (permalink / raw)
To: Kim, Jonathan; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
In-Reply-To: <20190620005313.56371-1-jonathan.kim-5C7GfCeVMHo@public.gmane.org>
On Wed, Jun 19, 2019 at 8:53 PM Kim, Jonathan <Jonathan.Kim@amd.com> wrote:
>
> v4: fixed kzalloc error check and modified df func init to return error code
>
> v3: fixed cleanup by adding fini to free up adev df config counters
>
> v2: simplified by removing xgmi references in function names and moving to
> generic df function names. fixed issue by removing hardcoded cake tx data
> events. streamlined error handling by having df_v3_6_pmc_get_ctrl return
> error code.
>
> add pmu attribute groups and structures for perf events.
> add sysfs to track available df perfmon counters
> fix overflow handling in perfmon counter reads.
>
> Change-Id: I61f731c0066b17834656c746e7efe038c4f62acf
> Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 17 +
> drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 449 ++++++++++++---------------
> drivers/gpu/drm/amd/amdgpu/df_v3_6.h | 19 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +
> 4 files changed, 231 insertions(+), 258 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index d355e9a09ad1..91cfcc7be5c1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -732,6 +732,7 @@ struct amd_powerplay {
> };
>
> #define AMDGPU_RESET_MAGIC_NUM 64
> +#define AMDGPU_MAX_DF_PERFMONS 16
> struct amdgpu_device {
> struct device *dev;
> struct drm_device *ddev;
> @@ -962,6 +963,7 @@ struct amdgpu_device {
> long compute_timeout;
>
> uint64_t unique_id;
> + uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
> };
>
> static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
> @@ -1201,4 +1203,19 @@ static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return
> #endif
>
> #include "amdgpu_object.h"
> +
> +/* used by df_v3_6.c and amdgpu_pmu.c */
> +#define AMDGPU_PMU_ATTR(_name, _object) \
> +static ssize_t \
> +_name##_show(struct device *dev, \
> + struct device_attribute *attr, \
> + char *page) \
> +{ \
> + BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
> + return sprintf(page, _object "\n"); \
> +} \
> + \
> +static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
> +
> #endif
> +
> diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> index 8c09bf994acd..12e3e67013d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> @@ -30,8 +30,104 @@
> static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
> 16, 32, 0, 0, 0, 2, 4, 8};
>
> +/* init df format attrs */
> +AMDGPU_PMU_ATTR(event, "config:0-7");
> +AMDGPU_PMU_ATTR(instance, "config:8-15");
> +AMDGPU_PMU_ATTR(umask, "config:16-23");
> +
> +/* df format attributes */
> +static struct attribute *df_v3_6_format_attrs[] = {
> + &pmu_attr_event.attr,
> + &pmu_attr_instance.attr,
> + &pmu_attr_umask.attr,
> + NULL
> +};
> +
> +/* df format attribute group */
> +static struct attribute_group df_v3_6_format_attr_group = {
> + .name = "format",
> + .attrs = df_v3_6_format_attrs,
> +};
> +
> +/* df event attrs */
> +AMDGPU_PMU_ATTR(cake0_pcsout_txdata,
> + "event=0x7,instance=0x46,umask=0x2");
> +AMDGPU_PMU_ATTR(cake1_pcsout_txdata,
> + "event=0x7,instance=0x47,umask=0x2");
> +AMDGPU_PMU_ATTR(cake0_pcsout_txmeta,
> + "event=0x7,instance=0x46,umask=0x4");
> +AMDGPU_PMU_ATTR(cake1_pcsout_txmeta,
> + "event=0x7,instance=0x47,umask=0x4");
> +AMDGPU_PMU_ATTR(cake0_ftiinstat_reqalloc,
> + "event=0xb,instance=0x46,umask=0x4");
> +AMDGPU_PMU_ATTR(cake1_ftiinstat_reqalloc,
> + "event=0xb,instance=0x47,umask=0x4");
> +AMDGPU_PMU_ATTR(cake0_ftiinstat_rspalloc,
> + "event=0xb,instance=0x46,umask=0x8");
> +AMDGPU_PMU_ATTR(cake1_ftiinstat_rspalloc,
> + "event=0xb,instance=0x47,umask=0x8");
> +
> +/* df event attributes */
> +static struct attribute *df_v3_6_event_attrs[] = {
> + &pmu_attr_cake0_pcsout_txdata.attr,
> + &pmu_attr_cake1_pcsout_txdata.attr,
> + &pmu_attr_cake0_pcsout_txmeta.attr,
> + &pmu_attr_cake1_pcsout_txmeta.attr,
> + &pmu_attr_cake0_ftiinstat_reqalloc.attr,
> + &pmu_attr_cake1_ftiinstat_reqalloc.attr,
> + &pmu_attr_cake0_ftiinstat_rspalloc.attr,
> + &pmu_attr_cake1_ftiinstat_rspalloc.attr,
> + NULL
> +};
> +
> +/* df event attribute group */
> +static struct attribute_group df_v3_6_event_attr_group = {
> + .name = "events",
> + .attrs = df_v3_6_event_attrs
> +};
> +
> +/* df event attr groups */
> +const struct attribute_group *df_v3_6_attr_groups[] = {
> + &df_v3_6_format_attr_group,
> + &df_v3_6_event_attr_group,
> + NULL
> +};
> +
> +/* get the number of df counters available */
> +static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct amdgpu_device *adev;
> + struct drm_device *ddev;
> + int i, count;
> +
> + ddev = dev_get_drvdata(dev);
> + adev = ddev->dev_private;
> + count = 0;
> +
> + for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
> + if (adev->df_perfmon_config_assign_mask[i] == 0)
> + count++;
> + }
> +
> + return snprintf(buf, PAGE_SIZE, "%i\n", count);
> +}
> +
> +/* device attr for available perfmon counters */
> +static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL);
> +
> +/* init perfmons */
> static void df_v3_6_init(struct amdgpu_device *adev)
> {
> + int i, ret;
> +
> + ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail);
> + if (ret)
> + DRM_ERROR("failed to create file for available df counters\n");
> +
> + for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++)
> + adev->df_perfmon_config_assign_mask[i] = 0;
> }
You never addressed my comments about df init from before. df_init
gets called from hw_init, so you shouldn't create files. Move df init
to being called from soc15 sw_init/fini and probably rename the df
callbacks to sw_init and sw_fini so we know not to add hw state to
those functions. As is now, we'll end up needlessly creating and
destorying files on suspend/resume.
Alex
>
> static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
> @@ -105,28 +201,19 @@ static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
> *flags |= AMD_CG_SUPPORT_DF_MGCG;
> }
>
> -/* hold counter assignment per gpu struct */
> -struct df_v3_6_event_mask {
> - struct amdgpu_device gpu;
> - uint64_t config_assign_mask[AMDGPU_DF_MAX_COUNTERS];
> -};
> -
> /* get assigned df perfmon ctr as int */
> -static void df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev,
> - uint64_t config,
> - int *counter)
> +static int df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev,
> + uint64_t config)
> {
> - struct df_v3_6_event_mask *mask;
> int i;
>
> - mask = container_of(adev, struct df_v3_6_event_mask, gpu);
> -
> - for (i = 0; i < AMDGPU_DF_MAX_COUNTERS; i++) {
> - if ((config & 0x0FFFFFFUL) == mask->config_assign_mask[i]) {
> - *counter = i;
> - return;
> - }
> + for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
> + if ((config & 0x0FFFFFFUL) ==
> + adev->df_perfmon_config_assign_mask[i])
> + return i;
> }
> +
> + return -EINVAL;
> }
>
> /* get address based on counter assignment */
> @@ -136,10 +223,7 @@ static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
> uint32_t *lo_base_addr,
> uint32_t *hi_base_addr)
> {
> -
> - int target_cntr = -1;
> -
> - df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
> + int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
>
> if (target_cntr < 0)
> return;
> @@ -177,40 +261,38 @@ static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev,
> }
>
> /* get control counter settings i.e. address and values to set */
> -static void df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
> +static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
> uint64_t config,
> uint32_t *lo_base_addr,
> uint32_t *hi_base_addr,
> uint32_t *lo_val,
> uint32_t *hi_val)
> {
> -
> - uint32_t eventsel, instance, unitmask;
> - uint32_t es_5_0, es_13_0, es_13_6, es_13_12, es_11_8, es_7_0;
> -
> df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr);
>
> - if (lo_val == NULL || hi_val == NULL)
> - return;
> -
> if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
> - DRM_ERROR("DF PMC addressing not retrieved! Lo: %x, Hi: %x",
> + DRM_ERROR("[DF PMC] addressing not retrieved! Lo: %x, Hi: %x",
> *lo_base_addr, *hi_base_addr);
> - return;
> + return -ENXIO;
> + }
> +
> + if (lo_val && hi_val) {
> + uint32_t eventsel, instance, unitmask;
> + uint32_t instance_10, instance_5432, instance_76;
> +
> + eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
> + unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
> + instance = DF_V3_6_GET_INSTANCE(config);
> +
> + instance_10 = instance & 0x3;
> + instance_5432 = (instance >> 2) & 0xf;
> + instance_76 = (instance >> 6) & 0x3;
> +
> + *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel;
> + *hi_val = (instance_76 << 29) | instance_5432;
> }
>
> - eventsel = GET_EVENT(config);
> - instance = GET_INSTANCE(config);
> - unitmask = GET_UNITMASK(config);
> -
> - es_5_0 = eventsel & 0x3FUL;
> - es_13_6 = instance;
> - es_13_0 = (es_13_6 << 6) + es_5_0;
> - es_13_12 = (es_13_0 & 0x03000UL) >> 12;
> - es_11_8 = (es_13_0 & 0x0F00UL) >> 8;
> - es_7_0 = es_13_0 & 0x0FFUL;
> - *lo_val = (es_7_0 & 0xFFUL) | ((unitmask & 0x0FUL) << 8);
> - *hi_val = (es_11_8 | ((es_13_12)<<(29)));
> + return 0;
> }
>
> /* assign df performance counters for read */
> @@ -218,26 +300,21 @@ static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
> uint64_t config,
> int *is_assigned)
> {
> -
> - struct df_v3_6_event_mask *mask;
> int i, target_cntr;
>
> - target_cntr = -1;
> -
> *is_assigned = 0;
>
> - df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
> + target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
>
> if (target_cntr >= 0) {
> *is_assigned = 1;
> return 0;
> }
>
> - mask = container_of(adev, struct df_v3_6_event_mask, gpu);
> -
> - for (i = 0; i < AMDGPU_DF_MAX_COUNTERS; i++) {
> - if (mask->config_assign_mask[i] == 0ULL) {
> - mask->config_assign_mask[i] = config & 0x0FFFFFFUL;
> + for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
> + if (adev->df_perfmon_config_assign_mask[i] == 0U) {
> + adev->df_perfmon_config_assign_mask[i] =
> + config & 0x0FFFFFFUL;
> return 0;
> }
> }
> @@ -249,66 +326,17 @@ static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
> static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev,
> uint64_t config)
> {
> -
> - struct df_v3_6_event_mask *mask;
> - int target_cntr;
> -
> - target_cntr = -1;
> -
> - df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
> -
> - mask = container_of(adev, struct df_v3_6_event_mask, gpu);
> + int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
>
> if (target_cntr >= 0)
> - mask->config_assign_mask[target_cntr] = 0ULL;
> -
> + adev->df_perfmon_config_assign_mask[target_cntr] = 0ULL;
> }
>
> -/*
> - * get xgmi link counters via programmable data fabric (df) counters (max 4)
> - * using cake tx event.
> - *
> - * @adev -> amdgpu device
> - * @instance-> currently cake has 2 links to poll on vega20
> - * @count -> counters to pass
> - *
> - */
> -
> -static void df_v3_6_get_xgmi_link_cntr(struct amdgpu_device *adev,
> - int instance,
> - uint64_t *count)
> -{
> - uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
> - uint64_t config;
> -
> - config = GET_INSTANCE_CONFIG(instance);
> -
> - df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
> - &hi_base_addr);
> -
> - if ((lo_base_addr == 0) || (hi_base_addr == 0))
> - return;
> -
> - lo_val = RREG32_PCIE(lo_base_addr);
> - hi_val = RREG32_PCIE(hi_base_addr);
>
> - *count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
> -}
> -
> -/*
> - * reset xgmi link counters
> - *
> - * @adev -> amdgpu device
> - * @instance-> currently cake has 2 links to poll on vega20
> - *
> - */
> -static void df_v3_6_reset_xgmi_link_cntr(struct amdgpu_device *adev,
> - int instance)
> +static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
> + uint64_t config)
> {
> uint32_t lo_base_addr, hi_base_addr;
> - uint64_t config;
> -
> - config = 0ULL | (0x7ULL) | ((0x46ULL + instance) << 8) | (0x2 << 16);
>
> df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
> &hi_base_addr);
> @@ -320,185 +348,106 @@ static void df_v3_6_reset_xgmi_link_cntr(struct amdgpu_device *adev,
> WREG32_PCIE(hi_base_addr, 0UL);
> }
>
> -/*
> - * add xgmi link counters
> - *
> - * @adev -> amdgpu device
> - * @instance-> currently cake has 2 links to poll on vega20
> - *
> - */
>
> -static int df_v3_6_add_xgmi_link_cntr(struct amdgpu_device *adev,
> - int instance)
> +static int df_v3_6_add_perfmon_cntr(struct amdgpu_device *adev,
> + uint64_t config)
> {
> uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
> - uint64_t config;
> int ret, is_assigned;
>
> - if (instance < 0 || instance > 1)
> - return -EINVAL;
> -
> - config = GET_INSTANCE_CONFIG(instance);
> -
> ret = df_v3_6_pmc_assign_cntr(adev, config, &is_assigned);
>
> if (ret || is_assigned)
> return ret;
>
> - df_v3_6_pmc_get_ctrl_settings(adev,
> + ret = df_v3_6_pmc_get_ctrl_settings(adev,
> config,
> &lo_base_addr,
> &hi_base_addr,
> &lo_val,
> &hi_val);
>
> + if (ret)
> + return ret;
> +
> + DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
> + config, lo_base_addr, hi_base_addr, lo_val, hi_val);
> +
> WREG32_PCIE(lo_base_addr, lo_val);
> WREG32_PCIE(hi_base_addr, hi_val);
>
> return ret;
> }
>
> -
> -/*
> - * start xgmi link counters
> - *
> - * @adev -> amdgpu device
> - * @instance-> currently cake has 2 links to poll on vega20
> - * @is_enable -> either resume or assign event via df perfmon
> - *
> - */
> -
> -static int df_v3_6_start_xgmi_link_cntr(struct amdgpu_device *adev,
> - int instance,
> - int is_enable)
> +static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
> + int is_enable)
> {
> uint32_t lo_base_addr, hi_base_addr, lo_val;
> - uint64_t config;
> - int ret;
> -
> - if (instance < 0 || instance > 1)
> - return -EINVAL;
> -
> - if (is_enable) {
> + int ret = 0;
>
> - ret = df_v3_6_add_xgmi_link_cntr(adev, instance);
> -
> - if (ret)
> - return ret;
> + switch (adev->asic_type) {
> + case CHIP_VEGA20:
>
> - } else {
> + df_v3_6_reset_perfmon_cntr(adev, config);
>
> - config = GET_INSTANCE_CONFIG(instance);
> + if (is_enable) {
> + ret = df_v3_6_add_perfmon_cntr(adev, config);
> + } else {
> + ret = df_v3_6_pmc_get_ctrl_settings(adev,
> + config,
> + &lo_base_addr,
> + &hi_base_addr,
> + NULL,
> + NULL);
>
> - df_v3_6_pmc_get_ctrl_settings(adev,
> - config,
> - &lo_base_addr,
> - &hi_base_addr,
> - NULL,
> - NULL);
> + if (ret)
> + return ret;
>
> - if (lo_base_addr == 0)
> - return -EINVAL;
> + lo_val = RREG32_PCIE(lo_base_addr);
>
> - lo_val = RREG32_PCIE(lo_base_addr);
> + DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
> + config, lo_base_addr, hi_base_addr, lo_val);
>
> - WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
> + WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
> + }
>
> - ret = 0;
> + break;
> + default:
> + break;
> }
>
> return ret;
> -
> }
>
> -/*
> - * start xgmi link counters
> - *
> - * @adev -> amdgpu device
> - * @instance-> currently cake has 2 links to poll on vega20
> - * @is_enable -> either pause or unassign event via df perfmon
> - *
> - */
> -
> -static int df_v3_6_stop_xgmi_link_cntr(struct amdgpu_device *adev,
> - int instance,
> - int is_disable)
> +static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
> + int is_disable)
> {
> -
> uint32_t lo_base_addr, hi_base_addr, lo_val;
> - uint64_t config;
> -
> - config = GET_INSTANCE_CONFIG(instance);
> -
> - if (is_disable) {
> - df_v3_6_reset_xgmi_link_cntr(adev, instance);
> - df_v3_6_pmc_release_cntr(adev, config);
> - } else {
> -
> - df_v3_6_pmc_get_ctrl_settings(adev,
> - config,
> - &lo_base_addr,
> - &hi_base_addr,
> - NULL,
> - NULL);
> -
> - if ((lo_base_addr == 0) || (hi_base_addr == 0))
> - return -EINVAL;
> -
> - lo_val = RREG32_PCIE(lo_base_addr);
> -
> - WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22));
> - }
> -
> - return 0;
> -}
> -
> -static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
> - int is_enable)
> -{
> - int xgmi_tx_link, ret = 0;
> + int ret = 0;
>
> switch (adev->asic_type) {
> case CHIP_VEGA20:
> - xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
> - : (IS_DF_XGMI_1_TX(config) ? 1 : -1);
> -
> - if (xgmi_tx_link >= 0)
> - ret = df_v3_6_start_xgmi_link_cntr(adev, xgmi_tx_link,
> - is_enable);
> + ret = df_v3_6_pmc_get_ctrl_settings(adev,
> + config,
> + &lo_base_addr,
> + &hi_base_addr,
> + NULL,
> + NULL);
>
> if (ret)
> return ret;
>
> - ret = 0;
> - break;
> - default:
> - break;
> - }
> + lo_val = RREG32_PCIE(lo_base_addr);
>
> - return ret;
> -}
> + DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
> + config, lo_base_addr, hi_base_addr, lo_val);
>
> -static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
> - int is_disable)
> -{
> - int xgmi_tx_link, ret = 0;
> + WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22));
>
> - switch (adev->asic_type) {
> - case CHIP_VEGA20:
> - xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
> - : (IS_DF_XGMI_1_TX(config) ? 1 : -1);
> -
> - if (xgmi_tx_link >= 0) {
> - ret = df_v3_6_stop_xgmi_link_cntr(adev,
> - xgmi_tx_link,
> - is_disable);
> - if (ret)
> - return ret;
> - }
> -
> - ret = 0;
> - break;
> + if (is_disable)
> + df_v3_6_pmc_release_cntr(adev, config);
> +
> + break;
> default:
> break;
> }
> @@ -510,24 +459,34 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
> uint64_t config,
> uint64_t *count)
> {
> -
> - int xgmi_tx_link;
> + uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
> + *count = 0;
>
> switch (adev->asic_type) {
> case CHIP_VEGA20:
> - xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
> - : (IS_DF_XGMI_1_TX(config) ? 1 : -1);
>
> - if (xgmi_tx_link >= 0) {
> - df_v3_6_reset_xgmi_link_cntr(adev, xgmi_tx_link);
> - df_v3_6_get_xgmi_link_cntr(adev, xgmi_tx_link, count);
> - }
> + df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
> + &hi_base_addr);
> +
> + if ((lo_base_addr == 0) || (hi_base_addr == 0))
> + return;
> +
> + lo_val = RREG32_PCIE(lo_base_addr);
> + hi_val = RREG32_PCIE(hi_base_addr);
> +
> + *count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
> +
> + if (*count >= DF_V3_6_PERFMON_OVERFLOW)
> + *count = 0;
> +
> + DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
> + config, lo_base_addr, hi_base_addr, lo_val, hi_val);
>
> break;
> +
> default:
> break;
> }
> -
> }
>
> const struct amdgpu_df_funcs df_v3_6_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.h b/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
> index fcffd807764d..76998541bc30 100644
> --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
> +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
> @@ -36,22 +36,15 @@ enum DF_V3_6_MGCG {
> };
>
> /* Defined in global_features.h as FTI_PERFMON_VISIBLE */
> -#define AMDGPU_DF_MAX_COUNTERS 4
> +#define DF_V3_6_MAX_COUNTERS 4
>
> /* get flags from df perfmon config */
> -#define GET_EVENT(x) (x & 0xFFUL)
> -#define GET_INSTANCE(x) ((x >> 8) & 0xFFUL)
> -#define GET_UNITMASK(x) ((x >> 16) & 0xFFUL)
> -#define GET_INSTANCE_CONFIG(x) (0ULL | (0x07ULL) \
> - | ((0x046ULL + x) << 8) \
> - | (0x02 << 16))
> -
> -/* df event conf macros */
> -#define IS_DF_XGMI_0_TX(x) (GET_EVENT(x) == 0x7 \
> - && GET_INSTANCE(x) == 0x46 && GET_UNITMASK(x) == 0x2)
> -#define IS_DF_XGMI_1_TX(x) (GET_EVENT(x) == 0x7 \
> - && GET_INSTANCE(x) == 0x47 && GET_UNITMASK(x) == 0x2)
> +#define DF_V3_6_GET_EVENT(x) (x & 0xFFUL)
> +#define DF_V3_6_GET_INSTANCE(x) ((x >> 8) & 0xFFUL)
> +#define DF_V3_6_GET_UNITMASK(x) ((x >> 16) & 0xFFUL)
> +#define DF_V3_6_PERFMON_OVERFLOW 0xFFFFFFFFFFFFULL
>
> +extern const struct attribute_group *df_v3_6_attr_groups[];
> extern const struct amdgpu_df_funcs df_v3_6_funcs;
>
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 78bd4fc07bab..7fee24ea7863 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1066,6 +1066,7 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev)
> static int soc15_common_hw_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + int ret;
>
> /* enable pcie gen2/3 link */
> soc15_pcie_gen3_enable(adev);
> @@ -1079,6 +1080,9 @@ static int soc15_common_hw_init(void *handle)
> */
> if (adev->nbio_funcs->remap_hdp_registers)
> adev->nbio_funcs->remap_hdp_registers(adev);
> +
> + adev->df_funcs->init(adev);
> +
> /* enable the doorbell aperture */
> soc15_enable_doorbell_aperture(adev, true);
> /* HW doorbell routing policy: doorbell writing not
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply
* Re: [igt-dev] [PATCH i-g-t 4/5] CONTRIBUTING: Rework a bit and update
From: Ser, Simon @ 2019-06-20 13:49 UTC (permalink / raw)
To: Hiler, Arkadiusz, igt-dev@lists.freedesktop.org; +Cc: Latvala, Petri
In-Reply-To: <20190617105443.8264-4-arkadiusz.hiler@intel.com>
On Mon, 2019-06-17 at 13:54 +0300, Arkadiusz Hiler wrote:
> I have split the main body of the CONTRIBUTING file to 3 sections:
> * the short welcome message
> * the code - styling, suggestions
> * sending patches - licensing informations, mailing lists, reviews, etc.
>
> Changes for the code section contents:
> * link to the kernel coding style docs
> * be more clear on subtest naming
> * mention igt_describe()
>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Should that be a S-o-b instead?
> ---
> CONTRIBUTING.md | 46 ++++++++++++++++++++++++++++++++++++----------
> 1 file changed, 36 insertions(+), 10 deletions(-)
>
> diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
> index d3a3d099..7deba078 100644
> --- a/CONTRIBUTING.md
> +++ b/CONTRIBUTING.md
> @@ -1,9 +1,41 @@
> +CONTRIBUTING
> +============
> +
> Patches to igt-gpu-tools are very much welcome, we really want this to be the
> universal set of low-level tools and testcases for kernel graphics drivers
> on Linux and similar platforms. So please bring on porting patches, bugfixes,
> improvements for documentation and new tools and testcases.
>
> -A short list of contribution guidelines:
> +
> +The Code
> +--------
> +
> +- The code should follow kernel coding style:
> + https://www.kernel.org/doc/html/latest/process/coding-style.html
> +
> +- Testcases (subtests) have to use minus signs (-) as a word separator.
> + The generated documentation contains glossary of commonly used terms.
Do we have a link to this generated documentation somewhere?
> +- All new test have to be described using `igt_describe()` family of
> + functions. The description should contain the spirit of the test (what is
> + the general idea behind the test) and *not* the letter (C to English
> + translation of the test). Refer to `igt_describe()` documentation for more
> + details.
Again, a direct link would be nice.
> +- The generated documentation contains explanation of magic control blocks like
> + `igt_subtest` and `igt_fixture`. Please make sure that you understand their
> + roles and limitation before using/altering them.
> +
> +- Also please make full use of all the helpers and convenience macros
> + provided by the igt library. The semantic patch lib/igt.cocci can help with
> + more automatic conversions.
> +
> +
> +Sending Patches
> +---------------
> +
> +- igt-gpu-tools is MIT licensed and we require contributions to follow the
> + developer's certificate of origin: http://developercertificate.org/
>
> - Please submit patches formatted with git send-email/git format-patch or
> equivalent to:
> @@ -23,14 +55,6 @@ A short list of contribution guidelines:
>
> on its first invocation.
>
> -- igt-gpu-tools is MIT licensed and we require contributions to follow the
> - developer's certificate of origin: http://developercertificate.org/
> -
> -- When submitting new testcases please follow the naming conventions documented
> - in the generated documentation. Also please make full use of all the helpers
> - and convenience macros provided by the igt library. The semantic patch
> - lib/igt.cocci can help with the more automatic conversions.
> -
> - Patches need to be reviewed on the mailing list. Exceptions only apply for
> testcases and tooling for drivers with just a single contributor (e.g. vc4).
> In this case patches must still be submitted to the mailing list first.
> @@ -46,7 +70,8 @@ A short list of contribution guidelines:
> - Changes to the testcases are automatically tested. Take the results into
> account before merging.
>
> -Commit rights
> +
> +Commit Rights
> -------------
>
> Commit rights will be granted to anyone who requests them and fulfills the
> @@ -80,6 +105,7 @@ come back to the project.
> Maintainers and committers should encourage contributors to request commit
> rights, especially junior contributors tend to underestimate their skills.
>
> +
> Code of Conduct
> ---------------
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply
* [PATCH v7 0/6] Add support for Orange Pi 3
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Ondrej Jirman, Mark Rutland, Alexandre Torgue, devicetree,
David Airlie, netdev, linux-kernel, dri-devel, linux-stm32,
Jose Abreu, linux-arm-kernel, Daniel Vetter, Giuseppe Cavallaro,
David S. Miller, Maxime Coquelin
From: Ondrej Jirman <megous@megous.com>
This series implements support for Xunlong Orange Pi 3 board.
- ethernet support (patches 1-3)
- HDMI support (patches 4-6)
For some people, ethernet doesn't work after reboot (but works on cold
boot), when the stmmac driver is built into the kernel. It works when
the driver is built as a module. It's either some timing issue, or power
supply issue or a combination of both. Module build induces a power
cycling of the phy.
I encourage people with this issue, to build the driver into the kernel,
and try to alter the reset timings for the phy in DTS or
startup-delay-us and report the findings.
Please take a look.
thank you and regards,
Ondrej Jirman
Changes in v7:
- dropped stored reference to connector_pdev as suggested by Jernej
- added forgotten dt-bindings reviewed-by tag
Changes in v6:
- added dt-bindings reviewed-by tag
- fix wording in stmmac commit (as suggested by Sergei)
Changes in v5:
- dropped already applied patches (pinctrl patches, mmc1 pinconf patch)
- rename GMAC-3V3 -> GMAC-3V to match the schematic (Jagan)
- changed hdmi-connector's ddc-supply property to ddc-en-gpios
(Rob Herring)
Changes in v4:
- fix checkpatch warnings/style issues
- use enum in struct sunxi_desc_function for io_bias_cfg_variant
- collected acked-by's
- fix compile error in drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c:156
caused by missing conversion from has_io_bias_cfg struct member
(I've kept the acked-by, because it's a trivial change, but feel free
to object.) (reported by Martin A. on github)
I did not have A80 pinctrl enabled for some reason, so I did not catch
this sooner.
- dropped brcm firmware patch (was already applied)
- dropped the wifi dts patch (will re-send after H6 RTC gets merged,
along with bluetooth support, in a separate series)
Changes in v3:
- dropped already applied patches
- changed pinctrl I/O bias selection constants to enum and renamed
- added /omit-if-no-ref/ to mmc1_pins
- made mmc1_pins default pinconf for mmc1 in H6 dtsi
- move ddc-supply to HDMI connector node, updated patch descriptions,
changed dt-bindings docs
Changes in v2:
- added dt-bindings documentation for the board's compatible string
(suggested by Clement)
- addressed checkpatch warnings and code formatting issues (on Maxime's
suggestions)
- stmmac: dropped useless parenthesis, reworded description of the patch
(suggested by Sergei)
- drop useles dev_info() about the selected io bias voltage
- docummented io voltage bias selection variant macros
- wifi: marked WiFi DTS patch and realted mmc1_pins as "DO NOT MERGE",
because wifi depends on H6 RTC support that's not merged yet (suggested
by Clement)
- added missing signed-of-bys
- changed &usb2otg dr_mode to otg, and added a note about VBUS
- improved wording of HDMI driver's DDC power supply patch
Icenowy Zheng (2):
net: stmmac: sun8i: add support for Allwinner H6 EMAC
net: stmmac: sun8i: force select external PHY when no internal one
Ondrej Jirman (4):
arm64: dts: allwinner: orange-pi-3: Enable ethernet
dt-bindings: display: hdmi-connector: Support DDC bus enable
drm: sun4i: Add support for enabling DDC I2C bus to sun8i_dw_hdmi glue
arm64: dts: allwinner: orange-pi-3: Enable HDMI output
.../display/connector/hdmi-connector.txt | 1 +
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 70 +++++++++++++++++++
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 54 ++++++++++++--
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 21 ++++++
5 files changed, 144 insertions(+), 4 deletions(-)
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] powerpc: enable a 30-bit ZONE_DMA for 32-bit pmac
From: Michael Ellerman @ 2019-06-20 13:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Christoph Hellwig, paulus
Cc: Larry.Finger, linuxppc-dev, linux-kernel, aaro.koskinen
In-Reply-To: <a5fc355e44fb5edea41274329f7c5d04a8dff6fc.camel@kernel.crashing.org>
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> On Wed, 2019-06-19 at 22:32 +1000, Michael Ellerman wrote:
>> Christoph Hellwig <hch@lst.de> writes:
>> > Any chance this could get picked up to fix the regression?
>>
>> Was hoping Ben would Ack it. He's still powermac maintainer :)
>>
>> I guess he OK'ed it in the other thread, will add it to my queue.
>
> Yeah ack. If I had written it myself, I would have made the DMA bits a
> variable and only set it down to 30 if I see that device in the DT
> early on, but I can't be bothered now, if it works, ship it :-)
OK, we can do that next release if someone's motivated.
> Note: The patch affects all ppc32, though I don't think it will cause
> any significant issue on those who don't need it.
Yeah. We could always hide it behind CONFIG_PPC_PMAC if it becomes a problem.
cheers
^ permalink raw reply
* [PATCH v7 1/6] net: stmmac: sun8i: add support for Allwinner H6 EMAC
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Mark Rutland, Maxime Coquelin, Ondrej Jirman, Alexandre Torgue,
devicetree, David Airlie, netdev, linux-kernel, dri-devel,
linux-stm32, Jose Abreu, Daniel Vetter, Giuseppe Cavallaro,
David S. Miller, linux-arm-kernel, Icenowy Zheng
In-Reply-To: <20190620134748.17866-1-megous@megous.com>
From: Icenowy Zheng <icenowy@aosc.io>
The EMAC on Allwinner H6 is just like the one on A64. The "internal PHY" on
H6 is on a co-packaged AC200 chip, and it's not really internal (it's
connected via RMII at PA GPIO bank).
Add support for the Allwinner H6 EMAC in the dwmac-sun8i driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index b15c6d5dbd38..c3e94104474f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -138,6 +138,20 @@ static const struct emac_variant emac_variant_a64 = {
.tx_delay_max = 7,
};
+static const struct emac_variant emac_variant_h6 = {
+ .default_syscon_value = 0x50000,
+ .syscon_field = &sun8i_syscon_reg_field,
+ /* The "Internal PHY" of H6 is not on the die. It's on the
+ * co-packaged AC200 chip instead.
+ */
+ .soc_has_internal_phy = false,
+ .support_mii = true,
+ .support_rmii = true,
+ .support_rgmii = true,
+ .rx_delay_max = 31,
+ .tx_delay_max = 7,
+};
+
#define EMAC_BASIC_CTL0 0x00
#define EMAC_BASIC_CTL1 0x04
#define EMAC_INT_STA 0x08
@@ -1216,6 +1230,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
.data = &emac_variant_r40 },
{ .compatible = "allwinner,sun50i-a64-emac",
.data = &emac_variant_a64 },
+ { .compatible = "allwinner,sun50i-h6-emac",
+ .data = &emac_variant_h6 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* ✓ Fi.CI.BAT: success for drm/i915/selftests: Use request managed wakerefs
From: Patchwork @ 2019-06-20 13:49 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
In-Reply-To: <20190620102432.31580-1-chris@chris-wilson.co.uk>
== Series Details ==
Series: drm/i915/selftests: Use request managed wakerefs
URL : https://patchwork.freedesktop.org/series/62445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6312 -> Patchwork_13363
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13363/
Known issues
------------
Here are the changes found in Patchwork_13363 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_switch@basic-default:
- fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108569])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-icl-guc/igt@gem_ctx_switch@basic-default.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13363/fi-icl-guc/igt@gem_ctx_switch@basic-default.html
* igt@gem_exec_create@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-icl-u3/igt@gem_exec_create@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13363/fi-icl-u3/igt@gem_exec_create@basic.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13363/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [DMESG-FAIL][7] ([fdo#110235]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13363/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][9] ([fdo#103167]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13363/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (49 -> 45)
------------------------------
Additional (5): fi-cml-u2 fi-bxt-j4205 fi-gdg-551 fi-icl-dsi fi-cml-u
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6312 -> Patchwork_13363
CI_DRM_6312: 034e3ac6a2d180d188da927388b60c7e62c5655b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5061: c88ced79a7b71aec58f1d9c5c599ac2f431bcf7a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13363: 2c57955587cb19ec6f7054be8ea9ef7275c8e06e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2c57955587cb drm/i915/selftests: Use request managed wakerefs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13363/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: [PATCH 2/2] drm/i915/guc: handle GuC messages received with CTB disabled
From: Chris Wilson @ 2019-06-20 13:48 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
In-Reply-To: <20190619214351.12000-3-daniele.ceraolospurio@intel.com>
Quoting Daniele Ceraolo Spurio (2019-06-19 22:43:51)
> +/*
> + * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
> + * register using the same bits used in the CT message payload. Since our
> + * communication channel with guc is turned off at this point, we can save the
> + * message and handle it after we turn it back on.
> + */
> +static void guc_clear_mmio_msg(struct intel_guc *guc)
> +{
> + intel_uncore_write(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15), 0);
Should the register be cleared on intel_guc_reset()? Otherwise, we would
be associating the stale msg from an earlier guc instance with the
current one.
That would mean clear_mmio_msg would want to be called from
guc_stop_communication not just guc_disable_communication.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [PATCH v7 4/6] dt-bindings: display: hdmi-connector: Support DDC bus enable
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Ondrej Jirman, Mark Rutland, Alexandre Torgue, devicetree,
David Airlie, netdev, linux-kernel, dri-devel, linux-stm32,
Jose Abreu, linux-arm-kernel, Daniel Vetter, Giuseppe Cavallaro,
Rob Herring, David S. Miller, Maxime Coquelin
In-Reply-To: <20190620134748.17866-1-megous@megous.com>
From: Ondrej Jirman <megous@megous.com>
Some Allwinner SoC using boards (Orange Pi 3 for example) need to enable
on-board voltage shifting logic for the DDC bus using a gpio to be able
to access DDC bus. Use ddc-en-gpios property on the hdmi-connector to
model this.
Add binding documentation for optional ddc-en-gpios property.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/display/connector/hdmi-connector.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
index 508aee461e0d..aeb07c4bd703 100644
--- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
+++ b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
@@ -9,6 +9,7 @@ Optional properties:
- label: a symbolic name for the connector
- hpd-gpios: HPD GPIO number
- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing
+- ddc-en-gpios: signal to enable DDC bus
Required nodes:
- Video port for HDMI input
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* linux-next: build failure after merge of the netfilter-next tree
From: Stephen Rothwell @ 2019-06-20 13:47 UTC (permalink / raw)
To: Pablo Neira Ayuso, NetFilter
Cc: Linux Next Mailing List, Linux Kernel Mailing List,
Fernando Fernandez Mancera
[-- Attachment #1: Type: text/plain, Size: 839 bytes --]
Hi all,
After merging the netfilter-next tree, today's linux-next build
(arm imx_v4_v5_defconfig and several others) failed like this:
In file included from net/netfilter/core.c:19:0:
include/linux/netfilter_ipv6.h: In function 'nf_ipv6_cookie_init_sequence':
include/linux/netfilter_ipv6.h:174:2: error: implicit declaration of function '__cookie_v6_init_sequence' [-Werror=implicit-function-declaration]
include/linux/netfilter_ipv6.h: In function 'nf_cookie_v6_check':
include/linux/netfilter_ipv6.h:189:2: error: implicit declaration of function '__cookie_v6_check' [-Werror=implicit-function-declaration]
Caused by commit
3006a5224f15 ("netfilter: synproxy: remove module dependency on IPv6 SYNPROXY")
This has been happening for a few days, sorry.
# CONFIG_IPV6 is not set
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH v7 2/6] net: stmmac: sun8i: force select external PHY when no internal one
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Icenowy Zheng, David Airlie, Daniel Vetter, Mark Rutland,
Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, David S. Miller,
Maxime Coquelin, dri-devel, devicetree, linux-arm-kernel,
linux-kernel, netdev, linux-stm32, Ondrej Jirman
In-Reply-To: <20190620134748.17866-1-megous@megous.com>
From: Icenowy Zheng <icenowy@aosc.io>
The PHY selection bit also exists on SoCs without an internal PHY; if it's
set to 1 (internal PHY, default value) then the MAC will not make use of
any PHY on such SoCs.
This problem appears when adapting for H6, which has no real internal PHY
(the "internal PHY" on H6 is not on-die, but on a co-packaged AC200 chip,
connected via RMII interface at GPIO bank A).
Force the PHY selection bit to 0 when the SOC doesn't have an internal PHY,
to address the problem of a wrong default value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index c3e94104474f..6d5cba4075eb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -898,6 +898,11 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
* address. No need to mask it again.
*/
reg |= 1 << H3_EPHY_ADDR_SHIFT;
+ } else {
+ /* For SoCs without internal PHY the PHY selection bit should be
+ * set to 0 (external PHY).
+ */
+ reg &= ~H3_EPHY_SELECT;
}
if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
--
2.22.0
^ permalink raw reply related
* [Buildroot] [git commit] configs/qemu_riscv64_virt: update to 5.1 kernel
From: Thomas Petazzoni @ 2019-06-20 13:48 UTC (permalink / raw)
To: buildroot
commit: https://git.buildroot.net/buildroot/commit/?id=3bc70e5f70c2ccc8f55ca5cf6960f6a4f572bd76
branch: https://git.buildroot.net/buildroot/commit/?id=refs/heads/master
Update the 64-bit defconfig to use the latest kernel.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
configs/qemu_riscv64_virt_defconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/configs/qemu_riscv64_virt_defconfig b/configs/qemu_riscv64_virt_defconfig
index 12afac44fb..c0b1a43925 100644
--- a/configs/qemu_riscv64_virt_defconfig
+++ b/configs/qemu_riscv64_virt_defconfig
@@ -10,13 +10,13 @@ BR2_TARGET_GENERIC_GETTY_PORT="ttyS0"
# Filesystem
BR2_TARGET_ROOTFS_EXT2=y
-# Linux headers same as kernel, a 4.20 series
-BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_20=y
+# Linux headers same as kernel, a 5.1 series
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_1=y
# Kernel
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.20.17"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.1.12"
BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y
BR2_LINUX_KERNEL_IMAGE=y
^ permalink raw reply related
* [PATCH v7 3/6] arm64: dts: allwinner: orange-pi-3: Enable ethernet
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Ondrej Jirman, Mark Rutland, Alexandre Torgue, devicetree,
David Airlie, netdev, linux-kernel, dri-devel, linux-stm32,
Jose Abreu, linux-arm-kernel, Daniel Vetter, Giuseppe Cavallaro,
David S. Miller, Maxime Coquelin
In-Reply-To: <20190620134748.17866-1-megous@megous.com>
From: Ondrej Jirman <megous@megous.com>
Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
to the phy datasheet, both regulators need to be enabled at the same time,
but we can only specify a single phy-supply in the DT.
This can be achieved by making one regulator depedning on the other via
vin-supply. While it's not a technically correct description of the
hardware, it achieves the purpose.
All values of RX/TX delay were tested exhaustively and a middle one of the
working values was chosen.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..2c6807b74ff6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -15,6 +15,7 @@
aliases {
serial0 = &uart0;
+ ethernet0 = &emac;
};
chosen {
@@ -44,6 +45,27 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
+
+ /*
+ * The board uses 2.5V RGMII signalling. Power sequence to enable
+ * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
+ * at the same time and to wait 100ms.
+ */
+ reg_gmac_2v5: gmac-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+
+ /* The real parent of gmac-2v5 is reg_vcc5v, but we need to
+ * enable two regulators to power the phy. This is one way
+ * to achieve that.
+ */
+ vin-supply = <®_aldo2>; /* GMAC-3V */
+ };
};
&cpu0 {
@@ -58,6 +80,28 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <®_gmac_2v5>;
+ allwinner,rx-delay-ps = <1500>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+ reset-assert-us = <15000>;
+ reset-deassert-us = <40000>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH net-next] hinic: implement the statistical interface of ethtool
From: Xue Chaojing @ 2019-06-20 5:58 UTC (permalink / raw)
To: davem
Cc: linux-kernel, netdev, luoshaokai, cloud.wangxiaoyun, xuechaojing,
chiqijun, wulike1
This patch implement the statistical interface of ethtool, user can use
ethtool -S to show hinic statistics.
Signed-off-by: Xue Chaojing <xuechaojing@huawei.com>
---
.../net/ethernet/huawei/hinic/hinic_ethtool.c | 341 ++++++++++++++++++
.../net/ethernet/huawei/hinic/hinic_hw_dev.h | 8 +
.../net/ethernet/huawei/hinic/hinic_main.c | 5 +
.../net/ethernet/huawei/hinic/hinic_port.c | 66 ++++
.../net/ethernet/huawei/hinic/hinic_port.h | 174 +++++++++
drivers/net/ethernet/huawei/hinic/hinic_rx.c | 15 +-
drivers/net/ethernet/huawei/hinic/hinic_rx.h | 5 +-
drivers/net/ethernet/huawei/hinic/hinic_tx.c | 8 +
drivers/net/ethernet/huawei/hinic/hinic_tx.h | 1 +
9 files changed, 620 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c b/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c
index be28a9a7f033..01e8793fcb7f 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c
@@ -438,6 +438,344 @@ static u32 hinic_get_rxfh_indir_size(struct net_device *netdev)
return HINIC_RSS_INDIR_SIZE;
}
+#define ARRAY_LEN(arr) ((int)((int)sizeof(arr) / (int)sizeof(arr[0])))
+
+#define HINIC_NETDEV_STAT(_stat_item) { \
+ .name = #_stat_item, \
+ .size = FIELD_SIZEOF(struct rtnl_link_stats64, _stat_item), \
+ .offset = offsetof(struct rtnl_link_stats64, _stat_item) \
+}
+
+static struct hinic_stats hinic_netdev_stats[] = {
+ HINIC_NETDEV_STAT(rx_packets),
+ HINIC_NETDEV_STAT(tx_packets),
+ HINIC_NETDEV_STAT(rx_bytes),
+ HINIC_NETDEV_STAT(tx_bytes),
+ HINIC_NETDEV_STAT(rx_errors),
+ HINIC_NETDEV_STAT(tx_errors),
+ HINIC_NETDEV_STAT(rx_dropped),
+ HINIC_NETDEV_STAT(tx_dropped),
+ HINIC_NETDEV_STAT(multicast),
+ HINIC_NETDEV_STAT(collisions),
+ HINIC_NETDEV_STAT(rx_length_errors),
+ HINIC_NETDEV_STAT(rx_over_errors),
+ HINIC_NETDEV_STAT(rx_crc_errors),
+ HINIC_NETDEV_STAT(rx_frame_errors),
+ HINIC_NETDEV_STAT(rx_fifo_errors),
+ HINIC_NETDEV_STAT(rx_missed_errors),
+ HINIC_NETDEV_STAT(tx_aborted_errors),
+ HINIC_NETDEV_STAT(tx_carrier_errors),
+ HINIC_NETDEV_STAT(tx_fifo_errors),
+ HINIC_NETDEV_STAT(tx_heartbeat_errors),
+};
+
+#define HINIC_FUNC_STAT(_stat_item) { \
+ .name = #_stat_item, \
+ .size = FIELD_SIZEOF(struct hinic_vport_stats, _stat_item), \
+ .offset = offsetof(struct hinic_vport_stats, _stat_item) \
+}
+
+static struct hinic_stats hinic_function_stats[] = {
+ HINIC_FUNC_STAT(tx_unicast_pkts_vport),
+ HINIC_FUNC_STAT(tx_unicast_bytes_vport),
+ HINIC_FUNC_STAT(tx_multicast_pkts_vport),
+ HINIC_FUNC_STAT(tx_multicast_bytes_vport),
+ HINIC_FUNC_STAT(tx_broadcast_pkts_vport),
+ HINIC_FUNC_STAT(tx_broadcast_bytes_vport),
+
+ HINIC_FUNC_STAT(rx_unicast_pkts_vport),
+ HINIC_FUNC_STAT(rx_unicast_bytes_vport),
+ HINIC_FUNC_STAT(rx_multicast_pkts_vport),
+ HINIC_FUNC_STAT(rx_multicast_bytes_vport),
+ HINIC_FUNC_STAT(rx_broadcast_pkts_vport),
+ HINIC_FUNC_STAT(rx_broadcast_bytes_vport),
+
+ HINIC_FUNC_STAT(tx_discard_vport),
+ HINIC_FUNC_STAT(rx_discard_vport),
+ HINIC_FUNC_STAT(tx_err_vport),
+ HINIC_FUNC_STAT(rx_err_vport),
+};
+
+#define HINIC_PORT_STAT(_stat_item) { \
+ .name = #_stat_item, \
+ .size = FIELD_SIZEOF(struct hinic_phy_port_stats, _stat_item), \
+ .offset = offsetof(struct hinic_phy_port_stats, _stat_item) \
+}
+
+static struct hinic_stats hinic_port_stats[] = {
+ HINIC_PORT_STAT(mac_rx_total_pkt_num),
+ HINIC_PORT_STAT(mac_rx_total_oct_num),
+ HINIC_PORT_STAT(mac_rx_bad_pkt_num),
+ HINIC_PORT_STAT(mac_rx_bad_oct_num),
+ HINIC_PORT_STAT(mac_rx_good_pkt_num),
+ HINIC_PORT_STAT(mac_rx_good_oct_num),
+ HINIC_PORT_STAT(mac_rx_uni_pkt_num),
+ HINIC_PORT_STAT(mac_rx_multi_pkt_num),
+ HINIC_PORT_STAT(mac_rx_broad_pkt_num),
+ HINIC_PORT_STAT(mac_tx_total_pkt_num),
+ HINIC_PORT_STAT(mac_tx_total_oct_num),
+ HINIC_PORT_STAT(mac_tx_bad_pkt_num),
+ HINIC_PORT_STAT(mac_tx_bad_oct_num),
+ HINIC_PORT_STAT(mac_tx_good_pkt_num),
+ HINIC_PORT_STAT(mac_tx_good_oct_num),
+ HINIC_PORT_STAT(mac_tx_uni_pkt_num),
+ HINIC_PORT_STAT(mac_tx_multi_pkt_num),
+ HINIC_PORT_STAT(mac_tx_broad_pkt_num),
+ HINIC_PORT_STAT(mac_rx_fragment_pkt_num),
+ HINIC_PORT_STAT(mac_rx_undersize_pkt_num),
+ HINIC_PORT_STAT(mac_rx_undermin_pkt_num),
+ HINIC_PORT_STAT(mac_rx_64_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_65_127_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_128_255_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_256_511_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_512_1023_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_1024_1518_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_1519_2047_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_2048_4095_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_4096_8191_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_8192_9216_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_9217_12287_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_12288_16383_oct_pkt_num),
+ HINIC_PORT_STAT(mac_rx_1519_max_good_pkt_num),
+ HINIC_PORT_STAT(mac_rx_1519_max_bad_pkt_num),
+ HINIC_PORT_STAT(mac_rx_oversize_pkt_num),
+ HINIC_PORT_STAT(mac_rx_jabber_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pause_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pri0_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pri1_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pri2_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pri3_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pri4_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pri5_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pri6_pkt_num),
+ HINIC_PORT_STAT(mac_rx_pfc_pri7_pkt_num),
+ HINIC_PORT_STAT(mac_rx_control_pkt_num),
+ HINIC_PORT_STAT(mac_rx_sym_err_pkt_num),
+ HINIC_PORT_STAT(mac_rx_fcs_err_pkt_num),
+ HINIC_PORT_STAT(mac_rx_send_app_good_pkt_num),
+ HINIC_PORT_STAT(mac_rx_send_app_bad_pkt_num),
+ HINIC_PORT_STAT(mac_tx_fragment_pkt_num),
+ HINIC_PORT_STAT(mac_tx_undersize_pkt_num),
+ HINIC_PORT_STAT(mac_tx_undermin_pkt_num),
+ HINIC_PORT_STAT(mac_tx_64_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_65_127_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_128_255_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_256_511_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_512_1023_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_1024_1518_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_1519_2047_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_2048_4095_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_4096_8191_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_8192_9216_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_9217_12287_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_12288_16383_oct_pkt_num),
+ HINIC_PORT_STAT(mac_tx_1519_max_good_pkt_num),
+ HINIC_PORT_STAT(mac_tx_1519_max_bad_pkt_num),
+ HINIC_PORT_STAT(mac_tx_oversize_pkt_num),
+ HINIC_PORT_STAT(mac_tx_jabber_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pause_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pri0_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pri1_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pri2_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pri3_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pri4_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pri5_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pri6_pkt_num),
+ HINIC_PORT_STAT(mac_tx_pfc_pri7_pkt_num),
+ HINIC_PORT_STAT(mac_tx_control_pkt_num),
+ HINIC_PORT_STAT(mac_tx_err_all_pkt_num),
+ HINIC_PORT_STAT(mac_tx_from_app_good_pkt_num),
+ HINIC_PORT_STAT(mac_tx_from_app_bad_pkt_num),
+};
+
+#define HINIC_TXQ_STAT(_stat_item) { \
+ .name = "txq%d_"#_stat_item, \
+ .size = FIELD_SIZEOF(struct hinic_txq_stats, _stat_item), \
+ .offset = offsetof(struct hinic_txq_stats, _stat_item) \
+}
+
+static struct hinic_stats hinic_tx_queue_stats[] = {
+ HINIC_TXQ_STAT(pkts),
+ HINIC_TXQ_STAT(bytes),
+ HINIC_TXQ_STAT(tx_busy),
+ HINIC_TXQ_STAT(tx_wake),
+ HINIC_TXQ_STAT(tx_dropped),
+ HINIC_TXQ_STAT(big_frags_pkts),
+};
+
+#define HINIC_RXQ_STAT(_stat_item) { \
+ .name = "rxq%d_"#_stat_item, \
+ .size = FIELD_SIZEOF(struct hinic_rxq_stats, _stat_item), \
+ .offset = offsetof(struct hinic_rxq_stats, _stat_item) \
+}
+
+static struct hinic_stats hinic_rx_queue_stats[] = {
+ HINIC_RXQ_STAT(pkts),
+ HINIC_RXQ_STAT(bytes),
+ HINIC_RXQ_STAT(errors),
+ HINIC_RXQ_STAT(csum_errors),
+ HINIC_RXQ_STAT(other_errors),
+};
+
+static void get_drv_queue_stats(struct hinic_dev *nic_dev, u64 *data)
+{
+ struct hinic_txq_stats txq_stats;
+ struct hinic_rxq_stats rxq_stats;
+ u16 i = 0, j = 0, qid = 0;
+ char *p;
+
+ for (qid = 0; qid < nic_dev->num_qps; qid++) {
+ if (!nic_dev->txqs)
+ break;
+
+ hinic_txq_get_stats(&nic_dev->txqs[qid], &txq_stats);
+ for (j = 0; j < ARRAY_LEN(hinic_tx_queue_stats); j++, i++) {
+ p = (char *)(&txq_stats) +
+ hinic_tx_queue_stats[j].offset;
+ data[i] = (hinic_tx_queue_stats[j].size ==
+ sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+ }
+ }
+
+ for (qid = 0; qid < nic_dev->num_qps; qid++) {
+ if (!nic_dev->rxqs)
+ break;
+
+ hinic_rxq_get_stats(&nic_dev->rxqs[qid], &rxq_stats);
+ for (j = 0; j < ARRAY_LEN(hinic_rx_queue_stats); j++, i++) {
+ p = (char *)(&rxq_stats) +
+ hinic_rx_queue_stats[j].offset;
+ data[i] = (hinic_rx_queue_stats[j].size ==
+ sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+ }
+ }
+}
+
+static void hinic_get_ethtool_stats(struct net_device *netdev,
+ struct ethtool_stats *stats, u64 *data)
+{
+ struct hinic_dev *nic_dev = netdev_priv(netdev);
+ struct hinic_vport_stats vport_stats = {0};
+ const struct rtnl_link_stats64 *net_stats;
+ struct hinic_phy_port_stats *port_stats;
+ struct rtnl_link_stats64 temp;
+ u16 i = 0, j = 0;
+ char *p;
+ int err;
+
+ net_stats = dev_get_stats(netdev, &temp);
+ for (j = 0; j < ARRAY_LEN(hinic_netdev_stats); j++, i++) {
+ p = (char *)(net_stats) + hinic_netdev_stats[j].offset;
+ data[i] = (hinic_netdev_stats[j].size ==
+ sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+ }
+
+ err = hinic_get_vport_stats(nic_dev, &vport_stats);
+ if (err)
+ netif_err(nic_dev, drv, netdev,
+ "Failed to get vport stats from firmware\n");
+
+ for (j = 0; j < ARRAY_LEN(hinic_function_stats); j++, i++) {
+ p = (char *)(&vport_stats) + hinic_function_stats[j].offset;
+ data[i] = (hinic_function_stats[j].size ==
+ sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+ }
+
+ port_stats = kzalloc(sizeof(*port_stats), GFP_KERNEL);
+ if (!port_stats) {
+ memset(&data[i], 0,
+ ARRAY_LEN(hinic_port_stats) * sizeof(*data));
+ i += ARRAY_LEN(hinic_port_stats);
+ goto get_drv_stats;
+ }
+
+ err = hinic_get_phy_port_stats(nic_dev, port_stats);
+ if (err)
+ netif_err(nic_dev, drv, netdev,
+ "Failed to get port stats from firmware\n");
+
+ for (j = 0; j < ARRAY_LEN(hinic_port_stats); j++, i++) {
+ p = (char *)(port_stats) + hinic_port_stats[j].offset;
+ data[i] = (hinic_port_stats[j].size ==
+ sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+ }
+
+ kfree(port_stats);
+
+get_drv_stats:
+ get_drv_queue_stats(nic_dev, data + i);
+}
+
+static int hinic_get_sset_count(struct net_device *netdev, int sset)
+{
+ struct hinic_dev *nic_dev = netdev_priv(netdev);
+ int count, q_num;
+
+ switch (sset) {
+ case ETH_SS_STATS:
+ q_num = nic_dev->num_qps;
+ count = ARRAY_LEN(hinic_netdev_stats) +
+ ARRAY_LEN(hinic_function_stats) +
+ (ARRAY_LEN(hinic_tx_queue_stats) +
+ ARRAY_LEN(hinic_rx_queue_stats)) * q_num;
+
+ count += ARRAY_LEN(hinic_port_stats);
+
+ return count;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static void hinic_get_strings(struct net_device *netdev,
+ u32 stringset, u8 *data)
+{
+ struct hinic_dev *nic_dev = netdev_priv(netdev);
+ char *p = (char *)data;
+ u16 i, j;
+
+ switch (stringset) {
+ case ETH_SS_STATS:
+ for (i = 0; i < ARRAY_LEN(hinic_netdev_stats); i++) {
+ memcpy(p, hinic_netdev_stats[i].name,
+ ETH_GSTRING_LEN);
+ p += ETH_GSTRING_LEN;
+ }
+
+ for (i = 0; i < ARRAY_LEN(hinic_function_stats); i++) {
+ memcpy(p, hinic_function_stats[i].name,
+ ETH_GSTRING_LEN);
+ p += ETH_GSTRING_LEN;
+ }
+
+ for (i = 0; i < ARRAY_LEN(hinic_port_stats); i++) {
+ memcpy(p, hinic_port_stats[i].name,
+ ETH_GSTRING_LEN);
+ p += ETH_GSTRING_LEN;
+ }
+
+ for (i = 0; i < nic_dev->num_qps; i++) {
+ for (j = 0; j < ARRAY_LEN(hinic_tx_queue_stats); j++) {
+ sprintf(p, hinic_tx_queue_stats[j].name, i);
+ p += ETH_GSTRING_LEN;
+ }
+ }
+
+ for (i = 0; i < nic_dev->num_qps; i++) {
+ for (j = 0; j < ARRAY_LEN(hinic_rx_queue_stats); j++) {
+ sprintf(p, hinic_rx_queue_stats[j].name, i);
+ p += ETH_GSTRING_LEN;
+ }
+ }
+
+ return;
+ default:
+ return;
+ }
+}
+
static const struct ethtool_ops hinic_ethtool_ops = {
.get_link_ksettings = hinic_get_link_ksettings,
.get_drvinfo = hinic_get_drvinfo,
@@ -450,6 +788,9 @@ static const struct ethtool_ops hinic_ethtool_ops = {
.get_rxfh_indir_size = hinic_get_rxfh_indir_size,
.get_rxfh = hinic_get_rxfh,
.set_rxfh = hinic_set_rxfh,
+ .get_sset_count = hinic_get_sset_count,
+ .get_ethtool_stats = hinic_get_ethtool_stats,
+ .get_strings = hinic_get_strings,
};
void hinic_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h b/drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h
index 7f854392f4e7..1220321614b4 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h
@@ -54,6 +54,14 @@ enum hinic_port_cmd {
HINIC_PORT_CMD_SET_RX_CSUM = 26,
+ HINIC_PORT_CMD_GET_PORT_STATISTICS = 28,
+
+ HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29,
+
+ HINIC_PORT_CMD_GET_VPORT_STAT = 30,
+
+ HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31,
+
HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37,
HINIC_PORT_CMD_SET_PORT_STATE = 41,
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_main.c b/drivers/net/ethernet/huawei/hinic/hinic_main.c
index 853fc3e7b514..152d16eabb1a 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_main.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_main.c
@@ -92,6 +92,9 @@ static void update_rx_stats(struct hinic_dev *nic_dev, struct hinic_rxq *rxq)
u64_stats_update_begin(&nic_rx_stats->syncp);
nic_rx_stats->bytes += rx_stats.bytes;
nic_rx_stats->pkts += rx_stats.pkts;
+ nic_rx_stats->errors += rx_stats.errors;
+ nic_rx_stats->csum_errors += rx_stats.csum_errors;
+ nic_rx_stats->other_errors += rx_stats.other_errors;
u64_stats_update_end(&nic_rx_stats->syncp);
hinic_rxq_clean_stats(rxq);
@@ -112,6 +115,7 @@ static void update_tx_stats(struct hinic_dev *nic_dev, struct hinic_txq *txq)
nic_tx_stats->tx_busy += tx_stats.tx_busy;
nic_tx_stats->tx_wake += tx_stats.tx_wake;
nic_tx_stats->tx_dropped += tx_stats.tx_dropped;
+ nic_tx_stats->big_frags_pkts += tx_stats.big_frags_pkts;
u64_stats_update_end(&nic_tx_stats->syncp);
hinic_txq_clean_stats(txq);
@@ -791,6 +795,7 @@ static void hinic_get_stats64(struct net_device *netdev,
stats->rx_bytes = nic_rx_stats->bytes;
stats->rx_packets = nic_rx_stats->pkts;
+ stats->rx_errors = nic_rx_stats->errors;
stats->tx_bytes = nic_tx_stats->bytes;
stats->tx_packets = nic_tx_stats->pkts;
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_port.c b/drivers/net/ethernet/huawei/hinic/hinic_port.c
index 3bd24cb8ed4b..85a56ecd1e66 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_port.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_port.c
@@ -942,3 +942,69 @@ int hinic_rss_template_free(struct hinic_dev *nic_dev, u8 tmpl_idx)
return 0;
}
+
+int hinic_get_vport_stats(struct hinic_dev *nic_dev,
+ struct hinic_vport_stats *stats)
+{
+ struct hinic_cmd_vport_stats vport_stats = {0};
+ struct hinic_port_stats_info stats_info = {0};
+ struct hinic_hwdev *hwdev = nic_dev->hwdev;
+ struct hinic_hwif *hwif = hwdev->hwif;
+ u16 out_size = sizeof(vport_stats);
+ struct pci_dev *pdev = hwif->pdev;
+ int err;
+
+ stats_info.stats_version = HINIC_PORT_STATS_VERSION;
+ stats_info.func_id = HINIC_HWIF_FUNC_IDX(hwif);
+ stats_info.stats_size = sizeof(vport_stats);
+
+ err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_VPORT_STAT,
+ &stats_info, sizeof(stats_info),
+ &vport_stats, &out_size);
+ if (err || !out_size || vport_stats.status) {
+ dev_err(&pdev->dev,
+ "Failed to get function statistics, err: %d, status: 0x%x, out size: 0x%x\n",
+ err, vport_stats.status, out_size);
+ return -EFAULT;
+ }
+
+ memcpy(stats, &vport_stats.stats, sizeof(*stats));
+ return 0;
+}
+
+int hinic_get_phy_port_stats(struct hinic_dev *nic_dev,
+ struct hinic_phy_port_stats *stats)
+{
+ struct hinic_port_stats_info stats_info = {0};
+ struct hinic_hwdev *hwdev = nic_dev->hwdev;
+ struct hinic_hwif *hwif = hwdev->hwif;
+ struct hinic_port_stats *port_stats;
+ u16 out_size = sizeof(*port_stats);
+ struct pci_dev *pdev = hwif->pdev;
+ int err;
+
+ port_stats = kzalloc(sizeof(*port_stats), GFP_KERNEL);
+ if (!port_stats)
+ return -ENOMEM;
+
+ stats_info.stats_version = HINIC_PORT_STATS_VERSION;
+ stats_info.stats_size = sizeof(*port_stats);
+
+ err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_PORT_STATISTICS,
+ &stats_info, sizeof(stats_info),
+ port_stats, &out_size);
+ if (err || !out_size || port_stats->status) {
+ dev_err(&pdev->dev,
+ "Failed to get port statistics, err: %d, status: 0x%x, out size: 0x%x\n",
+ err, port_stats->status, out_size);
+ err = -EINVAL;
+ goto out;
+ }
+
+ memcpy(stats, &port_stats->stats, sizeof(*stats));
+
+out:
+ kfree(port_stats);
+
+ return err;
+}
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_port.h b/drivers/net/ethernet/huawei/hinic/hinic_port.h
index f177945d64ae..8640ac0dc3ea 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_port.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_port.h
@@ -24,6 +24,7 @@
#define HINIC_RSS_KEY_SIZE 40
#define HINIC_RSS_INDIR_SIZE 256
+#define HINIC_PORT_STATS_VERSION 0
enum hinic_rx_mode {
HINIC_RX_MODE_UC = BIT(0),
@@ -325,6 +326,173 @@ struct hinic_rss_config {
u8 rsvd1[11];
};
+struct hinic_stats {
+ char name[ETH_GSTRING_LEN];
+ u32 size;
+ int offset;
+};
+
+struct hinic_vport_stats {
+ u64 tx_unicast_pkts_vport;
+ u64 tx_unicast_bytes_vport;
+ u64 tx_multicast_pkts_vport;
+ u64 tx_multicast_bytes_vport;
+ u64 tx_broadcast_pkts_vport;
+ u64 tx_broadcast_bytes_vport;
+
+ u64 rx_unicast_pkts_vport;
+ u64 rx_unicast_bytes_vport;
+ u64 rx_multicast_pkts_vport;
+ u64 rx_multicast_bytes_vport;
+ u64 rx_broadcast_pkts_vport;
+ u64 rx_broadcast_bytes_vport;
+
+ u64 tx_discard_vport;
+ u64 rx_discard_vport;
+ u64 tx_err_vport;
+ u64 rx_err_vport;
+};
+
+struct hinic_phy_port_stats {
+ u64 mac_rx_total_pkt_num;
+ u64 mac_rx_total_oct_num;
+ u64 mac_rx_bad_pkt_num;
+ u64 mac_rx_bad_oct_num;
+ u64 mac_rx_good_pkt_num;
+ u64 mac_rx_good_oct_num;
+ u64 mac_rx_uni_pkt_num;
+ u64 mac_rx_multi_pkt_num;
+ u64 mac_rx_broad_pkt_num;
+
+ u64 mac_tx_total_pkt_num;
+ u64 mac_tx_total_oct_num;
+ u64 mac_tx_bad_pkt_num;
+ u64 mac_tx_bad_oct_num;
+ u64 mac_tx_good_pkt_num;
+ u64 mac_tx_good_oct_num;
+ u64 mac_tx_uni_pkt_num;
+ u64 mac_tx_multi_pkt_num;
+ u64 mac_tx_broad_pkt_num;
+
+ u64 mac_rx_fragment_pkt_num;
+ u64 mac_rx_undersize_pkt_num;
+ u64 mac_rx_undermin_pkt_num;
+ u64 mac_rx_64_oct_pkt_num;
+ u64 mac_rx_65_127_oct_pkt_num;
+ u64 mac_rx_128_255_oct_pkt_num;
+ u64 mac_rx_256_511_oct_pkt_num;
+ u64 mac_rx_512_1023_oct_pkt_num;
+ u64 mac_rx_1024_1518_oct_pkt_num;
+ u64 mac_rx_1519_2047_oct_pkt_num;
+ u64 mac_rx_2048_4095_oct_pkt_num;
+ u64 mac_rx_4096_8191_oct_pkt_num;
+ u64 mac_rx_8192_9216_oct_pkt_num;
+ u64 mac_rx_9217_12287_oct_pkt_num;
+ u64 mac_rx_12288_16383_oct_pkt_num;
+ u64 mac_rx_1519_max_bad_pkt_num;
+ u64 mac_rx_1519_max_good_pkt_num;
+ u64 mac_rx_oversize_pkt_num;
+ u64 mac_rx_jabber_pkt_num;
+
+ u64 mac_rx_pause_num;
+ u64 mac_rx_pfc_pkt_num;
+ u64 mac_rx_pfc_pri0_pkt_num;
+ u64 mac_rx_pfc_pri1_pkt_num;
+ u64 mac_rx_pfc_pri2_pkt_num;
+ u64 mac_rx_pfc_pri3_pkt_num;
+ u64 mac_rx_pfc_pri4_pkt_num;
+ u64 mac_rx_pfc_pri5_pkt_num;
+ u64 mac_rx_pfc_pri6_pkt_num;
+ u64 mac_rx_pfc_pri7_pkt_num;
+ u64 mac_rx_control_pkt_num;
+ u64 mac_rx_y1731_pkt_num;
+ u64 mac_rx_sym_err_pkt_num;
+ u64 mac_rx_fcs_err_pkt_num;
+ u64 mac_rx_send_app_good_pkt_num;
+ u64 mac_rx_send_app_bad_pkt_num;
+
+ u64 mac_tx_fragment_pkt_num;
+ u64 mac_tx_undersize_pkt_num;
+ u64 mac_tx_undermin_pkt_num;
+ u64 mac_tx_64_oct_pkt_num;
+ u64 mac_tx_65_127_oct_pkt_num;
+ u64 mac_tx_128_255_oct_pkt_num;
+ u64 mac_tx_256_511_oct_pkt_num;
+ u64 mac_tx_512_1023_oct_pkt_num;
+ u64 mac_tx_1024_1518_oct_pkt_num;
+ u64 mac_tx_1519_2047_oct_pkt_num;
+ u64 mac_tx_2048_4095_oct_pkt_num;
+ u64 mac_tx_4096_8191_oct_pkt_num;
+ u64 mac_tx_8192_9216_oct_pkt_num;
+ u64 mac_tx_9217_12287_oct_pkt_num;
+ u64 mac_tx_12288_16383_oct_pkt_num;
+ u64 mac_tx_1519_max_bad_pkt_num;
+ u64 mac_tx_1519_max_good_pkt_num;
+ u64 mac_tx_oversize_pkt_num;
+ u64 mac_tx_jabber_pkt_num;
+
+ u64 mac_tx_pause_num;
+ u64 mac_tx_pfc_pkt_num;
+ u64 mac_tx_pfc_pri0_pkt_num;
+ u64 mac_tx_pfc_pri1_pkt_num;
+ u64 mac_tx_pfc_pri2_pkt_num;
+ u64 mac_tx_pfc_pri3_pkt_num;
+ u64 mac_tx_pfc_pri4_pkt_num;
+ u64 mac_tx_pfc_pri5_pkt_num;
+ u64 mac_tx_pfc_pri6_pkt_num;
+ u64 mac_tx_pfc_pri7_pkt_num;
+ u64 mac_tx_control_pkt_num;
+ u64 mac_tx_y1731_pkt_num;
+ u64 mac_tx_1588_pkt_num;
+ u64 mac_tx_err_all_pkt_num;
+ u64 mac_tx_from_app_good_pkt_num;
+ u64 mac_tx_from_app_bad_pkt_num;
+
+ u64 mac_rx_higig2_ext_pkt_num;
+ u64 mac_rx_higig2_message_pkt_num;
+ u64 mac_rx_higig2_error_pkt_num;
+ u64 mac_rx_higig2_cpu_ctrl_pkt_num;
+ u64 mac_rx_higig2_unicast_pkt_num;
+ u64 mac_rx_higig2_broadcast_pkt_num;
+ u64 mac_rx_higig2_l2_multicast_pkt_num;
+ u64 mac_rx_higig2_l3_multicast_pkt_num;
+
+ u64 mac_tx_higig2_message_pkt_num;
+ u64 mac_tx_higig2_ext_pkt_num;
+ u64 mac_tx_higig2_cpu_ctrl_pkt_num;
+ u64 mac_tx_higig2_unicast_pkt_num;
+ u64 mac_tx_higig2_broadcast_pkt_num;
+ u64 mac_tx_higig2_l2_multicast_pkt_num;
+ u64 mac_tx_higig2_l3_multicast_pkt_num;
+};
+
+struct hinic_port_stats_info {
+ u8 status;
+ u8 version;
+ u8 rsvd0[6];
+
+ u16 func_id;
+ u16 rsvd1;
+ u32 stats_version;
+ u32 stats_size;
+};
+
+struct hinic_port_stats {
+ u8 status;
+ u8 version;
+ u8 rsvd[6];
+
+ struct hinic_phy_port_stats stats;
+};
+
+struct hinic_cmd_vport_stats {
+ u8 status;
+ u8 version;
+ u8 rsvd0[6];
+
+ struct hinic_vport_stats stats;
+};
+
int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr,
u16 vlan_id);
@@ -393,4 +561,10 @@ int hinic_rss_get_template_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
int hinic_rss_get_hash_engine(struct hinic_dev *nic_dev, u8 tmpl_idx,
u8 *type);
+
+int hinic_get_phy_port_stats(struct hinic_dev *nic_dev,
+ struct hinic_phy_port_stats *stats);
+
+int hinic_get_vport_stats(struct hinic_dev *nic_dev,
+ struct hinic_vport_stats *stats);
#endif
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_rx.c b/drivers/net/ethernet/huawei/hinic/hinic_rx.c
index 04c887d13848..a6c498e9a0fd 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_rx.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_rx.c
@@ -65,6 +65,9 @@ void hinic_rxq_clean_stats(struct hinic_rxq *rxq)
u64_stats_update_begin(&rxq_stats->syncp);
rxq_stats->pkts = 0;
rxq_stats->bytes = 0;
+ rxq_stats->errors = 0;
+ rxq_stats->csum_errors = 0;
+ rxq_stats->other_errors = 0;
u64_stats_update_end(&rxq_stats->syncp);
}
@@ -83,6 +86,10 @@ void hinic_rxq_get_stats(struct hinic_rxq *rxq, struct hinic_rxq_stats *stats)
start = u64_stats_fetch_begin(&rxq_stats->syncp);
stats->pkts = rxq_stats->pkts;
stats->bytes = rxq_stats->bytes;
+ stats->errors = rxq_stats->csum_errors +
+ rxq_stats->other_errors;
+ stats->csum_errors = rxq_stats->csum_errors;
+ stats->other_errors = rxq_stats->other_errors;
} while (u64_stats_fetch_retry(&rxq_stats->syncp, start));
u64_stats_update_end(&stats->syncp);
}
@@ -110,10 +117,14 @@ static void rx_csum(struct hinic_rxq *rxq, u32 status,
if (!(netdev->features & NETIF_F_RXCSUM))
return;
- if (!csum_err)
+ if (!csum_err) {
skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
+ } else {
+ if (!(csum_err & (HINIC_RX_CSUM_HW_CHECK_NONE |
+ HINIC_RX_CSUM_IPSU_OTHER_ERR)))
+ rxq->rxq_stats.csum_errors++;
skb->ip_summed = CHECKSUM_NONE;
+ }
}
/**
* rx_alloc_skb - allocate skb and map it to dma address
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_rx.h b/drivers/net/ethernet/huawei/hinic/hinic_rx.h
index 08e7d88382cd..233d3850b7a8 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_rx.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_rx.h
@@ -30,7 +30,10 @@
struct hinic_rxq_stats {
u64 pkts;
u64 bytes;
-
+ u64 errors;
+ u64 csum_errors;
+ u64 other_errors;
+ u64 alloc_skb_err;
struct u64_stats_sync syncp;
};
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_tx.c b/drivers/net/ethernet/huawei/hinic/hinic_tx.c
index 0fbe8046824b..639ec81e0e10 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_tx.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_tx.c
@@ -92,6 +92,7 @@ void hinic_txq_clean_stats(struct hinic_txq *txq)
txq_stats->tx_busy = 0;
txq_stats->tx_wake = 0;
txq_stats->tx_dropped = 0;
+ txq_stats->big_frags_pkts = 0;
u64_stats_update_end(&txq_stats->syncp);
}
@@ -113,6 +114,7 @@ void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats)
stats->tx_busy = txq_stats->tx_busy;
stats->tx_wake = txq_stats->tx_wake;
stats->tx_dropped = txq_stats->tx_dropped;
+ stats->big_frags_pkts = txq_stats->big_frags_pkts;
} while (u64_stats_fetch_retry(&txq_stats->syncp, start));
u64_stats_update_end(&stats->syncp);
}
@@ -473,6 +475,12 @@ netdev_tx_t hinic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
}
nr_sges = skb_shinfo(skb)->nr_frags + 1;
+ if (nr_sges > 17) {
+ u64_stats_update_begin(&txq->txq_stats.syncp);
+ txq->txq_stats.big_frags_pkts++;
+ u64_stats_update_end(&txq->txq_stats.syncp);
+ }
+
if (nr_sges > txq->max_sges) {
netdev_err(netdev, "Too many Tx sges\n");
goto skb_error;
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_tx.h b/drivers/net/ethernet/huawei/hinic/hinic_tx.h
index 1fa55dce5aa7..f1ee0376dc88 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_tx.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_tx.h
@@ -30,6 +30,7 @@ struct hinic_txq_stats {
u64 tx_busy;
u64 tx_wake;
u64 tx_dropped;
+ u64 big_frags_pkts;
struct u64_stats_sync syncp;
};
--
2.17.1
^ permalink raw reply related
* [PATCH v7 0/6] Add support for Orange Pi 3
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Ondrej Jirman, David Airlie, Daniel Vetter, Mark Rutland,
Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, David S. Miller,
Maxime Coquelin, dri-devel, devicetree, linux-arm-kernel,
linux-kernel, netdev, linux-stm32
From: Ondrej Jirman <megous@megous.com>
This series implements support for Xunlong Orange Pi 3 board.
- ethernet support (patches 1-3)
- HDMI support (patches 4-6)
For some people, ethernet doesn't work after reboot (but works on cold
boot), when the stmmac driver is built into the kernel. It works when
the driver is built as a module. It's either some timing issue, or power
supply issue or a combination of both. Module build induces a power
cycling of the phy.
I encourage people with this issue, to build the driver into the kernel,
and try to alter the reset timings for the phy in DTS or
startup-delay-us and report the findings.
Please take a look.
thank you and regards,
Ondrej Jirman
Changes in v7:
- dropped stored reference to connector_pdev as suggested by Jernej
- added forgotten dt-bindings reviewed-by tag
Changes in v6:
- added dt-bindings reviewed-by tag
- fix wording in stmmac commit (as suggested by Sergei)
Changes in v5:
- dropped already applied patches (pinctrl patches, mmc1 pinconf patch)
- rename GMAC-3V3 -> GMAC-3V to match the schematic (Jagan)
- changed hdmi-connector's ddc-supply property to ddc-en-gpios
(Rob Herring)
Changes in v4:
- fix checkpatch warnings/style issues
- use enum in struct sunxi_desc_function for io_bias_cfg_variant
- collected acked-by's
- fix compile error in drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c:156
caused by missing conversion from has_io_bias_cfg struct member
(I've kept the acked-by, because it's a trivial change, but feel free
to object.) (reported by Martin A. on github)
I did not have A80 pinctrl enabled for some reason, so I did not catch
this sooner.
- dropped brcm firmware patch (was already applied)
- dropped the wifi dts patch (will re-send after H6 RTC gets merged,
along with bluetooth support, in a separate series)
Changes in v3:
- dropped already applied patches
- changed pinctrl I/O bias selection constants to enum and renamed
- added /omit-if-no-ref/ to mmc1_pins
- made mmc1_pins default pinconf for mmc1 in H6 dtsi
- move ddc-supply to HDMI connector node, updated patch descriptions,
changed dt-bindings docs
Changes in v2:
- added dt-bindings documentation for the board's compatible string
(suggested by Clement)
- addressed checkpatch warnings and code formatting issues (on Maxime's
suggestions)
- stmmac: dropped useless parenthesis, reworded description of the patch
(suggested by Sergei)
- drop useles dev_info() about the selected io bias voltage
- docummented io voltage bias selection variant macros
- wifi: marked WiFi DTS patch and realted mmc1_pins as "DO NOT MERGE",
because wifi depends on H6 RTC support that's not merged yet (suggested
by Clement)
- added missing signed-of-bys
- changed &usb2otg dr_mode to otg, and added a note about VBUS
- improved wording of HDMI driver's DDC power supply patch
Icenowy Zheng (2):
net: stmmac: sun8i: add support for Allwinner H6 EMAC
net: stmmac: sun8i: force select external PHY when no internal one
Ondrej Jirman (4):
arm64: dts: allwinner: orange-pi-3: Enable ethernet
dt-bindings: display: hdmi-connector: Support DDC bus enable
drm: sun4i: Add support for enabling DDC I2C bus to sun8i_dw_hdmi glue
arm64: dts: allwinner: orange-pi-3: Enable HDMI output
.../display/connector/hdmi-connector.txt | 1 +
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 70 +++++++++++++++++++
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 54 ++++++++++++--
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 21 ++++++
5 files changed, 144 insertions(+), 4 deletions(-)
--
2.22.0
^ permalink raw reply
* Re: [Qemu-devel] [PATCH v3 05/50] docs/devel: add plugins.rst design document
From: Alex Bennée @ 2019-06-20 13:38 UTC (permalink / raw)
To: Pranith Kumar; +Cc: qemu-devel
In-Reply-To: <CADYwmhHjfqDi_vXWnp_z9UUr2Lxvw6F8op3KJQqvU3Wog43f_Q@mail.gmail.com>
Pranith Kumar <bobby.prani@gmail.com> writes:
<snip>
>> +
>> +Plugin Life cycle
>> +=================
>> +
>> +First the plugin is loaded and the public qemu_plugin_install function
>> +is called. The plugin with then register callbacks for various plugin
>
> s/with/will/
>
>> +events. Generally at least the atexit_cb is registered so the plugin
>> +can dump its information at the end of a run.
>
> Is that a hard requirement?
Not really although for a lot of plugins it is a natural point to dump
the results of the experiment.
<snip>
>> +
>> +As a result registering/unregistering callbacks is "slow", since it
>> +takes a lock. But this is very infrequent; we want performance when
>> +calling (or not calling) callbacks, not when registering them. Using
>> +RCU is great for this.
>> +
>> +We support the uninstallation of a plugin at any time (e.g. from plugin
>> +callbacks). This means some callbacks might still be called after the uninstall
>> +function returns. The plugin isn't completely uninstalled until the
>> +safe work has executed while all vCPUs are quiescent.
>
> Isn't this when the atexit callback is invoked? Might add that to make
> it clearer.
No we can uninstall at any time, I've amended to:
We support the uninstallation of a plugin at any time (e.g. from
plugin callbacks). This allows plugins to remove themselves if they no
longer want to instrument the code. This operation is asynchronous
which means callbacks may still occur after the uninstall operation is
requested. The plugin isn't completely uninstalled until the safe work
has executed while all vCPUs are quiescent.
--
Alex Bennée
^ permalink raw reply
* [PATCH v7 3/6] arm64: dts: allwinner: orange-pi-3: Enable ethernet
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Ondrej Jirman, David Airlie, Daniel Vetter, Mark Rutland,
Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, David S. Miller,
Maxime Coquelin, dri-devel, devicetree, linux-arm-kernel,
linux-kernel, netdev, linux-stm32
In-Reply-To: <20190620134748.17866-1-megous@megous.com>
From: Ondrej Jirman <megous@megous.com>
Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
to the phy datasheet, both regulators need to be enabled at the same time,
but we can only specify a single phy-supply in the DT.
This can be achieved by making one regulator depedning on the other via
vin-supply. While it's not a technically correct description of the
hardware, it achieves the purpose.
All values of RX/TX delay were tested exhaustively and a middle one of the
working values was chosen.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..2c6807b74ff6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -15,6 +15,7 @@
aliases {
serial0 = &uart0;
+ ethernet0 = &emac;
};
chosen {
@@ -44,6 +45,27 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
+
+ /*
+ * The board uses 2.5V RGMII signalling. Power sequence to enable
+ * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
+ * at the same time and to wait 100ms.
+ */
+ reg_gmac_2v5: gmac-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+
+ /* The real parent of gmac-2v5 is reg_vcc5v, but we need to
+ * enable two regulators to power the phy. This is one way
+ * to achieve that.
+ */
+ vin-supply = <®_aldo2>; /* GMAC-3V */
+ };
};
&cpu0 {
@@ -58,6 +80,28 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <®_gmac_2v5>;
+ allwinner,rx-delay-ps = <1500>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+ reset-assert-us = <15000>;
+ reset-deassert-us = <40000>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
--
2.22.0
^ permalink raw reply related
* [Buildroot] [PATCH] package/zip: adjust the version to 3.0
From: Thomas Petazzoni @ 2019-06-20 13:48 UTC (permalink / raw)
To: buildroot
According to the project homepage at
http://infozip.sourceforge.net/Zip.html, the version is really named
3.0. This is also how it's called inside the zip30.ann file in the
source code, which says "We have posted Zip 3.0, July 5th 2008".
So the fact that the tarball is named zip30.tgz is just because
upstream wanted to avoid having two dots (perhaps by habit of the old
DOS 8.3 file name limitation ?).
The version is also named "3.0" in the SourceForge RSS at [0] that
release-monitoring.org is using for this package [1]. Therefore, by
using "3.0" as the version, we will match the version known by
release-monitoring.org.
Of course the tarball name is still zip30.tgz so we tweak the
ZIP_VERSION value appropriately.
[0] https://sourceforge.net/projects/infozip/rss?path=/
[1] https://release-monitoring.org/project/10080/
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
package/zip/zip.mk | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/package/zip/zip.mk b/package/zip/zip.mk
index 0bd3d3c11f..ca52c74fb1 100644
--- a/package/zip/zip.mk
+++ b/package/zip/zip.mk
@@ -4,8 +4,9 @@
#
################################################################################
-ZIP_VERSION = 30
-ZIP_SOURCE = zip$(ZIP_VERSION).tgz
+ZIP_VERSION = 3.0
+# The version is really 3.0, but the tarball is named zip30.tgz
+ZIP_SOURCE = zip$(subst .,,$(ZIP_VERSION)).tgz
ZIP_SITE = ftp://ftp.info-zip.org/pub/infozip/src
ZIP_LICENSE = Info-ZIP
ZIP_LICENSE_FILES = LICENSE
--
2.21.0
^ permalink raw reply related
* [PATCH v7 5/6] drm: sun4i: Add support for enabling DDC I2C bus to sun8i_dw_hdmi glue
From: megous @ 2019-06-20 13:47 UTC (permalink / raw)
To: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Jernej Škrabec
Cc: Ondrej Jirman, David Airlie, Daniel Vetter, Mark Rutland,
Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, David S. Miller,
Maxime Coquelin, dri-devel, devicetree, linux-arm-kernel,
linux-kernel, netdev, linux-stm32
In-Reply-To: <20190620134748.17866-1-megous@megous.com>
From: Ondrej Jirman <megous@megous.com>
Orange Pi 3 board requires enabling a voltage shifting circuit via GPIO
for the DDC bus to be usable.
Add support for hdmi-connector node's optional ddc-en-gpios property to
support this use case.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 54 +++++++++++++++++++++++++--
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +
2 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index 39d8509d96a0..6733bfc9c2d6 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -98,10 +98,34 @@ static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm,
return crtcs;
}
+static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev,
+ struct platform_device **pdev_out)
+{
+ struct platform_device *pdev;
+ struct device_node *remote;
+
+ remote = of_graph_get_remote_node(dev->of_node, 1, -1);
+ if (!remote)
+ return -ENODEV;
+
+ if (!of_device_is_compatible(remote, "hdmi-connector")) {
+ of_node_put(remote);
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(remote);
+ of_node_put(remote);
+ if (!pdev)
+ return -ENODEV;
+
+ *pdev_out = pdev;
+ return 0;
+}
+
static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
void *data)
{
- struct platform_device *pdev = to_platform_device(dev);
+ struct platform_device *pdev = to_platform_device(dev), *connector_pdev;
struct dw_hdmi_plat_data *plat_data;
struct drm_device *drm = data;
struct device_node *phy_node;
@@ -151,16 +175,30 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
return PTR_ERR(hdmi->regulator);
}
+ ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev);
+ if (!ret) {
+ hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev,
+ "ddc-en", GPIOD_OUT_HIGH);
+ platform_device_put(connector_pdev);
+
+ if (IS_ERR(hdmi->ddc_en)) {
+ dev_err(dev, "Couldn't get ddc-en gpio\n");
+ return PTR_ERR(hdmi->ddc_en);
+ }
+ }
+
ret = regulator_enable(hdmi->regulator);
if (ret) {
dev_err(dev, "Failed to enable regulator\n");
- return ret;
+ goto err_unref_ddc_en;
}
+ gpiod_set_value(hdmi->ddc_en, 1);
+
ret = reset_control_deassert(hdmi->rst_ctrl);
if (ret) {
dev_err(dev, "Could not deassert ctrl reset control\n");
- goto err_disable_regulator;
+ goto err_disable_ddc_en;
}
ret = clk_prepare_enable(hdmi->clk_tmds);
@@ -213,8 +251,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
clk_disable_unprepare(hdmi->clk_tmds);
err_assert_ctrl_reset:
reset_control_assert(hdmi->rst_ctrl);
-err_disable_regulator:
+err_disable_ddc_en:
+ gpiod_set_value(hdmi->ddc_en, 0);
regulator_disable(hdmi->regulator);
+err_unref_ddc_en:
+ if (hdmi->ddc_en)
+ gpiod_put(hdmi->ddc_en);
return ret;
}
@@ -228,7 +270,11 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
sun8i_hdmi_phy_remove(hdmi);
clk_disable_unprepare(hdmi->clk_tmds);
reset_control_assert(hdmi->rst_ctrl);
+ gpiod_set_value(hdmi->ddc_en, 0);
regulator_disable(hdmi->regulator);
+
+ if (hdmi->ddc_en)
+ gpiod_put(hdmi->ddc_en);
}
static const struct component_ops sun8i_dw_hdmi_ops = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index 720c5aa8adc1..d707c9171824 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -9,6 +9,7 @@
#include <drm/bridge/dw_hdmi.h>
#include <drm/drm_encoder.h>
#include <linux/clk.h>
+#include <linux/gpio/consumer.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -190,6 +191,7 @@ struct sun8i_dw_hdmi {
struct regulator *regulator;
const struct sun8i_dw_hdmi_quirks *quirks;
struct reset_control *rst_ctrl;
+ struct gpio_desc *ddc_en;
};
static inline struct sun8i_dw_hdmi *
--
2.22.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.