* [PATCH] arm64: dts: imx: Add Beacon i.mx8mm development kit
From: Adam Ford @ 2020-02-20 12:02 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Fabio Estevam, Adam Ford, Sascha Hauer, aford, open list,
Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Shawn Guo
Beacon Embeddedworks is launching a development kit based on the
i.MX8M Mini SoC. The kit consists of a System on Module (SOM)
+ baseboard. The SOM has the SoC, eMMC, and Ethernet. The baseboard
has an wm8962 audio CODEC, a single USB OTG, and three USB host ports.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/arch/arm64/boot/dts/freescale/beacon-imx8mm-baseboard.dtsi b/arch/arm64/boot/dts/freescale/beacon-imx8mm-baseboard.dtsi
new file mode 100644
index 000000000000..6f6a3e8ebb91
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/beacon-imx8mm-baseboard.dtsi
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "gen_led0";
+ gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
+ default-state = "none";
+ };
+
+ led1 {
+ label = "gen_led1";
+ gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
+ default-state = "none";
+ };
+
+ led2 {
+ label = "gen_led2";
+ gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
+ default-state = "none";
+ };
+
+ led3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led3>;
+ label = "heartbeat";
+ gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_audio: regulator-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_aud";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ audio-cpu = <&sai3>;
+ audio-codec = <&wm8962>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC";
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_espi2>;
+ status = "okay";
+ cs-gpios = <&gpio5 9 0>;
+
+ at25@0 {
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ spi-cpha;
+ spi-cpol;
+
+ pagesize = <32>;
+ size = <2048>;
+ address-width = <16>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c4 {
+
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pca6416_0: gpio@20 {
+ compatible = "nxp,pcal6416";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6414>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pca6416_1: gpio@21 {
+ compatible = "nxp,pcal6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ wm8962: audio-codec@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
+ clock-names = "xclk";
+ DCVDD-supply = <®_audio>;
+ DBVDD-supply = <®_audio>;
+ AVDD-supply = <®_audio>;
+ CPVDD-supply = <®_audio>;
+ MICVDD-supply = <®_audio>;
+ PLLVDD-supply = <®_audio>;
+ SPKVDD1-supply = <®_audio>;
+ SPKVDD2-supply = <®_audio>;
+ gpio-cfg = <
+ 0x0000 /* 0:Default */
+ 0x0000 /* 1:Default */
+ 0x0000 /* 2:FN_DMICCLK */
+ 0x0000 /* 3:Default */
+ 0x0000 /* 4:FN_DMICCDAT */
+ 0x0000 /* 5:Default */
+ >;
+ };
+};
+
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart2 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_espi2: espi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
+ >;
+ };
+
+ pinctrl_led3: led3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
+ >;
+ };
+
+ pinctrl_pcal6414: pcal6414-gpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
+ MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/freescale/beacon-imx8mm-kit.dts b/arch/arm64/boot/dts/freescale/beacon-imx8mm-kit.dts
new file mode 100644
index 000000000000..417b15d345d5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/beacon-imx8mm-kit.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "beacon-imx8mm-som.dtsi"
+#include "beacon-imx8mm-baseboard.dtsi"
+
+/ {
+ model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit";
+ compatible = "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/beacon-imx8mm-som.dtsi b/arch/arm64/boot/dts/freescale/beacon-imx8mm-som.dtsi
new file mode 100644
index 000000000000..a2028322c2a3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/beacon-imx8mm-som.dtsi
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+ usdhc1_pwrseq: usdhc1_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_gpio>;
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ clocks = <&osc_32k>;
+ clock-names = "ext_clock";
+ post-power-on-delay-ms = <80>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "BUCK3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ pagesize = <32>;
+ read-only; /* Manufacturing EEPROM programmed at factory */
+ reg = <0x50>;
+ };
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ clocks = <&osc_32k>;
+ clock-names = "extclk";
+ };
+};
+
+&usdhc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ non-removable;
+ cap-power-off-card;
+ pm-ignore-notify;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wlan>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
+ MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
+ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1grpgpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+
+ pinctrl_wlan: wlangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
+ >;
+ };
+};
--
2.25.0
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^ permalink raw reply related
* spi_flash_read issue
From: Fabio Estevam @ 2020-02-20 12:02 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1582193426408-0.post@n7.nabble.com>
On Thu, Feb 20, 2020 at 8:57 AM dvo <dan.vo.ict@jvn.edu.vn> wrote:
>
> Hello,
>
> I encounter an issue with spi_flash_read function. I'd copy uboot from SPI
> Flash to DDRAM. If I use the function once. It works OK. If I use the
> function is more than 1 time, then it doesn't work properly.
> Here is the procedure of what I did:
>
> uboot version: U-Boot 2019.07-00013-g6107815c9c
Could you please test mainline U-Boot instead?
Which SoC do you use?
^ permalink raw reply
* Re: [PATCH v1 0/2] perf report: Support annotation of code without symbols
From: Jin, Yao @ 2020-02-20 12:03 UTC (permalink / raw)
To: Jiri Olsa
Cc: acme, jolsa, peterz, mingo, alexander.shishkin, Linux-kernel, ak,
kan.liang, yao.jin
In-Reply-To: <20200220115629.GC565976@krava>
On 2/20/2020 7:56 PM, Jiri Olsa wrote:
> On Thu, Feb 20, 2020 at 08:59:00AM +0800, Jin Yao wrote:
>> For perf report on stripped binaries it is currently impossible to do
>> annotation. The annotation state is all tied to symbols, but there are
>> either no symbols, or symbols are not covering all the code.
>>
>> We should support the annotation functionality even without symbols.
>>
>> The first patch uses al_addr to print because it's easy to dump
>> the instructions from this address in binary for branch mode.
>>
>> The second patch supports the annotation on stripped binary.
>>
>> Jin Yao (2):
>> perf util: Print al_addr when symbol is not found
>> perf annotate: Support interactive annotation of code without symbols
>
> looks good, but I'm getting crash when annotating unresolved kernel address:
>
> jirka
>
>
Thanks for reporting the issue.
I guess you are trying the "0xffffffff81c00ae7", let me try to reproduce
this issue.
Thanks
Jin Yao
> Samples: 14 of event 'cycles:u', Event count (approx.): 1822321
> Overhead Command Shared Object Symbol
> 26.86% ls libc-2.30.so [.] __strcoll_l ▒
> 17.03% ls ls [.] 0x0000000000008968 ▒
> 13.10% ls [unknown] [k] 0xffffffff81c00ae7 ▒
> 13.02% ls ld-2.30.so [.] _dl_cache_libcmp ▒
> 12.84% ls libc-2.30.so [.] _int_malloc ▒
> 11.94% ls libc-2.30.so [.] __memcpy_chk ▒
> 5.21% ls ld-2.30.so [.] __GI___tunables_init ▒
> ▒
> Program received signal SIGSEGV, Segmentation fault. ▒
> add_annotate_opt (browser=0xec34a0, act=0x7fffffffabf0, optstr=0x7fffffffab70, ms=0xdbdb60, addr=18446744071591430887) at ui/browsers/hists.c:2500 ▒
> 2500 if (ms->map->dso->annotate_warned) ▒
> Missing separate debuginfos, use: dnf debuginfo-install brotli-1.0.7-6.fc31.x86_64 bzip2-libs-1.0.8-1.fc31.x86_64 cyrus-sasl-lib-2.1.27-2.fc31.x86_64 elfutils-debuginfod-client-0.178-7.fc31.x86_64 elfutils-libelf-0.178-7.fc31.x86_64 elfutils-libs-0.178-7.fc31.x86_64 glib2-2.62.5-1.fc31.x86_64 keyutils-libs-1.6-3.fc31.x86_64 krb5-libs-1.17-46.fc31.x86_64 libbabeltrace-1.5.7-2.fc31.x86_64 libcap-2.26-6.fc31.x86_64 libcom_err-1.45.5-1.fc31.x86_64 libcurl-7.66.0-1.fc31.x86_64 libgcc-9.2.1-1.fc31.x86_64 libidn2-2.3.0-1.fc31.x86_64 libnghttp2-1.40.0-1.fc31.x86_64 libpsl-0.21.0-2.fc31.x86_64 libselinux-2.9-5.fc31.x86_64 libssh-0.9.3-1.fc31.x86_64 libunwind-1.3.1-5.fc31.x86_64 libuuid-2.34-4.fc31.x86_64 libxcrypt-4.4.14-1.fc31.x86_64 libzstd-1.4.4-1.fc31.x86_64 openldap-2.4.47-3.fc31.x86_64 openssl-libs-1.1.1d-2.fc31.x86_64 pcre-8.43-3.fc31.x86_64 pcre2-10.34-6.fc31.x86_64 perl-libs-5.30.1-449.fc31.x86_64 popt-1.16-18.fc31.x86_64 python2-libs-2.7.17-1.fc31.x86_64 slang-2.3.2-6.fc31.x86_64 xz-libs-5.2.4-6.fc31.x86_64 zlib-1.2.11-20.fc31.x86_64 ▒
> (gdb) bt ▒
> #0 add_annotate_opt (browser=0xec34a0, act=0x7fffffffabf0, optstr=0x7fffffffab70, ms=0xdbdb60, addr=18446744071591430887) at ui/browsers/hists.c:2500 ▒
> #1 0x000000000061caf9 in perf_evsel__hists_browse (evsel=0xc58860, nr_events=1, helpline=0xef69f0 "Tip: Show current config key-value pairs: perf config --list", left_exits=false, hbt=0x0, min_pcnt=0, ▒
> env=0xc5c7b0, warn_lost_event=true, annotation_opts=0x7fffffffb518) at ui/browsers/hists.c:3265 ▒
> #2 0x000000000061dbc2 in perf_evlist__tui_browse_hists (evlist=0xc55ed0, help=0xef69f0 "Tip: Show current config key-value pairs: perf config --list", hbt=0x0, min_pcnt=0, env=0xc5c7b0, warn_lost_event=true, ▒
> annotation_opts=0x7fffffffb518) at ui/browsers/hists.c:3569 ▒
> #3 0x00000000004511e4 in report__browse_hists (rep=0x7fffffffb380) at builtin-report.c:630 ▒
> #4 0x00000000004521db in __cmd_report (rep=0x7fffffffb380) at builtin-report.c:975 ▒
> #5 0x000000000045444a in cmd_report (argc=0, argv=0x7fffffffd820) at builtin-report.c:1540 ▒
> #6 0x00000000004e384a in run_builtin (p=0xa5b370 <commands+240>, argc=1, argv=0x7fffffffd820) at perf.c:312 ▒
> #7 0x00000000004e3ab7 in handle_internal_command (argc=1, argv=0x7fffffffd820) at perf.c:364 ▒
> #8 0x00000000004e3bfe in run_argv (argcp=0x7fffffffd67c, argv=0x7fffffffd670) at perf.c:408 ▒
> #9 0x00000000004e3fca in main (argc=1, argv=0x7fffffffd820) at perf.c:538 ▒
> (gdb) ▒
>
>
>
>
^ permalink raw reply
* [Xen-devel] [PATCH] rwlock: allow recursive read locking when already locked in write mode
From: Roger Pau Monne @ 2020-02-20 12:02 UTC (permalink / raw)
To: xen-devel
Cc: Jürgen Groß, Stefano Stabellini, Julien Grall, Wei Liu,
Konrad Rzeszutek Wilk, George Dunlap, Andrew Cooper, Ian Jackson,
Jan Beulich, Roger Pau Monne
Allow a CPU already holding the lock in write mode to also lock it in
read mode. There's no harm in allowing read locking a rwlock that's
already owned by the caller (ie: CPU) in write mode. Allowing such
accesses is required at least for the CPU maps use-case.
In order to do this reserve 12bits of the lock, this allows to support
up to 4096 CPUs. Also reduce the write lock mask to 2 bits: one to
signal there are pending writers waiting on the lock and the other to
signal the lock is owned in write mode.
This reduces the maximum number of concurrent readers from 16777216 to
262144, I think this should still be enough, or else the lock field
can be expanded from 32 to 64bits if all architectures support atomic
operations on 64bit integers.
Fixes: 5872c83b42c608 ('smp: convert the cpu maps lock into a rw lock')
Reported-by: Jan Beulich <jbeulich@suse.com>
Reported-by: Jürgen Groß <jgross@suse.com>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
I've done some testing and at least the CPU down case is fixed now.
Posting early in order to get feedback on the approach taken.
---
xen/common/rwlock.c | 4 ++--
xen/include/xen/rwlock.h | 47 ++++++++++++++++++++++++++--------------
2 files changed, 33 insertions(+), 18 deletions(-)
diff --git a/xen/common/rwlock.c b/xen/common/rwlock.c
index d568bbf6de..dadab372b5 100644
--- a/xen/common/rwlock.c
+++ b/xen/common/rwlock.c
@@ -69,7 +69,7 @@ void queue_write_lock_slowpath(rwlock_t *lock)
/* Try to acquire the lock directly if no reader is present. */
if ( !atomic_read(&lock->cnts) &&
- (atomic_cmpxchg(&lock->cnts, 0, _QW_LOCKED) == 0) )
+ (atomic_cmpxchg(&lock->cnts, 0, _write_lock_val()) == 0) )
goto unlock;
/*
@@ -93,7 +93,7 @@ void queue_write_lock_slowpath(rwlock_t *lock)
cnts = atomic_read(&lock->cnts);
if ( (cnts == _QW_WAITING) &&
(atomic_cmpxchg(&lock->cnts, _QW_WAITING,
- _QW_LOCKED) == _QW_WAITING) )
+ _write_lock_val()) == _QW_WAITING) )
break;
cpu_relax();
diff --git a/xen/include/xen/rwlock.h b/xen/include/xen/rwlock.h
index 3dfea1ac2a..b430ebd846 100644
--- a/xen/include/xen/rwlock.h
+++ b/xen/include/xen/rwlock.h
@@ -20,21 +20,30 @@ typedef struct {
#define DEFINE_RWLOCK(l) rwlock_t l = RW_LOCK_UNLOCKED
#define rwlock_init(l) (*(l) = (rwlock_t)RW_LOCK_UNLOCKED)
-/*
- * Writer states & reader shift and bias.
- *
- * Writer field is 8 bit to allow for potential optimisation, see
- * _write_unlock().
- */
-#define _QW_WAITING 1 /* A writer is waiting */
-#define _QW_LOCKED 0xff /* A writer holds the lock */
-#define _QW_WMASK 0xff /* Writer mask.*/
-#define _QR_SHIFT 8 /* Reader count shift */
+/* Writer states & reader shift and bias. */
+#define _QW_WAITING 1 /* A writer is waiting */
+#define _QW_LOCKED 3 /* A writer holds the lock */
+#define _QW_WMASK 3 /* Writer mask */
+#define _QW_CPUSHIFT 2 /* Writer CPU shift */
+#define _QW_CPUMASK 0x3ffc /* Writer CPU mask */
+#define _QR_SHIFT 14 /* Reader count shift */
#define _QR_BIAS (1U << _QR_SHIFT)
void queue_read_lock_slowpath(rwlock_t *lock);
void queue_write_lock_slowpath(rwlock_t *lock);
+static inline bool _is_write_locked_by_me(uint32_t cnts)
+{
+ BUILD_BUG_ON((_QW_CPUMASK >> _QW_CPUSHIFT) < NR_CPUS);
+ return (cnts & _QW_WMASK) == _QW_LOCKED &&
+ MASK_EXTR(cnts, _QW_CPUMASK) == smp_processor_id();
+}
+
+static inline bool _can_read_lock(uint32_t cnts)
+{
+ return !(cnts & _QW_WMASK) || _is_write_locked_by_me(cnts);
+}
+
/*
* _read_trylock - try to acquire read lock of a queue rwlock.
* @lock : Pointer to queue rwlock structure.
@@ -45,10 +54,10 @@ static inline int _read_trylock(rwlock_t *lock)
u32 cnts;
cnts = atomic_read(&lock->cnts);
- if ( likely(!(cnts & _QW_WMASK)) )
+ if ( likely(_can_read_lock(cnts)) )
{
cnts = (u32)atomic_add_return(_QR_BIAS, &lock->cnts);
- if ( likely(!(cnts & _QW_WMASK)) )
+ if ( likely(_can_read_lock(cnts)) )
return 1;
atomic_sub(_QR_BIAS, &lock->cnts);
}
@@ -64,7 +73,7 @@ static inline void _read_lock(rwlock_t *lock)
u32 cnts;
cnts = atomic_add_return(_QR_BIAS, &lock->cnts);
- if ( likely(!(cnts & _QW_WMASK)) )
+ if ( likely(_can_read_lock(cnts)) )
return;
/* The slowpath will decrement the reader count, if necessary. */
@@ -115,6 +124,11 @@ static inline int _rw_is_locked(rwlock_t *lock)
return atomic_read(&lock->cnts);
}
+static inline uint32_t _write_lock_val(void)
+{
+ return _QW_LOCKED | MASK_INSR(smp_processor_id(), _QW_CPUMASK);
+}
+
/*
* queue_write_lock - acquire write lock of a queue rwlock.
* @lock : Pointer to queue rwlock structure.
@@ -122,7 +136,7 @@ static inline int _rw_is_locked(rwlock_t *lock)
static inline void _write_lock(rwlock_t *lock)
{
/* Optimize for the unfair lock case where the fair flag is 0. */
- if ( atomic_cmpxchg(&lock->cnts, 0, _QW_LOCKED) == 0 )
+ if ( atomic_cmpxchg(&lock->cnts, 0, _write_lock_val()) == 0 )
return;
queue_write_lock_slowpath(lock);
@@ -157,7 +171,7 @@ static inline int _write_trylock(rwlock_t *lock)
if ( unlikely(cnts) )
return 0;
- return likely(atomic_cmpxchg(&lock->cnts, 0, _QW_LOCKED) == 0);
+ return likely(atomic_cmpxchg(&lock->cnts, 0, _write_lock_val()) == 0);
}
static inline void _write_unlock(rwlock_t *lock)
@@ -166,7 +180,8 @@ static inline void _write_unlock(rwlock_t *lock)
* If the writer field is atomic, it can be cleared directly.
* Otherwise, an atomic subtraction will be used to clear it.
*/
- atomic_sub(_QW_LOCKED, &lock->cnts);
+ ASSERT(_is_write_locked_by_me(atomic_read(&lock->cnts)));
+ atomic_sub(_write_lock_val(), &lock->cnts);
}
static inline void _write_unlock_irq(rwlock_t *lock)
--
2.25.0
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related
* Re: [PATCH 3/5] arm64/vdso: Add time napespace page
From: Vincenzo Frascino @ 2020-02-20 12:03 UTC (permalink / raw)
To: Andrei Vagin
Cc: linux-arm-kernel, linux-kernel, Thomas Gleixner, Dmitry Safonov
In-Reply-To: <20200204175913.74901-4-avagin@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 7683 bytes --]
Hi Andrei,
On 04/02/2020 17:59, Andrei Vagin wrote:
> Allocate the time namespace page among VVAR pages. Provide
> __arch_get_timens_vdso_data() helper for VDSO code to get the
> code-relative position of VVARs on that special page.
>
> If a task belongs to a time namespace then the VVAR page which contains
> the system wide VDSO data is replaced with a namespace specific page
> which has the same layout as the VVAR page. That page has vdso_data->seq
> set to 1 to enforce the slow path and vdso_data->clock_mode set to
> VCLOCK_TIMENS to enforce the time namespace handling path.
>
> The extra check in the case that vdso_data->seq is odd, e.g. a concurrent
> update of the VDSO data is in progress, is not really affecting regular
> tasks which are not part of a time namespace as the task is spin waiting
> for the update to finish and vdso_data->seq to become even again.
>
> If a time namespace task hits that code path, it invokes the corresponding
> time getter function which retrieves the real VVAR page, reads host time
> and then adds the offset for the requested clock which is stored in the
> special VVAR page.
>
> Signed-off-by: Andrei Vagin <avagin@gmail.com>
> ---
> arch/arm64/Kconfig | 1 +
> .../arm64/include/asm/vdso/compat_gettimeofday.h | 11 +++++++++++
> arch/arm64/include/asm/vdso/gettimeofday.h | 8 ++++++++
> arch/arm64/kernel/vdso.c | 16 +++++++++++++---
> arch/arm64/kernel/vdso/vdso.lds.S | 3 ++-
> arch/arm64/kernel/vdso32/vdso.lds.S | 3 ++-
> include/vdso/datapage.h | 1 +
> 7 files changed, 38 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index e688dfad0b72..a671c2e36e5f 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -109,6 +109,7 @@ config ARM64
> select GENERIC_STRNLEN_USER
> select GENERIC_TIME_VSYSCALL
> select GENERIC_GETTIMEOFDAY
> + select GENERIC_VDSO_TIME_NS
> select HANDLE_DOMAIN_IRQ
> select HARDIRQS_SW_RESEND
> select HAVE_PCI
Could you please add the selection in a separate patch at the end of this series?
> diff --git a/arch/arm64/include/asm/vdso/compat_gettimeofday.h b/arch/arm64/include/asm/vdso/compat_gettimeofday.h
> index 537b1e695365..30a674f598c7 100644
> --- a/arch/arm64/include/asm/vdso/compat_gettimeofday.h
> +++ b/arch/arm64/include/asm/vdso/compat_gettimeofday.h
> @@ -161,6 +161,17 @@ static __always_inline const struct vdso_data *__arch_get_vdso_data(void)
> return ret;
> }
>
> +#ifdef CONFIG_TIME_NS
> +static __always_inline const struct vdso_data *__arch_get_timens_vdso_data(void)
> +{
> + const struct vdso_data *ret;
> +
> + asm volatile("mov %0, %1" : "=r"(ret) : "r"(_timens_data));
> +
> + return ret;
> +}
> +#endif
> +
> #endif /* !__ASSEMBLY__ */
>
> #endif /* __ASM_VDSO_GETTIMEOFDAY_H */
> diff --git a/arch/arm64/include/asm/vdso/gettimeofday.h b/arch/arm64/include/asm/vdso/gettimeofday.h
> index b08f476b72b4..aa38e80dfbc4 100644
> --- a/arch/arm64/include/asm/vdso/gettimeofday.h
> +++ b/arch/arm64/include/asm/vdso/gettimeofday.h
> @@ -98,6 +98,14 @@ const struct vdso_data *__arch_get_vdso_data(void)
> return _vdso_data;
> }
>
> +#ifdef CONFIG_TIME_NS
> +static __always_inline
> +const struct vdso_data *__arch_get_timens_vdso_data(void)
> +{
> + return _timens_data;
> +}
> +#endif
> +
> #endif /* !__ASSEMBLY__ */
>
> #endif /* __ASM_VDSO_GETTIMEOFDAY_H */
> diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
> index 5ef808ddf08c..bc93e26ae485 100644
> --- a/arch/arm64/kernel/vdso.c
> +++ b/arch/arm64/kernel/vdso.c
> @@ -46,6 +46,10 @@ enum arch_vdso_type {
> #define VDSO_TYPES (ARM64_VDSO + 1)
> #endif /* CONFIG_COMPAT_VDSO */
>
> +#define VVAR_DATA_PAGE_OFFSET 0
> +#define VVAR_TIMENS_PAGE_OFFSET 1
> +#define VVAR_NR_PAGES 2
> +
Maybe we could change this in an enumeration. Something like:
enum vvar_pages {
VVAR_DATA_PAGE_OFFSET = 0,
#ifdef CONFIG_TIME_NS
VVAR_TIMENS_PAGE_OFFSET = 1,
#endif /* CONFIG_TIME_NS */
VVAR_NR_PAGES = __VDSO_PAGES,
(look at the change suggested below for vdso.h)
};
> struct __vdso_abi {
> const char *name;
> const char *vdso_code_start;
> @@ -81,6 +85,12 @@ static union {
> } vdso_data_store __page_aligned_data;
> struct vdso_data *vdso_data = vdso_data_store.data;
>
> +
> +struct vdso_data *arch_get_vdso_data(void *vvar_page)
> +{
> + return (struct vdso_data *)(vvar_page);
> +}
> +
> static int __vdso_remap(enum arch_vdso_type arch_index,
> const struct vm_special_mapping *sm,
> struct vm_area_struct *new_vma)
> @@ -182,7 +192,7 @@ static int __setup_additional_pages(enum arch_vdso_type arch_index,
>
> vdso_text_len = vdso_lookup[arch_index].vdso_pages << PAGE_SHIFT;
> /* Be sure to map the data page */
> - vdso_mapping_len = vdso_text_len + PAGE_SIZE;
> + vdso_mapping_len = vdso_text_len + VVAR_NR_PAGES * PAGE_SIZE;
>
> vdso_base = get_unmapped_area(NULL, 0, vdso_mapping_len, 0, 0);
> if (IS_ERR_VALUE(vdso_base)) {
> @@ -190,13 +200,13 @@ static int __setup_additional_pages(enum arch_vdso_type arch_index,
> goto up_fail;
> }
>
> - ret = _install_special_mapping(mm, vdso_base, PAGE_SIZE,
> + ret = _install_special_mapping(mm, vdso_base, VVAR_NR_PAGES * PAGE_SIZE,
> VM_READ|VM_MAYREAD|VM_PFNMAP,
> vdso_lookup[arch_index].dm);
> if (IS_ERR(ret))
> goto up_fail;
>
> - vdso_base += PAGE_SIZE;
> + vdso_base += VVAR_NR_PAGES * PAGE_SIZE;
> mm->context.vdso = (void *)vdso_base;
> ret = _install_special_mapping(mm, vdso_base, vdso_text_len,
> VM_READ|VM_EXEC|
> diff --git a/arch/arm64/kernel/vdso/vdso.lds.S b/arch/arm64/kernel/vdso/vdso.lds.S
> index 7ad2d3a0cd48..a90b7d14e990 100644
> --- a/arch/arm64/kernel/vdso/vdso.lds.S
> +++ b/arch/arm64/kernel/vdso/vdso.lds.S
> @@ -17,7 +17,8 @@ OUTPUT_ARCH(aarch64)
>
> SECTIONS
> {
> - PROVIDE(_vdso_data = . - PAGE_SIZE);
> + PROVIDE(_vdso_data = . - 2 * PAGE_SIZE);
Maybe we could have some conditional definition on CONFIG_TIME_NS in vdso.h:
#ifdef CONFIG_TIME_NS
#define __VVAR_PAGES 2
#else
#define __VVAR_PAGES 1
#endif
and then here:
PROVIDE(_vdso_data = . - __VVAR_PAGES * PAGE_SIZE);
just to not forget what "2" stands for. What do you think?
> + PROVIDE(_timens_data = _vdso_data + PAGE_SIZE);
> . = VDSO_LBASE + SIZEOF_HEADERS;
>
> .hash : { *(.hash) } :text
> diff --git a/arch/arm64/kernel/vdso32/vdso.lds.S b/arch/arm64/kernel/vdso32/vdso.lds.S
> index a3944927eaeb..3e432b536e53 100644
> --- a/arch/arm64/kernel/vdso32/vdso.lds.S
> +++ b/arch/arm64/kernel/vdso32/vdso.lds.S
> @@ -17,7 +17,8 @@ OUTPUT_ARCH(arm)
>
> SECTIONS
> {
> - PROVIDE_HIDDEN(_vdso_data = . - PAGE_SIZE);
> + PROVIDE_HIDDEN(_vdso_data = . - 2 * PAGE_SIZE);
Ditto.
> + PROVIDE_HIDDEN(_timens_data = _vdso_data + PAGE_SIZE);
> . = VDSO_LBASE + SIZEOF_HEADERS;
>
> .hash : { *(.hash) } :text
> diff --git a/include/vdso/datapage.h b/include/vdso/datapage.h
> index c5f347cc5e55..57eec6caca69 100644
> --- a/include/vdso/datapage.h
> +++ b/include/vdso/datapage.h
> @@ -100,6 +100,7 @@ struct vdso_data {
> * relocation, and this is what we need.
> */
> extern struct vdso_data _vdso_data[CS_BASES] __attribute__((visibility("hidden")));
> +extern struct vdso_data _timens_data[CS_BASES] __attribute__((visibility("hidden")));
>
> #endif /* !__ASSEMBLY__ */
>
>
--
Regards,
Vincenzo
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^ permalink raw reply
* Re: [PATCH 3/5] arm64/vdso: Add time napespace page
From: Vincenzo Frascino @ 2020-02-20 12:03 UTC (permalink / raw)
To: Andrei Vagin
Cc: Thomas Gleixner, linux-kernel, linux-arm-kernel, Dmitry Safonov
In-Reply-To: <20200204175913.74901-4-avagin@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 7683 bytes --]
Hi Andrei,
On 04/02/2020 17:59, Andrei Vagin wrote:
> Allocate the time namespace page among VVAR pages. Provide
> __arch_get_timens_vdso_data() helper for VDSO code to get the
> code-relative position of VVARs on that special page.
>
> If a task belongs to a time namespace then the VVAR page which contains
> the system wide VDSO data is replaced with a namespace specific page
> which has the same layout as the VVAR page. That page has vdso_data->seq
> set to 1 to enforce the slow path and vdso_data->clock_mode set to
> VCLOCK_TIMENS to enforce the time namespace handling path.
>
> The extra check in the case that vdso_data->seq is odd, e.g. a concurrent
> update of the VDSO data is in progress, is not really affecting regular
> tasks which are not part of a time namespace as the task is spin waiting
> for the update to finish and vdso_data->seq to become even again.
>
> If a time namespace task hits that code path, it invokes the corresponding
> time getter function which retrieves the real VVAR page, reads host time
> and then adds the offset for the requested clock which is stored in the
> special VVAR page.
>
> Signed-off-by: Andrei Vagin <avagin@gmail.com>
> ---
> arch/arm64/Kconfig | 1 +
> .../arm64/include/asm/vdso/compat_gettimeofday.h | 11 +++++++++++
> arch/arm64/include/asm/vdso/gettimeofday.h | 8 ++++++++
> arch/arm64/kernel/vdso.c | 16 +++++++++++++---
> arch/arm64/kernel/vdso/vdso.lds.S | 3 ++-
> arch/arm64/kernel/vdso32/vdso.lds.S | 3 ++-
> include/vdso/datapage.h | 1 +
> 7 files changed, 38 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index e688dfad0b72..a671c2e36e5f 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -109,6 +109,7 @@ config ARM64
> select GENERIC_STRNLEN_USER
> select GENERIC_TIME_VSYSCALL
> select GENERIC_GETTIMEOFDAY
> + select GENERIC_VDSO_TIME_NS
> select HANDLE_DOMAIN_IRQ
> select HARDIRQS_SW_RESEND
> select HAVE_PCI
Could you please add the selection in a separate patch at the end of this series?
> diff --git a/arch/arm64/include/asm/vdso/compat_gettimeofday.h b/arch/arm64/include/asm/vdso/compat_gettimeofday.h
> index 537b1e695365..30a674f598c7 100644
> --- a/arch/arm64/include/asm/vdso/compat_gettimeofday.h
> +++ b/arch/arm64/include/asm/vdso/compat_gettimeofday.h
> @@ -161,6 +161,17 @@ static __always_inline const struct vdso_data *__arch_get_vdso_data(void)
> return ret;
> }
>
> +#ifdef CONFIG_TIME_NS
> +static __always_inline const struct vdso_data *__arch_get_timens_vdso_data(void)
> +{
> + const struct vdso_data *ret;
> +
> + asm volatile("mov %0, %1" : "=r"(ret) : "r"(_timens_data));
> +
> + return ret;
> +}
> +#endif
> +
> #endif /* !__ASSEMBLY__ */
>
> #endif /* __ASM_VDSO_GETTIMEOFDAY_H */
> diff --git a/arch/arm64/include/asm/vdso/gettimeofday.h b/arch/arm64/include/asm/vdso/gettimeofday.h
> index b08f476b72b4..aa38e80dfbc4 100644
> --- a/arch/arm64/include/asm/vdso/gettimeofday.h
> +++ b/arch/arm64/include/asm/vdso/gettimeofday.h
> @@ -98,6 +98,14 @@ const struct vdso_data *__arch_get_vdso_data(void)
> return _vdso_data;
> }
>
> +#ifdef CONFIG_TIME_NS
> +static __always_inline
> +const struct vdso_data *__arch_get_timens_vdso_data(void)
> +{
> + return _timens_data;
> +}
> +#endif
> +
> #endif /* !__ASSEMBLY__ */
>
> #endif /* __ASM_VDSO_GETTIMEOFDAY_H */
> diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
> index 5ef808ddf08c..bc93e26ae485 100644
> --- a/arch/arm64/kernel/vdso.c
> +++ b/arch/arm64/kernel/vdso.c
> @@ -46,6 +46,10 @@ enum arch_vdso_type {
> #define VDSO_TYPES (ARM64_VDSO + 1)
> #endif /* CONFIG_COMPAT_VDSO */
>
> +#define VVAR_DATA_PAGE_OFFSET 0
> +#define VVAR_TIMENS_PAGE_OFFSET 1
> +#define VVAR_NR_PAGES 2
> +
Maybe we could change this in an enumeration. Something like:
enum vvar_pages {
VVAR_DATA_PAGE_OFFSET = 0,
#ifdef CONFIG_TIME_NS
VVAR_TIMENS_PAGE_OFFSET = 1,
#endif /* CONFIG_TIME_NS */
VVAR_NR_PAGES = __VDSO_PAGES,
(look at the change suggested below for vdso.h)
};
> struct __vdso_abi {
> const char *name;
> const char *vdso_code_start;
> @@ -81,6 +85,12 @@ static union {
> } vdso_data_store __page_aligned_data;
> struct vdso_data *vdso_data = vdso_data_store.data;
>
> +
> +struct vdso_data *arch_get_vdso_data(void *vvar_page)
> +{
> + return (struct vdso_data *)(vvar_page);
> +}
> +
> static int __vdso_remap(enum arch_vdso_type arch_index,
> const struct vm_special_mapping *sm,
> struct vm_area_struct *new_vma)
> @@ -182,7 +192,7 @@ static int __setup_additional_pages(enum arch_vdso_type arch_index,
>
> vdso_text_len = vdso_lookup[arch_index].vdso_pages << PAGE_SHIFT;
> /* Be sure to map the data page */
> - vdso_mapping_len = vdso_text_len + PAGE_SIZE;
> + vdso_mapping_len = vdso_text_len + VVAR_NR_PAGES * PAGE_SIZE;
>
> vdso_base = get_unmapped_area(NULL, 0, vdso_mapping_len, 0, 0);
> if (IS_ERR_VALUE(vdso_base)) {
> @@ -190,13 +200,13 @@ static int __setup_additional_pages(enum arch_vdso_type arch_index,
> goto up_fail;
> }
>
> - ret = _install_special_mapping(mm, vdso_base, PAGE_SIZE,
> + ret = _install_special_mapping(mm, vdso_base, VVAR_NR_PAGES * PAGE_SIZE,
> VM_READ|VM_MAYREAD|VM_PFNMAP,
> vdso_lookup[arch_index].dm);
> if (IS_ERR(ret))
> goto up_fail;
>
> - vdso_base += PAGE_SIZE;
> + vdso_base += VVAR_NR_PAGES * PAGE_SIZE;
> mm->context.vdso = (void *)vdso_base;
> ret = _install_special_mapping(mm, vdso_base, vdso_text_len,
> VM_READ|VM_EXEC|
> diff --git a/arch/arm64/kernel/vdso/vdso.lds.S b/arch/arm64/kernel/vdso/vdso.lds.S
> index 7ad2d3a0cd48..a90b7d14e990 100644
> --- a/arch/arm64/kernel/vdso/vdso.lds.S
> +++ b/arch/arm64/kernel/vdso/vdso.lds.S
> @@ -17,7 +17,8 @@ OUTPUT_ARCH(aarch64)
>
> SECTIONS
> {
> - PROVIDE(_vdso_data = . - PAGE_SIZE);
> + PROVIDE(_vdso_data = . - 2 * PAGE_SIZE);
Maybe we could have some conditional definition on CONFIG_TIME_NS in vdso.h:
#ifdef CONFIG_TIME_NS
#define __VVAR_PAGES 2
#else
#define __VVAR_PAGES 1
#endif
and then here:
PROVIDE(_vdso_data = . - __VVAR_PAGES * PAGE_SIZE);
just to not forget what "2" stands for. What do you think?
> + PROVIDE(_timens_data = _vdso_data + PAGE_SIZE);
> . = VDSO_LBASE + SIZEOF_HEADERS;
>
> .hash : { *(.hash) } :text
> diff --git a/arch/arm64/kernel/vdso32/vdso.lds.S b/arch/arm64/kernel/vdso32/vdso.lds.S
> index a3944927eaeb..3e432b536e53 100644
> --- a/arch/arm64/kernel/vdso32/vdso.lds.S
> +++ b/arch/arm64/kernel/vdso32/vdso.lds.S
> @@ -17,7 +17,8 @@ OUTPUT_ARCH(arm)
>
> SECTIONS
> {
> - PROVIDE_HIDDEN(_vdso_data = . - PAGE_SIZE);
> + PROVIDE_HIDDEN(_vdso_data = . - 2 * PAGE_SIZE);
Ditto.
> + PROVIDE_HIDDEN(_timens_data = _vdso_data + PAGE_SIZE);
> . = VDSO_LBASE + SIZEOF_HEADERS;
>
> .hash : { *(.hash) } :text
> diff --git a/include/vdso/datapage.h b/include/vdso/datapage.h
> index c5f347cc5e55..57eec6caca69 100644
> --- a/include/vdso/datapage.h
> +++ b/include/vdso/datapage.h
> @@ -100,6 +100,7 @@ struct vdso_data {
> * relocation, and this is what we need.
> */
> extern struct vdso_data _vdso_data[CS_BASES] __attribute__((visibility("hidden")));
> +extern struct vdso_data _timens_data[CS_BASES] __attribute__((visibility("hidden")));
>
> #endif /* !__ASSEMBLY__ */
>
>
--
Regards,
Vincenzo
[-- Attachment #2: pEpkey.asc --]
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^ permalink raw reply
* [PATCH v3 5/5] powerpc/irq: Use current_stack_pointer in do_IRQ()
From: Michael Ellerman @ 2020-02-20 11:51 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20200220115141.2707-1-mpe@ellerman.id.au>
From: Christophe Leroy <christophe.leroy@c-s.fr>
Until commit 7306e83ccf5c ("powerpc: Don't use CURRENT_THREAD_INFO to
find the stack"), the current stack base address was obtained by
calling current_thread_info(). That inline function was simply masking
out the value of r1.
In that commit, it was changed to using current_stack_pointer() (since
renamed current_stack_frame()), which is a heavier function as it is
an outline assembly function which cannot be inlined and which reads
the content of the stack at 0(r1).
Convert to using current_stack_pointer for geting r1 and masking out
its value to obtain the base address of the stack pointer as before.
Fixes: 7306e83ccf5c ("powerpc: Don't use CURRENT_THREAD_INFO to find the stack")
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/a37e699e7ab897742c07b6838a08af33bc9217e3.1579849665.git.christophe.leroy@c-s.fr
---
arch/powerpc/kernel/irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 46d5852fb00a..1bed18b7229e 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -648,7 +648,7 @@ void do_IRQ(struct pt_regs *regs)
void *cursp, *irqsp, *sirqsp;
/* Switch to the irq stack to handle this */
- cursp = (void *)(current_stack_frame() & ~(THREAD_SIZE - 1));
+ cursp = (void *)(current_stack_pointer & ~(THREAD_SIZE - 1));
irqsp = hardirq_ctx[raw_smp_processor_id()];
sirqsp = softirq_ctx[raw_smp_processor_id()];
--
2.21.1
v3: s/get_sp()/current_stack_pointer/
^ permalink raw reply related
* Re: [yocto] Bitbake returning non-zero due to sstate errors
From: Richard Purdie @ 2020-02-20 12:04 UTC (permalink / raw)
To: Paul Barker; +Cc: Yocto discussion list
In-Reply-To: <CAM9ZRVv2Xoq=GBjQOXT+VBunhYG3n_dCw7Bv6XECTdRhdvzg9w@mail.gmail.com>
On Thu, 2020-02-20 at 11:59 +0000, Paul Barker wrote:
> I'm now looking into this...
>
> In sstate_checkhashes() we mark sstate as available if
> fetcher.checkstatus() succeeds. Then at a later point
> sstate_setscene() calls sstate_installpkg() calls pstaging_fetch()
> calls fetcher.download() to actually get the sstate artifact. If the
> artifact is removed from the mirror between these two accesses (due
> to an sstate mirror clean up running in parallel to a build), or if
> there is an intermittent download failure we could see checkstatus()
> succeed then download() fail.
>
> I don't think we should ignore all setscene errors but in the
> specific case where it's the download step that fails I think that
> should be a warning. Or it could be an error by default with a
> variable we can set to turn it into a warning. Does that sound
> reasonable? If so I'll work up a patch.
Thinking about the code, I'm not sure how you're generically going to
tell the difference between a setscene task that fails as the file
disappeared compared to a setscene failure with another real error? :/
We could make all failed setscene tasks warnings but I think that
buries actual real errors.
This is probably why I've not changed the code before now.
Special exit code values? :/
I'm open to proposals.
I know we could put in some configuration option but in general I hate
these as it just means more test matrix combinations and more ways for
people to see different behaviours. They have a time/place but I'm not
sure its here.
Cheers,
Richard
^ permalink raw reply
* [PATCH] block: Prevent hung_check firing during long sync IO
From: Ming Lei @ 2020-02-20 12:05 UTC (permalink / raw)
To: Jens Axboe
Cc: linux-block, Ming Lei, Salman Qazi, Jesse Barnes, Bart Van Assche
submit_bio_wait() can be called from ioctl(BLKSECDISCARD), which
may take long time to complete, as Salman mentioned, 4K BLKSECDISCARD
takes up to 100 second on some devices. Also any block I/O operation
that occurs after the BLKSECDISCARD is submitted will also potentially
be affected by the hung task timeouts.
So prevent hung_check from firing by taking same approach used
in blk_execute_rq(), and the wake-up interval is set as half the
hung_check timer period, which keeps overhead low enough.
Cc: Salman Qazi <sqazi@google.com>
Cc: Jesse Barnes <jsbarnes@google.com>
Cc: Bart Van Assche <bvanassche@acm.org>
Link: https://lkml.org/lkml/2020/2/12/1193
Reported-by: Salman Qazi <sqazi@google.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
---
block/bio.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/block/bio.c b/block/bio.c
index 94d697217887..c9ce19a86de7 100644
--- a/block/bio.c
+++ b/block/bio.c
@@ -17,6 +17,7 @@
#include <linux/cgroup.h>
#include <linux/blk-cgroup.h>
#include <linux/highmem.h>
+#include <linux/sched/sysctl.h>
#include <trace/events/block.h>
#include "blk.h"
@@ -1019,12 +1020,19 @@ static void submit_bio_wait_endio(struct bio *bio)
int submit_bio_wait(struct bio *bio)
{
DECLARE_COMPLETION_ONSTACK_MAP(done, bio->bi_disk->lockdep_map);
+ unsigned long hang_check;
bio->bi_private = &done;
bio->bi_end_io = submit_bio_wait_endio;
bio->bi_opf |= REQ_SYNC;
submit_bio(bio);
- wait_for_completion_io(&done);
+
+ /* Prevent hang_check timer from firing at us during very long I/O */
+ hang_check = sysctl_hung_task_timeout_secs;
+ if (hang_check)
+ while (!wait_for_completion_io_timeout(&done, hang_check * (HZ/2)));
+ else
+ wait_for_completion_io(&done);
return blk_status_to_errno(bio->bi_status);
}
--
2.20.1
^ permalink raw reply related
* Re: [PATCH v4 2/4] gpiolib: use kref in gpio_desc
From: Srinivas Kandagatla @ 2020-02-20 12:05 UTC (permalink / raw)
To: Bartosz Golaszewski, Linus Walleij, Khouloud Touil,
Geert Uytterhoeven
Cc: linux-gpio, linux-kernel, Bartosz Golaszewski
In-Reply-To: <20200220100141.5905-3-brgl@bgdev.pl>
On 20/02/2020 10:01, Bartosz Golaszewski wrote:
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -2798,6 +2798,8 @@ static int gpiod_request_commit(struct gpio_desc *desc, const char *label)
> goto done;
> }
>
> + kref_init(&desc->ref);
> +
Should we not decrement refcount on the error path of this function?
--srini
> if (chip->request) {
> /* chip->request may sleep */
> spin_unlock_irqrestore(&gpio_lock, flags);
> @@ -2933,6 +2935,13 @@ void gpiod_free(struct gpio_desc *desc)
> }
> }
^ permalink raw reply
* Re: [PATCH] mm: Avoid data corruption on CoW fault into PFN-mapped VMA
From: Kirill A. Shutemov @ 2020-02-20 12:06 UTC (permalink / raw)
To: Andrew Morton
Cc: Dan Williams, Justin He, linux-mm, linux-kernel,
Kirill A. Shutemov, Jeff Moyer
In-Reply-To: <20200219132239.92a22479e4bff7ec73ae6bdb@linux-foundation.org>
On Wed, Feb 19, 2020 at 01:22:39PM -0800, Andrew Morton wrote:
> On Tue, 18 Feb 2020 18:41:51 +0300 "Kirill A. Shutemov" <kirill@shutemov.name> wrote:
>
> > Jeff Moyer has reported that one of xfstests triggers a warning when run
> > on DAX-enabled filesystem:
> >
> > WARNING: CPU: 76 PID: 51024 at mm/memory.c:2317 wp_page_copy+0xc40/0xd50
> > ...
> > wp_page_copy+0x98c/0xd50 (unreliable)
> > do_wp_page+0xd8/0xad0
> > __handle_mm_fault+0x748/0x1b90
> > handle_mm_fault+0x120/0x1f0
> > __do_page_fault+0x240/0xd70
> > do_page_fault+0x38/0xd0
> > handle_page_fault+0x10/0x30
> >
> > The warning happens on failed __copy_from_user_inatomic() which tries to
> > copy data into a CoW page.
> >
> > This happens because of race between MADV_DONTNEED and CoW page fault:
> >
> > CPU0 CPU1
> > handle_mm_fault()
> > do_wp_page()
> > wp_page_copy()
> > do_wp_page()
> > madvise(MADV_DONTNEED)
> > zap_page_range()
> > zap_pte_range()
> > ptep_get_and_clear_full()
> > <TLB flush>
> > __copy_from_user_inatomic()
> > sees empty PTE and fails
> > WARN_ON_ONCE(1)
> > clear_page()
> >
> > The solution is to re-try __copy_from_user_inatomic() under PTL after
> > checking that PTE is matches the orig_pte.
> >
> > The second copy attempt can still fail, like due to non-readable PTE,
> > but there's nothing reasonable we can do about, except clearing the CoW
> > page.
>
> You don't think this is worthy of a cc:stable?
Please, add it.
Although, if I read history correctly, it is 15 year old bug that nobody
noticed until we added WARN() there :/
--
Kirill A. Shutemov
^ permalink raw reply
* Re: [PATCH v3 22/22] x86/int3: Ensure that poke_int3_handler() is not sanitized
From: Peter Zijlstra @ 2020-02-20 12:06 UTC (permalink / raw)
To: Dmitry Vyukov
Cc: LKML, linux-arch, Steven Rostedt, Ingo Molnar, Joel Fernandes,
Greg Kroah-Hartman, Gustavo A. R. Silva, Thomas Gleixner,
Paul E. McKenney, Josh Triplett, Mathieu Desnoyers, Lai Jiangshan,
Andy Lutomirski, tony.luck, Frederic Weisbecker, Dan Carpenter,
Masami Hiramatsu, Andrey Ryabinin, kasan-dev
In-Reply-To: <CACT4Y+ZfxqMuiL_UF+rCku628hirJwp3t3vW5WGM8DWG6OaCeg@mail.gmail.com>
On Thu, Feb 20, 2020 at 11:37:32AM +0100, Dmitry Vyukov wrote:
> On Wed, Feb 19, 2020 at 6:20 PM Peter Zijlstra <peterz@infradead.org> wrote:
> >
> > On Wed, Feb 19, 2020 at 05:30:25PM +0100, Peter Zijlstra wrote:
> >
> > > By inlining everything in poke_int3_handler() (except bsearch :/) we can
> > > mark the whole function off limits to everything and call it a day. That
> > > simplicity has been the guiding principle so far.
> > >
> > > Alternatively we can provide an __always_inline variant of bsearch().
> >
> > This reduces the __no_sanitize usage to just the exception entry
> > (do_int3) and the critical function: poke_int3_handler().
> >
> > Is this more acceptible?
>
> Let's say it's more acceptable.
>
> Acked-by: Dmitry Vyukov <dvyukov@google.com>
Thanks, I'll go make it happen.
> I guess there is no ideal solution here.
>
> Just a straw man proposal: expected number of elements is large enough
> to make bsearch profitable, right? I see 1 is a common case, but the
> other case has multiple entries.
Latency was the consideration; the linear search would dramatically
increase the runtime of the exception.
The current limit is 256 entries and we're hitting that quite often.
(we can trivially increase, but nobody has been able to show significant
benefits for that -- as of yet)
^ permalink raw reply
* Re: [PATCH v1 0/2] perf report: Support annotation of code without symbols
From: Jiri Olsa @ 2020-02-20 12:06 UTC (permalink / raw)
To: Jin, Yao
Cc: acme, jolsa, peterz, mingo, alexander.shishkin, Linux-kernel, ak,
kan.liang, yao.jin
In-Reply-To: <ca3fa091-f407-51e2-d617-90a842b36295@linux.intel.com>
On Thu, Feb 20, 2020 at 08:03:18PM +0800, Jin, Yao wrote:
>
>
> On 2/20/2020 7:56 PM, Jiri Olsa wrote:
> > On Thu, Feb 20, 2020 at 08:59:00AM +0800, Jin Yao wrote:
> > > For perf report on stripped binaries it is currently impossible to do
> > > annotation. The annotation state is all tied to symbols, but there are
> > > either no symbols, or symbols are not covering all the code.
> > >
> > > We should support the annotation functionality even without symbols.
> > >
> > > The first patch uses al_addr to print because it's easy to dump
> > > the instructions from this address in binary for branch mode.
> > >
> > > The second patch supports the annotation on stripped binary.
> > >
> > > Jin Yao (2):
> > > perf util: Print al_addr when symbol is not found
> > > perf annotate: Support interactive annotation of code without symbols
> >
> > looks good, but I'm getting crash when annotating unresolved kernel address:
> >
> > jirka
> >
> >
>
> Thanks for reporting the issue.
>
> I guess you are trying the "0xffffffff81c00ae7", let me try to reproduce
> this issue.
yes, I also checked and it did not happen before
jirka
>
> Thanks
> Jin Yao
>
> > Samples: 14 of event 'cycles:u', Event count (approx.): 1822321
> > Overhead Command Shared Object Symbol
> > 26.86% ls libc-2.30.so [.] __strcoll_l ▒
> > 17.03% ls ls [.] 0x0000000000008968 ▒
> > 13.10% ls [unknown] [k] 0xffffffff81c00ae7 ▒
> > 13.02% ls ld-2.30.so [.] _dl_cache_libcmp ▒
> > 12.84% ls libc-2.30.so [.] _int_malloc ▒
> > 11.94% ls libc-2.30.so [.] __memcpy_chk ▒
> > 5.21% ls ld-2.30.so [.] __GI___tunables_init ▒
> > ▒
> > Program received signal SIGSEGV, Segmentation fault. ▒
> > add_annotate_opt (browser=0xec34a0, act=0x7fffffffabf0, optstr=0x7fffffffab70, ms=0xdbdb60, addr=18446744071591430887) at ui/browsers/hists.c:2500 ▒
> > 2500 if (ms->map->dso->annotate_warned) ▒
> > Missing separate debuginfos, use: dnf debuginfo-install brotli-1.0.7-6.fc31.x86_64 bzip2-libs-1.0.8-1.fc31.x86_64 cyrus-sasl-lib-2.1.27-2.fc31.x86_64 elfutils-debuginfod-client-0.178-7.fc31.x86_64 elfutils-libelf-0.178-7.fc31.x86_64 elfutils-libs-0.178-7.fc31.x86_64 glib2-2.62.5-1.fc31.x86_64 keyutils-libs-1.6-3.fc31.x86_64 krb5-libs-1.17-46.fc31.x86_64 libbabeltrace-1.5.7-2.fc31.x86_64 libcap-2.26-6.fc31.x86_64 libcom_err-1.45.5-1.fc31.x86_64 libcurl-7.66.0-1.fc31.x86_64 libgcc-9.2.1-1.fc31.x86_64 libidn2-2.3.0-1.fc31.x86_64 libnghttp2-1.40.0-1.fc31.x86_64 libpsl-0.21.0-2.fc31.x86_64 libselinux-2.9-5.fc31.x86_64 libssh-0.9.3-1.fc31.x86_64 libunwind-1.3.1-5.fc31.x86_64 libuuid-2.34-4.fc31.x86_64 libxcrypt-4.4.14-1.fc31.x86_64 libzstd-1.4.4-1.fc31.x86_64 openldap-2.4.47-3.fc31.x86_64 openssl-libs-1.1.1d-2.fc31.x86_64 pcre-8.43-3.fc31.x86_64 pcre2-10.34-6.fc31.x86_64 perl-libs-5.30.1-449.fc31.x86_64 popt-1.16-18.fc31.x86_64 python2-libs-2.7.17-1.fc31.x86_64 slang-2.3.2-6.fc31.x86_64 xz-libs-5.2.4-6.fc31.x86_64 zlib-1.2.11-20.fc31.x86_64 ▒
> > (gdb) bt ▒
> > #0 add_annotate_opt (browser=0xec34a0, act=0x7fffffffabf0, optstr=0x7fffffffab70, ms=0xdbdb60, addr=18446744071591430887) at ui/browsers/hists.c:2500 ▒
> > #1 0x000000000061caf9 in perf_evsel__hists_browse (evsel=0xc58860, nr_events=1, helpline=0xef69f0 "Tip: Show current config key-value pairs: perf config --list", left_exits=false, hbt=0x0, min_pcnt=0, ▒
> > env=0xc5c7b0, warn_lost_event=true, annotation_opts=0x7fffffffb518) at ui/browsers/hists.c:3265 ▒
> > #2 0x000000000061dbc2 in perf_evlist__tui_browse_hists (evlist=0xc55ed0, help=0xef69f0 "Tip: Show current config key-value pairs: perf config --list", hbt=0x0, min_pcnt=0, env=0xc5c7b0, warn_lost_event=true, ▒
> > annotation_opts=0x7fffffffb518) at ui/browsers/hists.c:3569 ▒
> > #3 0x00000000004511e4 in report__browse_hists (rep=0x7fffffffb380) at builtin-report.c:630 ▒
> > #4 0x00000000004521db in __cmd_report (rep=0x7fffffffb380) at builtin-report.c:975 ▒
> > #5 0x000000000045444a in cmd_report (argc=0, argv=0x7fffffffd820) at builtin-report.c:1540 ▒
> > #6 0x00000000004e384a in run_builtin (p=0xa5b370 <commands+240>, argc=1, argv=0x7fffffffd820) at perf.c:312 ▒
> > #7 0x00000000004e3ab7 in handle_internal_command (argc=1, argv=0x7fffffffd820) at perf.c:364 ▒
> > #8 0x00000000004e3bfe in run_argv (argcp=0x7fffffffd67c, argv=0x7fffffffd670) at perf.c:408 ▒
> > #9 0x00000000004e3fca in main (argc=1, argv=0x7fffffffd820) at perf.c:538 ▒
> > (gdb) ▒
> >
> >
> >
> >
^ permalink raw reply
* [PATCH] drm/panel: ld9040: add MODULE_DEVICE_TABLE with SPI IDs
From: Marek Szyprowski @ 2020-02-20 12:07 UTC (permalink / raw)
To: dri-devel, linux-samsung-soc
Cc: Marek Szyprowski, Bartlomiej Zolnierkiewicz, Thierry Reding,
Sam Ravnborg, Andrzej Hajda
In-Reply-To: <CGME20200220120711eucas1p1f3ac819081ece4847b17c10c005dfa42@eucas1p1.samsung.com>
Add proper MODULE_DEVICE_TABLE structure with SPI IDs to allow proper
creation of SPI modalias string and fix autoloading module for this driver.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/gpu/drm/panel/panel-samsung-ld9040.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-samsung-ld9040.c b/drivers/gpu/drm/panel/panel-samsung-ld9040.c
index 3c52f15f7a1c..9bb2e8c7934a 100644
--- a/drivers/gpu/drm/panel/panel-samsung-ld9040.c
+++ b/drivers/gpu/drm/panel/panel-samsung-ld9040.c
@@ -373,6 +373,12 @@ static const struct of_device_id ld9040_of_match[] = {
};
MODULE_DEVICE_TABLE(of, ld9040_of_match);
+static const struct spi_device_id ld9040_ids[] = {
+ { "ld9040", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(spi, ld9040_ids);
+
static struct spi_driver ld9040_driver = {
.probe = ld9040_probe,
.remove = ld9040_remove,
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v2 1/7] mm/hotplug: fix hot remove failure in SPARSEMEM|!VMEMMAP case
From: David Hildenbrand @ 2020-02-20 12:07 UTC (permalink / raw)
To: Baoquan He, linux-kernel
Cc: linux-mm, akpm, richardw.yang, osalvador, dan.j.williams, mhocko,
rppt, robin.murphy
In-Reply-To: <20200220043316.19668-2-bhe@redhat.com>
On 20.02.20 05:33, Baoquan He wrote:
> In section_deactivate(), pfn_to_page() doesn't work any more after
> ms->section_mem_map is resetting to NULL in SPARSEMEM|!VMEMMAP case.
> It caused hot remove failure:
>
> kernel BUG at mm/page_alloc.c:4806!
> invalid opcode: 0000 [#1] SMP PTI
> CPU: 3 PID: 8 Comm: kworker/u16:0 Tainted: G W 5.5.0-next-20200205+ #340
> Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 0.0.0 02/06/2015
> Workqueue: kacpi_hotplug acpi_hotplug_work_fn
> RIP: 0010:free_pages+0x85/0xa0
> Call Trace:
> __remove_pages+0x99/0xc0
> arch_remove_memory+0x23/0x4d
> try_remove_memory+0xc8/0x130
> ? walk_memory_blocks+0x72/0xa0
> __remove_memory+0xa/0x11
> acpi_memory_device_remove+0x72/0x100
> acpi_bus_trim+0x55/0x90
> acpi_device_hotplug+0x2eb/0x3d0
> acpi_hotplug_work_fn+0x1a/0x30
> process_one_work+0x1a7/0x370
> worker_thread+0x30/0x380
> ? flush_rcu_work+0x30/0x30
> kthread+0x112/0x130
> ? kthread_create_on_node+0x60/0x60
> ret_from_fork+0x35/0x40
>
> Let's move the ->section_mem_map resetting after depopulate_section_memmap()
> to fix it.
>
> Signed-off-by: Baoquan He <bhe@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply
* Re: [PATCH 4/5] arm64/vdso: Handle faults on timens page
From: Vincenzo Frascino @ 2020-02-20 12:07 UTC (permalink / raw)
To: Andrei Vagin
Cc: linux-arm-kernel, linux-kernel, Thomas Gleixner, Dmitry Safonov
In-Reply-To: <20200204175913.74901-5-avagin@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2998 bytes --]
Hi Andrei,
On 04/02/2020 17:59, Andrei Vagin wrote:
> If a task belongs to a time namespace then the VVAR page which contains
> the system wide VDSO data is replaced with a namespace specific page
> which has the same layout as the VVAR page.
>
> Signed-off-by: Andrei Vagin <avagin@gmail.com>
> ---
> arch/arm64/kernel/vdso.c | 55 +++++++++++++++++++++++++++++++++++++---
> 1 file changed, 51 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
> index bc93e26ae485..2e553468b183 100644
> --- a/arch/arm64/kernel/vdso.c
> +++ b/arch/arm64/kernel/vdso.c
> @@ -23,6 +23,7 @@
> #include <vdso/datapage.h>
> #include <vdso/helpers.h>
> #include <vdso/vsyscall.h>
> +#include <linux/time_namespace.h>
>
Nit: Could you please group this with the linux/ headers and keep the
alphabetical order.
> #include <asm/cacheflush.h>
> #include <asm/signal32.h>
> @@ -171,15 +172,61 @@ int vdso_join_timens(struct task_struct *task, struct time_namespace *ns)
> up_write(&mm->mmap_sem);
> return 0;
> }
> +
> +static struct page *find_timens_vvar_page(struct vm_area_struct *vma)
> +{
> + if (likely(vma->vm_mm == current->mm))
> + return current->nsproxy->time_ns->vvar_page;
> +
> + /*
> + * VM_PFNMAP | VM_IO protect .fault() handler from being called
> + * through interfaces like /proc/$pid/mem or
> + * process_vm_{readv,writev}() as long as there's no .access()
> + * in special_mapping_vmops().
> + * For more details check_vma_flags() and __access_remote_vm()
> + */
> +
> + WARN(1, "vvar_page accessed remotely");
> +
> + return NULL;
> +}
> +#else
> +static inline struct page *find_timens_vvar_page(struct vm_area_struct *vma)
> +{
> + return NULL;
> +}
> #endif
>
> static vm_fault_t vvar_fault(const struct vm_special_mapping *sm,
> struct vm_area_struct *vma, struct vm_fault *vmf)
> {
> - if (vmf->pgoff == 0)
> - return vmf_insert_pfn(vma, vmf->address,
> - sym_to_pfn(vdso_data));
> - return VM_FAULT_SIGBUS;
> + struct page *timens_page = find_timens_vvar_page(vma);
> + unsigned long pfn;
> +
> + switch (vmf->pgoff) {
> + case VVAR_DATA_PAGE_OFFSET:
> + if (timens_page)
> + pfn = page_to_pfn(timens_page);
> + else
> + pfn = sym_to_pfn(vdso_data);
> + break;
> + case VVAR_TIMENS_PAGE_OFFSET:
> + /*
> + * If a task belongs to a time namespace then a namespace
> + * specific VVAR is mapped with the VVAR_DATA_PAGE_OFFSET and
> + * the real VVAR page is mapped with the VVAR_TIMENS_PAGE_OFFSET
> + * offset.
> + * See also the comment near timens_setup_vdso_data().
> + */
> + if (!timens_page)
> + return VM_FAULT_SIGBUS;
> + pfn = sym_to_pfn(vdso_data);
> + break;
> + default:
> + return VM_FAULT_SIGBUS;
> + }
> +
> + return vmf_insert_pfn(vma, vmf->address, pfn);
> }
>
> static int __setup_additional_pages(enum arch_vdso_type arch_index,
>
--
Regards,
Vincenzo
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* Re: [PATCH 4/5] arm64/vdso: Handle faults on timens page
From: Vincenzo Frascino @ 2020-02-20 12:07 UTC (permalink / raw)
To: Andrei Vagin
Cc: Thomas Gleixner, linux-kernel, linux-arm-kernel, Dmitry Safonov
In-Reply-To: <20200204175913.74901-5-avagin@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2998 bytes --]
Hi Andrei,
On 04/02/2020 17:59, Andrei Vagin wrote:
> If a task belongs to a time namespace then the VVAR page which contains
> the system wide VDSO data is replaced with a namespace specific page
> which has the same layout as the VVAR page.
>
> Signed-off-by: Andrei Vagin <avagin@gmail.com>
> ---
> arch/arm64/kernel/vdso.c | 55 +++++++++++++++++++++++++++++++++++++---
> 1 file changed, 51 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
> index bc93e26ae485..2e553468b183 100644
> --- a/arch/arm64/kernel/vdso.c
> +++ b/arch/arm64/kernel/vdso.c
> @@ -23,6 +23,7 @@
> #include <vdso/datapage.h>
> #include <vdso/helpers.h>
> #include <vdso/vsyscall.h>
> +#include <linux/time_namespace.h>
>
Nit: Could you please group this with the linux/ headers and keep the
alphabetical order.
> #include <asm/cacheflush.h>
> #include <asm/signal32.h>
> @@ -171,15 +172,61 @@ int vdso_join_timens(struct task_struct *task, struct time_namespace *ns)
> up_write(&mm->mmap_sem);
> return 0;
> }
> +
> +static struct page *find_timens_vvar_page(struct vm_area_struct *vma)
> +{
> + if (likely(vma->vm_mm == current->mm))
> + return current->nsproxy->time_ns->vvar_page;
> +
> + /*
> + * VM_PFNMAP | VM_IO protect .fault() handler from being called
> + * through interfaces like /proc/$pid/mem or
> + * process_vm_{readv,writev}() as long as there's no .access()
> + * in special_mapping_vmops().
> + * For more details check_vma_flags() and __access_remote_vm()
> + */
> +
> + WARN(1, "vvar_page accessed remotely");
> +
> + return NULL;
> +}
> +#else
> +static inline struct page *find_timens_vvar_page(struct vm_area_struct *vma)
> +{
> + return NULL;
> +}
> #endif
>
> static vm_fault_t vvar_fault(const struct vm_special_mapping *sm,
> struct vm_area_struct *vma, struct vm_fault *vmf)
> {
> - if (vmf->pgoff == 0)
> - return vmf_insert_pfn(vma, vmf->address,
> - sym_to_pfn(vdso_data));
> - return VM_FAULT_SIGBUS;
> + struct page *timens_page = find_timens_vvar_page(vma);
> + unsigned long pfn;
> +
> + switch (vmf->pgoff) {
> + case VVAR_DATA_PAGE_OFFSET:
> + if (timens_page)
> + pfn = page_to_pfn(timens_page);
> + else
> + pfn = sym_to_pfn(vdso_data);
> + break;
> + case VVAR_TIMENS_PAGE_OFFSET:
> + /*
> + * If a task belongs to a time namespace then a namespace
> + * specific VVAR is mapped with the VVAR_DATA_PAGE_OFFSET and
> + * the real VVAR page is mapped with the VVAR_TIMENS_PAGE_OFFSET
> + * offset.
> + * See also the comment near timens_setup_vdso_data().
> + */
> + if (!timens_page)
> + return VM_FAULT_SIGBUS;
> + pfn = sym_to_pfn(vdso_data);
> + break;
> + default:
> + return VM_FAULT_SIGBUS;
> + }
> +
> + return vmf_insert_pfn(vma, vmf->address, pfn);
> }
>
> static int __setup_additional_pages(enum arch_vdso_type arch_index,
>
--
Regards,
Vincenzo
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] bdi: fix use-after-free for bdi device
From: Jan Kara @ 2020-02-20 12:07 UTC (permalink / raw)
To: Yufen Yu; +Cc: Jan Kara, Tejun Heo, axboe, linux-block, bvanassche
In-Reply-To: <59a8851e-7ba2-e70d-36d8-be47829a7581@huawei.com>
On Thu 20-02-20 19:07:01, Yufen Yu wrote:
> Hi,
>
> On 2020/2/19 20:55, Jan Kara wrote:
> > Hi!
> >
> > On Sat 15-02-20 21:54:08, Yufen Yu wrote:
>
> >
> > I've now noticed there's commit 68f23b8906 "memcg: fix a crash in wb_workfn
> > when a device disappears" from end of January which tries to address the
> > issue you're looking into. Now AFAIU the code is till somewhat racy after
> > that commit so I wanted to mention this mostly so that you fixup also the
> > new bdi_dev_name() while you're fixing blkg_dev_name().
> >
> > Also I was wondering about one thing: If we really care about bdi->dev only
> > for the name, won't we be much better off with just copying the name to
> > bdi->name on registration? Sure it would consume a bit of memory for the
> > name copy but I don't think we really care and things would be IMO *much*
> > simpler that way... Yufen, Tejun, what do you think?
> >
>
> I think copying the name to bdi->name is also need protected by lock.
> Otherwise, the reader of bdi->name may read incorrect value when
> re-registion have not copy the name completely. Right? So, I also think
> using RCU to protect object lifetimes may be a better way.
OK, fair enough. :)
Honza
--
Jan Kara <jack@suse.com>
SUSE Labs, CR
^ permalink raw reply
* Re: [igt-dev] [PATCH i-g-t] tests/kms_rotation_crc: limit maximum used plane size
From: Lisovskiy, Stanislav @ 2020-02-20 12:09 UTC (permalink / raw)
To: juhapekka.heikkila@gmail.com, igt-dev@lists.freedesktop.org
In-Reply-To: <1581969803-15387-1-git-send-email-juhapekka.heikkila@gmail.com>
On Mon, 2020-02-17 at 22:03 +0200, Juha-Pekka Heikkila wrote:
> It shouldn't make difference here if used maximum available
> screen resolution or something smaller. Something smaller
> is much faster so limit maximum size to 640x480.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
> tests/kms_rotation_crc.c | 46 +++++++++++++++++++++++++++++++++-----
> --------
> 1 file changed, 33 insertions(+), 13 deletions(-)
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
> index 2a7b10e..819897b 100644
> --- a/tests/kms_rotation_crc.c
> +++ b/tests/kms_rotation_crc.c
> @@ -27,6 +27,8 @@
>
> #define MAX_FENCES 32
> #define MAXMULTIPLANESAMOUNT 2
> +#define TEST_MAX_WIDTH 640
> +#define TEST_MAX_HEIGHT 480
>
> struct p_struct {
> igt_plane_t *plane;
> @@ -65,6 +67,8 @@ typedef struct {
>
> struct p_struct *multiplaneoldview;
> struct p_point planepos[MAXMULTIPLANESAMOUNT];
> +
> + bool use_native_resolution;
> } data_t;
>
> typedef struct {
> @@ -210,8 +214,13 @@ static void prepare_fbs(data_t *data,
> igt_output_t *output,
>
> mode = igt_output_get_mode(output);
> if (plane->type != DRM_PLANE_TYPE_CURSOR) {
> - w = mode->hdisplay;
> - h = mode->vdisplay;
> + if (data->use_native_resolution) {
> + w = mode->hdisplay;
> + h = mode->vdisplay;
> + } else {
> + w = min(TEST_MAX_WIDTH, mode->hdisplay);
> + h = min(TEST_MAX_HEIGHT, mode->vdisplay);
> + }
>
> min_w = 256;
> min_h = 256;
> @@ -404,8 +413,16 @@ static void test_plane_rotation(data_t *data,
> int plane_type, bool test_bad_form
>
> /* Only support partial covering primary plane
> on gen9+ */
> if (plane_type == DRM_PLANE_TYPE_PRIMARY &&
> - i != rectangle &&
> intel_gen(intel_get_drm_devid(data->gfx_fd)) < 9)
> - continue;
> + intel_gen(intel_get_drm_devid(data-
> >gfx_fd)) < 9) {
> + if (i != rectangle)
> + continue;
> + else
> + data->use_native_resolution =
> true;
> +
> + } else {
> + data->use_native_resolution = false;
> + }
> +
>
> if (!data->override_fmt) {
> for (j = 0; j < plane->drm_plane-
> >count_formats; j++) {
> @@ -493,7 +510,7 @@ static void pointlocation(data_t *data,
> planeinfos *p, drmModeModeInfo *mode,
> int c)
> {
> if (data->planepos[c].origo & p_right) {
> - p[c].x1 = (int32_t)(data->planepos[c].x * mode-
> >hdisplay
> + p[c].x1 = (int32_t)(data->planepos[c].x *
> min(TEST_MAX_WIDTH, mode->hdisplay)
> + mode->hdisplay);
> p[c].x1 &= ~3;
> /*
> @@ -504,17 +521,17 @@ static void pointlocation(data_t *data,
> planeinfos *p, drmModeModeInfo *mode,
> */
> p[c].x1 -= mode->hdisplay & 2;
> } else {
> - p[c].x1 = (int32_t)(data->planepos[c].x * mode-
> >hdisplay);
> + p[c].x1 = (int32_t)(data->planepos[c].x *
> min(TEST_MAX_WIDTH, mode->hdisplay));
> p[c].x1 &= ~3;
> }
>
> if (data->planepos[c].origo & p_bottom) {
> - p[c].y1 = (int32_t)(data->planepos[c].y * mode-
> >vdisplay
> + p[c].y1 = (int32_t)(data->planepos[c].y *
> min(TEST_MAX_HEIGHT, mode->vdisplay)
> + mode->vdisplay);
> p[c].y1 &= ~3;
> p[c].y1 -= mode->vdisplay & 2;
> } else {
> - p[c].y1 = (int32_t)(data->planepos[c].y * mode-
> >vdisplay);
> + p[c].y1 = (int32_t)(data->planepos[c].y *
> min(TEST_MAX_HEIGHT, mode->vdisplay));
> p[c].y1 &= ~3;
> }
> }
> @@ -530,7 +547,7 @@ static void test_multi_plane_rotation(data_t
> *data, enum pipe pipe)
> igt_output_t *output;
> igt_crc_t retcrc_sw, retcrc_hw;
> planeinfos p[2];
> - int c;
> + int c, used_w, used_h;
> struct p_struct *oldplanes;
> drmModeModeInfo *mode;
>
> @@ -568,14 +585,17 @@ static void test_multi_plane_rotation(data_t
> *data, enum pipe pipe)
> igt_display_require_output(display);
> igt_display_commit2(display, COMMIT_ATOMIC);
>
> + used_w = min(TEST_MAX_WIDTH, mode->hdisplay);
> + used_h = min(TEST_MAX_HEIGHT, mode->vdisplay);
> +
> data->pipe_crc = igt_pipe_crc_new(data->gfx_fd, pipe,
> INTEL_PIPE_CRC_SOURCE
> _AUTO);
> igt_pipe_crc_start(data->pipe_crc);
>
> for (i = 0; i < ARRAY_SIZE(planeconfigs); i++) {
> p[0].planetype = DRM_PLANE_TYPE_PRIMARY;
> - p[0].width = (uint64_t)(planeconfigs[i].width *
> mode->hdisplay);
> - p[0].height = (uint64_t)(planeconfigs[i].height
> * mode->vdisplay);
> + p[0].width = (uint64_t)(planeconfigs[i].width *
> used_w);
> + p[0].height = (uint64_t)(planeconfigs[i].height
> * used_h);
> p[0].tiling = planeconfigs[i].tiling;
> pointlocation(data, (planeinfos *)&p, mode, 0);
>
> @@ -584,8 +604,8 @@ static void test_multi_plane_rotation(data_t
> *data, enum pipe pipe)
>
> for (j = 0; j <
> ARRAY_SIZE(planeconfigs); j++) {
> p[1].planetype =
> DRM_PLANE_TYPE_OVERLAY;
> - p[1].width =
> (uint64_t)(planeconfigs[j].width * mode->hdisplay);
> - p[1].height =
> (uint64_t)(planeconfigs[j].height * mode->vdisplay);
> + p[1].width =
> (uint64_t)(planeconfigs[j].width * used_w);
> + p[1].height =
> (uint64_t)(planeconfigs[j].height * used_h);
> p[1].tiling =
> planeconfigs[j].tiling;
> pointlocation(data, (planeinfos
> *)&p,
> mode, 1);
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: remove the other slab_dependencies
From: Patchwork @ 2020-02-20 12:10 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
In-Reply-To: <20200220105707.344522-1-matthew.auld@intel.com>
== Series Details ==
Series: drm/i915: remove the other slab_dependencies
URL : https://patchwork.freedesktop.org/series/73701/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7972 -> Patchwork_16643
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16643 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16643, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16643:
### IGT changes ###
#### Possible regressions ####
* igt@prime_busy@basic-wait-before-default:
- fi-skl-6770hq: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-skl-6770hq/igt@prime_busy@basic-wait-before-default.html
Known issues
------------
Here are the changes found in Patchwork_16643 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-hsw-peppy: [PASS][2] -> [INCOMPLETE][3] ([i915#694] / [i915#816])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
* igt@i915_selftest@live_gem_contexts:
- fi-cml-s: [PASS][4] -> [DMESG-FAIL][5] ([i915#877])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gtt:
- fi-bxt-dsi: [PASS][6] -> [TIMEOUT][7] ([fdo#112271])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-bxt-dsi/igt@i915_selftest@live_gtt.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-bxt-dsi/igt@i915_selftest@live_gtt.html
- fi-bdw-5557u: [PASS][8] -> [TIMEOUT][9] ([fdo#112271])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-bdw-5557u/igt@i915_selftest@live_gtt.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-bdw-5557u/igt@i915_selftest@live_gtt.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][10] -> [FAIL][11] ([i915#262])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][12] ([i915#585]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-icl-u3/igt@i915_module_load@reload.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-icl-u3/igt@i915_module_load@reload.html
* igt@i915_selftest@live_execlists:
- fi-icl-y: [DMESG-FAIL][14] ([fdo#108569]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-icl-y/igt@i915_selftest@live_execlists.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-icl-y/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [DMESG-FAIL][16] ([i915#730]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gtt:
- fi-kbl-7500u: [TIMEOUT][18] ([fdo#112271]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-kbl-7500u/igt@i915_selftest@live_gtt.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-kbl-7500u/igt@i915_selftest@live_gtt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][20] ([fdo#108569]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7972/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#112126]: https://bugs.freedesktop.org/show_bug.cgi?id=112126
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#585]: https://gitlab.freedesktop.org/drm/intel/issues/585
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#730]: https://gitlab.freedesktop.org/drm/intel/issues/730
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
Participating hosts (50 -> 43)
------------------------------
Additional (2): fi-skl-6770hq fi-gdg-551
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bdw-gvtdvm fi-byt-squawks fi-bsw-cyan fi-bsw-kefka fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7972 -> Patchwork_16643
CI-20190529: 20190529
CI_DRM_7972: 858e6dfae5d9f401678831159b994d197b121e7c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5453: cae9a5881ed2c5be2c2518a255740b612a927f9a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16643: eeb9d92e0efc49dd9f6cb222ad8566c2a75c3613 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
eeb9d92e0efc drm/i915: remove the other slab_dependencies
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16643/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: [dpdk-dev] [PATCH 2/4] ci: fix Travis config warnings
From: David Marchand @ 2020-02-20 12:09 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: Aaron Conole, dev, Michael Santana
In-Reply-To: <6771332.6fTUFtlzNn@xps>
On Thu, Feb 20, 2020 at 12:03 PM Thomas Monjalon <thomas@monjalon.net> wrote:
>
> 19/02/2020 20:41, David Marchand:
> > Reading https://config.travis-ci.com/ and using
> > https://config.travis-ci.com/explore to check changes, we can cleanup
> > some warnings reported by the config validation options in Travis.
>
> For documentation purpose, would be good to describe issues in the commit log.
Ok, will do.
--
David Marchand
^ permalink raw reply
* [Intel-gfx] [PATCH v17 0/7] Refactor Gen11+ SAGV support
From: Stanislav Lisovskiy @ 2020-02-20 12:07 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
v17: Had to rebase the whole series.
Stanislav Lisovskiy (7):
drm/i915: Start passing latency as parameter
drm/i915: Introduce skl_plane_wm_level accessor.
drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Added required new PCode commands
drm/i915: Restrict qgv points which don't have enough bandwidth.
drm/i915: Enable SAGV support for Gen12
drivers/gpu/drm/i915/display/intel_bw.c | 205 ++++--
drivers/gpu/drm/i915/display/intel_bw.h | 36 ++
drivers/gpu/drm/i915/display/intel_display.c | 131 +++-
.../drm/i915/display/intel_display_types.h | 2 +
.../gpu/drm/i915/display/intel_global_state.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_pm.c | 585 +++++++++++++++---
drivers/gpu/drm/i915/intel_pm.h | 4 +-
drivers/gpu/drm/i915/intel_sideband.c | 2 +
10 files changed, 834 insertions(+), 139 deletions(-)
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [Intel-gfx] [PATCH v17 1/7] drm/i915: Start passing latency as parameter
From: Stanislav Lisovskiy @ 2020-02-20 12:07 UTC (permalink / raw)
To: intel-gfx
In-Reply-To: <20200220120741.6917-1-stanislav.lisovskiy@intel.com>
We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ffac0b862ca5..d6933e382657 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4002,6 +4002,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -4024,7 +4025,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
drm_WARN_ON(&dev_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+ u32 latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4978,12 +4981,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5112,9 +5115,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
+ u32 latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
- result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+ wm_params, result_prev, result);
result_prev = result;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [Intel-gfx] [PATCH v17 3/7] drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
From: Stanislav Lisovskiy @ 2020-02-20 12:07 UTC (permalink / raw)
To: intel-gfx
In-Reply-To: <20200220120741.6917-1-stanislav.lisovskiy@intel.com>
We might be willing to call intel_atomic_get_old_global_obj_state
and intel_atomic_get_new_global_obj_state right away, however
those are not initializing global obj state as
intel_atomic_get_global_obj_state does.
Extracted initializing part to separate function and now using this
also in intel_atomic_get_old_global_obj_state and intel_atomic_get_new_global_obj_state
v2: - Fixed typo in function call
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 28 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_bw.h | 9 ++++++++
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 58b264bc318d..ff57277e8880 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -374,7 +374,33 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
return data_rate;
}
-static struct intel_bw_state *
+struct intel_bw_state *
+intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
+ if (IS_ERR(bw_state))
+ return ERR_CAST(bw_state);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+ bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
+
+ if (IS_ERR(bw_state))
+ return ERR_CAST(bw_state);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
intel_atomic_get_bw_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index a8aa7624c5aa..ac004d6f4276 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,15 @@ struct intel_bw_state {
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
+struct intel_bw_state *
+intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_bw_state(struct intel_atomic_state *state);
+
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related
* [Intel-gfx] [PATCH v17 2/7] drm/i915: Introduce skl_plane_wm_level accessor.
From: Stanislav Lisovskiy @ 2020-02-20 12:07 UTC (permalink / raw)
To: intel-gfx
In-Reply-To: <20200220120741.6917-1-stanislav.lisovskiy@intel.com>
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++++++-----------
1 file changed, 81 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d6933e382657..e1d167429489 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4548,6 +4548,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ int level,
+ int color_plane)
+{
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane->id];
+
+ return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4560,7 +4572,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
u16 total[I915_MAX_PLANES] = {};
u16 uv_total[I915_MAX_PLANES] = {};
u64 total_data_rate;
- enum plane_id plane_id;
+ struct intel_plane *plane;
int num_active;
u64 plane_data_rate[I915_MAX_PLANES] = {};
u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
@@ -4612,22 +4624,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
- if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+
+ wm_level = skl_plane_wm_level(plane, crtc_state,
+ level, false);
+ wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+ level, true);
+
+ if (plane->id == PLANE_CURSOR) {
+ if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
drm_WARN_ON(&dev_priv->drm,
- wm->wm[level].min_ddb_alloc != U16_MAX);
+ wm_level->min_ddb_alloc != U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4649,13 +4667,18 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* watermark level, plus an extra share of the leftover blocks
* proportional to its relative data rate.
*/
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
- if (plane_id == PLANE_CURSOR)
+ wm_level = skl_plane_wm_level(plane, crtc_state,
+ level, false);
+ wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+ level, true);
+
+ if (plane->id == PLANE_CURSOR)
continue;
/*
@@ -4665,22 +4688,22 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
if (total_data_rate == 0)
break;
- rate = plane_data_rate[plane_id];
+ rate = plane_data_rate[plane->id];
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+ total[plane->id] = wm_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
if (total_data_rate == 0)
break;
- rate = uv_plane_data_rate[plane_id];
+ rate = uv_plane_data_rate[plane->id];
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+ uv_total[plane->id] = wm_uv_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
@@ -4688,29 +4711,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
/* Set the actual DDB start/end points for each plane */
start = alloc->start;
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
struct skl_ddb_entry *plane_alloc =
- &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ &crtc_state->wm.skl.plane_ddb_y[plane->id];
struct skl_ddb_entry *uv_plane_alloc =
- &crtc_state->wm.skl.plane_ddb_uv[plane_id];
+ &crtc_state->wm.skl.plane_ddb_uv[plane->id];
- if (plane_id == PLANE_CURSOR)
+ if (plane->id == PLANE_CURSOR)
continue;
/* Gen11+ uses a separate plane for UV watermarks */
drm_WARN_ON(&dev_priv->drm,
- INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
+ INTEL_GEN(dev_priv) >= 11 && uv_total[plane->id]);
/* Leave disabled planes at (0,0) */
- if (total[plane_id]) {
+ if (total[plane->id]) {
plane_alloc->start = start;
- start += total[plane_id];
+ start += total[plane->id];
plane_alloc->end = start;
}
- if (uv_total[plane_id]) {
+ if (uv_total[plane->id]) {
uv_plane_alloc->start = start;
- start += uv_total[plane_id];
+ start += uv_total[plane->id];
uv_plane_alloc->end = start;
}
}
@@ -4722,9 +4745,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* that aren't actually possible.
*/
for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ &crtc_state->wm.skl.optimal.planes[plane->id];
+
+ wm_level = skl_plane_wm_level(plane, crtc_state,
+ level, false);
+ wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+ level, true);
/*
* We only disable the watermarks for each plane if
@@ -4738,9 +4768,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* planes must be enabled before the level will be used."
* So this is actually safe to do.
*/
- if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
- wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
- memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+ if (wm_level->min_ddb_alloc > total[plane->id] ||
+ wm_uv_level->min_ddb_alloc > uv_total[plane->id])
+ memset(&wm->wm[level], 0,
+ sizeof(struct skl_wm_level));
/*
* Wa_1408961008:icl, ehl
@@ -4748,9 +4779,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
- wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
- wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
- wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+ wm_level = skl_plane_wm_level(plane, crtc_state,
+ 0, false);
+ wm->wm[level].plane_res_b =
+ wm_level->plane_res_b;
+ wm->wm[level].plane_res_l =
+ wm_level->plane_res_l;
+ wm->wm[level].ignore_lines =
+ wm_level->ignore_lines;
}
}
}
@@ -4759,11 +4795,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* Go back and disable the transition watermark if it turns out we
* don't have enough DDB blocks for it.
*/
- for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ &crtc_state->wm.skl.optimal.planes[plane->id];
- if (wm->trans_wm.plane_res_b >= total[plane_id])
+ if (wm->trans_wm.plane_res_b >= total[plane->id])
memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
}
@@ -5354,10 +5390,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_y[plane_id];
const struct skl_ddb_entry *ddb_uv =
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
+ const struct skl_wm_level *wm_level;
for (level = 0; level <= max_level; level++) {
+ wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
&wm->trans_wm);
@@ -5388,10 +5427,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
&crtc_state->wm.skl.optimal.planes[plane_id];
const struct skl_ddb_entry *ddb =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
+ const struct skl_wm_level *wm_level;
for (level = 0; level <= max_level; level++) {
+ wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
--
2.24.1.485.gad05a3d8e5
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