* [PATCH v6 2/7] MIPS: JZ4780: Introduce SMP support.
From: 周琰杰 (Zhou Yanjie) @ 2020-02-20 16:24 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, tglx, ralf, paulburton,
jiaxun.yang, chenhc, sboyd, mturquette, mark.rutland, robh+dt,
daniel.lezcano, paul, geert+renesas, krzk, ebiederm,
miquel.raynal, keescook, sernia.zhou, zhenwenjin, dongsheng.qiu
In-Reply-To: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com>
Forward port smp support from kernel 3.18.3 of CI20_linux
to upstream kernel 5.6.
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
Notes:
v1->v2:
1.Remove unnecessary "plat_irq_dispatch(void)" in irq-ingenic.c.
2.Add a timeout check for "jz4780_boot_secondary()" to avoid a dead loop.
3.Replace hard code in smp.c with macro.
v2->v3:
1.Remove unnecessary "extern void (*r4k_blast_dcache)(void)" in smp.c.
2.Use "for_each_of_cpu_node" instead "for_each_compatible_node" in smp.c.
3.Use "of_cpu_node_to_id" instead "of_property_read_u32_index" in smp.c.
4.Move LCR related operations to jz4780-cgu.c.
v3->v4:
Rebase on top of kernel 5.6-rc1.
v4->v5:
1.Splitting changes involving "jz4780-cgu.c" into separate commit.
2.Use "request_irq()" replace "setup_irq()".
v5->v6:
In order to have a kernel that works on multiple SoCs at the same
time, use "IS_ENABLED()" replace "#ifdef".
arch/mips/include/asm/mach-jz4740/smp.h | 81 ++++++++++
arch/mips/jz4740/Kconfig | 3 +
arch/mips/jz4740/Makefile | 5 +
arch/mips/jz4740/prom.c | 4 +
arch/mips/jz4740/smp-entry.S | 57 +++++++
arch/mips/jz4740/smp.c | 254 ++++++++++++++++++++++++++++++++
arch/mips/kernel/idle.c | 36 ++++-
7 files changed, 439 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/include/asm/mach-jz4740/smp.h
create mode 100644 arch/mips/jz4740/smp-entry.S
create mode 100644 arch/mips/jz4740/smp.c
diff --git a/arch/mips/include/asm/mach-jz4740/smp.h b/arch/mips/include/asm/mach-jz4740/smp.h
new file mode 100644
index 00000000..af3c21b
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/smp.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2013, Paul Burton <paul.burton@imgtec.com>
+ * JZ4780 SMP definitions
+ */
+
+#ifndef __MIPS_ASM_MACH_JZ4740_JZ4780_SMP_H__
+#define __MIPS_ASM_MACH_JZ4740_JZ4780_SMP_H__
+
+#define read_c0_corectrl() __read_32bit_c0_register($12, 2)
+#define write_c0_corectrl(val) __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_corestatus() __read_32bit_c0_register($12, 3)
+#define write_c0_corestatus(val) __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_reim() __read_32bit_c0_register($12, 4)
+#define write_c0_reim(val) __write_32bit_c0_register($12, 4, val)
+
+#define read_c0_mailbox0() __read_32bit_c0_register($20, 0)
+#define write_c0_mailbox0(val) __write_32bit_c0_register($20, 0, val)
+
+#define read_c0_mailbox1() __read_32bit_c0_register($20, 1)
+#define write_c0_mailbox1(val) __write_32bit_c0_register($20, 1, val)
+
+#define smp_clr_pending(mask) do { \
+ unsigned int stat; \
+ stat = read_c0_corestatus(); \
+ stat &= ~((mask) & 0xff); \
+ write_c0_corestatus(stat); \
+ } while (0)
+
+/*
+ * Core Control register
+ */
+#define CORECTRL_SLEEP1M_SHIFT 17
+#define CORECTRL_SLEEP1M (_ULCAST_(0x1) << CORECTRL_SLEEP1M_SHIFT)
+#define CORECTRL_SLEEP0M_SHIFT 16
+#define CORECTRL_SLEEP0M (_ULCAST_(0x1) << CORECTRL_SLEEP0M_SHIFT)
+#define CORECTRL_RPC1_SHIFT 9
+#define CORECTRL_RPC1 (_ULCAST_(0x1) << CORECTRL_RPC1_SHIFT)
+#define CORECTRL_RPC0_SHIFT 8
+#define CORECTRL_RPC0 (_ULCAST_(0x1) << CORECTRL_RPC0_SHIFT)
+#define CORECTRL_SWRST1_SHIFT 1
+#define CORECTRL_SWRST1 (_ULCAST_(0x1) << CORECTRL_SWRST1_SHIFT)
+#define CORECTRL_SWRST0_SHIFT 0
+#define CORECTRL_SWRST0 (_ULCAST_(0x1) << CORECTRL_SWRST0_SHIFT)
+
+/*
+ * Core Status register
+ */
+#define CORESTATUS_SLEEP1_SHIFT 17
+#define CORESTATUS_SLEEP1 (_ULCAST_(0x1) << CORESTATUS_SLEEP1_SHIFT)
+#define CORESTATUS_SLEEP0_SHIFT 16
+#define CORESTATUS_SLEEP0 (_ULCAST_(0x1) << CORESTATUS_SLEEP0_SHIFT)
+#define CORESTATUS_IRQ1P_SHIFT 9
+#define CORESTATUS_IRQ1P (_ULCAST_(0x1) << CORESTATUS_IRQ1P_SHIFT)
+#define CORESTATUS_IRQ0P_SHIFT 8
+#define CORESTATUS_IRQ0P (_ULCAST_(0x1) << CORESTATUS_IRQ8P_SHIFT)
+#define CORESTATUS_MIRQ1P_SHIFT 1
+#define CORESTATUS_MIRQ1P (_ULCAST_(0x1) << CORESTATUS_MIRQ1P_SHIFT)
+#define CORESTATUS_MIRQ0P_SHIFT 0
+#define CORESTATUS_MIRQ0P (_ULCAST_(0x1) << CORESTATUS_MIRQ0P_SHIFT)
+
+/*
+ * Reset Entry & IRQ Mask register
+ */
+#define REIM_ENTRY_SHIFT 16
+#define REIM_ENTRY (_ULCAST_(0xffff) << REIM_ENTRY_SHIFT)
+#define REIM_IRQ1M_SHIFT 9
+#define REIM_IRQ1M (_ULCAST_(0x1) << REIM_IRQ1M_SHIFT)
+#define REIM_IRQ0M_SHIFT 8
+#define REIM_IRQ0M (_ULCAST_(0x1) << REIM_IRQ0M_SHIFT)
+#define REIM_MBOXIRQ1M_SHIFT 1
+#define REIM_MBOXIRQ1M (_ULCAST_(0x1) << REIM_MBOXIRQ1M_SHIFT)
+#define REIM_MBOXIRQ0M_SHIFT 0
+#define REIM_MBOXIRQ0M (_ULCAST_(0x1) << REIM_MBOXIRQ0M_SHIFT)
+
+extern void jz4780_smp_init(void);
+extern void jz4780_secondary_cpu_entry(void);
+
+#endif /* __MIPS_ASM_MACH_JZ4740_JZ4780_SMP_H__ */
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
index 412d2fa..0239597 100644
--- a/arch/mips/jz4740/Kconfig
+++ b/arch/mips/jz4740/Kconfig
@@ -34,9 +34,12 @@ config MACH_JZ4770
config MACH_JZ4780
bool
+ select GENERIC_CLOCKEVENTS_BROADCAST if SMP
select MIPS_CPU_SCACHE
+ select NR_CPUS_DEFAULT_2
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_SMP
config MACH_X1000
bool
diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
index 6de14c0..0a0f024 100644
--- a/arch/mips/jz4740/Makefile
+++ b/arch/mips/jz4740/Makefile
@@ -12,3 +12,8 @@ CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
# PM support
obj-$(CONFIG_PM) += pm.o
+
+# SMP support
+
+obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SMP) += smp-entry.o
diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c
index ff4555c..026259e 100644
--- a/arch/mips/jz4740/prom.c
+++ b/arch/mips/jz4740/prom.c
@@ -8,10 +8,14 @@
#include <asm/bootinfo.h>
#include <asm/fw/fw.h>
+#include <asm/mach-jz4740/smp.h>
void __init prom_init(void)
{
fw_init_cmdline();
+
+ if (IS_ENABLED(CONFIG_MACH_JZ4780) && IS_ENABLED(CONFIG_SMP))
+ jz4780_smp_init();
}
void __init prom_free_prom_memory(void)
diff --git a/arch/mips/jz4740/smp-entry.S b/arch/mips/jz4740/smp-entry.S
new file mode 100644
index 00000000..20049a3
--- /dev/null
+++ b/arch/mips/jz4740/smp-entry.S
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2013, Paul Burton <paul.burton@imgtec.com>
+ * JZ4780 SMP entry point
+ */
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/cacheops.h>
+#include <asm/mipsregs.h>
+
+#define CACHE_SIZE (32 * 1024)
+#define CACHE_LINESIZE 32
+
+.extern jz4780_cpu_entry_sp
+.extern jz4780_cpu_entry_gp
+
+.section .text.smp-entry
+.balign 0x10000
+.set noreorder
+LEAF(jz4780_secondary_cpu_entry)
+ mtc0 zero, CP0_CAUSE
+
+ li t0, ST0_CU0
+ mtc0 t0, CP0_STATUS
+
+ /* cache setup */
+ li t0, KSEG0
+ ori t1, t0, CACHE_SIZE
+ mtc0 zero, CP0_TAGLO, 0
+1: cache Index_Store_Tag_I, 0(t0)
+ cache Index_Store_Tag_D, 0(t0)
+ bne t0, t1, 1b
+ addiu t0, t0, CACHE_LINESIZE
+
+ /* kseg0 cache attribute */
+ mfc0 t0, CP0_CONFIG, 0
+ ori t0, t0, CONF_CM_CACHABLE_NONCOHERENT
+ mtc0 t0, CP0_CONFIG, 0
+
+ /* pagemask */
+ mtc0 zero, CP0_PAGEMASK, 0
+
+ /* retrieve sp */
+ la t0, jz4780_cpu_entry_sp
+ lw sp, 0(t0)
+
+ /* retrieve gp */
+ la t0, jz4780_cpu_entry_gp
+ lw gp, 0(t0)
+
+ /* jump to the kernel in kseg0 */
+ la t0, smp_bootstrap
+ jr t0
+ nop
+ END(jz4780_secondary_cpu_entry)
diff --git a/arch/mips/jz4740/smp.c b/arch/mips/jz4740/smp.c
new file mode 100644
index 00000000..5fe0cf3
--- /dev/null
+++ b/arch/mips/jz4740/smp.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2013, Paul Burton <paul.burton@imgtec.com>
+ * JZ4780 SMP
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/sched.h>
+#include <linux/sched/task_stack.h>
+#include <linux/smp.h>
+#include <linux/tick.h>
+#include <asm/mach-jz4740/smp.h>
+#include <asm/smp-ops.h>
+
+static struct clk *cpu_clock_gates[CONFIG_NR_CPUS] = { NULL };
+
+u32 jz4780_cpu_entry_sp;
+u32 jz4780_cpu_entry_gp;
+
+static struct cpumask cpu_running;
+
+static DEFINE_SPINLOCK(smp_lock);
+
+static irqreturn_t mbox_handler(int irq, void *dev_id)
+{
+ int cpu = smp_processor_id();
+ u32 action, status;
+
+ spin_lock(&smp_lock);
+
+ switch (cpu) {
+ case 0:
+ action = read_c0_mailbox0();
+ write_c0_mailbox0(0);
+ break;
+ case 1:
+ action = read_c0_mailbox1();
+ write_c0_mailbox1(0);
+ break;
+ default:
+ panic("unhandled cpu %d!", cpu);
+ }
+
+ /* clear pending mailbox interrupt */
+ status = read_c0_corestatus();
+ status &= ~(CORESTATUS_MIRQ0P << cpu);
+ write_c0_corestatus(status);
+
+ spin_unlock(&smp_lock);
+
+ if (action & SMP_RESCHEDULE_YOURSELF)
+ scheduler_ipi();
+ if (action & SMP_CALL_FUNCTION)
+ generic_smp_call_function_interrupt();
+
+ return IRQ_HANDLED;
+}
+
+static void jz4780_smp_setup(void)
+{
+ u32 addr, reim;
+ int cpu;
+
+ reim = read_c0_reim();
+
+ for (cpu = 0; cpu < NR_CPUS; cpu++) {
+ __cpu_number_map[cpu] = cpu;
+ __cpu_logical_map[cpu] = cpu;
+ set_cpu_possible(cpu, true);
+ }
+
+ /* mask mailbox interrupts for this core */
+ reim &= ~REIM_MBOXIRQ0M;
+ write_c0_reim(reim);
+
+ /* clear mailboxes & pending mailbox IRQs */
+ write_c0_mailbox0(0);
+ write_c0_mailbox1(0);
+ write_c0_corestatus(0);
+
+ /* set reset entry point */
+ addr = KSEG1ADDR((u32)&jz4780_secondary_cpu_entry);
+ WARN_ON(addr & ~REIM_ENTRY);
+ reim &= ~REIM_ENTRY;
+ reim |= addr & REIM_ENTRY;
+
+ /* unmask mailbox interrupts for this core */
+ reim |= REIM_MBOXIRQ0M;
+ write_c0_reim(reim);
+ set_c0_status(STATUSF_IP3);
+ irq_enable_hazard();
+
+ cpumask_set_cpu(cpu, &cpu_running);
+}
+
+static void jz4780_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *cpu_node;
+ unsigned cpu, ctrl;
+ int err;
+
+ /* setup the mailbox IRQ */
+ err = request_irq(MIPS_CPU_IRQ_BASE + 3, mbox_handler,
+ IRQF_PERCPU | IRQF_NO_THREAD, "core mailbox", NULL);
+ if (err)
+ pr_err("request_irq() on core mailbox failed\n");
+
+ init_cpu_present(cpu_possible_mask);
+
+ ctrl = read_c0_corectrl();
+
+ for (cpu = 0; cpu < max_cpus; cpu++) {
+ /* use reset entry point from REIM register */
+ ctrl |= CORECTRL_RPC0 << cpu;
+ }
+
+ for_each_of_cpu_node(cpu_node) {
+ cpu = of_cpu_node_to_id(cpu_node);
+ if (cpu < 0) {
+ pr_err("Failed to read index of %s\n",
+ cpu_node->full_name);
+ continue;
+ }
+
+ cpu_clock_gates[cpu] = of_clk_get(cpu_node, 0);
+ if (IS_ERR(cpu_clock_gates[cpu])) {
+ cpu_clock_gates[cpu] = NULL;
+ continue;
+ }
+
+ err = clk_prepare(cpu_clock_gates[cpu]);
+ if (err)
+ pr_err("Failed to prepare CPU clock gate\n");
+ }
+
+ write_c0_corectrl(ctrl);
+}
+
+static int jz4780_boot_secondary(int cpu, struct task_struct *idle)
+{
+ unsigned long flags;
+ u32 ctrl;
+
+ spin_lock_irqsave(&smp_lock, flags);
+
+ /* ensure the core is in reset */
+ ctrl = read_c0_corectrl();
+ ctrl |= CORECTRL_SWRST0 << cpu;
+ write_c0_corectrl(ctrl);
+
+ /* ungate core clock */
+ if (cpu_clock_gates[cpu])
+ clk_enable(cpu_clock_gates[cpu]);
+
+ /* set entry sp/gp register values */
+ jz4780_cpu_entry_sp = __KSTK_TOS(idle);
+ jz4780_cpu_entry_gp = (u32)task_thread_info(idle);
+ smp_wmb();
+
+ /* take the core out of reset */
+ ctrl &= ~(CORECTRL_SWRST0 << cpu);
+ write_c0_corectrl(ctrl);
+
+ cpumask_set_cpu(cpu, &cpu_running);
+
+ spin_unlock_irqrestore(&smp_lock, flags);
+
+ return 0;
+}
+
+static void jz4780_init_secondary(void)
+{
+}
+
+static void jz4780_smp_finish(void)
+{
+ u32 reim;
+
+ spin_lock(&smp_lock);
+
+ /* unmask mailbox interrupts for this core */
+ reim = read_c0_reim();
+ reim |= REIM_MBOXIRQ0M << smp_processor_id();
+ write_c0_reim(reim);
+
+ spin_unlock(&smp_lock);
+
+ /* unmask interrupts for this core */
+ change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP2 |
+ STATUSF_IP1 | STATUSF_IP0);
+ irq_enable_hazard();
+
+ /* force broadcast timer */
+ tick_broadcast_force();
+}
+
+static void jz4780_send_ipi_single_locked(int cpu, unsigned int action)
+{
+ u32 mbox;
+
+ switch (cpu) {
+ case 0:
+ mbox = read_c0_mailbox0();
+ write_c0_mailbox0(mbox | action);
+ break;
+ case 1:
+ mbox = read_c0_mailbox1();
+ write_c0_mailbox1(mbox | action);
+ break;
+ default:
+ panic("unhandled cpu %d!", cpu);
+ }
+}
+
+static void jz4780_send_ipi_single(int cpu, unsigned int action)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&smp_lock, flags);
+ jz4780_send_ipi_single_locked(cpu, action);
+ spin_unlock_irqrestore(&smp_lock, flags);
+}
+
+static void jz4780_send_ipi_mask(const struct cpumask *mask,
+ unsigned int action)
+{
+ unsigned long flags;
+ int cpu;
+
+ spin_lock_irqsave(&smp_lock, flags);
+
+ for_each_cpu(cpu, mask)
+ jz4780_send_ipi_single_locked(cpu, action);
+
+ spin_unlock_irqrestore(&smp_lock, flags);
+}
+
+static struct plat_smp_ops jz4780_smp_ops = {
+ .send_ipi_single = jz4780_send_ipi_single,
+ .send_ipi_mask = jz4780_send_ipi_mask,
+ .init_secondary = jz4780_init_secondary,
+ .smp_finish = jz4780_smp_finish,
+ .boot_secondary = jz4780_boot_secondary,
+ .smp_setup = jz4780_smp_setup,
+ .prepare_cpus = jz4780_smp_prepare_cpus,
+};
+
+void jz4780_smp_init(void)
+{
+ register_smp_ops(&jz4780_smp_ops);
+}
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 37f8e78..a3afd98 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -18,6 +18,7 @@
#include <asm/cpu-type.h>
#include <asm/idle.h>
#include <asm/mipsregs.h>
+#include <asm/r4kcache.h>
/*
* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -88,6 +89,34 @@ static void __cpuidle rm7k_wait_irqoff(void)
}
/*
+ * The Ingenic jz4780 SMP variant has to write back dirty cache lines before
+ * executing wait. The CPU & cache clock will be gated until we return from
+ * the wait, and if another core attempts to access data from our data cache
+ * during this time then it will lock up.
+ */
+void jz4780_smp_wait_irqoff(void)
+{
+ unsigned long pending = read_c0_cause() & read_c0_status() & CAUSEF_IP;
+
+ /*
+ * Going to idle has a significant overhead due to the cache flush so
+ * try to avoid it if we'll immediately be woken again due to an IRQ.
+ */
+ if (!need_resched() && !pending) {
+ r4k_blast_dcache();
+
+ __asm__(
+ " .set push \n"
+ " .set mips3 \n"
+ " sync \n"
+ " wait \n"
+ " .set pop \n");
+ }
+
+ local_irq_enable();
+}
+
+/*
* Au1 'wait' is only useful when the 32kHz counter is used as timer,
* since coreclock (and the cp0 counter) stops upon executing it. Only an
* interrupt can wake it, so they must be enabled before entering idle modes.
@@ -172,7 +201,6 @@ void __init check_wait(void)
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
case CPU_CAVIUM_OCTEON3:
- case CPU_XBURST:
case CPU_LOONGSON32:
case CPU_XLR:
case CPU_XLP:
@@ -246,6 +274,12 @@ void __init check_wait(void)
cpu_wait = r4k_wait;
*/
break;
+ case CPU_XBURST:
+ if (IS_ENABLED(CONFIG_MACH_JZ4780) &&
+ IS_ENABLED(CONFIG_SMP) && (NR_CPUS > 1))
+ cpu_wait = jz4780_smp_wait_irqoff;
+ else
+ cpu_wait = r4k_wait;
default:
break;
}
--
2.7.4
^ permalink raw reply related
* [PATCH v3] dt-bindings: mfd: Convert stmfx bindings to json-schema
From: Benjamin Gaignard @ 2020-02-20 16:22 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, alexandre.torgue, linus.walleij,
amelie.delaunay
Cc: devicetree, Benjamin Gaignard, linux-kernel, linux-gpio,
linux-stm32, linux-arm-kernel
Convert stmfx bindings to json-schema
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../devicetree/bindings/mfd/st,stmfx.yaml | 124 +++++++++++++++++++++
Documentation/devicetree/bindings/mfd/stmfx.txt | 28 -----
.../devicetree/bindings/pinctrl/pinctrl-stmfx.txt | 116 -------------------
3 files changed, 124 insertions(+), 144 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/st,stmfx.yaml
delete mode 100644 Documentation/devicetree/bindings/mfd/stmfx.txt
delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt
diff --git a/Documentation/devicetree/bindings/mfd/st,stmfx.yaml b/Documentation/devicetree/bindings/mfd/st,stmfx.yaml
new file mode 100644
index 000000000000..0ce56a0da553
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/st,stmfx.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/st,stmfx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectonics Multi-Function eXpander (STMFX) bindings
+
+description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
+ communication with the main MCU. Its main features are GPIO expansion,
+ main MCU IDD measurement (IDD is the amount of current that flows
+ through VDD) and resistive touchscreen controller.
+
+maintainers:
+ - Amelie Delaunay <amelie.delaunay@st.com>
+
+properties:
+ compatible:
+ const: st,stmfx-0300
+
+ reg:
+ enum: [ 0x42, 0x43 ]
+
+ interrupts:
+ maxItems: 1
+
+ drive-open-drain: true
+
+ vdd-supply:
+ maxItems: 1
+
+ pinctrl:
+ type: object
+
+ properties:
+ compatible:
+ const: st,stmfx-0300-pinctrl
+
+ "#gpio-cells":
+ const: 2
+
+ "#interrupt-cells":
+ const: 2
+
+ gpio-controller: true
+
+ interrupt-controller: true
+
+ gpio-ranges:
+ description: if all STMFX pins[24:0] are available (no other STMFX function in use),
+ you should use gpio-ranges = <&stmfx_pinctrl 0 0 24>;
+ if agpio[3:0] are not available (STMFX Touchscreen function in use),
+ you should use gpio-ranges = <&stmfx_pinctrl 0 0 16>, <&stmfx_pinctrl 20 20 4>;
+ if agpio[7:4] are not available (STMFX IDD function in use),
+ you should use gpio-ranges = <&stmfx_pinctrl 0 0 20>;
+ maxItems: 1
+
+ patternProperties:
+ "^[a-zA-Z]*-pins$":
+ type: object
+
+ allOf:
+ - $ref: ../pinctrl/pinmux-node.yaml
+
+ properties:
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-pin-default: true
+ bias-pull-down: true
+ drive-open-drain: true
+ drive-push-pull: true
+ output-high: true
+ output-low: true
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+ required:
+ - compatible
+ - "#gpio-cells"
+ - "#interrupt-cells"
+ - gpio-controller
+ - interrupt-controller
+ - gpio-ranges
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ stmfx@42 {
+ compatible = "st,stmfx-0300";
+ reg = <0x42>;
+ interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpioi>;
+ vdd-supply = <&v3v3>;
+
+ stmfx_pinctrl: pinctrl {
+ compatible = "st,stmfx-0300-pinctrl";
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ gpio-ranges = <&stmfx_pinctrl 0 0 24>;
+
+ joystick_pins: joystick-pins {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mfd/stmfx.txt b/Documentation/devicetree/bindings/mfd/stmfx.txt
deleted file mode 100644
index f0c2f7fcf5c7..000000000000
--- a/Documentation/devicetree/bindings/mfd/stmfx.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-STMicroelectonics Multi-Function eXpander (STMFX) Core bindings
-
-ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
-communication with the main MCU. Its main features are GPIO expansion, main
-MCU IDD measurement (IDD is the amount of current that flows through VDD) and
-resistive touchscreen controller.
-
-Required properties:
-- compatible: should be "st,stmfx-0300".
-- reg: I2C slave address of the device.
-- interrupts: interrupt specifier triggered by MFX_IRQ_OUT signal.
- Please refer to ../interrupt-controller/interrupt.txt
-
-Optional properties:
-- drive-open-drain: configure MFX_IRQ_OUT as open drain.
-- vdd-supply: phandle of the regulator supplying STMFX.
-
-Example:
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
- vdd-supply = <&v3v3>;
- };
-
-Please refer to ../pinctrl/pinctrl-stmfx.txt for STMFX GPIO expander function bindings.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt
deleted file mode 100644
index c1b4c1819b84..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander bindings
-
-ST Multi-Function eXpander (STMFX) offers up to 24 GPIOs expansion.
-Please refer to ../mfd/stmfx.txt for STMFX Core bindings.
-
-Required properties:
-- compatible: should be "st,stmfx-0300-pinctrl".
-- #gpio-cells: should be <2>, the first cell is the GPIO number and the second
- cell is the gpio flags in accordance with <dt-bindings/gpio/gpio.h>.
-- gpio-controller: marks the device as a GPIO controller.
-- #interrupt-cells: should be <2>, the first cell is the GPIO number and the
- second cell is the interrupt flags in accordance with
- <dt-bindings/interrupt-controller/irq.h>.
-- interrupt-controller: marks the device as an interrupt controller.
-- gpio-ranges: specifies the mapping between gpio controller and pin
- controller pins. Check "Concerning gpio-ranges property" below.
-Please refer to ../gpio/gpio.txt.
-
-Please refer to pinctrl-bindings.txt for pin configuration.
-
-Required properties for pin configuration sub-nodes:
-- pins: list of pins to which the configuration applies.
-
-Optional properties for pin configuration sub-nodes (pinconf-generic ones):
-- bias-disable: disable any bias on the pin.
-- bias-pull-up: the pin will be pulled up.
-- bias-pull-pin-default: use the pin-default pull state.
-- bias-pull-down: the pin will be pulled down.
-- drive-open-drain: the pin will be driven with open drain.
-- drive-push-pull: the pin will be driven actively high and low.
-- output-high: the pin will be configured as an output driving high level.
-- output-low: the pin will be configured as an output driving low level.
-
-Note that STMFX pins[15:0] are called "gpio[15:0]", and STMFX pins[23:16] are
-called "agpio[7:0]". Example, to refer to pin 18 of STMFX, use "agpio2".
-
-Concerning gpio-ranges property:
-- if all STMFX pins[24:0] are available (no other STMFX function in use), you
- should use gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-- if agpio[3:0] are not available (STMFX Touchscreen function in use), you
- should use gpio-ranges = <&stmfx_pinctrl 0 0 16>, <&stmfx_pinctrl 20 20 4>;
-- if agpio[7:4] are not available (STMFX IDD function in use), you
- should use gpio-ranges = <&stmfx_pinctrl 0 0 20>;
-
-
-Example:
-
- stmfx: stmfx@42 {
- ...
-
- stmfx_pinctrl: stmfx-pin-controller {
- compatible = "st,stmfx-0300-pinctrl";
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- gpio-controller;
- interrupt-controller;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- drive-push-pull;
- bias-pull-up;
- };
- };
- };
-
-Example of STMFX GPIO consumers:
-
- joystick {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- orange {
- gpios = <&stmfx_pinctrl 17 1>;
- };
-
- blue {
- gpios = <&stmfx_pinctrl 19 1>;
- };
- }
--
2.15.0
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^ permalink raw reply related
* [PATCH v6 1/7] clk: JZ4780: Add function for enable the second core.
From: 周琰杰 (Zhou Yanjie) @ 2020-02-20 16:24 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, tglx, ralf, paulburton,
jiaxun.yang, chenhc, sboyd, mturquette, mark.rutland, robh+dt,
daniel.lezcano, paul, geert+renesas, krzk, ebiederm,
miquel.raynal, keescook, sernia.zhou, zhenwenjin, dongsheng.qiu
In-Reply-To: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com>
Add "jz4780_core1_enable()" for enable the second core of JZ4780,
prepare for later commits.
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
Notes:
v5:
New patch, split from [1/6] in v4.
v5->v6:
simplify code with "readl_poll_timeout()".
drivers/clk/ingenic/jz4780-cgu.c | 55 ++++++++++++++++++++++++++++++++++++----
1 file changed, 50 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index d07fff1..92102d8 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -9,14 +9,16 @@
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/of.h>
+
#include <dt-bindings/clock/jz4780-cgu.h>
#include "cgu.h"
#include "pm.h"
/* CGU register offsets */
#define CGU_REG_CLOCKCONTROL 0x00
-#define CGU_REG_PLLCONTROL 0x0c
+#define CGU_REG_LCR 0x04
#define CGU_REG_APLL 0x10
#define CGU_REG_MPLL 0x14
#define CGU_REG_EPLL 0x18
@@ -46,8 +48,8 @@
#define CGU_REG_CLOCKSTATUS 0xd4
/* bits within the OPCR register */
-#define OPCR_SPENDN0 (1 << 7)
-#define OPCR_SPENDN1 (1 << 6)
+#define OPCR_SPENDN0 BIT(7)
+#define OPCR_SPENDN1 BIT(6)
/* bits within the USBPCR register */
#define USBPCR_USB_MODE BIT(31)
@@ -88,6 +90,13 @@
#define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT)
#define USBVBFIL_USBVBFIL_MASK (0xffff)
+/* bits within the LCR register */
+#define LCR_PD_SCPU BIT(31)
+#define LCR_SCPUS BIT(27)
+
+/* bits within the CLKGR1 register */
+#define CLKGR1_CORE1 BIT(15)
+
static struct ingenic_cgu *cgu;
static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)
@@ -205,6 +214,42 @@ static const struct clk_ops jz4780_otg_phy_ops = {
.set_rate = jz4780_otg_phy_set_rate,
};
+static int jz4780_core1_enable(struct clk_hw *hw)
+{
+ struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+ struct ingenic_cgu *cgu = ingenic_clk->cgu;
+ const unsigned int timeout = 5000;
+ unsigned long flags;
+ int retval;
+ u32 lcr, clkgr1;
+
+ spin_lock_irqsave(&cgu->lock, flags);
+
+ lcr = readl(cgu->base + CGU_REG_LCR);
+ lcr &= ~LCR_PD_SCPU;
+ writel(lcr, cgu->base + CGU_REG_LCR);
+
+ clkgr1 = readl(cgu->base + CGU_REG_CLKGR1);
+ clkgr1 &= ~CLKGR1_CORE1;
+ writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
+
+ spin_unlock_irqrestore(&cgu->lock, flags);
+
+ /* wait for the CPU to be powered up */
+ retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr,
+ !(lcr & LCR_SCPUS), 10, timeout);
+ if (retval == -ETIMEDOUT) {
+ pr_err("%s: Wait for power up core1 timeout\n", __func__);
+ return retval;
+ }
+
+ return 0;
+}
+
+static const struct clk_ops jz4780_core1_ops = {
+ .enable = jz4780_core1_enable,
+};
+
static const s8 pll_od_encoding[16] = {
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
@@ -701,9 +746,9 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
},
[JZ4780_CLK_CORE1] = {
- "core1", CGU_CLK_GATE,
+ "core1", CGU_CLK_CUSTOM,
.parents = { JZ4780_CLK_CPU, -1, -1, -1 },
- .gate = { CGU_REG_CLKGR1, 15 },
+ .custom = { &jz4780_core1_ops },
},
};
--
2.7.4
^ permalink raw reply related
* [PATCH] arm64: dts: meson-gxbb-vega-s95: fix bindings and bluetooth node
From: Christian Hewitt @ 2020-02-20 16:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kevin Hilman, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel
Cc: Oleg Ivanov, Christian Hewitt
This adds missing bindings and fixes BT output.
Fixes: b07a11dbdfeb ("arm64: dts: meson-gxbb-vega-s95: fix WiFi/BT module support")
Suggested-by: Oleg Ivanov <balbes-150@yandex.ru>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 5eab3df..0012779 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -4,6 +4,8 @@
*/
#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";
@@ -245,6 +247,9 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
};
};
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH v5 1/4] xfs: Refactor xfs_isilocked()
From: Chaitanya Kulkarni @ 2020-02-20 16:25 UTC (permalink / raw)
To: Pavel Reichl; +Cc: linux-xfs@vger.kernel.org
In-Reply-To: <CAJc7PzWrcXpcraAMEfMi6idTeYa9o009tZLOSzp3A6sC-km3DA@mail.gmail.com>
On 02/17/2020 02:56 AM, Pavel Reichl wrote:
> On Sat, Feb 15, 2020 at 2:38 AM Chaitanya Kulkarni
> <Chaitanya.Kulkarni@wdc.com> wrote:
>> >
>> >Since it has more than one patch and version 5,
>> >I couldn't find the cover-letter and a change log for this
>> >series, is there a particular reason why it is not present or I
>> >missed it?
>> >
>> >On 02/14/2020 11:00 AM, Pavel Reichl wrote:
>>> > >Refactor xfs_isilocked() to use newly introduced __xfs_rwsem_islocked().
>>> > >__xfs_rwsem_islocked() is a helper function which encapsulates checking
>>> > >state of rw_semaphores hold by inode.
>>> > >
>>> > >
>> >
>> >
> Hi Chaitanya,
>
> sorry for the absence of the changelog I forgot to add it - that was
> not on purpose.
>
> To summarize the changes: I moved the asserts from the first patch to
> the third as suggested by Eric and changed the commit messages as
> suggested by Dave.
Thanks.
>
> Regarding the missing cover-letter it was same since version one and I
> was not sure I should resend it with every new version, should I?
It's okay, it just makes re-viewer's life easier to look for the change.
>
> Thanks you for your comments.
>
> Best regards
>
> Pavel Reichl
>
>
^ permalink raw reply
* Re: [Xen-devel] [PATCH v6 4/6] libxl: allow creation of domains with a specified or random domid
From: Ian Jackson @ 2020-02-20 16:25 UTC (permalink / raw)
To: Paul Durrant
Cc: Stefano Stabellini, Julien Grall, Wei Liu, Konrad Rzeszutek Wilk,
Andrew Cooper, Jason Andryuk, George Dunlap, Jan Beulich,
Anthony Perard, xen-devel@lists.xenproject.org
In-Reply-To: <20200219093754.2924-5-pdurrant@amazon.com>
Paul Durrant writes ("[PATCH v6 4/6] libxl: allow creation of domains with a specified or random domid"):
> This patch adds a 'domid' field to libxl_domain_create_info and then
> modifies libxl__domain_make() to have Xen use that value if it is valid.
> If the domid value is invalid then Xen will choose the domid, as before,
> unless the value is the new special RANDOM_DOMID value added to the API.
> This value instructs libxl__domain_make() to choose a random domid value
> for Xen to use.
>
> If Xen determines that a domid specified to or chosen by
> libxl__domain_make() co-incides with an existing domain then the create
> operation will fail. In this case, if RANDOM_DOMID was specified to
> libxl__domain_make() then a new random value will be chosen and the create
> operation will be re-tried, otherwise libxl__domain_make() will fail.
>
> After Xen has successfully created a new domain, libxl__domain_make() will
> check whether its domid matches any recently used domid values. If it does
> then the domain will be destroyed. If the domid used in creation was
> specified to libxl__domain_make() then it will fail at this point,
> otherwise the create operation will be re-tried with either a new random
> or Xen-selected domid value.
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Thanks. The logic seems a lot clearer now.
Ian.
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^ permalink raw reply
* [PATCH v6 5/7] dt-bindings: MIPS: Document Ingenic SoCs binding.
From: 周琰杰 (Zhou Yanjie) @ 2020-02-20 16:24 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, tglx, ralf, paulburton,
jiaxun.yang, chenhc, sboyd, mturquette, mark.rutland, robh+dt,
daniel.lezcano, paul, geert+renesas, krzk, ebiederm,
miquel.raynal, keescook, sernia.zhou, zhenwenjin, dongsheng.qiu
In-Reply-To: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com>
Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
Change the two Document from txt to yaml.
v2->v3:
Fix formatting errors.
v3->v4:
Fix bugs in the two yaml files.
v4->v5:
No change.
v5->v6:
Rewrite the two yaml files.
.../bindings/mips/ingenic/ingenic,cpu.yaml | 61 ++++++++++++++++++++++
.../bindings/mips/ingenic/ingenic,soc.yaml | 34 ++++++++++++
2 files changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc.yaml
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
new file mode 100644
index 00000000..ad1fd86
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic XBurst family CPUs
+
+maintainers:
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
+description: |
+ Ingenic XBurst family CPUs shall have the following properties.
+
+properties:
+ compatible:
+ oneOf:
+
+ - description: Ingenic XBurst®1 CPU Core
+ items:
+ - const: ingenic,xburst
+
+ - description: Ingenic XBurst®2 CPU Core
+ items:
+ - const: ingenic,xburst2
+
+ reg:
+ description: |
+ The number of the CPU.
+
+required:
+ - device_type
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4780-cgu.h>
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+
+ clocks = <&cgu JZ4780_CLK_CPU>;
+ clock-names = "cpu";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <1>;
+
+ clocks = <&cgu JZ4780_CLK_CORE1>;
+ clock-names = "cpu";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc.yaml
new file mode 100644
index 00000000..8943e73
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/ingenic/ingenic,soc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic SoCs with XBurst CPU inside.
+
+maintainers:
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
+description: |
+ Ingenic SoCs with XBurst CPU inside shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Ingenic JZ47 Series Mobile Application Processor
+ items:
+ - const: ingenic,jz4740
+ - const: ingenic,jz4725b
+ - const: ingenic,jz4760
+ - const: ingenic,jz4760b
+ - const: ingenic,jz4770
+ - const: ingenic,jz4780
+
+ - description: Ingenic X Series IoT Application Processor
+ items:
+ - const: ingenic,x1000
+ - const: ingenic,x1000e
+ - const: ingenic,x1500
+...
--
2.7.4
^ permalink raw reply related
* [PATCH] arm64: dts: meson-gxbb-vega-s95: fix bindings and bluetooth node
From: Christian Hewitt @ 2020-02-20 16:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kevin Hilman, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel
Cc: Christian Hewitt, Oleg Ivanov
This adds missing bindings and fixes BT output.
Fixes: b07a11dbdfeb ("arm64: dts: meson-gxbb-vega-s95: fix WiFi/BT module support")
Suggested-by: Oleg Ivanov <balbes-150@yandex.ru>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 5eab3df..0012779 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -4,6 +4,8 @@
*/
#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";
@@ -245,6 +247,9 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
};
};
--
2.7.4
^ permalink raw reply related
* Introduce SMP support for CI20 (based on JZ4780) v6.
From: 周琰杰 (Zhou Yanjie) @ 2020-02-20 16:24 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, tglx, ralf, paulburton,
jiaxun.yang, chenhc, sboyd, mturquette, mark.rutland, robh+dt,
daniel.lezcano, paul, geert+renesas, krzk, ebiederm,
miquel.raynal, keescook, sernia.zhou, zhenwenjin, dongsheng.qiu
Introduce SMP support for MIPS Creator CI20, which is
based on Ingenic JZ4780 SoC.
^ permalink raw reply
* [PATCH v3] dt-bindings: mfd: Convert stmfx bindings to json-schema
From: Benjamin Gaignard @ 2020-02-20 16:22 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, alexandre.torgue, linus.walleij,
amelie.delaunay
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
linux-gpio, Benjamin Gaignard
Convert stmfx bindings to json-schema
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
.../devicetree/bindings/mfd/st,stmfx.yaml | 124 +++++++++++++++++++++
Documentation/devicetree/bindings/mfd/stmfx.txt | 28 -----
.../devicetree/bindings/pinctrl/pinctrl-stmfx.txt | 116 -------------------
3 files changed, 124 insertions(+), 144 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/st,stmfx.yaml
delete mode 100644 Documentation/devicetree/bindings/mfd/stmfx.txt
delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt
diff --git a/Documentation/devicetree/bindings/mfd/st,stmfx.yaml b/Documentation/devicetree/bindings/mfd/st,stmfx.yaml
new file mode 100644
index 000000000000..0ce56a0da553
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/st,stmfx.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/st,stmfx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectonics Multi-Function eXpander (STMFX) bindings
+
+description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
+ communication with the main MCU. Its main features are GPIO expansion,
+ main MCU IDD measurement (IDD is the amount of current that flows
+ through VDD) and resistive touchscreen controller.
+
+maintainers:
+ - Amelie Delaunay <amelie.delaunay@st.com>
+
+properties:
+ compatible:
+ const: st,stmfx-0300
+
+ reg:
+ enum: [ 0x42, 0x43 ]
+
+ interrupts:
+ maxItems: 1
+
+ drive-open-drain: true
+
+ vdd-supply:
+ maxItems: 1
+
+ pinctrl:
+ type: object
+
+ properties:
+ compatible:
+ const: st,stmfx-0300-pinctrl
+
+ "#gpio-cells":
+ const: 2
+
+ "#interrupt-cells":
+ const: 2
+
+ gpio-controller: true
+
+ interrupt-controller: true
+
+ gpio-ranges:
+ description: if all STMFX pins[24:0] are available (no other STMFX function in use),
+ you should use gpio-ranges = <&stmfx_pinctrl 0 0 24>;
+ if agpio[3:0] are not available (STMFX Touchscreen function in use),
+ you should use gpio-ranges = <&stmfx_pinctrl 0 0 16>, <&stmfx_pinctrl 20 20 4>;
+ if agpio[7:4] are not available (STMFX IDD function in use),
+ you should use gpio-ranges = <&stmfx_pinctrl 0 0 20>;
+ maxItems: 1
+
+ patternProperties:
+ "^[a-zA-Z]*-pins$":
+ type: object
+
+ allOf:
+ - $ref: ../pinctrl/pinmux-node.yaml
+
+ properties:
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-pin-default: true
+ bias-pull-down: true
+ drive-open-drain: true
+ drive-push-pull: true
+ output-high: true
+ output-low: true
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+ required:
+ - compatible
+ - "#gpio-cells"
+ - "#interrupt-cells"
+ - gpio-controller
+ - interrupt-controller
+ - gpio-ranges
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ stmfx@42 {
+ compatible = "st,stmfx-0300";
+ reg = <0x42>;
+ interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpioi>;
+ vdd-supply = <&v3v3>;
+
+ stmfx_pinctrl: pinctrl {
+ compatible = "st,stmfx-0300-pinctrl";
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ gpio-ranges = <&stmfx_pinctrl 0 0 24>;
+
+ joystick_pins: joystick-pins {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mfd/stmfx.txt b/Documentation/devicetree/bindings/mfd/stmfx.txt
deleted file mode 100644
index f0c2f7fcf5c7..000000000000
--- a/Documentation/devicetree/bindings/mfd/stmfx.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-STMicroelectonics Multi-Function eXpander (STMFX) Core bindings
-
-ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
-communication with the main MCU. Its main features are GPIO expansion, main
-MCU IDD measurement (IDD is the amount of current that flows through VDD) and
-resistive touchscreen controller.
-
-Required properties:
-- compatible: should be "st,stmfx-0300".
-- reg: I2C slave address of the device.
-- interrupts: interrupt specifier triggered by MFX_IRQ_OUT signal.
- Please refer to ../interrupt-controller/interrupt.txt
-
-Optional properties:
-- drive-open-drain: configure MFX_IRQ_OUT as open drain.
-- vdd-supply: phandle of the regulator supplying STMFX.
-
-Example:
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
- vdd-supply = <&v3v3>;
- };
-
-Please refer to ../pinctrl/pinctrl-stmfx.txt for STMFX GPIO expander function bindings.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt
deleted file mode 100644
index c1b4c1819b84..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander bindings
-
-ST Multi-Function eXpander (STMFX) offers up to 24 GPIOs expansion.
-Please refer to ../mfd/stmfx.txt for STMFX Core bindings.
-
-Required properties:
-- compatible: should be "st,stmfx-0300-pinctrl".
-- #gpio-cells: should be <2>, the first cell is the GPIO number and the second
- cell is the gpio flags in accordance with <dt-bindings/gpio/gpio.h>.
-- gpio-controller: marks the device as a GPIO controller.
-- #interrupt-cells: should be <2>, the first cell is the GPIO number and the
- second cell is the interrupt flags in accordance with
- <dt-bindings/interrupt-controller/irq.h>.
-- interrupt-controller: marks the device as an interrupt controller.
-- gpio-ranges: specifies the mapping between gpio controller and pin
- controller pins. Check "Concerning gpio-ranges property" below.
-Please refer to ../gpio/gpio.txt.
-
-Please refer to pinctrl-bindings.txt for pin configuration.
-
-Required properties for pin configuration sub-nodes:
-- pins: list of pins to which the configuration applies.
-
-Optional properties for pin configuration sub-nodes (pinconf-generic ones):
-- bias-disable: disable any bias on the pin.
-- bias-pull-up: the pin will be pulled up.
-- bias-pull-pin-default: use the pin-default pull state.
-- bias-pull-down: the pin will be pulled down.
-- drive-open-drain: the pin will be driven with open drain.
-- drive-push-pull: the pin will be driven actively high and low.
-- output-high: the pin will be configured as an output driving high level.
-- output-low: the pin will be configured as an output driving low level.
-
-Note that STMFX pins[15:0] are called "gpio[15:0]", and STMFX pins[23:16] are
-called "agpio[7:0]". Example, to refer to pin 18 of STMFX, use "agpio2".
-
-Concerning gpio-ranges property:
-- if all STMFX pins[24:0] are available (no other STMFX function in use), you
- should use gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-- if agpio[3:0] are not available (STMFX Touchscreen function in use), you
- should use gpio-ranges = <&stmfx_pinctrl 0 0 16>, <&stmfx_pinctrl 20 20 4>;
-- if agpio[7:4] are not available (STMFX IDD function in use), you
- should use gpio-ranges = <&stmfx_pinctrl 0 0 20>;
-
-
-Example:
-
- stmfx: stmfx@42 {
- ...
-
- stmfx_pinctrl: stmfx-pin-controller {
- compatible = "st,stmfx-0300-pinctrl";
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- gpio-controller;
- interrupt-controller;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- drive-push-pull;
- bias-pull-up;
- };
- };
- };
-
-Example of STMFX GPIO consumers:
-
- joystick {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- orange {
- gpios = <&stmfx_pinctrl 17 1>;
- };
-
- blue {
- gpios = <&stmfx_pinctrl 19 1>;
- };
- }
--
2.15.0
^ permalink raw reply related
* [PATCH] arm64: dts: meson-gxbb-vega-s95: fix bindings and bluetooth node
From: Christian Hewitt @ 2020-02-20 16:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kevin Hilman, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel
Cc: Oleg Ivanov, Christian Hewitt
This adds missing bindings and fixes BT output.
Fixes: b07a11dbdfeb ("arm64: dts: meson-gxbb-vega-s95: fix WiFi/BT module support")
Suggested-by: Oleg Ivanov <balbes-150@yandex.ru>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 5eab3df..0012779 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -4,6 +4,8 @@
*/
#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";
@@ -245,6 +247,9 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
};
};
--
2.7.4
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related
* Re: a bug(BUG: kernel NULL pointer dereference) of ib or mlx happened in 5.4.21 but not in 5.4.20
From: Wang Yugui @ 2020-02-20 16:26 UTC (permalink / raw)
To: Leon Romanovsky; +Cc: Chuck Lever, linux-rdma
In-Reply-To: <20200220140547.GE209126@unreal>
Hi, Leon, Chuck
It is still broken even with the hotfix(https://patchwork.kernel.org/patch/11387567/) for 5.4.21.
the call stack is almost the same.
Feb 20 23:49:53 T630 kernel: Call Trace:
Feb 20 23:49:53 T630 kernel: port_pkey_list_insert+0x30/0x1a0 [ib_core]
Feb 20 23:49:53 T630 kernel: ? kmem_cache_alloc_trace+0x219/0x230
Feb 20 23:49:53 T630 kernel: ib_security_modify_qp+0x244/0x3b0 [ib_core]
Feb 20 23:49:53 T630 kernel: _ib_modify_qp+0x1c0/0x3c0 [ib_core]
Feb 20 23:49:53 T630 kernel: ? dma_pool_free+0x24/0xc0
Feb 20 23:49:53 T630 kernel: ipoib_init_qp+0x77/0x190 [ib_ipoib]
Feb 20 23:49:53 T630 kernel: ? __mlx4_ib_query_pkey+0xe7/0x110 [mlx4_ib]
Feb 20 23:49:53 T630 kernel: ? ib_find_pkey+0x98/0xe0 [ib_core]
Feb 20 23:49:53 T630 kernel: ipoib_ib_dev_open_default+0x1a/0x180 [ib_ipoib]
Feb 20 23:49:53 T630 kernel: ipoib_ib_dev_open+0x66/0xa0 [ib_ipoib]
Feb 20 23:49:53 T630 kernel: ipoib_open+0x44/0x110 [ib_ipoib]
Feb 20 23:49:53 T630 kernel: __dev_open+0xcd/0x160
Feb 20 23:49:53 T630 kernel: __dev_change_flags+0x1ad/0x220
Feb 20 23:49:53 T630 kernel: ? __dev_notify_flags+0x95/0xf0
Feb 20 23:49:53 T630 kernel: dev_change_flags+0x21/0x60
Feb 20 23:49:53 T630 kernel: do_setlink+0x320/0xf00
Feb 20 23:49:53 T630 kernel: ? __nla_validate_parse+0x51/0x840
Feb 20 23:49:53 T630 kernel: ? xas_load+0x8/0x80
Feb 20 23:49:53 T630 kernel: ? __update_load_avg_cfs_rq+0x1d5/0x2c0
Feb 20 23:49:53 T630 kernel: ? cpumask_next+0x17/0x20
Feb 20 23:49:53 T630 kernel: ? __snmp6_fill_stats64.isra.56+0x6b/0x110
Feb 20 23:49:53 T630 kernel: ? __nla_validate_parse+0x51/0x840
Feb 20 23:49:53 T630 kernel: __rtnl_newlink+0x53d/0x890
Feb 20 23:49:53 T630 kernel: ? __nla_reserve+0x38/0x50
Feb 20 23:49:53 T630 kernel: ? __nla_put+0xc/0x20
Feb 20 23:49:53 T630 kernel: ? __nla_reserve+0x38/0x50
Feb 20 23:49:53 T630 kernel: ? __nla_put+0xc/0x20
Feb 20 23:49:53 T630 kernel: ? nla_put+0x2f/0x40
Feb 20 23:49:53 T630 kernel: ? __nla_reserve+0x38/0x50
Feb 20 23:49:53 T630 kernel: ? __nla_put+0xc/0x20
Feb 20 23:49:53 T630 kernel: ? nla_put+0x2f/0x40
Feb 20 23:49:53 T630 kernel: ? rt6_fill_node+0x2d4/0x850
Feb 20 23:49:53 T630 kernel: ? _cond_resched+0x15/0x30
Feb 20 23:49:53 T630 kernel: ? kmem_cache_alloc_trace+0x1c9/0x230
Feb 20 23:49:53 T630 kernel: rtnl_newlink+0x43/0x60
Feb 20 23:49:53 T630 kernel: rtnetlink_rcv_msg+0x2b1/0x360
Feb 20 23:49:53 T630 kernel: ? __kmalloc_node_track_caller+0x241/0x300
Feb 20 23:49:53 T630 kernel: ? _cond_resched+0x15/0x30
Feb 20 23:49:53 T630 kernel: ? rtnl_calcit.isra.32+0x110/0x110
Feb 20 23:49:53 T630 kernel: netlink_rcv_skb+0x49/0x110
Feb 20 23:49:53 T630 kernel: netlink_unicast+0x191/0x220
Feb 20 23:49:53 T630 kernel: netlink_sendmsg+0x21d/0x3f0
Feb 20 23:49:53 T630 kernel: sock_sendmsg+0x5b/0x60
Feb 20 23:49:53 T630 kernel: ____sys_sendmsg+0x1eb/0x260
Feb 20 23:49:53 T630 kernel: ? copy_msghdr_from_user+0xdb/0x160
Feb 20 23:49:53 T630 kernel: ___sys_sendmsg+0x7c/0xc0
Feb 20 23:49:53 T630 kernel: ? do_filp_open+0xa7/0x100
Feb 20 23:49:53 T630 kernel: ? netdev_run_todo+0x5e/0x290
Feb 20 23:49:53 T630 kernel: ? list_lru_add+0xb7/0x1d0
Feb 20 23:49:53 T630 kernel: __sys_sendmsg+0x57/0xa0
Feb 20 23:49:53 T630 kernel: do_syscall_64+0x5b/0x180
Feb 20 23:49:53 T630 kernel: entry_SYSCALL_64_after_hwframe+0x44/0xa9
This card have 2 port, and port 1 is set as InfiniBand, port 2
is set as Ethernet.
# ibstat
CA 'mlx4_0'
CA type: MT4099
Number of ports: 2
Firmware version: 2.42.5000
Hardware version: 1
Node GUID: 0xe41d2d03007b4080
System image GUID: 0xe41d2d03007b4083
Port 1:
State: Down
Physical state: Polling
Rate: 10
Base lid: 0
LMC: 0
SM lid: 0
Capability mask: 0x02594868
Port GUID: 0xe41d2d03007b4081
Link layer: InfiniBand
Port 2:
State: Down
Physical state: Disabled
Rate: 40
Base lid: 0
LMC: 0
SM lid: 0
Capability mask: 0x00010000
Port GUID: 0xe61d2dfffe7b4082
Link layer: Ethernet
Best Regards
王玉贵
2020/02/21
> On Thu, Feb 20, 2020 at 08:57:29AM -0500, Chuck Lever wrote:
> > Hello!
> >
> > Thanks for your bug report.
> >
> >
> > > On Feb 19, 2020, at 10:22 PM, Wang Yugui <wangyugui@e16-tech.com> wrote:
> > >
> > > Hi, chuck.lever
> > >
> > > a bug(BUG: kernel NULL pointer dereference) of ib or mlx happened in 5.4.21 but not in 5.4.20.
> > >
> > > maybe some releationship to xprtrdma-fix-dma-scatter-gather-list-mapping-imbalance.patch
> >
> > I don't see an obvious connection to fix-dma-scatter-gather-list-mapping-imbalance.
> > The backtrace below is through IPoIB code paths. Those have nothing to do with
> > NFS/RDMA, which is the only ULP code that is changed by my commit.
> >
> >
> > > maybe the info is useful.
> >
> > I'm copying linux-rdma for a bigger set of eyeballs.
> >
> > My knee-jerk recommendation is that if you have a reliable reproducer, try "git bisect"
> > between .20 and .21 to nail down a specific commit where the BUG starts to occur.
>
> No need to bisect, it is me who broke.
> The fix is already accepted, but not yet merged.
> https://patchwork.kernel.org/patch/11387567/
>
> Thanks
--------------------------------------
北京京垓科技有限公司
王玉贵 wangyugui@e16-tech.com
电话：+86-136-71123776
^ permalink raw reply
* Re: Security Working Group meeting - this Wednesday February 19 - summary results
From: Patrick Williams @ 2020-02-20 16:26 UTC (permalink / raw)
To: Joseph Reynolds; +Cc: openbmc
In-Reply-To: <f4d9d6f6-277e-8c8b-6b5c-d0577eaa82cc@linux.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1902 bytes --]
On Wed, Feb 19, 2020 at 05:05:09PM -0600, Joseph Reynolds wrote:
> On 2/17/20 4:29 PM, Joseph Reynolds wrote:
> > 6. (Bruce via email): BMCWeb Cert valid for 10 years -
> > https://lists.ozlabs.org/pipermail/openbmc/2020-February/020488.html
>
> Change BMCweb’s default self-signed cert to a maximum of 825 days.
> Recommend 30 days.
>
> When this is done, if BMCWeb generates a self-signed cert, and it is not
> replaced, and the BMC’s time is sane, then browsers that connect to BMCWeb
> will start to complain after 30 days.
>
> The recovery is: The BMC admin should install a valid BMCWeb site identity
> cert, then clients can re-connect to the BMC. (This will serve the updated
> cert and make the browser happy.)
>
> The “BMC Admin guide” should talk about installing your own cert.
>
> See docs here: https://github.com/openbmc/bmcweb/#configuration
>
> Ass code here: https://github.com/openbmc/bmcweb/blob/91243c3b28b1df66e682f5a3ee96341fdc516b5a/include/ssl_key_handler.hpp#L205
>
> Will there be a warning for the BMC admin (that the BMCWeb site cert will
> expire soon)? (And don’t rely on a warning from the browser itself.)
If I read this correctly, the side-effect of this proposed change is:
- If I leave my BMC running for 30 days without it crashing, the
certificate it presents will have become expired and no longer
valid.
Is that true? Can we put something into bmcweb to detect its own
certificate has expired and generate a new one?
I know self-signed certs aren't great, but the minute I have more than 6
systems I'm not going to want to follow some "BMC Admin Guide" to update
certificates by hand. So we're effectively forcing everyone to develop
some kind of certificate management infrastructure, without providing
(or pointing to an existing) implementation.
--
Patrick Williams
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^ permalink raw reply
* [PATCH] iommu: Force iommu shutdown on panic.
From: John Donnelly @ 2020-02-20 16:26 UTC (permalink / raw)
To: linux-kernel
This eliminates intermitten kdump hangs reported on AMD/x86 servers
with iommu enabled (iommu=on) regardless if iommu features are
used or not, on 5.4 kernels. When kdump fails to initialize and run, no vmcore
(crash dumps) are captured.
Derived from the upsteam commit: iommu/vt-d: Turn off translations at shutdown.
Signed-off-by: John Donnelly <john.p.donnelly@oracle.com>
Reviewed-by: Jack Vogel <jack.vogel@oracle.com>
---
arch/x86/include/asm/x86_init.h | 2 +-
arch/x86/kernel/amd_gart_64.c | 2 +-
arch/x86/kernel/reboot.c | 2 +-
arch/x86/kernel/x86_init.c | 2 +-
drivers/iommu/amd_iommu_init.c | 8 ++++----
drivers/iommu/intel-iommu.c | 9 ++++++---
include/linux/dmar.h | 4 ++--
kernel/panic.c | 7 +++++++
8 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 96d9cd208610..06233f57b7c9 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -270,7 +270,7 @@ struct x86_platform_ops {
unsigned long (*calibrate_tsc)(void);
void (*get_wallclock)(struct timespec64 *ts);
int (*set_wallclock)(const struct timespec64 *ts);
- void (*iommu_shutdown)(void);
+ void (*iommu_shutdown)(int panic);
bool (*is_untracked_pat_range)(u64 start, u64 end);
void (*nmi_init)(void);
unsigned char (*get_nmi_reason)(void);
diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c
index 4e5f50236048..2f805cc073ad 100644
--- a/arch/x86/kernel/amd_gart_64.c
+++ b/arch/x86/kernel/amd_gart_64.c
@@ -681,7 +681,7 @@ static const struct dma_map_ops gart_dma_ops = {
.get_required_mask = dma_direct_get_required_mask,
};
-static void gart_iommu_shutdown(void)
+static void gart_iommu_shutdown(int panic)
{
struct pci_dev *dev;
int i;
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 0cc7c0b106bb..fd3c88a4f2e7 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -708,7 +708,7 @@ void native_machine_shutdown(void)
#endif
#ifdef CONFIG_X86_64
- x86_platform.iommu_shutdown();
+ x86_platform.iommu_shutdown(0);
#endif
}
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 85f1a90c55cd..e63719710097 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -28,7 +28,7 @@
void x86_init_noop(void) { }
void __init x86_init_uint_noop(unsigned int unused) { }
static int __init iommu_init_noop(void) { return 0; }
-static void iommu_shutdown_noop(void) { }
+static void iommu_shutdown_noop(int panic) { }
bool __init bool_x86_init_noop(void) { return false; }
void x86_op_int_noop(int cpu) { }
static __init int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; }
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 2759a8d57b7f..a1afc2e2a68c 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -2361,7 +2361,7 @@ static void enable_iommus(void)
enable_iommus_v2();
}
-static void disable_iommus(void)
+static void disable_iommus(int panic)
{
struct amd_iommu *iommu;
@@ -2395,7 +2395,7 @@ static void amd_iommu_resume(void)
static int amd_iommu_suspend(void)
{
/* disable IOMMUs to go out of the way for BIOS */
- disable_iommus();
+ disable_iommus(0);
return 0;
}
@@ -2612,7 +2612,7 @@ static int __init early_amd_iommu_init(void)
/* Disable any previously enabled IOMMUs */
if (!is_kdump_kernel() || amd_iommu_disabled)
- disable_iommus();
+ disable_iommus(0);
if (amd_iommu_irq_remap)
amd_iommu_irq_remap = check_ioapic_information();
@@ -2762,7 +2762,7 @@ static int __init state_next(void)
if (ret) {
free_dma_resources();
if (!irq_remapping_enabled) {
- disable_iommus();
+ disable_iommus(0);
free_iommu_resources();
} else {
struct amd_iommu *iommu;
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 9dc37672bf89..8bc95f4e7d3e 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -4903,7 +4903,7 @@ static void intel_disable_iommus(void)
iommu_disable_translation(iommu);
}
-void intel_iommu_shutdown(void)
+void intel_iommu_shutdown(int panic)
{
struct dmar_drhd_unit *drhd;
struct intel_iommu *iommu = NULL;
@@ -4911,7 +4911,8 @@ void intel_iommu_shutdown(void)
if (no_iommu || dmar_disabled)
return;
- down_write(&dmar_global_lock);
+ if (!panic)
+ down_write(&dmar_global_lock);
/* Disable PMRs explicitly here. */
for_each_iommu(iommu, drhd)
@@ -4920,7 +4921,9 @@ void intel_iommu_shutdown(void)
/* Make sure the IOMMUs are switched off */
intel_disable_iommus();
- up_write(&dmar_global_lock);
+ if (!panic)
+ up_write(&dmar_global_lock);
+
}
static inline struct intel_iommu *dev_to_intel_iommu(struct device *dev)
diff --git a/include/linux/dmar.h b/include/linux/dmar.h
index f64ca27dc210..c4f24bc41169 100644
--- a/include/linux/dmar.h
+++ b/include/linux/dmar.h
@@ -129,7 +129,7 @@ static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg)
#ifdef CONFIG_INTEL_IOMMU
extern int iommu_detected, no_iommu;
extern int intel_iommu_init(void);
-extern void intel_iommu_shutdown(void);
+extern void intel_iommu_shutdown(int panic);
extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg);
extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg);
extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg);
@@ -138,7 +138,7 @@ extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
#else /* !CONFIG_INTEL_IOMMU: */
static inline int intel_iommu_init(void) { return -ENODEV; }
-static inline void intel_iommu_shutdown(void) { }
+static inline void intel_iommu_shutdown(int panic) { }
#define dmar_parse_one_rmrr dmar_res_noop
#define dmar_parse_one_atsr dmar_res_noop
diff --git a/kernel/panic.c b/kernel/panic.c
index b69ee9e76cb2..ee81462d5b1f 100644
--- a/kernel/panic.c
+++ b/kernel/panic.c
@@ -32,6 +32,7 @@
#include <linux/ratelimit.h>
#include <linux/debugfs.h>
#include <asm/sections.h>
+#include <linux/dmar.h>
#define PANIC_TIMER_STEP 100
#define PANIC_BLINK_SPD 18
@@ -213,6 +214,12 @@ void panic(const char *fmt, ...)
buf[len - 1] = '\0';
pr_emerg("Kernel panic - not syncing: %s\n", buf);
+
+#ifdef CONFIG_X86
+ pr_emerg("Shutting down iommu.\n");
+ x86_platform.iommu_shutdown(1);
+#endif
+
#ifdef CONFIG_DEBUG_BUGVERBOSE
/*
* Avoid nested stack-dumping if a panic occurs during oops processing
--
2.20.1
^ permalink raw reply related
* Re: S variable for svn fetcher Was: State of OE world - 2020-02-18
From: Khem Raj @ 2020-02-20 16:26 UTC (permalink / raw)
To: Martin Jansa; +Cc: openembeded-devel, Adrian Bunk
In-Reply-To: <20200220153758.o25tn46hhewgmasd@jama>
On Thu, Feb 20, 2020 at 7:38 AM Martin Jansa <martin.jansa@gmail.com> wrote:
>
> On Thu, Feb 20, 2020 at 05:16:20PM +0200, Adrian Bunk wrote:
> > On Thu, Feb 20, 2020 at 03:48:48PM +0100, Martin Jansa wrote:
> > >...
> > > Any idea why these aren't shown in our build?
> > >...
> >
> > What is your mirror configuration?
> >
> > Default configuration downloads the tarball from [1].
>
> Maybe I'm missing your point, but these aren't fetch issues.
>
> Even when bitbake fetches the tarball (with the svn repo), svn fetcher
> will still do the actual checkout to WORKDIR, so it will fail the same
> when fetching from upstream repo with svn or when using tarball.
>
they could have been fetched long time ago, perhaps it changed in this
area after that
when fetching fresh repos, just guessing
> Cheers,
^ permalink raw reply
* [chrome-os:chromeos-5.4 16/51] net/bluetooth/hci_le_splitter.c:609:3: warning: format '%u' expects argument of type 'unsigned int', but argument 3 has type 'size_t'
From: kbuild test robot @ 2020-02-20 16:27 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1825 bytes --]
tree: https://chromium.googlesource.com/chromiumos/third_party/kernel chromeos-5.4
head: 18103a374146f0808d20c7e8fed1880ccafc9fb0
commit: 42d50b012632da5f5cd873a4db4e53beb907e15a [16/51] Revert "FIXUP: CHROMIUM: Bluetooth: Add BT splitter"
config: x86_64-randconfig-a003-20200220 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.2-10+deb8u1) 4.9.2
reproduce:
git checkout 42d50b012632da5f5cd873a4db4e53beb907e15a
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
net/bluetooth/hci_le_splitter.c: In function 'hci_le_splitter_enq_packet':
>> net/bluetooth/hci_le_splitter.c:609:3: warning: format '%u' expects argument of type 'unsigned int', but argument 3 has type 'size_t' [-Wformat=]
pr_err("enqueue failed - not enough space to enqueue %u bytes over %u\n",
^
vim +609 net/bluetooth/hci_le_splitter.c
602
603 /* always takes ownership of skb */
604 static void hci_le_splitter_enq_packet(struct sk_buff *skb)
605 {
606 mutex_lock(&usr_msg_q_lock);
607 if (MAX_RX_QUEUE_SZ - usr_msg_q_len < skb->len) {
608
> 609 pr_err("enqueue failed - not enough space to enqueue %u bytes over %u\n",
610 skb->len, usr_msg_q_len);
611 kfree_skb(skb);
612 } else {
613 usr_msg_q_len += skb->len;
614 skb_queue_tail(&usr_msg_q, skb);
615 }
616 mutex_unlock(&usr_msg_q_lock);
617
618 /* wake up userspace in either case as we have data */
619 wake_up_interruptible(&usr_msg_wait_q);
620 }
621
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 39238 bytes --]
^ permalink raw reply
* Re: MCE handler gets NIP wrong on MPC8378
From: Christophe Leroy @ 2020-02-20 16:25 UTC (permalink / raw)
To: Radu Rendec; +Cc: linuxppc-dev
In-Reply-To: <CAD5jUk_L0tmy-2YwC9pZA=PXTeVLhq64emF3J5Vz=mVP_VHZ_w@mail.gmail.com>
Le 20/02/2020 à 17:02, Radu Rendec a écrit :
> On 02/20/2020 at 3:38 AM Christophe Leroy <christophe.leroy@c-s.fr> wrote:
>> On 02/19/2020 10:39 PM, Radu Rendec wrote:
>>> On 02/19/2020 at 4:21 PM Christophe Leroy <christophe.leroy@c-s.fr> wrote:
>>>>> Interesting.
>>>>>
>>>>> 0x900 is the adress of the timer interrupt.
>>>>>
>>>>> Would the MCE occur just after the timer interrupt ?
>>>
>>> I doubt that. I'm using a small test module to artificially trigger the
>>> MCE. Basically it's just this (the full code is in my original post):
>>>
>>> bad_addr_base = ioremap(0xf0000000, 0x100);
>>> x = ioread32(bad_addr_base);
>>>
>>> I find it hard to believe that every time I load the module the lwbrx
>>> instruction that triggers the MCE is executed exactly after the timer
>>> interrupt (or that the timer interrupt always occurs close to the lwbrx
>>> instruction).
>>
>> Can you try to see how much time there is between your read and the MCE ?
>> The below should allow it, you'll see first value in r13 and the other
>> in r14 (mce.c is your test code)
>>
>> Also provide the timebase frequency as reported in /proc/cpuinfo
>
> I just ran a test: r13 is 0xda8e0f91 and r14 is 0xdaae0f9c.
>
> # cat /proc/cpuinfo
> processor : 0
> cpu : e300c4
> clock : 800.000004MHz
> revision : 1.1 (pvr 8086 1011)
> bogomips : 200.00
> timebase : 100000000
>
> The difference between r14 and r13 is 0x20000b. Assuming TB is
> incremented with 'timebase' frequency, that means 20.97 milliseconds
> (although the e300 manual says TB is "incremented once every four core
> input clock cycles").
I wouldn't be surprised that the internal CPU clock be twice the input
clock.
So that's long enough to surely get a timer interrupt during every bad
access.
Now we have to understand why SRR1 contains the address of the timer
exception entry and not the address of the bad access.
The value of SRR1 confirms that it comes from 0x900 as MSR[IR] and [DR]
are cleared when interrupts are enabled.
Maybe you should file a support case at NXP. They are usually quite
professionnal at responding.
Christophe
^ permalink raw reply
* Re: switching ARC to 64-bit time_t (Re: [RFC v6 07/23] RISC-V: Use 64-bit time_t and off_t for RV32 and RV64)
From: Helmut Grohne @ 2020-02-20 16:27 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Florian Weimer, GNU C Library, Vineet Gupta, Palmer Dabbelt,
Lukasz Majewski, Zong Li, debian-arm, Alistair Francis,
Adhemerval Zanella, Maciej W. Rozycki, Alistair Francis, arcml,
Joseph Myers
In-Reply-To: <CAK8P3a1b73K+RjfHONWLy_dFUucXxwd+0jTnHmkf6YqwRjit4w@mail.gmail.com>
Hi Arnd,
On Thu, Feb 20, 2020 at 09:31:32AM +0100, Arnd Bergmann wrote:
> > > How do I build a latest RISCV 32-bit kernel + userland - do you have
> > > a buildroot branch somewhere that I can build / test with qemu ?
> >
> > Maybe a bit off topic - there is such QEMU and Yocto/OE based test
> > sandbox for ARM32:
> >
> > https://github.com/lmajewski/meta-y2038
> >
> > (the README provides steps for setup).
>
> (continuing off-topic, with debian-arm and Helmut on Cc)
>
> Would it be possible to take a snapshot of your glibc tree and
> start testing this out with debian-rebootstrap [1]?
This is exacty what rebootstrap is for. You should be able to experiment
with different ABIs without committing to a particular ABI. You can
fiddle with such aspects and then cross build a pile of around 120
Debian packages. That should uncover the most significant problems. You
don't even have to change the GNU triplet. You can just create an
incompatible throw-away port with an existing architecture name as
rebootstrap refuses to reuse any existing binary packages for the host
architecture.
If you want to pursue that route, get in touch with
debian-cross@lists.debian.org or #debian-bootstrap on irc.oftc.net. The
usual route is forking the rebootstrap.git repository. You just hack up
your toolchain modifications an retry the bootstrap from scratch until
you are satisfied. Be prepared to put up with half a day or a day of CPU
time for a single run. Don't hesitate to ask for help if you have
undecipherable build failures. Balint Reczey has done something quite
similar to what you're up to: He attempted creating ports that are
instrumented with sanitizers.
Since I saw arc in the subject, I also threw arc at rebootstrap. Turns
out that glibc 2.30 does not yet cover arc and using unpackaged versions
of glibc is non-trivial for rebootstrap, so I cannot do much about that.
Once arc support is in a released version of glibc, I'd be happy to be
pinged about it.
Helmut
_______________________________________________
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
^ permalink raw reply
* Re: [PATCH 4/4] Btrfs: implement full reflink support for inline extents
From: Josef Bacik @ 2020-02-20 16:27 UTC (permalink / raw)
To: Filipe Manana; +Cc: linux-btrfs
In-Reply-To: <CAL3q7H5buWQjhR2JTNyPVhZStJui8DKpUBhv1J_m8FVsbBWZ=Q@mail.gmail.com>
On 2/20/20 11:09 AM, Filipe Manana wrote:
> On Thu, Feb 20, 2020 at 3:30 PM Josef Bacik <josef@toxicpanda.com> wrote:
>>
>> On 2/19/20 9:06 AM, fdmanana@kernel.org wrote:
>>> From: Filipe Manana <fdmanana@suse.com>
>>>
>>> There are a few cases where we don't allow cloning an inline extent into
>>> the destination inode, returning -EOPNOTSUPP to user space. This was done
>>> to prevent several types of file corruption and because it's not very
>>> straightforward to deal with these cases, as they can't rely on simply
>>> copying the inline extent between leaves. Such cases require copying the
>>> inline extent's data into the respective page of the destination inode.
>>>
>>> Not supporting these cases makes it harder and more cumbersome to write
>>> applications/libraries that work on any filesystem with reflink support,
>>> since all these cases for which btrfs fails with -EOPNOTSUPP work just
>>> fine on xfs for example. These unsupported cases are also not documented
>>> anywhere and explaining which exact cases fail require a bit of too
>>> technical understanding of btrfs's internal (inline extents and when and
>>> where can they exist in a file), so it's not really user friendly.
>>>
>>> Also some test cases from fstests that use fsx, such as generic/522 for
>>> example, can sporadically fail because they trigger one of these cases,
>>> and fsx expects all operations to succeed.
>>>
>>> This change adds supports for cloning all these cases by copying the
>>> inline extent's data into the respective page of the destination inode.
>>>
>>> With this change test case btrfs/112 from fstests fails because it
>>> expects some clone operations to fail, so it will be updated. Also a
>>> new test case that exercises all these previously unsupported cases
>>> will be added to fstests.
>>>
>>> Signed-off-by: Filipe Manana <fdmanana@suse.com>
>>> ---
>>> fs/btrfs/reflink.c | 212 ++++++++++++++++++++++++++++++++-------------
>>> 1 file changed, 152 insertions(+), 60 deletions(-)
>>>
>>> diff --git a/fs/btrfs/reflink.c b/fs/btrfs/reflink.c
>>> index 7e7f46116db3..c19c87de6d4a 100644
>>> --- a/fs/btrfs/reflink.c
>>> +++ b/fs/btrfs/reflink.c
>>> @@ -1,8 +1,12 @@
>>> // SPDX-License-Identifier: GPL-2.0
>>>
>>> #include <linux/iversion.h>
>>> +#include <linux/blkdev.h>
>>> #include "misc.h"
>>> #include "ctree.h"
>>> +#include "btrfs_inode.h"
>>> +#include "compression.h"
>>> +#include "delalloc-space.h"
>>> #include "transaction.h"
>>>
>>> #define BTRFS_MAX_DEDUPE_LEN SZ_16M
>>> @@ -43,30 +47,121 @@ static int clone_finish_inode_update(struct btrfs_trans_handle *trans,
>>> return ret;
>>> }
>>>
>>> +static int copy_inline_to_page(struct inode *inode,
>>> + const u64 file_offset,
>>> + char *inline_data,
>>> + const u64 size,
>>> + const u64 datal,
>>> + const u8 comp_type)
>>> +{
>>> + const u64 block_size = btrfs_inode_sectorsize(inode);
>>> + const u64 range_end = file_offset + block_size - 1;
>>> + const size_t inline_size = size - btrfs_file_extent_calc_inline_size(0);
>>> + char *data_start = inline_data + btrfs_file_extent_calc_inline_size(0);
>>> + struct extent_changeset *data_reserved = NULL;
>>> + struct page *page = NULL;
>>> + bool page_locked = false;
>>> + int ret;
>>> +
>>> + ASSERT(IS_ALIGNED(file_offset, block_size));
>>> +
>>> + ret = btrfs_delalloc_reserve_space(inode, &data_reserved, file_offset,
>>> + block_size);
>>
>> This could potentially deadlock, as we could need to flush delalloc for this
>> inode that we've dirtied pages for and not be able to make progress because we
>> have this range locked.
>
> But we have already flushed the range before, after locking the inode
> and waiting for dio requests,
> so during the reflink operation no one should be able to dirty pages
> in the range. Or did I miss some edge case?
I had it in my head that we could do this multiple times, but that's stupid
because there's only one inline extent to copy from. You can add
Reviewed-by: Josef Bacik <josef@toxicpanda.com>
Thanks,
Josef
^ permalink raw reply
* [PATCH 0/4] drm/meson: add support for Amlogic Video FBC
From: Neil Armstrong @ 2020-02-20 16:27 UTC (permalink / raw)
To: daniel, dri-devel
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
Amlogic uses a proprietary lossless image compression protocol and format
for their hardware video codec accelerators, either video decoders or
video input encoders.
It considerably reduces memory bandwidth while writing and reading
frames in memory.
The underlying storage is considered to be 3 components, 8bit or 10-bit
per component, YCbCr 420, single plane :
- DRM_FORMAT_YUV420_8BIT
- DRM_FORMAT_YUV420_10BIT
This modifier will be notably added to DMA-BUF frames imported from the V4L2
Amlogic VDEC decoder.
At least two options are supported :
- Scatter mode: the buffer is filled with a IOMMU scatter table referring
to the encoder current memory layout. This mode if more efficient in terms
of memory allocation but frames are not dumpable and only valid during until
the buffer is freed and back in control of the encoder
- Memory saving: when the pixel bpp is 8b, the size of the superblock can
be reduced, thus saving memory.
This serie adds the missing register, updated the FBC decoder registers
content to be committed by the crtc code.
The Amlogic FBC has been tested with compressed content from the Amlogic
HW VP9 decoder on S905X (GXL), S905D2 (G12A) and S905X3 (SM1) in 8bit
(Scatter+Mem Saving on G12A/SM1, Mem Saving on GXL) and 10bit
(Scatter on G12A/SM1, default on GXL).
It's expected to work as-is on GXM and G12B SoCs.
Neil Armstrong (4):
drm/fourcc: Add modifier definitions for describing Amlogic Video
Framebuffer Compression
drm/meson: add Amlogic Video FBC registers
drm/meson: overlay: setup overlay for Amlogic FBC
drm/meson: crtc: handle commit of Amlogic FBC frames
drivers/gpu/drm/meson/meson_crtc.c | 118 ++++++++---
drivers/gpu/drm/meson/meson_drv.h | 16 ++
drivers/gpu/drm/meson/meson_overlay.c | 257 +++++++++++++++++++++++-
drivers/gpu/drm/meson/meson_registers.h | 22 ++
include/uapi/drm/drm_fourcc.h | 56 ++++++
5 files changed, 431 insertions(+), 38 deletions(-)
--
2.22.0
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^ permalink raw reply
* [PATCH 0/4] drm/meson: add support for Amlogic Video FBC
From: Neil Armstrong @ 2020-02-20 16:27 UTC (permalink / raw)
To: daniel, dri-devel
Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel
Amlogic uses a proprietary lossless image compression protocol and format
for their hardware video codec accelerators, either video decoders or
video input encoders.
It considerably reduces memory bandwidth while writing and reading
frames in memory.
The underlying storage is considered to be 3 components, 8bit or 10-bit
per component, YCbCr 420, single plane :
- DRM_FORMAT_YUV420_8BIT
- DRM_FORMAT_YUV420_10BIT
This modifier will be notably added to DMA-BUF frames imported from the V4L2
Amlogic VDEC decoder.
At least two options are supported :
- Scatter mode: the buffer is filled with a IOMMU scatter table referring
to the encoder current memory layout. This mode if more efficient in terms
of memory allocation but frames are not dumpable and only valid during until
the buffer is freed and back in control of the encoder
- Memory saving: when the pixel bpp is 8b, the size of the superblock can
be reduced, thus saving memory.
This serie adds the missing register, updated the FBC decoder registers
content to be committed by the crtc code.
The Amlogic FBC has been tested with compressed content from the Amlogic
HW VP9 decoder on S905X (GXL), S905D2 (G12A) and S905X3 (SM1) in 8bit
(Scatter+Mem Saving on G12A/SM1, Mem Saving on GXL) and 10bit
(Scatter on G12A/SM1, default on GXL).
It's expected to work as-is on GXM and G12B SoCs.
Neil Armstrong (4):
drm/fourcc: Add modifier definitions for describing Amlogic Video
Framebuffer Compression
drm/meson: add Amlogic Video FBC registers
drm/meson: overlay: setup overlay for Amlogic FBC
drm/meson: crtc: handle commit of Amlogic FBC frames
drivers/gpu/drm/meson/meson_crtc.c | 118 ++++++++---
drivers/gpu/drm/meson/meson_drv.h | 16 ++
drivers/gpu/drm/meson/meson_overlay.c | 257 +++++++++++++++++++++++-
drivers/gpu/drm/meson/meson_registers.h | 22 ++
include/uapi/drm/drm_fourcc.h | 56 ++++++
5 files changed, 431 insertions(+), 38 deletions(-)
--
2.22.0
^ permalink raw reply
* [PATCH 2/4] drm/meson: add Amlogic Video FBC registers
From: Neil Armstrong @ 2020-02-20 16:27 UTC (permalink / raw)
To: daniel, dri-devel
Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel
In-Reply-To: <20200220162758.13524-1-narmstrong@baylibre.com>
Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing
register.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_registers.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index 8ea00546cd4e..f784d7d1fe2e 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -144,10 +144,15 @@
#define VIU_SW_RESET_OSD1 BIT(0)
#define VIU_MISC_CTRL0 0x1a06
#define VIU_CTRL0_VD1_AFBC_MASK 0x170000
+#define VIU_CTRL0_AFBC_TO_VD1 BIT(20)
#define VIU_MISC_CTRL1 0x1a07
#define MALI_AFBC_MISC GENMASK(15, 8)
#define D2D3_INTF_LENGTH 0x1a08
#define D2D3_INTF_CTRL0 0x1a09
+#define VD1_AFBCD0_MISC_CTRL 0x1a0a
+#define VD1_AXI_SEL_AFB (1 << 12)
+#define AFBC_VD1_SEL (1 << 10)
+#define VD2_AFBCD1_MISC_CTRL 0x1a0b
#define VIU_OSD1_CTRL_STAT 0x1a10
#define VIU_OSD1_OSD_BLK_ENABLE BIT(0)
#define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2)
@@ -365,6 +370,23 @@
#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
#define AFBC_ENABLE 0x1ae0
+#define AFBC_MODE 0x1ae1
+#define AFBC_SIZE_IN 0x1ae2
+#define AFBC_DEC_DEF_COLOR 0x1ae3
+#define AFBC_CONV_CTRL 0x1ae4
+#define AFBC_LBUF_DEPTH 0x1ae5
+#define AFBC_HEAD_BADDR 0x1ae6
+#define AFBC_BODY_BADDR 0x1ae7
+#define AFBC_SIZE_OUT 0x1ae8
+#define AFBC_OUT_YSCOPE 0x1ae9
+#define AFBC_STAT 0x1aea
+#define AFBC_VD_CFMT_CTRL 0x1aeb
+#define AFBC_VD_CFMT_W 0x1aec
+#define AFBC_MIF_HOR_SCOPE 0x1aed
+#define AFBC_MIF_VER_SCOPE 0x1aee
+#define AFBC_PIXEL_HOR_SCOPE 0x1aef
+#define AFBC_PIXEL_VER_SCOPE 0x1af0
+#define AFBC_VD_CFMT_H 0x1af1
/* vpp */
#define VPP_DUMMY_DATA 0x1d00
--
2.22.0
^ permalink raw reply related
* [PATCH 2/4] drm/meson: add Amlogic Video FBC registers
From: Neil Armstrong @ 2020-02-20 16:27 UTC (permalink / raw)
To: daniel, dri-devel
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20200220162758.13524-1-narmstrong@baylibre.com>
Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing
register.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_registers.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index 8ea00546cd4e..f784d7d1fe2e 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -144,10 +144,15 @@
#define VIU_SW_RESET_OSD1 BIT(0)
#define VIU_MISC_CTRL0 0x1a06
#define VIU_CTRL0_VD1_AFBC_MASK 0x170000
+#define VIU_CTRL0_AFBC_TO_VD1 BIT(20)
#define VIU_MISC_CTRL1 0x1a07
#define MALI_AFBC_MISC GENMASK(15, 8)
#define D2D3_INTF_LENGTH 0x1a08
#define D2D3_INTF_CTRL0 0x1a09
+#define VD1_AFBCD0_MISC_CTRL 0x1a0a
+#define VD1_AXI_SEL_AFB (1 << 12)
+#define AFBC_VD1_SEL (1 << 10)
+#define VD2_AFBCD1_MISC_CTRL 0x1a0b
#define VIU_OSD1_CTRL_STAT 0x1a10
#define VIU_OSD1_OSD_BLK_ENABLE BIT(0)
#define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2)
@@ -365,6 +370,23 @@
#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
#define AFBC_ENABLE 0x1ae0
+#define AFBC_MODE 0x1ae1
+#define AFBC_SIZE_IN 0x1ae2
+#define AFBC_DEC_DEF_COLOR 0x1ae3
+#define AFBC_CONV_CTRL 0x1ae4
+#define AFBC_LBUF_DEPTH 0x1ae5
+#define AFBC_HEAD_BADDR 0x1ae6
+#define AFBC_BODY_BADDR 0x1ae7
+#define AFBC_SIZE_OUT 0x1ae8
+#define AFBC_OUT_YSCOPE 0x1ae9
+#define AFBC_STAT 0x1aea
+#define AFBC_VD_CFMT_CTRL 0x1aeb
+#define AFBC_VD_CFMT_W 0x1aec
+#define AFBC_MIF_HOR_SCOPE 0x1aed
+#define AFBC_MIF_VER_SCOPE 0x1aee
+#define AFBC_PIXEL_HOR_SCOPE 0x1aef
+#define AFBC_PIXEL_VER_SCOPE 0x1af0
+#define AFBC_VD_CFMT_H 0x1af1
/* vpp */
#define VPP_DUMMY_DATA 0x1d00
--
2.22.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH 4/4] drm/meson: crtc: handle commit of Amlogic FBC frames
From: Neil Armstrong @ 2020-02-20 16:27 UTC (permalink / raw)
To: daniel, dri-devel
Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel
In-Reply-To: <20200220162758.13524-1-narmstrong@baylibre.com>
Since the VD1 Amlogic FBC decoder is now configured by the overlay driver,
commit the right registers to decode the Amlogic FBC frame.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_crtc.c | 118 +++++++++++++++++++++--------
1 file changed, 88 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
index e66b6271ff58..d6dcfd654e9c 100644
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -291,6 +291,10 @@ static void meson_crtc_enable_vd1(struct meson_drm *priv)
VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
VPP_COLOR_MNG_ENABLE,
priv->io_base + _REG(VPP_MISC));
+
+ writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1,
+ priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0,
+ priv->io_base + _REG(VIU_MISC_CTRL0));
}
static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv)
@@ -300,6 +304,10 @@ static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv)
VD_BLEND_POSTBLD_SRC_VD1 |
VD_BLEND_POSTBLD_PREMULT_EN,
priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
+
+ writel_relaxed(priv->viu.vd1_afbc ?
+ (VD1_AXI_SEL_AFBC | AFBC_VD1_SEL) : 0,
+ priv->io_base + _REG(VD1_AFBCD0_MISC_CTRL));
}
void meson_crtc_irq(struct meson_drm *priv)
@@ -383,36 +391,86 @@ void meson_crtc_irq(struct meson_drm *priv)
/* Update the VD1 registers */
if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {
- switch (priv->viu.vd1_planes) {
- case 3:
- meson_canvas_config(priv->canvas,
- priv->canvas_id_vd1_2,
- priv->viu.vd1_addr2,
- priv->viu.vd1_stride2,
- priv->viu.vd1_height2,
- MESON_CANVAS_WRAP_NONE,
- MESON_CANVAS_BLKMODE_LINEAR,
- MESON_CANVAS_ENDIAN_SWAP64);
- /* fallthrough */
- case 2:
- meson_canvas_config(priv->canvas,
- priv->canvas_id_vd1_1,
- priv->viu.vd1_addr1,
- priv->viu.vd1_stride1,
- priv->viu.vd1_height1,
- MESON_CANVAS_WRAP_NONE,
- MESON_CANVAS_BLKMODE_LINEAR,
- MESON_CANVAS_ENDIAN_SWAP64);
- /* fallthrough */
- case 1:
- meson_canvas_config(priv->canvas,
- priv->canvas_id_vd1_0,
- priv->viu.vd1_addr0,
- priv->viu.vd1_stride0,
- priv->viu.vd1_height0,
- MESON_CANVAS_WRAP_NONE,
- MESON_CANVAS_BLKMODE_LINEAR,
- MESON_CANVAS_ENDIAN_SWAP64);
+ if (priv->viu.vd1_afbc) {
+ writel_relaxed(priv->viu.vd1_afbc_head_addr,
+ priv->io_base +
+ _REG(AFBC_HEAD_BADDR));
+ writel_relaxed(priv->viu.vd1_afbc_body_addr,
+ priv->io_base +
+ _REG(AFBC_BODY_BADDR));
+ writel_relaxed(priv->viu.vd1_afbc_en,
+ priv->io_base +
+ _REG(AFBC_ENABLE));
+ writel_relaxed(priv->viu.vd1_afbc_mode,
+ priv->io_base +
+ _REG(AFBC_MODE));
+ writel_relaxed(priv->viu.vd1_afbc_size_in,
+ priv->io_base +
+ _REG(AFBC_SIZE_IN));
+ writel_relaxed(priv->viu.vd1_afbc_dec_def_color,
+ priv->io_base +
+ _REG(AFBC_DEC_DEF_COLOR));
+ writel_relaxed(priv->viu.vd1_afbc_conv_ctrl,
+ priv->io_base +
+ _REG(AFBC_CONV_CTRL));
+ writel_relaxed(priv->viu.vd1_afbc_size_out,
+ priv->io_base +
+ _REG(AFBC_SIZE_OUT));
+ writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl,
+ priv->io_base +
+ _REG(AFBC_VD_CFMT_CTRL));
+ writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w,
+ priv->io_base +
+ _REG(AFBC_VD_CFMT_W));
+ writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope,
+ priv->io_base +
+ _REG(AFBC_MIF_HOR_SCOPE));
+ writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope,
+ priv->io_base +
+ _REG(AFBC_MIF_VER_SCOPE));
+ writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope,
+ priv->io_base+
+ _REG(AFBC_PIXEL_HOR_SCOPE));
+ writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope,
+ priv->io_base +
+ _REG(AFBC_PIXEL_VER_SCOPE));
+ writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h,
+ priv->io_base +
+ _REG(AFBC_VD_CFMT_H));
+ } else {
+ switch (priv->viu.vd1_planes) {
+ case 3:
+ meson_canvas_config(priv->canvas,
+ priv->canvas_id_vd1_2,
+ priv->viu.vd1_addr2,
+ priv->viu.vd1_stride2,
+ priv->viu.vd1_height2,
+ MESON_CANVAS_WRAP_NONE,
+ MESON_CANVAS_BLKMODE_LINEAR,
+ MESON_CANVAS_ENDIAN_SWAP64);
+ /* fallthrough */
+ case 2:
+ meson_canvas_config(priv->canvas,
+ priv->canvas_id_vd1_1,
+ priv->viu.vd1_addr1,
+ priv->viu.vd1_stride1,
+ priv->viu.vd1_height1,
+ MESON_CANVAS_WRAP_NONE,
+ MESON_CANVAS_BLKMODE_LINEAR,
+ MESON_CANVAS_ENDIAN_SWAP64);
+ /* fallthrough */
+ case 1:
+ meson_canvas_config(priv->canvas,
+ priv->canvas_id_vd1_0,
+ priv->viu.vd1_addr0,
+ priv->viu.vd1_stride0,
+ priv->viu.vd1_height0,
+ MESON_CANVAS_WRAP_NONE,
+ MESON_CANVAS_BLKMODE_LINEAR,
+ MESON_CANVAS_ENDIAN_SWAP64);
+ }
+
+ writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
}
writel_relaxed(priv->viu.vd1_if0_gen_reg,
--
2.22.0
^ permalink raw reply related
* [PATCH 3/4] drm/meson: overlay: setup overlay for Amlogic FBC
From: Neil Armstrong @ 2020-02-20 16:27 UTC (permalink / raw)
To: daniel, dri-devel
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20200220162758.13524-1-narmstrong@baylibre.com>
Setup the Amlogic FBC decoder for the VD1 video overlay plane.
The VD1 Amlogic FBC decoder is integrated in the pipeline like the
YUV pixel reading/formatter but used a direct memory address instead.
The default mode needs to calculate the content body size since the header
is allocated after.
The scatter mode needs a simplier management since only the header is needed,
since it contains an IOMMU scatter table to locate the superblocks in memory.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_drv.h | 16 ++
drivers/gpu/drm/meson/meson_overlay.c | 257 +++++++++++++++++++++++++-
2 files changed, 265 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
index 04fdf3826643..da951964e988 100644
--- a/drivers/gpu/drm/meson/meson_drv.h
+++ b/drivers/gpu/drm/meson/meson_drv.h
@@ -80,6 +80,7 @@ struct meson_drm {
bool vd1_enabled;
bool vd1_commit;
+ bool vd1_afbc;
unsigned int vd1_planes;
uint32_t vd1_if0_gen_reg;
uint32_t vd1_if0_luma_x0;
@@ -105,6 +106,21 @@ struct meson_drm {
uint32_t vd1_height0;
uint32_t vd1_height1;
uint32_t vd1_height2;
+ uint32_t vd1_afbc_mode;
+ uint32_t vd1_afbc_en;
+ uint32_t vd1_afbc_head_addr;
+ uint32_t vd1_afbc_body_addr;
+ uint32_t vd1_afbc_conv_ctrl;
+ uint32_t vd1_afbc_dec_def_color;
+ uint32_t vd1_afbc_vd_cfmt_ctrl;
+ uint32_t vd1_afbc_vd_cfmt_w;
+ uint32_t vd1_afbc_vd_cfmt_h;
+ uint32_t vd1_afbc_mif_hor_scope;
+ uint32_t vd1_afbc_mif_ver_scope;
+ uint32_t vd1_afbc_size_out;
+ uint32_t vd1_afbc_pixel_hor_scope;
+ uint32_t vd1_afbc_pixel_ver_scope;
+ uint32_t vd1_afbc_size_in;
uint32_t vpp_pic_in_height;
uint32_t vpp_postblend_vd1_h_start_end;
uint32_t vpp_postblend_vd1_v_start_end;
diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c
index 2468b0212d52..1fbb81732e9a 100644
--- a/drivers/gpu/drm/meson/meson_overlay.c
+++ b/drivers/gpu/drm/meson/meson_overlay.c
@@ -5,6 +5,7 @@
* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
*/
+#define DEBUG
#include <linux/bitfield.h>
#include <drm/drm_atomic.h>
@@ -76,6 +77,84 @@
#define VD_REGION24_START(value) FIELD_PREP(GENMASK(11, 0), value)
#define VD_REGION13_END(value) FIELD_PREP(GENMASK(27, 16), value)
+/* AFBC_ENABLE */
+#define AFBC_DEC_ENABLE BIT(8)
+#define AFBC_FRM_START BIT(0)
+
+/* AFBC_MODE */
+#define AFBC_HORZ_SKIP_UV(value) FIELD_PREP(GENMASK(1, 0), value)
+#define AFBC_VERT_SKIP_UV(value) FIELD_PREP(GENMASK(3, 2), value)
+#define AFBC_HORZ_SKIP_Y(value) FIELD_PREP(GENMASK(5, 4), value)
+#define AFBC_VERT_SKIP_Y(value) FIELD_PREP(GENMASK(7, 6), value)
+#define AFBC_COMPBITS_YUV(value) FIELD_PREP(GENMASK(13, 8), value)
+#define AFBC_COMPBITS_8BIT 0
+#define AFBC_COMPBITS_10BIT (2 | (2 << 2) | (2 << 4))
+#define AFBC_BURST_LEN(value) FIELD_PREP(GENMASK(15, 14), value)
+#define AFBC_HOLD_LINE_NUM(value) FIELD_PREP(GENMASK(22, 16), value)
+#define AFBC_MIF_URGENT(value) FIELD_PREP(GENMASK(25, 24), value)
+#define AFBC_REV_MODE(value) FIELD_PREP(GENMASK(27, 26), value)
+#define AFBC_BLK_MEM_MODE BIT(28)
+#define AFBC_SCATTER_MODE BIT(29)
+#define AFBC_SOFT_RESET BIT(31)
+
+/* AFBC_SIZE_IN */
+#define AFBC_HSIZE_IN(value) FIELD_PREP(GENMASK(28, 16), value)
+#define AFBC_VSIZE_IN(value) FIELD_PREP(GENMASK(12, 0), value)
+
+/* AFBC_DEC_DEF_COLOR */
+#define AFBC_DEF_COLOR_Y(value) FIELD_PREP(GENMASK(29, 20), value)
+#define AFBC_DEF_COLOR_U(value) FIELD_PREP(GENMASK(19, 10), value)
+#define AFBC_DEF_COLOR_V(value) FIELD_PREP(GENMASK(9, 0), value)
+
+/* AFBC_CONV_CTRL */
+#define AFBC_CONV_LBUF_LEN(value) FIELD_PREP(GENMASK(11, 0), value)
+
+/* AFBC_LBUF_DEPTH */
+#define AFBC_DEC_LBUF_DEPTH(value) FIELD_PREP(GENMASK(27, 16), value)
+#define AFBC_MIF_LBUF_DEPTH(value) FIELD_PREP(GENMASK(11, 0), value)
+
+/* AFBC_OUT_XSCOPE/AFBC_SIZE_OUT */
+#define AFBC_HSIZE_OUT(value) FIELD_PREP(GENMASK(28, 16), value)
+#define AFBC_VSIZE_OUT(value) FIELD_PREP(GENMASK(12, 0), value)
+#define AFBC_OUT_HORZ_BGN(value) FIELD_PREP(GENMASK(28, 16), value)
+#define AFBC_OUT_HORZ_END(value) FIELD_PREP(GENMASK(12, 0), value)
+
+/* AFBC_OUT_YSCOPE */
+#define AFBC_OUT_VERT_BGN(value) FIELD_PREP(GENMASK(28, 16), value)
+#define AFBC_OUT_VERT_END(value) FIELD_PREP(GENMASK(12, 0), value)
+
+/* AFBC_VD_CFMT_CTRL */
+#define AFBC_HORZ_RPT_PIXEL0 BIT(23)
+#define AFBC_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value)
+#define AFBC_HORZ_FMT_EN BIT(20)
+#define AFBC_VERT_RPT_LINE0 BIT(16)
+#define AFBC_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value)
+#define AFBC_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)
+#define AFBC_VERT_FMT_EN BIT(0)
+
+/* AFBC_VD_CFMT_W */
+#define AFBC_VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value)
+#define AFBC_VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value)
+
+/* AFBC_MIF_HOR_SCOPE */
+#define AFBC_MIF_BLK_BGN_H(value) FIELD_PREP(GENMASK(25, 16), value)
+#define AFBC_MIF_BLK_END_H(value) FIELD_PREP(GENMASK(9, 0), value)
+
+/* AFBC_MIF_VER_SCOPE */
+#define AFBC_MIF_BLK_BGN_V(value) FIELD_PREP(GENMASK(27, 16), value)
+#define AFBC_MIF_BLK_END_V(value) FIELD_PREP(GENMASK(11, 0), value)
+
+/* AFBC_PIXEL_HOR_SCOPE */
+#define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), value)
+#define AFBC_DEC_PIXEL_END_H(value) FIELD_PREP(GENMASK(12, 0), value)
+
+/* AFBC_PIXEL_VER_SCOPE */
+#define AFBC_DEC_PIXEL_BGN_V(value) FIELD_PREP(GENMASK(28, 16), value)
+#define AFBC_DEC_PIXEL_END_V(value) FIELD_PREP(GENMASK(12, 0), value)
+
+/* AFBC_VD_CFMT_H */
+#define AFBC_VD_HEIGHT(value) FIELD_PREP(GENMASK(12, 0), value)
+
struct meson_overlay {
struct drm_plane base;
struct meson_drm *priv;
@@ -157,6 +236,9 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
unsigned int ratio_x, ratio_y;
int temp_height, temp_width;
unsigned int w_in, h_in;
+ int afbc_left, afbc_right;
+ int afbc_top_src, afbc_bottom_src;
+ int afbc_top, afbc_bottom;
int temp, start, end;
if (!crtc_state) {
@@ -169,7 +251,7 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
w_in = fixed16_to_int(state->src_w);
h_in = fixed16_to_int(state->src_h);
- crop_top = fixed16_to_int(state->src_x);
+ crop_top = fixed16_to_int(state->src_y);
crop_left = fixed16_to_int(state->src_x);
video_top = state->crtc_y;
@@ -243,6 +325,14 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n",
vsc_startp, vsc_endp, vd_start_lines, vd_end_lines);
+ afbc_top = round_down(vd_start_lines, 4);
+ afbc_bottom = round_up(vd_end_lines + 1, 4);
+ afbc_top_src = 0;
+ afbc_bottom_src = round_up(h_in + 1, 4);
+
+ DRM_DEBUG("afbc top %d (src %d) bottom %d (src %d)\n",
+ afbc_top, afbc_top_src, afbc_bottom, afbc_bottom_src);
+
/* Horizontal */
start = video_left + video_width / 2 - ((w_in << 17) / ratio_x);
@@ -278,6 +368,16 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n",
hsc_startp, hsc_endp, hd_start_lines, hd_end_lines);
+ if (hd_start_lines > 0 || (hd_end_lines < w_in)) {
+ afbc_left = 0;
+ afbc_right = round_up(w_in, 32);
+ } else {
+ afbc_left = round_down(hd_start_lines, 32);
+ afbc_right = round_up(hd_end_lines + 1, 32);
+ }
+
+ DRM_DEBUG("afbc left %d right %d\n", afbc_left, afbc_right);
+
priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
priv->viu.vpp_vsc_ini_phase = vphase << 8;
@@ -293,6 +393,35 @@ static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) |
VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1);
+ priv->viu.vd1_afbc_vd_cfmt_w =
+ AFBC_VD_H_WIDTH(afbc_right - afbc_left) |
+ AFBC_VD_V_WIDTH(afbc_right / 2 - afbc_left / 2);
+
+ priv->viu.vd1_afbc_vd_cfmt_h =
+ AFBC_VD_HEIGHT((afbc_bottom - afbc_top) / 2);
+
+ priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) |
+ AFBC_MIF_BLK_END_H((afbc_right / 32) - 1);
+
+ priv->viu.vd1_afbc_mif_ver_scope = AFBC_MIF_BLK_BGN_V(afbc_top / 4) |
+ AFBC_MIF_BLK_END_H((afbc_bottom / 4) - 1);
+
+ priv->viu.vd1_afbc_size_out =
+ AFBC_HSIZE_OUT(afbc_right - afbc_left) |
+ AFBC_VSIZE_OUT(afbc_bottom - afbc_top);
+
+ priv->viu.vd1_afbc_pixel_hor_scope =
+ AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) |
+ AFBC_DEC_PIXEL_END_H(hd_end_lines - afbc_left);
+
+ priv->viu.vd1_afbc_pixel_ver_scope =
+ AFBC_DEC_PIXEL_BGN_V(vd_start_lines - afbc_top) |
+ AFBC_DEC_PIXEL_END_V(vd_end_lines - afbc_top);
+
+ priv->viu.vd1_afbc_size_in =
+ AFBC_HSIZE_IN(afbc_right - afbc_left) |
+ AFBC_VSIZE_IN(afbc_bottom_src - afbc_top_src);
+
priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) |
VD_Y_END(vd_end_lines);
@@ -350,11 +479,63 @@ static void meson_overlay_atomic_update(struct drm_plane *plane,
spin_lock_irqsave(&priv->drm->event_lock, flags);
- priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA |
- VD_URGENT_LUMA |
- VD_HOLD_LINES(9) |
- VD_CHRO_RPT_LASTL_CTRL |
- VD_ENABLE;
+ if ((fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0)) ==
+ DRM_FORMAT_MOD_AMLOGIC_FBC(0)) {
+ priv->viu.vd1_afbc = true;
+
+ priv->viu.vd1_afbc_mode = AFBC_MIF_URGENT(3) |
+ AFBC_HOLD_LINE_NUM(8) |
+ AFBC_BURST_LEN(2);
+
+ if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC_SCATTER)
+ priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE;
+
+ if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING)
+ priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE;
+
+ priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE;
+
+ priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256);
+
+ priv->viu.vd1_afbc_dec_def_color = AFBC_DEF_COLOR_Y(1023);
+
+ /* 420: horizontal / 2, vertical / 4 */
+ priv->viu.vd1_afbc_vd_cfmt_ctrl = AFBC_HORZ_RPT_PIXEL0 |
+ AFBC_HORZ_Y_C_RATIO(1) |
+ AFBC_HORZ_FMT_EN |
+ AFBC_VERT_RPT_LINE0 |
+ AFBC_VERT_INITIAL_PHASE(12) |
+ AFBC_VERT_PHASE_STEP(8) |
+ AFBC_VERT_FMT_EN;
+
+ switch (fb->format->format) {
+ /* AFBC Only formats */
+ case DRM_FORMAT_YUV420_10BIT:
+ priv->viu.vd1_afbc_mode |=
+ AFBC_COMPBITS_YUV(AFBC_COMPBITS_10BIT);
+ priv->viu.vd1_afbc_dec_def_color |=
+ AFBC_DEF_COLOR_U(512) |
+ AFBC_DEF_COLOR_V(512);
+ break;
+ case DRM_FORMAT_YUV420_8BIT:
+ priv->viu.vd1_afbc_dec_def_color |=
+ AFBC_DEF_COLOR_U(128) |
+ AFBC_DEF_COLOR_V(128);
+ break;
+ }
+
+ priv->viu.vd1_if0_gen_reg = 0;
+ priv->viu.vd1_if0_canvas0 = 0;
+ priv->viu.viu_vd1_fmt_ctrl = 0;
+ } else {
+ priv->viu.vd1_afbc = false;
+
+ priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA |
+ VD_URGENT_LUMA |
+ VD_HOLD_LINES(9) |
+ VD_CHRO_RPT_LASTL_CTRL |
+ VD_ENABLE;
+ }
/* Setup scaler params */
meson_overlay_setup_scaler_params(priv, plane, interlace_mode);
@@ -370,6 +551,7 @@ static void meson_overlay_atomic_update(struct drm_plane *plane,
priv->viu.vd1_if0_gen_reg2 = 0;
priv->viu.viu_vd1_fmt_ctrl = 0;
+ /* None will match for AFBC Only formats */
switch (fb->format->format) {
/* TOFIX DRM_FORMAT_RGB888 should be supported */
case DRM_FORMAT_YUYV:
@@ -488,13 +670,42 @@ static void meson_overlay_atomic_update(struct drm_plane *plane,
priv->viu.vd1_stride0 = fb->pitches[0];
priv->viu.vd1_height0 =
drm_format_info_plane_height(fb->format,
- fb->height, 0);
+ fb->height, 0);
DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n",
priv->viu.vd1_addr0,
priv->viu.vd1_stride0,
priv->viu.vd1_height0);
}
+ if (priv->viu.vd1_afbc) {
+ if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) {
+ /*
+ * In Scatter mode, the header contains the physical
+ * body content layout, thus the body content
+ * size isn't needed.
+ */
+ priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4;
+ priv->viu.vd1_afbc_body_addr = 0;
+ } else {
+ /* Default mode is 4k per superblock */
+ unsigned long block_size = 4096;
+ unsigned long body_size;
+
+ /* 8bit mem saving mode is 3072bytes per superblock */
+ if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE)
+ block_size = 3072;
+
+ body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) *
+ (ALIGN(priv->viu.vd1_height0, 32) / 32) *
+ block_size;
+
+ priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4;
+ /* Header is after body content */
+ priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 +
+ body_size) >> 4;
+ }
+ }
+
priv->viu.vd1_enabled = true;
spin_unlock_irqrestore(&priv->drm->event_lock, flags);
@@ -531,6 +742,23 @@ static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = {
.prepare_fb = drm_gem_fb_prepare_fb,
};
+static bool meson_overlay_format_mod_supported(struct drm_plane *plane,
+ u32 format, u64 modifier)
+{
+ if (modifier == DRM_FORMAT_MOD_LINEAR &&
+ format != DRM_FORMAT_YUV420_8BIT &&
+ format != DRM_FORMAT_YUV420_10BIT)
+ return true;
+
+ if ((modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0)) ==
+ DRM_FORMAT_MOD_AMLOGIC_FBC(0) &&
+ (format == DRM_FORMAT_YUV420_8BIT ||
+ format == DRM_FORMAT_YUV420_10BIT))
+ return true;
+
+ return false;
+}
+
static const struct drm_plane_funcs meson_overlay_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -538,6 +766,7 @@ static const struct drm_plane_funcs meson_overlay_funcs = {
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+ .format_mod_supported = meson_overlay_format_mod_supported,
};
static const uint32_t supported_drm_formats[] = {
@@ -549,6 +778,18 @@ static const uint32_t supported_drm_formats[] = {
DRM_FORMAT_YUV420,
DRM_FORMAT_YUV411,
DRM_FORMAT_YUV410,
+ DRM_FORMAT_YUV420_8BIT, /* Amlogic FBC Only */
+ DRM_FORMAT_YUV420_10BIT, /* Amlogic FBC Only */
+};
+
+static const uint64_t format_modifiers[] = {
+ DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_SCATTER |
+ DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING),
+ DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_SCATTER),
+ DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING),
+ DRM_FORMAT_MOD_AMLOGIC_FBC_DEFAULT,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID,
};
int meson_overlay_create(struct meson_drm *priv)
@@ -570,7 +811,7 @@ int meson_overlay_create(struct meson_drm *priv)
&meson_overlay_funcs,
supported_drm_formats,
ARRAY_SIZE(supported_drm_formats),
- NULL,
+ format_modifiers,
DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane");
drm_plane_helper_add(plane, &meson_overlay_helper_funcs);
--
2.22.0
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