* Re: [PATCH] fstests: add a another gap extent testcase for btrfs
From: Josef Bacik @ 2020-02-20 17:12 UTC (permalink / raw)
To: fdmanana; +Cc: linux-btrfs, kernel-team, fstests
In-Reply-To: <CAL3q7H7UaJ-_aT4-Ab1eheVJUDwyuc6UQ6-Q9cQZCU1GqjuSGQ@mail.gmail.com>
On 2/20/20 11:24 AM, Filipe Manana wrote:
> On Thu, Feb 20, 2020 at 2:39 PM Josef Bacik <josef@toxicpanda.com> wrote:
>>
>> This is a testcase for a corner that I missed when trying to fix gap
>> extents for btrfs. We would end up with gaps if we hole punched past
>> isize and then extended past the gap in a specific way. This is a
>> simple reproducer to show the problem, and has been properly fixed by my
>> patches now.
>>
>> Signed-off-by: Josef Bacik <josef@toxicpanda.com>
>> ---
>> tests/btrfs/204 | 85 +++++++++++++++++++++++++++++++++++++++++++++
>> tests/btrfs/204.out | 5 +++
>> tests/btrfs/group | 1 +
>> 3 files changed, 91 insertions(+)
>> create mode 100755 tests/btrfs/204
>> create mode 100644 tests/btrfs/204.out
>>
>> diff --git a/tests/btrfs/204 b/tests/btrfs/204
>> new file mode 100755
>> index 00000000..0d5c4bed
>> --- /dev/null
>> +++ b/tests/btrfs/204
>> @@ -0,0 +1,85 @@
>> +#! /bin/bash
>> +# SPDX-License-Identifier: GPL-2.0
>> +# Copyright (c) 2020 Facebook. All Rights Reserved.
>> +#
>> +# FS QA Test 204
>> +#
>> +# Validate that without no-holes we do not get a i_size that is after a gap in
>> +# the file extents on disk when punching a hole past i_size. This is fixed by
>> +# the following patches
>> +#
>> +# btrfs: use the file extent tree infrastructure
>> +# btrfs: replace all uses of btrfs_ordered_update_i_size
>> +#
>> +seq=`basename $0`
>> +seqres=$RESULT_DIR/$seq
>> +echo "QA output created by $seq"
>> +
>> +here=`pwd`
>> +tmp=/tmp/$$
>> +status=1 # failure is the default!
>> +trap "_cleanup; exit \$status" 0 1 2 3 15
>> +
>> +_cleanup()
>> +{
>> + cd /
>> + rm -f $tmp.*
>> +}
>> +
>> +# get standard environment, filters and checks
>> +. ./common/rc
>> +. ./common/filter
>> +. ./common/dmlogwrites
>> +
>> +# remove previous $seqres.full before test
>> +rm -f $seqres.full
>> +
>> +# real QA test starts here
>> +
>> +# Modify as appropriate.
>> +_supported_fs generic
>> +_supported_os Linux
>> +_require_test
>> +_require_scratch
>> +_require_log_writes
>
> _require_xfs_io_command "falloc" "-k"
> _require_xfs_io_command "fpunch"
>
>> +
>> +_log_writes_init $SCRATCH_DEV
>> +_log_writes_mkfs "-O ^no-holes" >> $seqres.full 2>&1
>> +
>> +# There's not a straightforward way to commit the transaction without also
>> +# flushing dirty pages, so shorten the commit interval to 1 so we're sure to get
>> +# a commit with our broken file
>> +_log_writes_mount -o commit=1
>> +
>> +# This creates a gap extent because fpunch doesn't insert hole extents past
>> +# i_size
>> +xfs_io -f -c "falloc -k 4k 8k" $SCRATCH_MNT/file
>> +xfs_io -f -c "fpunch 4k 4k" $SCRATCH_MNT/file
>> +
>> +# The pwrite extends the i_size to cover the gap extent, and then the truncate
>> +# sets the disk_i_size to 12k because it assumes everything was a-ok.
>> +xfs_io -f -c "pwrite 0 4k" $SCRATCH_MNT/file | _filter_xfs_io
>> +xfs_io -f -c "pwrite 0 8k" $SCRATCH_MNT/file | _filter_xfs_io
>> +xfs_io -f -c "truncate 12k" $SCRATCH_MNT/file
>> +
>> +# Wait for a transaction commit
>> +sleep 2
>> +
>> +_log_writes_unmount
>> +_log_writes_remove
>> +
>> +cur=$(_log_writes_find_next_fua 0)
>> +echo "cur=$cur" >> $seqres.full
>> +while [ ! -z "$cur" ]; do
>> + _log_writes_replay_log_range $cur $SCRATCH_DEV >> $seqres.full
>> +
>> + # We only care about the fs consistency, so just run fsck, we don't have
>> + # to mount the fs to validate it
>> + _check_scratch_fs
>> +
>> + cur=$(_log_writes_find_next_fua $(($cur + 1)))
>> +done
>> +
>> +# success, all done
>> +status=0
>> +exit
>> diff --git a/tests/btrfs/204.out b/tests/btrfs/204.out
>> new file mode 100644
>> index 00000000..44c7c8ae
>> --- /dev/null
>> +++ b/tests/btrfs/204.out
>> @@ -0,0 +1,5 @@
>> +QA output created by 204
>> +wrote 4096/4096 bytes at offset 0
>> +XXX Bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
>> +wrote 8192/8192 bytes at offset 0
>> +XXX Bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
>> diff --git a/tests/btrfs/group b/tests/btrfs/group
>> index 6acc6426..7a840177 100644
>> --- a/tests/btrfs/group
>> +++ b/tests/btrfs/group
>> @@ -206,3 +206,4 @@
>> 201 auto quick punch log
>> 202 auto quick subvol snapshot
>> 203 auto quick send clone
>> +204 auto quick log replay
>
> "prealloc" and "punch" groups as well.
>
> Since this just tests another variant of the same problem, maybe it
> could be added to btrfs/172, since that test is very recent and you
> authored it as well.
> Anyway, I don't have a strong preference.
>
> The test itself looks good to me, and with the _require_xfs_io_command
> thing added and the groups (maybe Eryu can add these at commit time):
>
> Reviewed-by: Filipe Manana <fdmanana@suse.com>
>
I like to keep these things discrete, if a test is testing two different things
and it fails I have to go comment out one part and re-run to figure out which
actually failed. Thanks,
Josef
^ permalink raw reply
* Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Remove (pipe == crtc->index) assumption
From: Ville Syrjälä @ 2020-02-20 17:12 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx
In-Reply-To: <20200211172532.14287-3-anshuman.gupta@intel.com>
On Tue, Feb 11, 2020 at 10:55:27PM +0530, Anshuman Gupta wrote:
> we can't have (pipe == crtc->index) assumption in
> driver in order to support 3 non-contiguous
> display pipe system.
>
> FIXME: Remove the WARN_ON(drm_crtc_index(&crtc->base) != crtc->pipe)
> when we will fix all such assumption.
>
> changes since RFC:
> - Added again removed (pipe == crtc->index) WARN_ON.
> - Pass drm_crtc_index instead of intel pipe in order to
> call drm_handle_vblank().
>
> v2:
> - used drm_crtc_handle_vblank()/drm_crtc_wait_one_vblank()
> instead of drm_handle_vblank/drm_wait_one_vblank(). [Jani]
> - introduced intel_handle_vblank() helper to avoid sprinkle
> of intel_crtc across irq_handlers. [Ville]
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
> drivers/gpu/drm/i915/display/intel_display_types.h | 14 +++++++++++++-
> drivers/gpu/drm/i915/i915_irq.c | 14 +++++++-------
> 3 files changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 80eebdc4c670..5333f7a7db42 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14395,11 +14395,11 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
> if (new_crtc_state->hw.active)
> I915_STATE_WARN(!(pll->active_mask & crtc_mask),
> "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
> - pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
> + pipe_name(crtc->pipe), pll->active_mask);
> else
> I915_STATE_WARN(pll->active_mask & crtc_mask,
> "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
> - pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
> + pipe_name(crtc->pipe), pll->active_mask);
>
> I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
> "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
> @@ -14428,10 +14428,10 @@ verify_shared_dpll_state(struct intel_crtc *crtc,
>
> I915_STATE_WARN(pll->active_mask & crtc_mask,
> "pll active mismatch (didn't expect pipe %c in active mask)\n",
> - pipe_name(drm_crtc_index(&crtc->base)));
> + pipe_name(crtc->pipe));
> I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
> "pll enabled crtcs mismatch (found %x in enabled mask)\n",
> - pipe_name(drm_crtc_index(&crtc->base)));
> + pipe_name(crtc->pipe));
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 283c622f8ba1..14e3d78fef7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1595,11 +1595,23 @@ intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
> (1 << INTEL_OUTPUT_DP_MST) |
> (1 << INTEL_OUTPUT_EDP));
> }
> +
> static inline void
> intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> - drm_wait_one_vblank(&dev_priv->drm, pipe);
> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> +
> + drm_crtc_wait_one_vblank(&crtc->base);
> +}
> +
> +static inline void
> +intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
> +{
> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> +
> + drm_crtc_handle_vblank(&crtc->base);
> }
There's no reason to put that into a header. Just put it into
i915_irq.c. With that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> static inline void
> intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a26f2bf1b6ea..bfd3b34f2be3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1364,7 +1364,7 @@ static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
>
> for_each_pipe(dev_priv, pipe) {
> if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
> - drm_handle_vblank(&dev_priv->drm, pipe);
> + intel_handle_vblank(dev_priv, pipe);
>
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> i9xx_pipe_crc_irq_handler(dev_priv, pipe);
> @@ -1382,7 +1382,7 @@ static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
>
> for_each_pipe(dev_priv, pipe) {
> if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
> - drm_handle_vblank(&dev_priv->drm, pipe);
> + intel_handle_vblank(dev_priv, pipe);
>
> if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
> blc_event = true;
> @@ -1406,7 +1406,7 @@ static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
>
> for_each_pipe(dev_priv, pipe) {
> if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
> - drm_handle_vblank(&dev_priv->drm, pipe);
> + intel_handle_vblank(dev_priv, pipe);
>
> if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
> blc_event = true;
> @@ -1432,7 +1432,7 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
>
> for_each_pipe(dev_priv, pipe) {
> if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
> - drm_handle_vblank(&dev_priv->drm, pipe);
> + intel_handle_vblank(dev_priv, pipe);
>
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> i9xx_pipe_crc_irq_handler(dev_priv, pipe);
> @@ -1970,7 +1970,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
>
> for_each_pipe(dev_priv, pipe) {
> if (de_iir & DE_PIPE_VBLANK(pipe))
> - drm_handle_vblank(&dev_priv->drm, pipe);
> + intel_handle_vblank(dev_priv, pipe);
>
> if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
> intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
> @@ -2023,7 +2023,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
>
> for_each_pipe(dev_priv, pipe) {
> if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
> - drm_handle_vblank(&dev_priv->drm, pipe);
> + intel_handle_vblank(dev_priv, pipe);
> }
>
> /* check event from PCH */
> @@ -2336,7 +2336,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
>
> if (iir & GEN8_PIPE_VBLANK)
> - drm_handle_vblank(&dev_priv->drm, pipe);
> + intel_handle_vblank(dev_priv, pipe);
>
> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
> hsw_pipe_crc_irq_handler(dev_priv, pipe);
> --
> 2.24.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [PATCH 0/2] SOF: Intel: hda: allow operation without i915 gfx
From: Kai Vehmanen @ 2020-02-20 17:10 UTC (permalink / raw)
To: broonie, alsa-devel
Cc: tiwai, pierre-louis.bossart, kai.vehmanen, ranjani.sridharan
Hi,
here's a pair of patches that fixes SOF HDA driver load
on devices that have:
- digital mics connected to Intel HDA (so that SOF needs to
be used instead of the legacy HDA driver), and
- external GPU (internal i915 graphics not enabled)
Kai Vehmanen (2):
ASoC: intel/skl/hda - add no-HDMI cases to generic HDA driver
ASoC: SOF: Intel: hda: allow operation without i915 gfx
sound/soc/intel/boards/skl_hda_dsp_common.h | 4 ++++
sound/soc/intel/boards/skl_hda_dsp_generic.c | 25 ++++++++++++++++----
sound/soc/sof/intel/hda-codec.c | 11 ++++++++-
sound/soc/sof/intel/hda.c | 22 +++++++----------
4 files changed, 42 insertions(+), 20 deletions(-)
--
2.17.1
^ permalink raw reply
* RE: [PATCH net-next 0/3] Improve bind(addr, 0) behaviour.
From: David Laight @ 2020-02-20 17:11 UTC (permalink / raw)
To: 'Kuniyuki Iwashima', davem@davemloft.net,
kuznet@ms2.inr.ac.ru, yoshfuji@linux-ipv6.org,
edumazet@google.com
Cc: kuni1840@gmail.com, netdev@vger.kernel.org,
osa-contribution-log@amazon.com
In-Reply-To: <20200220152020.13056-1-kuniyu@amazon.co.jp>
From: Kuniyuki Iwashima
> Sent: 20 February 2020 15:20
>
> Currently we fail to bind sockets to ephemeral ports when all of the ports
> are exhausted even if all sockets have SO_REUSEADDR enabled. In this case,
> we still have a chance to connect to the different remote hosts.
>
> The second and third patches fix the behaviour to fully utilize all space
> of the local (addr, port) tuples.
Would it make sense to only do this for the implicit bind() done
when connect() is called on an unbound socket?
In that case only the quadruplet of the local and remote addresses
needs to be unique.
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
^ permalink raw reply
* Re: [Intel-gfx] [PATCH i-g-t v2] lib/i915: Restrict mmap types to GTT if no MMAP_OFFSET support
From: Janusz Krzysztofik @ 2020-02-20 17:11 UTC (permalink / raw)
To: igt-dev; +Cc: intel-gfx
In-Reply-To: <20200220170819.31579-1-janusz.krzysztofik@linux.intel.com>
Please ignore this submission, the code is broken. Sorry for that.
Janusz
On Thursday, February 20, 2020 6:08:19 PM CET Janusz Krzysztofik wrote:
> Commit b0da8bb705c0 ("lib/i915: for_each_mmap_offset_type()")
> introduced a macro that makes it easy to repeat a test body within a
> loop for each mmap-offset mapping type supported by v4 of i915 MMAP_GTT
> API. However, when run on an older version of the driver, those
> subtests are believed to be still repeated for each known mmap-offset
> mapping type while effectively exercising GTT mapping type only. As
> that may be confusing, fix it.
>
> It has been assumed that the modified macro is still suitable for use
> inside gem_mmap_offset test itself. Would that not be case,
> gem_mmap_offset could redefine the macro back to its initial form for
> internal use.
>
> v2: Move extra condition to a separate function and call it via
> for_each_if(), in case we need to fix it again in future (Chris)
>
> Suggested-by: Michał Winiarski <michal.winiarski@intel.com>
> Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> lib/i915/gem_mman.c | 5 +++++
> lib/i915/gem_mman.h | 7 +++++--
> tests/i915/gem_ctx_sseu.c | 2 +-
> tests/i915/gem_exec_params.c | 2 +-
> tests/i915/gem_madvise.c | 18 ++++++++++++++----
> tests/i915/gem_mmap_offset.c | 10 +++++-----
> tests/i915/i915_pm_rpm.c | 2 +-
> 7 files changed, 32 insertions(+), 14 deletions(-)
>
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index 08ae67696..6fa8d1e8b 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -60,6 +60,11 @@ bool gem_has_mmap_offset(int fd)
> return gtt_version >= 4;
> }
>
> +bool gem_has_mmap_offset_type(int fd, const struct mmap_offset *t);
> +{
> + return gem_has_mmap_offset(fd) || t->type == I915_MMAP_OFFSET_GTT;
> +}
> +
> /**
> * __gem_mmap__gtt:
> * @fd: open i915 drm file descriptor
> diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
> index 4fc6a0186..2c4a7a00b 100644
> --- a/lib/i915/gem_mman.h
> +++ b/lib/i915/gem_mman.h
> @@ -101,10 +101,13 @@ extern const struct mmap_offset {
> unsigned int domain;
> } mmap_offset_types[];
>
> -#define for_each_mmap_offset_type(__t) \
> +bool gem_has_mmap_offset_type(int fd, const struct mmap_offset *t);
> +
> +#define for_each_mmap_offset_type(fd, __t) \
> for (const struct mmap_offset *__t = mmap_offset_types; \
> (__t)->name; \
> - (__t)++)
> + (__t)++) \
> + for_each_if(gem_has_mmap_offset_type((fd), (__t)))
>
> #endif /* GEM_MMAN_H */
>
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index d558c8baa..3bef11b51 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -531,7 +531,7 @@ igt_main
> test_invalid_sseu(fd);
>
> igt_subtest_with_dynamic("mmap-args") {
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(fd, t) {
> igt_dynamic_f("%s", t->name)
> test_mmapped_args(fd, t);
> }
> diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
> index e2912685b..cf7ea3065 100644
> --- a/tests/i915/gem_exec_params.c
> +++ b/tests/i915/gem_exec_params.c
> @@ -244,7 +244,7 @@ static void mmapped(int i915)
> buf = gem_create(i915, 4096);
> handle = batch_create(i915);
>
> - for_each_mmap_offset_type(t) { /* repetitive! */
> + for_each_mmap_offset_type(i915, t) { /* repetitive! */
> struct drm_i915_gem_execbuffer2 *execbuf;
> struct drm_i915_gem_exec_object2 *exec;
>
> diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
> index e8716a891..54c9befff 100644
> --- a/tests/i915/gem_madvise.c
> +++ b/tests/i915/gem_madvise.c
> @@ -62,12 +62,13 @@ dontneed_before_mmap(void)
> char *ptr;
> int fd;
>
> - for_each_mmap_offset_type(t) {
> + fd = drm_open_driver(DRIVER_INTEL);
> +
> + for_each_mmap_offset_type(fd, t) {
> sighandler_t old_sigsegv, old_sigbus;
>
> igt_debug("Mapping mode: %s\n", t->name);
>
> - fd = drm_open_driver(DRIVER_INTEL);
> handle = gem_create(fd, OBJECT_SIZE);
> gem_madvise(fd, handle, I915_MADV_DONTNEED);
>
> @@ -93,7 +94,11 @@ dontneed_before_mmap(void)
> munmap(ptr, OBJECT_SIZE);
> signal(SIGBUS, old_sigsegv);
> signal(SIGSEGV, old_sigbus);
> +
> + fd = drm_open_driver(DRIVER_INTEL);
> }
> +
> + close(fd);
> }
>
> static void
> @@ -103,12 +108,13 @@ dontneed_after_mmap(void)
> char *ptr;
> int fd;
>
> - for_each_mmap_offset_type(t) {
> + fd = drm_open_driver(DRIVER_INTEL);
> +
> + for_each_mmap_offset_type(fd, t) {
> sighandler_t old_sigsegv, old_sigbus;
>
> igt_debug("Mapping mode: %s\n", t->name);
>
> - fd = drm_open_driver(DRIVER_INTEL);
> handle = gem_create(fd, OBJECT_SIZE);
>
> ptr = __gem_mmap_offset(fd, handle, 0, OBJECT_SIZE,
> @@ -134,7 +140,11 @@ dontneed_after_mmap(void)
> munmap(ptr, OBJECT_SIZE);
> signal(SIGBUS, old_sigbus);
> signal(SIGSEGV, old_sigsegv);
> +
> + fd = drm_open_driver(DRIVER_INTEL);
> }
> +
> + close(fd);
> }
>
> static void
> diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
> index f49d18e63..1ec963b25 100644
> --- a/tests/i915/gem_mmap_offset.c
> +++ b/tests/i915/gem_mmap_offset.c
> @@ -128,7 +128,7 @@ static void basic_uaf(int i915)
> {
> const uint32_t obj_size = 4096;
>
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> uint32_t handle = gem_create(i915, obj_size);
> uint8_t *expected, *buf, *addr;
>
> @@ -176,7 +176,7 @@ static void basic_uaf(int i915)
>
> static void isolation(int i915)
> {
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> struct drm_i915_gem_mmap_offset mmap_arg = {
> .flags = t->type
> };
> @@ -245,7 +245,7 @@ static void pf_nonblock(int i915)
> {
> igt_spin_t *spin = igt_spin_new(i915);
>
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> uint32_t *ptr;
>
> ptr = __mmap_offset(i915, spin->handle, 0, 4096,
> @@ -324,7 +324,7 @@ static void open_flood(int i915, int timeout)
> handle = gem_create(i915, 4096);
> dmabuf = prime_handle_to_fd(i915, handle);
>
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> struct drm_i915_gem_mmap_offset arg = {
> .handle = handle,
> .flags = t->type,
> @@ -351,7 +351,7 @@ static void open_flood(int i915, int timeout)
> tmp = gem_reopen_driver(i915);
> handle = prime_fd_to_handle(i915, dmabuf);
>
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> struct drm_i915_gem_mmap_offset arg = {
> .handle = handle,
> .flags = t->type,
> diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
> index 0c2821122..1bec80db7 100644
> --- a/tests/i915/i915_pm_rpm.c
> +++ b/tests/i915/i915_pm_rpm.c
> @@ -2006,7 +2006,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
>
> /* GEM */
> igt_subtest_with_dynamic("gem-mmap-type") {
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(drm_fd, t) {
> igt_dynamic_f("%s", t->name)
> gem_mmap_args(t);
> }
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* Re: [igt-dev] [PATCH i-g-t v2] lib/i915: Restrict mmap types to GTT if no MMAP_OFFSET support
From: Janusz Krzysztofik @ 2020-02-20 17:11 UTC (permalink / raw)
To: igt-dev; +Cc: intel-gfx
In-Reply-To: <20200220170819.31579-1-janusz.krzysztofik@linux.intel.com>
Please ignore this submission, the code is broken. Sorry for that.
Janusz
On Thursday, February 20, 2020 6:08:19 PM CET Janusz Krzysztofik wrote:
> Commit b0da8bb705c0 ("lib/i915: for_each_mmap_offset_type()")
> introduced a macro that makes it easy to repeat a test body within a
> loop for each mmap-offset mapping type supported by v4 of i915 MMAP_GTT
> API. However, when run on an older version of the driver, those
> subtests are believed to be still repeated for each known mmap-offset
> mapping type while effectively exercising GTT mapping type only. As
> that may be confusing, fix it.
>
> It has been assumed that the modified macro is still suitable for use
> inside gem_mmap_offset test itself. Would that not be case,
> gem_mmap_offset could redefine the macro back to its initial form for
> internal use.
>
> v2: Move extra condition to a separate function and call it via
> for_each_if(), in case we need to fix it again in future (Chris)
>
> Suggested-by: Michał Winiarski <michal.winiarski@intel.com>
> Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> lib/i915/gem_mman.c | 5 +++++
> lib/i915/gem_mman.h | 7 +++++--
> tests/i915/gem_ctx_sseu.c | 2 +-
> tests/i915/gem_exec_params.c | 2 +-
> tests/i915/gem_madvise.c | 18 ++++++++++++++----
> tests/i915/gem_mmap_offset.c | 10 +++++-----
> tests/i915/i915_pm_rpm.c | 2 +-
> 7 files changed, 32 insertions(+), 14 deletions(-)
>
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index 08ae67696..6fa8d1e8b 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -60,6 +60,11 @@ bool gem_has_mmap_offset(int fd)
> return gtt_version >= 4;
> }
>
> +bool gem_has_mmap_offset_type(int fd, const struct mmap_offset *t);
> +{
> + return gem_has_mmap_offset(fd) || t->type == I915_MMAP_OFFSET_GTT;
> +}
> +
> /**
> * __gem_mmap__gtt:
> * @fd: open i915 drm file descriptor
> diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
> index 4fc6a0186..2c4a7a00b 100644
> --- a/lib/i915/gem_mman.h
> +++ b/lib/i915/gem_mman.h
> @@ -101,10 +101,13 @@ extern const struct mmap_offset {
> unsigned int domain;
> } mmap_offset_types[];
>
> -#define for_each_mmap_offset_type(__t) \
> +bool gem_has_mmap_offset_type(int fd, const struct mmap_offset *t);
> +
> +#define for_each_mmap_offset_type(fd, __t) \
> for (const struct mmap_offset *__t = mmap_offset_types; \
> (__t)->name; \
> - (__t)++)
> + (__t)++) \
> + for_each_if(gem_has_mmap_offset_type((fd), (__t)))
>
> #endif /* GEM_MMAN_H */
>
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index d558c8baa..3bef11b51 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -531,7 +531,7 @@ igt_main
> test_invalid_sseu(fd);
>
> igt_subtest_with_dynamic("mmap-args") {
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(fd, t) {
> igt_dynamic_f("%s", t->name)
> test_mmapped_args(fd, t);
> }
> diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
> index e2912685b..cf7ea3065 100644
> --- a/tests/i915/gem_exec_params.c
> +++ b/tests/i915/gem_exec_params.c
> @@ -244,7 +244,7 @@ static void mmapped(int i915)
> buf = gem_create(i915, 4096);
> handle = batch_create(i915);
>
> - for_each_mmap_offset_type(t) { /* repetitive! */
> + for_each_mmap_offset_type(i915, t) { /* repetitive! */
> struct drm_i915_gem_execbuffer2 *execbuf;
> struct drm_i915_gem_exec_object2 *exec;
>
> diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
> index e8716a891..54c9befff 100644
> --- a/tests/i915/gem_madvise.c
> +++ b/tests/i915/gem_madvise.c
> @@ -62,12 +62,13 @@ dontneed_before_mmap(void)
> char *ptr;
> int fd;
>
> - for_each_mmap_offset_type(t) {
> + fd = drm_open_driver(DRIVER_INTEL);
> +
> + for_each_mmap_offset_type(fd, t) {
> sighandler_t old_sigsegv, old_sigbus;
>
> igt_debug("Mapping mode: %s\n", t->name);
>
> - fd = drm_open_driver(DRIVER_INTEL);
> handle = gem_create(fd, OBJECT_SIZE);
> gem_madvise(fd, handle, I915_MADV_DONTNEED);
>
> @@ -93,7 +94,11 @@ dontneed_before_mmap(void)
> munmap(ptr, OBJECT_SIZE);
> signal(SIGBUS, old_sigsegv);
> signal(SIGSEGV, old_sigbus);
> +
> + fd = drm_open_driver(DRIVER_INTEL);
> }
> +
> + close(fd);
> }
>
> static void
> @@ -103,12 +108,13 @@ dontneed_after_mmap(void)
> char *ptr;
> int fd;
>
> - for_each_mmap_offset_type(t) {
> + fd = drm_open_driver(DRIVER_INTEL);
> +
> + for_each_mmap_offset_type(fd, t) {
> sighandler_t old_sigsegv, old_sigbus;
>
> igt_debug("Mapping mode: %s\n", t->name);
>
> - fd = drm_open_driver(DRIVER_INTEL);
> handle = gem_create(fd, OBJECT_SIZE);
>
> ptr = __gem_mmap_offset(fd, handle, 0, OBJECT_SIZE,
> @@ -134,7 +140,11 @@ dontneed_after_mmap(void)
> munmap(ptr, OBJECT_SIZE);
> signal(SIGBUS, old_sigbus);
> signal(SIGSEGV, old_sigsegv);
> +
> + fd = drm_open_driver(DRIVER_INTEL);
> }
> +
> + close(fd);
> }
>
> static void
> diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
> index f49d18e63..1ec963b25 100644
> --- a/tests/i915/gem_mmap_offset.c
> +++ b/tests/i915/gem_mmap_offset.c
> @@ -128,7 +128,7 @@ static void basic_uaf(int i915)
> {
> const uint32_t obj_size = 4096;
>
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> uint32_t handle = gem_create(i915, obj_size);
> uint8_t *expected, *buf, *addr;
>
> @@ -176,7 +176,7 @@ static void basic_uaf(int i915)
>
> static void isolation(int i915)
> {
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> struct drm_i915_gem_mmap_offset mmap_arg = {
> .flags = t->type
> };
> @@ -245,7 +245,7 @@ static void pf_nonblock(int i915)
> {
> igt_spin_t *spin = igt_spin_new(i915);
>
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> uint32_t *ptr;
>
> ptr = __mmap_offset(i915, spin->handle, 0, 4096,
> @@ -324,7 +324,7 @@ static void open_flood(int i915, int timeout)
> handle = gem_create(i915, 4096);
> dmabuf = prime_handle_to_fd(i915, handle);
>
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> struct drm_i915_gem_mmap_offset arg = {
> .handle = handle,
> .flags = t->type,
> @@ -351,7 +351,7 @@ static void open_flood(int i915, int timeout)
> tmp = gem_reopen_driver(i915);
> handle = prime_fd_to_handle(i915, dmabuf);
>
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(i915, t) {
> struct drm_i915_gem_mmap_offset arg = {
> .handle = handle,
> .flags = t->type,
> diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
> index 0c2821122..1bec80db7 100644
> --- a/tests/i915/i915_pm_rpm.c
> +++ b/tests/i915/i915_pm_rpm.c
> @@ -2006,7 +2006,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
>
> /* GEM */
> igt_subtest_with_dynamic("gem-mmap-type") {
> - for_each_mmap_offset_type(t) {
> + for_each_mmap_offset_type(drm_fd, t) {
> igt_dynamic_f("%s", t->name)
> gem_mmap_args(t);
> }
>
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply
* How to setup debug environment for image running in target board? #toolchain #yocto
From: amern2k16 @ 2020-02-20 17:11 UTC (permalink / raw)
To: yocto
[-- Attachment #1: Type: text/plain, Size: 800 bytes --]
I'm working with NXP iMX8QXPMEK evaluation board. I downloaded bsp release L4.19.35_1.1.0_MX8QXP from following site:
https://www.nxp.com/design/software/embedded-software/linux-software-and-development-tools/embedded-linux-for-i.mx-applications-processors:IMXLINUX?tab=Design_Tools_Tab
This bsp release is for Yocto Project 2.7 (Warrior)
I built yocto project for this bsp release. I copied built image into sd card and then booted NXP board from sd card. I need to step through USB Host Subsystem source code running in embedded linux kernel?
There is a serial connection between my NXP evaluation board and my PC. Micro-USB Debug port in NXP board is connected to USB port in my PC. How do I setup debugging environment so I can see source code and symbols running in my NXP board?
[-- Attachment #2: Type: text/html, Size: 850 bytes --]
^ permalink raw reply
* Re: [RFCv2 0/4] ext4: bmap & fiemap conversion to use iomap
From: Christoph Hellwig @ 2020-02-20 17:09 UTC (permalink / raw)
To: Ritesh Harjani
Cc: Jan Kara, Darrick J. Wong, tytso, adilger.kernel, linux-ext4,
linux-fsdevel, hch, cmaiolino
In-Reply-To: <20200220170304.80C3E52051@d06av21.portsmouth.uk.ibm.com>
On Thu, Feb 20, 2020 at 10:33:03PM +0530, Ritesh Harjani wrote:
> So I was making some changes along the above lines and I think we can take
> below approach for filesystem which could determine the
> _EXTENT_LAST relatively easily and for cases if it cannot
> as Jan also mentioned we could keep the current behavior as is and let
> iomap core decide the last disk extent.
Well, given that _EXTENT_LAST never worked properly on any file system
since it was added this actually changes behavior and could break
existing users. I'd rather update the documentation to match reality
rather than writing a lot of code for a feature no one obviously cared
about for years.
^ permalink raw reply
* Re: ioctl seems to change errno behaviour in 5.6.0rc2
From: Antonio Larrosa @ 2020-02-20 17:09 UTC (permalink / raw)
To: dgilbert; +Cc: linux-scsi, Arnd Bergmann
In-Reply-To: <3b6cf3fb-675e-fdea-590e-31d73ccab4cd@interlog.com>
On 20/2/20 17:30, Douglas Gilbert wrote:
> Antonio,
> A fix is in the works for this, see:
> [PATCH] compat_ioctl, cdrom: Replace .ioctl with .compat_ioctl in four
> appropriate places
>
> by Arnd Bergmann on the linux-scsi list.
>
Ah, perfect. Thanks!
--
Antonio Larrosa
^ permalink raw reply
* Re: [RFC PATCH 04/11] cpufreq: Remove Calxeda driver
From: Mark Langsdorf @ 2020-02-20 17:06 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, soc, Andre Przywara,
Robert Richter, Jon Loeliger, Alexander Graf, Matthias Brugger
Cc: kvm, Viresh Kumar, linux-ide, Will Deacon, linux-clk,
Joerg Roedel, Daniel Lezcano, devicetree, linux-pm, Eric Auger,
Alex Williamson, Borislav Petkov, Mauro Carvalho Chehab,
linux-edac, Jens Axboe, Tony Luck, Stephen Boyd, netdev,
Cornelia Huck, Rafael J. Wysocki, iommu, James Morse,
Robin Murphy, David S. Miller
In-Reply-To: <20200218171321.30990-5-robh@kernel.org>
On 2/18/20 11:13 AM, Rob Herring wrote:
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: linux-pm@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
Acked-by: Mark Langsdorf <mark.langsdorf@gmail.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [Intel-gfx] [PATCH i-g-t v2] lib/i915: Restrict mmap types to GTT if no MMAP_OFFSET support
From: Janusz Krzysztofik @ 2020-02-20 17:08 UTC (permalink / raw)
To: igt-dev; +Cc: intel-gfx
Commit b0da8bb705c0 ("lib/i915: for_each_mmap_offset_type()")
introduced a macro that makes it easy to repeat a test body within a
loop for each mmap-offset mapping type supported by v4 of i915 MMAP_GTT
API. However, when run on an older version of the driver, those
subtests are believed to be still repeated for each known mmap-offset
mapping type while effectively exercising GTT mapping type only. As
that may be confusing, fix it.
It has been assumed that the modified macro is still suitable for use
inside gem_mmap_offset test itself. Would that not be case,
gem_mmap_offset could redefine the macro back to its initial form for
internal use.
v2: Move extra condition to a separate function and call it via
for_each_if(), in case we need to fix it again in future (Chris)
Suggested-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/i915/gem_mman.c | 5 +++++
lib/i915/gem_mman.h | 7 +++++--
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_params.c | 2 +-
tests/i915/gem_madvise.c | 18 ++++++++++++++----
tests/i915/gem_mmap_offset.c | 10 +++++-----
tests/i915/i915_pm_rpm.c | 2 +-
7 files changed, 32 insertions(+), 14 deletions(-)
diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 08ae67696..6fa8d1e8b 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -60,6 +60,11 @@ bool gem_has_mmap_offset(int fd)
return gtt_version >= 4;
}
+bool gem_has_mmap_offset_type(int fd, const struct mmap_offset *t);
+{
+ return gem_has_mmap_offset(fd) || t->type == I915_MMAP_OFFSET_GTT;
+}
+
/**
* __gem_mmap__gtt:
* @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 4fc6a0186..2c4a7a00b 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -101,10 +101,13 @@ extern const struct mmap_offset {
unsigned int domain;
} mmap_offset_types[];
-#define for_each_mmap_offset_type(__t) \
+bool gem_has_mmap_offset_type(int fd, const struct mmap_offset *t);
+
+#define for_each_mmap_offset_type(fd, __t) \
for (const struct mmap_offset *__t = mmap_offset_types; \
(__t)->name; \
- (__t)++)
+ (__t)++) \
+ for_each_if(gem_has_mmap_offset_type((fd), (__t)))
#endif /* GEM_MMAN_H */
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index d558c8baa..3bef11b51 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -531,7 +531,7 @@ igt_main
test_invalid_sseu(fd);
igt_subtest_with_dynamic("mmap-args") {
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(fd, t) {
igt_dynamic_f("%s", t->name)
test_mmapped_args(fd, t);
}
diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index e2912685b..cf7ea3065 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -244,7 +244,7 @@ static void mmapped(int i915)
buf = gem_create(i915, 4096);
handle = batch_create(i915);
- for_each_mmap_offset_type(t) { /* repetitive! */
+ for_each_mmap_offset_type(i915, t) { /* repetitive! */
struct drm_i915_gem_execbuffer2 *execbuf;
struct drm_i915_gem_exec_object2 *exec;
diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
index e8716a891..54c9befff 100644
--- a/tests/i915/gem_madvise.c
+++ b/tests/i915/gem_madvise.c
@@ -62,12 +62,13 @@ dontneed_before_mmap(void)
char *ptr;
int fd;
- for_each_mmap_offset_type(t) {
+ fd = drm_open_driver(DRIVER_INTEL);
+
+ for_each_mmap_offset_type(fd, t) {
sighandler_t old_sigsegv, old_sigbus;
igt_debug("Mapping mode: %s\n", t->name);
- fd = drm_open_driver(DRIVER_INTEL);
handle = gem_create(fd, OBJECT_SIZE);
gem_madvise(fd, handle, I915_MADV_DONTNEED);
@@ -93,7 +94,11 @@ dontneed_before_mmap(void)
munmap(ptr, OBJECT_SIZE);
signal(SIGBUS, old_sigsegv);
signal(SIGSEGV, old_sigbus);
+
+ fd = drm_open_driver(DRIVER_INTEL);
}
+
+ close(fd);
}
static void
@@ -103,12 +108,13 @@ dontneed_after_mmap(void)
char *ptr;
int fd;
- for_each_mmap_offset_type(t) {
+ fd = drm_open_driver(DRIVER_INTEL);
+
+ for_each_mmap_offset_type(fd, t) {
sighandler_t old_sigsegv, old_sigbus;
igt_debug("Mapping mode: %s\n", t->name);
- fd = drm_open_driver(DRIVER_INTEL);
handle = gem_create(fd, OBJECT_SIZE);
ptr = __gem_mmap_offset(fd, handle, 0, OBJECT_SIZE,
@@ -134,7 +140,11 @@ dontneed_after_mmap(void)
munmap(ptr, OBJECT_SIZE);
signal(SIGBUS, old_sigbus);
signal(SIGSEGV, old_sigsegv);
+
+ fd = drm_open_driver(DRIVER_INTEL);
}
+
+ close(fd);
}
static void
diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
index f49d18e63..1ec963b25 100644
--- a/tests/i915/gem_mmap_offset.c
+++ b/tests/i915/gem_mmap_offset.c
@@ -128,7 +128,7 @@ static void basic_uaf(int i915)
{
const uint32_t obj_size = 4096;
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
uint32_t handle = gem_create(i915, obj_size);
uint8_t *expected, *buf, *addr;
@@ -176,7 +176,7 @@ static void basic_uaf(int i915)
static void isolation(int i915)
{
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
struct drm_i915_gem_mmap_offset mmap_arg = {
.flags = t->type
};
@@ -245,7 +245,7 @@ static void pf_nonblock(int i915)
{
igt_spin_t *spin = igt_spin_new(i915);
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
uint32_t *ptr;
ptr = __mmap_offset(i915, spin->handle, 0, 4096,
@@ -324,7 +324,7 @@ static void open_flood(int i915, int timeout)
handle = gem_create(i915, 4096);
dmabuf = prime_handle_to_fd(i915, handle);
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
struct drm_i915_gem_mmap_offset arg = {
.handle = handle,
.flags = t->type,
@@ -351,7 +351,7 @@ static void open_flood(int i915, int timeout)
tmp = gem_reopen_driver(i915);
handle = prime_fd_to_handle(i915, dmabuf);
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
struct drm_i915_gem_mmap_offset arg = {
.handle = handle,
.flags = t->type,
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 0c2821122..1bec80db7 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -2006,7 +2006,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
/* GEM */
igt_subtest_with_dynamic("gem-mmap-type") {
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(drm_fd, t) {
igt_dynamic_f("%s", t->name)
gem_mmap_args(t);
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* Re: [PATCH v4 00/11] RFC: [for 5.0]: HMP monitor handlers refactoring
From: Maxim Levitsky @ 2020-02-20 17:06 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: Kevin Wolf, qemu-block, Markus Armbruster, qemu-devel,
Gerd Hoffmann, Max Reitz
In-Reply-To: <20200207182835.GQ3302@work-vm>
On Fri, 2020-02-07 at 18:28 +0000, Dr. David Alan Gilbert wrote:
> * Maxim Levitsky (mlevitsk@redhat.com) wrote:
> > On Mon, 2020-02-03 at 19:57 +0000, Dr. David Alan Gilbert wrote:
> > > * Maxim Levitsky (mlevitsk@redhat.com) wrote:
> > > > This patch series is bunch of cleanups to the hmp monitor code.
> > > > It mostly moves the blockdev related hmp handlers to its own file,
> > > > and does some minor refactoring.
> > > >
> > > > No functional changes expected.
> > >
> > > You've still got the title marked as RFC - are you actually ready for
> > > this log?
> >
> > I forgot to update this to be honest, I don't consider this an RFC,
> > especially since I dropped for now the patches that might cause
> > issues. This is now just a nice refactoring.
>
> OK, so if we can get some block people to say they're happy, then
> I'd be happy to take this through HMP or they can take it through block.
Any update?
Best regards,
Maxim Levitsky
>
> Dave
>
> > Best regards,
> > Maxim Levitsky
> >
> > >
> > > Dave
> > >
> > > >
> > > > Changes from V1:
> > > > * move the handlers to block/monitor/block-hmp-cmds.c
> > > > * tiny cleanup for the commit messages
> > > >
> > > > Changes from V2:
> > > > * Moved all the function prototypes to new header (blockdev-hmp-cmds.h)
> > > > * Set the license of blockdev-hmp-cmds.c to GPLv2+
> > > > * Moved hmp_snapshot_* functions to blockdev-hmp-cmds.c
> > > > * Moved hmp_drive_add_node to blockdev-hmp-cmds.c
> > > > (this change needed some new exports, thus in separate new patch)
> > > > * Moved hmp_qemu_io and hmp_eject to blockdev-hmp-cmds.c
> > > > * Added 'error:' prefix to vreport, and updated the iotests
> > > > This is invasive change, but really feels like the right one
> > > > * Added minor refactoring patch that drops an unused #include
> > > >
> > > > Changes from V3:
> > > > * Dropped the error prefix patches for now due to fact that it seems
> > > > that libvirt doesn't need that after all. Oh well...
> > > > I'll send them in a separate series.
> > > >
> > > > * Hopefully correctly merged the copyright info the new files
> > > > Both files are GPLv2 now (due to code from hmp.h/hmp-cmds.c)
> > > >
> > > > * Addressed review feedback
> > > > * Renamed the added header to block-hmp-cmds.h
> > > >
> > > > * Got rid of checkpatch.pl warnings in the moved code
> > > > (cosmetic code changes only)
> > > >
> > > > * I kept the reviewed-by tags, since the changes I did are minor.
> > > > I hope that this is right thing to do.
> > > >
> > > > Best regards,
> > > > Maxim Levitsky
> > > >
> > > > Maxim Levitsky (11):
> > > > usb/dev-storage: remove unused include
> > > > monitor/hmp: uninline add_init_drive
> > > > monitor/hmp: rename device-hotplug.c to block/monitor/block-hmp-cmds.c
> > > > monitor/hmp: move hmp_drive_del and hmp_commit to block-hmp-cmds.c
> > > > monitor/hmp: move hmp_drive_mirror and hmp_drive_backup to
> > > > block-hmp-cmds.c Moved code was added after 2012-01-13, thus under
> > > > GPLv2+
> > > > monitor/hmp: move hmp_block_job* to block-hmp-cmds.c
> > > > monitor/hmp: move hmp_snapshot_* to block-hmp-cmds.c
> > > > hmp_snapshot_blkdev is from GPLv2 version of the hmp-cmds.c thus
> > > > have to change the licence to GPLv2
> > > > monitor/hmp: move hmp_nbd_server* to block-hmp-cmds.c
> > > > monitor/hmp: move remaining hmp_block* functions to block-hmp-cmds.c
> > > > monitor/hmp: move hmp_info_block* to block-hmp-cmds.c
> > > > monitor/hmp: Move hmp_drive_add_node to block-hmp-cmds.c
> > > >
> > > > MAINTAINERS | 1 +
> > > > Makefile.objs | 2 +-
> > > > block/Makefile.objs | 1 +
> > > > block/monitor/Makefile.objs | 1 +
> > > > block/monitor/block-hmp-cmds.c | 1002 ++++++++++++++++++++++++++++++++
> > > > blockdev.c | 137 +----
> > > > device-hotplug.c | 91 ---
> > > > hw/usb/dev-storage.c | 1 -
> > > > include/block/block-hmp-cmds.h | 54 ++
> > > > include/block/block_int.h | 5 +-
> > > > include/monitor/hmp.h | 24 -
> > > > include/sysemu/blockdev.h | 4 -
> > > > include/sysemu/sysemu.h | 3 -
> > > > monitor/hmp-cmds.c | 769 ------------------------
> > > > monitor/misc.c | 1 +
> > > > 15 files changed, 1072 insertions(+), 1024 deletions(-)
> > > > create mode 100644 block/monitor/Makefile.objs
> > > > create mode 100644 block/monitor/block-hmp-cmds.c
> > > > delete mode 100644 device-hotplug.c
> > > > create mode 100644 include/block/block-hmp-cmds.h
> > > >
> > > > --
> > > > 2.17.2
> > > >
> > >
> > > --
> > > Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
> >
> >
>
> --
> Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
^ permalink raw reply
* [igt-dev] [PATCH i-g-t v2] lib/i915: Restrict mmap types to GTT if no MMAP_OFFSET support
From: Janusz Krzysztofik @ 2020-02-20 17:08 UTC (permalink / raw)
To: igt-dev; +Cc: intel-gfx
Commit b0da8bb705c0 ("lib/i915: for_each_mmap_offset_type()")
introduced a macro that makes it easy to repeat a test body within a
loop for each mmap-offset mapping type supported by v4 of i915 MMAP_GTT
API. However, when run on an older version of the driver, those
subtests are believed to be still repeated for each known mmap-offset
mapping type while effectively exercising GTT mapping type only. As
that may be confusing, fix it.
It has been assumed that the modified macro is still suitable for use
inside gem_mmap_offset test itself. Would that not be case,
gem_mmap_offset could redefine the macro back to its initial form for
internal use.
v2: Move extra condition to a separate function and call it via
for_each_if(), in case we need to fix it again in future (Chris)
Suggested-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/i915/gem_mman.c | 5 +++++
lib/i915/gem_mman.h | 7 +++++--
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_params.c | 2 +-
tests/i915/gem_madvise.c | 18 ++++++++++++++----
tests/i915/gem_mmap_offset.c | 10 +++++-----
tests/i915/i915_pm_rpm.c | 2 +-
7 files changed, 32 insertions(+), 14 deletions(-)
diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 08ae67696..6fa8d1e8b 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -60,6 +60,11 @@ bool gem_has_mmap_offset(int fd)
return gtt_version >= 4;
}
+bool gem_has_mmap_offset_type(int fd, const struct mmap_offset *t);
+{
+ return gem_has_mmap_offset(fd) || t->type == I915_MMAP_OFFSET_GTT;
+}
+
/**
* __gem_mmap__gtt:
* @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 4fc6a0186..2c4a7a00b 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -101,10 +101,13 @@ extern const struct mmap_offset {
unsigned int domain;
} mmap_offset_types[];
-#define for_each_mmap_offset_type(__t) \
+bool gem_has_mmap_offset_type(int fd, const struct mmap_offset *t);
+
+#define for_each_mmap_offset_type(fd, __t) \
for (const struct mmap_offset *__t = mmap_offset_types; \
(__t)->name; \
- (__t)++)
+ (__t)++) \
+ for_each_if(gem_has_mmap_offset_type((fd), (__t)))
#endif /* GEM_MMAN_H */
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index d558c8baa..3bef11b51 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -531,7 +531,7 @@ igt_main
test_invalid_sseu(fd);
igt_subtest_with_dynamic("mmap-args") {
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(fd, t) {
igt_dynamic_f("%s", t->name)
test_mmapped_args(fd, t);
}
diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index e2912685b..cf7ea3065 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -244,7 +244,7 @@ static void mmapped(int i915)
buf = gem_create(i915, 4096);
handle = batch_create(i915);
- for_each_mmap_offset_type(t) { /* repetitive! */
+ for_each_mmap_offset_type(i915, t) { /* repetitive! */
struct drm_i915_gem_execbuffer2 *execbuf;
struct drm_i915_gem_exec_object2 *exec;
diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
index e8716a891..54c9befff 100644
--- a/tests/i915/gem_madvise.c
+++ b/tests/i915/gem_madvise.c
@@ -62,12 +62,13 @@ dontneed_before_mmap(void)
char *ptr;
int fd;
- for_each_mmap_offset_type(t) {
+ fd = drm_open_driver(DRIVER_INTEL);
+
+ for_each_mmap_offset_type(fd, t) {
sighandler_t old_sigsegv, old_sigbus;
igt_debug("Mapping mode: %s\n", t->name);
- fd = drm_open_driver(DRIVER_INTEL);
handle = gem_create(fd, OBJECT_SIZE);
gem_madvise(fd, handle, I915_MADV_DONTNEED);
@@ -93,7 +94,11 @@ dontneed_before_mmap(void)
munmap(ptr, OBJECT_SIZE);
signal(SIGBUS, old_sigsegv);
signal(SIGSEGV, old_sigbus);
+
+ fd = drm_open_driver(DRIVER_INTEL);
}
+
+ close(fd);
}
static void
@@ -103,12 +108,13 @@ dontneed_after_mmap(void)
char *ptr;
int fd;
- for_each_mmap_offset_type(t) {
+ fd = drm_open_driver(DRIVER_INTEL);
+
+ for_each_mmap_offset_type(fd, t) {
sighandler_t old_sigsegv, old_sigbus;
igt_debug("Mapping mode: %s\n", t->name);
- fd = drm_open_driver(DRIVER_INTEL);
handle = gem_create(fd, OBJECT_SIZE);
ptr = __gem_mmap_offset(fd, handle, 0, OBJECT_SIZE,
@@ -134,7 +140,11 @@ dontneed_after_mmap(void)
munmap(ptr, OBJECT_SIZE);
signal(SIGBUS, old_sigbus);
signal(SIGSEGV, old_sigsegv);
+
+ fd = drm_open_driver(DRIVER_INTEL);
}
+
+ close(fd);
}
static void
diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
index f49d18e63..1ec963b25 100644
--- a/tests/i915/gem_mmap_offset.c
+++ b/tests/i915/gem_mmap_offset.c
@@ -128,7 +128,7 @@ static void basic_uaf(int i915)
{
const uint32_t obj_size = 4096;
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
uint32_t handle = gem_create(i915, obj_size);
uint8_t *expected, *buf, *addr;
@@ -176,7 +176,7 @@ static void basic_uaf(int i915)
static void isolation(int i915)
{
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
struct drm_i915_gem_mmap_offset mmap_arg = {
.flags = t->type
};
@@ -245,7 +245,7 @@ static void pf_nonblock(int i915)
{
igt_spin_t *spin = igt_spin_new(i915);
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
uint32_t *ptr;
ptr = __mmap_offset(i915, spin->handle, 0, 4096,
@@ -324,7 +324,7 @@ static void open_flood(int i915, int timeout)
handle = gem_create(i915, 4096);
dmabuf = prime_handle_to_fd(i915, handle);
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
struct drm_i915_gem_mmap_offset arg = {
.handle = handle,
.flags = t->type,
@@ -351,7 +351,7 @@ static void open_flood(int i915, int timeout)
tmp = gem_reopen_driver(i915);
handle = prime_fd_to_handle(i915, dmabuf);
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(i915, t) {
struct drm_i915_gem_mmap_offset arg = {
.handle = handle,
.flags = t->type,
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 0c2821122..1bec80db7 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -2006,7 +2006,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
/* GEM */
igt_subtest_with_dynamic("gem-mmap-type") {
- for_each_mmap_offset_type(t) {
+ for_each_mmap_offset_type(drm_fd, t) {
igt_dynamic_f("%s", t->name)
gem_mmap_args(t);
}
--
2.21.0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related
* [PATCH] iio: industrialio-core: Fix debugfs read
From: Alexandru Tachici @ 2020-02-20 17:07 UTC (permalink / raw)
To: linux-iio, linux-kernel; +Cc: jic23, Alexandru Tachici
Currently iio_debugfs_read_reg calls debugfs_reg_access
every time it is ran. Reading the same hardware register
multiple times during the same reading of a debugfs file
can cause unintended effects.
For example for each: cat iio:device0/direct_reg_access
the file_operations.read function will be called at least
twice. First will return the full length of the string in
bytes and the second will return 0.
This patch makes iio_debugfs_read_reg to call debugfs_reg_access
only when the user's buffer position (*ppos) is 0. (meaning
it is the beginning of a new reading of the debugfs file).
Fixes: e553f182d55b ("staging: iio: core: Introduce debugfs support, add support for direct register access")
Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
drivers/iio/industrialio-core.c | 34 +++++++++++++++++++++++----------
include/linux/iio/iio.h | 2 ++
2 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c
index 65ff0d067018..637cea14afdb 100644
--- a/drivers/iio/industrialio-core.c
+++ b/drivers/iio/industrialio-core.c
@@ -297,26 +297,40 @@ static void __exit iio_exit(void)
}
#if defined(CONFIG_DEBUG_FS)
-static ssize_t iio_debugfs_read_reg(struct file *file, char __user *userbuf,
- size_t count, loff_t *ppos)
+static int iio_debugfs_get_reg_string(struct iio_dev *indio_dev)
{
- struct iio_dev *indio_dev = file->private_data;
- char buf[20];
+ const struct iio_info *info = indio_dev->info;
unsigned val = 0;
- ssize_t len;
int ret;
- ret = indio_dev->info->debugfs_reg_access(indio_dev,
- indio_dev->cached_reg_addr,
- 0, &val);
+ ret = info->debugfs_reg_access(indio_dev, indio_dev->cached_reg_addr,
+ 0, &val);
if (ret) {
dev_err(indio_dev->dev.parent, "%s: read failed\n", __func__);
return ret;
}
+ indio_dev->read_buf_len = snprintf(indio_dev->read_buf,
+ sizeof(indio_dev->read_buf),
+ "0x%X\n", val);
+ return 0;
+}
- len = snprintf(buf, sizeof(buf), "0x%X\n", val);
+static ssize_t iio_debugfs_read_reg(struct file *file, char __user *userbuf,
+ size_t count, loff_t *ppos)
+{
+ struct iio_dev *indio_dev = file->private_data;
+ loff_t pos = *ppos;
+ int ret;
+
+ if (pos == 0) {
+ ret = iio_debugfs_get_reg_string(indio_dev);
+ if (ret)
+ return ret;
+ }
- return simple_read_from_buffer(userbuf, count, ppos, buf, len);
+ return simple_read_from_buffer(userbuf, count, ppos,
+ indio_dev->read_buf,
+ indio_dev->read_buf_len);
}
static ssize_t iio_debugfs_write_reg(struct file *file,
diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h
index 862ce0019eba..eed58ed2f368 100644
--- a/include/linux/iio/iio.h
+++ b/include/linux/iio/iio.h
@@ -568,6 +568,8 @@ struct iio_dev {
#if defined(CONFIG_DEBUG_FS)
struct dentry *debugfs_dentry;
unsigned cached_reg_addr;
+ char read_buf[20];
+ unsigned int read_buf_len;
#endif
};
--
2.20.1
^ permalink raw reply related
* Re: [RFC PATCH 02/11] ata: Remove Calxeda AHCI driver
From: Mark Langsdorf @ 2020-02-20 17:07 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, soc, Andre Przywara,
Robert Richter, Jon Loeliger, Alexander Graf, Matthias Brugger
Cc: kvm, Viresh Kumar, linux-ide, Will Deacon, linux-clk,
Joerg Roedel, Daniel Lezcano, devicetree, linux-pm, Eric Auger,
Alex Williamson, Borislav Petkov, Mauro Carvalho Chehab,
linux-edac, Jens Axboe, Tony Luck, Stephen Boyd, netdev,
Cornelia Huck, Rafael J. Wysocki, iommu, James Morse,
Robin Murphy, David S. Miller
In-Reply-To: <20200218171321.30990-3-robh@kernel.org>
On 2/18/20 11:13 AM, Rob Herring wrote:
> Cc: Jens Axboe <axboe@kernel.dk>
> Cc: linux-ide@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
Acked-by: Mark Langsdorf <mark.langsdorf@gmail.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [RFC PATCH 02/11] ata: Remove Calxeda AHCI driver
From: Mark Langsdorf @ 2020-02-20 17:07 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, soc, Andre Przywara,
Robert Richter, Jon Loeliger, Alexander Graf, Matthias Brugger
Cc: Alex Williamson, Borislav Petkov, Cornelia Huck, Daniel Lezcano,
David S. Miller, devicetree, Eric Auger, iommu, James Morse,
Jens Axboe, Joerg Roedel, kvm, linux-clk, linux-edac, linux-ide,
linux-pm, Mauro Carvalho Chehab, netdev, Rafael J. Wysocki,
Robin Murphy, Stephen Boyd, Tony Luck, Viresh Kumar, Will Deacon
In-Reply-To: <20200218171321.30990-3-robh@kernel.org>
On 2/18/20 11:13 AM, Rob Herring wrote:
> Cc: Jens Axboe <axboe@kernel.dk>
> Cc: linux-ide@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
Acked-by: Mark Langsdorf <mark.langsdorf@gmail.com>
^ permalink raw reply
* [PATCH v2 2/2] Documentation: devictree: Add ipq806x mdio bindings
From: Ansuel Smith @ 2020-02-20 17:07 UTC (permalink / raw)
Cc: Ansuel Smith, Andy Gross, Bjorn Andersson, David S. Miller,
Rob Herring, Mark Rutland, Andrew Lunn, Florian Fainelli,
Heiner Kallweit, Russell King, linux-arm-msm, netdev, devicetree,
linux-kernel
In-Reply-To: <20200220170732.12741-1-ansuelsmth@gmail.com>
Add documentations for ipq806x mdio driver.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
.../bindings/net/qcom,ipq8064-mdio.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml
diff --git a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml
new file mode 100644
index 000000000000..c5a21c0b5325
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.txt
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm ipq806x MDIO bus controller
+
+description: |+
+ The ipq806x soc have a MDIO dedicated controller that is
+ used to comunicate with the gmac phy conntected.
+ Child nodes of this MDIO bus controller node are standard
+ Ethernet PHY device nodes as described in
+ Documentation/devicetree/bindings/net/phy.txt
+
+allOf:
+ - $ref: "mdio.yaml#"
+
+properties:
+ compatible:
+ const: qcom,ipq8064-mdio
+ reg:
+ maxItems: 1
+ description: address and length of the register set for the device
+ clocks:
+ maxItems: 1
+ description: A reference to the clock supplying the MDIO bus controller
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ mdio@37000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,ipq8064-mdio", "syscon";
+ reg = <0x37000000 0x200000>;
+ resets = <&gcc GMAC_CORE1_RESET>;
+ reset-names = "stmmaceth";
+ clocks = <&gcc GMAC_CORE1_CLK>;
+
+ switch@10 {
+ compatible = "qca,qca8337";
+ ...
+ }
+ };
\ No newline at end of file
--
2.25.0
^ permalink raw reply related
* [PATCH v2 1/2] net: mdio: add ipq8064 mdio driver
From: Ansuel Smith @ 2020-02-20 17:07 UTC (permalink / raw)
Cc: Ansuel Smith, Andy Gross, Bjorn Andersson, David S. Miller,
Rob Herring, Mark Rutland, Andrew Lunn, Florian Fainelli,
Heiner Kallweit, Russell King, linux-arm-msm, netdev, devicetree,
linux-kernel
Currently ipq806x soc use generi bitbang driver to
comunicate with the gmac ethernet interface.
Add a dedicated driver created by chunkeey to fix this.
Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/net/phy/Kconfig | 8 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-ipq8064.c | 163 +++++++++++++++++++++++++++++++++
3 files changed, 172 insertions(+)
create mode 100644 drivers/net/phy/mdio-ipq8064.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 9dabe03a668c..ec2a5493a7e8 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -157,6 +157,14 @@ config MDIO_I2C
This is library mode.
+config MDIO_IPQ8064
+ tristate "Qualcomm IPQ8064 MDIO interface support"
+ depends on HAS_IOMEM && OF_MDIO
+ depends on MFD_SYSCON
+ help
+ This driver supports the MDIO interface found in the network
+ interface units of the IPQ8064 SoC
+
config MDIO_MOXART
tristate "MOXA ART MDIO interface support"
depends on ARCH_MOXART || COMPILE_TEST
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index fe5badf13b65..8f02bd2089f3 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
+obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o
obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/mdio-ipq8064.c b/drivers/net/phy/mdio-ipq8064.c
new file mode 100644
index 000000000000..e974a6f5d5ef
--- /dev/null
+++ b/drivers/net/phy/mdio-ipq8064.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Qualcomm IPQ8064 MDIO interface driver
+//
+// Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/of_mdio.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
+
+/* MII address register definitions */
+#define MII_ADDR_REG_ADDR 0x10
+#define MII_BUSY BIT(0)
+#define MII_WRITE BIT(1)
+#define MII_CLKRANGE_60_100M (0 << 2)
+#define MII_CLKRANGE_100_150M (1 << 2)
+#define MII_CLKRANGE_20_35M (2 << 2)
+#define MII_CLKRANGE_35_60M (3 << 2)
+#define MII_CLKRANGE_150_250M (4 << 2)
+#define MII_CLKRANGE_250_300M (5 << 2)
+#define MII_CLKRANGE_MASK GENMASK(4, 2)
+#define MII_REG_SHIFT 6
+#define MII_REG_MASK GENMASK(10, 6)
+#define MII_ADDR_SHIFT 11
+#define MII_ADDR_MASK GENMASK(15, 11)
+
+#define MII_DATA_REG_ADDR 0x14
+
+#define MII_MDIO_DELAY (1000)
+#define MII_MDIO_RETRY (10)
+
+struct ipq8064_mdio {
+ struct regmap *base; /* NSS_GMAC0_BASE */
+};
+
+static int
+ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
+{
+ u32 busy;
+
+ return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
+ !(busy & MII_BUSY), MII_MDIO_DELAY,
+ MII_MDIO_RETRY * USEC_PER_MSEC);
+}
+
+static int
+ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
+{
+ struct ipq8064_mdio *priv = bus->priv;
+ u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
+ u32 ret_val;
+ int err;
+
+ /* Reject clause 45 */
+ if (reg_offset & MII_ADDR_C45)
+ return -EOPNOTSUPP;
+
+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
+
+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
+ usleep_range(10, 20);
+
+ err = ipq8064_mdio_wait_busy(priv);
+ if (err)
+ return err;
+
+ regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
+ return (int)ret_val;
+}
+
+static int
+ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
+{
+ struct ipq8064_mdio *priv = bus->priv;
+ u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
+
+ /* Reject clause 45 */
+ if (reg_offset & MII_ADDR_C45)
+ return -EOPNOTSUPP;
+
+ regmap_write(priv->base, MII_DATA_REG_ADDR, data);
+
+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
+
+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
+ usleep_range(10, 20);
+
+ return ipq8064_mdio_wait_busy(priv);
+}
+
+static int
+ipq8064_mdio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct ipq8064_mdio *priv;
+ struct mii_bus *bus;
+ int ret;
+
+ bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
+ if (!bus)
+ return -ENOMEM;
+
+ bus->name = "ipq8064_mdio_bus";
+ bus->read = ipq8064_mdio_read;
+ bus->write = ipq8064_mdio_write;
+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
+ bus->parent = &pdev->dev;
+
+ priv = bus->priv;
+ priv->base = syscon_node_to_regmap(np);
+ if (IS_ERR_OR_NULL(priv->base)) {
+ priv->base = syscon_regmap_lookup_by_phandle(np, "master");
+ if (IS_ERR_OR_NULL(priv->base)) {
+ dev_err(&pdev->dev, "master phandle not found\n");
+ return -EINVAL;
+ }
+ }
+
+ ret = of_mdiobus_register(bus, np);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, bus);
+ return 0;
+}
+
+static int
+ipq8064_mdio_remove(struct platform_device *pdev)
+{
+ struct mii_bus *bus = platform_get_drvdata(pdev);
+
+ mdiobus_unregister(bus);
+
+ return 0;
+}
+
+static const struct of_device_id ipq8064_mdio_dt_ids[] = {
+ { .compatible = "qcom,ipq8064-mdio" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
+
+static struct platform_driver ipq8064_mdio_driver = {
+ .probe = ipq8064_mdio_probe,
+ .remove = ipq8064_mdio_remove,
+ .driver = {
+ .name = "ipq8064-mdio",
+ .of_match_table = ipq8064_mdio_dt_ids,
+ },
+};
+
+module_platform_driver(ipq8064_mdio_driver);
+
+MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
+MODULE_LICENSE("GPL");
--
2.25.0
^ permalink raw reply related
* Re: [PATCH v3] binutils: Upgrade to 2.34 release
From: Khem Raj @ 2020-02-20 17:07 UTC (permalink / raw)
To: Peter Kjellerstedt, openembedded-core@lists.openembedded.org
Cc: Christopher Clark
In-Reply-To: <ef62cf8da954430991546afa3e3b3840@XBOX03.axis.com>
On 2/20/20 12:07 AM, Peter Kjellerstedt wrote:
>> -----Original Message-----
>> From: openembedded-core-bounces@lists.openembedded.org <openembedded-core-
>> bounces@lists.openembedded.org> On Behalf Of Khem Raj
>> Sent: den 19 februari 2020 23:43
>> To: openembedded-core@lists.openembedded.org
>> Cc: Christopher Clark <christopher.clark6@baesystems.com>
>> Subject: [OE-core] [PATCH v3] binutils: Upgrade to 2.34 release
>>
>> Details of changelog [1]
>>
>> Removing bfd/ld patch to ebale pe targets instead use
>
> Change "ebale" to "enable".
>
Will be in v4
>> specific emulations via --enable-targets for x86_64
>>
>> Re-arrange/forward-port patches and upgrade libctf configure to libtool
>> 2.4 patch
>>
>> rpaths are no longer emitted into elfedit/readelf therefore no need of
>> chrpath anymore
>>
>> Instead of pre-generating configure scripts and house them in libtool
>> patch, generate them during configure. This also ensures that we do not
>> patch configure directly but rather the sources which generate it
>>
>> Package newly added libctf library
>>
>> [1] https://lists.gnu.org/archive/html/info-gnu/2020-02/msg00000.html
>>
>> Signed-off-by: Khem Raj <mailto:raj.khem@gmail.com>
>> Cc: Christopher Clark <mailto:christopher.clark6@baesystems.com>
>> ---
>> v2: Fix libtool patch and drop EFI patch for configure option
>> v3: Make libtool patch not generate configure, fix packaging
>
> [cut]
>
>> diff --git a/meta/recipes-devtools/binutils/binutils.inc b/meta/recipes-devtools/binutils/binutils.inc
>> index a4b9aa586d..b070d85e15 100644
>> --- a/meta/recipes-devtools/binutils/binutils.inc
>> +++ b/meta/recipes-devtools/binutils/binutils.inc
>> @@ -13,17 +13,12 @@ LICENSE = "GPLv3"
>>
>> DEPENDS = "flex-native bison-native zlib-native gnu-config-native autoconf-native"
>>
>> -#
>> -# we need chrpath > 0.14 and some distros like centos 7 still have older chrpath
>> -#
>> -DEPENDS_append_class-target = " chrpath-replacement-native"
>> -EXTRANATIVEPATH_append_class-target = " chrpath-native"
>> -
>> inherit autotools gettext multilib_header texinfo
>>
>> FILES_${PN} = " \
>> ${bindir}/${TARGET_PREFIX}* \
>> - ${libdir}/lib*-*.so \
>> + ${libdir}/lib*.so.* \
>> + ${libdir}/lib*-${PV}*.so \
>> ${prefix}/${TARGET_SYS}/bin/* \
>> ${bindir}/embedspu"
>>
>> @@ -33,6 +28,8 @@ FILES_${PN}-dev = " \
>> ${includedir} \
>> ${libdir}/*.la \
>> ${libdir}/libbfd.so \
>> + ${libdir}/libctf.so \
>> + ${libdir}/libctf-nobfd.so \
>> ${libdir}/libopcodes.so"
>>
>> # Rather than duplicating multiple entries for these, make one
>> @@ -80,6 +77,8 @@ EXTRA_OECONF = "--program-prefix=${TARGET_PREFIX} \
>> ${LDGOLD} \
>> mailto:${@bb.utils.contains('DISTRO_FEATURES', 'multiarch', '--enable-64-bit-bfd', '', d)}"
>>
>> +EXTRA_OECONF_append_x86-64 = " --enable-targets=x86_64-pe,x86_64-pep "
>> +
>> LDGOLD_class-native = ""
>> LDGOLD_class-crosssdk = ""
>> LDGOLD ?= "mailto:${@bb.utils.contains('DISTRO_FEATURES', 'ld-is-gold', '--enable-gold=default --enable-threads', '--enable-gold --enable-ld=default --enable-threads', d)}"
>> @@ -112,7 +111,14 @@ export CC_FOR_BUILD = "LD_LIBRARY_PATH= ${BUILD_CC}"
>> MULTIARCH := "mailto:${@bb.utils.contains("DISTRO_FEATURES", "multiarch", "yes", "no", d)}"
>> do_configure[vardeps] += "MULTIARCH"
>> do_configure () {
>> - (cd ${S}; gnu-configize) || die "Failed to run gnu-configize"
>> + (for d in . bfd binutils gas gold gprof ld libctf opcodes; do
>> + cd ${S}/$d
>> + autoconf
>> + rm -rf autom4te.cache
>> + done
>> + cd ${S}
>> + gnu-configize)
>> +
>
> Correct the indentation to use tabs.
>
in v4
> There are also some patches below that still modify configure, which
> shouldn't be needed with the introduction of autoconf above.
>
thats intentional. Ideally all patches should modify configure since
that will be needed if they are upstreamed. However, libtool 2.4 is
quite intrusive where it has to be regenerated almost everytime it is
rebased on top of latest binutils.
>> oe_runconf
>> #
>> # must prime config.cache to ensure the build of libiberty
>> @@ -123,10 +129,6 @@ do_configure () {
>> done
>> }
>>
>> -do_compile_append_class-target() {
>> - chrpath -d ${B}/binutils/elfedit
>> - chrpath -d ${B}/binutils/readelf
>> -}
>> do_install () {
>> autotools_do_install
>>
>> diff --git a/meta/recipes-devtools/binutils/binutils/0001-binutils-crosssdk-Generate-relocatable-SDKs.patch b/meta/recipes-devtools/binutils/binutils/0001-binutils-crosssdk-Generate-relocatable-SDKs.patch
>> index 3a9461bf4a..a36c259711 100644
>> --- a/meta/recipes-devtools/binutils/binutils/0001-binutils-crosssdk-Generate-relocatable-SDKs.patch
>> +++ b/meta/recipes-devtools/binutils/binutils/0001-binutils-crosssdk-Generate-relocatable-SDKs.patch
>> @@ -1,7 +1,7 @@
>> -From c9aed4cb3c02715b2ba1fc70949043849f202f46 Mon Sep 17 00:00:00 2001
>> +From 9caa0964b6f50411d1b4520a31461cd0a87810fd Mon Sep 17 00:00:00 2001
>> From: Khem Raj <mailto:raj.khem@gmail.com>
>> -Date: Sun, 8 Dec 2019 00:31:35 -0800
>> -Subject: [PATCH] binutils-crosssdk: Generate relocatable SDKs
>> +Date: Mon, 2 Mar 2015 01:58:54 +0000
>> +Subject: [PATCH 01/15] binutils-crosssdk: Generate relocatable SDKs
>>
>> This patch will modify the ELF linker scripts so that the crosssdk
>> linker will generate binaries with a 4096 bytes PT_INTERP section. When the binaries
>
> [cut]
>
>> @@ -57,3 +57,6 @@ index f9f0f7d402..9e469dca86 100644
>> fi
>> if test -z "$PLT"; then
>> IPLT=".iplt ${RELOCATING-0} : { *(.iplt) }"
>> +--
>> +2.25.1
>> +
>
> May I suggest that you continue to use --no-signature and --no-numbered as
> options to git format-patch to avoid unnecessary changes to the patches?
>
I guess yes will be in v4
> [cut]
>
>> diff --git a/meta/recipes-devtools/binutils/binutils/0007-Use-libtool-2.4.patch b/meta/recipes-devtools/binutils/binutils/0007-Use-libtool-2.4.patch
>> new file mode 100644
>> index 0000000000..82906026a9
>> --- /dev/null
>> +++ b/meta/recipes-devtools/binutils/binutils/0007-Use-libtool-2.4.patch
>> @@ -0,0 +1,7118 @@
>> +From c0ec70962bffb56b563475f539e8175ea97d7eb1 Mon Sep 17 00:00:00 2001
>> +From: Khem Raj <raj.khem@gmail.com>
>> +Date: Sun, 14 Feb 2016 17:04:07 +0000
>> +Subject: [PATCH 07/15] Use libtool 2.4
>> +
>> +get libtool sysroot support
>> +
>> +Upstream-Status: Pending
>> +
>> +Signed-off-by: Khem Raj <raj.khem@gmail.com>
>> +---
>> + bfd/configure.ac | 2 +-
>> + libtool.m4 | 1080 +++++++++++------
>> + ltmain.sh | 2925 +++++++++++++++++++++++++++++++---------------
>> + ltoptions.m4 | 2 +-
>> + ltversion.m4 | 12 +-
>> + lt~obsolete.m4 | 2 +-
>
> Wouldn't it be better to run automake --add-missing --copy instead
> (or autoreconf)? That way you would get rid of all the patches to
> Makefile.in as well.
As said above, we only want to regenerate configure, nothing else, there
are different versions of gettext etc would be needed to fully
reconfigure it and its version specific.
>
>> + 6 files changed, 2717 insertions(+), 1306 deletions(-)
>> +
>
> [cut]
>
> //Peter
>
^ permalink raw reply
* Re: [RFC PATCH 04/11] cpufreq: Remove Calxeda driver
From: Mark Langsdorf @ 2020-02-20 17:06 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, soc, Andre Przywara,
Robert Richter, Jon Loeliger, Alexander Graf, Matthias Brugger
Cc: Alex Williamson, Borislav Petkov, Cornelia Huck, Daniel Lezcano,
David S. Miller, devicetree, Eric Auger, iommu, James Morse,
Jens Axboe, Joerg Roedel, kvm, linux-clk, linux-edac, linux-ide,
linux-pm, Mauro Carvalho Chehab, netdev, Rafael J. Wysocki,
Robin Murphy, Stephen Boyd, Tony Luck, Viresh Kumar, Will Deacon
In-Reply-To: <20200218171321.30990-5-robh@kernel.org>
On 2/18/20 11:13 AM, Rob Herring wrote:
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: linux-pm@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
Acked-by: Mark Langsdorf <mark.langsdorf@gmail.com>
^ permalink raw reply
* [Intel-gfx] [PATCH v7 8/8] drm/i915/gvt: Make WARN* drm specific where vgpu ptr is available
From: Pankaj Bharadiya @ 2020-02-20 16:55 UTC (permalink / raw)
To: jani.nikula, daniel, intel-gfx, dri-devel, Zhenyu Wang, Zhi Wang,
Joonas Lahtinen, Rodrigo Vivi, David Airlie
In-Reply-To: <20200220165507.16823-1-pankaj.laxminarayan.bharadiya@intel.com>
Drm specific drm_WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device struct pointer is readily
available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@@
identifier func, T;
@@
func(struct intel_vgpu *T,...) {
+struct drm_i915_private *i915 = T->gvt->dev_priv;
<+...
(
-WARN(
+drm_WARN(&i915->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&i915->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&i915->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&i915->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
---
drivers/gpu/drm/i915/gvt/cfg_space.c | 23 +++++++++++--------
drivers/gpu/drm/i915/gvt/display.c | 3 ++-
drivers/gpu/drm/i915/gvt/edid.c | 17 +++++++++-----
drivers/gpu/drm/i915/gvt/gtt.c | 21 ++++++++++++-----
drivers/gpu/drm/i915/gvt/handlers.c | 20 ++++++++++++-----
drivers/gpu/drm/i915/gvt/interrupt.c | 15 ++++++++-----
drivers/gpu/drm/i915/gvt/kvmgt.c | 10 ++++++---
drivers/gpu/drm/i915/gvt/mmio.c | 30 +++++++++++++++----------
drivers/gpu/drm/i915/gvt/mmio_context.c | 6 +++--
drivers/gpu/drm/i915/gvt/scheduler.c | 6 +++--
drivers/gpu/drm/i915/gvt/vgpu.c | 6 +++--
11 files changed, 104 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
index 19cf1bbe059d..7fd16bab2f39 100644
--- a/drivers/gpu/drm/i915/gvt/cfg_space.c
+++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
@@ -106,10 +106,13 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,
int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
- if (WARN_ON(bytes > 4))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN_ON(&i915->drm, bytes > 4))
return -EINVAL;
- if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
+ if (drm_WARN_ON(&i915->drm,
+ offset + bytes > vgpu->gvt->device_info.cfg_space_size))
return -EINVAL;
memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
@@ -297,34 +300,36 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
int ret;
- if (WARN_ON(bytes > 4))
+ if (drm_WARN_ON(&i915->drm, bytes > 4))
return -EINVAL;
- if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
+ if (drm_WARN_ON(&i915->drm,
+ offset + bytes > vgpu->gvt->device_info.cfg_space_size))
return -EINVAL;
/* First check if it's PCI_COMMAND */
if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {
- if (WARN_ON(bytes > 2))
+ if (drm_WARN_ON(&i915->drm, bytes > 2))
return -EINVAL;
return emulate_pci_command_write(vgpu, offset, p_data, bytes);
}
switch (rounddown(offset, 4)) {
case PCI_ROM_ADDRESS:
- if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
return -EINVAL;
return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
- if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
return -EINVAL;
return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
case INTEL_GVT_PCI_SWSCI:
- if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
return -EINVAL;
ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
if (ret)
@@ -332,7 +337,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
break;
case INTEL_GVT_PCI_OPREGION:
- if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
return -EINVAL;
ret = intel_vgpu_opregion_base_write_handler(vgpu,
*(u32 *)p_data);
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 9a9329fb8d64..9bfc0ae30157 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -320,9 +320,10 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
int type, unsigned int resolution)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
- if (WARN_ON(resolution >= GVT_EDID_NUM))
+ if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
return -EINVAL;
port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 97bf75890c7d..c093038eb30b 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -276,7 +276,9 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
- WARN_ON(1);
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ drm_WARN_ON(&i915->drm, 1);
return 0;
}
@@ -371,7 +373,9 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
- if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
@@ -399,7 +403,9 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
- if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
@@ -473,6 +479,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
unsigned int offset,
void *p_data)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
int msg_length, ret_msg_size;
int msg, addr, ctrl, op;
@@ -532,9 +539,9 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
* support the gfx driver to do EDID access.
*/
} else {
- if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
+ if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
return;
- if (WARN_ON(msg_length != 4))
+ if (drm_WARN_ON(&i915->drm, msg_length != 4))
return;
if (i2c_edid->edid_available && i2c_edid->slave_selected) {
unsigned char val = edid_get_byte(vgpu);
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 4a4828074cb7..25bd5c052909 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -71,8 +71,10 @@ bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
/* translate a guest gmadr to host gmadr */
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
{
- if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
- "invalid guest gmadr %llx\n", g_addr))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr),
+ "invalid guest gmadr %llx\n", g_addr))
return -EACCES;
if (vgpu_gmadr_is_aperture(vgpu, g_addr))
@@ -87,8 +89,10 @@ int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
/* translate a host gmadr to guest gmadr */
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
{
- if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
- "invalid host gmadr %llx\n", h_addr))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
+ "invalid host gmadr %llx\n", h_addr))
return -EACCES;
if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
@@ -940,6 +944,7 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *e)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;
enum intel_gvt_gtt_type cur_pt_type;
@@ -952,7 +957,9 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
if (!gtt_type_is_pt(cur_pt_type) ||
!gtt_type_is_pt(cur_pt_type + 1)) {
- WARN(1, "Invalid page table type, cur_pt_type is: %d\n", cur_pt_type);
+ drm_WARN(&i915->drm, 1,
+ "Invalid page table type, cur_pt_type is: %d\n",
+ cur_pt_type);
return -EINVAL;
}
@@ -2347,6 +2354,7 @@ int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
static int alloc_scratch_pages(struct intel_vgpu *vgpu,
enum intel_gvt_gtt_type type)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_gtt *gtt = &vgpu->gtt;
struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
int page_entry_num = I915_GTT_PAGE_SIZE >>
@@ -2356,7 +2364,8 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
dma_addr_t daddr;
- if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
+ if (drm_WARN_ON(&i915->drm,
+ type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
return -EINVAL;
scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 288572e27473..1793f6991fa8 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1306,13 +1306,15 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
static int pf_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
u32 val = *(u32 *)p_data;
if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
- WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
- vgpu->id);
+ drm_WARN_ONCE(&i915->drm, true,
+ "VM(%d): guest is trying to scaling a plane\n",
+ vgpu->id);
return 0;
}
@@ -1360,13 +1362,15 @@ static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
u32 mode;
write_vreg(vgpu, offset, p_data, bytes);
mode = vgpu_vreg(vgpu, offset);
if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
- WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
+ drm_WARN_ONCE(&i915->drm, 1,
+ "VM(%d): iGVT-g doesn't support GuC\n",
vgpu->id);
return 0;
}
@@ -1377,10 +1381,12 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
u32 trtte = *(u32 *)p_data;
if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
- WARN(1, "VM(%d): Use physical address for TRTT!\n",
+ drm_WARN(&i915->drm, 1,
+ "VM(%d): Use physical address for TRTT!\n",
vgpu->id);
return -EINVAL;
}
@@ -1682,12 +1688,13 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu,
static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
struct intel_vgpu_execlist *execlist;
u32 data = *(u32 *)p_data;
int ret = 0;
- if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
+ if (drm_WARN_ON(&i915->drm, ring_id < 0 || ring_id >= I915_NUM_ENGINES))
return -EINVAL;
execlist = &vgpu->submission.execlist[ring_id];
@@ -3541,13 +3548,14 @@ bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
void *pdata, unsigned int bytes, bool is_read)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_mmio_info *mmio_info;
struct gvt_mmio_block *mmio_block;
gvt_mmio_func func;
int ret;
- if (WARN_ON(bytes > 8))
+ if (drm_WARN_ON(&i915->drm, bytes > 8))
return -EINVAL;
/*
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 11accd3e1023..4d4783efc9b6 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -244,6 +244,7 @@ int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
unsigned int reg, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_irq_ops *ops = gvt->irq.ops;
struct intel_gvt_irq_info *info;
@@ -255,7 +256,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
vgpu_vreg(vgpu, reg) = ier;
info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
- if (WARN_ON(!info))
+ if (drm_WARN_ON(&i915->drm, !info))
return -EINVAL;
if (info->has_upstream_irq)
@@ -282,6 +283,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
iir_to_regbase(reg));
u32 iir = *(u32 *)p_data;
@@ -289,7 +291,7 @@ int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
(vgpu_vreg(vgpu, reg) ^ iir));
- if (WARN_ON(!info))
+ if (drm_WARN_ON(&i915->drm, !info))
return -EINVAL;
vgpu_vreg(vgpu, reg) &= ~iir;
@@ -319,6 +321,7 @@ static struct intel_gvt_irq_map gen8_irq_map[] = {
static void update_upstream_irq(struct intel_vgpu *vgpu,
struct intel_gvt_irq_info *info)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt_irq *irq = &vgpu->gvt->irq;
struct intel_gvt_irq_map *map = irq->irq_map;
struct intel_gvt_irq_info *up_irq_info = NULL;
@@ -340,7 +343,8 @@ static void update_upstream_irq(struct intel_vgpu *vgpu,
if (!up_irq_info)
up_irq_info = irq->info[map->up_irq_group];
else
- WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
+ drm_WARN_ON(&i915->drm, up_irq_info !=
+ irq->info[map->up_irq_group]);
bit = map->up_irq_bit;
@@ -350,7 +354,7 @@ static void update_upstream_irq(struct intel_vgpu *vgpu,
clear_bits |= (1 << bit);
}
- if (WARN_ON(!up_irq_info))
+ if (drm_WARN_ON(&i915->drm, !up_irq_info))
return;
if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
@@ -618,13 +622,14 @@ static struct intel_gvt_irq_ops gen8_irq_ops = {
void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
enum intel_gvt_event_type event)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_irq *irq = &gvt->irq;
gvt_event_virt_handler_t handler;
struct intel_gvt_irq_ops *ops = gvt->irq.ops;
handler = get_event_virt_handler(irq, event);
- WARN_ON(!handler);
+ drm_WARN_ON(&i915->drm, !handler);
handler(irq, event, vgpu);
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 3259a1fa69e1..f349e7acb375 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -120,6 +120,7 @@ static bool kvmgt_guest_exit(struct kvmgt_guest_info *info);
static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
unsigned long size)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
int total_pages;
int npage;
int ret;
@@ -130,7 +131,7 @@ static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
unsigned long cur_gfn = gfn + npage;
ret = vfio_unpin_pages(mdev_dev(vgpu->vdev.mdev), &cur_gfn, 1);
- WARN_ON(ret != 1);
+ drm_WARN_ON(&i915->drm, ret != 1);
}
}
@@ -808,6 +809,7 @@ static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu)
static void __intel_vgpu_release(struct intel_vgpu *vgpu)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct kvmgt_guest_info *info;
int ret;
@@ -821,11 +823,13 @@ static void __intel_vgpu_release(struct intel_vgpu *vgpu)
ret = vfio_unregister_notifier(mdev_dev(vgpu->vdev.mdev), VFIO_IOMMU_NOTIFY,
&vgpu->vdev.iommu_notifier);
- WARN(ret, "vfio_unregister_notifier for iommu failed: %d\n", ret);
+ drm_WARN(&i915->drm, ret,
+ "vfio_unregister_notifier for iommu failed: %d\n", ret);
ret = vfio_unregister_notifier(mdev_dev(vgpu->vdev.mdev), VFIO_GROUP_NOTIFY,
&vgpu->vdev.group_notifier);
- WARN(ret, "vfio_unregister_notifier for group failed: %d\n", ret);
+ drm_WARN(&i915->drm, ret,
+ "vfio_unregister_notifier for group failed: %d\n", ret);
/* dereference module reference taken at open */
module_put(THIS_MODULE);
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index a55178884d67..1046a68da888 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -102,6 +102,7 @@ static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
unsigned int offset = 0;
int ret = -EINVAL;
@@ -114,15 +115,17 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
- if (WARN_ON(bytes > 8))
+ if (drm_WARN_ON(&i915->drm, bytes > 8))
goto err;
if (reg_is_gtt(gvt, offset)) {
- if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
+ !IS_ALIGNED(offset, 8)))
goto err;
- if (WARN_ON(bytes != 4 && bytes != 8))
+ if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
goto err;
- if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
+ if (drm_WARN_ON(&i915->drm,
+ !reg_is_gtt(gvt, offset + bytes - 1)))
goto err;
ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
@@ -132,16 +135,16 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
goto out;
}
- if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
+ if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
goto out;
}
- if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
+ if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))
goto err;
if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
- if (WARN_ON(!IS_ALIGNED(offset, bytes)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))
goto err;
}
@@ -174,6 +177,7 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
unsigned int offset = 0;
int ret = -EINVAL;
@@ -187,15 +191,17 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
- if (WARN_ON(bytes > 8))
+ if (drm_WARN_ON(&i915->drm, bytes > 8))
goto err;
if (reg_is_gtt(gvt, offset)) {
- if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
+ !IS_ALIGNED(offset, 8)))
goto err;
- if (WARN_ON(bytes != 4 && bytes != 8))
+ if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
goto err;
- if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
+ if (drm_WARN_ON(&i915->drm,
+ !reg_is_gtt(gvt, offset + bytes - 1)))
goto err;
ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
@@ -205,7 +211,7 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
goto out;
}
- if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
+ if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
goto out;
}
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index a4a1de347af0..46c291e4926b 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -392,6 +392,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
int ring_id)
{
+ struct drm_i915_private *i915 = pre->gvt->dev_priv;
struct drm_i915_private *dev_priv;
i915_reg_t offset, l3_offset;
u32 old_v, new_v;
@@ -406,7 +407,7 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
int i;
dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
- if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
+ if (drm_WARN_ON(&i915->drm, ring_id >= ARRAY_SIZE(regs)))
return;
if (ring_id == RCS0 && IS_GEN(dev_priv, 9))
@@ -551,9 +552,10 @@ static void switch_mmio(struct intel_vgpu *pre,
void intel_gvt_switch_mmio(struct intel_vgpu *pre,
struct intel_vgpu *next, int ring_id)
{
+ struct drm_i915_private *i915 = pre->gvt->dev_priv;
struct drm_i915_private *dev_priv;
- if (WARN_ON(!pre && !next))
+ if (drm_WARN_ON(&i915->drm, !pre && !next))
return;
gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 685d1e04a5ff..cc89afd7b5f1 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1309,6 +1309,7 @@ int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
intel_engine_mask_t engine_mask,
unsigned int interface)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_submission *s = &vgpu->submission;
const struct intel_vgpu_submission_ops *ops[] = {
[INTEL_VGPU_EXECLIST_SUBMISSION] =
@@ -1316,10 +1317,11 @@ int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
};
int ret;
- if (WARN_ON(interface >= ARRAY_SIZE(ops)))
+ if (drm_WARN_ON(&i915->drm, interface >= ARRAY_SIZE(ops)))
return -EINVAL;
- if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
+ if (drm_WARN_ON(&i915->drm,
+ interface == 0 && engine_mask != ALL_ENGINES))
return -EINVAL;
if (s->active)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 85bd9bf4f6ee..6f35e9a3a561 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -37,6 +37,7 @@
void populate_pvinfo_page(struct intel_vgpu *vgpu)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
/* setup the ballooning information */
vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
@@ -69,7 +70,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
- WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
+ drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
}
#define VGPU_MAX_WEIGHT 16
@@ -270,11 +271,12 @@ void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
*/
void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
mutex_lock(&vgpu->vgpu_lock);
- WARN(vgpu->active, "vGPU is still active!\n");
+ drm_WARN(&i915->drm, vgpu->active, "vGPU is still active!\n");
intel_gvt_debugfs_remove_vgpu(vgpu);
intel_vgpu_clean_sched_policy(vgpu);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [Intel-gfx] [PATCH v7 8/8] drm/i915/gvt: Make WARN* drm specific where vgpu ptr is available
From: Pankaj Bharadiya @ 2020-02-20 16:55 UTC (permalink / raw)
To: jani.nikula, daniel, intel-gfx, dri-devel, Zhenyu Wang, Zhi Wang,
Joonas Lahtinen, Rodrigo Vivi, David Airlie
Cc: pankaj.laxminarayan.bharadiya
In-Reply-To: <20200220165507.16823-1-pankaj.laxminarayan.bharadiya@intel.com>
Drm specific drm_WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device struct pointer is readily
available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@@
identifier func, T;
@@
func(struct intel_vgpu *T,...) {
+struct drm_i915_private *i915 = T->gvt->dev_priv;
<+...
(
-WARN(
+drm_WARN(&i915->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&i915->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&i915->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&i915->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
---
drivers/gpu/drm/i915/gvt/cfg_space.c | 23 +++++++++++--------
drivers/gpu/drm/i915/gvt/display.c | 3 ++-
drivers/gpu/drm/i915/gvt/edid.c | 17 +++++++++-----
drivers/gpu/drm/i915/gvt/gtt.c | 21 ++++++++++++-----
drivers/gpu/drm/i915/gvt/handlers.c | 20 ++++++++++++-----
drivers/gpu/drm/i915/gvt/interrupt.c | 15 ++++++++-----
drivers/gpu/drm/i915/gvt/kvmgt.c | 10 ++++++---
drivers/gpu/drm/i915/gvt/mmio.c | 30 +++++++++++++++----------
drivers/gpu/drm/i915/gvt/mmio_context.c | 6 +++--
drivers/gpu/drm/i915/gvt/scheduler.c | 6 +++--
drivers/gpu/drm/i915/gvt/vgpu.c | 6 +++--
11 files changed, 104 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
index 19cf1bbe059d..7fd16bab2f39 100644
--- a/drivers/gpu/drm/i915/gvt/cfg_space.c
+++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
@@ -106,10 +106,13 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,
int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
- if (WARN_ON(bytes > 4))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN_ON(&i915->drm, bytes > 4))
return -EINVAL;
- if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
+ if (drm_WARN_ON(&i915->drm,
+ offset + bytes > vgpu->gvt->device_info.cfg_space_size))
return -EINVAL;
memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
@@ -297,34 +300,36 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
int ret;
- if (WARN_ON(bytes > 4))
+ if (drm_WARN_ON(&i915->drm, bytes > 4))
return -EINVAL;
- if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
+ if (drm_WARN_ON(&i915->drm,
+ offset + bytes > vgpu->gvt->device_info.cfg_space_size))
return -EINVAL;
/* First check if it's PCI_COMMAND */
if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {
- if (WARN_ON(bytes > 2))
+ if (drm_WARN_ON(&i915->drm, bytes > 2))
return -EINVAL;
return emulate_pci_command_write(vgpu, offset, p_data, bytes);
}
switch (rounddown(offset, 4)) {
case PCI_ROM_ADDRESS:
- if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
return -EINVAL;
return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
- if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
return -EINVAL;
return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
case INTEL_GVT_PCI_SWSCI:
- if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
return -EINVAL;
ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
if (ret)
@@ -332,7 +337,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
break;
case INTEL_GVT_PCI_OPREGION:
- if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
return -EINVAL;
ret = intel_vgpu_opregion_base_write_handler(vgpu,
*(u32 *)p_data);
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 9a9329fb8d64..9bfc0ae30157 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -320,9 +320,10 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
int type, unsigned int resolution)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
- if (WARN_ON(resolution >= GVT_EDID_NUM))
+ if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
return -EINVAL;
port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 97bf75890c7d..c093038eb30b 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -276,7 +276,9 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
- WARN_ON(1);
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ drm_WARN_ON(&i915->drm, 1);
return 0;
}
@@ -371,7 +373,9 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
- if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
@@ -399,7 +403,9 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
- if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
@@ -473,6 +479,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
unsigned int offset,
void *p_data)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
int msg_length, ret_msg_size;
int msg, addr, ctrl, op;
@@ -532,9 +539,9 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
* support the gfx driver to do EDID access.
*/
} else {
- if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
+ if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
return;
- if (WARN_ON(msg_length != 4))
+ if (drm_WARN_ON(&i915->drm, msg_length != 4))
return;
if (i2c_edid->edid_available && i2c_edid->slave_selected) {
unsigned char val = edid_get_byte(vgpu);
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 4a4828074cb7..25bd5c052909 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -71,8 +71,10 @@ bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
/* translate a guest gmadr to host gmadr */
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
{
- if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
- "invalid guest gmadr %llx\n", g_addr))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr),
+ "invalid guest gmadr %llx\n", g_addr))
return -EACCES;
if (vgpu_gmadr_is_aperture(vgpu, g_addr))
@@ -87,8 +89,10 @@ int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
/* translate a host gmadr to guest gmadr */
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
{
- if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
- "invalid host gmadr %llx\n", h_addr))
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+
+ if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
+ "invalid host gmadr %llx\n", h_addr))
return -EACCES;
if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
@@ -940,6 +944,7 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *e)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;
enum intel_gvt_gtt_type cur_pt_type;
@@ -952,7 +957,9 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
if (!gtt_type_is_pt(cur_pt_type) ||
!gtt_type_is_pt(cur_pt_type + 1)) {
- WARN(1, "Invalid page table type, cur_pt_type is: %d\n", cur_pt_type);
+ drm_WARN(&i915->drm, 1,
+ "Invalid page table type, cur_pt_type is: %d\n",
+ cur_pt_type);
return -EINVAL;
}
@@ -2347,6 +2354,7 @@ int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
static int alloc_scratch_pages(struct intel_vgpu *vgpu,
enum intel_gvt_gtt_type type)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_gtt *gtt = &vgpu->gtt;
struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
int page_entry_num = I915_GTT_PAGE_SIZE >>
@@ -2356,7 +2364,8 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
dma_addr_t daddr;
- if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
+ if (drm_WARN_ON(&i915->drm,
+ type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
return -EINVAL;
scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 288572e27473..1793f6991fa8 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1306,13 +1306,15 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
static int pf_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
u32 val = *(u32 *)p_data;
if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
- WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
- vgpu->id);
+ drm_WARN_ONCE(&i915->drm, true,
+ "VM(%d): guest is trying to scaling a plane\n",
+ vgpu->id);
return 0;
}
@@ -1360,13 +1362,15 @@ static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
u32 mode;
write_vreg(vgpu, offset, p_data, bytes);
mode = vgpu_vreg(vgpu, offset);
if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
- WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
+ drm_WARN_ONCE(&i915->drm, 1,
+ "VM(%d): iGVT-g doesn't support GuC\n",
vgpu->id);
return 0;
}
@@ -1377,10 +1381,12 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
u32 trtte = *(u32 *)p_data;
if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
- WARN(1, "VM(%d): Use physical address for TRTT!\n",
+ drm_WARN(&i915->drm, 1,
+ "VM(%d): Use physical address for TRTT!\n",
vgpu->id);
return -EINVAL;
}
@@ -1682,12 +1688,13 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu,
static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
struct intel_vgpu_execlist *execlist;
u32 data = *(u32 *)p_data;
int ret = 0;
- if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
+ if (drm_WARN_ON(&i915->drm, ring_id < 0 || ring_id >= I915_NUM_ENGINES))
return -EINVAL;
execlist = &vgpu->submission.execlist[ring_id];
@@ -3541,13 +3548,14 @@ bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
void *pdata, unsigned int bytes, bool is_read)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_mmio_info *mmio_info;
struct gvt_mmio_block *mmio_block;
gvt_mmio_func func;
int ret;
- if (WARN_ON(bytes > 8))
+ if (drm_WARN_ON(&i915->drm, bytes > 8))
return -EINVAL;
/*
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 11accd3e1023..4d4783efc9b6 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -244,6 +244,7 @@ int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
unsigned int reg, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_irq_ops *ops = gvt->irq.ops;
struct intel_gvt_irq_info *info;
@@ -255,7 +256,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
vgpu_vreg(vgpu, reg) = ier;
info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
- if (WARN_ON(!info))
+ if (drm_WARN_ON(&i915->drm, !info))
return -EINVAL;
if (info->has_upstream_irq)
@@ -282,6 +283,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
iir_to_regbase(reg));
u32 iir = *(u32 *)p_data;
@@ -289,7 +291,7 @@ int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
(vgpu_vreg(vgpu, reg) ^ iir));
- if (WARN_ON(!info))
+ if (drm_WARN_ON(&i915->drm, !info))
return -EINVAL;
vgpu_vreg(vgpu, reg) &= ~iir;
@@ -319,6 +321,7 @@ static struct intel_gvt_irq_map gen8_irq_map[] = {
static void update_upstream_irq(struct intel_vgpu *vgpu,
struct intel_gvt_irq_info *info)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt_irq *irq = &vgpu->gvt->irq;
struct intel_gvt_irq_map *map = irq->irq_map;
struct intel_gvt_irq_info *up_irq_info = NULL;
@@ -340,7 +343,8 @@ static void update_upstream_irq(struct intel_vgpu *vgpu,
if (!up_irq_info)
up_irq_info = irq->info[map->up_irq_group];
else
- WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
+ drm_WARN_ON(&i915->drm, up_irq_info !=
+ irq->info[map->up_irq_group]);
bit = map->up_irq_bit;
@@ -350,7 +354,7 @@ static void update_upstream_irq(struct intel_vgpu *vgpu,
clear_bits |= (1 << bit);
}
- if (WARN_ON(!up_irq_info))
+ if (drm_WARN_ON(&i915->drm, !up_irq_info))
return;
if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
@@ -618,13 +622,14 @@ static struct intel_gvt_irq_ops gen8_irq_ops = {
void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
enum intel_gvt_event_type event)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_irq *irq = &gvt->irq;
gvt_event_virt_handler_t handler;
struct intel_gvt_irq_ops *ops = gvt->irq.ops;
handler = get_event_virt_handler(irq, event);
- WARN_ON(!handler);
+ drm_WARN_ON(&i915->drm, !handler);
handler(irq, event, vgpu);
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 3259a1fa69e1..f349e7acb375 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -120,6 +120,7 @@ static bool kvmgt_guest_exit(struct kvmgt_guest_info *info);
static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
unsigned long size)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
int total_pages;
int npage;
int ret;
@@ -130,7 +131,7 @@ static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
unsigned long cur_gfn = gfn + npage;
ret = vfio_unpin_pages(mdev_dev(vgpu->vdev.mdev), &cur_gfn, 1);
- WARN_ON(ret != 1);
+ drm_WARN_ON(&i915->drm, ret != 1);
}
}
@@ -808,6 +809,7 @@ static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu)
static void __intel_vgpu_release(struct intel_vgpu *vgpu)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct kvmgt_guest_info *info;
int ret;
@@ -821,11 +823,13 @@ static void __intel_vgpu_release(struct intel_vgpu *vgpu)
ret = vfio_unregister_notifier(mdev_dev(vgpu->vdev.mdev), VFIO_IOMMU_NOTIFY,
&vgpu->vdev.iommu_notifier);
- WARN(ret, "vfio_unregister_notifier for iommu failed: %d\n", ret);
+ drm_WARN(&i915->drm, ret,
+ "vfio_unregister_notifier for iommu failed: %d\n", ret);
ret = vfio_unregister_notifier(mdev_dev(vgpu->vdev.mdev), VFIO_GROUP_NOTIFY,
&vgpu->vdev.group_notifier);
- WARN(ret, "vfio_unregister_notifier for group failed: %d\n", ret);
+ drm_WARN(&i915->drm, ret,
+ "vfio_unregister_notifier for group failed: %d\n", ret);
/* dereference module reference taken at open */
module_put(THIS_MODULE);
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index a55178884d67..1046a68da888 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -102,6 +102,7 @@ static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
unsigned int offset = 0;
int ret = -EINVAL;
@@ -114,15 +115,17 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
- if (WARN_ON(bytes > 8))
+ if (drm_WARN_ON(&i915->drm, bytes > 8))
goto err;
if (reg_is_gtt(gvt, offset)) {
- if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
+ !IS_ALIGNED(offset, 8)))
goto err;
- if (WARN_ON(bytes != 4 && bytes != 8))
+ if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
goto err;
- if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
+ if (drm_WARN_ON(&i915->drm,
+ !reg_is_gtt(gvt, offset + bytes - 1)))
goto err;
ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
@@ -132,16 +135,16 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
goto out;
}
- if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
+ if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
goto out;
}
- if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
+ if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))
goto err;
if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
- if (WARN_ON(!IS_ALIGNED(offset, bytes)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))
goto err;
}
@@ -174,6 +177,7 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
unsigned int offset = 0;
int ret = -EINVAL;
@@ -187,15 +191,17 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
- if (WARN_ON(bytes > 8))
+ if (drm_WARN_ON(&i915->drm, bytes > 8))
goto err;
if (reg_is_gtt(gvt, offset)) {
- if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
+ if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
+ !IS_ALIGNED(offset, 8)))
goto err;
- if (WARN_ON(bytes != 4 && bytes != 8))
+ if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
goto err;
- if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
+ if (drm_WARN_ON(&i915->drm,
+ !reg_is_gtt(gvt, offset + bytes - 1)))
goto err;
ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
@@ -205,7 +211,7 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
goto out;
}
- if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
+ if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
goto out;
}
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index a4a1de347af0..46c291e4926b 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -392,6 +392,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
int ring_id)
{
+ struct drm_i915_private *i915 = pre->gvt->dev_priv;
struct drm_i915_private *dev_priv;
i915_reg_t offset, l3_offset;
u32 old_v, new_v;
@@ -406,7 +407,7 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
int i;
dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
- if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
+ if (drm_WARN_ON(&i915->drm, ring_id >= ARRAY_SIZE(regs)))
return;
if (ring_id == RCS0 && IS_GEN(dev_priv, 9))
@@ -551,9 +552,10 @@ static void switch_mmio(struct intel_vgpu *pre,
void intel_gvt_switch_mmio(struct intel_vgpu *pre,
struct intel_vgpu *next, int ring_id)
{
+ struct drm_i915_private *i915 = pre->gvt->dev_priv;
struct drm_i915_private *dev_priv;
- if (WARN_ON(!pre && !next))
+ if (drm_WARN_ON(&i915->drm, !pre && !next))
return;
gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 685d1e04a5ff..cc89afd7b5f1 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1309,6 +1309,7 @@ int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
intel_engine_mask_t engine_mask,
unsigned int interface)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_submission *s = &vgpu->submission;
const struct intel_vgpu_submission_ops *ops[] = {
[INTEL_VGPU_EXECLIST_SUBMISSION] =
@@ -1316,10 +1317,11 @@ int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
};
int ret;
- if (WARN_ON(interface >= ARRAY_SIZE(ops)))
+ if (drm_WARN_ON(&i915->drm, interface >= ARRAY_SIZE(ops)))
return -EINVAL;
- if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
+ if (drm_WARN_ON(&i915->drm,
+ interface == 0 && engine_mask != ALL_ENGINES))
return -EINVAL;
if (s->active)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 85bd9bf4f6ee..6f35e9a3a561 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -37,6 +37,7 @@
void populate_pvinfo_page(struct intel_vgpu *vgpu)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
/* setup the ballooning information */
vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
@@ -69,7 +70,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
- WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
+ drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
}
#define VGPU_MAX_WEIGHT 16
@@ -270,11 +271,12 @@ void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
*/
void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_gvt *gvt = vgpu->gvt;
mutex_lock(&vgpu->vgpu_lock);
- WARN(vgpu->active, "vGPU is still active!\n");
+ drm_WARN(&i915->drm, vgpu->active, "vGPU is still active!\n");
intel_gvt_debugfs_remove_vgpu(vgpu);
intel_vgpu_clean_sched_policy(vgpu);
--
2.23.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [Intel-gfx] [PATCH v7 7/8] drm/i915/gvt: Make WARN* drm specific where drm_priv ptr is available
From: Pankaj Bharadiya @ 2020-02-20 16:55 UTC (permalink / raw)
To: jani.nikula, daniel, intel-gfx, dri-devel, Zhenyu Wang, Zhi Wang,
Joonas Lahtinen, Rodrigo Vivi, David Airlie
Cc: pankaj.laxminarayan.bharadiya
In-Reply-To: <20200220165507.16823-1-pankaj.laxminarayan.bharadiya@intel.com>
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is
readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
---
drivers/gpu/drm/i915/gvt/aperture_gm.c | 6 +++---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/gvt/display.c | 3 ++-
drivers/gpu/drm/i915/gvt/dmabuf.c | 4 ++--
drivers/gpu/drm/i915/gvt/edid.c | 2 +-
drivers/gpu/drm/i915/gvt/gvt.c | 4 ++--
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
8 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index 771420453f82..29eed8400647 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -134,11 +134,11 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
- if (WARN_ON(fence >= vgpu_fence_sz(vgpu)))
+ if (drm_WARN_ON(&dev_priv->drm, fence >= vgpu_fence_sz(vgpu)))
return;
reg = vgpu->fence.regs[fence];
- if (WARN_ON(!reg))
+ if (drm_WARN_ON(&dev_priv->drm, !reg))
return;
fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
@@ -167,7 +167,7 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu)
struct i915_fence_reg *reg;
u32 i;
- if (WARN_ON(!vgpu_fence_sz(vgpu)))
+ if (drm_WARN_ON(&dev_priv->drm, !vgpu_fence_sz(vgpu)))
return;
intel_runtime_pm_get(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 21a176cd8acc..73a2891114a4 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1230,7 +1230,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
dword2 = cmd_val(s, 2);
v = (dword0 & GENMASK(21, 19)) >> 19;
- if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
+ if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
return -EBADRQC;
info->pipe = gen8_plane_code[v].pipe;
@@ -1250,7 +1250,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
info->stride_reg = SPRSTRIDE(info->pipe);
info->surf_reg = SPRSURF(info->pipe);
} else {
- WARN_ON(1);
+ drm_WARN_ON(&dev_priv->drm, 1);
return -EBADRQC;
}
return 0;
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index e1c313da6c00..9a9329fb8d64 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -71,7 +71,8 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
+ if (drm_WARN_ON(&dev_priv->drm,
+ pipe < PIPE_A || pipe >= I915_MAX_PIPES))
return -EINVAL;
if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 2477a1e5a166..b854bd243e11 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -67,11 +67,11 @@ static int vgpu_gem_get_pages(
u32 page_num;
fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info;
- if (WARN_ON(!fb_info))
+ if (drm_WARN_ON(&dev_priv->drm, !fb_info))
return -ENODEV;
vgpu = fb_info->obj->vgpu;
- if (WARN_ON(!vgpu))
+ if (drm_WARN_ON(&dev_priv->drm, !vgpu))
return -ENODEV;
st = kmalloc(sizeof(*st), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 1fe6124918f1..97bf75890c7d 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -153,7 +153,7 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
port = cnp_get_port_from_gmbus0(pin_select);
else
port = get_port_from_gmbus0(pin_select);
- if (WARN_ON(port < 0))
+ if (drm_WARN_ON(&dev_priv->drm, port < 0))
return 0;
vgpu->display.i2c_edid.state = I2C_GMBUS;
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index 8f37eefa0a02..d51684627f3d 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -267,7 +267,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv)
{
struct intel_gvt *gvt = to_gvt(dev_priv);
- if (WARN_ON(!gvt))
+ if (drm_WARN_ON(&dev_priv->drm, !gvt))
return;
intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu);
@@ -306,7 +306,7 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
struct intel_vgpu *vgpu;
int ret;
- if (WARN_ON(dev_priv->gvt))
+ if (drm_WARN_ON(&dev_priv->drm, dev_priv->gvt))
return -EEXIST;
gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index ae6700dc9d73..288572e27473 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -836,7 +836,7 @@ static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
event = AUX_CHANNEL_D;
else {
- WARN_ON(true);
+ drm_WARN_ON(&dev_priv->drm, true);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index aaf15916d29a..a4a1de347af0 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -357,7 +357,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
if (!regs)
return;
- if (WARN_ON(ring_id >= cnt))
+ if (drm_WARN_ON(&dev_priv->drm, ring_id >= cnt))
return;
if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
--
2.23.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [Intel-gfx] [PATCH v7 7/8] drm/i915/gvt: Make WARN* drm specific where drm_priv ptr is available
From: Pankaj Bharadiya @ 2020-02-20 16:55 UTC (permalink / raw)
To: jani.nikula, daniel, intel-gfx, dri-devel, Zhenyu Wang, Zhi Wang,
Joonas Lahtinen, Rodrigo Vivi, David Airlie
In-Reply-To: <20200220165507.16823-1-pankaj.laxminarayan.bharadiya@intel.com>
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is
readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
---
drivers/gpu/drm/i915/gvt/aperture_gm.c | 6 +++---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/gvt/display.c | 3 ++-
drivers/gpu/drm/i915/gvt/dmabuf.c | 4 ++--
drivers/gpu/drm/i915/gvt/edid.c | 2 +-
drivers/gpu/drm/i915/gvt/gvt.c | 4 ++--
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
8 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index 771420453f82..29eed8400647 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -134,11 +134,11 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
- if (WARN_ON(fence >= vgpu_fence_sz(vgpu)))
+ if (drm_WARN_ON(&dev_priv->drm, fence >= vgpu_fence_sz(vgpu)))
return;
reg = vgpu->fence.regs[fence];
- if (WARN_ON(!reg))
+ if (drm_WARN_ON(&dev_priv->drm, !reg))
return;
fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
@@ -167,7 +167,7 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu)
struct i915_fence_reg *reg;
u32 i;
- if (WARN_ON(!vgpu_fence_sz(vgpu)))
+ if (drm_WARN_ON(&dev_priv->drm, !vgpu_fence_sz(vgpu)))
return;
intel_runtime_pm_get(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 21a176cd8acc..73a2891114a4 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1230,7 +1230,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
dword2 = cmd_val(s, 2);
v = (dword0 & GENMASK(21, 19)) >> 19;
- if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
+ if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
return -EBADRQC;
info->pipe = gen8_plane_code[v].pipe;
@@ -1250,7 +1250,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
info->stride_reg = SPRSTRIDE(info->pipe);
info->surf_reg = SPRSURF(info->pipe);
} else {
- WARN_ON(1);
+ drm_WARN_ON(&dev_priv->drm, 1);
return -EBADRQC;
}
return 0;
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index e1c313da6c00..9a9329fb8d64 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -71,7 +71,8 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
+ if (drm_WARN_ON(&dev_priv->drm,
+ pipe < PIPE_A || pipe >= I915_MAX_PIPES))
return -EINVAL;
if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 2477a1e5a166..b854bd243e11 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -67,11 +67,11 @@ static int vgpu_gem_get_pages(
u32 page_num;
fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info;
- if (WARN_ON(!fb_info))
+ if (drm_WARN_ON(&dev_priv->drm, !fb_info))
return -ENODEV;
vgpu = fb_info->obj->vgpu;
- if (WARN_ON(!vgpu))
+ if (drm_WARN_ON(&dev_priv->drm, !vgpu))
return -ENODEV;
st = kmalloc(sizeof(*st), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 1fe6124918f1..97bf75890c7d 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -153,7 +153,7 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
port = cnp_get_port_from_gmbus0(pin_select);
else
port = get_port_from_gmbus0(pin_select);
- if (WARN_ON(port < 0))
+ if (drm_WARN_ON(&dev_priv->drm, port < 0))
return 0;
vgpu->display.i2c_edid.state = I2C_GMBUS;
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index 8f37eefa0a02..d51684627f3d 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -267,7 +267,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv)
{
struct intel_gvt *gvt = to_gvt(dev_priv);
- if (WARN_ON(!gvt))
+ if (drm_WARN_ON(&dev_priv->drm, !gvt))
return;
intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu);
@@ -306,7 +306,7 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
struct intel_vgpu *vgpu;
int ret;
- if (WARN_ON(dev_priv->gvt))
+ if (drm_WARN_ON(&dev_priv->drm, dev_priv->gvt))
return -EEXIST;
gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index ae6700dc9d73..288572e27473 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -836,7 +836,7 @@ static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
event = AUX_CHANNEL_D;
else {
- WARN_ON(true);
+ drm_WARN_ON(&dev_priv->drm, true);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index aaf15916d29a..a4a1de347af0 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -357,7 +357,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
if (!regs)
return;
- if (WARN_ON(ring_id >= cnt))
+ if (drm_WARN_ON(&dev_priv->drm, ring_id >= cnt))
return;
if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
--
2.23.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related
* [Intel-gfx] [PATCH v7 6/8] drm/i915/display/hdcp: Make WARN* drm specific where drm_priv ptr is available
From: Pankaj Bharadiya @ 2020-02-20 16:55 UTC (permalink / raw)
To: jani.nikula, daniel, intel-gfx, dri-devel, Joonas Lahtinen,
Rodrigo Vivi, David Airlie, Ramalingam C, Uma Shankar,
Chris Wilson, Ville Syrjälä, Daniele Ceraolo Spurio
Cc: pankaj.laxminarayan.bharadiya
In-Reply-To: <20200220165507.16823-1-pankaj.laxminarayan.bharadiya@intel.com>
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is
readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 30e0a3aa9d57..229b4e329864 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -872,7 +872,8 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
goto out;
}
- if (WARN_ON(!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) {
+ if (drm_WARN_ON(&dev_priv->drm,
+ !intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) {
drm_err(&dev_priv->drm,
"%s:%d HDCP link stopped encryption,%x\n",
connector->base.name, connector->base.base.id,
@@ -1561,8 +1562,9 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
int ret;
- WARN_ON(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
- LINK_ENCRYPTION_STATUS);
+ drm_WARN_ON(&dev_priv->drm,
+ intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS);
if (hdcp->shim->toggle_signalling) {
ret = hdcp->shim->toggle_signalling(intel_dig_port, true);
if (ret) {
@@ -1599,8 +1601,8 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
int ret;
- WARN_ON(!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
- LINK_ENCRYPTION_STATUS));
+ drm_WARN_ON(&dev_priv->drm, !(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS));
intel_de_write(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port),
intel_de_read(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port)) & ~CTL_LINK_ENCRYPTION_REQ);
@@ -1720,7 +1722,8 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
goto out;
}
- if (WARN_ON(!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) {
+ if (drm_WARN_ON(&dev_priv->drm,
+ !intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) {
drm_err(&dev_priv->drm,
"HDCP2.2 link stopped the encryption, %x\n",
intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)));
@@ -1916,7 +1919,7 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
return;
mutex_lock(&dev_priv->hdcp_comp_mutex);
- WARN_ON(dev_priv->hdcp_comp_added);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->hdcp_comp_added);
dev_priv->hdcp_comp_added = true;
mutex_unlock(&dev_priv->hdcp_comp_mutex);
@@ -1990,7 +1993,8 @@ int intel_hdcp_enable(struct intel_connector *connector,
return -ENOENT;
mutex_lock(&hdcp->mutex);
- WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
+ drm_WARN_ON(&dev_priv->drm,
+ hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
if (INTEL_GEN(dev_priv) >= 12) {
--
2.23.0
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
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