* Re: RFC: Split EPT huge pages in advance of dirty logging
From: Ben Gardon @ 2020-02-20 17:34 UTC (permalink / raw)
To: Zhoujian (jay), Junaid Shahid
Cc: Peter Xu, kvm@vger.kernel.org, qemu-devel@nongnu.org,
pbonzini@redhat.com, dgilbert@redhat.com, quintela@redhat.com,
Liujinsong (Paul), linfeng (M), wangxin (U), Huangweidong (C)
In-Reply-To: <B2D15215269B544CADD246097EACE7474BB03772@DGGEMM528-MBX.china.huawei.com>
On Thu, Feb 20, 2020 at 5:53 AM Zhoujian (jay) <jianjay.zhou@huawei.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Peter Xu [mailto:peterx@redhat.com]
> > Sent: Thursday, February 20, 2020 1:19 AM
> > To: Zhoujian (jay) <jianjay.zhou@huawei.com>
> > Cc: kvm@vger.kernel.org; qemu-devel@nongnu.org; pbonzini@redhat.com;
> > dgilbert@redhat.com; quintela@redhat.com; Liujinsong (Paul)
> > <liu.jinsong@huawei.com>; linfeng (M) <linfeng23@huawei.com>; wangxin (U)
> > <wangxinxin.wang@huawei.com>; Huangweidong (C)
> > <weidong.huang@huawei.com>
> > Subject: Re: RFC: Split EPT huge pages in advance of dirty logging
> >
> > On Wed, Feb 19, 2020 at 01:19:08PM +0000, Zhoujian (jay) wrote:
> > > Hi Peter,
> > >
> > > > -----Original Message-----
> > > > From: Peter Xu [mailto:peterx@redhat.com]
> > > > Sent: Wednesday, February 19, 2020 1:43 AM
> > > > To: Zhoujian (jay) <jianjay.zhou@huawei.com>
> > > > Cc: kvm@vger.kernel.org; qemu-devel@nongnu.org;
> > pbonzini@redhat.com;
> > > > dgilbert@redhat.com; quintela@redhat.com; Liujinsong (Paul)
> > > > <liu.jinsong@huawei.com>; linfeng (M) <linfeng23@huawei.com>;
> > > > wangxin (U) <wangxinxin.wang@huawei.com>; Huangweidong (C)
> > > > <weidong.huang@huawei.com>
> > > > Subject: Re: RFC: Split EPT huge pages in advance of dirty logging
> > > >
> > > > On Tue, Feb 18, 2020 at 01:13:47PM +0000, Zhoujian (jay) wrote:
> > > > > Hi all,
> > > > >
> > > > > We found that the guest will be soft-lockup occasionally when live
> > > > > migrating a 60 vCPU, 512GiB huge page and memory sensitive VM. The
> > > > > reason is clear, almost all of the vCPUs are waiting for the KVM
> > > > > MMU spin-lock to create 4K SPTEs when the huge pages are write
> > > > > protected. This
> > > > phenomenon is also described in this patch set:
> > > > > https://patchwork.kernel.org/cover/11163459/
> > > > > which aims to handle page faults in parallel more efficiently.
> > > > >
> > > > > Our idea is to use the migration thread to touch all of the guest
> > > > > memory in the granularity of 4K before enabling dirty logging. To
> > > > > be more specific, we split all the PDPE_LEVEL SPTEs into
> > > > > DIRECTORY_LEVEL SPTEs as the first step, and then split all the
> > > > > DIRECTORY_LEVEL SPTEs into
> > > > PAGE_TABLE_LEVEL SPTEs as the following step.
> > > >
> > > > IIUC, QEMU will prefer to use huge pages for all the anonymous
> > > > ramblocks (please refer to ram_block_add):
> > > >
> > > > qemu_madvise(new_block->host, new_block->max_length,
> > > > QEMU_MADV_HUGEPAGE);
> > >
> > > Yes, you're right
> > >
> > > >
> > > > Another alternative I can think of is to add an extra parameter to
> > > > QEMU to explicitly disable huge pages (so that can even be
> > > > MADV_NOHUGEPAGE instead of MADV_HUGEPAGE). However that
> > should also
> > > > drag down the performance for the whole lifecycle of the VM.
> > >
> > > From the performance point of view, it is better to keep the huge
> > > pages when the VM is not in the live migration state.
> > >
> > > > A 3rd option is to make a QMP
> > > > command to dynamically turn huge pages on/off for ramblocks globally.
> > >
> > > We're searching a dynamic method too.
> > > We plan to add two new flags for each memory slot, say
> > > KVM_MEM_FORCE_PT_DIRECTORY_PAGES and
> > > KVM_MEM_FORCE_PT_PAGE_TABLE_PAGES. These flags can be set through
> > > KVM_SET_USER_MEMORY_REGION ioctl.
> > >
> > > The mapping_level which is called by tdp_page_fault in the kernel side
> > > will return PT_DIRECTORY_LEVEL if the
> > KVM_MEM_FORCE_PT_DIRECTORY_PAGES
> > > flag of the memory slot is set, and return PT_PAGE_TABLE_LEVEL if the
> > > KVM_MEM_FORCE_PT_PAGE_TABLE_PAGES flag is set.
> > >
> > > The key steps to split the huge pages in advance of enabling dirty log
> > > is as follows:
> > > 1. The migration thread in user space uses
> > KVM_SET_USER_MEMORY_REGION
> > > ioctl to set the KVM_MEM_FORCE_PT_DIRECTORY_PAGES flag for each
> > memory
> > > slot.
> > > 2. The migration thread continues to use the KVM_SPLIT_HUGE_PAGES
> > > ioctl (which is newly added) to do the splitting of large pages in the
> > > kernel side.
> > > 3. A new vCPU is created temporally(do some initialization but will
> > > not
> > > run) to help to do the work, i.e. as the parameter of the tdp_page_fault.
> > > 4. Collect the GPA ranges of all the memory slots with the
> > > KVM_MEM_FORCE_PT_DIRECTORY_PAGES flag set.
> > > 5. Split the 1G huge pages(collected in step 4) into 2M by calling
> > > tdp_page_fault, since the mapping_level will return
> > > PT_DIRECTORY_LEVEL. Here is the main difference from the usual path
> > > which is caused by the Guest side(EPT violation/misconfig etc), we
> > > call it directly in the hypervisor side.
> > > 6. Do some cleanups, i.e. free the vCPU related resources 7. The
> > > KVM_SPLIT_HUGE_PAGES ioctl returned to the user space side.
> > > 8. Using KVM_MEM_FORCE_PT_PAGE_TABLE_PAGES instread of
> > > KVM_MEM_FORCE_PT_DIRECTORY_PAGES to repeat step 1 ~ step 7, in step
> > 5
> > > the 2M huge pages will be splitted into 4K pages.
> > > 9. Clear the KVM_MEM_FORCE_PT_DIRECTORY_PAGES and
> > > KVM_MEM_FORCE_PT_PAGE_TABLE_PAGES flags for each memory slot.
> > > 10. Then the migration thread calls the log_start ioctl to enable the
> > > dirty logging, and the remaining thing is the same.
> >
> > I'm not sure... I think it would be good if there is a way to have finer granularity
> > control on using huge pages for any process, then KVM can directly leverage
> > that because KVM page tables should always respect the mm configurations on
> > these (so e.g. when huge page split, KVM gets notifications via mmu notifiers).
> > Have you thought of such a more general way?
>
> I did have thought of this, if we split the huge pages into 4K of a process, I'm
> afraid it will not be workable for the huge pages sharing scenario, e.g. DPDK,
> SPDK etc. So, only split the EPT page table and keep the VM process page table
> (e.g. qemu) untouched is the goal.
>
> >
> > (And I just noticed that MADV_NOHUGEPAGE is only a hint to khugepaged
> > and probably won't split any huge page at all after madvise() returns..)
> > To tell the truth I'm still confused on how split of huge pages helped in your
> > case...
>
> I'm sorry if the meaning is not expressed clearly, and thanks for your patience.
>
> > If I read it right the test reduced some execution time from 9s to a
> > few ms after your splittion of huge pages.
>
> Yes
>
> > The thing is I don't see how split of
> > huge pages could solve the mmu_lock contention with the huge VM, because
> > IMO even if we split the huge pages into smaller ones, those pages should still
> > be write-protected and need merely the same number of page faults to resolve
> > when accessed/written? And I thought that should only be fixed with
> > solutions like what Ben has proposed with the MMU rework. Could you show
> > me what I've missed?
>
> Let me try to describe the reason of mmu_lock contention more clearly and the
> effort we tried to do...
> The huge VM only has EPT >= level 2 sptes, and level 1 sptes don't
> exist at the beginning. Write protect all the huge pages will trigger EPT
> violation to create level 1 sptes for all the vCPUs which want to write the
> content of the memory. Different vCPU write the different areas of
> the memory, but they need the same kvm->mmu_lock to create the level 1
> sptes, this situation will be worse if the number of vCPU and the memory of
> VM is large(in our case 60U512G), meanwhile the VM has
> memory-write-intensive work to do. In order to reduce the mmu_lock
> contention, we try to: write protect VM memory gradually in small chunks,
> such as 1G or 2M. Using a vCPU temporary creately by migration thread to
> split 1G to 2M as the first step, and to split 2M to 4K as the second step
> (this is a little hacking...and I do not know any side effect will be triggered
> indeed).
> Comparing to write protect all VM memory in one go, the write
> protected range is limited in this way and only the vCPUs write this limited
> range will be involved to take the mmu_lock. The contention will be reduced
> since the memory range is small and the number of vCPU involved is small
> too.
>
> Of course, it will take some extra time to split all the huge pages into 4K
> page before the real migration started, about 60s for 512G in my experiment.
>
> During the memory iterative copy phase, PML will do the dirty logging work
> (not write protected case for 4K), or IIRC using fast_page_fault to mark page
> dirty if PML is not supported, which case the mmu_lock does not needed.
>
> Regards,
> Jay Zhou
(Ah I top-posted I'm sorry. Re-sending at the bottom.)
FWIW, we currently do this eager splitting at Google for live
migration. When the log-dirty-memory flag is set on a memslot we
eagerly split all pages in the slot down to 4k granularity.
As Jay said, this does not cause crippling lock contention because the
vCPU page faults generated by write protection / splitting can be
resolved in the fast page fault path without acquiring the MMU lock.
I believe +Junaid Shahid tried to upstream this approach at some point
in the past, but the patch set didn't make it in. (This was before my
time, so I'm hoping he has a link.)
I haven't done the analysis to know if eager splitting is more or less
efficient with parallel slow-path page faults, but it's definitely
faster under the MMU lock.
^ permalink raw reply
* Re: [PATCH 16/19] target/arm: Remove ARM_FEATURE_VFP*
From: Peter Maydell @ 2020-02-20 17:33 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
In-Reply-To: <20200214181547.21408-17-richard.henderson@linaro.org>
On Fri, 14 Feb 2020 at 18:16, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We have converted all tests against these features
> to ISAR tests.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply
* Re: [PATCH] describe: output tag's ref instead of embedded name
From: Junio C Hamano @ 2020-02-20 17:34 UTC (permalink / raw)
To: Jeff King; +Cc: Matheus Tavares, git, rhi
In-Reply-To: <20200220112539.GB1252160@coredump.intra.peff.net>
Jeff King <peff@peff.net> writes:
> On Wed, Feb 19, 2020 at 03:14:14AM -0800, Junio C Hamano wrote:
>
>> To continue playing devil's advocate and to step back a bit,
>>
>> - The "git describe" command finds that the given commit is
>> "closest" to that tag Bob called "v1.0".
>>
>> - But if it outputs "v1.0" like the current code does, it cannot be
>> fed back to get_oid() to name the right object, if the given commit
>> is "at" the tag (i.e. there is no "-$number-g$objectname" suffix),
>> which is a problem. We want "git describe" to give an output
>> usable with get_oid() and the name must refer to the correct
>> object (i.e. the one given to "git describe" as an input).
>>
>> There are multiple approaches to make it possible to feed the output
>> back to get_oid() to obtain correct result:
>> [...]
>
> Thanks for clearly laying out your thinking. All of what you wrote makes
> sense to me and I'd be OK with any of the options you described.
>
> The "-g$objectname" one is kind of clever, and definitely not something
> I had thought of. We already have "--long", and of course we'd show the
> long version for any name that isn't an exact match anyway. So as an
> added bonus, it seems unlikely to surprise anybody who is expecting the
> current "show the tag, not the refname" output (though again, this is
> rare enough that I think people simply expect them to be the same ;) ).
There is one thing you may have brought up in the discussion but I
did not touch. Using v1.0-0-g0123456, based on tagname "v1.0" Bob
gave to it would still describe the right object, but if the user
forced "--no-long", it becomes unclear what we should do.
Saying "v1.0" like the current code does would re-introduce the
"output cannot be fed back to get_oid()" when refs/tags/v1.0 does
not exist, and when it does, get_oid() would yield a wrong object.
Another thing that is not satisfying is what should happen in "all"
mode. We add "tags/" prefix so in the case we've been discussing,
the output would be "tags/v1.0-0-g0123456", but the whole reason why
we add the prefix is to say that the early part of the name, "v1.0",
is a tag, and it would be natural to associate it with refs/tags/v1.0
that is *not* Bob's tag.
Having said all that, here is what I have at this moment.
-- >8 --
Subject: describe: force long format for a name based on a mislocated tag
An annotated tag has two names: where it sits in the refs/tags
hierarchy and the tagname recorded in the "tag" field in the object
itself. They usually should match.
Since 212945d4 ("Teach git-describe to verify annotated tag names
before output", 2008-02-28), a commit described using an annotated
tag bases its name on the tagname from the object. While this was a
deliberate design decision to make it easier to converse about tags
with others, even if the tags happen to be fetched to a different
name than it was given by its creator, it had one downside.
The output from "git describe", at least in the modern Git, should
be usable as an object name to name the exact commit given to the
"git describe" command. Using the tagname, when two names differ,
breaks this property, when describing a commit that is directly
pointed at by such a tag. An annotated tag Bob made as "v1.0" may
sit at "refs/tags/v1.0-bob" in the ref hierarchy, and output from
"git describe v1.0-bob^0" would say "v1.0", but there may not be
any tag at "refs/tags/v1.0" locally or there may be another tag that
points at a different object.
Note that this won't be a problem if a commit being described is not
directly pointed at by such a mislocated tag. In the example in the
previous paragraph, "git describe v1.0-bob~1" would result in "v1.0"
(i.e. the tagname taken from the tag object) followed by "-1-gXXXXX"
where XXXXX is the abbreviated object name, and a string that ends
with "-g" followed by a hexadecimal string is an object name for the
object whose name begins with hexadecimal string (as long as it is
unique), so it does not matter if the leading part is "v1.0" or
"v1.0-bob".
Show the name in the long format, i.e. with "-0-gXXXXX" suffix, when
the name we give is based on a mislocated annotated tag to ensure
that the output can be used as the object name for the object
originally given to the command to fix the issue.
While at it, remove an overly cautious dead code to protect against
an annotated tag object without the tagname. Such a tag is filtered
out much earlier in the codeflow, and will not reach this part of
the code.
Helped-by: Matheus Tavares <matheus.bernardino@usp.br>
Helped-by: Jeff King <peff@peff.net>
Signed-off-by: Junio C Hamano <gitster@pobox.com>
---
builtin/describe.c | 13 ++++++++-----
t/t6120-describe.sh | 10 +++++++++-
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/builtin/describe.c b/builtin/describe.c
index b6df81d8d0..5e8484f654 100644
--- a/builtin/describe.c
+++ b/builtin/describe.c
@@ -54,6 +54,7 @@ struct commit_name {
struct tag *tag;
unsigned prio:2; /* annotated tag = 2, tag = 1, head = 0 */
unsigned name_checked:1;
+ unsigned misnamed:1;
struct object_id oid;
char *path;
};
@@ -132,6 +133,7 @@ static void add_to_known_names(const char *path,
e->tag = tag;
e->prio = prio;
e->name_checked = 0;
+ e->misnamed = 0;
oidcpy(&e->oid, oid);
free(e->path);
e->path = xstrdup(path);
@@ -275,10 +277,11 @@ static void append_name(struct commit_name *n, struct strbuf *dst)
die(_("annotated tag %s not available"), n->path);
}
if (n->tag && !n->name_checked) {
- if (!n->tag->tag)
- die(_("annotated tag %s has no embedded name"), n->path);
- if (strcmp(n->tag->tag, all ? n->path + 5 : n->path))
- warning(_("tag '%s' is really '%s' here"), n->tag->tag, n->path);
+ if (strcmp(n->tag->tag, all ? n->path + 5 : n->path)) {
+ warning(_("tag '%s' is externally known as '%s'"),
+ n->path, n->tag->tag);
+ n->misnamed = 1;
+ }
n->name_checked = 1;
}
@@ -314,7 +317,7 @@ static void describe_commit(struct object_id *oid, struct strbuf *dst)
* Exact match to an existing ref.
*/
append_name(n, dst);
- if (longformat)
+ if (n->misnamed || longformat)
append_suffix(0, n->tag ? get_tagged_oid(n->tag) : oid, dst);
if (suffix)
strbuf_addstr(dst, suffix);
diff --git a/t/t6120-describe.sh b/t/t6120-describe.sh
index 45047d0a72..16a261c45d 100755
--- a/t/t6120-describe.sh
+++ b/t/t6120-describe.sh
@@ -130,12 +130,20 @@ test_expect_success 'rename tag A to Q locally' '
mv .git/refs/tags/A .git/refs/tags/Q
'
cat - >err.expect <<EOF
-warning: tag 'A' is really 'Q' here
+warning: tag 'Q' is externally known as 'A'
EOF
check_describe A-* HEAD
test_expect_success 'warning was displayed for Q' '
test_i18ncmp err.expect err.actual
'
+test_expect_success 'misnamed annotated tag forces long output' '
+ description=$(git describe --no-long Q^0) &&
+ expr "$description" : "A-0-g[0-9a-f]*$" &&
+ git rev-parse --verify "$description" >actual &&
+ git rev-parse --verify Q^0 >expect &&
+ test_cmp expect actual
+'
+
test_expect_success 'rename tag Q back to A' '
mv .git/refs/tags/Q .git/refs/tags/A
'
^ permalink raw reply related
* [LTP] [PATCH V2 06/10] syscalls/fsmount: Improve fsmount01 test
From: Petr Vorel @ 2020-02-20 17:34 UTC (permalink / raw)
To: ltp
In-Reply-To: <9706f359006ea409d2f85c111d3e001ca6f6d128.1582104018.git.viresh.kumar@linaro.org>
Hi,
> +static struct tcase {
> + char *name;
> + unsigned int flags;
> + unsigned int mount_attrs;
> +} tcases[] = {
> + {"Flag 0, attr RDONLY", 0, MOUNT_ATTR_RDONLY},
> + {"Flag 0, attr NOSUID", 0, MOUNT_ATTR_NOSUID},
> + {"Flag 0, attr NODEV", 0, MOUNT_ATTR_NODEV},
> + {"Flag 0, attr NOEXEC", 0, MOUNT_ATTR_NOEXEC},
> + {"Flag 0, attr RELATIME", 0, MOUNT_ATTR_RELATIME},
> + {"Flag 0, attr NOATIME", 0, MOUNT_ATTR_NOATIME},
> + {"Flag 0, attr STRICTATIME", 0, MOUNT_ATTR_STRICTATIME},
> + {"Flag 0, attr NODIRATIME", 0, MOUNT_ATTR_NODIRATIME},
> + {"Flag CLOEXEC, attr RDONLY", FSMOUNT_CLOEXEC, MOUNT_ATTR_RDONLY},
> + {"Flag CLOEXEC, attr NOSUID", FSMOUNT_CLOEXEC, MOUNT_ATTR_NOSUID},
> + {"Flag CLOEXEC, attr NODEV", FSMOUNT_CLOEXEC, MOUNT_ATTR_NODEV},
> + {"Flag CLOEXEC, attr NOEXEC", FSMOUNT_CLOEXEC, MOUNT_ATTR_NOEXEC},
> + {"Flag CLOEXEC, attr RELATIME", FSMOUNT_CLOEXEC, MOUNT_ATTR_RELATIME},
> + {"Flag CLOEXEC, attr NOATIME", FSMOUNT_CLOEXEC, MOUNT_ATTR_NOATIME},
> + {"Flag CLOEXEC, attr STRICTATIME", FSMOUNT_CLOEXEC, MOUNT_ATTR_STRICTATIME},
> + {"Flag CLOEXEC, attr NODIRATIME", FSMOUNT_CLOEXEC, MOUNT_ATTR_NODIRATIME},
> +};
I'd use desc field
#define DESC(x, y) .flags = x, .mount_attrs = y, .desc = #x ", " #y
+static struct tcase {
+ char *desc;
+ unsigned int flags;
+ unsigned int mount_attrs;
+} tcases[] = {
+ {DESC(0, MOUNT_ATTR_RDONLY)},
+ {DESC(0, MOUNT_ATTR_NOSUID)},
(avoid copy paste).
> +static void setup(void)
> {
> - if (is_mounted)
> - SAFE_UMOUNT(MNTPOINT);
> + fsopen_supported_by_kernel();
again, just .setup = fsopen_supported_by_kernel;
> }
> -static void test_fsmount(void)
> +static void run(unsigned int n)
> {
> + struct tcase *tc = &tcases[n];
> + int sfd, mfd;
> +
> TEST(fsopen(tst_device->fs_type, FSOPEN_CLOEXEC));
> - if (TST_RET < 0)
> - tst_brk(TBROK | TTERRNO, "fsopen() on %s failed", tst_device->fs_type);
> + if (TST_RET == -1) {
> + tst_brk(TBROK | TTERRNO, "fsopen() on %s failed",
> + tst_device->fs_type);
Again, tst_brk(TBROK) shouldn't be on tcnt = ARRAY_SIZE(tcases),
it skips all following tests after failure (sometimes needed but IMHO not here).
> + }
> sfd = TST_RET;
> - tst_res(TPASS, "fsopen() on %s", tst_device->fs_type);
> TEST(fsconfig(sfd, FSCONFIG_SET_STRING, "source", tst_device->dev, 0));
> - if (TST_RET < 0)
> + if (TST_RET < 0) {
> + SAFE_CLOSE(sfd);
> tst_brk(TBROK | TTERRNO,
> "fsconfig() failed to set source to %s", tst_device->dev);
> - tst_res(TPASS, "fsconfig() set source to %s", tst_device->dev);
> -
> + }
> TEST(fsconfig(sfd, FSCONFIG_CMD_CREATE, NULL, NULL, 0));
> - if (TST_RET < 0)
> + if (TST_RET < 0) {
> + SAFE_CLOSE(sfd);
> tst_brk(TBROK | TTERRNO, "fsconfig() created superblock");
As you added more runs of the test (changed .test_all to .test && run =
ARRAY_SIZE(tcases)), you need to change all tst_brk() to tst_res() + return.
I also merged tst_brk(TBROK), I guess TFAIL would be better.
Other than that it looks ok.
I also wonder if it'd be worth to implement in fsmount.h some macros to reduce
code duplicity. e.g. one of similar patterns (just flag is different):
TEST(fsopen(tst_device->fs_type, FLAG));
fd = TST_RET;
if (fd == -1)
tst_brk(TBROK | TERRNO, "fsopen() failed");
But that's not important.
Kind regards,
Petr
^ permalink raw reply
* [meta-python2][PATCH 1/1] python-lxml: fix installation
From: Joe Slater @ 2020-02-20 17:34 UTC (permalink / raw)
To: openembedded-devel
Inherit setuptools before adding to variables defined in it.
Signed-off-by: Joe Slater <joe.slater@windriver.com>
---
recipes-devtools/python/python-lxml_4.4.2.bb | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/recipes-devtools/python/python-lxml_4.4.2.bb b/recipes-devtools/python/python-lxml_4.4.2.bb
index 911ba58..0f9cdf7 100644
--- a/recipes-devtools/python/python-lxml_4.4.2.bb
+++ b/recipes-devtools/python/python-lxml_4.4.2.bb
@@ -21,6 +21,11 @@ SRC_URI[sha256sum] = "eff69ddbf3ad86375c344339371168640951c302450c5d3e9936e98d64
DEPENDS += "libxml2 libxslt"
+
+inherit setuptools
+
+# add to the defaults which are set in the setuptools bbclass
+#
DISTUTILS_BUILD_ARGS += " \
--with-xslt-config='pkg-config libxslt' \
--with-xml2-config='pkg-config libxml-2.0' \
@@ -31,7 +36,7 @@ DISTUTILS_INSTALL_ARGS += " \
--with-xml2-config='pkg-config libxml-2.0' \
"
-inherit pypi setuptools
+inherit pypi
# {standard input}: Assembler messages:
# {standard input}:1488805: Error: branch out of range
--
2.7.4
^ permalink raw reply related
* Re: S variable for svn fetcher Was: State of OE world - 2020-02-18
From: Martin Jansa @ 2020-02-20 17:34 UTC (permalink / raw)
To: Adrian Bunk; +Cc: openembeded-devel
In-Reply-To: <20200220162312.cqh5bwvdwxjp362g@jama>
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On Thu, Feb 20, 2020 at 05:23:12PM +0100, Martin Jansa wrote:
> On Thu, Feb 20, 2020 at 06:11:59PM +0200, Adrian Bunk wrote:
> > On Thu, Feb 20, 2020 at 04:37:58PM +0100, Martin Jansa wrote:
> > > On Thu, Feb 20, 2020 at 05:16:20PM +0200, Adrian Bunk wrote:
> > > > On Thu, Feb 20, 2020 at 03:48:48PM +0100, Martin Jansa wrote:
> > > > >...
> > > > > Any idea why these aren't shown in our build?
> > > > >...
> > > >
> > > > What is your mirror configuration?
> > > >
> > > > Default configuration downloads the tarball from [1].
> > >
> > > Maybe I'm missing your point, but these aren't fetch issues.
> > >...
> >
> > MIRRORS = "" (and deleting the downloaded tar) is what I needed for
> > getting a build failure.
>
> OK, I see now, sorry.
>
> That explains why it's not shown in khem's builds and might be broken
> well before thud already, the tarball created here today:
>
> $ tar xvf ../downloads/gpio_svn.openmoko.org_.trunk.src.target_4949_.tar.gz
> gpio/
> gpio/trunk/
> gpio/trunk/doc/
> gpio/trunk/doc/hardware/
> gpio/trunk/doc/hardware/GTA01Bv3/
> gpio/trunk/doc/hardware/GTA01Bv3/gpio.txt
> gpio/trunk/doc/hardware/GTA01Bv3/pmu-voltage.txt
> ...
>
> while the corresponding tarball on mirror:
> http://sources.openembedded.org/gpio_svn.openmoko.org_.trunk.src.target_4949_.tar.gz
> $ tar xvf gpio_svn.openmoko.org_.trunk.src.target_4949_.tar.gz
> gpio/
> gpio/gpio-s3c6410.c
> gpio/Makefile
> gpio/gpio.c
> gpio/gpio-glamo.c
> gpio/README
>
> Will check when it got broken before thud.
It's still reproducible in pyro, so probably not caused by changes in OE.
There is one more recipe using svn in meta-multimedia which works fine:
meta-multimedia/recipes-dvb/oscam/oscam_svn.bb:SRC_URI = "svn://www.streamboard.tv/svn/oscam;module=trunk;protocol=http \
The rest are all from svn.openmoko.org:
meta-oe/recipes-support/samsung-soc-utils/s3c24xx-gpio_svn.bb:SRC_URI = "svn://svn.openmoko.org/trunk/src/target;module=gpio;protocol=http"
meta-oe/recipes-support/samsung-soc-utils/s3c64xx-gpio_svn.bb:SRC_URI = "svn://svn.openmoko.org/trunk/src/target;module=gpio;protocol=http"
meta-oe/recipes-support/samsung-soc-utils/sjf2410-linux-native_svn.bb:SRC_URI = "svn://svn.openmoko.org/trunk/src/host/;module=sjf2410-linux;protocol=http \
meta-oe/recipes-support/usbpath/usbpath_svn.bb:SRC_URI = "svn://svn.openmoko.org/trunk/src/host;module=usbpath;protocol=http \
meta-oe/recipes-support/wmiconfig/wmiconfig_svn.bb:SRC_URI = "svn://svn.openmoko.org/trunk/src/target;module=AR6kSDK.build_sw.18;protocol=http \
And now this leads to do_fetch running:
svn --non-interactive --trust-server-cert co --no-auth-cache --ignore-externals -r 4949 http://svn.openmoko.org/trunk/src/target/gpio@4949 gpio
as before, but now it redirects to github:
Redirecting to URL 'https://github.com/openmoko/openmoko-svn':
A gpio/branches
A gpio/branches/oe
A gpio/branches/oe/pre-20070305
A gpio/branches/oe/pre-20070305/README
A gpio/branches/oe/pre-20070305/classes
A gpio/branches/oe/pre-20070305/classes/autotools.bbclass
A gpio/branches/oe/pre-20070305/classes/base.bbclass
A gpio/branches/oe/pre-20070305/classes/openmoko-base.bbclass
A gpio/branches/oe/pre-20070305/classes/openmoko-panel-plugin.bbclass
..
and the svn bridge to github probably doesn't work exactly the same as the
native svn repo used to work, but I don't see it explicitly mentioned in:
https://help.github.com/en/github/importing-your-projects-to-github/support-for-subversion-clients
So to resolve this quickly I'm going to send SRC_URI updates for
these recipes to just use git fetcher from:
https://github.com/openmoko/openmoko-svn
directly. I don't think anyone is using these nowadays, so it's
also fine with me to just delete them all, which I'll do in
separate follow-up commit in case someone tries to resurrect them
later in own layer.
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^ permalink raw reply
* Re: [PATCH AUTOSEL 5.5 389/542] clocksource/drivers/hyper-v: Reserve PAGE_SIZE space for tsc page
From: Sasha Levin @ 2020-02-20 17:34 UTC (permalink / raw)
To: Michael Kelley
Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, Boqun Feng,
linux-hyperv@vger.kernel.org, Daniel Lezcano
In-Reply-To: <MW2PR2101MB10526693E43DF07E03D5EB0FD7150@MW2PR2101MB1052.namprd21.prod.outlook.com>
On Fri, Feb 14, 2020 at 04:11:03PM +0000, Michael Kelley wrote:
>This patch does not need to be backported to any stable releases. It is prep work for guests on Hyper-V ARM64 when the guest page size is 16K or 64K, and that functionality isn't upstream yet.
Now dropped, thank you.
--
Thanks,
Sasha
^ permalink raw reply
* Re: [PATCH 15/19] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP
From: Peter Maydell @ 2020-02-20 17:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
In-Reply-To: <20200214181547.21408-16-richard.henderson@linaro.org>
On Fri, 14 Feb 2020 at 18:16, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use isar feature tests instead of feature bit tests.
>
> Although none of QEMUs current cpus have VFPv3 without D32,
> replace the large comment explaining why with one line that
> sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions.
> Mirror the test sequence used in the linux kernel.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/elfload.c | 24 +++++++++++++++---------
> 1 file changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index f3080a1635..c52c814a2e 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -468,22 +468,28 @@ static uint32_t get_elf_hwcap(void)
>
> /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
> GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
> - GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP);
> GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
> GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
> GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
> - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
> GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
> - GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4);
> + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
> +
> GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA);
> GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT);
> - /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c.
> - * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of
> - * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated
> - * to our VFP_FP16 feature bit.
> + /*
> + * Note that none of QEMU's cpus have double precision without single
> + * precision support in VFP, so only test the single precision field.
> */
Why not actually mirror the kernel's test sequence, rather
than having a comment about how we deviate from it ?
> - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32);
> - GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
> + GET_FEATURE_ID(aa32_fpsp_v2, ARM_HWCAP_ARM_VFP);
> + if (cpu_isar_feature(aa32_fpsp_v3, cpu)) {
> + hwcaps |= ARM_HWCAP_ARM_VFPv3;
> + if (cpu_isar_feature(aa32_simd_r32, cpu)) {
> + hwcaps |= ARM_HWCAP_ARM_VFPD32;
> + } else {
> + hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
> + }
> + }
> + GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
>
> return hwcaps;
> }
thanks
-- PMM
^ permalink raw reply
* Re: [PATCH RFC 0/2] KVM: nVMX: fix apicv disablement for L1
From: Sean Christopherson @ 2020-02-20 17:33 UTC (permalink / raw)
To: Vitaly Kuznetsov
Cc: Jim Mattson, kvm, Paolo Bonzini, Wanpeng Li, linux-kernel
In-Reply-To: <20200220172205.197767-1-vkuznets@redhat.com>
On Thu, Feb 20, 2020 at 06:22:03PM +0100, Vitaly Kuznetsov wrote:
> It was found that fine-grained VMX feature enablement in QEMU is broken
> when combined with SynIC:
>
> qemu-system-x86_64 -machine q35,accel=kvm -cpu host,hv_vpindex,hv_synic -smp 2 -m 16384 -vnc :0
> qemu-system-x86_64: error: failed to set MSR 0x48d to 0xff00000016
> qemu-system-x86_64: <...>: kvm_buf_set_msrs: Assertion `ret == cpu->kvm_msr_buf->nmsrs' failed.
> Aborted
>
> QEMU thread: https://lists.gnu.org/archive/html/qemu-devel/2020-02/msg04838.html
>
> Turns out, this is a KVM issue: when SynIC is enabled, PIN_BASED_POSTED_INTR
> gets filtered out from VMX MSRs for all newly created (but not existent!)
> vCPUS. Patch1 addresses this. Also, apicv disablement for L1 doesn't seem
> to disable it for L2 (at least on CPU0) so unless there's a good reason
> to not allow this we need to make it work. PATCH2, suggested by Paolo,
> is supposed to do the job.
>
> RFC: I looked at the code and ran some tests and nothing suspicious popped
> out, however, I'm still not convinced this is a good idea to have apicv
> enabled for L2 when it's disabled for L1...
Eh, if it works... IMO, enabling apicv for both L1 and L2 is far more
mindbending.
> Also, we may prefer to merge or re-order these two patches.
It does seem like patch 2 should be applied first.
> Vitaly Kuznetsov (2):
> KVM: nVMX: clear PIN_BASED_POSTED_INTR from nested pinbased_ctls only
> when apicv is globally disabled
> KVM: nVMX: handle nested posted interrupts when apicv is disabled for
> L1
>
> arch/x86/include/asm/kvm_host.h | 2 +-
> arch/x86/kvm/lapic.c | 5 +----
> arch/x86/kvm/svm.c | 7 ++++++-
> arch/x86/kvm/vmx/capabilities.h | 1 +
> arch/x86/kvm/vmx/nested.c | 5 ++---
> arch/x86/kvm/vmx/nested.h | 3 +--
> arch/x86/kvm/vmx/vmx.c | 23 +++++++++++++----------
> 7 files changed, 25 insertions(+), 21 deletions(-)
>
> --
> 2.24.1
>
^ permalink raw reply
* Re: [PATCH 0/3] KVM: arm64: Ask the compiler to __always_inline functions used by KVM at HYP
From: James Morse @ 2020-02-20 17:33 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Suzuki K Poulose, Marc Zyngier, linux-arm-kernel, Sami Tolvanen,
Catalin Marinas, Will Deacon, kvmarm, Julien Thierry
In-Reply-To: <CAKv+Gu-tPOWyxjsKrL-auC=ZxeNJPgAPyQ2rBd9S8sgMbb=r_w@mail.gmail.com>
Hi Ard,
On 20/02/2020 17:04, Ard Biesheuvel wrote:
> On Thu, 20 Feb 2020 at 17:58, James Morse <james.morse@arm.com> wrote:
>> It turns out KVM relies on the inline hint being honoured by the compiler
>> in quite a few more places than expected. Something about the Shadow Call
>> Stack support[0] causes the compiler to avoid inline-ing and to place
>> these functions outside the __hyp_text. This ruins KVM's day.
>>
>> Add the simon-says __always_inline annotation to all the static
>> inlines that KVM calls from HYP code.
> This isn't quite as yuck as I expected, fortunately, but it does beg
> the question whether we shouldn't simply map the entire kernel at EL2
> instead?
If the kernel is big enough to need internal veneers (the 128M range?), these would
certainly go horribly wrong because its running somewhere other than the relocation-time
address. We would need a way of telling the linker to keep the bits of KVM close together...
Thanks,
James
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] ASoC: tas2562: Add support for digital volume control
From: Dan Murphy @ 2020-02-20 17:27 UTC (permalink / raw)
To: lgirdwood, broonie, perex, tiwai; +Cc: alsa-devel, linux-kernel, Dan Murphy
Add support for digital volume control. There is no dedicated register
for volume control but instead there are 4. The values of the registers
are determined with exponential floating point math.
So a table was created with register values for 2dB step increments
from -110dB to 0dB.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
sound/soc/codecs/tas2562.c | 94 ++++++++++++++++++++++++++++++++++++++
sound/soc/codecs/tas2562.h | 6 ++-
2 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/tas2562.c b/sound/soc/codecs/tas2562.c
index b2682c2360b6..e577aa6f304a 100644
--- a/sound/soc/codecs/tas2562.c
+++ b/sound/soc/codecs/tas2562.c
@@ -26,6 +26,24 @@
#define TAS2562_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FORMAT_S32_LE)
+/* DVC equation involves floating point math
+ * round(10^(volume in dB/20)*2^30)
+ * so create a lookup table for 2dB step
+ */
+static const unsigned int float_vol_db_lookup[] = {
+0x00000d43, 0x000010b2, 0x00001505, 0x00001a67, 0x00002151,
+0x000029f1, 0x000034cd, 0x00004279, 0x000053af, 0x0000695b,
+0x0000695b, 0x0000a6fa, 0x0000d236, 0x000108a4, 0x00014d2a,
+0x0001a36e, 0x00021008, 0x000298c0, 0x000344df, 0x00041d8f,
+0x00052e5a, 0x000685c8, 0x00083621, 0x000a566d, 0x000d03a7,
+0x0010624d, 0x0014a050, 0x0019f786, 0x0020b0bc, 0x0029279d,
+0x0033cf8d, 0x004139d3, 0x00521d50, 0x00676044, 0x0082248a,
+0x00a3d70a, 0x00ce4328, 0x0103ab3d, 0x0146e75d, 0x019b8c27,
+0x02061b89, 0x028c423f, 0x03352529, 0x0409c2b0, 0x05156d68,
+0x080e9f96, 0x0a24b062, 0x0cc509ab, 0x10137987, 0x143d1362,
+0x197a967f, 0x2013739e, 0x28619ae9, 0x32d64617, 0x40000000
+};
+
struct tas2562_data {
struct snd_soc_component *component;
struct gpio_desc *sdz_gpio;
@@ -34,6 +52,7 @@ struct tas2562_data {
struct i2c_client *client;
int v_sense_slot;
int i_sense_slot;
+ int volume_lvl;
};
static int tas2562_set_bias_level(struct snd_soc_component *component,
@@ -334,6 +353,22 @@ static int tas2562_codec_probe(struct snd_soc_component *component)
if (ret < 0)
return ret;
+ /* Set the Digital volume to -110dB */
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG4, 0x00);
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG3, 0x00);
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG2, 0x0d);
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG1, 0x43);
+ if (ret)
+ return ret;
+
+ tas2562->volume_lvl = 0;
+
return 0;
}
@@ -414,6 +449,50 @@ static int tas2562_dac_event(struct snd_soc_dapm_widget *w,
return 0;
}
+static int tas2562_volume_control_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+ struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
+
+ ucontrol->value.integer.value[0] = tas2562->volume_lvl;
+ return 0;
+}
+
+static int tas2562_volume_control_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+ struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
+ int ret;
+ u32 reg_val;
+
+ reg_val = float_vol_db_lookup[ucontrol->value.integer.value[0]/2];
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG4,
+ (reg_val & 0xff));
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG3,
+ ((reg_val >> 8) & 0xff));
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG2,
+ ((reg_val >> 16) & 0xff));
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG1,
+ ((reg_val >> 24) & 0xff));
+ if (ret)
+ return ret;
+
+ tas2562->volume_lvl = ucontrol->value.integer.value[0];
+
+ return ret;
+}
+
+/* Digital Volume Control. From 0 dB to -110 dB in 1 dB steps */
+static const DECLARE_TLV_DB_SCALE(dvc_tlv, -11000, 100, 0);
+
static DECLARE_TLV_DB_SCALE(tas2562_dac_tlv, 850, 50, 0);
static const struct snd_kcontrol_new isense_switch =
@@ -427,6 +506,17 @@ static const struct snd_kcontrol_new vsense_switch =
static const struct snd_kcontrol_new tas2562_snd_controls[] = {
SOC_SINGLE_TLV("Amp Gain Volume", TAS2562_PB_CFG1, 0, 0x1c, 0,
tas2562_dac_tlv),
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Digital Volume Control",
+ .index = 0,
+ .tlv.p = dvc_tlv,
+ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = snd_soc_info_volsw,
+ .get = tas2562_volume_control_get,
+ .put = tas2562_volume_control_put,
+ .private_value = SOC_SINGLE_VALUE(TAS2562_DVC_CFG1, 0, 110, 0, 0) ,
+ },
};
static const struct snd_soc_dapm_widget tas2562_dapm_widgets[] = {
@@ -517,6 +607,10 @@ static const struct reg_default tas2562_reg_defaults[] = {
{ TAS2562_PB_CFG1, 0x20 },
{ TAS2562_TDM_CFG0, 0x09 },
{ TAS2562_TDM_CFG1, 0x02 },
+ { TAS2562_DVC_CFG1, 0x40 },
+ { TAS2562_DVC_CFG2, 0x40 },
+ { TAS2562_DVC_CFG3, 0x00 },
+ { TAS2562_DVC_CFG4, 0x00 },
};
static const struct regmap_config tas2562_regmap_config = {
diff --git a/sound/soc/codecs/tas2562.h b/sound/soc/codecs/tas2562.h
index 6f55ebcf19ea..28e75fc431d0 100644
--- a/sound/soc/codecs/tas2562.h
+++ b/sound/soc/codecs/tas2562.h
@@ -35,8 +35,10 @@
#define TAS2562_REV_ID TAS2562_REG(0, 0x7d)
/* Page 2 */
-#define TAS2562_DVC_CFG1 TAS2562_REG(2, 0x01)
-#define TAS2562_DVC_CFG2 TAS2562_REG(2, 0x02)
+#define TAS2562_DVC_CFG1 TAS2562_REG(2, 0x0c)
+#define TAS2562_DVC_CFG2 TAS2562_REG(2, 0x0d)
+#define TAS2562_DVC_CFG3 TAS2562_REG(2, 0x0e)
+#define TAS2562_DVC_CFG4 TAS2562_REG(2, 0x0f)
#define TAS2562_RESET BIT(0)
--
2.25.0
^ permalink raw reply related
* Re: [PATCH 0/3] KVM: arm64: Ask the compiler to __always_inline functions used by KVM at HYP
From: James Morse @ 2020-02-20 17:33 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Marc Zyngier, linux-arm-kernel, Sami Tolvanen, Catalin Marinas,
Will Deacon, kvmarm
In-Reply-To: <CAKv+Gu-tPOWyxjsKrL-auC=ZxeNJPgAPyQ2rBd9S8sgMbb=r_w@mail.gmail.com>
Hi Ard,
On 20/02/2020 17:04, Ard Biesheuvel wrote:
> On Thu, 20 Feb 2020 at 17:58, James Morse <james.morse@arm.com> wrote:
>> It turns out KVM relies on the inline hint being honoured by the compiler
>> in quite a few more places than expected. Something about the Shadow Call
>> Stack support[0] causes the compiler to avoid inline-ing and to place
>> these functions outside the __hyp_text. This ruins KVM's day.
>>
>> Add the simon-says __always_inline annotation to all the static
>> inlines that KVM calls from HYP code.
> This isn't quite as yuck as I expected, fortunately, but it does beg
> the question whether we shouldn't simply map the entire kernel at EL2
> instead?
If the kernel is big enough to need internal veneers (the 128M range?), these would
certainly go horribly wrong because its running somewhere other than the relocation-time
address. We would need a way of telling the linker to keep the bits of KVM close together...
Thanks,
James
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply
* Re: [PATCH 1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u
From: Philippe Mathieu-Daudé @ 2020-02-20 17:31 UTC (permalink / raw)
To: Bin Meng, Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
In-Reply-To: <1582209758-2996-1-git-send-email-bmeng.cn@gmail.com>
Hi Bin,
On 2/20/20 3:42 PM, Bin Meng wrote:
> Although the real world SiFive HiFive Unleashed board is a 64-bit
> hardware configuration, with QEMU it is possible to test 32-bit
> configuration with the same hardware features.
>
> This updates the roms Makefile to add the build rules for creating
> the 32-bit OpenSBI firmware image for sifive_u machine. A pre-built
> OpenSBI image (built from commit 3e7d666) has been added as the
> default bios for 32-bit sifive_u machine.
With QEMU:
fatal: ambiguous argument '3e7d666': unknown revision or path not in the
working tree.
This looks like an OpenSBI commit but QEMU only include up to v0.5.
Can you build v0.5? Else can you update the submodule?
Also, can you add a CI job to build this, so we have reproducible builds
(see QEMU commit 71920809ceabed as example)?
Thanks,
Phil.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Makefile | 2 +-
> pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 0 -> 49472 bytes
> roms/Makefile | 7 +++++++
> 3 files changed, 8 insertions(+), 1 deletion(-)
> create mode 100644 pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
>
> diff --git a/Makefile b/Makefile
> index b5a7377..ee7aa6d 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -804,7 +804,7 @@ u-boot.e500 u-boot-sam460-20100605.bin \
> qemu_vga.ndrv \
> edk2-licenses.txt \
> hppa-firmware.img \
> -opensbi-riscv32-virt-fw_jump.bin \
> +opensbi-riscv32-sifive_u-fw_jump.bin opensbi-riscv32-virt-fw_jump.bin \
> opensbi-riscv64-sifive_u-fw_jump.bin opensbi-riscv64-virt-fw_jump.bin
>
>
> diff --git a/pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
> new file mode 100644
> index 0000000000000000000000000000000000000000..93e2556baa261bfd796cdc484b345bf958c8afea
> GIT binary patch
> literal 49472
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> z1L;sFpjSW+eDT7+pq15a#lB0dy2O!A#xjcX<AK9dsF&<R-6-<3w);a@j{#*+I{m!!
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> ya#H%;@0n$pO+cR{C-u9VQ&Z*;ko&Cz+(Cw-iw&)SA5k;=`4{eFMQ~U9-v0tg0|1@?
>
> literal 0
> HcmV?d00001
>
> diff --git a/roms/Makefile b/roms/Makefile
> index 28e1e55..f9acf39 100644
> --- a/roms/Makefile
> +++ b/roms/Makefile
> @@ -66,6 +66,7 @@ default help:
> @echo " efi -- update UEFI (edk2) platform firmware"
> @echo " opensbi32-virt -- update OpenSBI for 32-bit virt machine"
> @echo " opensbi64-virt -- update OpenSBI for 64-bit virt machine"
> + @echo " opensbi32-sifive_u -- update OpenSBI for 32-bit sifive_u machine"
> @echo " opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u machine"
> @echo " bios-microvm -- update bios-microvm.bin (qboot)"
> @echo " clean -- delete the files generated by the previous" \
> @@ -181,6 +182,12 @@ opensbi64-virt:
> PLATFORM="qemu/virt"
> cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-virt-fw_jump.bin
>
> +opensbi32-sifive_u:
> + $(MAKE) -C opensbi \
> + CROSS_COMPILE=$(riscv32_cross_prefix) \
> + PLATFORM="sifive/fu540"
> + cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin ../pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
> +
> opensbi64-sifive_u:
> $(MAKE) -C opensbi \
> CROSS_COMPILE=$(riscv64_cross_prefix) \
>
^ permalink raw reply
* Re: crash on connect
From: Glauber Costa @ 2020-02-20 17:33 UTC (permalink / raw)
To: Jens Axboe; +Cc: io-uring, Avi Kivity
In-Reply-To: <ac81e9ef-b828-65e4-f2bb-5485c69fb7b8@kernel.dk>
On Thu, Feb 20, 2020 at 12:28 PM Jens Axboe <axboe@kernel.dk> wrote:
>
> On 2/20/20 9:52 AM, Glauber Costa wrote:
> > On Thu, Feb 20, 2020 at 11:39 AM Jens Axboe <axboe@kernel.dk> wrote:
> >>
> >> On 2/20/20 9:34 AM, Glauber Costa wrote:
> >>> On Thu, Feb 20, 2020 at 11:29 AM Jens Axboe <axboe@kernel.dk> wrote:
> >>>>
> >>>> On 2/20/20 9:17 AM, Jens Axboe wrote:
> >>>>> On 2/20/20 7:19 AM, Glauber Costa wrote:
> >>>>>> Hi there, me again
> >>>>>>
> >>>>>> Kernel is at 043f0b67f2ab8d1af418056bc0cc6f0623d31347
> >>>>>>
> >>>>>> This test is easier to explain: it essentially issues a connect and a
> >>>>>> shutdown right away.
> >>>>>>
> >>>>>> It currently fails due to no fault of io_uring. But every now and then
> >>>>>> it crashes (you may have to run more than once to get it to crash)
> >>>>>>
> >>>>>> Instructions are similar to my last test.
> >>>>>> Except the test to build is now "tests/unit/connect_test"
> >>>>>> Code is at git@github.com:glommer/seastar.git branch io-uring-connect-crash
> >>>>>>
> >>>>>> Run it with ./build/release/tests/unit/connect_test -- -c1
> >>>>>> --reactor-backend=uring
> >>>>>>
> >>>>>> Backtrace attached
> >>>>>
> >>>>> Perfect thanks, I'll take a look!
> >>>>
> >>>> Haven't managed to crash it yet, but every run complains:
> >>>>
> >>>> got to shutdown of 10 with refcnt: 2
> >>>> Refs being all dropped, calling forget for 10
> >>>> terminate called after throwing an instance of 'fmt::v6::format_error'
> >>>> what(): argument index out of range
> >>>> unknown location(0): fatal error: in "unixdomain_server": signal: SIGABRT (application abort requested)
> >>>>
> >>>> Not sure if that's causing it not to fail here.
> >>>
> >>> Ok, that means it "passed". (I was in the process of figuring out
> >>> where I got this wrong when I started seeing the crashes)
> >>
> >> Can you do, in your kernel dir:
> >>
> >> $ gdb vmlinux
> >> [...]
> >> (gdb) l *__io_queue_sqe+0x4a
> >>
> >> and see what it says?
> >
> > 0xffffffff81375ada is in __io_queue_sqe (fs/io_uring.c:4814).
> > 4809 struct io_kiocb *linked_timeout;
> > 4810 struct io_kiocb *nxt = NULL;
> > 4811 int ret;
> > 4812
> > 4813 again:
> > 4814 linked_timeout = io_prep_linked_timeout(req);
> > 4815
> > 4816 ret = io_issue_sqe(req, sqe, &nxt, true);
> > 4817
> > 4818 /*
> >
> > (I am not using timeouts, just async_cancel)
>
> Can't seem to hit it here, went through thousands of iterations...
> I'll keep trying.
>
> If you have time, you can try and enable CONFIG_KASAN=y and see if
> you can hit it with that.
sure thing. will let you know
>
> --
> Jens Axboe
>
^ permalink raw reply
* Re: [Nouveau] [PATCH] nv50_disp_chan_mthd: ensure mthd is not NULL
From: Ilia Mirkin @ 2020-02-20 17:32 UTC (permalink / raw)
To: Frédéric Pierret
Cc: David Airlie, nouveau, LKML, dri-devel, Ben Skeggs
In-Reply-To: <c94ce223-56d5-e31a-2a2c-59defb988b28@qubes-os.org>
Hi Frédéric,
It appears Ben made his own version of this patch (probably based on
the one you added to the kernel bz), and it's already upstream:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v5.6-rc2&id=0e6176c6d286316e9431b4f695940cfac4ffe6c2
Cheers,
-ilia
On Thu, Feb 20, 2020 at 12:19 PM Frédéric Pierret
<frederic.pierret@qubes-os.org> wrote:
>
> Hi,
> Is anything missing here? How can I get this merged?
>
> Best regards,
> Frédéric Pierret
>
> On 2020-02-08 20:43, Frédéric Pierret wrote:
> > Pointer to structure array is assumed not NULL by default. It has
> > the consequence to raise a kernel panic when it's not the case.
> >
> > Basically, running at least a RTX2080TI on Xen makes a bad mmio error
> > which causes having 'mthd' pointer to be NULL in 'channv50.c'. From the
> > code, it's assumed to be not NULL by accessing directly 'mthd->data[0]'
> > which is the reason of the kernel panic. Simply check if the pointer
> > is not NULL before continuing.
> >
> > BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=206299
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Frédéric Pierret (fepitre) <frederic.pierret@qubes-os.org>
> > ---
> > drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
> > index bcf32d92ee5a..50e3539f33d2 100644
> > --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
> > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
> > @@ -74,6 +74,8 @@ nv50_disp_chan_mthd(struct nv50_disp_chan *chan, int debug)
> >
> > if (debug > subdev->debug)
> > return;
> > + if (!mthd)
> > + return;
> >
> > for (i = 0; (list = mthd->data[i].mthd) != NULL; i++) {
> > u32 base = chan->head * mthd->addr;
> >
>
> _______________________________________________
> Nouveau mailing list
> Nouveau@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/nouveau
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: RFC: Split EPT huge pages in advance of dirty logging
From: Ben Gardon @ 2020-02-20 17:32 UTC (permalink / raw)
To: Zhoujian (jay)
Cc: Peter Xu, kvm@vger.kernel.org, qemu-devel@nongnu.org,
pbonzini@redhat.com, dgilbert@redhat.com, quintela@redhat.com,
Liujinsong (Paul), linfeng (M), wangxin (U), Huangweidong (C),
Junaid Shahid
In-Reply-To: <B2D15215269B544CADD246097EACE7474BB03772@DGGEMM528-MBX.china.huawei.com>
FWIW, we currently do this eager splitting at Google for live
migration. When the log-dirty-memory flag is set on a memslot we
eagerly split all pages in the slot down to 4k granularity.
As Jay said, this does not cause crippling lock contention because the
vCPU page faults generated by write protection / splitting can be
resolved in the fast page fault path without acquiring the MMU lock.
I believe +Junaid Shahid tried to upstream this approach at some point
in the past, but the patch set didn't make it in. (This was before my
time, so I'm hoping he has a link.)
I haven't done the analysis to know if eager splitting is more or less
efficient with parallel slow-path page faults, but it's definitely
faster under the MMU lock.
On Thu, Feb 20, 2020 at 5:53 AM Zhoujian (jay) <jianjay.zhou@huawei.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Peter Xu [mailto:peterx@redhat.com]
> > Sent: Thursday, February 20, 2020 1:19 AM
> > To: Zhoujian (jay) <jianjay.zhou@huawei.com>
> > Cc: kvm@vger.kernel.org; qemu-devel@nongnu.org; pbonzini@redhat.com;
> > dgilbert@redhat.com; quintela@redhat.com; Liujinsong (Paul)
> > <liu.jinsong@huawei.com>; linfeng (M) <linfeng23@huawei.com>; wangxin (U)
> > <wangxinxin.wang@huawei.com>; Huangweidong (C)
> > <weidong.huang@huawei.com>
> > Subject: Re: RFC: Split EPT huge pages in advance of dirty logging
> >
> > On Wed, Feb 19, 2020 at 01:19:08PM +0000, Zhoujian (jay) wrote:
> > > Hi Peter,
> > >
> > > > -----Original Message-----
> > > > From: Peter Xu [mailto:peterx@redhat.com]
> > > > Sent: Wednesday, February 19, 2020 1:43 AM
> > > > To: Zhoujian (jay) <jianjay.zhou@huawei.com>
> > > > Cc: kvm@vger.kernel.org; qemu-devel@nongnu.org;
> > pbonzini@redhat.com;
> > > > dgilbert@redhat.com; quintela@redhat.com; Liujinsong (Paul)
> > > > <liu.jinsong@huawei.com>; linfeng (M) <linfeng23@huawei.com>;
> > > > wangxin (U) <wangxinxin.wang@huawei.com>; Huangweidong (C)
> > > > <weidong.huang@huawei.com>
> > > > Subject: Re: RFC: Split EPT huge pages in advance of dirty logging
> > > >
> > > > On Tue, Feb 18, 2020 at 01:13:47PM +0000, Zhoujian (jay) wrote:
> > > > > Hi all,
> > > > >
> > > > > We found that the guest will be soft-lockup occasionally when live
> > > > > migrating a 60 vCPU, 512GiB huge page and memory sensitive VM. The
> > > > > reason is clear, almost all of the vCPUs are waiting for the KVM
> > > > > MMU spin-lock to create 4K SPTEs when the huge pages are write
> > > > > protected. This
> > > > phenomenon is also described in this patch set:
> > > > > https://patchwork.kernel.org/cover/11163459/
> > > > > which aims to handle page faults in parallel more efficiently.
> > > > >
> > > > > Our idea is to use the migration thread to touch all of the guest
> > > > > memory in the granularity of 4K before enabling dirty logging. To
> > > > > be more specific, we split all the PDPE_LEVEL SPTEs into
> > > > > DIRECTORY_LEVEL SPTEs as the first step, and then split all the
> > > > > DIRECTORY_LEVEL SPTEs into
> > > > PAGE_TABLE_LEVEL SPTEs as the following step.
> > > >
> > > > IIUC, QEMU will prefer to use huge pages for all the anonymous
> > > > ramblocks (please refer to ram_block_add):
> > > >
> > > > qemu_madvise(new_block->host, new_block->max_length,
> > > > QEMU_MADV_HUGEPAGE);
> > >
> > > Yes, you're right
> > >
> > > >
> > > > Another alternative I can think of is to add an extra parameter to
> > > > QEMU to explicitly disable huge pages (so that can even be
> > > > MADV_NOHUGEPAGE instead of MADV_HUGEPAGE). However that
> > should also
> > > > drag down the performance for the whole lifecycle of the VM.
> > >
> > > From the performance point of view, it is better to keep the huge
> > > pages when the VM is not in the live migration state.
> > >
> > > > A 3rd option is to make a QMP
> > > > command to dynamically turn huge pages on/off for ramblocks globally.
> > >
> > > We're searching a dynamic method too.
> > > We plan to add two new flags for each memory slot, say
> > > KVM_MEM_FORCE_PT_DIRECTORY_PAGES and
> > > KVM_MEM_FORCE_PT_PAGE_TABLE_PAGES. These flags can be set through
> > > KVM_SET_USER_MEMORY_REGION ioctl.
> > >
> > > The mapping_level which is called by tdp_page_fault in the kernel side
> > > will return PT_DIRECTORY_LEVEL if the
> > KVM_MEM_FORCE_PT_DIRECTORY_PAGES
> > > flag of the memory slot is set, and return PT_PAGE_TABLE_LEVEL if the
> > > KVM_MEM_FORCE_PT_PAGE_TABLE_PAGES flag is set.
> > >
> > > The key steps to split the huge pages in advance of enabling dirty log
> > > is as follows:
> > > 1. The migration thread in user space uses
> > KVM_SET_USER_MEMORY_REGION
> > > ioctl to set the KVM_MEM_FORCE_PT_DIRECTORY_PAGES flag for each
> > memory
> > > slot.
> > > 2. The migration thread continues to use the KVM_SPLIT_HUGE_PAGES
> > > ioctl (which is newly added) to do the splitting of large pages in the
> > > kernel side.
> > > 3. A new vCPU is created temporally(do some initialization but will
> > > not
> > > run) to help to do the work, i.e. as the parameter of the tdp_page_fault.
> > > 4. Collect the GPA ranges of all the memory slots with the
> > > KVM_MEM_FORCE_PT_DIRECTORY_PAGES flag set.
> > > 5. Split the 1G huge pages(collected in step 4) into 2M by calling
> > > tdp_page_fault, since the mapping_level will return
> > > PT_DIRECTORY_LEVEL. Here is the main difference from the usual path
> > > which is caused by the Guest side(EPT violation/misconfig etc), we
> > > call it directly in the hypervisor side.
> > > 6. Do some cleanups, i.e. free the vCPU related resources 7. The
> > > KVM_SPLIT_HUGE_PAGES ioctl returned to the user space side.
> > > 8. Using KVM_MEM_FORCE_PT_PAGE_TABLE_PAGES instread of
> > > KVM_MEM_FORCE_PT_DIRECTORY_PAGES to repeat step 1 ~ step 7, in step
> > 5
> > > the 2M huge pages will be splitted into 4K pages.
> > > 9. Clear the KVM_MEM_FORCE_PT_DIRECTORY_PAGES and
> > > KVM_MEM_FORCE_PT_PAGE_TABLE_PAGES flags for each memory slot.
> > > 10. Then the migration thread calls the log_start ioctl to enable the
> > > dirty logging, and the remaining thing is the same.
> >
> > I'm not sure... I think it would be good if there is a way to have finer granularity
> > control on using huge pages for any process, then KVM can directly leverage
> > that because KVM page tables should always respect the mm configurations on
> > these (so e.g. when huge page split, KVM gets notifications via mmu notifiers).
> > Have you thought of such a more general way?
>
> I did have thought of this, if we split the huge pages into 4K of a process, I'm
> afraid it will not be workable for the huge pages sharing scenario, e.g. DPDK,
> SPDK etc. So, only split the EPT page table and keep the VM process page table
> (e.g. qemu) untouched is the goal.
>
> >
> > (And I just noticed that MADV_NOHUGEPAGE is only a hint to khugepaged
> > and probably won't split any huge page at all after madvise() returns..)
> > To tell the truth I'm still confused on how split of huge pages helped in your
> > case...
>
> I'm sorry if the meaning is not expressed clearly, and thanks for your patience.
>
> > If I read it right the test reduced some execution time from 9s to a
> > few ms after your splittion of huge pages.
>
> Yes
>
> > The thing is I don't see how split of
> > huge pages could solve the mmu_lock contention with the huge VM, because
> > IMO even if we split the huge pages into smaller ones, those pages should still
> > be write-protected and need merely the same number of page faults to resolve
> > when accessed/written? And I thought that should only be fixed with
> > solutions like what Ben has proposed with the MMU rework. Could you show
> > me what I've missed?
>
> Let me try to describe the reason of mmu_lock contention more clearly and the
> effort we tried to do...
> The huge VM only has EPT >= level 2 sptes, and level 1 sptes don't
> exist at the beginning. Write protect all the huge pages will trigger EPT
> violation to create level 1 sptes for all the vCPUs which want to write the
> content of the memory. Different vCPU write the different areas of
> the memory, but they need the same kvm->mmu_lock to create the level 1
> sptes, this situation will be worse if the number of vCPU and the memory of
> VM is large(in our case 60U512G), meanwhile the VM has
> memory-write-intensive work to do. In order to reduce the mmu_lock
> contention, we try to: write protect VM memory gradually in small chunks,
> such as 1G or 2M. Using a vCPU temporary creately by migration thread to
> split 1G to 2M as the first step, and to split 2M to 4K as the second step
> (this is a little hacking...and I do not know any side effect will be triggered
> indeed).
> Comparing to write protect all VM memory in one go, the write
> protected range is limited in this way and only the vCPUs write this limited
> range will be involved to take the mmu_lock. The contention will be reduced
> since the memory range is small and the number of vCPU involved is small
> too.
>
> Of course, it will take some extra time to split all the huge pages into 4K
> page before the real migration started, about 60s for 512G in my experiment.
>
> During the memory iterative copy phase, PML will do the dirty logging work
> (not write protected case for 4K), or IIRC using fast_page_fault to mark page
> dirty if PML is not supported, which case the mmu_lock does not needed.
>
> Regards,
> Jay Zhou
^ permalink raw reply
* Re: [RFC PATCH 1/3] efi/x86: Use symbolic constants in PE header instead of bare numbers
From: Ard Biesheuvel @ 2020-02-20 17:32 UTC (permalink / raw)
To: Arvind Sankar
Cc: linux-efi, Laszlo Ersek, Leif Lindholm, Peter Jones,
Matthew Garrett, Alexander Graf, Ilias Apalodimas,
Heinrich Schuchardt, Daniel Kiper, James Bottomley
In-Reply-To: <20200220172831.GA2417225@rani.riverdale.lan>
On Thu, 20 Feb 2020 at 18:28, Arvind Sankar <nivedita@alum.mit.edu> wrote:
>
> On Thu, Feb 20, 2020 at 12:06:47PM +0100, Ard Biesheuvel wrote:
> > Replace bare numbers in the PE/COFF header structure with symbolic
> > constants so they become self documenting.
> >
> > Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
> > ---
> > arch/x86/boot/header.S | 60 ++++++++++----------
> > 1 file changed, 31 insertions(+), 29 deletions(-)
> >
> > diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
> > index 44aeb63ca6ae..9110b58aa2ec 100644
> > --- a/arch/x86/boot/header.S
> > +++ b/arch/x86/boot/header.S
> > @@ -210,7 +200,10 @@ section_table:
> > .long 0 # PointerToLineNumbers
> > .word 0 # NumberOfRelocations
> > .word 0 # NumberOfLineNumbers
> > - .long 0x60500020 # Characteristics (section flags)
> > + .long IMAGE_SCN_CNT_CODE | \
> > + IMAGE_SCN_MEM_READ | \
> > + IMAGE_SCN_MEM_EXECUTE | \
> > + IMAGE_SCN_ALIGN_16BYTES # Characteristics
>
> The IMAGE_SCN_ALIGN bits are marked as "valid only for object files".
> Can they be removed?
>
Yes, they probably should. I just didn't want to do it in the same patch.
> >
> > #
> > # The EFI application loader requires a relocation section
> > @@ -228,7 +221,10 @@ section_table:
> > .long 0 # PointerToLineNumbers
> > .word 0 # NumberOfRelocations
> > .word 0 # NumberOfLineNumbers
> > - .long 0x42100040 # Characteristics (section flags)
> > + .long IMAGE_SCN_CNT_INITIALIZED_DATA | \
> > + IMAGE_SCN_MEM_READ | \
> > + IMAGE_SCN_MEM_DISCARDABLE | \
> > + IMAGE_SCN_ALIGN_1BYTES # Characteristics
> >
> > #ifdef CONFIG_EFI_MIXED
> > #
> > @@ -244,7 +240,10 @@ section_table:
> > .long 0 # PointerToLineNumbers
> > .word 0 # NumberOfRelocations
> > .word 0 # NumberOfLineNumbers
> > - .long 0x42100040 # Characteristics (section flags)
> > + .long IMAGE_SCN_CNT_INITIALIZED_DATA | \
> > + IMAGE_SCN_MEM_READ | \
> > + IMAGE_SCN_MEM_DISCARDABLE | \
> > + IMAGE_SCN_ALIGN_1BYTES # Characteristics
> > #endif
> >
> > #
> > @@ -263,7 +262,10 @@ section_table:
> > .long 0 # PointerToLineNumbers
> > .word 0 # NumberOfRelocations
> > .word 0 # NumberOfLineNumbers
> > - .long 0x60500020 # Characteristics (section flags)
> > + .long IMAGE_SCN_CNT_CODE | \
> > + IMAGE_SCN_MEM_READ | \
> > + IMAGE_SCN_MEM_EXECUTE | \
> > + IMAGE_SCN_ALIGN_16BYTES # Characteristics
>
> The .text section contains data as well. Shouldn't it be marked
> IMAGE_SCN_MEM_WRITE also?
>
Another good point. For ARM and arm64, I actually changed this into
split R-X and RW- sections, in case the loader decides to honour these
attributes (which it should imo)
So yes, we should either add IMAGE_SCN_MEM_WRITE, or add a .data
section (although we probably don't have the space for that).
Another thing I wondered was whether we really need the .reloc
section. We don't have one on ARM, and it works fine with the existing
EDK2 loader.
Peter: any idea whether the issue with .reloc you pointed out to me
the other day still exists in EDK2 today?
^ permalink raw reply
* [PATCH] ASoC: tas2562: Add support for digital volume control
From: Dan Murphy @ 2020-02-20 17:27 UTC (permalink / raw)
To: lgirdwood, broonie, perex, tiwai; +Cc: alsa-devel, linux-kernel, Dan Murphy
Add support for digital volume control. There is no dedicated register
for volume control but instead there are 4. The values of the registers
are determined with exponential floating point math.
So a table was created with register values for 2dB step increments
from -110dB to 0dB.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
sound/soc/codecs/tas2562.c | 94 ++++++++++++++++++++++++++++++++++++++
sound/soc/codecs/tas2562.h | 6 ++-
2 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/tas2562.c b/sound/soc/codecs/tas2562.c
index b2682c2360b6..e577aa6f304a 100644
--- a/sound/soc/codecs/tas2562.c
+++ b/sound/soc/codecs/tas2562.c
@@ -26,6 +26,24 @@
#define TAS2562_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FORMAT_S32_LE)
+/* DVC equation involves floating point math
+ * round(10^(volume in dB/20)*2^30)
+ * so create a lookup table for 2dB step
+ */
+static const unsigned int float_vol_db_lookup[] = {
+0x00000d43, 0x000010b2, 0x00001505, 0x00001a67, 0x00002151,
+0x000029f1, 0x000034cd, 0x00004279, 0x000053af, 0x0000695b,
+0x0000695b, 0x0000a6fa, 0x0000d236, 0x000108a4, 0x00014d2a,
+0x0001a36e, 0x00021008, 0x000298c0, 0x000344df, 0x00041d8f,
+0x00052e5a, 0x000685c8, 0x00083621, 0x000a566d, 0x000d03a7,
+0x0010624d, 0x0014a050, 0x0019f786, 0x0020b0bc, 0x0029279d,
+0x0033cf8d, 0x004139d3, 0x00521d50, 0x00676044, 0x0082248a,
+0x00a3d70a, 0x00ce4328, 0x0103ab3d, 0x0146e75d, 0x019b8c27,
+0x02061b89, 0x028c423f, 0x03352529, 0x0409c2b0, 0x05156d68,
+0x080e9f96, 0x0a24b062, 0x0cc509ab, 0x10137987, 0x143d1362,
+0x197a967f, 0x2013739e, 0x28619ae9, 0x32d64617, 0x40000000
+};
+
struct tas2562_data {
struct snd_soc_component *component;
struct gpio_desc *sdz_gpio;
@@ -34,6 +52,7 @@ struct tas2562_data {
struct i2c_client *client;
int v_sense_slot;
int i_sense_slot;
+ int volume_lvl;
};
static int tas2562_set_bias_level(struct snd_soc_component *component,
@@ -334,6 +353,22 @@ static int tas2562_codec_probe(struct snd_soc_component *component)
if (ret < 0)
return ret;
+ /* Set the Digital volume to -110dB */
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG4, 0x00);
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG3, 0x00);
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG2, 0x0d);
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG1, 0x43);
+ if (ret)
+ return ret;
+
+ tas2562->volume_lvl = 0;
+
return 0;
}
@@ -414,6 +449,50 @@ static int tas2562_dac_event(struct snd_soc_dapm_widget *w,
return 0;
}
+static int tas2562_volume_control_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+ struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
+
+ ucontrol->value.integer.value[0] = tas2562->volume_lvl;
+ return 0;
+}
+
+static int tas2562_volume_control_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+ struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
+ int ret;
+ u32 reg_val;
+
+ reg_val = float_vol_db_lookup[ucontrol->value.integer.value[0]/2];
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG4,
+ (reg_val & 0xff));
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG3,
+ ((reg_val >> 8) & 0xff));
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG2,
+ ((reg_val >> 16) & 0xff));
+ if (ret)
+ return ret;
+ ret = snd_soc_component_write(component, TAS2562_DVC_CFG1,
+ ((reg_val >> 24) & 0xff));
+ if (ret)
+ return ret;
+
+ tas2562->volume_lvl = ucontrol->value.integer.value[0];
+
+ return ret;
+}
+
+/* Digital Volume Control. From 0 dB to -110 dB in 1 dB steps */
+static const DECLARE_TLV_DB_SCALE(dvc_tlv, -11000, 100, 0);
+
static DECLARE_TLV_DB_SCALE(tas2562_dac_tlv, 850, 50, 0);
static const struct snd_kcontrol_new isense_switch =
@@ -427,6 +506,17 @@ static const struct snd_kcontrol_new vsense_switch =
static const struct snd_kcontrol_new tas2562_snd_controls[] = {
SOC_SINGLE_TLV("Amp Gain Volume", TAS2562_PB_CFG1, 0, 0x1c, 0,
tas2562_dac_tlv),
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Digital Volume Control",
+ .index = 0,
+ .tlv.p = dvc_tlv,
+ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = snd_soc_info_volsw,
+ .get = tas2562_volume_control_get,
+ .put = tas2562_volume_control_put,
+ .private_value = SOC_SINGLE_VALUE(TAS2562_DVC_CFG1, 0, 110, 0, 0) ,
+ },
};
static const struct snd_soc_dapm_widget tas2562_dapm_widgets[] = {
@@ -517,6 +607,10 @@ static const struct reg_default tas2562_reg_defaults[] = {
{ TAS2562_PB_CFG1, 0x20 },
{ TAS2562_TDM_CFG0, 0x09 },
{ TAS2562_TDM_CFG1, 0x02 },
+ { TAS2562_DVC_CFG1, 0x40 },
+ { TAS2562_DVC_CFG2, 0x40 },
+ { TAS2562_DVC_CFG3, 0x00 },
+ { TAS2562_DVC_CFG4, 0x00 },
};
static const struct regmap_config tas2562_regmap_config = {
diff --git a/sound/soc/codecs/tas2562.h b/sound/soc/codecs/tas2562.h
index 6f55ebcf19ea..28e75fc431d0 100644
--- a/sound/soc/codecs/tas2562.h
+++ b/sound/soc/codecs/tas2562.h
@@ -35,8 +35,10 @@
#define TAS2562_REV_ID TAS2562_REG(0, 0x7d)
/* Page 2 */
-#define TAS2562_DVC_CFG1 TAS2562_REG(2, 0x01)
-#define TAS2562_DVC_CFG2 TAS2562_REG(2, 0x02)
+#define TAS2562_DVC_CFG1 TAS2562_REG(2, 0x0c)
+#define TAS2562_DVC_CFG2 TAS2562_REG(2, 0x0d)
+#define TAS2562_DVC_CFG3 TAS2562_REG(2, 0x0e)
+#define TAS2562_DVC_CFG4 TAS2562_REG(2, 0x0f)
#define TAS2562_RESET BIT(0)
--
2.25.0
^ permalink raw reply related
* Re: [Nouveau] [PATCH] nv50_disp_chan_mthd: ensure mthd is not NULL
From: Ilia Mirkin @ 2020-02-20 17:32 UTC (permalink / raw)
To: Frédéric Pierret
Cc: Ben Skeggs, David Airlie, Daniel Vetter, dri-devel, nouveau, LKML
In-Reply-To: <c94ce223-56d5-e31a-2a2c-59defb988b28@qubes-os.org>
Hi Frédéric,
It appears Ben made his own version of this patch (probably based on
the one you added to the kernel bz), and it's already upstream:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v5.6-rc2&id=0e6176c6d286316e9431b4f695940cfac4ffe6c2
Cheers,
-ilia
On Thu, Feb 20, 2020 at 12:19 PM Frédéric Pierret
<frederic.pierret@qubes-os.org> wrote:
>
> Hi,
> Is anything missing here? How can I get this merged?
>
> Best regards,
> Frédéric Pierret
>
> On 2020-02-08 20:43, Frédéric Pierret wrote:
> > Pointer to structure array is assumed not NULL by default. It has
> > the consequence to raise a kernel panic when it's not the case.
> >
> > Basically, running at least a RTX2080TI on Xen makes a bad mmio error
> > which causes having 'mthd' pointer to be NULL in 'channv50.c'. From the
> > code, it's assumed to be not NULL by accessing directly 'mthd->data[0]'
> > which is the reason of the kernel panic. Simply check if the pointer
> > is not NULL before continuing.
> >
> > BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=206299
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Frédéric Pierret (fepitre) <frederic.pierret@qubes-os.org>
> > ---
> > drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
> > index bcf32d92ee5a..50e3539f33d2 100644
> > --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
> > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
> > @@ -74,6 +74,8 @@ nv50_disp_chan_mthd(struct nv50_disp_chan *chan, int debug)
> >
> > if (debug > subdev->debug)
> > return;
> > + if (!mthd)
> > + return;
> >
> > for (i = 0; (list = mthd->data[i].mthd) != NULL; i++) {
> > u32 base = chan->head * mthd->addr;
> >
>
> _______________________________________________
> Nouveau mailing list
> Nouveau@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply
* Re: question about iommu_need_mapping
From: Jerry Snitselaar @ 2020-02-20 17:32 UTC (permalink / raw)
To: Lu Baolu, Joerg Roedel, iommu, linux-kernel
In-Reply-To: <20200220162441.bhnpwgsmj4vlp3ve@cantor>
On Thu Feb 20 20, Jerry Snitselaar wrote:
>On Thu Feb 20 20, Lu Baolu wrote:
>>Hi Jerry,
>>
>>On 2020/2/20 7:55, Jerry Snitselaar wrote:
>>>Is it possible for a device to end up with dev->archdata.iommu == NULL
>>>on iommu_need_mapping in the following instance:
>>>
>>>1. iommu_group has dma domain for default
>>>2. device gets private identity domain in intel_iommu_add_device
>>>3. iommu_need_mapping gets called with that device.
>>>4. dmar_remove_one_dev_info sets dev->archdata.iommu = NULL via
>>>unlink_domain_info.
>>>5. request_default_domain_for_dev exits after checking that
>>>group->default_domain
>>> exists, and group->default_domain->type is dma.
>>>6. iommu_request_dma_domain_for_dev returns 0 from
>>>request_default_domain_for_dev
>>> and a private dma domain isn't created for the device.
>>>
>>
>>Yes. It's possible.
>>
>>>The case I was seeing went away with commit 9235cb13d7d1 ("iommu/vt-d:
>>>Allow devices with RMRRs to use identity domain"), because it changed
>>>which domain the group and devices were using, but it seems like it is
>>>still a possibility with the code. Baolu, you mentioned possibly
>>>removing the domain switch. Commit 98b2fffb5e27 ("iommu/vt-d: Handle
>>>32bit device with identity default domain") makes it sound like the
>>>domain switch is required.
>>
>>It's more "nice to have" than "required" if the iommu driver doesn't
>>disable swiotlb explicitly. The device access of system memory higher
>>than the device's addressing capability could go through the bounced
>>buffer implemented in swiotlb.
>>
>>Best regards,
>>baolu
>
>Hi Baolu,
>
>Would this mean switching to bounce_dma_ops instead?
>
Never mind. I see that it would go into the dma_direct code.
>Regards,
>Jerry
>
>>_______________________________________________
>>iommu mailing list
>>iommu@lists.linux-foundation.org
>>https://lists.linuxfoundation.org/mailman/listinfo/iommu
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* Re: [PATCH] bus: sunxi-rsb: Return correct data when mixing 16-bit and 8-bit reads
From: Maxime Ripard @ 2020-02-20 17:32 UTC (permalink / raw)
To: Ondrej Jirman
Cc: Samuel Holland, open list, Stephen Boyd, linux-sunxi,
Chen-Yu Tsai, moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20200219010951.395599-1-megous@megous.com>
[-- Attachment #1.1: Type: text/plain, Size: 2112 bytes --]
On Wed, Feb 19, 2020 at 02:09:50AM +0100, Ondrej Jirman wrote:
> When doing a 16-bit read that returns data in the MSB byte, the
> RSB_DATA register will keep the MSB byte unchanged when doing
> the following 8-bit read. sunxi_rsb_read() will then return
> a result that contains high byte from 16-bit read mixed with
> the 8-bit result.
>
> The consequence is that after this happens the PMIC's regmap will
> look like this: (0x33 is the high byte from the 16-bit read)
>
> % cat /sys/kernel/debug/regmap/sunxi-rsb-3a3/registers
> 00: 33
> 01: 33
> 02: 33
> 03: 33
> 04: 33
> 05: 33
> 06: 33
> 07: 33
> 08: 33
> 09: 33
> 0a: 33
> 0b: 33
> 0c: 33
> 0d: 33
> 0e: 33
> [snip]
>
> Fix this by masking the result of the read with the correct mask
> based on the size of the read. There are no 16-bit users in the
> mainline kernel, so this doesn't need to get into the stable tree.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> ---
> drivers/bus/sunxi-rsb.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
> index b8043b58568ac..8ab6a3865f569 100644
> --- a/drivers/bus/sunxi-rsb.c
> +++ b/drivers/bus/sunxi-rsb.c
> @@ -316,6 +316,7 @@ static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
> {
> u32 cmd;
> int ret;
> + u32 mask;
>
> if (!buf)
> return -EINVAL;
> @@ -323,12 +324,15 @@ static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
> switch (len) {
> case 1:
> cmd = RSB_CMD_RD8;
> + mask = 0xffu;
> break;
> case 2:
> cmd = RSB_CMD_RD16;
> + mask = 0xffffu;
> break;
> case 4:
> cmd = RSB_CMD_RD32;
> + mask = 0xffffffffu;
> break;
> default:
> dev_err(rsb->dev, "Invalid access width: %zd\n", len);
> @@ -345,7 +349,7 @@ static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
> if (ret)
> goto unlock;
>
> - *buf = readl(rsb->regs + RSB_DATA);
> + *buf = readl(rsb->regs + RSB_DATA) & mask;
Thanks for debugging this and the extensive commit log.
I guess it would be cleaner to just use GENMASK(len * 8, 0) here?
Maxime
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: question about iommu_need_mapping
From: Jerry Snitselaar @ 2020-02-20 17:32 UTC (permalink / raw)
To: Lu Baolu, Joerg Roedel, iommu, linux-kernel
In-Reply-To: <20200220162441.bhnpwgsmj4vlp3ve@cantor>
On Thu Feb 20 20, Jerry Snitselaar wrote:
>On Thu Feb 20 20, Lu Baolu wrote:
>>Hi Jerry,
>>
>>On 2020/2/20 7:55, Jerry Snitselaar wrote:
>>>Is it possible for a device to end up with dev->archdata.iommu == NULL
>>>on iommu_need_mapping in the following instance:
>>>
>>>1. iommu_group has dma domain for default
>>>2. device gets private identity domain in intel_iommu_add_device
>>>3. iommu_need_mapping gets called with that device.
>>>4. dmar_remove_one_dev_info sets dev->archdata.iommu = NULL via
>>>unlink_domain_info.
>>>5. request_default_domain_for_dev exits after checking that
>>>group->default_domain
>>> exists, and group->default_domain->type is dma.
>>>6. iommu_request_dma_domain_for_dev returns 0 from
>>>request_default_domain_for_dev
>>> and a private dma domain isn't created for the device.
>>>
>>
>>Yes. It's possible.
>>
>>>The case I was seeing went away with commit 9235cb13d7d1 ("iommu/vt-d:
>>>Allow devices with RMRRs to use identity domain"), because it changed
>>>which domain the group and devices were using, but it seems like it is
>>>still a possibility with the code. Baolu, you mentioned possibly
>>>removing the domain switch. Commit 98b2fffb5e27 ("iommu/vt-d: Handle
>>>32bit device with identity default domain") makes it sound like the
>>>domain switch is required.
>>
>>It's more "nice to have" than "required" if the iommu driver doesn't
>>disable swiotlb explicitly. The device access of system memory higher
>>than the device's addressing capability could go through the bounced
>>buffer implemented in swiotlb.
>>
>>Best regards,
>>baolu
>
>Hi Baolu,
>
>Would this mean switching to bounce_dma_ops instead?
>
Never mind. I see that it would go into the dma_direct code.
>Regards,
>Jerry
>
>>_______________________________________________
>>iommu mailing list
>>iommu@lists.linux-foundation.org
>>https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* Re: [PATCH] bus: sunxi-rsb: Return correct data when mixing 16-bit and 8-bit reads
From: Maxime Ripard @ 2020-02-20 17:32 UTC (permalink / raw)
To: Ondrej Jirman
Cc: linux-sunxi, Chen-Yu Tsai, Samuel Holland, Stephen Boyd,
moderated list:ARM/Allwinner sunXi SoC support, open list
In-Reply-To: <20200219010951.395599-1-megous@megous.com>
[-- Attachment #1: Type: text/plain, Size: 2112 bytes --]
On Wed, Feb 19, 2020 at 02:09:50AM +0100, Ondrej Jirman wrote:
> When doing a 16-bit read that returns data in the MSB byte, the
> RSB_DATA register will keep the MSB byte unchanged when doing
> the following 8-bit read. sunxi_rsb_read() will then return
> a result that contains high byte from 16-bit read mixed with
> the 8-bit result.
>
> The consequence is that after this happens the PMIC's regmap will
> look like this: (0x33 is the high byte from the 16-bit read)
>
> % cat /sys/kernel/debug/regmap/sunxi-rsb-3a3/registers
> 00: 33
> 01: 33
> 02: 33
> 03: 33
> 04: 33
> 05: 33
> 06: 33
> 07: 33
> 08: 33
> 09: 33
> 0a: 33
> 0b: 33
> 0c: 33
> 0d: 33
> 0e: 33
> [snip]
>
> Fix this by masking the result of the read with the correct mask
> based on the size of the read. There are no 16-bit users in the
> mainline kernel, so this doesn't need to get into the stable tree.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> ---
> drivers/bus/sunxi-rsb.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
> index b8043b58568ac..8ab6a3865f569 100644
> --- a/drivers/bus/sunxi-rsb.c
> +++ b/drivers/bus/sunxi-rsb.c
> @@ -316,6 +316,7 @@ static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
> {
> u32 cmd;
> int ret;
> + u32 mask;
>
> if (!buf)
> return -EINVAL;
> @@ -323,12 +324,15 @@ static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
> switch (len) {
> case 1:
> cmd = RSB_CMD_RD8;
> + mask = 0xffu;
> break;
> case 2:
> cmd = RSB_CMD_RD16;
> + mask = 0xffffu;
> break;
> case 4:
> cmd = RSB_CMD_RD32;
> + mask = 0xffffffffu;
> break;
> default:
> dev_err(rsb->dev, "Invalid access width: %zd\n", len);
> @@ -345,7 +349,7 @@ static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
> if (ret)
> goto unlock;
>
> - *buf = readl(rsb->regs + RSB_DATA);
> + *buf = readl(rsb->regs + RSB_DATA) & mask;
Thanks for debugging this and the extensive commit log.
I guess it would be cleaner to just use GENMASK(len * 8, 0) here?
Maxime
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [Xen-devel] [PATCH v2] rwlock: allow recursive read locking when already locked in write mode
From: Roger Pau Monne @ 2020-02-20 17:31 UTC (permalink / raw)
To: xen-devel
Cc: Jürgen Groß, Stefano Stabellini, Julien Grall, Wei Liu,
Konrad Rzeszutek Wilk, George Dunlap, Andrew Cooper, Ian Jackson,
Jan Beulich, Roger Pau Monne
Allow a CPU already holding the lock in write mode to also lock it in
read mode. There's no harm in allowing read locking a rwlock that's
already owned by the caller (ie: CPU) in write mode. Allowing such
accesses is required at least for the CPU maps use-case.
In order to do this reserve 14bits of the lock, this allows to support
up to 16384 CPUs. Also reduce the write lock mask to 2 bits: one to
signal there are pending writers waiting on the lock and the other to
signal the lock is owned in write mode. Note the write related data
is using 16bits, this is done in order to be able to clear it (and
thus release the lock) using a 16bit atomic write.
This reduces the maximum number of concurrent readers from 16777216 to
65536, I think this should still be enough, or else the lock field
can be expanded from 32 to 64bits if all architectures support atomic
operations on 64bit integers.
Fixes: 5872c83b42c608 ('smp: convert the cpu maps lock into a rw lock')
Reported-by: Jan Beulich <jbeulich@suse.com>
Reported-by: Jürgen Groß <jgross@suse.com>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
Changes since v1:
- Move the processor ID field to start at bit 0 and hence avoid the
shift when checking it.
- Enlarge write related structures to use 16bit, and hence allow them
to be cleared using an atomic write.
---
xen/common/rwlock.c | 4 +--
xen/include/xen/rwlock.h | 53 +++++++++++++++++++++++++---------------
2 files changed, 35 insertions(+), 22 deletions(-)
diff --git a/xen/common/rwlock.c b/xen/common/rwlock.c
index d568bbf6de..dadab372b5 100644
--- a/xen/common/rwlock.c
+++ b/xen/common/rwlock.c
@@ -69,7 +69,7 @@ void queue_write_lock_slowpath(rwlock_t *lock)
/* Try to acquire the lock directly if no reader is present. */
if ( !atomic_read(&lock->cnts) &&
- (atomic_cmpxchg(&lock->cnts, 0, _QW_LOCKED) == 0) )
+ (atomic_cmpxchg(&lock->cnts, 0, _write_lock_val()) == 0) )
goto unlock;
/*
@@ -93,7 +93,7 @@ void queue_write_lock_slowpath(rwlock_t *lock)
cnts = atomic_read(&lock->cnts);
if ( (cnts == _QW_WAITING) &&
(atomic_cmpxchg(&lock->cnts, _QW_WAITING,
- _QW_LOCKED) == _QW_WAITING) )
+ _write_lock_val()) == _QW_WAITING) )
break;
cpu_relax();
diff --git a/xen/include/xen/rwlock.h b/xen/include/xen/rwlock.h
index 3dfea1ac2a..59f0d21075 100644
--- a/xen/include/xen/rwlock.h
+++ b/xen/include/xen/rwlock.h
@@ -20,21 +20,30 @@ typedef struct {
#define DEFINE_RWLOCK(l) rwlock_t l = RW_LOCK_UNLOCKED
#define rwlock_init(l) (*(l) = (rwlock_t)RW_LOCK_UNLOCKED)
-/*
- * Writer states & reader shift and bias.
- *
- * Writer field is 8 bit to allow for potential optimisation, see
- * _write_unlock().
- */
-#define _QW_WAITING 1 /* A writer is waiting */
-#define _QW_LOCKED 0xff /* A writer holds the lock */
-#define _QW_WMASK 0xff /* Writer mask.*/
-#define _QR_SHIFT 8 /* Reader count shift */
+/* Writer states & reader shift and bias. */
+#define _QW_CPUMASK 0x3fff /* Writer CPU mask */
+#define _QW_SHIFT 14 /* Writer flags shift */
+#define _QW_WAITING (1u << _QW_SHIFT) /* A writer is waiting */
+#define _QW_LOCKED (3u << _QW_SHIFT) /* A writer holds the lock */
+#define _QW_WMASK (3u << _QW_SHIFT) /* Writer mask */
+#define _QR_SHIFT 16 /* Reader count shift */
#define _QR_BIAS (1U << _QR_SHIFT)
void queue_read_lock_slowpath(rwlock_t *lock);
void queue_write_lock_slowpath(rwlock_t *lock);
+static inline bool _is_write_locked_by_me(uint32_t cnts)
+{
+ BUILD_BUG_ON(_QW_CPUMASK < NR_CPUS);
+ return (cnts & _QW_WMASK) == _QW_LOCKED &&
+ (cnts & _QW_CPUMASK) == smp_processor_id();
+}
+
+static inline bool _can_read_lock(uint32_t cnts)
+{
+ return !(cnts & _QW_WMASK) || _is_write_locked_by_me(cnts);
+}
+
/*
* _read_trylock - try to acquire read lock of a queue rwlock.
* @lock : Pointer to queue rwlock structure.
@@ -45,10 +54,10 @@ static inline int _read_trylock(rwlock_t *lock)
u32 cnts;
cnts = atomic_read(&lock->cnts);
- if ( likely(!(cnts & _QW_WMASK)) )
+ if ( likely(_can_read_lock(cnts)) )
{
cnts = (u32)atomic_add_return(_QR_BIAS, &lock->cnts);
- if ( likely(!(cnts & _QW_WMASK)) )
+ if ( likely(_can_read_lock(cnts)) )
return 1;
atomic_sub(_QR_BIAS, &lock->cnts);
}
@@ -64,7 +73,7 @@ static inline void _read_lock(rwlock_t *lock)
u32 cnts;
cnts = atomic_add_return(_QR_BIAS, &lock->cnts);
- if ( likely(!(cnts & _QW_WMASK)) )
+ if ( likely(_can_read_lock(cnts)) )
return;
/* The slowpath will decrement the reader count, if necessary. */
@@ -115,6 +124,11 @@ static inline int _rw_is_locked(rwlock_t *lock)
return atomic_read(&lock->cnts);
}
+static inline uint32_t _write_lock_val(void)
+{
+ return _QW_LOCKED | smp_processor_id();
+}
+
/*
* queue_write_lock - acquire write lock of a queue rwlock.
* @lock : Pointer to queue rwlock structure.
@@ -122,7 +136,7 @@ static inline int _rw_is_locked(rwlock_t *lock)
static inline void _write_lock(rwlock_t *lock)
{
/* Optimize for the unfair lock case where the fair flag is 0. */
- if ( atomic_cmpxchg(&lock->cnts, 0, _QW_LOCKED) == 0 )
+ if ( atomic_cmpxchg(&lock->cnts, 0, _write_lock_val()) == 0 )
return;
queue_write_lock_slowpath(lock);
@@ -157,16 +171,15 @@ static inline int _write_trylock(rwlock_t *lock)
if ( unlikely(cnts) )
return 0;
- return likely(atomic_cmpxchg(&lock->cnts, 0, _QW_LOCKED) == 0);
+ return likely(atomic_cmpxchg(&lock->cnts, 0, _write_lock_val()) == 0);
}
static inline void _write_unlock(rwlock_t *lock)
{
- /*
- * If the writer field is atomic, it can be cleared directly.
- * Otherwise, an atomic subtraction will be used to clear it.
- */
- atomic_sub(_QW_LOCKED, &lock->cnts);
+ /* Since the writer field is atomic, it can be cleared directly. */
+ ASSERT(_is_write_locked_by_me(atomic_read(&lock->cnts)));
+ BUILD_BUG_ON(_QR_SHIFT != 16);
+ write_atomic((uint16_t *)&lock->cnts, 0);
}
static inline void _write_unlock_irq(rwlock_t *lock)
--
2.25.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related
* [ext4:fix-bz-206443 3/6] fs/ext4/balloc.c:285:16: sparse: sparse: incompatible types in comparison expression (different address spaces):
From: kbuild test robot @ 2020-02-20 17:31 UTC (permalink / raw)
To: Theodore Ts'o; +Cc: kbuild-all, linux-ext4
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git fix-bz-206443
head: c20bac9bf82cd6560d269aa1e885e036d9e418b3
commit: cd19e90e29ccc914b52eeb53afef676edaac911c [3/6] ext4: fix potential race between online resizing and write operations
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-173-ge0787745-dirty
git checkout cd19e90e29ccc914b52eeb53afef676edaac911c
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> fs/ext4/balloc.c:285:16: sparse: sparse: incompatible types in comparison expression (different address spaces):
>> fs/ext4/balloc.c:285:16: sparse: struct buffer_head *[noderef] <asn:4> *
>> fs/ext4/balloc.c:285:16: sparse: struct buffer_head **
--
>> fs/ext4/resize.c:894:9: sparse: sparse: incompatible types in comparison expression (different address spaces):
>> fs/ext4/resize.c:894:9: sparse: struct buffer_head *[noderef] <asn:4> *
>> fs/ext4/resize.c:894:9: sparse: struct buffer_head **
fs/ext4/resize.c:952:9: sparse: sparse: incompatible types in comparison expression (different address spaces):
fs/ext4/resize.c:952:9: sparse: struct buffer_head *[noderef] <asn:4> *
fs/ext4/resize.c:952:9: sparse: struct buffer_head **
vim +285 fs/ext4/balloc.c
245
246 /*
247 * The free blocks are managed by bitmaps. A file system contains several
248 * blocks groups. Each group contains 1 bitmap block for blocks, 1 bitmap
249 * block for inodes, N blocks for the inode table and data blocks.
250 *
251 * The file system contains group descriptors which are located after the
252 * super block. Each descriptor contains the number of the bitmap block and
253 * the free blocks count in the block. The descriptors are loaded in memory
254 * when a file system is mounted (see ext4_fill_super).
255 */
256
257 /**
258 * ext4_get_group_desc() -- load group descriptor from disk
259 * @sb: super block
260 * @block_group: given block group
261 * @bh: pointer to the buffer head to store the block
262 * group descriptor
263 */
264 struct ext4_group_desc * ext4_get_group_desc(struct super_block *sb,
265 ext4_group_t block_group,
266 struct buffer_head **bh)
267 {
268 unsigned int group_desc;
269 unsigned int offset;
270 ext4_group_t ngroups = ext4_get_groups_count(sb);
271 struct ext4_group_desc *desc;
272 struct ext4_sb_info *sbi = EXT4_SB(sb);
273 struct buffer_head *bh_p;
274
275 if (block_group >= ngroups) {
276 ext4_error(sb, "block_group >= groups_count - block_group = %u,"
277 " groups_count = %u", block_group, ngroups);
278
279 return NULL;
280 }
281
282 group_desc = block_group >> EXT4_DESC_PER_BLOCK_BITS(sb);
283 offset = block_group & (EXT4_DESC_PER_BLOCK(sb) - 1);
284 rcu_read_lock();
> 285 bh_p = rcu_dereference(sbi->s_group_desc)[group_desc];
286 /*
287 * We can unlock here since the pointer being dereferenced won't be
288 * dereferenced again. By looking at the usage in add_new_gdb() the
289 * value isn't modified, just the pointer, and so it remains valid.
290 */
291 rcu_read_unlock();
292 if (!bh_p) {
293 ext4_error(sb, "Group descriptor not loaded - "
294 "block_group = %u, group_desc = %u, desc = %u",
295 block_group, group_desc, offset);
296 return NULL;
297 }
298
299 desc = (struct ext4_group_desc *)(
300 (__u8 *)bh_p->b_data +
301 offset * EXT4_DESC_SIZE(sb));
302 if (bh)
303 *bh = bh_p;
304 return desc;
305 }
306
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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