* [f2fs-dev] [Bug 208565] There may be dead lock for cp_rwsem during checkpoint
From: bugzilla-daemon @ 2020-07-17 1:54 UTC (permalink / raw)
To: linux-f2fs-devel
In-Reply-To: <bug-208565-202145@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=208565
Chao Yu (chao@kernel.org) changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |ASSIGNED
CC| |chao@kernel.org
--- Comment #2 from Chao Yu (chao@kernel.org) ---
(In reply to Jaegeuk Kim from comment #1)
> Thank you for the report.
>
> I think this is valid point that we need to fix.
> I'm testing a RFC patch like this. Thanks.
>
Could you please check generic/204 testcase? as this fix diff skips codes added
in commit 052a82d85a3b ("f2fs: fix to writeout dirty inode during node flush").
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* [igt-dev] [PATCH] i915/perf: Sanity check reports in mapped OA buffer
From: Umesh Nerlige Ramappa @ 2020-07-17 1:54 UTC (permalink / raw)
To: Lionel G Landwerlin, igt-dev
For applications that need a faster way to access reports in the OA
buffer, i915 now provides a way to map the OA buffer to privileged user
space. Add a test to sanity check reports in the mapped OA buffer.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
include/drm-uapi/i915_drm.h | 32 ++++++++++
tests/i915/perf.c | 118 ++++++++++++++++++++++++++++++++++++
2 files changed, 150 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 2b55af13..f7523d55 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2048,6 +2048,38 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
+/**
+ * Returns OA buffer properties to be used with mmap.
+ *
+ * This ioctl is available in perf revision 6.
+ */
+#define I915_PERF_IOCTL_GET_OA_BUFFER_INFO _IO('i', 0x3)
+
+/**
+ * OA buffer size and offset.
+ */
+struct drm_i915_perf_oa_buffer_info {
+ __u32 size;
+ __u32 offset;
+ __u64 reserved[4];
+};
+
+/**
+ * Returns current position of OA buffer head and tail.
+ *
+ * This ioctl is available in perf revision 6.
+ */
+#define I915_PERF_IOCTL_GET_OA_BUFFER_HEAD_TAIL _IO('i', 0x4)
+
+/**
+ * OA buffer head and tail.
+ */
+struct drm_i915_perf_oa_buffer_head_tail {
+ __u32 head;
+ __u32 tail;
+ __u64 reserved[4];
+};
+
/**
* Common to all i915 perf records
*/
diff --git a/tests/i915/perf.c b/tests/i915/perf.c
index 92edc9f1..36e98ffa 100644
--- a/tests/i915/perf.c
+++ b/tests/i915/perf.c
@@ -204,6 +204,7 @@ static struct intel_perf *intel_perf = NULL;
static struct intel_perf_metric_set *test_set = NULL;
static bool *undefined_a_counters;
static uint64_t oa_exp_1_millisec;
+struct intel_mmio_data mmio_data;
static igt_render_copyfunc_t render_copy = NULL;
static uint32_t (*read_report_ticks)(uint32_t *report,
@@ -4768,6 +4769,108 @@ test_whitelisted_registers_userspace_config(void)
i915_perf_remove_config(drm_fd, config_id);
}
+#define OA_BUFFER_DATA(tail, head, oa_buffer_size) \
+ (((tail) - (head)) & ((oa_buffer_size) - 1))
+
+static uint32_t oa_status_reg(void)
+{
+ if (IS_HASWELL(devid))
+ return intel_register_read(&mmio_data, 0x2346) & 0x7;
+ else if (IS_GEN12(devid))
+ return intel_register_read(&mmio_data, 0xdafc) & 0x7;
+ else
+ return intel_register_read(&mmio_data, 0x2b08) & 0xf;
+}
+
+static void check_reports_from_mapped_buffer(enum drm_i915_oa_format fmt,
+ int oa_exponent)
+{
+ struct drm_i915_perf_oa_buffer_info oa_buffer;
+ struct drm_i915_perf_oa_buffer_head_tail oa_ht;
+ struct oa_format format = get_oa_format(fmt);
+ size_t report_size = format.size;
+ uint8_t *reports;
+ uint32_t *report0, *report1;
+ uint32_t num_reports, timer_reports = 0;
+ uint32_t period_us = oa_exponent_to_ns(oa_exponent) / 1000;
+ void *oa_vaddr;
+ int i;
+
+ do_ioctl(stream_fd, I915_PERF_IOCTL_GET_OA_BUFFER_INFO, &oa_buffer);
+
+ igt_debug("size = %d\n", oa_buffer.size);
+ igt_debug("offset = %x\n", oa_buffer.offset);
+
+ igt_assert_eq(oa_buffer.size & (oa_buffer.size - 1), 0);
+ igt_assert_eq(oa_status_reg(), 0);
+
+ /* try a couple invalid mmaps */
+ /* bad offsets */
+ igt_assert(mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE,
+ stream_fd, 0) == (void *) -1);
+ igt_assert(mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE,
+ stream_fd, 8192) == (void *) -1);
+ igt_assert(mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE,
+ stream_fd, 11) == (void *) -1);
+
+ /* bad size */
+ igt_assert(mmap(0, oa_buffer.size + 4096, PROT_READ, MAP_PRIVATE,
+ stream_fd, oa_buffer.offset) == (void *) -1);
+
+ /* do the right thing */
+ oa_vaddr = mmap(0, oa_buffer.size, PROT_READ, MAP_PRIVATE, stream_fd, oa_buffer.offset);
+
+ /* wait for approx 100 reports */
+ usleep(100 * period_us);
+
+ do_ioctl(stream_fd, I915_PERF_IOCTL_GET_OA_BUFFER_HEAD_TAIL, &oa_ht);
+
+ igt_debug("head = %x\n", oa_ht.head);
+ igt_debug("tail = %x\n", oa_ht.tail);
+
+ reports = (uint8_t *) (oa_vaddr + oa_ht.head);
+
+ num_reports = OA_BUFFER_DATA(oa_ht.tail,
+ oa_ht.head,
+ oa_buffer.size) / report_size;
+
+ for (i = 0; i < num_reports; i++) {
+ report1 = (uint32_t *)(reports + (i * report_size));
+ if (!oa_report_is_periodic(oa_exponent, report1))
+ continue;
+
+ timer_reports++;
+ if (timer_reports >= 2)
+ sanity_check_reports(report0, report1, fmt);
+
+ report0 = report1;
+ }
+
+ munmap(oa_vaddr, oa_buffer.size);
+}
+
+static void test_mapped_oa_buffer(void)
+{
+ int oa_exponent = max_oa_exponent_for_period_lte(1000000);
+ enum drm_i915_oa_format fmt = test_set->perf_oa_format;
+ uint64_t properties[] = {
+ DRM_I915_PERF_PROP_SAMPLE_OA, true,
+ DRM_I915_PERF_PROP_OA_METRICS_SET, test_set->perf_oa_metrics_set,
+ DRM_I915_PERF_PROP_OA_FORMAT, fmt,
+ DRM_I915_PERF_PROP_OA_EXPONENT, oa_exponent,
+
+ };
+ struct drm_i915_perf_open_param param = {
+ .flags = I915_PERF_FLAG_FD_CLOEXEC,
+ .num_properties = sizeof(properties) / 16,
+ .properties_ptr = to_user_pointer(properties),
+ };
+
+ stream_fd = __perf_open(drm_fd, ¶m, false);
+ check_reports_from_mapped_buffer(fmt, oa_exponent);
+ __perf_close(stream_fd);
+}
+
static unsigned
read_i915_module_ref(void)
{
@@ -4936,6 +5039,9 @@ igt_main
render_copy = igt_get_render_copyfunc(devid);
igt_require_f(render_copy, "no render-copy function\n");
+
+ intel_register_access_init(&mmio_data, intel_get_pci_device(),
+ 0, drm_fd);
}
igt_subtest("non-system-wide-paranoid")
@@ -5096,6 +5202,17 @@ igt_main
igt_subtest("whitelisted-registers-userspace-config")
test_whitelisted_registers_userspace_config();
+
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(i915_perf_revision(drm_fd) >= 6);
+ }
+
+ igt_describe("Verify mapping of oa buffer");
+ igt_subtest("mapped-oa-buffer")
+ test_mapped_oa_buffer();
+ }
+
igt_fixture {
/* leave sysctl options in their default state... */
write_u64_file("/proc/sys/dev/i915/oa_max_sample_rate", 100000);
@@ -5104,6 +5221,7 @@ igt_main
if (intel_perf)
intel_perf_free(intel_perf);
+ intel_register_access_fini(&mmio_data);
close(drm_fd);
}
}
--
2.20.1
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* [PATCH 13/13] pinctrl: rockchip: do codingstyle by adding mux route definitions
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add MR_SAME/MR_GRF/MR_PMU definitions, and update data in mux route
structures.
This patch do nothing change, only do some codingstyle.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 674 +++++------------------------
1 file changed, 104 insertions(+), 570 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 71a367896297..50558ffcc05c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -78,6 +78,9 @@ enum rockchip_pinctrl_type {
#define ROCKCHIP_DRV_3BITS_PER_PIN (3)
#define ROCKCHIP_DRV_BITS_PER_PIN (2)
+#define RK_GENMASK_VAL(h, l, v) \
+ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
+
/**
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -290,6 +293,25 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3, \
}
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
+ { \
+ .bank_num = ID, \
+ .pin = PIN, \
+ .func = FUNC, \
+ .route_offset = REG, \
+ .route_val = VAL, \
+ .route_location = FLAG, \
+ }
+
+#define MR_SAME(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
+
+#define MR_GRF(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
+
+#define MR_PMU(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
+
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @num: bank number.
@@ -804,597 +826,109 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
}
static struct rockchip_mux_route_data px30_mux_route_data[] = {
- {
- /* cif-d2m0 */
- .bank_num = 2,
- .pin = 0,
- .func = 1,
- .route_offset = 0x184,
- .route_val = BIT(16 + 7),
- }, {
- /* cif-d2m1 */
- .bank_num = 3,
- .pin = 3,
- .func = 3,
- .route_offset = 0x184,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* pdm-m0 */
- .bank_num = 3,
- .pin = 22,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 8),
- }, {
- /* pdm-m1 */
- .bank_num = 2,
- .pin = 22,
- .func = 1,
- .route_offset = 0x184,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* uart2-rxm0 */
- .bank_num = 1,
- .pin = 27,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 10),
- }, {
- /* uart2-rxm1 */
- .bank_num = 2,
- .pin = 14,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 10) | BIT(10),
- }, {
- /* uart3-rxm0 */
- .bank_num = 0,
- .pin = 17,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 9),
- }, {
- /* uart3-rxm1 */
- .bank_num = 1,
- .pin = 15,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 9) | BIT(9),
- },
+ MR_SAME(2, 0, 1, 0x184, RK_GENMASK_VAL(7, 7, 0)), /* cif-d2m0 */
+ MR_SAME(3, 3, 3, 0x184, RK_GENMASK_VAL(7, 7, 1)), /* cif-d2m1 */
+ MR_SAME(3, 22, 2, 0x184, RK_GENMASK_VAL(8, 8, 0)), /* pdm-m0 */
+ MR_SAME(2, 22, 1, 0x184, RK_GENMASK_VAL(8, 8, 1)), /* pdm-m1 */
+ MR_SAME(0, 17, 2, 0x184, RK_GENMASK_VAL(9, 9, 0)), /* uart3-rxm0 */
+ MR_SAME(1, 15, 2, 0x184, RK_GENMASK_VAL(9, 9, 1)), /* uart3-rxm1 */
+ MR_SAME(1, 27, 2, 0x184, RK_GENMASK_VAL(10, 10, 0)), /* uart2-rxm0 */
+ MR_SAME(2, 14, 2, 0x184, RK_GENMASK_VAL(10, 10, 1)), /* uart2-rxm1 */
};
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
- {
- /* spi-0 */
- .bank_num = 1,
- .pin = 10,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4),
- }, {
- /* spi-1 */
- .bank_num = 1,
- .pin = 27,
- .func = 3,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
- }, {
- /* spi-2 */
- .bank_num = 0,
- .pin = 13,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
- }, {
- /* i2s-0 */
- .bank_num = 1,
- .pin = 5,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 5),
- }, {
- /* i2s-1 */
- .bank_num = 0,
- .pin = 14,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 5) | BIT(5),
- }, {
- /* emmc-0 */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 6),
- }, {
- /* emmc-1 */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 6) | BIT(6),
- },
+ MR_SAME(1, 10, 1, 0x144, RK_GENMASK_VAL(4, 3, 0)), /* spi-0 */
+ MR_SAME(1, 27, 3, 0x144, RK_GENMASK_VAL(4, 3, 1)), /* spi-1 */
+ MR_SAME(0, 13, 2, 0x144, RK_GENMASK_VAL(4, 3, 2)), /* spi-2 */
+ MR_SAME(1, 5, 1, 0x144, RK_GENMASK_VAL(5, 5, 0)), /* i2s-0 */
+ MR_SAME(1, 14, 1, 0x144, RK_GENMASK_VAL(5, 5, 1)), /* i2s-1 */
+ MR_SAME(1, 22, 2, 0x144, RK_GENMASK_VAL(6, 6, 0)), /* emmc-0 */
+ MR_SAME(2, 4, 2, 0x144, RK_GENMASK_VAL(6, 6, 1)), /* emmc-1 */
};
static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
- {
- /* non-iomuxed emmc/flash pins on flash-dqs */
- .bank_num = 0,
- .pin = 24,
- .func = 1,
- .route_location = ROCKCHIP_ROUTE_GRF,
- .route_offset = 0xa0,
- .route_val = BIT(16 + 11),
- }, {
- /* non-iomuxed emmc/flash pins on emmc-clk */
- .bank_num = 0,
- .pin = 24,
- .func = 2,
- .route_location = ROCKCHIP_ROUTE_GRF,
- .route_offset = 0xa0,
- .route_val = BIT(16 + 11) | BIT(11),
- },
+ /* non-iomuxed emmc/flash pins on flash-dqs */
+ MR_GRF(0, 24, 1, 0xa0, RK_GENMASK_VAL(11, 11, 0)),
+ /* non-iomuxed emmc/flash pins on emmc-clk */
+ MR_GRF(0, 24, 2, 0xa0, RK_GENMASK_VAL(11, 11, 1)),
};
static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
- {
- /* pwm0-0 */
- .bank_num = 0,
- .pin = 26,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16),
- }, {
- /* pwm0-1 */
- .bank_num = 3,
- .pin = 21,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(0),
- }, {
- /* pwm1-0 */
- .bank_num = 0,
- .pin = 27,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 1),
- }, {
- /* pwm1-1 */
- .bank_num = 0,
- .pin = 30,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 1) | BIT(1),
- }, {
- /* pwm2-0 */
- .bank_num = 0,
- .pin = 28,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2),
- }, {
- /* pwm2-1 */
- .bank_num = 1,
- .pin = 12,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* pwm3-0 */
- .bank_num = 3,
- .pin = 26,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3),
- }, {
- /* pwm3-1 */
- .bank_num = 1,
- .pin = 11,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* sdio-0_d0 */
- .bank_num = 1,
- .pin = 1,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4),
- }, {
- /* sdio-1_d0 */
- .bank_num = 3,
- .pin = 2,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4) | BIT(4),
- }, {
- /* spi-0_rx */
- .bank_num = 0,
- .pin = 13,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 5),
- }, {
- /* spi-1_rx */
- .bank_num = 2,
- .pin = 0,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 5) | BIT(5),
- }, {
- /* emmc-0_cmd */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7),
- }, {
- /* emmc-1_cmd */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* uart2-0_rx */
- .bank_num = 1,
- .pin = 19,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8),
- }, {
- /* uart2-1_rx */
- .bank_num = 1,
- .pin = 10,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* uart1-0_rx */
- .bank_num = 1,
- .pin = 10,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 11),
- }, {
- /* uart1-1_rx */
- .bank_num = 3,
- .pin = 13,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 11) | BIT(11),
- },
+ MR_SAME(0, 26, 1, 0x50, RK_GENMASK_VAL(0, 0, 0)), /* pwm0-0 */
+ MR_SAME(3, 21, 1, 0x50, RK_GENMASK_VAL(0, 0, 1)), /* pwm0-1 */
+ MR_SAME(0, 27, 1, 0x50, RK_GENMASK_VAL(1, 1, 0)), /* pwm1-0 */
+ MR_SAME(0, 30, 2, 0x50, RK_GENMASK_VAL(1, 1, 1)), /* pwm1-1 */
+ MR_SAME(0, 28, 1, 0x50, RK_GENMASK_VAL(2, 2, 0)), /* pwm2-0 */
+ MR_SAME(1, 12, 2, 0x50, RK_GENMASK_VAL(2, 2, 1)), /* pwm2-1 */
+ MR_SAME(3, 26, 1, 0x50, RK_GENMASK_VAL(3, 3, 0)), /* pwm3-0 */
+ MR_SAME(1, 11, 2, 0x50, RK_GENMASK_VAL(3, 3, 1)), /* pwm3-1 */
+ MR_SAME(1, 1, 1, 0x50, RK_GENMASK_VAL(4, 4, 0)), /* sdio-0_d0 */
+ MR_SAME(3, 2, 1, 0x50, RK_GENMASK_VAL(4, 4, 1)), /* sdio-1_d0 */
+ MR_SAME(0, 13, 2, 0x50, RK_GENMASK_VAL(5, 5, 0)), /* spi-0_rx */
+ MR_SAME(2, 0, 2, 0x50, RK_GENMASK_VAL(5, 5, 1)), /* spi-1_rx */
+ MR_SAME(1, 22, 2, 0x50, RK_GENMASK_VAL(7, 7, 0)), /* emmc-0_cmd */
+ MR_SAME(2, 4, 2, 0x50, RK_GENMASK_VAL(7, 7, 1)), /* emmc-1_cmd */
+ MR_SAME(1, 19, 2, 0x50, RK_GENMASK_VAL(8, 8, 0)), /* uart2-0_rx */
+ MR_SAME(1, 10, 2, 0x50, RK_GENMASK_VAL(8, 8, 1)), /* uart2-1_rx */
+ MR_SAME(1, 10, 1, 0x50, RK_GENMASK_VAL(11, 11, 0)), /* uart1-0_rx */
+ MR_SAME(3, 13, 1, 0x50, RK_GENMASK_VAL(11, 11, 1)), /* uart1-1_rx */
};
static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
- {
- /* edphdmi_cecinoutt1 */
- .bank_num = 7,
- .pin = 16,
- .func = 2,
- .route_offset = 0x264,
- .route_val = BIT(16 + 12) | BIT(12),
- }, {
- /* edphdmi_cecinout */
- .bank_num = 7,
- .pin = 23,
- .func = 4,
- .route_offset = 0x264,
- .route_val = BIT(16 + 12),
- },
+ MR_SAME(7, 16, 2, 0x264, RK_GENMASK_VAL(12, 12, 1)), /* edphdmi_cecinoutt1 */
+ MR_SAME(7, 23, 4, 0x264, RK_GENMASK_VAL(12, 12, 0)), /* edphdmi_cecinout */
};
static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
- {
- /* rtc_clk */
- .bank_num = 0,
- .pin = 19,
- .func = 1,
- .route_offset = 0x314,
- .route_val = BIT(16 + 0) | BIT(0),
- }, {
- /* uart2_rxm0 */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 2) | BIT(16 + 3),
- }, {
- /* uart2_rxm1 */
- .bank_num = 4,
- .pin = 26,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
- }, {
- /* i2c3_sdam0 */
- .bank_num = 0,
- .pin = 15,
- .func = 2,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9),
- }, {
- /* i2c3_sdam1 */
- .bank_num = 3,
- .pin = 12,
- .func = 2,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
- }, {
- /* i2c3_sdam2 */
- .bank_num = 2,
- .pin = 0,
- .func = 3,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
- }, {
- /* i2s-8ch-1-sclktxm0 */
- .bank_num = 1,
- .pin = 3,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3),
- }, {
- /* i2s-8ch-1-sclkrxm0 */
- .bank_num = 1,
- .pin = 4,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3),
- }, {
- /* i2s-8ch-1-sclktxm1 */
- .bank_num = 1,
- .pin = 13,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* i2s-8ch-1-sclkrxm1 */
- .bank_num = 1,
- .pin = 14,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* pdm-clkm0 */
- .bank_num = 1,
- .pin = 4,
- .func = 3,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13),
- }, {
- /* pdm-clkm1 */
- .bank_num = 1,
- .pin = 14,
- .func = 4,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
- }, {
- /* pdm-clkm2 */
- .bank_num = 2,
- .pin = 6,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
- }, {
- /* pdm-clkm-m2 */
- .bank_num = 2,
- .pin = 4,
- .func = 3,
- .route_offset = 0x600,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* spi1_miso */
- .bank_num = 3,
- .pin = 10,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 9),
- }, {
- /* spi1_miso_m1 */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 9) | BIT(9),
- }, {
- /* owire_m0 */
- .bank_num = 0,
- .pin = 11,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11),
- }, {
- /* owire_m1 */
- .bank_num = 1,
- .pin = 22,
- .func = 7,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
- }, {
- /* owire_m2 */
- .bank_num = 2,
- .pin = 2,
- .func = 5,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
- }, {
- /* can_rxd_m0 */
- .bank_num = 0,
- .pin = 11,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13),
- }, {
- /* can_rxd_m1 */
- .bank_num = 1,
- .pin = 22,
- .func = 5,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
- }, {
- /* can_rxd_m2 */
- .bank_num = 2,
- .pin = 2,
- .func = 4,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
- }, {
- /* mac_rxd0_m0 */
- .bank_num = 1,
- .pin = 20,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 14),
- }, {
- /* mac_rxd0_m1 */
- .bank_num = 4,
- .pin = 2,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 14) | BIT(14),
- }, {
- /* uart3_rx */
- .bank_num = 3,
- .pin = 12,
- .func = 4,
- .route_offset = 0x314,
- .route_val = BIT(16 + 15),
- }, {
- /* uart3_rx_m1 */
- .bank_num = 0,
- .pin = 17,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 15) | BIT(15),
- },
+ MR_SAME(0, 19, 1, 0x314, RK_GENMASK_VAL(0, 0, 1)), /* rtc_clk */
+ MR_SAME(1, 22, 2, 0x314, RK_GENMASK_VAL(3, 2, 0)), /* uart2_rxm0 */
+ MR_SAME(4, 26, 2, 0x314, RK_GENMASK_VAL(3, 2, 1)), /* uart2_rxm1 */
+ MR_SAME(0, 15, 2, 0x608, RK_GENMASK_VAL(9, 8, 0)), /* i2c3_sdam0 */
+ MR_SAME(3, 12, 2, 0x608, RK_GENMASK_VAL(9, 8, 1)), /* i2c3_sdam1 */
+ MR_SAME(2, 0, 3, 0x608, RK_GENMASK_VAL(9, 8, 2)), /* i2c3_sdam2 */
+ MR_SAME(1, 3, 2, 0x308, RK_GENMASK_VAL(3, 3, 0)), /* i2s-8ch-1-sclktxm0 */
+ MR_SAME(1, 4, 2, 0x308, RK_GENMASK_VAL(3, 3, 0)), /* i2s-8ch-1-sclkrxm0 */
+ MR_SAME(1, 13, 2, 0x308, RK_GENMASK_VAL(3, 3, 1)), /* i2s-8ch-1-sclktxm1 */
+ MR_SAME(1, 14, 2, 0x308, RK_GENMASK_VAL(3, 3, 1)), /* i2s-8ch-1-sclkrxm1 */
+ MR_SAME(1, 4, 3, 0x308, RK_GENMASK_VAL(13, 12, 0)), /* pdm-clkm0 */
+ MR_SAME(1, 14, 4, 0x308, RK_GENMASK_VAL(13, 12, 1)), /* pdm-clkm1 */
+ MR_SAME(2, 6, 2, 0x308, RK_GENMASK_VAL(13, 12, 2)), /* pdm-clkm2 */
+ MR_SAME(2, 4, 3, 0x600, RK_GENMASK_VAL(2, 2, 1)), /* pdm-clkm-m2 */
+ MR_SAME(3, 10, 3, 0x314, RK_GENMASK_VAL(9, 9, 0)), /* spi1_miso */
+ MR_SAME(2, 4, 2, 0x314, RK_GENMASK_VAL(9, 9, 1)), /* spi1_miso_m1 */
+ MR_SAME(0, 11, 3, 0x314, RK_GENMASK_VAL(11, 10, 0)), /* owire_m0 */
+ MR_SAME(1, 22, 7, 0x314, RK_GENMASK_VAL(11, 10, 1)), /* owire_m1 */
+ MR_SAME(2, 2, 5, 0x314, RK_GENMASK_VAL(11, 10, 2)), /* owire_m2 */
+ MR_SAME(0, 11, 2, 0x314, RK_GENMASK_VAL(13, 12, 0)), /* can_rxd_m0 */
+ MR_SAME(1, 22, 5, 0x314, RK_GENMASK_VAL(13, 12, 1)), /* can_rxd_m1 */
+ MR_SAME(2, 2, 4, 0x314, RK_GENMASK_VAL(13, 12, 2)), /* can_rxd_m2 */
+ MR_SAME(1, 20, 3, 0x314, RK_GENMASK_VAL(14, 14, 0)), /* mac_rxd0_m0 */
+ MR_SAME(4, 2, 2, 0x314, RK_GENMASK_VAL(14, 14, 1)), /* mac_rxd0_m1 */
+ MR_SAME(3, 12, 4, 0x314, RK_GENMASK_VAL(15, 15, 0)), /* uart3_rx */
+ MR_SAME(0, 17, 3, 0x314, RK_GENMASK_VAL(15, 15, 1)), /* uart3_rx_m1 */
};
static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
- {
- /* uart2dbg_rxm0 */
- .bank_num = 1,
- .pin = 1,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(16 + 1),
- }, {
- /* uart2dbg_rxm1 */
- .bank_num = 2,
- .pin = 1,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
- }, {
- /* gmac-m1_rxd0 */
- .bank_num = 1,
- .pin = 11,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* gmac-m1-optimized_rxd3 */
- .bank_num = 1,
- .pin = 14,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 10) | BIT(10),
- }, {
- /* pdm_sdi0m0 */
- .bank_num = 2,
- .pin = 19,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3),
- }, {
- /* pdm_sdi0m1 */
- .bank_num = 1,
- .pin = 23,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* spi_rxdm2 */
- .bank_num = 3,
- .pin = 2,
- .func = 4,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
- }, {
- /* i2s2_sdim0 */
- .bank_num = 1,
- .pin = 24,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 6),
- }, {
- /* i2s2_sdim1 */
- .bank_num = 3,
- .pin = 2,
- .func = 6,
- .route_offset = 0x50,
- .route_val = BIT(16 + 6) | BIT(6),
- }, {
- /* card_iom1 */
- .bank_num = 2,
- .pin = 22,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* tsp_d5m1 */
- .bank_num = 2,
- .pin = 16,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* cif_data5m1 */
- .bank_num = 2,
- .pin = 16,
- .func = 4,
- .route_offset = 0x50,
- .route_val = BIT(16 + 9) | BIT(9),
- },
+ MR_SAME(1, 1, 2, 0x50, RK_GENMASK_VAL(1, 0, 0)), /* uart2dbg_rxm0 */
+ MR_SAME(2, 1, 1, 0x50, RK_GENMASK_VAL(1, 0, 1)), /* uart2dbg_rxm1 */
+ MR_SAME(1, 11, 2, 0x50, RK_GENMASK_VAL(2, 2, 1)), /* gmac-m1_rxd0 */
+ MR_SAME(1, 14, 2, 0x50, RK_GENMASK_VAL(10, 10, 1)), /* gmac-m1-optimized_rxd3 */
+ MR_SAME(2, 19, 2, 0x50, RK_GENMASK_VAL(3, 3, 0)), /* pdm_sdi0m0 */
+ MR_SAME(1, 23, 3, 0x50, RK_GENMASK_VAL(3, 3, 1)), /* pdm_sdi0m1 */
+ MR_SAME(3, 2, 4, 0x50, RK_GENMASK_VAL(5, 4, 2)), /* spi_rxdm2 */
+ MR_SAME(1, 24, 1, 0x50, RK_GENMASK_VAL(6, 6, 0)), /* i2s2_sdim0 */
+ MR_SAME(3, 2, 6, 0x50, RK_GENMASK_VAL(6, 6, 1)), /* i2s2_sdim1 */
+ MR_SAME(2, 22, 3, 0x50, RK_GENMASK_VAL(7, 7, 1)), /* card_iom1 */
+ MR_SAME(2, 16, 3, 0x50, RK_GENMASK_VAL(8, 8, 1)), /* tsp_d5m1 */
+ MR_SAME(2, 16, 4, 0x50, RK_GENMASK_VAL(9, 9, 1)), /* cif_data5m1 */
};
static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
- {
- /* uart2dbga_rx */
- .bank_num = 4,
- .pin = 8,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11),
- }, {
- /* uart2dbgb_rx */
- .bank_num = 4,
- .pin = 16,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
- }, {
- /* uart2dbgc_rx */
- .bank_num = 4,
- .pin = 19,
- .func = 1,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
- }, {
- /* pcie_clkreqn */
- .bank_num = 2,
- .pin = 26,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 14),
- }, {
- /* pcie_clkreqnb */
- .bank_num = 4,
- .pin = 24,
- .func = 1,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 14) | BIT(14),
- },
+ MR_SAME(4, 8, 2, 0xe21c, RK_GENMASK_VAL(11, 10, 0)), /* uart2dbga_rx */
+ MR_SAME(4, 16, 2, 0xe21c, RK_GENMASK_VAL(11, 10, 1)), /* uart2dbgb_rx */
+ MR_SAME(4, 19, 1, 0xe21c, RK_GENMASK_VAL(11, 10, 2)), /* uart2dbgc_rx */
+ MR_SAME(2, 26, 2, 0xe21c, RK_GENMASK_VAL(14, 14, 0)), /* pcie_clkreqn */
+ MR_SAME(4, 24, 1, 0xe21c, RK_GENMASK_VAL(14, 14, 1)), /* pcie_clkreqnb */
};
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
--
2.17.1
^ permalink raw reply related
* [f2fs-dev] [PATCH v3 0/7] add support for direct I/O with fscrypt using blk-crypto
From: Satya Tangirala via Linux-f2fs-devel @ 2020-07-17 1:45 UTC (permalink / raw)
To: linux-fscrypt, linux-fsdevel, linux-f2fs-devel, linux-ext4
Cc: linux-xfs, Satya Tangirala
This patch series adds support for direct I/O with fscrypt using
blk-crypto. It has been rebased on fscrypt/master.
Patch 1 adds two functions to fscrypt that need to be called to determine
if direct I/O is supported for a request.
Patches 2 and 3 wire up direct-io and iomap respectively with the functions
introduced in Patch 1 and set bio crypt contexts on bios when appropriate
by calling into fscrypt.
Patches 4 and 5 allow ext4 and f2fs direct I/O to support fscrypt without
falling back to buffered I/O.
Patches 6 and 7 update the fscrypt documentation for inline encryption
support and direct I/O. The documentation now notes the required conditions
for inline encryption and direct I/O on encrypted files.
This patch series was tested by running xfstests with test_dummy_encryption
with and without the 'inlinecrypt' mount option, and there were no
meaningful regressions. One regression was for generic/587 on ext4,
but that test isn't compatible with test_dummy_encryption in the first
place, and the test "incorrectly" passes without the 'inlinecrypt' mount
option - a patch will be sent out to exclude that test when
test_dummy_encryption is turned on with ext4 (like the other quota related
tests that use user visible quota files). The other regression was for
generic/252 on ext4, which does direct I/O with a buffer aligned to the
block device's blocksize, but not necessarily aligned to the filesystem's
block size, which direct I/O with fscrypt requires.
Changes v2 => v3:
- add changelog to coverletter
Changes v1 => v2:
- Fix bug in f2fs caused by replacing f2fs_post_read_required() with
!fscrypt_dio_supported() since the latter doesn't check for
compressed inodes unlike the former.
- Add patches 6 and 7 for fscrypt documentation
- cleanups and comments
Eric Biggers (5):
fscrypt: Add functions for direct I/O support
direct-io: add support for fscrypt using blk-crypto
iomap: support direct I/O with fscrypt using blk-crypto
ext4: support direct I/O with fscrypt using blk-crypto
f2fs: support direct I/O with fscrypt using blk-crypto
Satya Tangirala (2):
fscrypt: document inline encryption support
fscrypt: update documentation for direct I/O support
Documentation/filesystems/fscrypt.rst | 36 +++++++++++-
fs/crypto/crypto.c | 8 +++
fs/crypto/inline_crypt.c | 80 +++++++++++++++++++++++++++
fs/direct-io.c | 15 ++++-
fs/ext4/file.c | 10 ++--
fs/f2fs/f2fs.h | 6 +-
fs/iomap/direct-io.c | 8 +++
include/linux/fscrypt.h | 19 +++++++
8 files changed, 173 insertions(+), 9 deletions(-)
--
2.28.0.rc0.105.gf9edc3c819-goog
_______________________________________________
Linux-f2fs-devel mailing list
Linux-f2fs-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/linux-f2fs-devel
^ permalink raw reply
* [PATCH 12/13] pinctrl: rockchip: define common codes without special chip name
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Modify RK3399_DRV_3BITS_PER_PIN to ROCKCHIP_DRV_3BITS_PER_PIN, and
modify RK3288_DRV_BITS_PER_PIN to ROCKCHIP_DRV_BITS_PER_PIN.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 3b74455dcdb2..71a367896297 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -75,6 +75,9 @@ enum rockchip_pinctrl_type {
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WIDTH_2BIT BIT(5)
+#define ROCKCHIP_DRV_3BITS_PER_PIN (3)
+#define ROCKCHIP_DRV_BITS_PER_PIN (2)
+
/**
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -2074,7 +2077,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
-#define RK3399_DRV_3BITS_PER_PIN 3
#define RK3399_PULL_BITS_PER_PIN 2
#define RK3399_PULL_PINS_PER_REG 8
#define RK3399_PULL_BANK_STRIDE 16
@@ -2154,7 +2156,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
- rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2197,7 +2199,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
- rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
@@ -2251,7 +2253,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
- rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2291,7 +2293,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
- rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
--
2.17.1
^ permalink raw reply related
* [PATCH 10/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3288 definitons to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index ec6a1a08f8b1..04e7027ec8e1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1855,6 +1855,11 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
}
#define RK3288_PULL_OFFSET 0x140
+#define RK3288_PULL_PMU_OFFSET 0x64
+#define RK3288_PULL_BITS_PER_PIN 2
+#define RK3288_PULL_PINS_PER_REG 8
+#define RK3288_PULL_BANK_STRIDE 16
+
static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
@@ -1864,22 +1869,22 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
- *reg = RK3188_PULL_PMU_OFFSET;
+ *reg = RK3288_PULL_PMU_OFFSET;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3288_PULL_PINS_PER_REG;
+ *bit *= RK3288_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3288_PULL_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3288_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3288_PULL_PINS_PER_REG);
+ *bit *= RK3288_PULL_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* [f2fs-dev] [PATCH v3 5/7] f2fs: support direct I/O with fscrypt using blk-crypto
From: Satya Tangirala via Linux-f2fs-devel @ 2020-07-17 1:45 UTC (permalink / raw)
To: linux-fscrypt, linux-fsdevel, linux-f2fs-devel, linux-ext4
Cc: linux-xfs, Satya Tangirala, Eric Biggers
In-Reply-To: <20200717014540.71515-1-satyat@google.com>
From: Eric Biggers <ebiggers@google.com>
Wire up f2fs with fscrypt direct I/O support. direct I/O with fscrypt is
only supported through blk-crypto (i.e. CONFIG_BLK_INLINE_ENCRYPTION must
have been enabled, the 'inlinecrypt' mount option must have been specified,
and either hardware inline encryption support must be present or
CONFIG_BLK_INLINE_ENCYRPTION_FALLBACK must have been enabled). Further,
direct I/O on encrypted files is only supported when I/O is aligned
to the filesystem block size (which is *not* necessarily the same as the
block device's block size).
Signed-off-by: Eric Biggers <ebiggers@google.com>
Co-developed-by: Satya Tangirala <satyat@google.com>
Signed-off-by: Satya Tangirala <satyat@google.com>
---
fs/f2fs/f2fs.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h
index b35a50f4953c..978130b5a195 100644
--- a/fs/f2fs/f2fs.h
+++ b/fs/f2fs/f2fs.h
@@ -4082,7 +4082,11 @@ static inline bool f2fs_force_buffered_io(struct inode *inode,
struct f2fs_sb_info *sbi = F2FS_I_SB(inode);
int rw = iov_iter_rw(iter);
- if (f2fs_post_read_required(inode))
+ if (!fscrypt_dio_supported(iocb, iter))
+ return true;
+ if (fsverity_active(inode))
+ return true;
+ if (f2fs_compressed_file(inode))
return true;
if (f2fs_is_multi_device(sbi))
return true;
--
2.28.0.rc0.105.gf9edc3c819-goog
_______________________________________________
Linux-f2fs-devel mailing list
Linux-f2fs-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/linux-f2fs-devel
^ permalink raw reply related
* + revert-squashfs-migrate-from-ll_rw_block-usage-to-bio.patch added to -mm tree
From: Andrew Morton @ 2020-07-17 1:53 UTC (permalink / raw)
To: adrien+dev, akpm, bernd.amend, drosen, groeck, hch, mm-commits,
phillip, pliard
In-Reply-To: <20200703151445.b6a0cfee402c7c5c4651f1b1@linux-foundation.org>
The patch titled
Subject: revert "squashfs: migrate from ll_rw_block usage to BIO"
has been added to the -mm tree. Its filename is
revert-squashfs-migrate-from-ll_rw_block-usage-to-bio.patch
This patch should soon appear at
http://ozlabs.org/~akpm/mmots/broken-out/revert-squashfs-migrate-from-ll_rw_block-usage-to-bio.patch
and later at
http://ozlabs.org/~akpm/mmotm/broken-out/revert-squashfs-migrate-from-ll_rw_block-usage-to-bio.patch
Before you just go and hit "reply", please:
a) Consider who else should be cc'ed
b) Prefer to cc a suitable mailing list as well
c) Ideally: find the original patch on the mailing list and do a
reply-to-all to that, adding suitable additional cc's
*** Remember to use Documentation/process/submit-checklist.rst when testing your code ***
The -mm tree is included into linux-next and is updated
there every 3-4 working days
------------------------------------------------------
From: Andrew Morton <akpm@linux-foundation.org>
Subject: revert "squashfs: migrate from ll_rw_block usage to BIO"
Revert 93e72b3c612adc ("squashfs: migrate from ll_rw_block usage to BIO")
due to a regression reported by Bernd Amend.
Link: http://lkml.kernel.org/r/CAF31+H5ZB7zn73obrc5svLzgfsTnyYe5TKvr7-6atUOqrRY+2w@mail.gmail.com
Reported-by: Bernd Amend <bernd.amend@gmail.com>
Cc: Philippe Liard <pliard@google.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Adrien Schildknecht <adrien+dev@schischi.me>
Cc: Phillip Lougher <phillip@squashfs.org.uk>
Cc: Guenter Roeck <groeck@chromium.org>
Cc: Daniel Rosenberg <drosen@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
fs/squashfs/block.c | 273 ++++++++++------------
fs/squashfs/decompressor.h | 5
fs/squashfs/decompressor_multi.c | 9
fs/squashfs/decompressor_multi_percpu.c | 6
fs/squashfs/decompressor_single.c | 9
fs/squashfs/lz4_wrapper.c | 17 -
fs/squashfs/lzo_wrapper.c | 17 -
fs/squashfs/squashfs.h | 4
fs/squashfs/xz_wrapper.c | 51 +---
fs/squashfs/zlib_wrapper.c | 63 ++---
fs/squashfs/zstd_wrapper.c | 62 ++--
11 files changed, 237 insertions(+), 279 deletions(-)
--- a/fs/squashfs/block.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/block.c
@@ -13,7 +13,6 @@
* datablocks and metadata blocks.
*/
-#include <linux/blkdev.h>
#include <linux/fs.h>
#include <linux/vfs.h>
#include <linux/slab.h>
@@ -28,104 +27,45 @@
#include "page_actor.h"
/*
- * Returns the amount of bytes copied to the page actor.
+ * Read the metadata block length, this is stored in the first two
+ * bytes of the metadata block.
*/
-static int copy_bio_to_actor(struct bio *bio,
- struct squashfs_page_actor *actor,
- int offset, int req_length)
-{
- void *actor_addr = squashfs_first_page(actor);
- struct bvec_iter_all iter_all = {};
- struct bio_vec *bvec = bvec_init_iter_all(&iter_all);
- int copied_bytes = 0;
- int actor_offset = 0;
-
- if (WARN_ON_ONCE(!bio_next_segment(bio, &iter_all)))
- return 0;
-
- while (copied_bytes < req_length) {
- int bytes_to_copy = min_t(int, bvec->bv_len - offset,
- PAGE_SIZE - actor_offset);
-
- bytes_to_copy = min_t(int, bytes_to_copy,
- req_length - copied_bytes);
- memcpy(actor_addr + actor_offset,
- page_address(bvec->bv_page) + bvec->bv_offset + offset,
- bytes_to_copy);
-
- actor_offset += bytes_to_copy;
- copied_bytes += bytes_to_copy;
- offset += bytes_to_copy;
-
- if (actor_offset >= PAGE_SIZE) {
- actor_addr = squashfs_next_page(actor);
- if (!actor_addr)
- break;
- actor_offset = 0;
- }
- if (offset >= bvec->bv_len) {
- if (!bio_next_segment(bio, &iter_all))
- break;
- offset = 0;
- }
- }
- squashfs_finish_page(actor);
- return copied_bytes;
-}
-
-static int squashfs_bio_read(struct super_block *sb, u64 index, int length,
- struct bio **biop, int *block_offset)
+static struct buffer_head *get_block_length(struct super_block *sb,
+ u64 *cur_index, int *offset, int *length)
{
struct squashfs_sb_info *msblk = sb->s_fs_info;
- const u64 read_start = round_down(index, msblk->devblksize);
- const sector_t block = read_start >> msblk->devblksize_log2;
- const u64 read_end = round_up(index + length, msblk->devblksize);
- const sector_t block_end = read_end >> msblk->devblksize_log2;
- int offset = read_start - round_down(index, PAGE_SIZE);
- int total_len = (block_end - block) << msblk->devblksize_log2;
- const int page_count = DIV_ROUND_UP(total_len + offset, PAGE_SIZE);
- int error, i;
- struct bio *bio;
-
- bio = bio_alloc(GFP_NOIO, page_count);
- if (!bio)
- return -ENOMEM;
+ struct buffer_head *bh;
- bio_set_dev(bio, sb->s_bdev);
- bio->bi_opf = READ;
- bio->bi_iter.bi_sector = block * (msblk->devblksize >> SECTOR_SHIFT);
-
- for (i = 0; i < page_count; ++i) {
- unsigned int len =
- min_t(unsigned int, PAGE_SIZE - offset, total_len);
- struct page *page = alloc_page(GFP_NOIO);
-
- if (!page) {
- error = -ENOMEM;
- goto out_free_bio;
- }
- if (!bio_add_page(bio, page, len, offset)) {
- error = -EIO;
- goto out_free_bio;
+ bh = sb_bread(sb, *cur_index);
+ if (bh == NULL)
+ return NULL;
+
+ if (msblk->devblksize - *offset == 1) {
+ *length = (unsigned char) bh->b_data[*offset];
+ put_bh(bh);
+ bh = sb_bread(sb, ++(*cur_index));
+ if (bh == NULL)
+ return NULL;
+ *length |= (unsigned char) bh->b_data[0] << 8;
+ *offset = 1;
+ } else {
+ *length = (unsigned char) bh->b_data[*offset] |
+ (unsigned char) bh->b_data[*offset + 1] << 8;
+ *offset += 2;
+
+ if (*offset == msblk->devblksize) {
+ put_bh(bh);
+ bh = sb_bread(sb, ++(*cur_index));
+ if (bh == NULL)
+ return NULL;
+ *offset = 0;
}
- offset = 0;
- total_len -= len;
}
- error = submit_bio_wait(bio);
- if (error)
- goto out_free_bio;
-
- *biop = bio;
- *block_offset = index & ((1 << msblk->devblksize_log2) - 1);
- return 0;
-
-out_free_bio:
- bio_free_pages(bio);
- bio_put(bio);
- return error;
+ return bh;
}
+
/*
* Read and decompress a metadata block or datablock. Length is non-zero
* if a datablock is being read (the size is stored elsewhere in the
@@ -136,88 +76,129 @@ out_free_bio:
* algorithms).
*/
int squashfs_read_data(struct super_block *sb, u64 index, int length,
- u64 *next_index, struct squashfs_page_actor *output)
+ u64 *next_index, struct squashfs_page_actor *output)
{
struct squashfs_sb_info *msblk = sb->s_fs_info;
- struct bio *bio = NULL;
- int compressed;
- int res;
- int offset;
+ struct buffer_head **bh;
+ int offset = index & ((1 << msblk->devblksize_log2) - 1);
+ u64 cur_index = index >> msblk->devblksize_log2;
+ int bytes, compressed, b = 0, k = 0, avail, i;
+
+ bh = kcalloc(((output->length + msblk->devblksize - 1)
+ >> msblk->devblksize_log2) + 1, sizeof(*bh), GFP_KERNEL);
+ if (bh == NULL)
+ return -ENOMEM;
if (length) {
/*
* Datablock.
*/
+ bytes = -offset;
compressed = SQUASHFS_COMPRESSED_BLOCK(length);
length = SQUASHFS_COMPRESSED_SIZE_BLOCK(length);
+ if (next_index)
+ *next_index = index + length;
+
TRACE("Block @ 0x%llx, %scompressed size %d, src size %d\n",
index, compressed ? "" : "un", length, output->length);
+
+ if (length < 0 || length > output->length ||
+ (index + length) > msblk->bytes_used)
+ goto read_failure;
+
+ for (b = 0; bytes < length; b++, cur_index++) {
+ bh[b] = sb_getblk(sb, cur_index);
+ if (bh[b] == NULL)
+ goto block_release;
+ bytes += msblk->devblksize;
+ }
+ ll_rw_block(REQ_OP_READ, 0, b, bh);
} else {
/*
* Metadata block.
*/
- const u8 *data;
- struct bvec_iter_all iter_all = {};
- struct bio_vec *bvec = bvec_init_iter_all(&iter_all);
-
- if (index + 2 > msblk->bytes_used) {
- res = -EIO;
- goto out;
- }
- res = squashfs_bio_read(sb, index, 2, &bio, &offset);
- if (res)
- goto out;
-
- if (WARN_ON_ONCE(!bio_next_segment(bio, &iter_all))) {
- res = -EIO;
- goto out_free_bio;
- }
- /* Extract the length of the metadata block */
- data = page_address(bvec->bv_page) + bvec->bv_offset;
- length = data[offset];
- if (offset <= bvec->bv_len - 1) {
- length |= data[offset + 1] << 8;
- } else {
- if (WARN_ON_ONCE(!bio_next_segment(bio, &iter_all))) {
- res = -EIO;
- goto out_free_bio;
- }
- data = page_address(bvec->bv_page) + bvec->bv_offset;
- length |= data[0] << 8;
- }
- bio_free_pages(bio);
- bio_put(bio);
+ if ((index + 2) > msblk->bytes_used)
+ goto read_failure;
+ bh[0] = get_block_length(sb, &cur_index, &offset, &length);
+ if (bh[0] == NULL)
+ goto read_failure;
+ b = 1;
+
+ bytes = msblk->devblksize - offset;
compressed = SQUASHFS_COMPRESSED(length);
length = SQUASHFS_COMPRESSED_SIZE(length);
- index += 2;
+ if (next_index)
+ *next_index = index + length + 2;
TRACE("Block @ 0x%llx, %scompressed size %d\n", index,
- compressed ? "" : "un", length);
+ compressed ? "" : "un", length);
+
+ if (length < 0 || length > output->length ||
+ (index + length) > msblk->bytes_used)
+ goto block_release;
+
+ for (; bytes < length; b++) {
+ bh[b] = sb_getblk(sb, ++cur_index);
+ if (bh[b] == NULL)
+ goto block_release;
+ bytes += msblk->devblksize;
+ }
+ ll_rw_block(REQ_OP_READ, 0, b - 1, bh + 1);
}
- if (next_index)
- *next_index = index + length;
- res = squashfs_bio_read(sb, index, length, &bio, &offset);
- if (res)
- goto out;
+ for (i = 0; i < b; i++) {
+ wait_on_buffer(bh[i]);
+ if (!buffer_uptodate(bh[i]))
+ goto block_release;
+ }
if (compressed) {
- if (!msblk->stream) {
- res = -EIO;
- goto out_free_bio;
- }
- res = squashfs_decompress(msblk, bio, offset, length, output);
+ if (!msblk->stream)
+ goto read_failure;
+ length = squashfs_decompress(msblk, bh, b, offset, length,
+ output);
+ if (length < 0)
+ goto read_failure;
} else {
- res = copy_bio_to_actor(bio, output, offset, length);
+ /*
+ * Block is uncompressed.
+ */
+ int in, pg_offset = 0;
+ void *data = squashfs_first_page(output);
+
+ for (bytes = length; k < b; k++) {
+ in = min(bytes, msblk->devblksize - offset);
+ bytes -= in;
+ while (in) {
+ if (pg_offset == PAGE_SIZE) {
+ data = squashfs_next_page(output);
+ pg_offset = 0;
+ }
+ avail = min_t(int, in, PAGE_SIZE -
+ pg_offset);
+ memcpy(data + pg_offset, bh[k]->b_data + offset,
+ avail);
+ in -= avail;
+ pg_offset += avail;
+ offset += avail;
+ }
+ offset = 0;
+ put_bh(bh[k]);
+ }
+ squashfs_finish_page(output);
}
-out_free_bio:
- bio_free_pages(bio);
- bio_put(bio);
-out:
- if (res < 0)
- ERROR("Failed to read block 0x%llx: %d\n", index, res);
+ kfree(bh);
+ return length;
- return res;
+block_release:
+ for (; k < b; k++)
+ put_bh(bh[k]);
+
+read_failure:
+ ERROR("squashfs_read_data failed to read block 0x%llx\n",
+ (unsigned long long) index);
+ kfree(bh);
+ return -EIO;
}
--- a/fs/squashfs/decompressor.h~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/decompressor.h
@@ -10,14 +10,13 @@
* decompressor.h
*/
-#include <linux/bio.h>
-
struct squashfs_decompressor {
void *(*init)(struct squashfs_sb_info *, void *);
void *(*comp_opts)(struct squashfs_sb_info *, void *, int);
void (*free)(void *);
int (*decompress)(struct squashfs_sb_info *, void *,
- struct bio *, int, int, struct squashfs_page_actor *);
+ struct buffer_head **, int, int, int,
+ struct squashfs_page_actor *);
int id;
char *name;
int supported;
--- a/fs/squashfs/decompressor_multi.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/decompressor_multi.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <linux/mutex.h>
#include <linux/slab.h>
-#include <linux/bio.h>
+#include <linux/buffer_head.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/cpumask.h>
@@ -180,15 +180,14 @@ wait:
}
-int squashfs_decompress(struct squashfs_sb_info *msblk, struct bio *bio,
- int offset, int length,
- struct squashfs_page_actor *output)
+int squashfs_decompress(struct squashfs_sb_info *msblk, struct buffer_head **bh,
+ int b, int offset, int length, struct squashfs_page_actor *output)
{
int res;
struct squashfs_stream *stream = msblk->stream;
struct decomp_stream *decomp_stream = get_decomp_stream(msblk, stream);
res = msblk->decompressor->decompress(msblk, decomp_stream->stream,
- bio, offset, length, output);
+ bh, b, offset, length, output);
put_decomp_stream(decomp_stream, stream);
if (res < 0)
ERROR("%s decompression failed, data probably corrupt\n",
--- a/fs/squashfs/decompressor_multi_percpu.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/decompressor_multi_percpu.c
@@ -75,8 +75,8 @@ void squashfs_decompressor_destroy(struc
}
}
-int squashfs_decompress(struct squashfs_sb_info *msblk, struct bio *bio,
- int offset, int length, struct squashfs_page_actor *output)
+int squashfs_decompress(struct squashfs_sb_info *msblk, struct buffer_head **bh,
+ int b, int offset, int length, struct squashfs_page_actor *output)
{
struct squashfs_stream *stream;
int res;
@@ -84,7 +84,7 @@ int squashfs_decompress(struct squashfs_
local_lock(&msblk->stream->lock);
stream = this_cpu_ptr(msblk->stream);
- res = msblk->decompressor->decompress(msblk, stream->stream, bio,
+ res = msblk->decompressor->decompress(msblk, stream->stream, bh, b,
offset, length, output);
local_unlock(&msblk->stream->lock);
--- a/fs/squashfs/decompressor_single.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/decompressor_single.c
@@ -7,7 +7,7 @@
#include <linux/types.h>
#include <linux/mutex.h>
#include <linux/slab.h>
-#include <linux/bio.h>
+#include <linux/buffer_head.h>
#include "squashfs_fs.h"
#include "squashfs_fs_sb.h"
@@ -59,15 +59,14 @@ void squashfs_decompressor_destroy(struc
}
}
-int squashfs_decompress(struct squashfs_sb_info *msblk, struct bio *bio,
- int offset, int length,
- struct squashfs_page_actor *output)
+int squashfs_decompress(struct squashfs_sb_info *msblk, struct buffer_head **bh,
+ int b, int offset, int length, struct squashfs_page_actor *output)
{
int res;
struct squashfs_stream *stream = msblk->stream;
mutex_lock(&stream->mutex);
- res = msblk->decompressor->decompress(msblk, stream->stream, bio,
+ res = msblk->decompressor->decompress(msblk, stream->stream, bh, b,
offset, length, output);
mutex_unlock(&stream->mutex);
--- a/fs/squashfs/lz4_wrapper.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/lz4_wrapper.c
@@ -4,7 +4,7 @@
* Phillip Lougher <phillip@squashfs.org.uk>
*/
-#include <linux/bio.h>
+#include <linux/buffer_head.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
@@ -89,23 +89,20 @@ static void lz4_free(void *strm)
static int lz4_uncompress(struct squashfs_sb_info *msblk, void *strm,
- struct bio *bio, int offset, int length,
+ struct buffer_head **bh, int b, int offset, int length,
struct squashfs_page_actor *output)
{
- struct bvec_iter_all iter_all = {};
- struct bio_vec *bvec = bvec_init_iter_all(&iter_all);
struct squashfs_lz4 *stream = strm;
void *buff = stream->input, *data;
- int bytes = length, res;
+ int avail, i, bytes = length, res;
- while (bio_next_segment(bio, &iter_all)) {
- int avail = min(bytes, ((int)bvec->bv_len) - offset);
-
- data = page_address(bvec->bv_page) + bvec->bv_offset;
- memcpy(buff, data + offset, avail);
+ for (i = 0; i < b; i++) {
+ avail = min(bytes, msblk->devblksize - offset);
+ memcpy(buff, bh[i]->b_data + offset, avail);
buff += avail;
bytes -= avail;
offset = 0;
+ put_bh(bh[i]);
}
res = LZ4_decompress_safe(stream->input, stream->output,
--- a/fs/squashfs/lzo_wrapper.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/lzo_wrapper.c
@@ -9,7 +9,7 @@
*/
#include <linux/mutex.h>
-#include <linux/bio.h>
+#include <linux/buffer_head.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/lzo.h>
@@ -63,24 +63,21 @@ static void lzo_free(void *strm)
static int lzo_uncompress(struct squashfs_sb_info *msblk, void *strm,
- struct bio *bio, int offset, int length,
+ struct buffer_head **bh, int b, int offset, int length,
struct squashfs_page_actor *output)
{
- struct bvec_iter_all iter_all = {};
- struct bio_vec *bvec = bvec_init_iter_all(&iter_all);
struct squashfs_lzo *stream = strm;
void *buff = stream->input, *data;
- int bytes = length, res;
+ int avail, i, bytes = length, res;
size_t out_len = output->length;
- while (bio_next_segment(bio, &iter_all)) {
- int avail = min(bytes, ((int)bvec->bv_len) - offset);
-
- data = page_address(bvec->bv_page) + bvec->bv_offset;
- memcpy(buff, data + offset, avail);
+ for (i = 0; i < b; i++) {
+ avail = min(bytes, msblk->devblksize - offset);
+ memcpy(buff, bh[i]->b_data + offset, avail);
buff += avail;
bytes -= avail;
offset = 0;
+ put_bh(bh[i]);
}
res = lzo1x_decompress_safe(stream->input, (size_t)length,
--- a/fs/squashfs/squashfs.h~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/squashfs.h
@@ -40,8 +40,8 @@ extern void *squashfs_decompressor_setup
/* decompressor_xxx.c */
extern void *squashfs_decompressor_create(struct squashfs_sb_info *, void *);
extern void squashfs_decompressor_destroy(struct squashfs_sb_info *);
-extern int squashfs_decompress(struct squashfs_sb_info *, struct bio *,
- int, int, struct squashfs_page_actor *);
+extern int squashfs_decompress(struct squashfs_sb_info *, struct buffer_head **,
+ int, int, int, struct squashfs_page_actor *);
extern int squashfs_max_decompressors(void);
/* export.c */
--- a/fs/squashfs/xz_wrapper.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/xz_wrapper.c
@@ -10,7 +10,7 @@
#include <linux/mutex.h>
-#include <linux/bio.h>
+#include <linux/buffer_head.h>
#include <linux/slab.h>
#include <linux/xz.h>
#include <linux/bitops.h>
@@ -117,12 +117,11 @@ static void squashfs_xz_free(void *strm)
static int squashfs_xz_uncompress(struct squashfs_sb_info *msblk, void *strm,
- struct bio *bio, int offset, int length,
+ struct buffer_head **bh, int b, int offset, int length,
struct squashfs_page_actor *output)
{
- struct bvec_iter_all iter_all = {};
- struct bio_vec *bvec = bvec_init_iter_all(&iter_all);
- int total = 0, error = 0;
+ enum xz_ret xz_err;
+ int avail, total = 0, k = 0;
struct squashfs_xz *stream = strm;
xz_dec_reset(stream->state);
@@ -132,23 +131,11 @@ static int squashfs_xz_uncompress(struct
stream->buf.out_size = PAGE_SIZE;
stream->buf.out = squashfs_first_page(output);
- for (;;) {
- enum xz_ret xz_err;
-
- if (stream->buf.in_pos == stream->buf.in_size) {
- const void *data;
- int avail;
-
- if (!bio_next_segment(bio, &iter_all)) {
- /* XZ_STREAM_END must be reached. */
- error = -EIO;
- break;
- }
-
- avail = min(length, ((int)bvec->bv_len) - offset);
- data = page_address(bvec->bv_page) + bvec->bv_offset;
+ do {
+ if (stream->buf.in_pos == stream->buf.in_size && k < b) {
+ avail = min(length, msblk->devblksize - offset);
length -= avail;
- stream->buf.in = data + offset;
+ stream->buf.in = bh[k]->b_data + offset;
stream->buf.in_size = avail;
stream->buf.in_pos = 0;
offset = 0;
@@ -163,17 +150,23 @@ static int squashfs_xz_uncompress(struct
}
xz_err = xz_dec_run(stream->state, &stream->buf);
- if (xz_err == XZ_STREAM_END)
- break;
- if (xz_err != XZ_OK) {
- error = -EIO;
- break;
- }
- }
+
+ if (stream->buf.in_pos == stream->buf.in_size && k < b)
+ put_bh(bh[k++]);
+ } while (xz_err == XZ_OK);
squashfs_finish_page(output);
- return error ? error : total + stream->buf.out_pos;
+ if (xz_err != XZ_STREAM_END || k < b)
+ goto out;
+
+ return total + stream->buf.out_pos;
+
+out:
+ for (; k < b; k++)
+ put_bh(bh[k]);
+
+ return -EIO;
}
const struct squashfs_decompressor squashfs_xz_comp_ops = {
--- a/fs/squashfs/zlib_wrapper.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/zlib_wrapper.c
@@ -10,7 +10,7 @@
#include <linux/mutex.h>
-#include <linux/bio.h>
+#include <linux/buffer_head.h>
#include <linux/slab.h>
#include <linux/zlib.h>
#include <linux/vmalloc.h>
@@ -50,35 +50,21 @@ static void zlib_free(void *strm)
static int zlib_uncompress(struct squashfs_sb_info *msblk, void *strm,
- struct bio *bio, int offset, int length,
+ struct buffer_head **bh, int b, int offset, int length,
struct squashfs_page_actor *output)
{
- struct bvec_iter_all iter_all = {};
- struct bio_vec *bvec = bvec_init_iter_all(&iter_all);
- int zlib_init = 0, error = 0;
+ int zlib_err, zlib_init = 0, k = 0;
z_stream *stream = strm;
stream->avail_out = PAGE_SIZE;
stream->next_out = squashfs_first_page(output);
stream->avail_in = 0;
- for (;;) {
- int zlib_err;
-
- if (stream->avail_in == 0) {
- const void *data;
- int avail;
-
- if (!bio_next_segment(bio, &iter_all)) {
- /* Z_STREAM_END must be reached. */
- error = -EIO;
- break;
- }
-
- avail = min(length, ((int)bvec->bv_len) - offset);
- data = page_address(bvec->bv_page) + bvec->bv_offset;
+ do {
+ if (stream->avail_in == 0 && k < b) {
+ int avail = min(length, msblk->devblksize - offset);
length -= avail;
- stream->next_in = data + offset;
+ stream->next_in = bh[k]->b_data + offset;
stream->avail_in = avail;
offset = 0;
}
@@ -92,28 +78,37 @@ static int zlib_uncompress(struct squash
if (!zlib_init) {
zlib_err = zlib_inflateInit(stream);
if (zlib_err != Z_OK) {
- error = -EIO;
- break;
+ squashfs_finish_page(output);
+ goto out;
}
zlib_init = 1;
}
zlib_err = zlib_inflate(stream, Z_SYNC_FLUSH);
- if (zlib_err == Z_STREAM_END)
- break;
- if (zlib_err != Z_OK) {
- error = -EIO;
- break;
- }
- }
+
+ if (stream->avail_in == 0 && k < b)
+ put_bh(bh[k++]);
+ } while (zlib_err == Z_OK);
squashfs_finish_page(output);
- if (!error)
- if (zlib_inflateEnd(stream) != Z_OK)
- error = -EIO;
+ if (zlib_err != Z_STREAM_END)
+ goto out;
+
+ zlib_err = zlib_inflateEnd(stream);
+ if (zlib_err != Z_OK)
+ goto out;
+
+ if (k < b)
+ goto out;
+
+ return stream->total_out;
+
+out:
+ for (; k < b; k++)
+ put_bh(bh[k]);
- return error ? error : stream->total_out;
+ return -EIO;
}
const struct squashfs_decompressor squashfs_zlib_comp_ops = {
--- a/fs/squashfs/zstd_wrapper.c~revert-squashfs-migrate-from-ll_rw_block-usage-to-bio
+++ a/fs/squashfs/zstd_wrapper.c
@@ -9,7 +9,7 @@
*/
#include <linux/mutex.h>
-#include <linux/bio.h>
+#include <linux/buffer_head.h>
#include <linux/slab.h>
#include <linux/zstd.h>
#include <linux/vmalloc.h>
@@ -59,44 +59,33 @@ static void zstd_free(void *strm)
static int zstd_uncompress(struct squashfs_sb_info *msblk, void *strm,
- struct bio *bio, int offset, int length,
+ struct buffer_head **bh, int b, int offset, int length,
struct squashfs_page_actor *output)
{
struct workspace *wksp = strm;
ZSTD_DStream *stream;
size_t total_out = 0;
- int error = 0;
+ size_t zstd_err;
+ int k = 0;
ZSTD_inBuffer in_buf = { NULL, 0, 0 };
ZSTD_outBuffer out_buf = { NULL, 0, 0 };
- struct bvec_iter_all iter_all = {};
- struct bio_vec *bvec = bvec_init_iter_all(&iter_all);
stream = ZSTD_initDStream(wksp->window_size, wksp->mem, wksp->mem_size);
if (!stream) {
ERROR("Failed to initialize zstd decompressor\n");
- return -EIO;
+ goto out;
}
out_buf.size = PAGE_SIZE;
out_buf.dst = squashfs_first_page(output);
- for (;;) {
- size_t zstd_err;
+ do {
+ if (in_buf.pos == in_buf.size && k < b) {
+ int avail = min(length, msblk->devblksize - offset);
- if (in_buf.pos == in_buf.size) {
- const void *data;
- int avail;
-
- if (!bio_next_segment(bio, &iter_all)) {
- error = -EIO;
- break;
- }
-
- avail = min(length, ((int)bvec->bv_len) - offset);
- data = page_address(bvec->bv_page) + bvec->bv_offset;
length -= avail;
- in_buf.src = data + offset;
+ in_buf.src = bh[k]->b_data + offset;
in_buf.size = avail;
in_buf.pos = 0;
offset = 0;
@@ -108,8 +97,8 @@ static int zstd_uncompress(struct squash
/* Shouldn't run out of pages
* before stream is done.
*/
- error = -EIO;
- break;
+ squashfs_finish_page(output);
+ goto out;
}
out_buf.pos = 0;
out_buf.size = PAGE_SIZE;
@@ -118,20 +107,29 @@ static int zstd_uncompress(struct squash
total_out -= out_buf.pos;
zstd_err = ZSTD_decompressStream(stream, &out_buf, &in_buf);
total_out += out_buf.pos; /* add the additional data produced */
- if (zstd_err == 0)
- break;
- if (ZSTD_isError(zstd_err)) {
- ERROR("zstd decompression error: %d\n",
- (int)ZSTD_getErrorCode(zstd_err));
- error = -EIO;
- break;
- }
- }
+ if (in_buf.pos == in_buf.size && k < b)
+ put_bh(bh[k++]);
+ } while (zstd_err != 0 && !ZSTD_isError(zstd_err));
squashfs_finish_page(output);
- return error ? error : total_out;
+ if (ZSTD_isError(zstd_err)) {
+ ERROR("zstd decompression error: %d\n",
+ (int)ZSTD_getErrorCode(zstd_err));
+ goto out;
+ }
+
+ if (k < b)
+ goto out;
+
+ return (int)total_out;
+
+out:
+ for (; k < b; k++)
+ put_bh(bh[k]);
+
+ return -EIO;
}
const struct squashfs_decompressor squashfs_zstd_comp_ops = {
_
Patches currently in -mm which might be from akpm@linux-foundation.org are
mm-close-race-between-munmap-and-expand_upwards-downwards-fix.patch
revert-squashfs-migrate-from-ll_rw_block-usage-to-bio.patch
mm.patch
mm-handle-page-mapping-better-in-dump_page-fix.patch
mm-memcg-percpu-account-percpu-memory-to-memory-cgroups-fix.patch
mm-memcg-percpu-account-percpu-memory-to-memory-cgroups-fix-fix.patch
mm-thp-replace-http-links-with-https-ones-fix.patch
mm-vmstat-add-events-for-thp-migration-without-split-fix.patch
linux-next-rejects.patch
linux-next-git-rejects.patch
mm-migrate-clear-__gfp_reclaim-to-make-the-migration-callback-consistent-with-regular-thp-allocations-fix.patch
mm-madvise-introduce-process_madvise-syscall-an-external-memory-hinting-api-fix.patch
mm-madvise-introduce-process_madvise-syscall-an-external-memory-hinting-api-fix-2.patch
kernel-forkc-export-kernel_thread-to-modules.patch
^ permalink raw reply
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Remaining RKL patches (rev7)
From: Patchwork @ 2020-07-17 1:53 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
In-Reply-To: <20200716220551.2730644-1-matthew.d.roper@intel.com>
[-- Attachment #1.1: Type: text/plain, Size: 17122 bytes --]
== Series Details ==
Series: Remaining RKL patches (rev7)
URL : https://patchwork.freedesktop.org/series/77971/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8758_full -> Patchwork_18197_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18197_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18197_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18197_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s3:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl6/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl2/igt@gem_exec_suspend@basic-s3.html
Known issues
------------
Here are the changes found in Patchwork_18197_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_userptr_blits@invalid-mmap-offset-unsync@gtt:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([i915#2119])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-iclb1/igt@gem_userptr_blits@invalid-mmap-offset-unsync@gtt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-iclb8/igt@gem_userptr_blits@invalid-mmap-offset-unsync@gtt.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [PASS][5] -> [WARN][6] ([i915#1519])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-hsw2/igt@i915_pm_rc6_residency@rc6-idle.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-hsw1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@mock@requests:
- shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([i915#2110])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-hsw7/igt@i915_selftest@mock@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-hsw6/igt@i915_selftest@mock@requests.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-180:
- shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-glk4/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
* igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#177] / [i915#52] / [i915#54])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl2/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl9/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html
* igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-hsw1/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-hsw6/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#2122])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +5 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#53])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl9/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-iclb7/igt@kms_psr@psr2_sprite_render.html
* igt@kms_vblank@crtc-id:
- shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +7 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl8/igt@kms_vblank@crtc-id.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl1/igt@kms_vblank@crtc-id.html
* igt@kms_vblank@pipe-a-query-forked-busy:
- shard-tglb: [PASS][33] -> [DMESG-WARN][34] ([i915#402]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-tglb1/igt@kms_vblank@pipe-a-query-forked-busy.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-tglb5/igt@kms_vblank@pipe-a-query-forked-busy.html
* igt@kms_vblank@pipe-c-wait-busy-hang:
- shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#1635] / [i915#1982]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-apl7/igt@kms_vblank@pipe-c-wait-busy-hang.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-apl4/igt@kms_vblank@pipe-c-wait-busy-hang.html
#### Possible fixes ####
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-glk9/igt@gem_exec_whisper@basic-contexts-forked-all.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@i915_pm_rpm@i2c:
- shard-skl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +8 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl9/igt@i915_pm_rpm@i2c.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl5/igt@i915_pm_rpm@i2c.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-glk3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [INCOMPLETE][43] ([i915#300]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-snb: [TIMEOUT][45] ([i915#1958] / [i915#2119]) -> [PASS][46] +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-snb5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-snb5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions:
- shard-kbl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-kbl4/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-kbl6/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
- shard-apl: [DMESG-WARN][49] ([i915#1635] / [i915#1982]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-apl8/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-apl2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-tglb5/igt@kms_frontbuffer_tracking@psr-slowdraw.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-tglb2/igt@kms_frontbuffer_tracking@psr-slowdraw.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][55] ([i915#31]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-kbl3/igt@kms_setmode@basic.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-kbl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@blocking-parameterized:
- shard-tglb: [FAIL][59] ([i915#1542]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-tglb3/igt@perf@blocking-parameterized.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-tglb2/igt@perf@blocking-parameterized.html
* igt@perf_pmu@busy-idle@rcs0:
- shard-snb: [FAIL][61] ([i915#1958]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-snb5/igt@perf_pmu@busy-idle@rcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-snb5/igt@perf_pmu@busy-idle@rcs0.html
* igt@perf_pmu@busy-idle@vcs0:
- shard-snb: [INCOMPLETE][63] ([i915#2119] / [i915#82]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-snb5/igt@perf_pmu@busy-idle@vcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-snb5/igt@perf_pmu@busy-idle@vcs0.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-snb: [TIMEOUT][65] ([i915#1958] / [i915#2119]) -> [FAIL][66] ([i915#1930])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-snb5/igt@gem_exec_reloc@basic-concurrent16.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-snb5/igt@gem_exec_reloc@basic-concurrent16.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo:
- shard-snb: [TIMEOUT][67] ([i915#1958] / [i915#2119]) -> [SKIP][68] ([fdo#109271]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-snb5/igt@kms_ccs@pipe-c-ccs-on-another-bo.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-snb5/igt@kms_ccs@pipe-c-ccs-on-another-bo.html
* igt@runner@aborted:
- shard-hsw: [FAIL][69] ([i915#2110]) -> [FAIL][70] ([i915#1436] / [i915#2110])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-hsw1/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-hsw6/igt@runner@aborted.html
- shard-apl: ([FAIL][71], [FAIL][72], [FAIL][73]) ([i915#1610] / [i915#1635] / [i915#2110] / [i915#637]) -> [FAIL][74] ([i915#1635] / [i915#2110])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-apl8/igt@runner@aborted.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-apl1/igt@runner@aborted.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8758/shard-apl8/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/shard-apl7/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
[i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#637]: https://gitlab.freedesktop.org/drm/intel/issues/637
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8758 -> Patchwork_18197
CI-20190529: 20190529
CI_DRM_8758: b6738761bde03de00a1c84c6a85f9379f53f585c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5738: bc8b56fe177af34fbde7b96f1f66614a0014c6ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18197: dfcce2d96955e0636baa8270decdc53ec3519ab2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18197/index.html
[-- Attachment #1.2: Type: text/html, Size: 20528 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [PATCH 07/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3368 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 34 ++++++++++++++++++------------
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 71335ed003b3..8e3fa9011165 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1987,6 +1987,9 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
+#define RK3368_PULL_BITS_PER_PIN 2
+#define RK3368_PULL_PINS_PER_REG 8
+#define RK3368_PULL_BANK_STRIDE 16
static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1999,25 +2002,28 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3368_PULL_PINS_PER_REG;
+ *bit *= RK3368_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3368_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3368_PULL_PINS_PER_REG);
+ *bit *= RK3368_PULL_BITS_PER_PIN;
}
}
#define RK3368_DRV_PMU_OFFSET 0x20
#define RK3368_DRV_GRF_OFFSET 0x200
+#define RK3368_DRV_BITS_PER_PIN 2
+#define RK3368_DRV_PINS_PER_REG 8
+#define RK3368_DRV_BANK_STRIDE 16
static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2030,20 +2036,20 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
- *bit = pin_num % RK3288_DRV_PINS_PER_REG;
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3368_DRV_PINS_PER_REG;
+ *bit *= RK3368_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3368_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *bit = (pin_num % RK3368_DRV_PINS_PER_REG);
+ *bit *= RK3368_DRV_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* Re: [PATCH V3 10/10] nvmet: use xarray for ctrl ns storing
From: Chaitanya Kulkarni @ 2020-07-17 1:52 UTC (permalink / raw)
To: Christoph Hellwig, willy@infradead.org
Cc: kbusch@kernel.org, sagi@grimberg.me,
linux-nvme@lists.infradead.org
In-Reply-To: <20200715071027.GB22320@lst.de>
On 7/15/20 00:10, Christoph Hellwig wrote:
>> index 9cdc39c8b729..2908acc7b1e2 100644
>> --- a/drivers/nvme/target/core.c
>> +++ b/drivers/nvme/target/core.c
>> @@ -115,13 +115,14 @@ u16 nvmet_zero_sgl(struct nvmet_req *req, off_t off, size_t len)
>>
>> static unsigned int nvmet_max_nsid(struct nvmet_subsys *subsys)
>> {
>> - struct nvmet_ns *ns;
>> + unsigned long nsid = 0;
>> + struct nvmet_ns *cur;
>> + unsigned long idx;
>>
>> - if (list_empty(&subsys->namespaces))
>> - return 0;
>> + xa_for_each(&subsys->namespaces, idx, cur)
>> + nsid = cur->nsid;
>>
>> - ns = list_last_entry(&subsys->namespaces, struct nvmet_ns, dev_link);
>> - return ns->nsid;
>> + return nsid;
>> }
>
> If Matthew wants to add a helper to return the highest id for an xarray
> this would be the place to use it.
>
Matthew, any suggestions on how to add a helper for above use case ?
we want to get the highest possible available index for in the XArray.
>
>> + ret = xa_insert(&subsys->namespaces, ns->nsid, ns, GFP_KERNEL);
>> + if (ret)
>> + goto out_dev_put;
>
Christoph,
> I don't think out_dev_put is enough here as that fails to tear down
> ns->ref.
>
Yes the call to percpu_ref_exit() is missing here, also it needs to
restore the subsys->max_nsid when xa_insert() fails (correct me if I'm
wrong), will add it to V4.
_______________________________________________
Linux-nvme mailing list
Linux-nvme@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-nvme
^ permalink raw reply
* [f2fs-dev] [PATCH v3 7/7] fscrypt: update documentation for direct I/O support
From: Satya Tangirala via Linux-f2fs-devel @ 2020-07-17 1:45 UTC (permalink / raw)
To: linux-fscrypt, linux-fsdevel, linux-f2fs-devel, linux-ext4
Cc: linux-xfs, Satya Tangirala
In-Reply-To: <20200717014540.71515-1-satyat@google.com>
Update fscrypt documentation to reflect the addition of direct I/O support
and document the necessary conditions for direct I/O on encrypted files.
Signed-off-by: Satya Tangirala <satyat@google.com>
---
Documentation/filesystems/fscrypt.rst | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/Documentation/filesystems/fscrypt.rst b/Documentation/filesystems/fscrypt.rst
index f3d87a1a0a7f..95c76a5f0567 100644
--- a/Documentation/filesystems/fscrypt.rst
+++ b/Documentation/filesystems/fscrypt.rst
@@ -1049,8 +1049,10 @@ astute users may notice some differences in behavior:
may be used to overwrite the source files but isn't guaranteed to be
effective on all filesystems and storage devices.
-- Direct I/O is not supported on encrypted files. Attempts to use
- direct I/O on such files will fall back to buffered I/O.
+- Direct I/O is supported on encrypted files only under some circumstances
+ (see `Direct I/O support`_ for details). When these circumstances are not
+ met, attempts to use direct I/O on such files will fall back to buffered
+ I/O.
- The fallocate operations FALLOC_FL_COLLAPSE_RANGE and
FALLOC_FL_INSERT_RANGE are not supported on encrypted files and will
@@ -1257,6 +1259,20 @@ without the key is subject to change in the future. It is only meant
as a way to temporarily present valid filenames so that commands like
``rm -r`` work as expected on encrypted directories.
+Direct I/O support
+------------------
+
+Direct I/O on encrypted files is supported through blk-crypto. In
+particular, this means the kernel must have CONFIG_BLK_INLINE_ENCRYPTION
+enabled, the filesystem must have had the 'inlinecrypt' mount option
+specified, and either hardware inline encryption must be present, or
+CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK must have been enabled. Further,
+any I/O must be aligned to the filesystem block size (*not* necessarily
+the same as the block device's block size) - in particular, any userspace
+buffer into which data is read/written from must also be aligned to the
+filesystem block size. If any of these conditions isn't met, attempts to do
+direct I/O on an encrypted file will fall back to buffered I/O.
+
Tests
=====
--
2.28.0.rc0.105.gf9edc3c819-goog
_______________________________________________
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Linux-f2fs-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/linux-f2fs-devel
^ permalink raw reply related
* [f2fs-dev] [PATCH v3 3/7] iomap: support direct I/O with fscrypt using blk-crypto
From: Satya Tangirala via Linux-f2fs-devel @ 2020-07-17 1:45 UTC (permalink / raw)
To: linux-fscrypt, linux-fsdevel, linux-f2fs-devel, linux-ext4
Cc: linux-xfs, Satya Tangirala, Eric Biggers
In-Reply-To: <20200717014540.71515-1-satyat@google.com>
From: Eric Biggers <ebiggers@google.com>
Wire up iomap direct I/O with the fscrypt additions for direct I/O,
and set bio crypt contexts on bios when appropriate.
Make iomap_dio_bio_actor() call fscrypt_limit_io_pages() to ensure that
DUNs remain contiguous within a bio, since it works directly with logical
ranges and can't call fscrypt_mergeable_bio() on each page.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Co-developed-by: Satya Tangirala <satyat@google.com>
Signed-off-by: Satya Tangirala <satyat@google.com>
---
fs/iomap/direct-io.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/fs/iomap/direct-io.c b/fs/iomap/direct-io.c
index ec7b78e6feca..4507dc16dbe5 100644
--- a/fs/iomap/direct-io.c
+++ b/fs/iomap/direct-io.c
@@ -6,6 +6,7 @@
#include <linux/module.h>
#include <linux/compiler.h>
#include <linux/fs.h>
+#include <linux/fscrypt.h>
#include <linux/iomap.h>
#include <linux/backing-dev.h>
#include <linux/uio.h>
@@ -183,11 +184,14 @@ static void
iomap_dio_zero(struct iomap_dio *dio, struct iomap *iomap, loff_t pos,
unsigned len)
{
+ struct inode *inode = file_inode(dio->iocb->ki_filp);
struct page *page = ZERO_PAGE(0);
int flags = REQ_SYNC | REQ_IDLE;
struct bio *bio;
bio = bio_alloc(GFP_KERNEL, 1);
+ fscrypt_set_bio_crypt_ctx(bio, inode, pos >> inode->i_blkbits,
+ GFP_KERNEL);
bio_set_dev(bio, iomap->bdev);
bio->bi_iter.bi_sector = iomap_sector(iomap, pos);
bio->bi_private = dio;
@@ -253,6 +257,7 @@ iomap_dio_bio_actor(struct inode *inode, loff_t pos, loff_t length,
ret = nr_pages;
goto out;
}
+ nr_pages = fscrypt_limit_io_pages(inode, pos, nr_pages);
if (need_zeroout) {
/* zero out from the start of the block to the write offset */
@@ -270,6 +275,8 @@ iomap_dio_bio_actor(struct inode *inode, loff_t pos, loff_t length,
}
bio = bio_alloc(GFP_KERNEL, nr_pages);
+ fscrypt_set_bio_crypt_ctx(bio, inode, pos >> inode->i_blkbits,
+ GFP_KERNEL);
bio_set_dev(bio, iomap->bdev);
bio->bi_iter.bi_sector = iomap_sector(iomap, pos);
bio->bi_write_hint = dio->iocb->ki_hint;
@@ -307,6 +314,7 @@ iomap_dio_bio_actor(struct inode *inode, loff_t pos, loff_t length,
copied += n;
nr_pages = iov_iter_npages(dio->submit.iter, BIO_MAX_PAGES);
+ nr_pages = fscrypt_limit_io_pages(inode, pos, nr_pages);
iomap_dio_submit_bio(dio, iomap, bio, pos);
pos += n;
} while (nr_pages);
--
2.28.0.rc0.105.gf9edc3c819-goog
_______________________________________________
Linux-f2fs-devel mailing list
Linux-f2fs-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/linux-f2fs-devel
^ permalink raw reply related
* Re: [PATCH] ASoC: meson: add the missed kfree() for axg_card_add_tdm_loopback
From: Jing Xiangfeng @ 2020-07-17 1:49 UTC (permalink / raw)
To: Jerome Brunet, lgirdwood, broonie, perex, tiwai, khilman,
kuninori.morimoto.gx
Cc: linux-amlogic, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <1jzh7zegfw.fsf@starbuckisacylon.baylibre.com>
On 2020/7/16 21:29, Jerome Brunet wrote:
>
> On Thu 16 Jul 2020 at 15:25, Jing Xiangfeng <jingxiangfeng@huawei.com> wrote:
>
>> axg_card_add_tdm_loopback() misses to call kfree() in an error path. Add
>> the missed function call to fix it.
>>
>> Fixes: c84836d7f650 ("ASoC: meson: axg-card: use modern dai_link style")
>> Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com>
>
> Thanks for fixing this.
> Maybe it would be better to use the devm_ variant for the name instead ?
Ok, I'll send a v2 with this change.
Thanks for your review.
>
>> ---
>> sound/soc/meson/axg-card.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/sound/soc/meson/axg-card.c b/sound/soc/meson/axg-card.c
>> index 89f7f64747cd..6eac22ba8b99 100644
>> --- a/sound/soc/meson/axg-card.c
>> +++ b/sound/soc/meson/axg-card.c
>> @@ -121,8 +121,10 @@ static int axg_card_add_tdm_loopback(struct snd_soc_card *card,
>> return -ENOMEM;
>>
>> dlc = devm_kzalloc(card->dev, 2 * sizeof(*dlc), GFP_KERNEL);
>> - if (!dlc)
>> + if (!dlc) {
>> + kfree(lb->name);
>> return -ENOMEM;
>> + }
>>
>> lb->cpus = &dlc[0];
>> lb->codecs = &dlc[1];
>
> .
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] ASoC: meson: add the missed kfree() for axg_card_add_tdm_loopback
From: Jing Xiangfeng @ 2020-07-17 1:49 UTC (permalink / raw)
To: Jerome Brunet, lgirdwood, broonie, perex, tiwai, khilman,
kuninori.morimoto.gx
Cc: linux-amlogic, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <1jzh7zegfw.fsf@starbuckisacylon.baylibre.com>
On 2020/7/16 21:29, Jerome Brunet wrote:
>
> On Thu 16 Jul 2020 at 15:25, Jing Xiangfeng <jingxiangfeng@huawei.com> wrote:
>
>> axg_card_add_tdm_loopback() misses to call kfree() in an error path. Add
>> the missed function call to fix it.
>>
>> Fixes: c84836d7f650 ("ASoC: meson: axg-card: use modern dai_link style")
>> Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com>
>
> Thanks for fixing this.
> Maybe it would be better to use the devm_ variant for the name instead ?
Ok, I'll send a v2 with this change.
Thanks for your review.
>
>> ---
>> sound/soc/meson/axg-card.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/sound/soc/meson/axg-card.c b/sound/soc/meson/axg-card.c
>> index 89f7f64747cd..6eac22ba8b99 100644
>> --- a/sound/soc/meson/axg-card.c
>> +++ b/sound/soc/meson/axg-card.c
>> @@ -121,8 +121,10 @@ static int axg_card_add_tdm_loopback(struct snd_soc_card *card,
>> return -ENOMEM;
>>
>> dlc = devm_kzalloc(card->dev, 2 * sizeof(*dlc), GFP_KERNEL);
>> - if (!dlc)
>> + if (!dlc) {
>> + kfree(lb->name);
>> return -ENOMEM;
>> + }
>>
>> lb->cpus = &dlc[0];
>> lb->codecs = &dlc[1];
>
> .
>
^ permalink raw reply
* RE: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support
From: Alim Akhtar @ 2020-07-16 16:45 UTC (permalink / raw)
To: 'Avi Shchislowski', 'Bart Van Assche',
daejun7.park, 'Avri Altman', jejb, martin.petersen,
asutoshd, beanhuo, stanley.chu, cang, tomas.winkler
Cc: linux-scsi, linux-kernel, 'Sang-yoon Oh',
'Sung-Jun Park', 'yongmyung lee',
'Jinyoung CHOI', 'Adel Choi',
'BoRam Shin'
In-Reply-To: <SN6PR04MB3872FBE1EAE3578BFD2601189A7F0@SN6PR04MB3872.namprd04.prod.outlook.com>
Hi Avi,
> -----Original Message-----
> From: Avi Shchislowski <Avi.Shchislowski@wdc.com>
> Sent: 16 July 2020 15:31
> To: Bart Van Assche <bvanassche@acm.org>; daejun7.park@samsung.com; Avri
> Altman <Avri.Altman@wdc.com>; jejb@linux.ibm.com;
> martin.petersen@oracle.com; asutoshd@codeaurora.org;
> beanhuo@micron.com; stanley.chu@mediatek.com; cang@codeaurora.org;
> tomas.winkler@intel.com; ALIM AKHTAR <alim.akhtar@samsung.com>
> Cc: linux-scsi@vger.kernel.org; linux-kernel@vger.kernel.org; Sang-yoon Oh
> <sangyoon.oh@samsung.com>; Sung-Jun Park
> <sungjun07.park@samsung.com>; yongmyung lee
> <ymhungry.lee@samsung.com>; Jinyoung CHOI <j-young.choi@samsung.com>;
> Adel Choi <adel.choi@samsung.com>; BoRam Shin
> <boram.shin@samsung.com>
> Subject: RE: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support
>
>
>
> > -----Original Message-----
> > From: Bart Van Assche <bvanassche@acm.org>
> > Sent: Thursday, July 16, 2020 4:42 AM
> > To: Avi Shchislowski <Avi.Shchislowski@wdc.com>;
> > daejun7.park@samsung.com; Avri Altman <Avri.Altman@wdc.com>;
> > jejb@linux.ibm.com; martin.petersen@oracle.com;
> > asutoshd@codeaurora.org; beanhuo@micron.com;
> stanley.chu@mediatek.com;
> > cang@codeaurora.org; tomas.winkler@intel.com; ALIM AKHTAR
> > <alim.akhtar@samsung.com>
> > Cc: linux-scsi@vger.kernel.org; linux-kernel@vger.kernel.org;
> > Sang-yoon Oh <sangyoon.oh@samsung.com>; Sung-Jun Park
> > <sungjun07.park@samsung.com>; yongmyung lee
> > <ymhungry.lee@samsung.com>; Jinyoung CHOI <j-
> young.choi@samsung.com>;
> > Adel Choi <adel.choi@samsung.com>; BoRam Shin
> <boram.shin@samsung.com>
> > Subject: Re: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster
> > Support
> >
> > CAUTION: This email originated from outside of Western Digital. Do not
> > click on links or open attachments unless you recognize the sender and
> > know that the content is safe.
> >
> >
> > On 2020-07-15 11:34, Avi Shchislowski wrote:
> > > My name is Avi Shchislowski, I am managing the WDC's Linux Host R&D
> > > team
> > in which Avri is a member of.
> > > As the review process of HPB is progressing very constructively, we
> > > are getting
> > more and more requests from OEMs, Inquiring about HPB in general, and
> > host control mode in particular.
> > >
> > > Their main concern is that HPB will make it to 5.9 merge window, but
> > > the host
> > control mode patches will not.
> > > Thus, because of recent Google's GKI, the next Android LTS might not
> > > include
> > HPB with host control mode.
> > >
> > > Aside of those requests, initial host control mode testing are
> > > showing
> > promising prospective with respect of performance gain.
> > >
> > > What would be, in your opinion, the best policy that host control
> > > mode is
> > included in next Android LTS?
> >
> > Hi Avi,
> >
> > Are you perhaps referring to the HPB patch series that has already been
> posted?
> > Although I'm not sure of this, I think that the SCSI maintainer
> > expects more
> > Reviewed-by: and Tested-by: tags. Has anyone from WDC already taken
> > the time to review and/or test this patch series?
> >
> > Thanks,
> >
> > Bart.
>
> Yes, I am referring to the current proposal which I am replying to:
> [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support This proposal
> does not contains host mode, hence our customers concern.
> What would be, in your opinion, the best policy that host control mode is
> included in next Android LTS assuming it will be based on kernel v5.9 ?
>
This series has nothing to do with Host mode control, this series is targeted for device mode control. General consensus here is to land this series as it is (unless someone has more review comments) and lets add/enhance whatever need to be done for adding Host mode controls as well as other HPB2.0 related changes.
> Thanks,
> Avi
^ permalink raw reply
* [PATCH v13 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC
From: Alim Akhtar @ 2020-07-16 19:22 UTC (permalink / raw)
To: vkoul
Cc: devicetree, linux-samsung-soc, linux-kernel, krzk,
Kishon Vijay Abraham I, robh+dt, Alim Akhtar, linux-arm-kernel
In-Reply-To: <20200716192217.35740-1-alim.akhtar@samsung.com>
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
[Robot: -Wmissing-prototypes and -Wsometimes-uninitialized]
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Kiwoong Kim <kwmad.kim@samsung.com>
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Vinod Koul <vkoul@kernel.org>
Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
- Changes V12 -> V13
* Addressed more review comments from Vinod [1]
[1] https://lkml.org/lkml/2020/7/13/99
- Changes V11 -> V12
* Fixed kernel test robot warnings
- Changes V10 -> V11
* Addressed review comments from Vinod
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 81 ++++++
drivers/phy/samsung/phy-samsung-ufs.c | 366 ++++++++++++++++++++++++++
drivers/phy/samsung/phy-samsung-ufs.h | 139 ++++++++++
5 files changed, 596 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 19f2e3119343..e20d2fcc9fe7 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index 000000000000..518923141958
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
+ [CFG_PRE_INIT] = exynos7_pre_init_cfg,
+ [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
+ [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
+};
+
+static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
+ .cfg = exynos7_ufs_phy_cfgs,
+ .isol = {
+ .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
+ .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
+ .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
+ },
+ .has_symbol_clk = 1,
+};
+
+#endif /* _PHY_EXYNOS7_UFS_H_ */
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
new file mode 100644
index 000000000000..43ef77d1d96c
--- /dev/null
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver for Samsung SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <essuuj@gmail.com>
+ * Author: Alim Akhtar <alim.akhtar@samsung.com>
+ *
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "phy-samsung-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
+ const struct samsung_ufs_phy_cfg *cfg,
+ u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ const unsigned int timeout_us = 100000;
+ const unsigned int sleep_us = 10;
+ u32 val;
+ int err;
+
+ err = readl_poll_timeout(
+ ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
+ val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
+ if (err) {
+ dev_err(ufs_phy->dev,
+ "failed to get phy pll lock acquisition %d\n", err);
+ goto out;
+ }
+
+ err = readl_poll_timeout(
+ ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+ val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
+ if (err)
+ dev_err(ufs_phy->dev,
+ "failed to get phy cdr lock acquisition %d\n", err);
+out:
+ return err;
+}
+
+static int samsung_ufs_phy_calibrate(struct phy *phy)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct samsung_ufs_phy_cfg *cfg;
+ int err = 0;
+ int i;
+
+ if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
+ ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state);
+ return -EINVAL;
+ }
+
+ cfg = cfgs[ufs_phy->ufs_phy_state];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ samsung_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+ if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
+ err = samsung_ufs_phy_wait_for_lock_acq(phy);
+
+ /**
+ * In Samsung ufshci, PHY need to be calibrated at different
+ * stages / state mainly before Linkstartup, after Linkstartup,
+ * before power mode change and after power mode change.
+ * Below state machine to make sure to calibrate PHY in each
+ * state. Here after configuring PHY in a given state, will
+ * change the state to next state so that next state phy
+ * calibration value can be programed
+ */
+out:
+ switch (ufs_phy->ufs_phy_state) {
+ case CFG_PRE_INIT:
+ ufs_phy->ufs_phy_state = CFG_POST_INIT;
+ break;
+ case CFG_POST_INIT:
+ ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
+ break;
+ case CFG_PRE_PWR_HS:
+ ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
+ break;
+ case CFG_POST_PWR_HS:
+ /* Change back to INIT state */
+ ufs_phy->ufs_phy_state = CFG_PRE_INIT;
+ break;
+ default:
+ dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
+ }
+
+ return err;
+}
+
+static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy)
+{
+ int ret;
+
+ phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
+ if (IS_ERR(phy->tx0_symbol_clk)) {
+ dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
+ return PTR_ERR(phy->tx0_symbol_clk);
+ }
+
+ phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
+ if (IS_ERR(phy->rx0_symbol_clk)) {
+ dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
+ return PTR_ERR(phy->rx0_symbol_clk);
+ }
+
+ phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
+ if (IS_ERR(phy->rx0_symbol_clk)) {
+ dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
+ return PTR_ERR(phy->rx1_symbol_clk);
+ }
+
+ ret = clk_prepare_enable(phy->tx0_symbol_clk);
+ if (ret) {
+ dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", __func__, ret);
+ goto out;
+ }
+
+ ret = clk_prepare_enable(phy->rx0_symbol_clk);
+ if (ret) {
+ dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", __func__, ret);
+ goto out_disable_tx0_clk;
+ }
+
+ ret = clk_prepare_enable(phy->rx1_symbol_clk);
+ if (ret) {
+ dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", __func__, ret);
+ goto out_disable_rx0_clk;
+ }
+
+ return 0;
+
+out_disable_rx0_clk:
+ clk_disable_unprepare(phy->rx0_symbol_clk);
+out_disable_tx0_clk:
+ clk_disable_unprepare(phy->tx0_symbol_clk);
+out:
+ return ret;
+}
+
+static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
+{
+ int ret;
+
+ phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
+ if (IS_ERR(phy->ref_clk))
+ dev_err(phy->dev, "failed to get ref_clk clock\n");
+
+ ret = clk_prepare_enable(phy->ref_clk);
+ if (ret) {
+ dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, ret);
+ return ret;
+ }
+
+ dev_dbg(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", clk_get_rate(phy->ref_clk));
+
+ return 0;
+}
+
+static int samsung_ufs_phy_init(struct phy *phy)
+{
+ struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
+ int ret;
+
+ ss_phy->lane_cnt = phy->attrs.bus_width;
+ ss_phy->ufs_phy_state = CFG_PRE_INIT;
+
+ if (ss_phy->drvdata->has_symbol_clk) {
+ ret = samsung_ufs_phy_symbol_clk_init(ss_phy);
+ if (ret)
+ dev_err(ss_phy->dev, "failed to set ufs phy symbol clocks\n");
+ }
+
+ ret = samsung_ufs_phy_clks_init(ss_phy);
+ if (ret)
+ dev_err(ss_phy->dev, "failed to set ufs phy clocks\n");
+
+ ret = samsung_ufs_phy_calibrate(phy);
+ if (ret)
+ dev_err(ss_phy->dev, "ufs phy calibration failed\n");
+
+ return ret;
+}
+
+static int samsung_ufs_phy_power_on(struct phy *phy)
+{
+ struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
+
+ samsung_ufs_phy_ctrl_isol(ss_phy, false);
+ return 0;
+}
+
+static int samsung_ufs_phy_power_off(struct phy *phy)
+{
+ struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
+
+ samsung_ufs_phy_ctrl_isol(ss_phy, true);
+ return 0;
+}
+
+static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
+ enum phy_mode mode, int submode)
+{
+ struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(generic_phy);
+
+ ss_phy->mode = PHY_MODE_INVALID;
+
+ if (mode > 0)
+ ss_phy->mode = mode;
+
+ return 0;
+}
+
+static int samsung_ufs_phy_exit(struct phy *phy)
+{
+ struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
+
+ clk_disable_unprepare(ss_phy->ref_clk);
+
+ if (ss_phy->drvdata->has_symbol_clk) {
+ clk_disable_unprepare(ss_phy->tx0_symbol_clk);
+ clk_disable_unprepare(ss_phy->rx0_symbol_clk);
+ clk_disable_unprepare(ss_phy->rx1_symbol_clk);
+ }
+
+ return 0;
+}
+
+static struct phy_ops samsung_ufs_phy_ops = {
+ .init = samsung_ufs_phy_init,
+ .exit = samsung_ufs_phy_exit,
+ .power_on = samsung_ufs_phy_power_on,
+ .power_off = samsung_ufs_phy_power_off,
+ .calibrate = samsung_ufs_phy_calibrate,
+ .set_mode = samsung_ufs_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id samsung_ufs_phy_match[];
+
+static int samsung_ufs_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *match;
+ struct samsung_ufs_phy *phy;
+ struct phy *gen_phy;
+ struct phy_provider *phy_provider;
+ const struct samsung_ufs_phy_drvdata *drvdata;
+ int err = 0;
+
+ match = of_match_node(samsung_ufs_phy_match, dev->of_node);
+ if (!match) {
+ err = -EINVAL;
+ dev_err(dev, "failed to get match_node\n");
+ goto out;
+ }
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma");
+ if (IS_ERR(phy->reg_pma)) {
+ err = PTR_ERR(phy->reg_pma);
+ goto out;
+ }
+
+ phy->reg_pmu = syscon_regmap_lookup_by_phandle(
+ dev->of_node, "samsung,pmu-syscon");
+ if (IS_ERR(phy->reg_pmu)) {
+ err = PTR_ERR(phy->reg_pmu);
+ dev_err(dev, "failed syscon remap for pmu\n");
+ goto out;
+ }
+
+ gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
+ if (IS_ERR(gen_phy)) {
+ err = PTR_ERR(gen_phy);
+ dev_err(dev, "failed to create PHY for ufs-phy\n");
+ goto out;
+ }
+
+ drvdata = match->data;
+ phy->dev = dev;
+ phy->drvdata = drvdata;
+ phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
+ phy->isol = &drvdata->isol;
+ phy->lane_cnt = PHY_DEF_LANE_CNT;
+
+ phy_set_drvdata(gen_phy, phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
+ err = PTR_ERR(phy_provider);
+ dev_err(dev, "failed to register phy-provider\n");
+ goto out;
+ }
+out:
+ return err;
+}
+
+static const struct of_device_id samsung_ufs_phy_match[] = {
+ {
+ .compatible = "samsung,exynos7-ufs-phy",
+ .data = &exynos7_ufs_phy,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
+
+static struct platform_driver samsung_ufs_phy_driver = {
+ .probe = samsung_ufs_phy_probe,
+ .driver = {
+ .name = "samsung-ufs-phy",
+ .of_match_table = samsung_ufs_phy_match,
+ },
+};
+module_platform_driver(samsung_ufs_phy_driver);
+MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
+MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
+MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
new file mode 100644
index 000000000000..5de78710524c
--- /dev/null
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <essuuj@gmail.com>
+ * Author: Alim Akhtar <alim.akhtar@samsung.com>
+ *
+ */
+#ifndef _PHY_SAMSUNG_UFS_
+#define _PHY_SAMSUNG_UFS_
+
+#define PHY_COMN_BLK 1
+#define PHY_TRSV_BLK 2
+#define END_UFS_PHY_CFG { 0 }
+#define PHY_TRSV_CH_OFFSET 0x30
+#define PHY_APB_ADDR(off) ((off) << 2)
+
+#define PHY_COMN_REG_CFG(o, v, d) { \
+ .off_0 = PHY_APB_ADDR((o)), \
+ .off_1 = 0, \
+ .val = (v), \
+ .desc = (d), \
+ .id = PHY_COMN_BLK, \
+}
+
+#define PHY_TRSV_REG_CFG(o, v, d) { \
+ .off_0 = PHY_APB_ADDR((o)), \
+ .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \
+ .val = (v), \
+ .desc = (d), \
+ .id = PHY_TRSV_BLK, \
+}
+
+/* UFS PHY registers */
+#define PHY_PLL_LOCK_STATUS 0x1e
+#define PHY_CDR_LOCK_STATUS 0x5e
+
+#define PHY_PLL_LOCK_BIT BIT(5)
+#define PHY_CDR_LOCK_BIT BIT(4)
+
+/* description for PHY calibration */
+enum {
+ /* applicable to any */
+ PWR_DESC_ANY = 0,
+ /* mode */
+ PWR_DESC_PWM = 1,
+ PWR_DESC_HS = 2,
+ /* series */
+ PWR_DESC_SER_A = 1,
+ PWR_DESC_SER_B = 2,
+ /* gear */
+ PWR_DESC_G1 = 1,
+ PWR_DESC_G2 = 2,
+ PWR_DESC_G3 = 3,
+ /* field mask */
+ MD_MASK = 0x3,
+ SR_MASK = 0x3,
+ GR_MASK = 0x7,
+};
+
+#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
+#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
+#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
+#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
+#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
+#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
+#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
+ (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
+#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_PWM)
+#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
+ (((s) & SR_MASK) << 2) | PWR_DESC_HS)
+#define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_HS)
+#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_ANY)
+/* PHY calibration point/state */
+enum {
+ CFG_PRE_INIT,
+ CFG_POST_INIT,
+ CFG_PRE_PWR_HS,
+ CFG_POST_PWR_HS,
+ CFG_TAG_MAX,
+};
+
+struct samsung_ufs_phy_cfg {
+ u32 off_0;
+ u32 off_1;
+ u32 val;
+ u8 desc;
+ u8 id;
+};
+
+struct samsung_ufs_phy_drvdata {
+ const struct samsung_ufs_phy_cfg **cfg;
+ struct pmu_isol {
+ u32 offset;
+ u32 mask;
+ u32 en;
+ } isol;
+ bool has_symbol_clk;
+};
+
+struct samsung_ufs_phy {
+ struct device *dev;
+ void __iomem *reg_pma;
+ struct regmap *reg_pmu;
+ struct clk *ref_clk;
+ struct clk *ref_clk_parent;
+ struct clk *tx0_symbol_clk;
+ struct clk *rx0_symbol_clk;
+ struct clk *rx1_symbol_clk;
+ const struct samsung_ufs_phy_drvdata *drvdata;
+ struct samsung_ufs_phy_cfg **cfg;
+ const struct pmu_isol *isol;
+ u8 lane_cnt;
+ int ufs_phy_state;
+ enum phy_mode mode;
+};
+
+static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
+{
+ return (struct samsung_ufs_phy *)phy_get_drvdata(phy);
+}
+
+static inline void samsung_ufs_phy_ctrl_isol(
+ struct samsung_ufs_phy *phy, u32 isol)
+{
+ regmap_update_bits(phy->reg_pmu, phy->isol->offset,
+ phy->isol->mask, isol ? 0 : phy->isol->en);
+}
+
+#include "phy-exynos7-ufs.h"
+
+#endif /* _PHY_SAMSUNG_UFS_ */
--
2.17.1
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* Re: [PATCH] ASoC: meson: add the missed kfree() for axg_card_add_tdm_loopback
From: Jing Xiangfeng @ 2020-07-17 1:49 UTC (permalink / raw)
To: Jerome Brunet, lgirdwood, broonie, perex, tiwai, khilman,
kuninori.morimoto.gx
Cc: linux-amlogic, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <1jzh7zegfw.fsf@starbuckisacylon.baylibre.com>
On 2020/7/16 21:29, Jerome Brunet wrote:
>
> On Thu 16 Jul 2020 at 15:25, Jing Xiangfeng <jingxiangfeng@huawei.com> wrote:
>
>> axg_card_add_tdm_loopback() misses to call kfree() in an error path. Add
>> the missed function call to fix it.
>>
>> Fixes: c84836d7f650 ("ASoC: meson: axg-card: use modern dai_link style")
>> Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com>
>
> Thanks for fixing this.
> Maybe it would be better to use the devm_ variant for the name instead ?
Ok, I'll send a v2 with this change.
Thanks for your review.
>
>> ---
>> sound/soc/meson/axg-card.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/sound/soc/meson/axg-card.c b/sound/soc/meson/axg-card.c
>> index 89f7f64747cd..6eac22ba8b99 100644
>> --- a/sound/soc/meson/axg-card.c
>> +++ b/sound/soc/meson/axg-card.c
>> @@ -121,8 +121,10 @@ static int axg_card_add_tdm_loopback(struct snd_soc_card *card,
>> return -ENOMEM;
>>
>> dlc = devm_kzalloc(card->dev, 2 * sizeof(*dlc), GFP_KERNEL);
>> - if (!dlc)
>> + if (!dlc) {
>> + kfree(lb->name);
>> return -ENOMEM;
>> + }
>>
>> lb->cpus = &dlc[0];
>> lb->codecs = &dlc[1];
>
> .
>
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^ permalink raw reply
* [PATCH v13 1/2] dt-bindings: phy: Document Samsung UFS PHY bindings
From: Alim Akhtar @ 2020-07-16 19:22 UTC (permalink / raw)
To: vkoul
Cc: devicetree, linux-samsung-soc, linux-kernel, krzk, robh+dt,
Alim Akhtar, linux-arm-kernel
In-Reply-To: <CGME20200716194405epcas5p2da2808b30d8f958290bc5d424aa6a0c7@epcas5p2.samsung.com>
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index 000000000000..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar <alim.akhtar@samsung.com>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: phy-pma
+
+ clocks:
+ items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos7-clk.h>
+
+ ufs_phy: ufs-phy@15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+ clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+ };
+...
base-commit: 0ff35966d171ec99b118df666c1687cc86ba8d7e
--
2.17.1
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* [PATCH 01/13] pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl
From: Jianqun Xu @ 2020-07-17 1:48 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add nr_pins to rockchip_pin_ctrl by hand, instead of calculating during
driver probe. This patch is prepare work for making rockchip_pin_ctrl to
be const type.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c07324d1f265..bc465da68f26 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3573,6 +3573,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
+ u32 nr_pins;
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -3599,13 +3600,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
bank = ctrl->pin_banks;
+ nr_pins = 0;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;
raw_spin_lock_init(&bank->slock);
bank->drvdata = d;
- bank->pin_base = ctrl->nr_pins;
- ctrl->nr_pins += bank->nr_pins;
+ bank->pin_base = nr_pins;
+ nr_pins += bank->nr_pins;
/* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {
@@ -3692,6 +3694,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
}
}
+ WARN_ON(nr_pins != ctrl->nr_pins);
+
return ctrl;
}
@@ -3852,6 +3856,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
static struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks = px30_pin_banks,
.nr_banks = ARRAY_SIZE(px30_pin_banks),
+ .nr_pins = 128,
.label = "PX30-GPIO",
.type = PX30,
.grf_mux_offset = 0x0,
@@ -3876,6 +3881,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
+ .nr_pins = 128,
.label = "RV1108-GPIO",
.type = RV1108,
.grf_mux_offset = 0x10,
@@ -3897,6 +3903,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = {
static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pin_banks = rk2928_pin_banks,
.nr_banks = ARRAY_SIZE(rk2928_pin_banks),
+ .nr_pins = 128,
.label = "RK2928-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3912,6 +3919,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
+ .nr_pins = 96,
.label = "RK3036-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3930,6 +3938,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = {
static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
.pin_banks = rk3066a_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
+ .nr_pins = 176,
.label = "RK3066a-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3946,6 +3955,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = {
static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.pin_banks = rk3066b_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
+ .nr_pins = 128,
.label = "RK3066b-GPIO",
.type = RK3066B,
.grf_mux_offset = 0x60,
@@ -3961,6 +3971,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
+ .nr_pins = 128,
.label = "RK3128-GPIO",
.type = RK3128,
.grf_mux_offset = 0xa8,
@@ -3981,6 +3992,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = {
static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
+ .nr_pins = 128,
.label = "RK3188-GPIO",
.type = RK3188,
.grf_mux_offset = 0x60,
@@ -3999,6 +4011,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = {
static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
+ .nr_pins = 128,
.label = "RK3228-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4043,6 +4056,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = {
static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
+ .nr_pins = 264,
.label = "RK3288-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4079,6 +4093,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = {
static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
.pin_banks = rk3308_pin_banks,
.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
+ .nr_pins = 160,
.label = "RK3308-GPIO",
.type = RK3308,
.grf_mux_offset = 0x0,
@@ -4108,6 +4123,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
+ .nr_pins = 128,
.label = "RK3328-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4134,6 +4150,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = {
static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
+ .nr_pins = 128,
.label = "RK3368-GPIO",
.type = RK3368,
.grf_mux_offset = 0x0,
@@ -4198,6 +4215,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
+ .nr_pins = 160,
.label = "RK3399-GPIO",
.type = RK3399,
.grf_mux_offset = 0xe000,
--
2.17.1
^ permalink raw reply related
* Re: [PATCH] ASoC: meson: add the missed kfree() for axg_card_add_tdm_loopback
From: Jing Xiangfeng @ 2020-07-17 1:49 UTC (permalink / raw)
To: Jerome Brunet, lgirdwood, broonie, perex, tiwai, khilman,
kuninori.morimoto.gx
Cc: alsa-devel, linux-arm-kernel, linux-amlogic, linux-kernel
In-Reply-To: <1jzh7zegfw.fsf@starbuckisacylon.baylibre.com>
On 2020/7/16 21:29, Jerome Brunet wrote:
>
> On Thu 16 Jul 2020 at 15:25, Jing Xiangfeng <jingxiangfeng@huawei.com> wrote:
>
>> axg_card_add_tdm_loopback() misses to call kfree() in an error path. Add
>> the missed function call to fix it.
>>
>> Fixes: c84836d7f650 ("ASoC: meson: axg-card: use modern dai_link style")
>> Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com>
>
> Thanks for fixing this.
> Maybe it would be better to use the devm_ variant for the name instead ?
Ok, I'll send a v2 with this change.
Thanks for your review.
>
>> ---
>> sound/soc/meson/axg-card.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/sound/soc/meson/axg-card.c b/sound/soc/meson/axg-card.c
>> index 89f7f64747cd..6eac22ba8b99 100644
>> --- a/sound/soc/meson/axg-card.c
>> +++ b/sound/soc/meson/axg-card.c
>> @@ -121,8 +121,10 @@ static int axg_card_add_tdm_loopback(struct snd_soc_card *card,
>> return -ENOMEM;
>>
>> dlc = devm_kzalloc(card->dev, 2 * sizeof(*dlc), GFP_KERNEL);
>> - if (!dlc)
>> + if (!dlc) {
>> + kfree(lb->name);
>> return -ENOMEM;
>> + }
>>
>> lb->cpus = &dlc[0];
>> lb->codecs = &dlc[1];
>
> .
>
^ permalink raw reply
* [PATCH 00/13] pinctrl: rockchip: prepare work for split driver
From: Jianqun Xu @ 2020-07-17 1:48 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
This serial patchs include 12 codingstyle patches and 1 bug fix (enable
gpio pclk for rockchip_gpio_to_irq).
Also it's prepare for split driver work.
Jianqun Xu (13):
pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl
pinctrl: rockchip: modify rockchip_pin_ctrl to const struct
pinctrl: rockchip: make driver be tristate module
pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
pinctrl: rockchip: create irq mapping in gpio_to_irq
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: define common codes without special chip name
pinctrl: rockchip: do codingstyle by adding mux route definitions
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-rockchip.c | 933 ++++++++---------------------
2 files changed, 261 insertions(+), 674 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH 03/13] pinctrl: rockchip: make driver be tristate module
From: Jianqun Xu @ 2020-07-17 1:48 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-rockchip.c | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8828613c4e0e..dd4874e2ac67 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
config PINCTRL_ROCKCHIP
- bool
+ tristate "Rockchip gpio and pinctrl driver"
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 77c1e6744f6c..ec509ef8bd8d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
*/
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
+#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/machine.h>
@@ -4259,6 +4261,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &rk3399_pin_ctrl },
{},
};
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
static struct platform_driver rockchip_pinctrl_driver = {
.probe = rockchip_pinctrl_probe,
@@ -4274,3 +4277,7 @@ static int __init rockchip_pinctrl_drv_register(void)
return platform_driver_register(&rockchip_pinctrl_driver);
}
postcore_initcall(rockchip_pinctrl_drv_register);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v2 2/6] options: Add zonecapacity option for zonemode=zbd
From: Damien Le Moal @ 2020-07-17 1:48 UTC (permalink / raw)
To: Shinichiro Kawasaki, fio@vger.kernel.org, Jens Axboe
Cc: Hans Holmberg, Aravind Ramesh
In-Reply-To: <20200715064141.116415-3-shinichiro.kawasaki@wdc.com>
On 2020/07/15 15:41, Shin'ichiro Kawasaki wrote:
> From: Hans Holmberg <hans.holmberg@wdc.com>
>
> To test zone capacity handling by fio using regular block devices, add
> zonecapacity option for zonemode=zbd. It allows to specify zone capacity
> common to all zones.
Please better describe the option:
This new option allows specifying a zone capacity smaller than the zone size.
Similarly to the zonesize option, the zonecapacity defined value applies to all
emulated zones of the device.
>
> Signed-off-by: Hans Holmberg <hans.holmberg@wdc.com>
> Signed-off-by: Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>
> ---
> HOWTO | 18 +++++++++++++++---
> cconv.c | 2 ++
> fio.1 | 13 +++++++++++--
> options.c | 11 +++++++++++
> thread_options.h | 2 ++
> zbd.c | 13 ++++++++++++-
> 6 files changed, 53 insertions(+), 6 deletions(-)
>
> diff --git a/HOWTO b/HOWTO
> index 8cf8d650..35ead0cb 100644
> --- a/HOWTO
> +++ b/HOWTO
> @@ -970,14 +970,15 @@ Target file/device
> Accepted values are:
>
> **none**
> - The :option:`zonerange`, :option:`zonesize` and
> - :option:`zoneskip` parameters are ignored.
> + The :option:`zonerange`, :option:`zonesize`,
> + :option `zonecapacity` and option:`zoneskip`
> + parameters are ignored.
> **strided**
> I/O happens in a single zone until
> :option:`zonesize` bytes have been transferred.
> After that number of bytes has been
> transferred processing of the next zone
> - starts.
> + starts. :option `zonecapacity` is ignored.
> **zbd**
> Zoned block device mode. I/O happens
> sequentially in each zone, even if random I/O
> @@ -1004,6 +1005,17 @@ Target file/device
> For :option:`zonemode` =zbd, this is the size of a single zone. The
> :option:`zonerange` parameter is ignored in this mode.
>
> +
> +.. option:: zonecapacity=int
> +
> + For :option:`zonemode` =zbd, this defines the capacity of a single zone,
> + which is the accessible area starting from the zone start address.
> + This parameter only applies when using :option:`zonemode` =zbd in
> + combination with regular block devices. If not specified it defaults to
> + the zone size. If the target device is a zoned block device, the zone
> + capacity is obtained from the device information and this option is
> + ignored.
> +
> .. option:: zoneskip=int
>
> For :option:`zonemode` =strided, the number of bytes to skip after
> diff --git a/cconv.c b/cconv.c
> index 449bcf7b..2469389b 100644
> --- a/cconv.c
> +++ b/cconv.c
> @@ -223,6 +223,7 @@ void convert_thread_options_to_cpu(struct thread_options *o,
> o->ss_limit.u.f = fio_uint64_to_double(le64_to_cpu(top->ss_limit.u.i));
> o->zone_range = le64_to_cpu(top->zone_range);
> o->zone_size = le64_to_cpu(top->zone_size);
> + o->zone_capacity = le64_to_cpu(top->zone_capacity);
> o->zone_skip = le64_to_cpu(top->zone_skip);
> o->zone_mode = le32_to_cpu(top->zone_mode);
> o->lockmem = le64_to_cpu(top->lockmem);
> @@ -563,6 +564,7 @@ void convert_thread_options_to_net(struct thread_options_pack *top,
> top->ss_limit.u.i = __cpu_to_le64(fio_double_to_uint64(o->ss_limit.u.f));
> top->zone_range = __cpu_to_le64(o->zone_range);
> top->zone_size = __cpu_to_le64(o->zone_size);
> + top->zone_capacity = __cpu_to_le64(o->zone_capacity);
> top->zone_skip = __cpu_to_le64(o->zone_skip);
> top->zone_mode = __cpu_to_le32(o->zone_mode);
> top->lockmem = __cpu_to_le64(o->lockmem);
> diff --git a/fio.1 b/fio.1
> index f134e0bf..68aeb21f 100644
> --- a/fio.1
> +++ b/fio.1
> @@ -738,12 +738,13 @@ Accepted values are:
> .RS
> .TP
> .B none
> -The \fBzonerange\fR, \fBzonesize\fR and \fBzoneskip\fR parameters are ignored.
> +The \fBzonerange\fR, \fBzonesize\fR \fBzonecapacity and \fBzoneskip\fR
Missing \fR after \fBzonecapacity.
> +parameters are ignored.
> .TP
> .B strided
> I/O happens in a single zone until \fBzonesize\fR bytes have been transferred.
> After that number of bytes has been transferred processing of the next zone
> -starts.
> +starts. The \fBzonecapacity parameter is ignored.
Same here too.
> .TP
> .B zbd
> Zoned block device mode. I/O happens sequentially in each zone, even if random
> @@ -771,6 +772,14 @@ zoned block device, the specified \fBzonesize\fR must be 0 or equal to the
> device zone size. For a regular block device or file, the specified
> \fBzonesize\fR must be at least 512B.
> .TP
> +.BI zonecapacity \fR=\fPint
> +For \fBzonemode\fR=zbd, this defines the capacity of a single zone, which is
> +the accessible area starting from the zone start address. This parameter only
> +applies when using \fBzonemode\fR=zbd in combination with regular block devices.
> +If not specified it defaults to the zone size. If the target device is a zoned
> +block device, the zone capacity is obtained from the device information and this
> +option is ignored.
> +.TP
> .BI zoneskip \fR=\fPint
> For \fBzonemode\fR=strided, the number of bytes to skip after \fBzonesize\fR
> bytes of data have been transferred.
> diff --git a/options.c b/options.c
> index 85a0f490..251ad2c1 100644
> --- a/options.c
> +++ b/options.c
> @@ -3327,6 +3327,17 @@ struct fio_option fio_options[FIO_MAX_OPTS] = {
> .category = FIO_OPT_C_IO,
> .group = FIO_OPT_G_ZONE,
> },
> + {
> + .name = "zonecapacity",
> + .lname = "Zone capacity",
> + .type = FIO_OPT_STR_VAL,
> + .off1 = offsetof(struct thread_options, zone_capacity),
> + .help = "Capacity per zone",
> + .def = "0",
> + .interval = 1024 * 1024,
> + .category = FIO_OPT_C_IO,
> + .group = FIO_OPT_G_ZONE,
> + },
> {
> .name = "zonerange",
> .lname = "Zone range",
> diff --git a/thread_options.h b/thread_options.h
> index 968ea0ab..3fe48ecc 100644
> --- a/thread_options.h
> +++ b/thread_options.h
> @@ -193,6 +193,7 @@ struct thread_options {
> unsigned int loops;
> unsigned long long zone_range;
> unsigned long long zone_size;
> + unsigned long long zone_capacity;
> unsigned long long zone_skip;
> enum fio_zone_mode zone_mode;
> unsigned long long lockmem;
> @@ -487,6 +488,7 @@ struct thread_options_pack {
> uint32_t loops;
> uint64_t zone_range;
> uint64_t zone_size;
> + uint64_t zone_capacity;
> uint64_t zone_skip;
> uint64_t lockmem;
> uint32_t mem_type;
> diff --git a/zbd.c b/zbd.c
> index c738a58b..85478aa5 100644
> --- a/zbd.c
> +++ b/zbd.c
> @@ -371,6 +371,7 @@ static int init_zone_info(struct thread_data *td, struct fio_file *f)
> uint32_t nr_zones;
> struct fio_zone_info *p;
> uint64_t zone_size = td->o.zone_size;
> + uint64_t zone_capacity = td->o.zone_capacity;
> struct zoned_block_device_info *zbd_info = NULL;
> int i;
>
> @@ -386,6 +387,16 @@ static int init_zone_info(struct thread_data *td, struct fio_file *f)
> return 1;
> }
>
> + if (zone_capacity == 0)
> + zone_capacity = zone_size;
> +
> + if (zone_capacity > zone_size) {
> + log_err("%s: job parameter zonecapacity %llu is larger than zone size %llu\n",
> + f->file_name, (unsigned long long) td->o.zone_capacity,
> + (unsigned long long) td->o.zone_size);
> + return 1;
> + }
> +
> nr_zones = (f->real_file_size + zone_size - 1) / zone_size;
> zbd_info = scalloc(1, sizeof(*zbd_info) +
> (nr_zones + 1) * sizeof(zbd_info->zone_info[0]));
> @@ -402,7 +413,7 @@ static int init_zone_info(struct thread_data *td, struct fio_file *f)
> p->wp = p->start;
> p->type = ZBD_ZONE_TYPE_SWR;
> p->cond = ZBD_ZONE_COND_EMPTY;
> - p->capacity = zone_size;
> + p->capacity = zone_capacity;
> }
> /* a sentinel */
> p->start = nr_zones * zone_size;
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply
* [PATCH v13 1/2] dt-bindings: phy: Document Samsung UFS PHY bindings
From: Alim Akhtar @ 2020-07-16 19:22 UTC (permalink / raw)
To: vkoul
Cc: robh+dt, krzk, linux-kernel, devicetree, linux-arm-kernel,
linux-samsung-soc, Alim Akhtar
In-Reply-To: <CGME20200716194405epcas5p2da2808b30d8f958290bc5d424aa6a0c7@epcas5p2.samsung.com>
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index 000000000000..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar <alim.akhtar@samsung.com>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ items:
+ - const: phy-pma
+
+ clocks:
+ items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos7-clk.h>
+
+ ufs_phy: ufs-phy@15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+ clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+ };
+...
base-commit: 0ff35966d171ec99b118df666c1687cc86ba8d7e
--
2.17.1
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