* [PATCH 06/13] pinctrl: rockchip: Add RK3399 definitions to separate from other SoCs
From: Jianqun Xu @ 2020-07-17 3:26 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add RK3399 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 1be4627f3877..71335ed003b3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2050,6 +2050,9 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
#define RK3399_DRV_3BITS_PER_PIN 3
+#define RK3399_PULL_BITS_PER_PIN 2
+#define RK3399_PULL_PINS_PER_REG 8
+#define RK3399_PULL_BANK_STRIDE 16
static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2062,22 +2065,22 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3399_PULL_PINS_PER_REG;
+ *bit *= RK3399_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3399_PULL_PINS_PER_REG);
+ *bit *= RK3399_PULL_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH 05/13] pinctrl: rockchip: create irq mapping in gpio_to_irq
From: Jianqun Xu @ 2020-07-17 3:26 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mapping
This patch can speed up system boot on, also abandon many unused irq
mappings' create.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 28 ++++++++++++----------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index d34fada39227..1be4627f3877 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3196,7 +3196,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
irq = __ffs(pend);
pend &= ~BIT(irq);
- virq = irq_linear_revmap(bank->domain, irq);
+ virq = irq_find_mapping(bank->domain, irq);
if (!virq) {
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
@@ -3375,7 +3375,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
- int i, j;
+ int i;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (!bank->valid) {
@@ -3402,7 +3402,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
"rockchip_gpio_irq", handle_level_irq,
- clr, 0, IRQ_GC_INIT_MASK_CACHE);
+ clr, 0, 0);
if (ret) {
dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
bank->name);
@@ -3411,14 +3411,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
continue;
}
- /*
- * Linux assumes that all interrupts start out disabled/masked.
- * Our driver only uses the concept of masked and always keeps
- * things enabled, so for us that's all masked and all enabled.
- */
- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
-
gc = irq_get_domain_generic_chip(bank->domain, 0);
gc->reg_base = bank->reg_base;
gc->private = bank;
@@ -3435,13 +3427,17 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
+ /*
+ * Linux assumes that all interrupts start out disabled/masked.
+ * Our driver only uses the concept of masked and always keeps
+ * things enabled, so for us that's all masked and all enabled.
+ */
+ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
+ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
+ gc->mask_cache = 0xffffffff;
+
irq_set_chained_handler_and_data(bank->irq,
rockchip_irq_demux, bank);
-
- /* map the gpio irqs here, when the clock is still running */
- for (j = 0 ; j < 32 ; j++)
- irq_create_mapping(bank->domain, j);
-
clk_disable(bank->clk);
}
--
2.17.1
^ permalink raw reply related
* [PATCH 03/13] pinctrl: rockchip: make driver be tristate module
From: Jianqun Xu @ 2020-07-17 3:24 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-rockchip.c | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8828613c4e0e..dd4874e2ac67 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
config PINCTRL_ROCKCHIP
- bool
+ tristate "Rockchip gpio and pinctrl driver"
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 77c1e6744f6c..ec509ef8bd8d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
*/
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
+#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/machine.h>
@@ -4259,6 +4261,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &rk3399_pin_ctrl },
{},
};
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
static struct platform_driver rockchip_pinctrl_driver = {
.probe = rockchip_pinctrl_probe,
@@ -4274,3 +4277,7 @@ static int __init rockchip_pinctrl_drv_register(void)
return platform_driver_register(&rockchip_pinctrl_driver);
}
postcore_initcall(rockchip_pinctrl_drv_register);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
--
2.17.1
^ permalink raw reply related
* [PATCH 01/13] pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl
From: Jianqun Xu @ 2020-07-17 3:23 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
Add nr_pins to rockchip_pin_ctrl by hand, instead of calculating during
driver probe. This patch is prepare work for making rockchip_pin_ctrl to
be const type.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c07324d1f265..bc465da68f26 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3573,6 +3573,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
+ u32 nr_pins;
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -3599,13 +3600,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
bank = ctrl->pin_banks;
+ nr_pins = 0;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;
raw_spin_lock_init(&bank->slock);
bank->drvdata = d;
- bank->pin_base = ctrl->nr_pins;
- ctrl->nr_pins += bank->nr_pins;
+ bank->pin_base = nr_pins;
+ nr_pins += bank->nr_pins;
/* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {
@@ -3692,6 +3694,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
}
}
+ WARN_ON(nr_pins != ctrl->nr_pins);
+
return ctrl;
}
@@ -3852,6 +3856,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
static struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks = px30_pin_banks,
.nr_banks = ARRAY_SIZE(px30_pin_banks),
+ .nr_pins = 128,
.label = "PX30-GPIO",
.type = PX30,
.grf_mux_offset = 0x0,
@@ -3876,6 +3881,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
+ .nr_pins = 128,
.label = "RV1108-GPIO",
.type = RV1108,
.grf_mux_offset = 0x10,
@@ -3897,6 +3903,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = {
static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pin_banks = rk2928_pin_banks,
.nr_banks = ARRAY_SIZE(rk2928_pin_banks),
+ .nr_pins = 128,
.label = "RK2928-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3912,6 +3919,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
+ .nr_pins = 96,
.label = "RK3036-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3930,6 +3938,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = {
static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
.pin_banks = rk3066a_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
+ .nr_pins = 176,
.label = "RK3066a-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3946,6 +3955,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = {
static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.pin_banks = rk3066b_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
+ .nr_pins = 128,
.label = "RK3066b-GPIO",
.type = RK3066B,
.grf_mux_offset = 0x60,
@@ -3961,6 +3971,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
+ .nr_pins = 128,
.label = "RK3128-GPIO",
.type = RK3128,
.grf_mux_offset = 0xa8,
@@ -3981,6 +3992,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = {
static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
+ .nr_pins = 128,
.label = "RK3188-GPIO",
.type = RK3188,
.grf_mux_offset = 0x60,
@@ -3999,6 +4011,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = {
static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
+ .nr_pins = 128,
.label = "RK3228-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4043,6 +4056,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = {
static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
+ .nr_pins = 264,
.label = "RK3288-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4079,6 +4093,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = {
static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
.pin_banks = rk3308_pin_banks,
.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
+ .nr_pins = 160,
.label = "RK3308-GPIO",
.type = RK3308,
.grf_mux_offset = 0x0,
@@ -4108,6 +4123,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
+ .nr_pins = 128,
.label = "RK3328-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4134,6 +4150,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = {
static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
+ .nr_pins = 128,
.label = "RK3368-GPIO",
.type = RK3368,
.grf_mux_offset = 0x0,
@@ -4198,6 +4215,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
+ .nr_pins = 160,
.label = "RK3399-GPIO",
.type = RK3399,
.grf_mux_offset = 0xe000,
--
2.17.1
^ permalink raw reply related
* [PATCH 02/13] pinctrl: rockchip: modify rockchip_pin_ctrl to const struct
From: Jianqun Xu @ 2020-07-17 3:24 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
The rockchip_pin_ctrl structure actually is soc data structure for
pinctrl on Rockchip SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 62 +++++++++++++++---------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index bc465da68f26..77c1e6744f6c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -392,7 +392,7 @@ struct rockchip_pinctrl {
struct regmap *regmap_pull;
struct regmap *regmap_pmu;
struct device *dev;
- struct rockchip_pin_ctrl *ctrl;
+ const struct rockchip_pin_ctrl *ctrl;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct rockchip_pin_group *groups;
@@ -779,7 +779,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
int *reg, u8 *bit, int *mask)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_recalced_data *data;
int i;
@@ -1396,7 +1396,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
int mux, u32 *loc, u32 *reg, u32 *value)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_route_data *data;
int i;
@@ -2112,7 +2112,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u32 data, temp, rmask_bits;
@@ -2189,7 +2189,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i;
u32 data, rmask, rmask_bits, temp;
@@ -2297,7 +2297,7 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, pull_type;
u8 bit;
@@ -2341,7 +2341,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i, pull_type;
u8 bit;
@@ -2427,7 +2427,7 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
@@ -2449,7 +2449,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
int pin_num, int enable)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
@@ -2621,7 +2621,7 @@ static const struct pinmux_ops rockchip_pmx_ops = {
* Pinconf_ops handling
*/
-static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
+static bool rockchip_pinconf_pull_valid(const struct rockchip_pin_ctrl *ctrl,
enum pin_config_param pull)
{
switch (ctrl->type) {
@@ -3366,7 +3366,7 @@ static void rockchip_irq_disable(struct irq_data *d)
static int rockchip_interrupts_register(struct platform_device *pdev,
struct rockchip_pinctrl *info)
{
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_pin_bank *bank = ctrl->pin_banks;
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
@@ -3447,7 +3447,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
static int rockchip_gpiolib_register(struct platform_device *pdev,
struct rockchip_pinctrl *info)
{
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_pin_bank *bank = ctrl->pin_banks;
struct gpio_chip *gc;
int ret;
@@ -3493,7 +3493,7 @@ static int rockchip_gpiolib_register(struct platform_device *pdev,
static int rockchip_gpiolib_unregister(struct platform_device *pdev,
struct rockchip_pinctrl *info)
{
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_pin_bank *bank = ctrl->pin_banks;
int i;
@@ -3563,20 +3563,20 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
static const struct of_device_id rockchip_pinctrl_dt_match[];
/* retrieve the soc specific data */
-static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
+static const struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
struct rockchip_pinctrl *d,
struct platform_device *pdev)
{
const struct of_device_id *match;
struct device_node *node = pdev->dev.of_node;
struct device_node *np;
- struct rockchip_pin_ctrl *ctrl;
+ const const struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
u32 nr_pins;
match = of_match_node(rockchip_pinctrl_dt_match, node);
- ctrl = (struct rockchip_pin_ctrl *)match->data;
+ ctrl = (const struct rockchip_pin_ctrl *)match->data;
for_each_child_of_node(node, np) {
if (!of_find_property(np, "gpio-controller", NULL))
@@ -3748,7 +3748,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
{
struct rockchip_pinctrl *info;
struct device *dev = &pdev->dev;
- struct rockchip_pin_ctrl *ctrl;
+ const const struct rockchip_pin_ctrl *ctrl;
struct device_node *np = pdev->dev.of_node, *node;
struct resource *res;
void __iomem *base;
@@ -3853,7 +3853,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
),
};
-static struct rockchip_pin_ctrl px30_pin_ctrl = {
+static const struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks = px30_pin_banks,
.nr_banks = ARRAY_SIZE(px30_pin_banks),
.nr_pins = 128,
@@ -3878,7 +3878,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
};
-static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
+static const struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
.nr_pins = 128,
@@ -3900,7 +3900,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pin_banks = rk2928_pin_banks,
.nr_banks = ARRAY_SIZE(rk2928_pin_banks),
.nr_pins = 128,
@@ -3916,7 +3916,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
PIN_BANK(2, 32, "gpio2"),
};
-static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
.nr_pins = 96,
@@ -3935,7 +3935,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = {
PIN_BANK(6, 16, "gpio6"),
};
-static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
.pin_banks = rk3066a_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
.nr_pins = 176,
@@ -3952,7 +3952,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.pin_banks = rk3066b_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
.nr_pins = 128,
@@ -3968,7 +3968,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
.nr_pins = 128,
@@ -3989,7 +3989,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
.nr_pins = 128,
@@ -4008,7 +4008,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
.nr_pins = 128,
@@ -4053,7 +4053,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = {
PIN_BANK(8, 16, "gpio8"),
};
-static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
.nr_pins = 264,
@@ -4090,7 +4090,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = {
IOMUX_WIDTH_2BIT),
};
-static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3308_pin_ctrl = {
.pin_banks = rk3308_pin_banks,
.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
.nr_pins = 160,
@@ -4120,7 +4120,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
0),
};
-static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
.nr_pins = 128,
@@ -4147,7 +4147,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
.nr_pins = 128,
@@ -4212,7 +4212,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
),
};
-static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
.nr_pins = 160,
--
2.17.1
^ permalink raw reply related
* [PATCH 04/13] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
From: Jianqun Xu @ 2020-07-17 3:24 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>
There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index ec509ef8bd8d..d34fada39227 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3155,7 +3155,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
if (!bank->domain)
return -ENXIO;
+ clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
+ clk_disable(bank->clk);
return (virq) ? : -ENXIO;
}
--
2.17.1
^ permalink raw reply related
* [PATCH RESEND 00/13] pinctrl: rockchip: prepare work for split driver
From: Jianqun Xu @ 2020-07-17 3:23 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
This serial patchs include 12 codingstyle patches and 1 bug fix (enable
gpio pclk for rockchip_gpio_to_irq).
Also it's prepare for split driver work.
Jianqun Xu (13):
pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl
pinctrl: rockchip: modify rockchip_pin_ctrl to const struct
pinctrl: rockchip: make driver be tristate module
pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
pinctrl: rockchip: create irq mapping in gpio_to_irq
pinctrl: rockchip: Add RK3399 definitions to separate from other SoCs
pinctrl: rockchip: Add RK3368 definitions to separate from other SoCs
pinctrl: rockchip: Add RK3308 definitions to separate from other SoCs
pinctrl: rockchip: Add RK3228 definitions to separate from other SoCs
pinctrl: rockchip: Add RK3288 definitions to separate from other SoCs
pinctrl: rockchip: Add RK3128 definitions to separate from other SoCs
pinctrl: rockchip: define common codes without special chip name
pinctrl: rockchip: do codingstyle by adding mux route definitions
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-rockchip.c | 933 ++++++++---------------------
2 files changed, 261 insertions(+), 674 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH v4 00/25] x86: Enhance MTRR functionality to support multiple CPUs
From: Simon Glass @ 2020-07-17 3:24 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200708013446.2600256-1-sjg@chromium.org>
Hi Bin,
On Tue, 7 Jul 2020 at 19:36, Simon Glass <sjg@chromium.org> wrote:
>
> At present MTRRs are mirrored to the secondary CPUs only once, as those
> CPUs are started up. But U-Boot may add more MTRRs later, e.g. if it
> decides that a video console must be set up.
>
> This series enhances the x86 multi-processor support to allow MTRRs to
> be updated at any time. It also updates the 'mtrr' command to support
> setting the MTRRs on CPUs other than the boot CPU.
>
> Changes in v4:
> - Update get_bsp() to return zero when SMP is not inited
> - Add a Kconfig to control this feature, enabled only on APL
> - Only enable this feature of CONFIG_SMP_AP_WORK is enabled
> - Allow running on the BSP if SMP is not enabled
> - Update mp_next_cpu() to stop if CONFIG_SMP_AP_WORK is not enabled
Is anything else needed with this series?
Regards,
Simon
^ permalink raw reply
* Re: [PATCH V5 1/4] mm/debug_vm_pgtable: Add tests validating arch helpers for core MM features
From: Anshuman Khandual @ 2020-07-17 3:20 UTC (permalink / raw)
To: Steven Price, linux-mm
Cc: Heiko Carstens, Paul Mackerras, H. Peter Anvin, agordeev,
Will Deacon, linux-riscv, linux-arch, linux-s390, x86,
Mike Rapoport, Christian Borntraeger, Ingo Molnar,
gerald.schaefer, ziy, Catalin Marinas, linux-snps-arc,
Vasily Gorbik, cai, Paul Walmsley, Kirill A . Shutemov,
Thomas Gleixner, linux-arm-kernel, christophe.leroy, Vineet Gupta,
linux-kernel, Palmer Dabbelt, aneesh.kumar, Borislav Petkov,
Andrew Morton, linuxppc-dev, rppt
In-Reply-To: <2ff756c5-28e2-b64a-3788-260ba30c6409@arm.com>
On 07/16/2020 07:44 PM, Steven Price wrote:
> On 13/07/2020 04:23, Anshuman Khandual wrote:
>> This adds new tests validating arch page table helpers for these following
>> core memory features. These tests create and test specific mapping types at
>> various page table levels.
>>
>> 1. SPECIAL mapping
>> 2. PROTNONE mapping
>> 3. DEVMAP mapping
>> 4. SOFTDIRTY mapping
>> 5. SWAP mapping
>> 6. MIGRATION mapping
>> 7. HUGETLB mapping
>> 8. THP mapping
>>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>> Cc: Mike Rapoport <rppt@linux.ibm.com>
>> Cc: Vineet Gupta <vgupta@synopsys.com>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Cc: Paul Mackerras <paulus@samba.org>
>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
>> Cc: Vasily Gorbik <gor@linux.ibm.com>
>> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Borislav Petkov <bp@alien8.de>
>> Cc: "H. Peter Anvin" <hpa@zytor.com>
>> Cc: Kirill A. Shutemov <kirill@shutemov.name>
>> Cc: Paul Walmsley <paul.walmsley@sifive.com>
>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>> Cc: linux-snps-arc@lists.infradead.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Cc: linux-s390@vger.kernel.org
>> Cc: linux-riscv@lists.infradead.org
>> Cc: x86@kernel.org
>> Cc: linux-mm@kvack.org
>> Cc: linux-arch@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Tested-by: Vineet Gupta <vgupta@synopsys.com> #arc
>> Reviewed-by: Zi Yan <ziy@nvidia.com>
>> Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> mm/debug_vm_pgtable.c | 302 +++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 301 insertions(+), 1 deletion(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index 61ab16fb2e36..2fac47db3eb7 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
> [...]
>> +
>> +static void __init pte_swap_tests(unsigned long pfn, pgprot_t prot)
>> +{
>> + swp_entry_t swp;
>> + pte_t pte;
>> +
>> + pte = pfn_pte(pfn, prot);
>> + swp = __pte_to_swp_entry(pte);
>
> Minor issue: this doesn't look necessarily valid - there's no reason a normal PTE can be turned into a swp_entry. In practise this is likely to work on all architectures because there's no reason not to use (at least) all the PFN bits for the swap entry, but it doesn't exactly seem correct.
Agreed, that it is a simple test but nonetheless a valid one which
makes sure that PFN value remained unchanged during pte <---> swp
conversion.
>
> Can we start with a swp_entry_t (from __swp_entry()) and check the round trip of that?
>
> It would also seem sensible to have a check that is_swap_pte(__swp_entry_to_pte(__swp_entry(x,y))) is true.
From past experiences, getting any these new tests involving platform
helpers, working on all existing enabled archs is neither trivial nor
going to be quick. Existing tests here are known to succeed in enabled
platforms. Nonetheless, proposed tests as in the above suggestions do
make sense but will try to accommodate them in a later patch.
^ permalink raw reply
* Re: [PATCH V5 1/4] mm/debug_vm_pgtable: Add tests validating arch helpers for core MM features
From: Anshuman Khandual @ 2020-07-17 3:20 UTC (permalink / raw)
To: Steven Price, linux-mm
Cc: Benjamin Herrenschmidt, Heiko Carstens, Paul Mackerras,
H. Peter Anvin, agordeev, Will Deacon, linux-riscv, linux-arch,
linux-s390, Michael Ellerman, x86, christophe.leroy,
Mike Rapoport, Christian Borntraeger, Ingo Molnar,
gerald.schaefer, ziy, Catalin Marinas, linux-snps-arc,
Vasily Gorbik, cai, Paul Walmsley, Kirill A . Shutemov,
Thomas Gleixner, linux-arm-kernel, christophe.leroy, Vineet Gupta,
linux-kernel, Palmer Dabbelt, aneesh.kumar, Borislav Petkov,
Andrew Morton, linuxppc-dev, rppt
In-Reply-To: <2ff756c5-28e2-b64a-3788-260ba30c6409@arm.com>
On 07/16/2020 07:44 PM, Steven Price wrote:
> On 13/07/2020 04:23, Anshuman Khandual wrote:
>> This adds new tests validating arch page table helpers for these following
>> core memory features. These tests create and test specific mapping types at
>> various page table levels.
>>
>> 1. SPECIAL mapping
>> 2. PROTNONE mapping
>> 3. DEVMAP mapping
>> 4. SOFTDIRTY mapping
>> 5. SWAP mapping
>> 6. MIGRATION mapping
>> 7. HUGETLB mapping
>> 8. THP mapping
>>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>> Cc: Mike Rapoport <rppt@linux.ibm.com>
>> Cc: Vineet Gupta <vgupta@synopsys.com>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Cc: Paul Mackerras <paulus@samba.org>
>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
>> Cc: Vasily Gorbik <gor@linux.ibm.com>
>> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Borislav Petkov <bp@alien8.de>
>> Cc: "H. Peter Anvin" <hpa@zytor.com>
>> Cc: Kirill A. Shutemov <kirill@shutemov.name>
>> Cc: Paul Walmsley <paul.walmsley@sifive.com>
>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>> Cc: linux-snps-arc@lists.infradead.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Cc: linux-s390@vger.kernel.org
>> Cc: linux-riscv@lists.infradead.org
>> Cc: x86@kernel.org
>> Cc: linux-mm@kvack.org
>> Cc: linux-arch@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Tested-by: Vineet Gupta <vgupta@synopsys.com> #arc
>> Reviewed-by: Zi Yan <ziy@nvidia.com>
>> Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> mm/debug_vm_pgtable.c | 302 +++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 301 insertions(+), 1 deletion(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index 61ab16fb2e36..2fac47db3eb7 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
> [...]
>> +
>> +static void __init pte_swap_tests(unsigned long pfn, pgprot_t prot)
>> +{
>> + swp_entry_t swp;
>> + pte_t pte;
>> +
>> + pte = pfn_pte(pfn, prot);
>> + swp = __pte_to_swp_entry(pte);
>
> Minor issue: this doesn't look necessarily valid - there's no reason a normal PTE can be turned into a swp_entry. In practise this is likely to work on all architectures because there's no reason not to use (at least) all the PFN bits for the swap entry, but it doesn't exactly seem correct.
Agreed, that it is a simple test but nonetheless a valid one which
makes sure that PFN value remained unchanged during pte <---> swp
conversion.
>
> Can we start with a swp_entry_t (from __swp_entry()) and check the round trip of that?
>
> It would also seem sensible to have a check that is_swap_pte(__swp_entry_to_pte(__swp_entry(x,y))) is true.
From past experiences, getting any these new tests involving platform
helpers, working on all existing enabled archs is neither trivial nor
going to be quick. Existing tests here are known to succeed in enabled
platforms. Nonetheless, proposed tests as in the above suggestions do
make sense but will try to accommodate them in a later patch.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v3 10/10] acpi: Enable ACPI table generation by default on x86
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
This should ideally be used by all x86 boards in U-Boot. Enable it by
default. If some boards don't use it, the cost is small.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v3:
- Rebase to x86/master
Changes in v2:
- Don't enable this for qemu
arch/Kconfig | 1 +
drivers/core/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index a11f872938..9be02d1319 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -190,6 +190,7 @@ config X86
imply PCH
imply RTC_MC146818
imply IRQ
+ imply ACPIGEN if !QEMU
# Thing to enable for when SPL/TPL are enabled: SPL
imply SPL_DM
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index a594899f37..00d1d80dc3 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -270,7 +270,7 @@ config DM_DEV_READ_INLINE
config ACPIGEN
bool "Support ACPI table generation in driver model"
- default y if SANDBOX || GENERATE_ACPI_TABLE
+ default y if SANDBOX || (GENERATE_ACPI_TABLE && !QEMU)
help
This option enables generation of ACPI tables using driver-model
devices. It adds a new operation struct to each driver, to support
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 09/10] x86: Rename board_final_cleanup() to board_final_init()
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
This function sounds like something that is called when U-Boot is about to
jump to Linux. In fact it is an init function.
Rename it to reduce confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
---
(no changes since v1)
arch/x86/cpu/coreboot/coreboot.c | 4 ++--
arch/x86/cpu/cpu.c | 8 ++++----
arch/x86/cpu/efi/app.c | 2 +-
arch/x86/cpu/quark/quark.c | 2 +-
arch/x86/lib/fsp/fsp_common.c | 2 +-
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index d44db1347b..22a93254a9 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -42,7 +42,7 @@ int print_cpuinfo(void)
return default_print_cpuinfo();
}
-static void board_final_cleanup(void)
+static void board_final_init(void)
{
/*
* Un-cache the ROM so the kernel has one
@@ -80,7 +80,7 @@ int last_stage_init(void)
if (CONFIG_IS_ENABLED(USB_KEYBOARD))
usb_init();
- board_final_cleanup();
+ board_final_init();
return 0;
}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 9ef797b41b..98ed66e67d 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -179,10 +179,10 @@ void show_boot_progress(int val)
#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
/*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
+ * Implement a weak default function for boards that need to do some final init
+ * before the system is ready.
*/
-__weak void board_final_cleanup(void)
+__weak void board_final_init(void)
{
}
@@ -190,7 +190,7 @@ int last_stage_init(void)
{
struct acpi_fadt __maybe_unused *fadt;
- board_final_cleanup();
+ board_final_init();
if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
fadt = acpi_find_fadt();
diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c
index 10677ecbc2..f754489784 100644
--- a/arch/x86/cpu/efi/app.c
+++ b/arch/x86/cpu/efi/app.c
@@ -24,7 +24,7 @@ int print_cpuinfo(void)
return default_print_cpuinfo();
}
-void board_final_cleanup(void)
+void board_final_init(void)
{
}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index ddad02e375..30b4711b9a 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -363,7 +363,7 @@ int arch_misc_init(void)
return 0;
}
-void board_final_cleanup(void)
+void board_final_init(void)
{
struct quark_rcba *rcba;
u32 base, val;
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 8e3082d4c8..ea52954725 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -47,7 +47,7 @@ int fsp_init_phase_pci(void)
return status ? -EPERM : 0;
}
-void board_final_cleanup(void)
+void board_final_init(void)
{
u32 status;
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 08/10] x86: acpi: Correct the version of the MADT
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
Currently U-Boot implements version 2 but reports version 4. Correct it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
---
(no changes since v2)
Changes in v2:
- Use ACPI_MADT_REV_ACPI_3_0 instead of the open-coded value
arch/x86/lib/acpi_table.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index d2bc3386eb..3a93fedfc3 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -155,7 +155,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
/* Fill out header fields */
acpi_fill_header(header, "APIC");
header->length = sizeof(struct acpi_madt);
- header->revision = 4;
+ header->revision = ACPI_MADT_REV_ACPI_3_0;
madt->lapic_addr = LAPIC_DEFAULT_BASE;
madt->flags = ACPI_MADT_PCAT_COMPAT;
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 07/10] x86: Drop setup_pcat_compatibility()
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
This function does not exist anymore. Drop it from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v2)
Changes in v2:
- Remove the function from zimage.c also
arch/x86/include/asm/u-boot-x86.h | 2 --
arch/x86/lib/zimage.c | 10 ----------
2 files changed, 12 deletions(-)
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index bd3f44014c..d732661f6d 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -83,8 +83,6 @@ int default_print_cpuinfo(void);
/* Set up a UART which can be used with printch(), printhex8(), etc. */
int setup_internal_uart(int enable);
-void setup_pcat_compatibility(void);
-
void isa_unmap_rom(u32 addr);
u32 isa_map_rom(u32 bus_addr, int size);
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 64d14e8911..d2b6002008 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -304,13 +304,6 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
return 0;
}
-void setup_pcat_compatibility(void)
- __attribute__((weak, alias("__setup_pcat_compatibility")));
-
-void __setup_pcat_compatibility(void)
-{
-}
-
int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct boot_params *base_ptr;
@@ -323,9 +316,6 @@ int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
disable_interrupts();
- /* Setup board for maximum PC/AT Compatibility */
- setup_pcat_compatibility();
-
if (argc >= 2) {
/* argv[1] holds the address of the bzImage */
s = argv[1];
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 06/10] x86: Update the comment about booting for FSP2
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
The comment here applies only to FSP1, so update it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
---
(no changes since v1)
arch/x86/cpu/start.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 01524635e9..4ad515ce08 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -124,6 +124,7 @@ car_init_ret:
#endif
#else
/*
+ * Instructions for FSP1, but not FSP2:
* U-Boot enters here twice. For the first time it comes from
* car_init_done() with esp points to a temporary stack and esi
* set to zero. For the second time it comes from fsp_init_done()
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 05/10] x86: Store the coreboot table address in global_data
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
At present this information is used to locate and parse the tables but is
not stored. Store it so that we can display it to the user, e.g. with the
'bdinfo' command.
Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(),
so it is always set when booting from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
---
Changes in v3:
- Update the commit message with an explanation of GD_FLG_SKIP_LL_INIT
arch/x86/cpu/coreboot/tables.c | 8 +++++++-
arch/x86/cpu/i386/cpu.c | 7 ++++++-
arch/x86/include/asm/global_data.h | 1 +
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index a5d31d1dea..1594b4a8b2 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -10,6 +10,8 @@
#include <net.h>
#include <asm/arch/sysinfo.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* This needs to be in the .data section so that it's copied over during
* relocation. By default it's put in the .bss section which is simply filled
@@ -243,6 +245,10 @@ int get_coreboot_info(struct sysinfo_t *info)
if (addr < 0)
return addr;
ret = cb_parse_header((void *)addr, 0x1000, info);
+ if (!ret)
+ return -ENOENT;
+ gd->arch.coreboot_table = addr;
+ gd->flags |= GD_FLG_SKIP_LL_INIT;
- return ret == 1 ? 0 : -ENOENT;
+ return 0;
}
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index d27324cb4e..a6a6afec8c 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -455,10 +455,15 @@ int x86_cpu_init_f(void)
int x86_cpu_reinit_f(void)
{
+ long addr;
+
setup_identity();
setup_pci_ram_top();
- if (locate_coreboot_table() >= 0)
+ addr = locate_coreboot_table();
+ if (addr >= 0) {
+ gd->arch.coreboot_table = addr;
gd->flags |= GD_FLG_SKIP_LL_INIT;
+ }
return 0;
}
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 5bc251c0dd..3e4044593c 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -123,6 +123,7 @@ struct arch_global_data {
#endif
void *itss_priv; /* Private ITSS data pointer */
ulong acpi_start; /* Start address of ACPI tables */
+ ulong coreboot_table; /* Address of coreboot table */
};
#endif
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 04/10] x86: apl: Adjust FSP-M code to avoid hard-coded address
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
Update this code to calculate the address to use, rather than hard-coding
it. Obtain the requested stack size from the FSP.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v2)
Changes in v2:
- Split out the boot_mode change into a separate patch
arch/x86/cpu/apollolake/fsp_m.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
index e19a2b0826..cef937573b 100644
--- a/arch/x86/cpu/apollolake/fsp_m.c
+++ b/arch/x86/cpu/apollolake/fsp_m.c
@@ -24,7 +24,8 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
cache_ret = prepare_mrc_cache(upd);
if (cache_ret && cache_ret != -ENOENT)
return log_msg_ret("mrc", cache_ret);
- arch->stack_base = (void *)0xfef96000;
+ arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE -
+ arch->stack_size);
arch->boot_loader_tolum_size = 0;
arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION :
FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 03/10] x86: apl: Set the correct boot mode in the FSP-M code
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
If there is MRC information we should run FSP-M with a different
boot_mode flag since it is supposed to do a 'fast path' through the
memory init. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v2)
Changes in v2:
- Add a new commit to handle the boot_mode fix
arch/x86/cpu/apollolake/fsp_m.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
index 65461d85b8..e19a2b0826 100644
--- a/arch/x86/cpu/apollolake/fsp_m.c
+++ b/arch/x86/cpu/apollolake/fsp_m.c
@@ -26,7 +26,8 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
return log_msg_ret("mrc", cache_ret);
arch->stack_base = (void *)0xfef96000;
arch->boot_loader_tolum_size = 0;
- arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
+ arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION :
+ FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
node = dev_ofnode(dev);
if (!ofnode_valid(node))
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 02/10] x86: Add debugging to table writing
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
Writing tables is currently pretty opaque. Add a bit of debugging to the
process so we can see what tables are written and where they start/end in
memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
---
(no changes since v1)
arch/x86/lib/tables.c | 38 ++++++++++++++++++++++++++++----------
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 574d331d76..7bad5dd303 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <log.h>
#include <malloc.h>
#include <smbios.h>
#include <acpi/acpi_table.h>
@@ -20,21 +21,32 @@
*/
typedef ulong (*table_write)(ulong addr);
-static table_write table_write_funcs[] = {
+/**
+ * struct table_info - Information about each table to write
+ *
+ * @name: Name of table (for debugging)
+ * @write: Function to call to write this table
+ */
+struct table_info {
+ const char *name;
+ table_write write;
+};
+
+static struct table_info table_list[] = {
#ifdef CONFIG_GENERATE_PIRQ_TABLE
- write_pirq_routing_table,
+ { "pirq", write_pirq_routing_table },
#endif
#ifdef CONFIG_GENERATE_SFI_TABLE
- write_sfi_table,
+ { "sfi", write_sfi_table, },
#endif
#ifdef CONFIG_GENERATE_MP_TABLE
- write_mp_table,
+ { "mp", write_mp_table, },
#endif
#ifdef CONFIG_GENERATE_ACPI_TABLE
- write_acpi_tables,
+ { "acpi", write_acpi_tables, },
#endif
#ifdef CONFIG_GENERATE_SMBIOS_TABLE
- write_smbios_table,
+ { "smbios", write_smbios_table, },
#endif
};
@@ -58,19 +70,22 @@ void write_tables(void)
u32 rom_table_end;
#ifdef CONFIG_SEABIOS
u32 high_table, table_size;
- struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1];
+ struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1];
#endif
int i;
- for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) {
- rom_table_end = table_write_funcs[i](rom_table_start);
+ debug("Writing tables to %x:\n", rom_table_start);
+ for (i = 0; i < ARRAY_SIZE(table_list); i++) {
+ const struct table_info *table = &table_list[i];
+
+ rom_table_end = table->write(rom_table_start);
rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN);
#ifdef CONFIG_SEABIOS
table_size = rom_table_end - rom_table_start;
high_table = (u32)high_table_malloc(table_size);
if (high_table) {
- table_write_funcs[i](high_table);
+ table->write(high_table);
cfg_tables[i].start = high_table;
cfg_tables[i].size = table_size;
@@ -79,6 +94,8 @@ void write_tables(void)
}
#endif
+ debug("- wrote '%s' to %x, end %x\n", table->name,
+ rom_table_start, rom_table_end);
rom_table_start = rom_table_end;
}
@@ -87,4 +104,5 @@ void write_tables(void)
cfg_tables[i].size = 0;
write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
#endif
+ debug("- done writing tables\n");
}
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 01/10] x86: apl: Fix save/restore of ITSS priorities
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20200717032239.197695-1-sjg@chromium.org>
The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.
Fix this by allocating space in the relocated memory for the ITSS data.
Save it there and access it from the driver after relocation.
This fixes interrupt handling on coral.
Also drop the log_msg_ret() in irq_first_device_type() since this function
can be called speculatively in places where we are not sure if there is
an interrupt controller of that type. The resulting log errors are
confusing when there is no error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
---
(no changes since v2)
Changes in v2:
- Add mention of why log_msg_ret() is dropped
arch/x86/cpu/apollolake/fsp_s.c | 11 +++++------
arch/x86/cpu/cpu.c | 18 +++++++++++++++---
arch/x86/cpu/intel_common/itss.c | 25 +++++++++++++++++++++++--
arch/x86/include/asm/global_data.h | 1 +
arch/x86/include/asm/itss.h | 2 +-
drivers/misc/irq-uclass.c | 2 +-
6 files changed, 46 insertions(+), 13 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 3a54297a28..e54b0ac104 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -160,11 +160,6 @@ int arch_fsps_preinit(void)
ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
if (ret)
return log_msg_ret("no itss", ret);
- /*
- * Snapshot the current GPIO IRQ polarities. FSP is setting a default
- * policy that doesn't honour boards' requirements
- */
- irq_snapshot_polarities(itss);
/*
* Clear the GPI interrupt status and enable registers. These
@@ -203,7 +198,11 @@ int arch_fsp_init_r(void)
ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
if (ret)
return log_msg_ret("no itss", ret);
- /* Restore GPIO IRQ polarities back to previous settings */
+
+ /*
+ * Restore GPIO IRQ polarities back to previous settings. This was
+ * stored in reserve_arch() - see X86_IRQT_ITSS
+ */
irq_restore_polarities(itss);
/* soc_init() */
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 23a4d633d2..9ef797b41b 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -25,6 +25,7 @@
#include <dm.h>
#include <errno.h>
#include <init.h>
+#include <irq.h>
#include <log.h>
#include <malloc.h>
#include <syscon.h>
@@ -269,9 +270,11 @@ int cpu_init_r(void)
#ifndef CONFIG_EFI_STUB
int reserve_arch(void)
{
-#ifdef CONFIG_ENABLE_MRC_CACHE
- mrccache_reserve();
-#endif
+ struct udevice *itss;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
+ mrccache_reserve();
#ifdef CONFIG_SEABIOS
high_table_reserve();
@@ -288,6 +291,15 @@ int reserve_arch(void)
fsp_save_s3_stack();
}
}
+ ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
+ if (!ret) {
+ /*
+ * Snapshot the current GPIO IRQ polarities. FSP-S is about to
+ * run and will set a default policy that doesn't honour boards'
+ * requirements
+ */
+ irq_snapshot_polarities(itss);
+ }
return 0;
}
diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c
index 963afa8f5b..fe84ebe29f 100644
--- a/arch/x86/cpu/intel_common/itss.c
+++ b/arch/x86/cpu/intel_common/itss.c
@@ -65,14 +65,23 @@ static int snapshot_polarities(struct udevice *dev)
int i;
reg_start = start / IRQS_PER_IPC;
- reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
+ reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
+ log_info("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot);
for (i = reg_start; i < reg_end; i++) {
uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
priv->irq_snapshot[i] = pcr_read32(dev, reg);
+ log_debug(" - %d, reg %x: irq_snapshot[i] %x\n", i, reg,
+ priv->irq_snapshot[i]);
}
+ /* Save the snapshot for use after relocation */
+ gd->start_addr_sp -= sizeof(*priv);
+ gd->start_addr_sp &= ~0xf;
+ gd->arch.itss_priv = (void *)gd->start_addr_sp;
+ memcpy(gd->arch.itss_priv, priv, sizeof(*priv));
+
return 0;
}
@@ -91,16 +100,26 @@ static void show_polarities(struct udevice *dev, const char *msg)
static int restore_polarities(struct udevice *dev)
{
struct itss_priv *priv = dev_get_priv(dev);
+ struct itss_priv *old_priv;
const int start = GPIO_IRQ_START;
const int end = GPIO_IRQ_END;
int reg_start;
int reg_end;
int i;
+ /* Get the snapshot which was stored by the pre-reloc device */
+ old_priv = gd->arch.itss_priv;
+ if (!old_priv)
+ return log_msg_ret("priv", -EFAULT);
+ memcpy(priv->irq_snapshot, old_priv->irq_snapshot,
+ sizeof(priv->irq_snapshot));
+
show_polarities(dev, "Before");
+ log_info("priv->irq_snapshot %p\n", priv->irq_snapshot);
reg_start = start / IRQS_PER_IPC;
- reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
+ reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
+
for (i = reg_start; i < reg_end; i++) {
u32 mask;
@@ -125,6 +144,8 @@ static int restore_polarities(struct udevice *dev)
mask &= ~((1U << irq_start) - 1);
reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
+ log_debug(" - %d, reg %x: mask %x, irq_snapshot[i] %x\n",
+ i, reg, mask, priv->irq_snapshot[i]);
pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
}
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 0e64c8a46d..5bc251c0dd 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -121,6 +121,7 @@ struct arch_global_data {
#ifdef CONFIG_FSP_VERSION2
struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */
#endif
+ void *itss_priv; /* Private ITSS data pointer */
ulong acpi_start; /* Start address of ACPI tables */
};
diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h
index c75d8fe8c2..f7d3240384 100644
--- a/arch/x86/include/asm/itss.h
+++ b/arch/x86/include/asm/itss.h
@@ -16,7 +16,7 @@
#define ITSS_MAX_IRQ 119
#define IRQS_PER_IPC 32
-#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC)
+#define NUM_IPC_REGS DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC)
/* Max PXRC registers in ITSS */
#define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
index 8727a33dd9..94fa233f19 100644
--- a/drivers/misc/irq-uclass.c
+++ b/drivers/misc/irq-uclass.c
@@ -168,7 +168,7 @@ int irq_first_device_type(enum irq_dev_t type, struct udevice **devp)
ret = uclass_first_device_drvdata(UCLASS_IRQ, type, devp);
if (ret)
- return log_msg_ret("find", ret);
+ return ret;
return 0;
}
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply related
* [PATCH v3 00/10] x86: Programmatic generation of ACPI tables (Part C)
From: Simon Glass @ 2020-07-17 3:22 UTC (permalink / raw)
To: u-boot
This series is split off from the original ACPI series and renumbered to
version 1.
It includes functions for generating more ACPI constructs as well as I2C,
GPIO and sound support. There are also quite a few patches related to
getting coral to work correctly with ACPI.
Changes in v3:
- Update the commit message with an explanation of GD_FLG_SKIP_LL_INIT
- Rebase to x86/master
Changes in v2:
- Add mention of why log_msg_ret() is dropped
- Add a new commit to handle the boot_mode fix
- Split out the boot_mode change into a separate patch
- Remove the function from zimage.c also
- Use ACPI_MADT_REV_ACPI_3_0 instead of the open-coded value
- Don't enable this for qemu
Simon Glass (10):
x86: apl: Fix save/restore of ITSS priorities
x86: Add debugging to table writing
x86: apl: Set the correct boot mode in the FSP-M code
x86: apl: Adjust FSP-M code to avoid hard-coded address
x86: Store the coreboot table address in global_data
x86: Update the comment about booting for FSP2
x86: Drop setup_pcat_compatibility()
x86: acpi: Correct the version of the MADT
x86: Rename board_final_cleanup() to board_final_init()
acpi: Enable ACPI table generation by default on x86
arch/Kconfig | 1 +
arch/x86/cpu/apollolake/fsp_m.c | 6 +++--
arch/x86/cpu/apollolake/fsp_s.c | 11 ++++-----
arch/x86/cpu/coreboot/coreboot.c | 4 ++--
arch/x86/cpu/coreboot/tables.c | 8 ++++++-
arch/x86/cpu/cpu.c | 26 ++++++++++++++------
arch/x86/cpu/efi/app.c | 2 +-
arch/x86/cpu/i386/cpu.c | 7 +++++-
arch/x86/cpu/intel_common/itss.c | 25 ++++++++++++++++++--
arch/x86/cpu/quark/quark.c | 2 +-
arch/x86/cpu/start.S | 1 +
arch/x86/include/asm/global_data.h | 2 ++
arch/x86/include/asm/itss.h | 2 +-
arch/x86/include/asm/u-boot-x86.h | 2 --
arch/x86/lib/acpi_table.c | 2 +-
arch/x86/lib/fsp/fsp_common.c | 2 +-
arch/x86/lib/tables.c | 38 ++++++++++++++++++++++--------
arch/x86/lib/zimage.c | 10 --------
drivers/core/Kconfig | 2 +-
drivers/misc/irq-uclass.c | 2 +-
20 files changed, 105 insertions(+), 50 deletions(-)
--
2.28.0.rc0.105.gf9edc3c819-goog
^ permalink raw reply
* Re: [PATCH V5 1/4] mm/debug_vm_pgtable: Add tests validating arch helpers for core MM features
From: Anshuman Khandual @ 2020-07-17 3:20 UTC (permalink / raw)
To: Steven Price, linux-mm
Cc: Benjamin Herrenschmidt, Heiko Carstens, Paul Mackerras,
H. Peter Anvin, agordeev, Will Deacon, linux-riscv, linux-arch,
linux-s390, Michael Ellerman, x86, christophe.leroy,
Mike Rapoport, Christian Borntraeger, Ingo Molnar,
gerald.schaefer, ziy, Catalin Marinas, linux-snps-arc,
Vasily Gorbik, cai, Paul Walmsley, Kirill A . Shutemov,
Thomas Gleixner, linux-arm-kernel, christophe.leroy, Vineet Gupta,
linux-kernel, Palmer Dabbelt, aneesh.kumar, Borislav Petkov,
Andrew Morton, linuxppc-dev, rppt
In-Reply-To: <2ff756c5-28e2-b64a-3788-260ba30c6409@arm.com>
On 07/16/2020 07:44 PM, Steven Price wrote:
> On 13/07/2020 04:23, Anshuman Khandual wrote:
>> This adds new tests validating arch page table helpers for these following
>> core memory features. These tests create and test specific mapping types at
>> various page table levels.
>>
>> 1. SPECIAL mapping
>> 2. PROTNONE mapping
>> 3. DEVMAP mapping
>> 4. SOFTDIRTY mapping
>> 5. SWAP mapping
>> 6. MIGRATION mapping
>> 7. HUGETLB mapping
>> 8. THP mapping
>>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>> Cc: Mike Rapoport <rppt@linux.ibm.com>
>> Cc: Vineet Gupta <vgupta@synopsys.com>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Cc: Paul Mackerras <paulus@samba.org>
>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
>> Cc: Vasily Gorbik <gor@linux.ibm.com>
>> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Borislav Petkov <bp@alien8.de>
>> Cc: "H. Peter Anvin" <hpa@zytor.com>
>> Cc: Kirill A. Shutemov <kirill@shutemov.name>
>> Cc: Paul Walmsley <paul.walmsley@sifive.com>
>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>> Cc: linux-snps-arc@lists.infradead.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Cc: linux-s390@vger.kernel.org
>> Cc: linux-riscv@lists.infradead.org
>> Cc: x86@kernel.org
>> Cc: linux-mm@kvack.org
>> Cc: linux-arch@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Tested-by: Vineet Gupta <vgupta@synopsys.com> #arc
>> Reviewed-by: Zi Yan <ziy@nvidia.com>
>> Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> mm/debug_vm_pgtable.c | 302 +++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 301 insertions(+), 1 deletion(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index 61ab16fb2e36..2fac47db3eb7 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
> [...]
>> +
>> +static void __init pte_swap_tests(unsigned long pfn, pgprot_t prot)
>> +{
>> + swp_entry_t swp;
>> + pte_t pte;
>> +
>> + pte = pfn_pte(pfn, prot);
>> + swp = __pte_to_swp_entry(pte);
>
> Minor issue: this doesn't look necessarily valid - there's no reason a normal PTE can be turned into a swp_entry. In practise this is likely to work on all architectures because there's no reason not to use (at least) all the PFN bits for the swap entry, but it doesn't exactly seem correct.
Agreed, that it is a simple test but nonetheless a valid one which
makes sure that PFN value remained unchanged during pte <---> swp
conversion.
>
> Can we start with a swp_entry_t (from __swp_entry()) and check the round trip of that?
>
> It would also seem sensible to have a check that is_swap_pte(__swp_entry_to_pte(__swp_entry(x,y))) is true.
From past experiences, getting any these new tests involving platform
helpers, working on all existing enabled archs is neither trivial nor
going to be quick. Existing tests here are known to succeed in enabled
platforms. Nonetheless, proposed tests as in the above suggestions do
make sense but will try to accommodate them in a later patch.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply
* Re: [PATCH V5 1/4] mm/debug_vm_pgtable: Add tests validating arch helpers for core MM features
From: Anshuman Khandual @ 2020-07-17 3:20 UTC (permalink / raw)
To: Steven Price, linux-mm
Cc: Benjamin Herrenschmidt, Heiko Carstens, Paul Mackerras,
H. Peter Anvin, agordeev, Will Deacon, linux-riscv, linux-arch,
linux-s390, Michael Ellerman, x86, christophe.leroy,
Mike Rapoport, Christian Borntraeger, Ingo Molnar,
gerald.schaefer, ziy, Catalin Marinas, linux-snps-arc,
Vasily Gorbik, cai, Paul Walmsley, Kirill A . Shutemov,
Thomas Gleixner, linux-arm-kernel, christophe.leroy, Vineet Gupta,
linux-kernel, Palmer Dabbelt, aneesh.kumar, Borislav Petkov,
Andrew Morton, linuxppc-dev, rppt
In-Reply-To: <2ff756c5-28e2-b64a-3788-260ba30c6409@arm.com>
On 07/16/2020 07:44 PM, Steven Price wrote:
> On 13/07/2020 04:23, Anshuman Khandual wrote:
>> This adds new tests validating arch page table helpers for these following
>> core memory features. These tests create and test specific mapping types at
>> various page table levels.
>>
>> 1. SPECIAL mapping
>> 2. PROTNONE mapping
>> 3. DEVMAP mapping
>> 4. SOFTDIRTY mapping
>> 5. SWAP mapping
>> 6. MIGRATION mapping
>> 7. HUGETLB mapping
>> 8. THP mapping
>>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>> Cc: Mike Rapoport <rppt@linux.ibm.com>
>> Cc: Vineet Gupta <vgupta@synopsys.com>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Cc: Paul Mackerras <paulus@samba.org>
>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
>> Cc: Vasily Gorbik <gor@linux.ibm.com>
>> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Borislav Petkov <bp@alien8.de>
>> Cc: "H. Peter Anvin" <hpa@zytor.com>
>> Cc: Kirill A. Shutemov <kirill@shutemov.name>
>> Cc: Paul Walmsley <paul.walmsley@sifive.com>
>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>> Cc: linux-snps-arc@lists.infradead.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Cc: linux-s390@vger.kernel.org
>> Cc: linux-riscv@lists.infradead.org
>> Cc: x86@kernel.org
>> Cc: linux-mm@kvack.org
>> Cc: linux-arch@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Tested-by: Vineet Gupta <vgupta@synopsys.com> #arc
>> Reviewed-by: Zi Yan <ziy@nvidia.com>
>> Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> mm/debug_vm_pgtable.c | 302 +++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 301 insertions(+), 1 deletion(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index 61ab16fb2e36..2fac47db3eb7 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
> [...]
>> +
>> +static void __init pte_swap_tests(unsigned long pfn, pgprot_t prot)
>> +{
>> + swp_entry_t swp;
>> + pte_t pte;
>> +
>> + pte = pfn_pte(pfn, prot);
>> + swp = __pte_to_swp_entry(pte);
>
> Minor issue: this doesn't look necessarily valid - there's no reason a normal PTE can be turned into a swp_entry. In practise this is likely to work on all architectures because there's no reason not to use (at least) all the PFN bits for the swap entry, but it doesn't exactly seem correct.
Agreed, that it is a simple test but nonetheless a valid one which
makes sure that PFN value remained unchanged during pte <---> swp
conversion.
>
> Can we start with a swp_entry_t (from __swp_entry()) and check the round trip of that?
>
> It would also seem sensible to have a check that is_swap_pte(__swp_entry_to_pte(__swp_entry(x,y))) is true.
From past experiences, getting any these new tests involving platform
helpers, working on all existing enabled archs is neither trivial nor
going to be quick. Existing tests here are known to succeed in enabled
platforms. Nonetheless, proposed tests as in the above suggestions do
make sense but will try to accommodate them in a later patch.
_______________________________________________
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
^ permalink raw reply
* Re: [PATCH V5 1/4] mm/debug_vm_pgtable: Add tests validating arch helpers for core MM features
From: Anshuman Khandual @ 2020-07-17 3:20 UTC (permalink / raw)
To: Steven Price, linux-mm
Cc: Catalin Marinas, Heiko Carstens, Paul Mackerras, H. Peter Anvin,
agordeev, Will Deacon, linux-riscv, linux-arch, linux-s390,
Michael Ellerman, x86, christophe.leroy, Mike Rapoport,
Christian Borntraeger, Ingo Molnar, linux-arm-kernel, ziy,
Benjamin Herrenschmidt, linux-snps-arc, Vasily Gorbik, cai,
Paul Walmsley, Kirill A . Shutemov, Thomas Gleixner,
gerald.schaefer, christophe.leroy, Vineet Gupta, linux-kernel,
Palmer Dabbelt, aneesh.kumar, Borislav Petkov, Andrew Morton,
linuxppc-dev, rppt
In-Reply-To: <2ff756c5-28e2-b64a-3788-260ba30c6409@arm.com>
On 07/16/2020 07:44 PM, Steven Price wrote:
> On 13/07/2020 04:23, Anshuman Khandual wrote:
>> This adds new tests validating arch page table helpers for these following
>> core memory features. These tests create and test specific mapping types at
>> various page table levels.
>>
>> 1. SPECIAL mapping
>> 2. PROTNONE mapping
>> 3. DEVMAP mapping
>> 4. SOFTDIRTY mapping
>> 5. SWAP mapping
>> 6. MIGRATION mapping
>> 7. HUGETLB mapping
>> 8. THP mapping
>>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>> Cc: Mike Rapoport <rppt@linux.ibm.com>
>> Cc: Vineet Gupta <vgupta@synopsys.com>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Cc: Paul Mackerras <paulus@samba.org>
>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
>> Cc: Vasily Gorbik <gor@linux.ibm.com>
>> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Borislav Petkov <bp@alien8.de>
>> Cc: "H. Peter Anvin" <hpa@zytor.com>
>> Cc: Kirill A. Shutemov <kirill@shutemov.name>
>> Cc: Paul Walmsley <paul.walmsley@sifive.com>
>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>> Cc: linux-snps-arc@lists.infradead.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Cc: linux-s390@vger.kernel.org
>> Cc: linux-riscv@lists.infradead.org
>> Cc: x86@kernel.org
>> Cc: linux-mm@kvack.org
>> Cc: linux-arch@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Tested-by: Vineet Gupta <vgupta@synopsys.com> #arc
>> Reviewed-by: Zi Yan <ziy@nvidia.com>
>> Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> mm/debug_vm_pgtable.c | 302 +++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 301 insertions(+), 1 deletion(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index 61ab16fb2e36..2fac47db3eb7 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
> [...]
>> +
>> +static void __init pte_swap_tests(unsigned long pfn, pgprot_t prot)
>> +{
>> + swp_entry_t swp;
>> + pte_t pte;
>> +
>> + pte = pfn_pte(pfn, prot);
>> + swp = __pte_to_swp_entry(pte);
>
> Minor issue: this doesn't look necessarily valid - there's no reason a normal PTE can be turned into a swp_entry. In practise this is likely to work on all architectures because there's no reason not to use (at least) all the PFN bits for the swap entry, but it doesn't exactly seem correct.
Agreed, that it is a simple test but nonetheless a valid one which
makes sure that PFN value remained unchanged during pte <---> swp
conversion.
>
> Can we start with a swp_entry_t (from __swp_entry()) and check the round trip of that?
>
> It would also seem sensible to have a check that is_swap_pte(__swp_entry_to_pte(__swp_entry(x,y))) is true.
From past experiences, getting any these new tests involving platform
helpers, working on all existing enabled archs is neither trivial nor
going to be quick. Existing tests here are known to succeed in enabled
platforms. Nonetheless, proposed tests as in the above suggestions do
make sense but will try to accommodate them in a later patch.
^ permalink raw reply
* Re: [PATCH V5 1/4] mm/debug_vm_pgtable: Add tests validating arch helpers for core MM features
From: Anshuman Khandual @ 2020-07-17 3:20 UTC (permalink / raw)
To: Steven Price, linux-mm
Cc: Catalin Marinas, Heiko Carstens, Paul Mackerras, H. Peter Anvin,
agordeev, Will Deacon, linux-riscv, linux-arch, linux-s390,
Michael Ellerman, x86, christophe.leroy, Mike Rapoport,
Christian Borntraeger, Ingo Molnar, linux-arm-kernel, ziy,
Benjamin Herrenschmidt, linux-snps-arc, Vasily Gorbik, cai,
Paul Walmsley, Kirill A . Shutemov
In-Reply-To: <2ff756c5-28e2-b64a-3788-260ba30c6409@arm.com>
On 07/16/2020 07:44 PM, Steven Price wrote:
> On 13/07/2020 04:23, Anshuman Khandual wrote:
>> This adds new tests validating arch page table helpers for these following
>> core memory features. These tests create and test specific mapping types at
>> various page table levels.
>>
>> 1. SPECIAL mapping
>> 2. PROTNONE mapping
>> 3. DEVMAP mapping
>> 4. SOFTDIRTY mapping
>> 5. SWAP mapping
>> 6. MIGRATION mapping
>> 7. HUGETLB mapping
>> 8. THP mapping
>>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com>
>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>> Cc: Mike Rapoport <rppt@linux.ibm.com>
>> Cc: Vineet Gupta <vgupta@synopsys.com>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Cc: Paul Mackerras <paulus@samba.org>
>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
>> Cc: Vasily Gorbik <gor@linux.ibm.com>
>> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Borislav Petkov <bp@alien8.de>
>> Cc: "H. Peter Anvin" <hpa@zytor.com>
>> Cc: Kirill A. Shutemov <kirill@shutemov.name>
>> Cc: Paul Walmsley <paul.walmsley@sifive.com>
>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>> Cc: linux-snps-arc@lists.infradead.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Cc: linux-s390@vger.kernel.org
>> Cc: linux-riscv@lists.infradead.org
>> Cc: x86@kernel.org
>> Cc: linux-mm@kvack.org
>> Cc: linux-arch@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Tested-by: Vineet Gupta <vgupta@synopsys.com> #arc
>> Reviewed-by: Zi Yan <ziy@nvidia.com>
>> Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> mm/debug_vm_pgtable.c | 302 +++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 301 insertions(+), 1 deletion(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index 61ab16fb2e36..2fac47db3eb7 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
> [...]
>> +
>> +static void __init pte_swap_tests(unsigned long pfn, pgprot_t prot)
>> +{
>> + swp_entry_t swp;
>> + pte_t pte;
>> +
>> + pte = pfn_pte(pfn, prot);
>> + swp = __pte_to_swp_entry(pte);
>
> Minor issue: this doesn't look necessarily valid - there's no reason a normal PTE can be turned into a swp_entry. In practise this is likely to work on all architectures because there's no reason not to use (at least) all the PFN bits for the swap entry, but it doesn't exactly seem correct.
Agreed, that it is a simple test but nonetheless a valid one which
makes sure that PFN value remained unchanged during pte <---> swp
conversion.
>
> Can we start with a swp_entry_t (from __swp_entry()) and check the round trip of that?
>
> It would also seem sensible to have a check that is_swap_pte(__swp_entry_to_pte(__swp_entry(x,y))) is true.
From past experiences, getting any these new tests involving platform
helpers, working on all existing enabled archs is neither trivial nor
going to be quick. Existing tests here are known to succeed in enabled
platforms. Nonetheless, proposed tests as in the above suggestions do
make sense but will try to accommodate them in a later patch.
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