* [xen-unstable test] 167605: tolerable FAIL
From: osstest service owner @ 2022-01-05 11:32 UTC (permalink / raw)
To: xen-devel
flight 167605 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/167605/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stop fail like 167603
test-armhf-armhf-libvirt 16 saverestore-support-check fail like 167603
test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 167603
test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stop fail like 167603
test-amd64-i386-xl-qemut-ws16-amd64 19 guest-stop fail like 167603
test-amd64-i386-xl-qemut-win7-amd64 19 guest-stop fail like 167603
test-amd64-i386-xl-qemuu-win7-amd64 19 guest-stop fail like 167603
test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stop fail like 167603
test-armhf-armhf-libvirt-qcow2 15 saverestore-support-check fail like 167603
test-armhf-armhf-libvirt-raw 15 saverestore-support-check fail like 167603
test-amd64-i386-xl-qemuu-ws16-amd64 19 guest-stop fail like 167603
test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail like 167603
test-arm64-arm64-xl-seattle 15 migrate-support-check fail never pass
test-arm64-arm64-xl-seattle 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-xsm 15 migrate-support-check fail never pass
test-amd64-i386-libvirt-xsm 15 migrate-support-check fail never pass
test-amd64-i386-libvirt 15 migrate-support-check fail never pass
test-amd64-i386-xl-pvshim 14 guest-start fail never pass
test-arm64-arm64-xl 15 migrate-support-check fail never pass
test-arm64-arm64-xl 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-thunderx 15 migrate-support-check fail never pass
test-arm64-arm64-xl-thunderx 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-xl-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit1 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit1 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit2 15 migrate-support-check fail never pass
test-arm64-arm64-libvirt-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit2 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass
test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass
test-amd64-i386-libvirt-raw 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-multivcpu 15 migrate-support-check fail never pass
test-armhf-armhf-xl-multivcpu 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-libvirt 15 migrate-support-check fail never pass
test-armhf-armhf-xl-rtds 15 migrate-support-check fail never pass
test-armhf-armhf-xl-rtds 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit1 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit1 16 saverestore-support-check fail never pass
test-armhf-armhf-xl 15 migrate-support-check fail never pass
test-armhf-armhf-xl 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-cubietruck 15 migrate-support-check fail never pass
test-armhf-armhf-xl-cubietruck 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-vhd 14 migrate-support-check fail never pass
test-armhf-armhf-xl-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit2 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit2 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-arndale 15 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt-qcow2 14 migrate-support-check fail never pass
test-armhf-armhf-libvirt-raw 14 migrate-support-check fail never pass
version targeted for testing:
xen af0c5430a82c77432729d61c9b409dd32c477b20
baseline version:
xen af0c5430a82c77432729d61c9b409dd32c477b20
Last test of basis 167605 2022-01-05 01:54:06 Z 0 days
Testing same since (not found) 0 attempts
jobs:
build-amd64-xsm pass
build-arm64-xsm pass
build-i386-xsm pass
build-amd64-xtf pass
build-amd64 pass
build-arm64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-arm64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-prev pass
build-i386-prev pass
build-amd64-pvops pass
build-arm64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
test-xtf-amd64-amd64-1 pass
test-xtf-amd64-amd64-2 pass
test-xtf-amd64-amd64-3 pass
test-xtf-amd64-amd64-4 pass
test-xtf-amd64-amd64-5 pass
test-amd64-amd64-xl pass
test-amd64-coresched-amd64-xl pass
test-arm64-arm64-xl pass
test-armhf-armhf-xl pass
test-amd64-i386-xl pass
test-amd64-coresched-i386-xl pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-i386-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-debianhvm-i386-xsm pass
test-amd64-i386-xl-qemut-debianhvm-i386-xsm pass
test-amd64-amd64-xl-qemuu-debianhvm-i386-xsm pass
test-amd64-i386-xl-qemuu-debianhvm-i386-xsm pass
test-amd64-amd64-libvirt-xsm pass
test-arm64-arm64-libvirt-xsm pass
test-amd64-i386-libvirt-xsm pass
test-amd64-amd64-xl-xsm pass
test-arm64-arm64-xl-xsm pass
test-amd64-i386-xl-xsm pass
test-amd64-amd64-qemuu-nested-amd fail
test-amd64-amd64-xl-pvhv2-amd pass
test-amd64-i386-qemut-rhel6hvm-amd pass
test-amd64-i386-qemuu-rhel6hvm-amd pass
test-amd64-amd64-dom0pvh-xl-amd pass
test-amd64-amd64-xl-qemut-debianhvm-amd64 pass
test-amd64-i386-xl-qemut-debianhvm-amd64 pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64 pass
test-amd64-i386-xl-qemuu-debianhvm-amd64 pass
test-amd64-i386-freebsd10-amd64 pass
test-amd64-amd64-qemuu-freebsd11-amd64 pass
test-amd64-amd64-qemuu-freebsd12-amd64 pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
test-amd64-amd64-xl-qemut-win7-amd64 fail
test-amd64-i386-xl-qemut-win7-amd64 fail
test-amd64-amd64-xl-qemuu-win7-amd64 fail
test-amd64-i386-xl-qemuu-win7-amd64 fail
test-amd64-amd64-xl-qemut-ws16-amd64 fail
test-amd64-i386-xl-qemut-ws16-amd64 fail
test-amd64-amd64-xl-qemuu-ws16-amd64 fail
test-amd64-i386-xl-qemuu-ws16-amd64 fail
test-armhf-armhf-xl-arndale pass
test-amd64-amd64-examine-bios pass
test-amd64-i386-examine-bios pass
test-amd64-amd64-xl-credit1 pass
test-arm64-arm64-xl-credit1 pass
test-armhf-armhf-xl-credit1 pass
test-amd64-amd64-xl-credit2 pass
test-arm64-arm64-xl-credit2 pass
test-armhf-armhf-xl-credit2 pass
test-armhf-armhf-xl-cubietruck pass
test-amd64-amd64-xl-qemuu-dmrestrict-amd64-dmrestrict pass
test-amd64-i386-xl-qemuu-dmrestrict-amd64-dmrestrict pass
test-amd64-amd64-examine pass
test-arm64-arm64-examine pass
test-armhf-armhf-examine pass
test-amd64-i386-examine pass
test-amd64-i386-freebsd10-i386 pass
test-amd64-amd64-qemuu-nested-intel pass
test-amd64-amd64-xl-pvhv2-intel pass
test-amd64-i386-qemut-rhel6hvm-intel pass
test-amd64-i386-qemuu-rhel6hvm-intel pass
test-amd64-amd64-dom0pvh-xl-intel pass
test-amd64-amd64-libvirt pass
test-armhf-armhf-libvirt pass
test-amd64-i386-libvirt pass
test-amd64-amd64-livepatch pass
test-amd64-i386-livepatch pass
test-amd64-amd64-migrupgrade pass
test-amd64-i386-migrupgrade pass
test-amd64-amd64-xl-multivcpu pass
test-armhf-armhf-xl-multivcpu pass
test-amd64-amd64-pair pass
test-amd64-i386-pair pass
test-amd64-amd64-libvirt-pair pass
test-amd64-i386-libvirt-pair pass
test-amd64-amd64-xl-pvshim pass
test-amd64-i386-xl-pvshim fail
test-amd64-amd64-pygrub pass
test-armhf-armhf-libvirt-qcow2 pass
test-amd64-amd64-xl-qcow2 pass
test-arm64-arm64-libvirt-raw pass
test-armhf-armhf-libvirt-raw pass
test-amd64-i386-libvirt-raw pass
test-amd64-amd64-xl-rtds pass
test-armhf-armhf-xl-rtds pass
test-arm64-arm64-xl-seattle pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64-shadow pass
test-amd64-i386-xl-qemuu-debianhvm-amd64-shadow pass
test-amd64-amd64-xl-shadow pass
test-amd64-i386-xl-shadow pass
test-arm64-arm64-xl-thunderx pass
test-amd64-amd64-examine-uefi pass
test-amd64-i386-examine-uefi pass
test-amd64-amd64-libvirt-vhd pass
test-arm64-arm64-xl-vhd pass
test-armhf-armhf-xl-vhd pass
test-amd64-i386-xl-vhd pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Published tested tree is already up to date.
^ permalink raw reply
* [PATCH 1/8] ASoC: cs35l41: Add cs35l51/53 IDs
From: Charles Keepax @ 2022-01-05 11:30 UTC (permalink / raw)
To: broonie; +Cc: patches, alsa-devel, david.rhodes, lgirdwood, tiwai
In-Reply-To: <20220105113026.18955-1-ckeepax@opensource.cirrus.com>
From: David Rhodes <david.rhodes@cirrus.com>
Add IDs for the CS35L51/53 variants, the functionality is shared with
CS35L41.
Signed-off-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
sound/soc/codecs/cs35l41-i2c.c | 2 ++
sound/soc/codecs/cs35l41-spi.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/sound/soc/codecs/cs35l41-i2c.c b/sound/soc/codecs/cs35l41-i2c.c
index de5c8612f0307..eb8dfb6d9c950 100644
--- a/sound/soc/codecs/cs35l41-i2c.c
+++ b/sound/soc/codecs/cs35l41-i2c.c
@@ -22,6 +22,8 @@
static const struct i2c_device_id cs35l41_id_i2c[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
+ { "cs35l51", 0 },
+ { "cs35l53", 0 },
{}
};
diff --git a/sound/soc/codecs/cs35l41-spi.c b/sound/soc/codecs/cs35l41-spi.c
index c157153f28d87..86bbe2fba956e 100644
--- a/sound/soc/codecs/cs35l41-spi.c
+++ b/sound/soc/codecs/cs35l41-spi.c
@@ -20,6 +20,8 @@
static const struct spi_device_id cs35l41_id_spi[] = {
{ "cs35l40", 0 },
{ "cs35l41", 0 },
+ { "cs35l51", 0 },
+ { "cs35l53", 0 },
{}
};
--
2.11.0
^ permalink raw reply related
* [PATCH 5/8] firmware: cs_dsp: Clear core reset for cache
From: Charles Keepax @ 2022-01-05 11:30 UTC (permalink / raw)
To: broonie; +Cc: patches, alsa-devel, david.rhodes, lgirdwood, tiwai
In-Reply-To: <20220105113026.18955-1-ckeepax@opensource.cirrus.com>
If the Halo registers are kept in the register cache the
HALO_CORE_RESET bit will be retained as 1 after reset is triggered in
cs_dsp_halo_start_core. This will cause subsequent writes to reset
the core which is not desired. Apart from this bit the rest of the
register bits are cacheable, so for safety sake clear the bit to
ensure the cache is consistent.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
drivers/firmware/cirrus/cs_dsp.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/firmware/cirrus/cs_dsp.c b/drivers/firmware/cirrus/cs_dsp.c
index 5af8171d6cedf..e48108e694f8d 100644
--- a/drivers/firmware/cirrus/cs_dsp.c
+++ b/drivers/firmware/cirrus/cs_dsp.c
@@ -2744,10 +2744,16 @@ EXPORT_SYMBOL_GPL(cs_dsp_stop);
static int cs_dsp_halo_start_core(struct cs_dsp *dsp)
{
- return regmap_update_bits(dsp->regmap,
- dsp->base + HALO_CCM_CORE_CONTROL,
- HALO_CORE_RESET | HALO_CORE_EN,
- HALO_CORE_RESET | HALO_CORE_EN);
+ int ret;
+
+ ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
+ HALO_CORE_RESET | HALO_CORE_EN,
+ HALO_CORE_RESET | HALO_CORE_EN);
+ if (ret)
+ return ret;
+
+ return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
+ HALO_CORE_RESET, 0);
}
static void cs_dsp_halo_stop_core(struct cs_dsp *dsp)
--
2.11.0
^ permalink raw reply related
* [PATCH 2/8] ASoC: cs35l41: Remove incorrect comment
From: Charles Keepax @ 2022-01-05 11:30 UTC (permalink / raw)
To: broonie; +Cc: patches, alsa-devel, david.rhodes, lgirdwood, tiwai
In-Reply-To: <20220105113026.18955-1-ckeepax@opensource.cirrus.com>
The IRQ is not used for the PDN_DONE bit, this is polled during the DAPM
sequence, remove the misleading comment.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
sound/soc/codecs/cs35l41.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/sound/soc/codecs/cs35l41.c b/sound/soc/codecs/cs35l41.c
index d9e6e84e64d0b..980294c1bcdba 100644
--- a/sound/soc/codecs/cs35l41.c
+++ b/sound/soc/codecs/cs35l41.c
@@ -1338,8 +1338,6 @@ int cs35l41_probe(struct cs35l41_private *cs35l41,
ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq,
IRQF_ONESHOT | IRQF_SHARED | irq_pol,
"cs35l41", cs35l41);
-
- /* CS35L41 needs INT for PDN_DONE */
if (ret != 0) {
dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret);
goto err;
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v2 0/2]kernel-shark:add new plugin for xenomai cobalt_switch_context events
From: Yordan Karadzhov @ 2022-01-05 11:32 UTC (permalink / raw)
To: Hongzhan Chen, linux-trace-devel
In-Reply-To: <20211222064014.4471-1-hongzhan.chen@intel.com>
On 22.12.21 г. 8:40 ч., Hongzhan Chen wrote:
> 1. To avoid code duplication, move some common APIs and definitions
> out to create new files and share with other plugins.
> 2. add new plugin for handling xenomai cobalt_switch_context events
> to visualize OOB state of RT tasks.
>
> I tried to move common APIs and definitions to KsPlugins.cpp/hpp but
> found these definitions finally depend on KsMainWindow object used
> by _doubleClick of LatencyBox assigned by plugin_set_gui_ptr via
> KSHARK_MENU_PLUGIN_INITIALIZER.
> I do not know how to remove this dependency so I create new files to
> avoid code duplication. Please suggest if there is better way.
Hi Hongzhan,
Indeed, this turns to be a bit trickier than I expected, but it is possible.
I will comment in the patch.
thanks,
Yordan
>
> Hongzhan Chen (2):
> kernel-shark: Move common APIs and definitions out to avoid
> duplication
> kernel-shark: Add plugin for handling Xenomai cobalt_context_switch
>
> src/libkshark-tepdata.c | 1 +
> src/plugins/CMakeLists.txt | 6 +-
> src/plugins/CobaltSwitchEvents.cpp | 125 +++++++++++++++
> src/plugins/CommonSched.hpp | 99 ++++++++++++
> src/plugins/SchedEvents.cpp | 87 +----------
> src/plugins/common_sched.c | 37 +++++
> src/plugins/common_sched.h | 50 ++++++
> src/plugins/sched_events.c | 37 +----
> src/plugins/sched_events.h | 12 +-
> src/plugins/xenomai_cobalt_switch_events.c | 169 +++++++++++++++++++++
> src/plugins/xenomai_cobalt_switch_events.h | 54 +++++++
> 11 files changed, 545 insertions(+), 132 deletions(-)
> create mode 100644 src/plugins/CobaltSwitchEvents.cpp
> create mode 100644 src/plugins/CommonSched.hpp
> create mode 100644 src/plugins/common_sched.c
> create mode 100644 src/plugins/common_sched.h
> create mode 100644 src/plugins/xenomai_cobalt_switch_events.c
> create mode 100644 src/plugins/xenomai_cobalt_switch_events.h
>
^ permalink raw reply
* [PATCH 6/8] ASoC: wm_adsp: Add support for "toggle" preloaders
From: Charles Keepax @ 2022-01-05 11:30 UTC (permalink / raw)
To: broonie; +Cc: patches, alsa-devel, david.rhodes, lgirdwood, tiwai
In-Reply-To: <20220105113026.18955-1-ckeepax@opensource.cirrus.com>
In the case a device can support retaining the firmware memory across
low power states it is useful for the preloader widget to only power up
whilst actually loading/unloading the core, as opposed to the normal
operation where the widget is powered for the entire time a firmware is
preloaded onto the core. Add support for this mode and a flag to enable
it.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
sound/soc/codecs/wm_adsp.c | 14 +++++++++++---
sound/soc/codecs/wm_adsp.h | 8 ++++++++
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index c3112bf238666..f3672e3d1703e 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -896,11 +896,12 @@ int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
struct wm_adsp *dsp = &dsps[mc->shift - 1];
char preload[32];
- snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->cs_dsp.name);
+ if (dsp->preloaded == ucontrol->value.integer.value[0])
+ return 0;
- dsp->preloaded = ucontrol->value.integer.value[0];
+ snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->cs_dsp.name);
- if (ucontrol->value.integer.value[0])
+ if (ucontrol->value.integer.value[0] || dsp->toggle_preload)
snd_soc_component_force_enable_pin(component, preload);
else
snd_soc_component_disable_pin(component, preload);
@@ -909,6 +910,13 @@ int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
flush_work(&dsp->boot_work);
+ dsp->preloaded = ucontrol->value.integer.value[0];
+
+ if (dsp->toggle_preload) {
+ snd_soc_component_disable_pin(component, preload);
+ snd_soc_dapm_sync(dapm);
+ }
+
return 0;
}
EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h
index 0e2f113bd3422..7f4fabbc6ad3a 100644
--- a/sound/soc/codecs/wm_adsp.h
+++ b/sound/soc/codecs/wm_adsp.h
@@ -41,6 +41,14 @@ struct wm_adsp {
struct list_head compr_list;
struct list_head buffer_list;
+
+ /*
+ * Flag indicating the preloader widget only needs power toggled
+ * on state change rather than held on for the duration of the
+ * preload, useful for devices that can retain firmware memory
+ * across power down.
+ */
+ bool toggle_preload;
};
#define WM_ADSP1(wname, num) \
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 1/2] drm/bridge: anx7625: add HDCP support
From: Xin Ji @ 2022-01-05 11:31 UTC (permalink / raw)
To: Robert Foss
Cc: narmstrong, dan.carpenter, Laurent.pinchart, jonas,
jernej.skrabec, airlied, daniel, sam, pihsun, tzungbi, maxime,
drinkcat, hsinyi, dri-devel, linux-kernel, bliang, qwen
In-Reply-To: <CAG3jFysy1BcykodMWRnvB-BJj9Jx7yHLbsJu2Kp52n_7kVS4gw@mail.gmail.com>
On Wed, Jan 05, 2022 at 11:32:01AM +0100, Robert Foss wrote:
> On Wed, 5 Jan 2022 at 08:17, Xin Ji <xji@analogixsemi.com> wrote:
> >
> > On Tue, Jan 04, 2022 at 03:50:34PM +0100, Robert Foss wrote:
> > > Hey Xin,
> > Hi Robert Foss, thanks for the reply.
> > As HDCP config interface "anx7625_hdcp_config(..)" need be called in
> > anx7625_connector_atomic_check(...) interface, so I cannot split out
> > atomic conversion patch.
>
> I don't think that's correct, but maybe I'm missing something. The
> atomic conversion patch should be self-contained if done before the
> addition of HDCP support.
Hi Robert Foss, OK, you are right, I'll split out the atomic conversion patch.
Thanks,
Xin
>
> >
> > Thanks,
> > Xin
> > >
> > > On Tue, 9 Nov 2021 at 03:42, Xin Ji <xji@analogixsemi.com> wrote:
> > > >
> > > > This patch provides HDCP setting interface for userspace to dynamic
> > > > enable/disable HDCP function.
> > > >
> > > > Signed-off-by: Xin Ji <xji@analogixsemi.com>
> > > > ---
> > > > drivers/gpu/drm/bridge/analogix/anx7625.c | 368 +++++++++++++++++++++-
> > > > drivers/gpu/drm/bridge/analogix/anx7625.h | 69 +++-
> > > > 2 files changed, 425 insertions(+), 12 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > > index 001fb39d9919..6d93026c2999 100644
> > > > --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > > @@ -26,6 +26,7 @@
> > > > #include <drm/drm_crtc_helper.h>
> > > > #include <drm/drm_dp_helper.h>
> > > > #include <drm/drm_edid.h>
> > > > +#include <drm/drm_hdcp.h>
> > > > #include <drm/drm_mipi_dsi.h>
> > > > #include <drm/drm_of.h>
> > > > #include <drm/drm_panel.h>
> > > > @@ -213,6 +214,60 @@ static int wait_aux_op_finish(struct anx7625_data *ctx)
> > > > return 0;
> > > > }
> > > >
> > > > +static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
> > > > + u8 addrh, u8 addrm, u8 addrl,
> > > > + u8 len, u8 *buf)
> > > > +{
> > > > + struct device *dev = &ctx->client->dev;
> > > > + int ret;
> > > > + u8 cmd;
> > > > +
> > > > + if (len > MAX_DPCD_BUFFER_SIZE) {
> > > > + DRM_DEV_ERROR(dev, "exceed aux buffer len.\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + cmd = ((len - 1) << 4) | 0x09;
> > > > +
> > > > + /* Set command and length */
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_COMMAND, cmd);
> > > > +
> > > > + /* Set aux access address */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_ADDR_7_0, addrl);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_ADDR_15_8, addrm);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_ADDR_19_16, addrh);
> > > > +
> > > > + /* Enable aux access */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
> > > > +
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "cannot access aux related register.\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + usleep_range(2000, 2100);
> > > > +
> > > > + ret = wait_aux_op_finish(ctx);
> > > > + if (ret) {
> > > > + DRM_DEV_ERROR(dev, "aux IO error: wait aux op finish.\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_BUFF_START, len, buf);
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "read dpcd register failed\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static int anx7625_video_mute_control(struct anx7625_data *ctx,
> > > > u8 status)
> > > > {
> > > > @@ -669,6 +724,160 @@ static int anx7625_dpi_config(struct anx7625_data *ctx)
> > > > return ret;
> > > > }
> > > >
> > > > +static int anx7625_read_flash_status(struct anx7625_data *ctx)
> > > > +{
> > > > + return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
> > > > +}
> > > > +
> > > > +static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
> > > > +{
> > > > + int ret, val;
> > > > + struct device *dev = &ctx->client->dev;
> > > > + u8 ident[32];
> > >
> > > Could this hardcoded array length be replaced with FLASH_BUF_LEN?
> > >
> > > > +
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_ADDR_HIGH, 0x91);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_ADDR_LOW, 0xA0);
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "IO error : set key flash address.\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "IO error : set key flash len.\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_FLASH_RW_CTRL, FLASH_READ);
> > > > + ret |= readx_poll_timeout(anx7625_read_flash_status,
> > > > + ctx, val,
> > > > + ((val & FLASH_DONE) || (val < 0)),
> > > > + 2000,
> > > > + 2000 * 150);
> > > > + if (ret) {
> > > > + DRM_DEV_ERROR(dev, "flash read access fail!\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_BUF_BASE_ADDR,
> > > > + FLASH_BUF_LEN, ident);
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "read flash data fail!\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
> > > > + return -EINVAL;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
> > > > +{
> > > > + int ret;
> > > > + struct device *dev = &ctx->client->dev;
> > > > +
> > > > + /* Select HDCP 1.4 KEY */
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_BOOT_RETRY, 0x12);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_LEN_H, HDCP14KEY_SIZE >> 12);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_LEN_L, HDCP14KEY_SIZE >> 4);
> > > > +
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_ADDR_H, 0);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_ADDR_L, 0);
> > > > + /* Enable HDCP 1.4 KEY load */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_CTRL, DECRYPT_EN | LOAD_START);
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "load HDCP 1.4 key done\n");
> > > > + return ret;
> > > > +}
> > > > +
> > > > +static int anx7625_hdcp_config(struct anx7625_data *ctx, bool on)
> > > > +{
> > > > + u8 bcap;
> > > > + int ret;
> > > > + struct device *dev = &ctx->client->dev;
> > > > +
> > > > + if (!on) {
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "disable HDCP 1.4\n");
> > > > +
> > > > + /* Disable HDCP */
> > > > + ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
> > > > + /* Try auth flag */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
> > > > + /* Interrupt for DRM */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
> > > > + if (ret < 0)
> > > > + DRM_DEV_ERROR(dev, "fail to disable HDCP\n");
> > > > +
> > > > + return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
> > > > + TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF);
> > > > + }
> > > > +
> > > > + ret = anx7625_hdcp_key_probe(ctx);
> > > > + if (ret) {
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "no key found, not to do hdcp\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + anx7625_aux_dpcd_read(ctx, 0x06, 0x80, 0x28, 1, &bcap);
> > > > + if (!(bcap & 0x01)) {
> > > > + DRM_WARN("downstream not support HDCP 1.4, cap(%x).\n", bcap);
> > > > + return 0;
> > > > + }
> > > > +
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "enable HDCP 1.4\n");
> > > > +
> > > > + /* First clear HDCP state */
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
> > > > + TX_HDCP_CTRL0,
> > > > + KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
> > > > + usleep_range(1000, 1100);
> > > > + /* Second clear HDCP state */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
> > > > + TX_HDCP_CTRL0,
> > > > + KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
> > > > +
> > > > + /* Set time for waiting KSVR */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
> > > > + SP_TX_WAIT_KSVR_TIME, 0xc8);
> > > > + /* Set time for waiting R0 */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
> > > > + SP_TX_WAIT_R0_TIME, 0xb0);
> > > > + ret |= anx7625_hdcp_key_load(ctx);
> > > > + if (ret) {
> > > > + DRM_WARN("prepare HDCP key failed.\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
> > > > +
> > > > + /* Try auth flag */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
> > > > + /* Interrupt for DRM */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
> > > > + if (ret < 0)
> > > > + DRM_DEV_ERROR(dev, "fail to enable HDCP\n");
> > > > +
> > > > + return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
> > > > + TX_HDCP_CTRL0, HARD_AUTH_EN);
> > > > +}
> > > > +
> > > > static void anx7625_dp_start(struct anx7625_data *ctx)
> > > > {
> > > > int ret;
> > > > @@ -679,6 +888,9 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
> > > > return;
> > > > }
> > > >
> > > > + /* Disable HDCP */
> > > > + anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
> > > > +
> > > > if (ctx->pdata.is_dpi)
> > > > ret = anx7625_dpi_config(ctx);
> > > > else
> > > > @@ -686,6 +898,10 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
> > > >
> > > > if (ret < 0)
> > > > DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
> > > > +
> > > > + ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
> > > > +
> > > > + ctx->dp_en = 1;
> > > > }
> > > >
> > > > static void anx7625_dp_stop(struct anx7625_data *ctx)
> > > > @@ -705,6 +921,10 @@ static void anx7625_dp_stop(struct anx7625_data *ctx)
> > > > ret |= anx7625_video_mute_control(ctx, 1);
> > > > if (ret < 0)
> > > > DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
> > > > +
> > > > + ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
> > > > +
> > > > + ctx->dp_en = 0;
> > > > }
> > > >
> > > > static int sp_tx_rst_aux(struct anx7625_data *ctx)
> > > > @@ -859,7 +1079,7 @@ static int sp_tx_edid_read(struct anx7625_data *ctx,
> > > > AP_AUX_ADDR_7_0, 0x50);
> > > > ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > AP_AUX_ADDR_15_8, 0);
> > > > - ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > AP_AUX_ADDR_19_16, 0xf0);
> > > > if (ret < 0) {
> > > > DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
> > > > @@ -1688,6 +1908,83 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
> > > > return 0;
> > > > }
> > > >
> > > > +void hdcp_check_work_func(struct work_struct *work)
> > > > +{
> > > > + u8 status;
> > > > + struct delayed_work *dwork;
> > > > + struct anx7625_data *ctx;
> > > > + struct device *dev;
> > > > + struct drm_device *drm_dev;
> > > > +
> > > > + dwork = to_delayed_work(work);
> > > > + ctx = container_of(dwork, struct anx7625_data, hdcp_work);
> > > > + dev = &ctx->client->dev;
> > > > +
> > > > + if (!ctx->connector) {
> > > > + DRM_ERROR("HDCP connector is null!");
> > > > + return;
> > > > + }
> > > > +
> > > > + drm_dev = ctx->connector->dev;
> > > > + drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
> > > > + mutex_lock(&ctx->hdcp_wq_lock);
> > > > +
> > > > + status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "sink HDCP status check: %.02x\n", status);
> > > > + if (status & BIT(1)) {
> > > > + ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
> > > > + drm_hdcp_update_content_protection(ctx->connector,
> > > > + ctx->hdcp_cp);
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "update CP to ENABLE\n");
> > > > + }
> > > > +
> > > > + mutex_unlock(&ctx->hdcp_wq_lock);
> > > > + drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
> > > > +}
> > > > +
> > > > +static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
> > > > + struct drm_connector_state *state)
> > > > +{
> > > > + struct device *dev = &ctx->client->dev;
> > > > + int cp;
> > > > +
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "hdcp state check\n");
> > > > + cp = state->content_protection;
> > > > +
> > > > + if (cp == ctx->hdcp_cp)
> > > > + return 0;
> > > > +
> > > > + if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
> > > > + if (ctx->dp_en) {
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "enable HDCP\n");
> > > > + anx7625_hdcp_config(ctx, true);
> > > > +
> > > > + queue_delayed_work(ctx->hdcp_workqueue,
> > > > + &ctx->hdcp_work,
> > > > + msecs_to_jiffies(2000));
> > > > + }
> > > > + }
> > > > +
> > > > + if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> > > > + if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
> > > > + DRM_ERROR("current CP is not ENABLED\n");
> > > > + return -EINVAL;
> > > > + }
> > > > + anx7625_hdcp_config(ctx, false);
> > > > + ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
> > > > + drm_hdcp_update_content_protection(ctx->connector,
> > > > + ctx->hdcp_cp);
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "update CP to UNDESIRE\n");
> > > > + }
> > > > +
> > > > + if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
> > > > + DRM_ERROR("Userspace illegal set to PROTECTION ENABLE\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static int anx7625_bridge_attach(struct drm_bridge *bridge,
> > > > enum drm_bridge_attach_flags flags)
> > > > {
> > > > @@ -1902,25 +2199,58 @@ static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
> > > > return true;
> > > > }
> > > >
> > > > -static void anx7625_bridge_enable(struct drm_bridge *bridge)
> > > > +static int anx7625_bridge_atomic_check(struct drm_bridge *bridge,
> > > > + struct drm_bridge_state *bridge_state,
> > > > + struct drm_crtc_state *crtc_state,
> > > > + struct drm_connector_state *conn_state)
> > > > {
> > > > struct anx7625_data *ctx = bridge_to_anx7625(bridge);
> > > > struct device *dev = &ctx->client->dev;
> > > >
> > > > - DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n");
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "drm bridge atomic check\n");
> > > > + anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
> > > > + &crtc_state->adjusted_mode);
> > > > +
> > > > + return anx7625_connector_atomic_check(ctx, conn_state);
>
> If doing an atomic only conversion patch, the above function call
> could simply be removed.
>
> > > > +}
> > > > +
> > > > +static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge,
> > > > + struct drm_bridge_state *state)
> > > > +{
> > > > + struct anx7625_data *ctx = bridge_to_anx7625(bridge);
> > > > + struct device *dev = &ctx->client->dev;
> > > > + struct drm_connector *connector;
> > > > +
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "drm atomic enable\n");
> > > > +
> > > > + if (!bridge->encoder) {
> > > > + DRM_DEV_ERROR(dev, "Parent encoder object not found");
> > > > + return;
> > > > + }
> > > > +
> > > > + connector = drm_atomic_get_new_connector_for_encoder(state->base.state,
> > > > + bridge->encoder);
> > > > + if (!connector)
> > > > + return;
> > > > +
> > > > + ctx->connector = connector;
> > > > +
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "attached content protection.\n");
> > > >
> > > > pm_runtime_get_sync(dev);
> > > >
> > > > anx7625_dp_start(ctx);
> > > > }
> > > >
> > > > -static void anx7625_bridge_disable(struct drm_bridge *bridge)
> > > > +static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge,
> > > > + struct drm_bridge_state *old)
> > > > {
> > > > struct anx7625_data *ctx = bridge_to_anx7625(bridge);
> > > > struct device *dev = &ctx->client->dev;
> > > >
> > > > DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n");
> > > >
> > > > + ctx->connector = NULL;
> > > > anx7625_dp_stop(ctx);
> > > >
> > > > pm_runtime_put_sync(dev);
> > > > @@ -1950,11 +2280,14 @@ static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge,
> > > >
> > > > static const struct drm_bridge_funcs anx7625_bridge_funcs = {
> > > > .attach = anx7625_bridge_attach,
> > > > - .disable = anx7625_bridge_disable,
> > > > .mode_valid = anx7625_bridge_mode_valid,
> > > > .mode_set = anx7625_bridge_mode_set,
> > > > - .mode_fixup = anx7625_bridge_mode_fixup,
> > > > - .enable = anx7625_bridge_enable,
> > > > + .atomic_check = anx7625_bridge_atomic_check,
> > > > + .atomic_enable = anx7625_bridge_atomic_enable,
> > > > + .atomic_disable = anx7625_bridge_atomic_disable,
> > > > + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> > > > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> > > > + .atomic_reset = drm_atomic_helper_bridge_reset,
> > >
> > > Could this atomic conversion be split out into its own logical patch?
> > >
> > > > .detect = anx7625_bridge_detect,
> > > > .get_edid = anx7625_bridge_get_edid,
> > > > };
> > > > @@ -2134,6 +2467,15 @@ static int anx7625_i2c_probe(struct i2c_client *client,
> > > > anx7625_init_gpio(platform);
> > > >
> > > > mutex_init(&platform->lock);
> > > > + mutex_init(&platform->hdcp_wq_lock);
> > > > +
> > > > + INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
> > > > + platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
> > > > + if (!platform->hdcp_workqueue) {
> > > > + DRM_DEV_ERROR(dev, "fail to create work queue\n");
> > > > + ret = -ENOMEM;
> > > > + goto free_platform;
> > > > + }
> > > >
> > > > platform->pdata.intp_irq = client->irq;
> > > > if (platform->pdata.intp_irq) {
> > > > @@ -2143,7 +2485,7 @@ static int anx7625_i2c_probe(struct i2c_client *client,
> > > > if (!platform->workqueue) {
> > > > DRM_DEV_ERROR(dev, "fail to create work queue\n");
> > > > ret = -ENOMEM;
> > > > - goto free_platform;
> > > > + goto free_hdcp_wq;
> > > > }
> > > >
> > > > ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
> > > > @@ -2213,6 +2555,10 @@ static int anx7625_i2c_probe(struct i2c_client *client,
> > > > if (platform->workqueue)
> > > > destroy_workqueue(platform->workqueue);
> > > >
> > > > +free_hdcp_wq:
> > > > + if (platform->hdcp_workqueue)
> > > > + destroy_workqueue(platform->hdcp_workqueue);
> > > > +
> > > > free_platform:
> > > > kfree(platform);
> > > >
> > > > @@ -2228,6 +2574,12 @@ static int anx7625_i2c_remove(struct i2c_client *client)
> > > > if (platform->pdata.intp_irq)
> > > > destroy_workqueue(platform->workqueue);
> > > >
> > > > + if (platform->hdcp_workqueue) {
> > > > + cancel_delayed_work(&platform->hdcp_work);
> > > > + flush_workqueue(platform->workqueue);
> > > > + destroy_workqueue(platform->workqueue);
> > > > + }
> > > > +
> > > > if (!platform->pdata.low_power_mode)
> > > > pm_runtime_put_sync_suspend(&client->dev);
> > > >
> > > > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
> > > > index 3d79b6fb13c8..89b1b347a463 100644
> > > > --- a/drivers/gpu/drm/bridge/analogix/anx7625.h
> > > > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h
> > > > @@ -59,10 +59,23 @@
> > > >
> > > > /***************************************************************/
> > > > /* Register definition of device address 0x70 */
> > > > -#define I2C_ADDR_70_DPTX 0x70
> > > > -
> > > > -#define SP_TX_LINK_BW_SET_REG 0xA0
> > > > -#define SP_TX_LANE_COUNT_SET_REG 0xA1
> > > > +#define TX_HDCP_CTRL0 0x01
> > > > +#define STORE_AN BIT(7)
> > > > +#define RX_REPEATER BIT(6)
> > > > +#define RE_AUTHEN BIT(5)
> > > > +#define SW_AUTH_OK BIT(4)
> > > > +#define HARD_AUTH_EN BIT(3)
> > > > +#define ENC_EN BIT(2)
> > > > +#define BKSV_SRM_PASS BIT(1)
> > > > +#define KSVLIST_VLD BIT(0)
> > > > +
> > > > +#define SP_TX_WAIT_R0_TIME 0x40
> > > > +#define SP_TX_WAIT_KSVR_TIME 0x42
> > > > +#define SP_TX_SYS_CTRL1_REG 0x80
> > > > +#define HDCP2TX_FW_EN BIT(4)
> > > > +
> > > > +#define SP_TX_LINK_BW_SET_REG 0xA0
> > > > +#define SP_TX_LANE_COUNT_SET_REG 0xA1
> > > >
> > > > #define M_VID_0 0xC0
> > > > #define M_VID_1 0xC1
> > > > @@ -71,6 +84,12 @@
> > > > #define N_VID_1 0xC4
> > > > #define N_VID_2 0xC5
> > > >
> > > > +#define KEY_START_ADDR 0x9000
> > > > +#define KEY_RESERVED 416
> > > > +
> > > > +#define HDCP14KEY_START_ADDR (KEY_START_ADDR + KEY_RESERVED)
> > > > +#define HDCP14KEY_SIZE 624
> > > > +
> > > > /***************************************************************/
> > > > /* Register definition of device address 0x72 */
> > > > #define AUX_RST 0x04
> > > > @@ -155,9 +174,43 @@
> > > >
> > > > #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E
> > > >
> > > > +#define R_BOOT_RETRY 0x00
> > > > +#define R_RAM_ADDR_H 0x01
> > > > +#define R_RAM_ADDR_L 0x02
> > > > +#define R_RAM_LEN_H 0x03
> > > > +#define R_RAM_LEN_L 0x04
> > > > #define FLASH_LOAD_STA 0x05
> > > > #define FLASH_LOAD_STA_CHK BIT(7)
> > > >
> > > > +#define R_RAM_CTRL 0x05
> > > > +/* bit positions */
> > > > +#define FLASH_DONE BIT(7)
> > > > +#define BOOT_LOAD_DONE BIT(6)
> > > > +#define CRC_OK BIT(5)
> > > > +#define LOAD_DONE BIT(4)
> > > > +#define O_RW_DONE BIT(3)
> > > > +#define FUSE_BUSY BIT(2)
> > > > +#define DECRYPT_EN BIT(1)
> > > > +#define LOAD_START BIT(0)
> > > > +
> > > > +#define FLASH_ADDR_HIGH 0x0F
> > > > +#define FLASH_ADDR_LOW 0x10
> > > > +#define FLASH_LEN_HIGH 0x31
> > > > +#define FLASH_LEN_LOW 0x32
> > > > +#define R_FLASH_RW_CTRL 0x33
> > > > +/* bit positions */
> > > > +#define READ_DELAY_SELECT BIT(7)
> > > > +#define GENERAL_INSTRUCTION_EN BIT(6)
> > > > +#define FLASH_ERASE_EN BIT(5)
> > > > +#define RDID_READ_EN BIT(4)
> > > > +#define REMS_READ_EN BIT(3)
> > > > +#define WRITE_STATUS_EN BIT(2)
> > > > +#define FLASH_READ BIT(1)
> > > > +#define FLASH_WRITE BIT(0)
> > > > +
> > > > +#define FLASH_BUF_BASE_ADDR 0x60
> > > > +#define FLASH_BUF_LEN 0x20
> > > > +
> > > > #define XTAL_FRQ_SEL 0x3F
> > > > /* bit field positions */
> > > > #define XTAL_FRQ_SEL_POS 5
> > > > @@ -392,21 +445,29 @@ struct anx7625_data {
> > > > struct platform_device *audio_pdev;
> > > > int hpd_status;
> > > > int hpd_high_cnt;
> > > > + int dp_en;
> > > > + int hdcp_cp;
> > > > /* Lock for work queue */
> > > > struct mutex lock;
> > > > struct i2c_client *client;
> > > > struct anx7625_i2c_client i2c;
> > > > struct i2c_client *last_client;
> > > > + struct timer_list hdcp_timer;
> > > > struct s_edid_data slimport_edid_p;
> > > > struct device *codec_dev;
> > > > hdmi_codec_plugged_cb plugged_cb;
> > > > struct work_struct work;
> > > > struct workqueue_struct *workqueue;
> > > > + struct delayed_work hdcp_work;
> > > > + struct workqueue_struct *hdcp_workqueue;
> > > > + /* Lock for hdcp work queue */
> > > > + struct mutex hdcp_wq_lock;
> > > > char edid_block;
> > > > struct display_timing dt;
> > > > u8 display_timing_valid;
> > > > struct drm_bridge bridge;
> > > > u8 bridge_attached;
> > > > + struct drm_connector *connector;
> > > > struct mipi_dsi_device *dsi;
> > > > };
> > > >
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > With the above issues fixed, feel free to add my R-b to this patch and
> > > the split out atomic conversion patch.
> > >
> > > Reviewed-by: Robert Foss <robert.foss@linaro.org>
^ permalink raw reply
* Re: [PATCH 1/2] drm/bridge: anx7625: add HDCP support
From: Xin Ji @ 2022-01-05 11:31 UTC (permalink / raw)
To: Robert Foss
Cc: drinkcat, pihsun, jonas, airlied, bliang, dri-devel, narmstrong,
linux-kernel, jernej.skrabec, tzungbi, Laurent.pinchart, hsinyi,
sam, qwen, dan.carpenter, maxime
In-Reply-To: <CAG3jFysy1BcykodMWRnvB-BJj9Jx7yHLbsJu2Kp52n_7kVS4gw@mail.gmail.com>
On Wed, Jan 05, 2022 at 11:32:01AM +0100, Robert Foss wrote:
> On Wed, 5 Jan 2022 at 08:17, Xin Ji <xji@analogixsemi.com> wrote:
> >
> > On Tue, Jan 04, 2022 at 03:50:34PM +0100, Robert Foss wrote:
> > > Hey Xin,
> > Hi Robert Foss, thanks for the reply.
> > As HDCP config interface "anx7625_hdcp_config(..)" need be called in
> > anx7625_connector_atomic_check(...) interface, so I cannot split out
> > atomic conversion patch.
>
> I don't think that's correct, but maybe I'm missing something. The
> atomic conversion patch should be self-contained if done before the
> addition of HDCP support.
Hi Robert Foss, OK, you are right, I'll split out the atomic conversion patch.
Thanks,
Xin
>
> >
> > Thanks,
> > Xin
> > >
> > > On Tue, 9 Nov 2021 at 03:42, Xin Ji <xji@analogixsemi.com> wrote:
> > > >
> > > > This patch provides HDCP setting interface for userspace to dynamic
> > > > enable/disable HDCP function.
> > > >
> > > > Signed-off-by: Xin Ji <xji@analogixsemi.com>
> > > > ---
> > > > drivers/gpu/drm/bridge/analogix/anx7625.c | 368 +++++++++++++++++++++-
> > > > drivers/gpu/drm/bridge/analogix/anx7625.h | 69 +++-
> > > > 2 files changed, 425 insertions(+), 12 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > > index 001fb39d9919..6d93026c2999 100644
> > > > --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > > > @@ -26,6 +26,7 @@
> > > > #include <drm/drm_crtc_helper.h>
> > > > #include <drm/drm_dp_helper.h>
> > > > #include <drm/drm_edid.h>
> > > > +#include <drm/drm_hdcp.h>
> > > > #include <drm/drm_mipi_dsi.h>
> > > > #include <drm/drm_of.h>
> > > > #include <drm/drm_panel.h>
> > > > @@ -213,6 +214,60 @@ static int wait_aux_op_finish(struct anx7625_data *ctx)
> > > > return 0;
> > > > }
> > > >
> > > > +static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
> > > > + u8 addrh, u8 addrm, u8 addrl,
> > > > + u8 len, u8 *buf)
> > > > +{
> > > > + struct device *dev = &ctx->client->dev;
> > > > + int ret;
> > > > + u8 cmd;
> > > > +
> > > > + if (len > MAX_DPCD_BUFFER_SIZE) {
> > > > + DRM_DEV_ERROR(dev, "exceed aux buffer len.\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + cmd = ((len - 1) << 4) | 0x09;
> > > > +
> > > > + /* Set command and length */
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_COMMAND, cmd);
> > > > +
> > > > + /* Set aux access address */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_ADDR_7_0, addrl);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_ADDR_15_8, addrm);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_ADDR_19_16, addrh);
> > > > +
> > > > + /* Enable aux access */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
> > > > +
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "cannot access aux related register.\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + usleep_range(2000, 2100);
> > > > +
> > > > + ret = wait_aux_op_finish(ctx);
> > > > + if (ret) {
> > > > + DRM_DEV_ERROR(dev, "aux IO error: wait aux op finish.\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
> > > > + AP_AUX_BUFF_START, len, buf);
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "read dpcd register failed\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static int anx7625_video_mute_control(struct anx7625_data *ctx,
> > > > u8 status)
> > > > {
> > > > @@ -669,6 +724,160 @@ static int anx7625_dpi_config(struct anx7625_data *ctx)
> > > > return ret;
> > > > }
> > > >
> > > > +static int anx7625_read_flash_status(struct anx7625_data *ctx)
> > > > +{
> > > > + return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
> > > > +}
> > > > +
> > > > +static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
> > > > +{
> > > > + int ret, val;
> > > > + struct device *dev = &ctx->client->dev;
> > > > + u8 ident[32];
> > >
> > > Could this hardcoded array length be replaced with FLASH_BUF_LEN?
> > >
> > > > +
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_ADDR_HIGH, 0x91);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_ADDR_LOW, 0xA0);
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "IO error : set key flash address.\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "IO error : set key flash len.\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_FLASH_RW_CTRL, FLASH_READ);
> > > > + ret |= readx_poll_timeout(anx7625_read_flash_status,
> > > > + ctx, val,
> > > > + ((val & FLASH_DONE) || (val < 0)),
> > > > + 2000,
> > > > + 2000 * 150);
> > > > + if (ret) {
> > > > + DRM_DEV_ERROR(dev, "flash read access fail!\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_BUF_BASE_ADDR,
> > > > + FLASH_BUF_LEN, ident);
> > > > + if (ret < 0) {
> > > > + DRM_DEV_ERROR(dev, "read flash data fail!\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
> > > > + return -EINVAL;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
> > > > +{
> > > > + int ret;
> > > > + struct device *dev = &ctx->client->dev;
> > > > +
> > > > + /* Select HDCP 1.4 KEY */
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_BOOT_RETRY, 0x12);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_LEN_H, HDCP14KEY_SIZE >> 12);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_LEN_L, HDCP14KEY_SIZE >> 4);
> > > > +
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_ADDR_H, 0);
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_ADDR_L, 0);
> > > > + /* Enable HDCP 1.4 KEY load */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > + R_RAM_CTRL, DECRYPT_EN | LOAD_START);
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "load HDCP 1.4 key done\n");
> > > > + return ret;
> > > > +}
> > > > +
> > > > +static int anx7625_hdcp_config(struct anx7625_data *ctx, bool on)
> > > > +{
> > > > + u8 bcap;
> > > > + int ret;
> > > > + struct device *dev = &ctx->client->dev;
> > > > +
> > > > + if (!on) {
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "disable HDCP 1.4\n");
> > > > +
> > > > + /* Disable HDCP */
> > > > + ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
> > > > + /* Try auth flag */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
> > > > + /* Interrupt for DRM */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
> > > > + if (ret < 0)
> > > > + DRM_DEV_ERROR(dev, "fail to disable HDCP\n");
> > > > +
> > > > + return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
> > > > + TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF);
> > > > + }
> > > > +
> > > > + ret = anx7625_hdcp_key_probe(ctx);
> > > > + if (ret) {
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "no key found, not to do hdcp\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + anx7625_aux_dpcd_read(ctx, 0x06, 0x80, 0x28, 1, &bcap);
> > > > + if (!(bcap & 0x01)) {
> > > > + DRM_WARN("downstream not support HDCP 1.4, cap(%x).\n", bcap);
> > > > + return 0;
> > > > + }
> > > > +
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "enable HDCP 1.4\n");
> > > > +
> > > > + /* First clear HDCP state */
> > > > + ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
> > > > + TX_HDCP_CTRL0,
> > > > + KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
> > > > + usleep_range(1000, 1100);
> > > > + /* Second clear HDCP state */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
> > > > + TX_HDCP_CTRL0,
> > > > + KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
> > > > +
> > > > + /* Set time for waiting KSVR */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
> > > > + SP_TX_WAIT_KSVR_TIME, 0xc8);
> > > > + /* Set time for waiting R0 */
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
> > > > + SP_TX_WAIT_R0_TIME, 0xb0);
> > > > + ret |= anx7625_hdcp_key_load(ctx);
> > > > + if (ret) {
> > > > + DRM_WARN("prepare HDCP key failed.\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
> > > > +
> > > > + /* Try auth flag */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
> > > > + /* Interrupt for DRM */
> > > > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
> > > > + if (ret < 0)
> > > > + DRM_DEV_ERROR(dev, "fail to enable HDCP\n");
> > > > +
> > > > + return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
> > > > + TX_HDCP_CTRL0, HARD_AUTH_EN);
> > > > +}
> > > > +
> > > > static void anx7625_dp_start(struct anx7625_data *ctx)
> > > > {
> > > > int ret;
> > > > @@ -679,6 +888,9 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
> > > > return;
> > > > }
> > > >
> > > > + /* Disable HDCP */
> > > > + anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
> > > > +
> > > > if (ctx->pdata.is_dpi)
> > > > ret = anx7625_dpi_config(ctx);
> > > > else
> > > > @@ -686,6 +898,10 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
> > > >
> > > > if (ret < 0)
> > > > DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
> > > > +
> > > > + ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
> > > > +
> > > > + ctx->dp_en = 1;
> > > > }
> > > >
> > > > static void anx7625_dp_stop(struct anx7625_data *ctx)
> > > > @@ -705,6 +921,10 @@ static void anx7625_dp_stop(struct anx7625_data *ctx)
> > > > ret |= anx7625_video_mute_control(ctx, 1);
> > > > if (ret < 0)
> > > > DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
> > > > +
> > > > + ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
> > > > +
> > > > + ctx->dp_en = 0;
> > > > }
> > > >
> > > > static int sp_tx_rst_aux(struct anx7625_data *ctx)
> > > > @@ -859,7 +1079,7 @@ static int sp_tx_edid_read(struct anx7625_data *ctx,
> > > > AP_AUX_ADDR_7_0, 0x50);
> > > > ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > AP_AUX_ADDR_15_8, 0);
> > > > - ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
> > > > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > > > AP_AUX_ADDR_19_16, 0xf0);
> > > > if (ret < 0) {
> > > > DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
> > > > @@ -1688,6 +1908,83 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
> > > > return 0;
> > > > }
> > > >
> > > > +void hdcp_check_work_func(struct work_struct *work)
> > > > +{
> > > > + u8 status;
> > > > + struct delayed_work *dwork;
> > > > + struct anx7625_data *ctx;
> > > > + struct device *dev;
> > > > + struct drm_device *drm_dev;
> > > > +
> > > > + dwork = to_delayed_work(work);
> > > > + ctx = container_of(dwork, struct anx7625_data, hdcp_work);
> > > > + dev = &ctx->client->dev;
> > > > +
> > > > + if (!ctx->connector) {
> > > > + DRM_ERROR("HDCP connector is null!");
> > > > + return;
> > > > + }
> > > > +
> > > > + drm_dev = ctx->connector->dev;
> > > > + drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
> > > > + mutex_lock(&ctx->hdcp_wq_lock);
> > > > +
> > > > + status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "sink HDCP status check: %.02x\n", status);
> > > > + if (status & BIT(1)) {
> > > > + ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
> > > > + drm_hdcp_update_content_protection(ctx->connector,
> > > > + ctx->hdcp_cp);
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "update CP to ENABLE\n");
> > > > + }
> > > > +
> > > > + mutex_unlock(&ctx->hdcp_wq_lock);
> > > > + drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
> > > > +}
> > > > +
> > > > +static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
> > > > + struct drm_connector_state *state)
> > > > +{
> > > > + struct device *dev = &ctx->client->dev;
> > > > + int cp;
> > > > +
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "hdcp state check\n");
> > > > + cp = state->content_protection;
> > > > +
> > > > + if (cp == ctx->hdcp_cp)
> > > > + return 0;
> > > > +
> > > > + if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
> > > > + if (ctx->dp_en) {
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "enable HDCP\n");
> > > > + anx7625_hdcp_config(ctx, true);
> > > > +
> > > > + queue_delayed_work(ctx->hdcp_workqueue,
> > > > + &ctx->hdcp_work,
> > > > + msecs_to_jiffies(2000));
> > > > + }
> > > > + }
> > > > +
> > > > + if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> > > > + if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
> > > > + DRM_ERROR("current CP is not ENABLED\n");
> > > > + return -EINVAL;
> > > > + }
> > > > + anx7625_hdcp_config(ctx, false);
> > > > + ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
> > > > + drm_hdcp_update_content_protection(ctx->connector,
> > > > + ctx->hdcp_cp);
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "update CP to UNDESIRE\n");
> > > > + }
> > > > +
> > > > + if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
> > > > + DRM_ERROR("Userspace illegal set to PROTECTION ENABLE\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static int anx7625_bridge_attach(struct drm_bridge *bridge,
> > > > enum drm_bridge_attach_flags flags)
> > > > {
> > > > @@ -1902,25 +2199,58 @@ static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
> > > > return true;
> > > > }
> > > >
> > > > -static void anx7625_bridge_enable(struct drm_bridge *bridge)
> > > > +static int anx7625_bridge_atomic_check(struct drm_bridge *bridge,
> > > > + struct drm_bridge_state *bridge_state,
> > > > + struct drm_crtc_state *crtc_state,
> > > > + struct drm_connector_state *conn_state)
> > > > {
> > > > struct anx7625_data *ctx = bridge_to_anx7625(bridge);
> > > > struct device *dev = &ctx->client->dev;
> > > >
> > > > - DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n");
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "drm bridge atomic check\n");
> > > > + anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
> > > > + &crtc_state->adjusted_mode);
> > > > +
> > > > + return anx7625_connector_atomic_check(ctx, conn_state);
>
> If doing an atomic only conversion patch, the above function call
> could simply be removed.
>
> > > > +}
> > > > +
> > > > +static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge,
> > > > + struct drm_bridge_state *state)
> > > > +{
> > > > + struct anx7625_data *ctx = bridge_to_anx7625(bridge);
> > > > + struct device *dev = &ctx->client->dev;
> > > > + struct drm_connector *connector;
> > > > +
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "drm atomic enable\n");
> > > > +
> > > > + if (!bridge->encoder) {
> > > > + DRM_DEV_ERROR(dev, "Parent encoder object not found");
> > > > + return;
> > > > + }
> > > > +
> > > > + connector = drm_atomic_get_new_connector_for_encoder(state->base.state,
> > > > + bridge->encoder);
> > > > + if (!connector)
> > > > + return;
> > > > +
> > > > + ctx->connector = connector;
> > > > +
> > > > + DRM_DEV_DEBUG_DRIVER(dev, "attached content protection.\n");
> > > >
> > > > pm_runtime_get_sync(dev);
> > > >
> > > > anx7625_dp_start(ctx);
> > > > }
> > > >
> > > > -static void anx7625_bridge_disable(struct drm_bridge *bridge)
> > > > +static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge,
> > > > + struct drm_bridge_state *old)
> > > > {
> > > > struct anx7625_data *ctx = bridge_to_anx7625(bridge);
> > > > struct device *dev = &ctx->client->dev;
> > > >
> > > > DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n");
> > > >
> > > > + ctx->connector = NULL;
> > > > anx7625_dp_stop(ctx);
> > > >
> > > > pm_runtime_put_sync(dev);
> > > > @@ -1950,11 +2280,14 @@ static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge,
> > > >
> > > > static const struct drm_bridge_funcs anx7625_bridge_funcs = {
> > > > .attach = anx7625_bridge_attach,
> > > > - .disable = anx7625_bridge_disable,
> > > > .mode_valid = anx7625_bridge_mode_valid,
> > > > .mode_set = anx7625_bridge_mode_set,
> > > > - .mode_fixup = anx7625_bridge_mode_fixup,
> > > > - .enable = anx7625_bridge_enable,
> > > > + .atomic_check = anx7625_bridge_atomic_check,
> > > > + .atomic_enable = anx7625_bridge_atomic_enable,
> > > > + .atomic_disable = anx7625_bridge_atomic_disable,
> > > > + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> > > > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> > > > + .atomic_reset = drm_atomic_helper_bridge_reset,
> > >
> > > Could this atomic conversion be split out into its own logical patch?
> > >
> > > > .detect = anx7625_bridge_detect,
> > > > .get_edid = anx7625_bridge_get_edid,
> > > > };
> > > > @@ -2134,6 +2467,15 @@ static int anx7625_i2c_probe(struct i2c_client *client,
> > > > anx7625_init_gpio(platform);
> > > >
> > > > mutex_init(&platform->lock);
> > > > + mutex_init(&platform->hdcp_wq_lock);
> > > > +
> > > > + INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
> > > > + platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
> > > > + if (!platform->hdcp_workqueue) {
> > > > + DRM_DEV_ERROR(dev, "fail to create work queue\n");
> > > > + ret = -ENOMEM;
> > > > + goto free_platform;
> > > > + }
> > > >
> > > > platform->pdata.intp_irq = client->irq;
> > > > if (platform->pdata.intp_irq) {
> > > > @@ -2143,7 +2485,7 @@ static int anx7625_i2c_probe(struct i2c_client *client,
> > > > if (!platform->workqueue) {
> > > > DRM_DEV_ERROR(dev, "fail to create work queue\n");
> > > > ret = -ENOMEM;
> > > > - goto free_platform;
> > > > + goto free_hdcp_wq;
> > > > }
> > > >
> > > > ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
> > > > @@ -2213,6 +2555,10 @@ static int anx7625_i2c_probe(struct i2c_client *client,
> > > > if (platform->workqueue)
> > > > destroy_workqueue(platform->workqueue);
> > > >
> > > > +free_hdcp_wq:
> > > > + if (platform->hdcp_workqueue)
> > > > + destroy_workqueue(platform->hdcp_workqueue);
> > > > +
> > > > free_platform:
> > > > kfree(platform);
> > > >
> > > > @@ -2228,6 +2574,12 @@ static int anx7625_i2c_remove(struct i2c_client *client)
> > > > if (platform->pdata.intp_irq)
> > > > destroy_workqueue(platform->workqueue);
> > > >
> > > > + if (platform->hdcp_workqueue) {
> > > > + cancel_delayed_work(&platform->hdcp_work);
> > > > + flush_workqueue(platform->workqueue);
> > > > + destroy_workqueue(platform->workqueue);
> > > > + }
> > > > +
> > > > if (!platform->pdata.low_power_mode)
> > > > pm_runtime_put_sync_suspend(&client->dev);
> > > >
> > > > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
> > > > index 3d79b6fb13c8..89b1b347a463 100644
> > > > --- a/drivers/gpu/drm/bridge/analogix/anx7625.h
> > > > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h
> > > > @@ -59,10 +59,23 @@
> > > >
> > > > /***************************************************************/
> > > > /* Register definition of device address 0x70 */
> > > > -#define I2C_ADDR_70_DPTX 0x70
> > > > -
> > > > -#define SP_TX_LINK_BW_SET_REG 0xA0
> > > > -#define SP_TX_LANE_COUNT_SET_REG 0xA1
> > > > +#define TX_HDCP_CTRL0 0x01
> > > > +#define STORE_AN BIT(7)
> > > > +#define RX_REPEATER BIT(6)
> > > > +#define RE_AUTHEN BIT(5)
> > > > +#define SW_AUTH_OK BIT(4)
> > > > +#define HARD_AUTH_EN BIT(3)
> > > > +#define ENC_EN BIT(2)
> > > > +#define BKSV_SRM_PASS BIT(1)
> > > > +#define KSVLIST_VLD BIT(0)
> > > > +
> > > > +#define SP_TX_WAIT_R0_TIME 0x40
> > > > +#define SP_TX_WAIT_KSVR_TIME 0x42
> > > > +#define SP_TX_SYS_CTRL1_REG 0x80
> > > > +#define HDCP2TX_FW_EN BIT(4)
> > > > +
> > > > +#define SP_TX_LINK_BW_SET_REG 0xA0
> > > > +#define SP_TX_LANE_COUNT_SET_REG 0xA1
> > > >
> > > > #define M_VID_0 0xC0
> > > > #define M_VID_1 0xC1
> > > > @@ -71,6 +84,12 @@
> > > > #define N_VID_1 0xC4
> > > > #define N_VID_2 0xC5
> > > >
> > > > +#define KEY_START_ADDR 0x9000
> > > > +#define KEY_RESERVED 416
> > > > +
> > > > +#define HDCP14KEY_START_ADDR (KEY_START_ADDR + KEY_RESERVED)
> > > > +#define HDCP14KEY_SIZE 624
> > > > +
> > > > /***************************************************************/
> > > > /* Register definition of device address 0x72 */
> > > > #define AUX_RST 0x04
> > > > @@ -155,9 +174,43 @@
> > > >
> > > > #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E
> > > >
> > > > +#define R_BOOT_RETRY 0x00
> > > > +#define R_RAM_ADDR_H 0x01
> > > > +#define R_RAM_ADDR_L 0x02
> > > > +#define R_RAM_LEN_H 0x03
> > > > +#define R_RAM_LEN_L 0x04
> > > > #define FLASH_LOAD_STA 0x05
> > > > #define FLASH_LOAD_STA_CHK BIT(7)
> > > >
> > > > +#define R_RAM_CTRL 0x05
> > > > +/* bit positions */
> > > > +#define FLASH_DONE BIT(7)
> > > > +#define BOOT_LOAD_DONE BIT(6)
> > > > +#define CRC_OK BIT(5)
> > > > +#define LOAD_DONE BIT(4)
> > > > +#define O_RW_DONE BIT(3)
> > > > +#define FUSE_BUSY BIT(2)
> > > > +#define DECRYPT_EN BIT(1)
> > > > +#define LOAD_START BIT(0)
> > > > +
> > > > +#define FLASH_ADDR_HIGH 0x0F
> > > > +#define FLASH_ADDR_LOW 0x10
> > > > +#define FLASH_LEN_HIGH 0x31
> > > > +#define FLASH_LEN_LOW 0x32
> > > > +#define R_FLASH_RW_CTRL 0x33
> > > > +/* bit positions */
> > > > +#define READ_DELAY_SELECT BIT(7)
> > > > +#define GENERAL_INSTRUCTION_EN BIT(6)
> > > > +#define FLASH_ERASE_EN BIT(5)
> > > > +#define RDID_READ_EN BIT(4)
> > > > +#define REMS_READ_EN BIT(3)
> > > > +#define WRITE_STATUS_EN BIT(2)
> > > > +#define FLASH_READ BIT(1)
> > > > +#define FLASH_WRITE BIT(0)
> > > > +
> > > > +#define FLASH_BUF_BASE_ADDR 0x60
> > > > +#define FLASH_BUF_LEN 0x20
> > > > +
> > > > #define XTAL_FRQ_SEL 0x3F
> > > > /* bit field positions */
> > > > #define XTAL_FRQ_SEL_POS 5
> > > > @@ -392,21 +445,29 @@ struct anx7625_data {
> > > > struct platform_device *audio_pdev;
> > > > int hpd_status;
> > > > int hpd_high_cnt;
> > > > + int dp_en;
> > > > + int hdcp_cp;
> > > > /* Lock for work queue */
> > > > struct mutex lock;
> > > > struct i2c_client *client;
> > > > struct anx7625_i2c_client i2c;
> > > > struct i2c_client *last_client;
> > > > + struct timer_list hdcp_timer;
> > > > struct s_edid_data slimport_edid_p;
> > > > struct device *codec_dev;
> > > > hdmi_codec_plugged_cb plugged_cb;
> > > > struct work_struct work;
> > > > struct workqueue_struct *workqueue;
> > > > + struct delayed_work hdcp_work;
> > > > + struct workqueue_struct *hdcp_workqueue;
> > > > + /* Lock for hdcp work queue */
> > > > + struct mutex hdcp_wq_lock;
> > > > char edid_block;
> > > > struct display_timing dt;
> > > > u8 display_timing_valid;
> > > > struct drm_bridge bridge;
> > > > u8 bridge_attached;
> > > > + struct drm_connector *connector;
> > > > struct mipi_dsi_device *dsi;
> > > > };
> > > >
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > With the above issues fixed, feel free to add my R-b to this patch and
> > > the split out atomic conversion patch.
> > >
> > > Reviewed-by: Robert Foss <robert.foss@linaro.org>
^ permalink raw reply
* Re: [PATCH v2 1/2] btrfs: harden identification of the stale device
From: Anand Jain @ 2022-01-05 11:31 UTC (permalink / raw)
To: dsterba, linux-btrfs, josef
In-Reply-To: <20220104185611.GX28560@twin.jikos.cz>
On 05/01/2022 02:56, David Sterba wrote:
> On Sat, Dec 11, 2021 at 02:15:29AM +0800, Anand Jain wrote:
>> Identifying and removing the stale device from the fs_uuids list is done
>> by the function btrfs_free_stale_devices().
>> btrfs_free_stale_devices() in turn depends on the function
>> device_path_matched() to check if the device repeats in more than one
>> btrfs_device structure.
>>
>> The matching of the device happens by its path, the device path. However,
>> when dm mapper is in use, the dm device paths are nothing but a link to
>> the actual block device, which leads to the device_path_matched() failing
>> to match.
>>
>> Fix this by matching the dev_t as provided by lookup_bdev() instead of
>> plain strcmp() the device paths.
>>
>> Reported-by: Josef Bacik <josef@toxicpanda.com>
>> Signed-off-by: Anand Jain <anand.jain@oracle.com>
>> ---
>>
>> v2: Fix
>> sparse: warning: incorrect type in argument 1 (different address spaces)
>> For using device->name->str
>>
>> Fix Josef suggestion to pass dev_t instead of device-path in the
>> patch 2/2.
>>
>> fs/btrfs/volumes.c | 41 ++++++++++++++++++++++++++++++++++++-----
>> 1 file changed, 36 insertions(+), 5 deletions(-)
>>
>> diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c
>> index 1b02c03a882c..559fdb0c4a0e 100644
>> --- a/fs/btrfs/volumes.c
>> +++ b/fs/btrfs/volumes.c
>> @@ -534,15 +534,46 @@ btrfs_get_bdev_and_sb(const char *device_path, fmode_t flags, void *holder,
>> return ret;
>> }
>>
>> -static bool device_path_matched(const char *path, struct btrfs_device *device)
>> +/*
>> + * Check if the device in the 'path' matches with the device in the given
>> + * struct btrfs_device '*device'.
>> + * Returns:
>> + * 0 If it is the same device.
>> + * 1 If it is not the same device.
>> + * -errno For error.
>> + */
>> +static int device_matched(struct btrfs_device *device, const char *path)
>> {
>> - int found;
>> + char *device_name;
>> + dev_t dev_old;
>> + dev_t dev_new;
>> + int ret;
>> +
>> + device_name = kzalloc(BTRFS_PATH_NAME_MAX, GFP_KERNEL);
>> + if (!device_name)
>> + return -ENOMEM;
>>
>> rcu_read_lock();
>> - found = strcmp(rcu_str_deref(device->name), path);
>> + ret = sprintf(device_name, "%s", rcu_str_deref(device->name));
>
> I wonder if the temporary allocation could be avoided, as it's the
> exactly same path of the device, so it could be passed to lookup_bdev.
Yeah, I tried but to no avail. Unless I drop the rcu read lock and
use the str directly as below.
lookup_bdev(device->name->str, &dev_old);
We do skip rcu access for device->name at a few locations.
Also, pls note lookup_bdev() can't be called within rcu_read_lock(),
(calling sleep function warning).
>> rcu_read_unlock();
>> + if (!ret) {
>> + kfree(device_name);
>> + return -EINVAL;
>> + }
>>
>> - return found == 0;
>> + ret = lookup_bdev(device_name, &dev_old);
>> + kfree(device_name);
>> + if (ret)
>> + return ret;
>> +
>> + ret = lookup_bdev(path, &dev_new);
>> + if (ret)
>> + return ret;
>> +
>> + if (dev_old == dev_new)
>> + return 0;
>> +
>> + return 1;
>> }
>>
>> /*
>> @@ -577,7 +608,7 @@ static int btrfs_free_stale_devices(const char *path,
>> continue;
>> if (path && !device->name)
>> continue;
>> - if (path && !device_path_matched(path, device))
>> + if (path && device_matched(device, path) != 0)
>
> You've changed the fuction to return errors but it's not checked,
> besides the memory allocation failure, the lookup functions could fail
> for various reasons so I don't think it's safe to ignore the errors.
IMO there isn't much that the parent function should do even if the
device_matched() returns an error for the reasons you stated.
Mainly because btrfs_free_stale_devices() OR btrfs_forget_devices()
is used as a cleanup ops in the primary task functions such as
btrfs_scan_one_device() and btrfs_init_new_device(). Even if we don't
remove the stale there is no harm.
Further btrfs_forget_devices() is called from btrfs_control_ioctl()
which is a userland call for forget devices. So as we traverse the
device list, if a device lookup fails IMO, it is ok to skip to the next
device in the list and return the status of the device match.
Even more, IMO we should save the dev_t in the struct btrfs_device,
upon which the device_matched() will go away altogether. This change
is outside of the bug that we intended to fix here. I will clean that
up separately.
Thanks, Anand
>> continue;
>> if (fs_devices->opened) {
>> /* for an already deleted device return 0 */
>> --
>> 2.33.1
^ permalink raw reply
* Re: [PATCH v12 0/3] net: ethernet: mtk_eth_soc: refactoring and Clause 45
From: patchwork-bot+netdevbpf @ 2022-01-05 11:30 UTC (permalink / raw)
To: Daniel Golle
Cc: linux-mediatek, netdev, linux-arm-kernel, linux-kernel, nbd, john,
sean.wang, Mark-MC.Lee, davem, kuba, matthias.bgg, linux, andrew,
hkallweit1
In-Reply-To: <YdQ4HzLjpuVW4YFi@makrotopia.org>
Hello:
This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:
On Tue, 4 Jan 2022 12:05:51 +0000 you wrote:
> Rework value and type of mdio read and write functions in mtk_eth_soc
> and generally clean up and unify both functions.
> Then add support to access Clause 45 phy registers, using newly
> introduced helper macros added by a patch Russell King has suggested
> in a reply to an earlier version of this series [1].
>
> All three commits are tested on the Bananapi BPi-R64 board having
> MediaTek MT7531BE DSA gigE switch using clause 22 MDIO and
> Ubiquiti UniFi 6 LR access point having Aquantia AQR112C PHY using
> clause 45 MDIO.
>
> [...]
Here is the summary with links:
- [v12,1/3] net: ethernet: mtk_eth_soc: fix return values and refactor MDIO ops
https://git.kernel.org/netdev/net-next/c/eda80b249df7
- [v12,2/3] net: mdio: add helpers to extract clause 45 regad and devad fields
https://git.kernel.org/netdev/net-next/c/c6af53f038aa
- [v12,3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access
https://git.kernel.org/netdev/net-next/c/e2e7f6e29c99
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
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^ permalink raw reply
* [PATCH 4/8] ASoC: cs35l41: Correct handling of some registers in the cache
From: Charles Keepax @ 2022-01-05 11:30 UTC (permalink / raw)
To: broonie; +Cc: patches, alsa-devel, david.rhodes, lgirdwood, tiwai
In-Reply-To: <20220105113026.18955-1-ckeepax@opensource.cirrus.com>
It makes no sense to cache the test/user key registers, since they
require values written at specific times, mark them volatile. It is
probably best if they can't be accessed from user-space either, so
mark them precious as well.
The interrupt force, edge, polarity and debounce are all settings
applied to the IRQ rather than status bits and as such should not be
volatile.
The OTP trim values will require re-application in the event of a
cache sync and as such should not be volatile. The OTPID however
should be volatile.
The DSP scratch registers are used to read back an error/debug code
from the DSP on shutdown, as such these should be marked volatile.
Finally, add some missing defaults, add TST_FS_MON0, and allow the
DSP core control register to be cached.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
sound/soc/codecs/cs35l41-lib.c | 81 ++++++++++++------------------------------
1 file changed, 22 insertions(+), 59 deletions(-)
diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c
index d026c5e3a378b..639dcd25b17e9 100644
--- a/sound/soc/codecs/cs35l41-lib.c
+++ b/sound/soc/codecs/cs35l41-lib.c
@@ -20,6 +20,11 @@ static const struct reg_default cs35l41_reg[] = {
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_PWR_CTRL3, 0x01000010 },
{ CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
+ { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 },
+ { CS35L41_TST_FS_MON0, 0x00020016 },
+ { CS35L41_BSTCVRT_COEFF, 0x00002424 },
+ { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 },
+ { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A },
{ CS35L41_SP_ENABLES, 0x00000000 },
{ CS35L41_SP_RATE_CTRL, 0x00000028 },
{ CS35L41_SP_FORMAT, 0x18180200 },
@@ -48,11 +53,16 @@ static const struct reg_default cs35l41_reg[] = {
{ CS35L41_WKFET_CFG, 0x00000111 },
{ CS35L41_NG_CFG, 0x00000033 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
+ { CS35L41_IRQ1_MASK1, 0xFFFFFFFF },
+ { CS35L41_IRQ1_MASK2, 0xFFFFFFFF },
+ { CS35L41_IRQ1_MASK3, 0xFFFF87FF },
+ { CS35L41_IRQ1_MASK4, 0xFEFFFFFF },
{ CS35L41_GPIO1_CTRL1, 0xE1000001 },
{ CS35L41_GPIO2_CTRL1, 0xE1000001 },
{ CS35L41_MIXER_NGATE_CFG, 0x00000000 },
{ CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
{ CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
+ { CS35L41_DSP1_CCM_CORE_CTRL, 0x00000101 },
};
static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
@@ -84,6 +94,7 @@ static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
case CS35L41_DSP_CLK_CTRL:
case CS35L41_GLOBAL_CLK_CTRL:
case CS35L41_DATA_FS_SEL:
+ case CS35L41_TST_FS_MON0:
case CS35L41_MDSYNC_EN:
case CS35L41_MDSYNC_TX_ID:
case CS35L41_MDSYNC_PWR_CTRL:
@@ -342,7 +353,10 @@ static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
static bool cs35l41_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
+ case CS35L41_TEST_KEY_CTL:
+ case CS35L41_USER_KEY_CTL:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
+ case CS35L41_TST_FS_MON0:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
@@ -359,6 +373,9 @@ static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
case CS35L41_SFT_RESET:
case CS35L41_FABID:
case CS35L41_REVID:
+ case CS35L41_OTPID:
+ case CS35L41_TEST_KEY_CTL:
+ case CS35L41_USER_KEY_CTL:
case CS35L41_DTEMP_EN:
case CS35L41_IRQ1_STATUS:
case CS35L41_IRQ1_STATUS1:
@@ -369,17 +386,6 @@ static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
case CS35L41_IRQ1_RAW_STATUS2:
case CS35L41_IRQ1_RAW_STATUS3:
case CS35L41_IRQ1_RAW_STATUS4:
- case CS35L41_IRQ1_FRC1:
- case CS35L41_IRQ1_FRC2:
- case CS35L41_IRQ1_FRC3:
- case CS35L41_IRQ1_FRC4:
- case CS35L41_IRQ1_EDGE1:
- case CS35L41_IRQ1_EDGE4:
- case CS35L41_IRQ1_POL1:
- case CS35L41_IRQ1_POL2:
- case CS35L41_IRQ1_POL3:
- case CS35L41_IRQ1_POL4:
- case CS35L41_IRQ1_DB3:
case CS35L41_IRQ2_STATUS:
case CS35L41_IRQ2_STATUS1:
case CS35L41_IRQ2_STATUS2:
@@ -389,54 +395,7 @@ static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
case CS35L41_IRQ2_RAW_STATUS2:
case CS35L41_IRQ2_RAW_STATUS3:
case CS35L41_IRQ2_RAW_STATUS4:
- case CS35L41_IRQ2_FRC1:
- case CS35L41_IRQ2_FRC2:
- case CS35L41_IRQ2_FRC3:
- case CS35L41_IRQ2_FRC4:
- case CS35L41_IRQ2_EDGE1:
- case CS35L41_IRQ2_EDGE4:
- case CS35L41_IRQ2_POL1:
- case CS35L41_IRQ2_POL2:
- case CS35L41_IRQ2_POL3:
- case CS35L41_IRQ2_POL4:
- case CS35L41_IRQ2_DB3:
case CS35L41_GPIO_STATUS1:
- case CS35L41_OTP_TRIM_1:
- case CS35L41_OTP_TRIM_2:
- case CS35L41_OTP_TRIM_3:
- case CS35L41_OTP_TRIM_4:
- case CS35L41_OTP_TRIM_5:
- case CS35L41_OTP_TRIM_6:
- case CS35L41_OTP_TRIM_7:
- case CS35L41_OTP_TRIM_8:
- case CS35L41_OTP_TRIM_9:
- case CS35L41_OTP_TRIM_10:
- case CS35L41_OTP_TRIM_11:
- case CS35L41_OTP_TRIM_12:
- case CS35L41_OTP_TRIM_13:
- case CS35L41_OTP_TRIM_14:
- case CS35L41_OTP_TRIM_15:
- case CS35L41_OTP_TRIM_16:
- case CS35L41_OTP_TRIM_17:
- case CS35L41_OTP_TRIM_18:
- case CS35L41_OTP_TRIM_19:
- case CS35L41_OTP_TRIM_20:
- case CS35L41_OTP_TRIM_21:
- case CS35L41_OTP_TRIM_22:
- case CS35L41_OTP_TRIM_23:
- case CS35L41_OTP_TRIM_24:
- case CS35L41_OTP_TRIM_25:
- case CS35L41_OTP_TRIM_26:
- case CS35L41_OTP_TRIM_27:
- case CS35L41_OTP_TRIM_28:
- case CS35L41_OTP_TRIM_29:
- case CS35L41_OTP_TRIM_30:
- case CS35L41_OTP_TRIM_31:
- case CS35L41_OTP_TRIM_32:
- case CS35L41_OTP_TRIM_33:
- case CS35L41_OTP_TRIM_34:
- case CS35L41_OTP_TRIM_35:
- case CS35L41_OTP_TRIM_36:
case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
@@ -445,7 +404,11 @@ static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
- case CS35L41_DSP1_CCM_CORE_CTRL ... CS35L41_DSP1_WDT_STATUS:
+ case CS35L41_DSP1_SCRATCH1:
+ case CS35L41_DSP1_SCRATCH2:
+ case CS35L41_DSP1_SCRATCH3:
+ case CS35L41_DSP1_SCRATCH4:
+ case CS35L41_DSP1_CCM_CLK_OVERRIDE ... CS35L41_DSP1_WDT_STATUS:
case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
return true;
default:
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v2 11/11] usb: gadget: f_uac2: Determining bInterval for HS and SS
From: Pavel Hofman @ 2022-01-05 11:31 UTC (permalink / raw)
To: John Keeping
Cc: linux-usb, Ruslan Bilovol, Felipe Balbi, Jerome Brunet,
Julian Scheel, Greg Kroah-Hartman
In-Reply-To: <YdRovSviQ4IQ82zm@donbot>
Dne 04. 01. 22 v 16:33 John Keeping napsal(a):
> On Thu, Dec 23, 2021 at 08:09:39AM +0100, Pavel Hofman wrote:
>>
>> Dne 22. 12. 21 v 20:50 John Keeping napsal(a):
>>> On Wed, 22 Dec 2021 14:35:07 +0100
>>> Pavel Hofman <pavel.hofman@ivitera.com> wrote:
>>>
>>>> Dne 21. 12. 21 v 13:29 John Keeping napsal(a):
>>>>> On Mon, Dec 20, 2021 at 10:11:30PM +0100, Pavel Hofman wrote:
>>>>>> So far bInterval for HS and SS was fixed at 4, disallowing faster
>>>>>> samplerates. The patch determines the largest bInterval (4 to 1)
>>>>>> for which the required bandwidth of the max samplerate fits the
>>>>>> max allowed packet size. If the required bandwidth exceeds max
>>>>>> bandwidth for single-packet mode (ep->mc=1), bInterval is left at
>>>>>> 1.
>>>>>
>>>>> I'm not sure if this is desirable - there are more concerns around
>>>>> the interval than just whether the bandwidth is available.
>>>>>
>>>>> The nice thing about having the HS/SS interval at 4 when the FS
>>>>> value is 1 is that these both correspond to 1ms, which means the
>>>>> calculations for minimum buffer & period sizes are the same for
>>>>> FS/HS/SS.
>>>>
>>>> Please do you see any specific place in u_audio.c where the interval of
>>>> 1ms is assumed?
>>>>
>>>> * Buffer/period size max limits are fixed
>>>> * Bufer min size is calculated from the max_packet_size
>>>> * snd_pcm_period_elapsed() is called when the current request fill
>>>> overlaps the period boundary:
>>>>
>>>> if ((hw_ptr % snd_pcm_lib_period_bytes(substream)) < req->actual)
>>>> snd_pcm_period_elapsed(substream);
>>>>
>>>>
>>>> The fixed HS bInterval=4 severely limits the available bandwidth,
>>>> disallowing even the very basic 192kHz/2ch/24bits config.
>>>
>>> Yes, but the problem is if the device enumerates as full-speed the
>>> capability is no longer there.
>>>
>>> I agree that is unlikely to be a problem in real use, but I think it
>>> deserves consideration.
>>
>> Please can you elaborate more on that? If the device enumerates as FS, it's
>> automatically limited to bInterval=1 fullspeed frame. Not much more to do,
>> IIUC.
>
> Say we have 8 channels of 32-bit audio at 96kHz which requires 3072000
> bytes per second, and IIUC we need bInterval == 2 for this to work at
> HS.
>
> But for FS there is no way to provide that bandwidth, so if the gadget
> happens to be connected to a host that is only capable of FS then the
> configuration just doesn't work. I think what actually happens given
> the current code is that each packet ends up truncated and parts of the
> audio data are just dropped.
Yes. The current version will drop data for both FS (inevitably) and HS,
eventhough there is no technical reason to drop data for HS as the
bandwidth is available.
>
>>> For the last few years I've been using bInterval == 1 but I also have a
>>> hack to disable full-speed operation completely. In my case this is
>>> because I want to minimise latency and with the 1ms interval for FS the
>>> minimum ALSA period size is too large.
>>>
>>> Basically, I agree with wanting a smaller bInterval, but I want it for a
>>> different reason and I'd like to see a patch that addresses both our use
>>> cases ;-)
>>>
>>>> In f_uac2.c both HS/SS the max packet size, async EP OUT feedback value,
>>>> as well as async EP IN momentary packet size calculations already take
>>>> into account the bInterval of the respective endpoint.
>>>>
>>>> I have been using bInterval < 4 in most of my tests for almost a year,
>>>> testing packet sizes at up to 1024 bytes per 125us uframe, both
>>>> directions, and the gadget has been bitperfect for samplerates up to
>>>> 4MHz (including correctly working async feedback, tested on linux (up to
>>>> 4MHz) and windows 10 WASAPI exclusive (up to 1.5MHz). For larger
>>>> samplerates tests I increased the buffers like in the patch below but I
>>>> did it just in case to minimize probability of xruns. It's not part of
>>>> this patchset and should be configured dynamically too, if actually
>>>> needed at all:
>>>
>>> This is another case of a different trade-off - I use PREEMPT_RT to
>>> minimise xruns and run with a period of 16 samples.
>>>
>>>>> How do FS transfers work if the bandwidth requirements necessitate a
>>>>> smaller interval for HS/SS? Doesn't that mean the FS transfers
>>>>> must be too big?
>>>>
>>>> Only UAC2 HS/SS bIntervals are dynamic with this patch, FS stays fixed
>>>> at 1ms. For HS/SS the max packet size is calculated together with the
>>>> bInterval, so that the largest bInterval possible to fit the ISOC max
>>>> packetsize limits is chosen.
>>>
>>> I'd really like to see FS mode become unsupported when the packet size
>>> is too big. This is a slight issue right now (for 1023 vs 1024) but
>>> this patch makes it significantly worse for the high bandwidth case.
>>
>> I am afraid I do not understand what the patch makes worse. For FS it always
>> yields bInterval=1 and the corresponding maxPacketSize, a calculation of
>> which has not been changed by the patch.
>
> See my comment above - before the difference was really 1023 vs 1024 so
> it's possible to hit a problematic configuration but it's a smaller
> window.
For me the problematic configuration is the one which does not work,
which this feature actually tries to reduce (for HS).
>
> I really think we should avoid a configuration that mostly works but
> fails in surprising ways (for example, working at HS but resulting in
> corrupt data at FS because there just isn't sufficient bandwidth for the
> sample rate, sample size and channel configuration selected).
I understand your reasoning. See below.
>
>>> Right now I have this patch which is a hack but does at least result in
>>> an error for the host when trying to enable audio at FS. It would be
>>> really nice to properly handle this in the composite gadget core so that
>>> the audio function is exposed only at HS/SS with proper
>>> DT_OTHER_SPEED_CONFIG handling, but currently that code assumes that the
>>> same number of descriptors is provided for each speed.
>>>
>>> -- 8< --
>>> diff --git a/drivers/usb/gadget/function/f_uac2.c b/drivers/usb/gadget/function/f_uac2.c
>>> index 36fa6ef0581b..b4946409b38a 100644
>>> --- a/drivers/usb/gadget/function/f_uac2.c
>>> +++ b/drivers/usb/gadget/function/f_uac2.c
>>> @@ -1356,6 +1356,9 @@ afunc_set_alt(struct usb_function *fn, unsigned intf, unsigned alt)
>>> return 0;
>>> }
>>> + if (gadget->speed < USB_SPEED_HIGH && alt)
>>> + return -EINVAL;
>>> +
>>> if (intf == uac2->as_out_intf) {
>>> uac2->as_out_alt = alt;
>>> -- >8 --
>>>
>>>>> I don't think there has ever been a check that the configured sample
>>>>> size, channel count and interval actually fit in the max packet
>>>>> size for an endpoint. Is that something that should be checked to
>>>>> give an error on bind if the configuration can't work?
>>>>
>>>> The existing code has never had checks for any of that. Actually the
>>>> dynamic bInterval calculation in this patch handles the bInterval and
>>>> packetsize for configured parameters up to maximum ISOC bandwidth. Next
>>>> version of this patch will at least warn about exceeding the overall
>>>> available bandwidth.
>>>>
>>>> There are many patches to go before the audio gadget becomes fool-proof,
>>>> but at least it should be practically usable with these patches (when
>>>> finalized) and the gaudio controller example implementation.
>>>
>>> Agreed, and I really appreciate the improvements you're making here.
>>>
>>> The reason I suggested the new checks here is that it makes a lot of
>>> sense if the bInterval value is exposed as part of the configfs
>>> interface. It means there's one extra value to set for high bandwidth
>>> operation, rather than having it "just work", but I think the
>>> latency/bandwidth tradeoffs here mean that there's no way for the kernel
>>> to select the right value for all scenarios, so really we need to let
>>> the user tell us what they want.
>>
>> OK. IMO it could be easily resolved by having the upper bInterval limit for
>> the largest-fitting bInterval check of my patch configurable by new configfs
>> max_bint, defaulting to the existing value of 4. I would leave the default
>> (4), minimizing CPU load, you would set max_bint=1, minimizing latency. Any
>> max_bint value in between would work, while still having available the
>> automated calculation if lower bint value was required for the given
>> parameters.
>>
>> In addition, the final check dev_warn can be chanched to dev_err + returning
>> EINVAL, providing the discussed sanity check. The check would work for FS as
>> well as for HS/SS.
>>
>> This change could be split to three patches:
>>
>> 1. the automated calculation with fixed max_bint=4 - my current patch,
>> dev_warn if max_size_bw > max_size_ep, max_size_bw limited to max_size_ep,
>> no error, only warning.
>>
>> 2. adding the uac2_opts max_bint, using in set_ep_max_packet_size_bint
>>
>> 3. turning the sanity check warning to failing error: changing the dev_warn
>> in the final check to dev_err+ returning error.
>>
>> So the final version could look like this:
>
> This sounds good to me.
>
> But I think you'll hit the FS vs HS bandwidth issue described above when
> trying anything that requires a lower bInterval ;-)
Well, the FS bandwidth is just too small, but IMO it's not a reason to
limit HS too, as is limited now.
>
> I really think the answer to this is an extra patch/series that disables
> operation at full speed when more bandwidth is required. Ideally that
> would include enhancing the gadget core to support different descriptors
> for different speeds (which is already somewhat supported as other speed
> config descriptors are returned correctly, but IIRC there's an
> assumption that the number of descriptors is the same across all
> speeds).
More patches in that area are certainly required.
What I can do:
* Separate the maxbandwidth patch series from the
multiple-rates/rate-notification series to:
* patch 1 - the automated bint/maxPacketSize calculation with fixed
max_bint=4 (for HS/SS), warning if bandwidth exceeded
* patch 2 - adding the uac2_opts max_bint to allow lower latency (I
already have this prepared)
* patch 3 - failing f_uac2 load when requested params exceed HS/SS
limits (for bInterval=1). The calculation method is always called for
all FS/HS/SS now, so I cannot fail the FS check as it would break HS/SS.
I do not know how (and at what point) to disable operation for FS.
Perhaps you could follow up with suitable patch, tested on your
FS-capable HW?
Thanks a lot,
Pavel.
^ permalink raw reply
* [PATCH] media: st-hva: Fix PM disable depth imbalance in hva_hw_probe
From: Miaoqian Lin @ 2022-01-05 11:31 UTC (permalink / raw)
Cc: linmq006, Jean-Christophe Trotin, Mauro Carvalho Chehab,
Peter Griffin, Yannick Fertre, Hans Verkuil, linux-media,
linux-kernel
The pm_runtime_enable will increase power disable depth.
If the probe fails, we should use pm_runtime_disable() to balance
pm_runtime_enable().
Fixes: 57b2c06 ("[media] st-hva: multi-format video encoder V4L2 driver")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
---
drivers/media/platform/sti/hva/hva-hw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/sti/hva/hva-hw.c b/drivers/media/platform/sti/hva/hva-hw.c
index 15e8f83b1b56..bef880951921 100644
--- a/drivers/media/platform/sti/hva/hva-hw.c
+++ b/drivers/media/platform/sti/hva/hva-hw.c
@@ -406,7 +406,8 @@ int hva_hw_probe(struct platform_device *pdev, struct hva_dev *hva)
err_clk:
if (hva->clk)
clk_unprepare(hva->clk);
-
+disable_pm_runtime:
+ pm_runtime_disable(dev);
return ret;
}
--
2.17.1
^ permalink raw reply related
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915: split out intel_vtd.[ch] from i915_drv.h
From: Patchwork @ 2022-01-05 11:30 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
In-Reply-To: <20220105094155.933291-1-jani.nikula@intel.com>
[-- Attachment #1: Type: text/plain, Size: 30303 bytes --]
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: split out intel_vtd.[ch] from i915_drv.h
URL : https://patchwork.freedesktop.org/series/98498/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11047_full -> Patchwork_21924_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21924_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21924_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 12)
------------------------------
Missing (1): shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21924_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-suspend-interruptible@a-vga1:
- shard-snb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-snb2/igt@kms_flip@flip-vs-suspend-interruptible@a-vga1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-snb2/igt@kms_flip@flip-vs-suspend-interruptible@a-vga1.html
* igt@kms_lease@cursor_implicit_plane:
- shard-apl: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl8/igt@kms_lease@cursor_implicit_plane.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl7/igt@kms_lease@cursor_implicit_plane.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_whisper@basic-contexts-forked:
- {shard-rkl}: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-6/igt@gem_exec_whisper@basic-contexts-forked.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-5/igt@gem_exec_whisper@basic-contexts-forked.html
* igt@gem_exec_whisper@basic-queues-priority:
- {shard-rkl}: [PASS][7] -> [INCOMPLETE][8] +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-6/igt@gem_exec_whisper@basic-queues-priority.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-5/igt@gem_exec_whisper@basic-queues-priority.html
* igt@testdisplay:
- {shard-tglu}: [PASS][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@testdisplay.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglu-3/igt@testdisplay.html
Known issues
------------
Here are the changes found in Patchwork_21924_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][11] ([i915#3002])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl9/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][12] ([i915#180]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl3/igt@gem_exec_suspend@basic-s3@smem.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk1/igt@gem_exec_whisper@basic-queues-forked.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-glk2/igt@gem_exec_whisper@basic-queues-forked.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb1/igt@gem_huc_copy@huc-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglb7/igt@gem_huc_copy@huc-copy.html
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl7/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl4/igt@gem_lmem_swapping@random.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271]) +181 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl3/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl3/igt@gem_softpin@noreloc-s3.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl4/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][26] ([i915#3318])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl1/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1436] / [i915#716])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl7/igt@gen9_exec_parse@allowed-all.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl8/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][29] ([i915#454])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][30] -> [FAIL][31] ([i915#454])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271]) +102 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_suspend@sysfs-reader:
- shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#2867])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb8/igt@i915_suspend@sysfs-reader.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb5/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][35] ([i915#3743]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0:
- shard-skl: NOTRUN -> [DMESG-WARN][36] ([i915#1982])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][38] ([i915#3763])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3777])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3886]) +10 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +4 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +6 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl3/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +6 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl7/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +12 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +10 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl4/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][46] ([i915#1319])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl6/igt@kms_content_protection@atomic-dpms.html
- shard-kbl: NOTRUN -> [TIMEOUT][47] ([i915#1319])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][48] ([i915#2105])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@kms_content_protection@uevent.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109274] / [fdo#111825])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglb5/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][50] -> [FAIL][51] ([i915#2346] / [i915#533])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][52] -> [DMESG-WARN][53] ([i915#180] / [i915#1982])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271]) +121 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#1188])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl4/igt@kms_hdr@bpc-switch.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl6/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#533])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#533])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl7/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl4/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][63] -> [SKIP][64] ([fdo#109441])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2437])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2437])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl7/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2437])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl4/igt@kms_writeback@writeback-pixel-formats.html
* igt@sysfs_clients@split-10:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2994])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl2/igt@sysfs_clients@split-10.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2994]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl7/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@fbdev@pan:
- {shard-rkl}: ([SKIP][70], [SKIP][71]) ([i915#2582]) -> [PASS][72]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@fbdev@pan.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-4/igt@fbdev@pan.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@fbdev@pan.html
* igt@gem_ctx_shared@detached-shared-gtt:
- {shard-rkl}: [INCOMPLETE][73] -> ([PASS][74], [PASS][75])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@gem_ctx_shared@detached-shared-gtt.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-4/igt@gem_ctx_shared@detached-shared-gtt.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@gem_ctx_shared@detached-shared-gtt.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-skl: [TIMEOUT][76] ([i915#3063]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-skl4/igt@gem_eio@in-flight-contexts-10ms.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-skl7/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@kms:
- shard-tglb: [FAIL][78] ([i915#232]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb8/igt@gem_eio@kms.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglb7/igt@gem_eio@kms.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][80] ([i915#2481] / [i915#3070]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@gem_eio@unwedge-stress.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@bonded-pair:
- {shard-tglu}: [FAIL][82] ([i915#1888]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@gem_exec_balancer@bonded-pair.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglu-3/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: [SKIP][84] ([i915#4525]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb3/igt@gem_exec_balancer@parallel.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb2/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [FAIL][86] ([i915#2842]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl6/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][88] ([i915#2842]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][90] ([i915#2842]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [FAIL][92] ([i915#2842]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb1/igt@gem_exec_fair@basic-pace@vecs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- {shard-tglu}: [INCOMPLETE][94] ([i915#750]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-7/igt@gem_ppgtt@blt-vs-render-ctxn.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglu-5/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][96] ([i915#180]) -> [PASS][97] +3 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-apl2/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][98] ([i915#4281]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-fence:
- {shard-tglu}: [WARN][100] ([i915#2681]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@gem-pread:
- {shard-rkl}: [SKIP][102] ([fdo#109308]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@i915_pm_rpm@gem-pread.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@i915_pm_rpm@gem-pread.html
* igt@i915_selftest@live@gt_pm:
- {shard-tglu}: [DMESG-FAIL][104] ([i915#3987]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-tglu-8/igt@i915_selftest@live@gt_pm.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-tglu-7/igt@i915_selftest@live@gt_pm.html
* igt@kms_atomic@test-only:
- {shard-rkl}: [SKIP][106] ([i915#1845]) -> [PASS][107] +5 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_atomic@test-only.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_atomic@test-only.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk: [DMESG-WARN][108] ([i915#118]) -> [PASS][109] +3 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-180.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [SKIP][110] ([i915#1845] / [i915#4098]) -> [PASS][111] +3 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@pipe-a-ctm-0-5:
- {shard-rkl}: [SKIP][112] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_color@pipe-a-ctm-0-5.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_color@pipe-a-ctm-max:
- {shard-rkl}: [SKIP][114] ([i915#1149] / [i915#1849]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-5/igt@kms_color@pipe-a-ctm-max.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_color@pipe-a-ctm-max.html
* igt@kms_color@pipe-b-ctm-0-5:
- {shard-rkl}: ([SKIP][116], [SKIP][117]) ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][118]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-4/igt@kms_color@pipe-b-ctm-0-5.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_color@pipe-b-ctm-0-5.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- {shard-rkl}: [SKIP][119] ([fdo#112022] / [i915#4070]) -> [PASS][120] +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- {shard-rkl}: [SKIP][121] ([fdo#111825] / [i915#4070]) -> [PASS][122] +2 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [FAIL][123] ([i915#2346]) -> [PASS][124] +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_dp_aux_dev:
- {shard-rkl}: [SKIP][125] ([i915#1257]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_dp_aux_dev.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
- {shard-rkl}: [SKIP][127] ([fdo#111314]) -> [PASS][128] +2 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- {shard-rkl}: ([SKIP][129], [SKIP][130]) ([fdo#110189] / [i915#3955]) -> [PASS][131]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-iclb: [SKIP][132] ([i915#3701]) -> [PASS][133] +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling:
- {shard-rkl}: [INCOMPLETE][134] ([i915#3701]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][136] ([i915#180]) -> [PASS][137] +5 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- {shard-rkl}: [SKIP][138] ([i915#1849]) -> [PASS][139] +5 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite:
- {shard-rkl}: [SKIP][140] ([i915#4098]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- {shard-rkl}: [SKIP][142] ([i915#1849] / [i915#4070]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][144] ([fdo#109441]) -> [PASS][145] +1 similar issue
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@sprite_render:
- {shard-rkl}: [SKIP][146] ([i915#1072]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11047/shard-rkl-1/igt@kms_psr@sprite_render.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/shard-rkl-6/igt@kms_psr@sprite_render.html
* igt@kms_setmode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21924/index.html
[-- Attachment #2: Type: text/html, Size: 33344 bytes --]
^ permalink raw reply
* Re: [RFC 04/10] vdpa-dev: implement the instance_init/class_init interface
From: Stefano Garzarella @ 2022-01-05 11:28 UTC (permalink / raw)
To: Longpeng(Mike)
Cc: mst, jasowang, cohuck, qemu-devel, yechuan, arei.gonglei,
huangzhichao, stefanha, pbonzini
In-Reply-To: <20220105005900.860-5-longpeng2@huawei.com>
On Wed, Jan 05, 2022 at 08:58:54AM +0800, Longpeng(Mike) wrote:
>From: Longpeng <longpeng2@huawei.com>
>
>Implements the .instance_init and the .class_init interface.
>
>Signed-off-by: Longpeng <longpeng2@huawei.com>
>---
> hw/virtio/vdpa-dev-pci.c | 80 +++++++++++++++++++++++++++++++++++-
> hw/virtio/vdpa-dev.c | 68 +++++++++++++++++++++++++++++-
> include/hw/virtio/vdpa-dev.h | 2 +
> 3 files changed, 146 insertions(+), 4 deletions(-)
>
>diff --git a/hw/virtio/vdpa-dev-pci.c b/hw/virtio/vdpa-dev-pci.c
>index a5a7b528a9..0af54a26d4 100644
>--- a/hw/virtio/vdpa-dev-pci.c
>+++ b/hw/virtio/vdpa-dev-pci.c
>@@ -23,14 +23,90 @@ struct VhostVdpaDevicePCI {
> VhostVdpaDevice vdev;
> };
>
>+static uint32_t
>+vdpa_dev_pci_get_info(const char *name, uint64_t cmd, Error **errp)
>+{
>+ int device_fd;
>+ uint32_t val;
>+ int ret;
>+
>+ device_fd = qemu_open(name, O_RDWR, errp);
>+ if (device_fd == -1) {
>+ return (uint32_t)-1;
>+ }
>+
>+ ret = ioctl(device_fd, cmd, &val);
>+ if (ret < 0) {
>+ error_setg(errp, "vhost-vdpa-device-pci: cmd 0x%lx failed: %s",
>+ cmd, strerror(errno));
>+ goto out;
>+ }
>+
>+out:
>+ close(device_fd);
>+ return val;
>+}
>+
>+static inline uint32_t
>+vdpa_dev_pci_get_devid(VhostVdpaDevicePCI *dev, Error **errp)
>+{
>+ return vdpa_dev_pci_get_info(dev->vdev.vdpa_dev,
>+ VHOST_VDPA_GET_DEVICE_ID, errp);
>+}
>+
>+static inline uint32_t
>+vdpa_dev_pci_get_vectors_num(VhostVdpaDevicePCI *dev, Error **errp)
>+{
>+ return vdpa_dev_pci_get_info(dev->vdev.vdpa_dev,
>+ VHOST_VDPA_GET_VECTORS_NUM, errp);
>+}
>+
> static void vhost_vdpa_device_pci_instance_init(Object *obj)
> {
>- return;
>+ VhostVdpaDevicePCI *dev = VHOST_VDPA_DEVICE_PCI(obj);
>+
>+ virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
>+ TYPE_VHOST_VDPA_DEVICE);
>+ object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
>+ "bootindex");
>+}
>+
>+static Property vhost_vdpa_device_pci_properties[] = {
>+ DEFINE_PROP_END_OF_LIST(),
>+};
>+
>+static void
>+vhost_vdpa_device_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
>+{
>+ VhostVdpaDevicePCI *dev = VHOST_VDPA_DEVICE_PCI(vpci_dev);
>+ DeviceState *vdev = DEVICE(&dev->vdev);
>+ uint32_t devid;
>+ uint32_t vectors;
>+
>+ devid = vdpa_dev_pci_get_devid(dev, errp);
>+ if (*errp) {
>+ return;
>+ }
>+
>+ vectors = vdpa_dev_pci_get_vectors_num(dev, errp);
>+ if (*errp) {
>+ return;
>+ }
>+
>+ vpci_dev->class_code = virtio_pci_get_class_id(devid);
>+ vpci_dev->pdev_id = virtio_pci_get_pci_devid(devid);
>+ vpci_dev->nvectors = vectors;
>+ qdev_realize(vdev, BUS(&vpci_dev->bus), errp);
> }
>
> static void vhost_vdpa_device_pci_class_init(ObjectClass *klass, void *data)
> {
>- return;
>+ DeviceClass *dc = DEVICE_CLASS(klass);
>+ VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
>+
>+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
>+ device_class_set_props(dc, vhost_vdpa_device_pci_properties);
>+ k->realize = vhost_vdpa_device_pci_realize;
> }
>
> static const VirtioPCIDeviceTypeInfo vhost_vdpa_device_pci_info = {
>diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c
>index f4f92b90b0..790117fb3b 100644
>--- a/hw/virtio/vdpa-dev.c
>+++ b/hw/virtio/vdpa-dev.c
>@@ -15,16 +15,80 @@
> #include "sysemu/sysemu.h"
> #include "sysemu/runstate.h"
>
>-static void vhost_vdpa_device_class_init(ObjectClass *klass, void *data)
>+static void vhost_vdpa_device_realize(DeviceState *dev, Error **errp)
> {
> return;
> }
>
>-static void vhost_vdpa_device_instance_init(Object *obj)
>+static void vhost_vdpa_device_unrealize(DeviceState *dev)
>+{
>+ return;
>+}
>+
>+static void
>+vhost_vdpa_device_get_config(VirtIODevice *vdev, uint8_t *config)
>+{
>+ return;
>+}
>+
>+static void
>+vhost_vdpa_device_set_config(VirtIODevice *vdev, const uint8_t *config)
> {
> return;
> }
>
>+static uint64_t vhost_vdpa_device_get_features(VirtIODevice *vdev,
>+ uint64_t features,
>+ Error **errp)
>+{
>+ return (uint64_t)-1;
>+}
>+
>+static void vhost_vdpa_device_set_status(VirtIODevice *vdev, uint8_t status)
>+{
>+ return;
>+}
>+
>+static Property vhost_vdpa_device_properties[] = {
>+ DEFINE_PROP_STRING("vdpa-dev", VhostVdpaDevice, vdpa_dev),
>+ DEFINE_PROP_END_OF_LIST(),
>+};
>+
>+static const VMStateDescription vmstate_vhost_vdpa_device = {
>+ .name = "vhost-vdpa-device",
>+ .minimum_version_id = 1,
>+ .version_id = 1,
>+ .fields = (VMStateField[]) {
>+ VMSTATE_VIRTIO_DEVICE,
>+ VMSTATE_END_OF_LIST()
>+ },
>+};
>+
>+static void vhost_vdpa_device_class_init(ObjectClass *klass, void *data)
>+{
>+ DeviceClass *dc = DEVICE_CLASS(klass);
>+ VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
>+
>+ device_class_set_props(dc, vhost_vdpa_device_properties);
>+ dc->desc = "VDPA-based generic PCI device assignment";
IIUC, this should be the description of the generic vhost vDPA device,
not the PCI implementation, right?
Thanks,
Stefano
^ permalink raw reply
* Re: [PATCH v12 0/3] net: ethernet: mtk_eth_soc: refactoring and Clause 45
From: patchwork-bot+netdevbpf @ 2022-01-05 11:30 UTC (permalink / raw)
To: Daniel Golle
Cc: linux-mediatek, netdev, linux-arm-kernel, linux-kernel, nbd, john,
sean.wang, Mark-MC.Lee, davem, kuba, matthias.bgg, linux, andrew,
hkallweit1
In-Reply-To: <YdQ4HzLjpuVW4YFi@makrotopia.org>
Hello:
This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:
On Tue, 4 Jan 2022 12:05:51 +0000 you wrote:
> Rework value and type of mdio read and write functions in mtk_eth_soc
> and generally clean up and unify both functions.
> Then add support to access Clause 45 phy registers, using newly
> introduced helper macros added by a patch Russell King has suggested
> in a reply to an earlier version of this series [1].
>
> All three commits are tested on the Bananapi BPi-R64 board having
> MediaTek MT7531BE DSA gigE switch using clause 22 MDIO and
> Ubiquiti UniFi 6 LR access point having Aquantia AQR112C PHY using
> clause 45 MDIO.
>
> [...]
Here is the summary with links:
- [v12,1/3] net: ethernet: mtk_eth_soc: fix return values and refactor MDIO ops
https://git.kernel.org/netdev/net-next/c/eda80b249df7
- [v12,2/3] net: mdio: add helpers to extract clause 45 regad and devad fields
https://git.kernel.org/netdev/net-next/c/c6af53f038aa
- [v12,3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access
https://git.kernel.org/netdev/net-next/c/e2e7f6e29c99
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply
* Re: [PATCH v12 0/3] net: ethernet: mtk_eth_soc: refactoring and Clause 45
From: patchwork-bot+netdevbpf @ 2022-01-05 11:30 UTC (permalink / raw)
To: Daniel Golle
Cc: linux-mediatek, netdev, linux-arm-kernel, linux-kernel, nbd, john,
sean.wang, Mark-MC.Lee, davem, kuba, matthias.bgg, linux, andrew,
hkallweit1
In-Reply-To: <YdQ4HzLjpuVW4YFi@makrotopia.org>
Hello:
This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:
On Tue, 4 Jan 2022 12:05:51 +0000 you wrote:
> Rework value and type of mdio read and write functions in mtk_eth_soc
> and generally clean up and unify both functions.
> Then add support to access Clause 45 phy registers, using newly
> introduced helper macros added by a patch Russell King has suggested
> in a reply to an earlier version of this series [1].
>
> All three commits are tested on the Bananapi BPi-R64 board having
> MediaTek MT7531BE DSA gigE switch using clause 22 MDIO and
> Ubiquiti UniFi 6 LR access point having Aquantia AQR112C PHY using
> clause 45 MDIO.
>
> [...]
Here is the summary with links:
- [v12,1/3] net: ethernet: mtk_eth_soc: fix return values and refactor MDIO ops
https://git.kernel.org/netdev/net-next/c/eda80b249df7
- [v12,2/3] net: mdio: add helpers to extract clause 45 regad and devad fields
https://git.kernel.org/netdev/net-next/c/c6af53f038aa
- [v12,3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access
https://git.kernel.org/netdev/net-next/c/e2e7f6e29c99
You are awesome, thank you!
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^ permalink raw reply
* Re: [PATCH net-next v3 0/3] net: lan966x: Extend switchdev with mdb support
From: patchwork-bot+netdevbpf @ 2022-01-05 11:30 UTC (permalink / raw)
To: Horatiu Vultur
Cc: linux-kernel, netdev, UNGLinuxDriver, davem, kuba, f.fainelli,
vivien.didelot, vladimir.oltean, andrew
In-Reply-To: <20220104153338.425250-1-horatiu.vultur@microchip.com>
Hello:
This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:
On Tue, 4 Jan 2022 16:33:35 +0100 you wrote:
> This patch series extends lan966x with mdb support by implementing
> the switchdev callbacks: SWITCHDEV_OBJ_ID_PORT_MDB and
> SWITCHDEV_OBJ_ID_HOST_MDB.
> It adds support for both ipv4/ipv6 entries and l2 entries.
>
> v2->v3:
> - rename PGID_FIRST and PGID_LAST to PGID_GP_START and PGID_GP_END
> - don't forget and relearn an entry for the CPU if there are more
> references to the cpu.
>
> [...]
Here is the summary with links:
- [net-next,v3,1/3] net: lan966x: Add function lan966x_mac_ip_learn()
https://git.kernel.org/netdev/net-next/c/fc0c3fe7486f
- [net-next,v3,2/3] net: lan966x: Add PGID_GP_START and PGID_GP_END
https://git.kernel.org/netdev/net-next/c/11b0a27772f5
- [net-next,v3,3/3] net: lan966x: Extend switchdev with mdb support
https://git.kernel.org/netdev/net-next/c/7aacb894b1ad
You are awesome, thank you!
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* Re: [PATCH RFT] scsi: pm8001: Fix FW crash for maxcpus=1
From: John Garry @ 2022-01-05 11:28 UTC (permalink / raw)
To: Damien Le Moal, jejb, martin.petersen, jinpu.wang, Ajish.Koshy,
Viswas.G
Cc: linux-scsi, linux-kernel, vishakhavc, ipylypiv, Ruksar.devadi,
Vasanthalakshmi.Tharmarajan
In-Reply-To: <d2d3c903-fb91-e218-9e0a-aeb2ff9e401a@opensource.wdc.com>
On 05/01/2022 04:03, Damien Le Moal wrote:
> On 1/5/22 03:26, John Garry wrote:
>> According to the comment in check_fw_ready() we should not check the
>> IOP1_READY field in register SCRATCH_PAD_1 for 8008 or 8009 controllers.
>>
>> However we check this very field in process_oq() for processing the highest
>> index interrupt vector. Change that function to not check IOP1_READY for
>> those mentioned controllers, but do check ILA_READY in both cases.
>>
>> The reason I assume that this was not hit earlier was because we always
>> allocated 64 MSI(X), and just did not pass the vector index check in
>> process_oq(), i.e. the handler never ran for vector index 63.
>>
>> Signed-off-by: John Garry<john.garry@huawei.com>
>>
>> diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
>> index 2101fc5761c3..77b8bb30615b 100644
>> --- a/drivers/scsi/pm8001/pm80xx_hwi.c
>> +++ b/drivers/scsi/pm8001/pm80xx_hwi.c
>> @@ -4162,9 +4162,16 @@ static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
>> u32 regval;
>>
>> if (vec == (pm8001_ha->max_q_num - 1)) {
>> + u32 mipsall_ready;
>> +
>> + if ((pm8001_ha->chip_id == chip_8008) ||
>> + (pm8001_ha->chip_id == chip_8009))
> nit: no need for the inner brackets here.
ok, I can fix that.
But I would also like opinion from microchip guys/maintainer on why this
code is here at all. Seems strange in the way we check in this register
in the interrupt handler for only a specific vector and, also, why we
check at all in an interrupt handler.
>
>> + mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
>> + else
>> + mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
>> +
>> regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
>> - if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
>> - SCRATCH_PAD_MIPSALL_READY) {
>> + if ((regval & mipsall_ready) != mipsall_ready) {
>> pm8001_ha->controller_fatal_error = true;
>> pm8001_dbg(pm8001_ha, FAIL,
>> "Firmware Fatal error! Regval:0x%x\n",
>> diff --git a/drivers/scsi/pm8001/pm80xx_hwi.h b/drivers/scsi/pm8001/pm80xx_hwi.h
>> index c7e5d93bea92..c41ed039c92a 100644
>> --- a/drivers/scsi/pm8001/pm80xx_hwi.h
>> +++ b/drivers/scsi/pm8001/pm80xx_hwi.h
>> @@ -1405,8 +1405,12 @@ typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
>> #define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
>> #define SCRATCH_PAD_IOP0_READY 0xC00
>> #define SCRATCH_PAD_IOP1_READY 0x3000
>> -#define SCRATCH_PAD_MIPSALL_READY (SCRATCH_PAD_IOP1_READY | \
>> +#define SCRATCH_PAD_MIPSALL_READY_16PORT (SCRATCH_PAD_IOP1_READY | \
>> SCRATCH_PAD_IOP0_READY | \
>> + SCRATCH_PAD_ILA_READY | \
>> + SCRATCH_PAD_RAAE_READY)
>> +#define SCRATCH_PAD_MIPSALL_READY_8PORT (SCRATCH_PAD_IOP0_READY | \
>> + SCRATCH_PAD_ILA_READY | \
>> SCRATCH_PAD_RAAE_READY)
>>
>> /* boot loader state */
> Otherwise, looks OK to me.
> I tested with and without max_cpus=1 with a ATTO Technology, Inc.
> ExpressSAS 12Gb/s SAS/SATA HBA (rev 06) adapter and everything is OK.
> That adapter uses chip_8072 though, not 8008 or 8009.
>
> Feel free to add:
>
> Reviewed-by: Damien Le Moal<damien.lemoal@opensource.wdc.com>
> Tested-by: Damien Le Moal<damien.lemoal@opensource.wdc.com>
Thanks!
john
^ permalink raw reply
* Re: [PATCH] platform/x86: Add Asus TF103C dock driver
From: Andy Shevchenko @ 2022-01-05 11:26 UTC (permalink / raw)
To: Hans de Goede
Cc: Mark Gross, Andy Shevchenko, platform-driver-x86,
Michał Mirosław, Ion Agorria, Svyatoslav Ryhel
In-Reply-To: <3504b30f-a63d-c0cd-00ce-38ab0089c5be@redhat.com>
On Wed, Jan 05, 2022 at 12:06:57PM +0100, Hans de Goede wrote:
> On 1/4/22 16:32, Andy Shevchenko wrote:
> > On Sun, Dec 26, 2021 at 03:18:49PM +0100, Hans de Goede wrote:
...
> >> +/* Byte 0 is the length of the rest of the packet */
> >> +static const u8 tf103c_dock_enable_cmd[9] = { 8, 0x20, 0, 0, 0, 0, 0x20, 0, 0 };
> >> +static const u8 tf103c_dock_usb_enable_cmd[9] = { 8, 0, 0, 0, 0, 0, 0, 0x40, 0 };
> >> +static const u8 tf103c_dock_suspend_cmd[9] = { 8, 0, 0x20, 0, 0, 0x22, 0, 0, 0 };
> >
> > This seems to me rather
> >
> > struct {
> > u8 cmd;
> > DECLARE_BITMAP(payload, 64);
> > };
> >
> > And those 2s and 4s are actually some bits in payload with some meaning.
> >
> > Would it be the case?
>
> Something like that yes, there are some hints that this is a bitfield in
> the Android driver code, but then in other places it seems to be more of
> a command structure then just individual bits having a meaning.
>
> All in all we really don't know, so I'm going to keep this as just
> an opaque array of bytes, because that is really what it is / what we know
> about it.
Thinking more about this it rather __le64. then it's more easily to see the
bits there. I still think the byte array here carries less information than
what we can assume. In the case of __le64 you don't need to keep a length,
you may derive it from the size of the supplied variable.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH][honister] linux-yocto: add libmpc-native to DEPENDS
From: Ross Burton @ 2022-01-05 11:27 UTC (permalink / raw)
To: openembedded-core
From: Ross Burton <ross@burtonini.com>
5.10.85 changed how the GCC plugins are built, which means they now
depend on both GMP and MPC to be built. We already depend on gmp-native,
so add libmpc-native aswell.
Signed-off-by: Ross Burton <ross.burton@arm.com>
---
meta/recipes-kernel/linux/linux-yocto_5.10.bb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meta/recipes-kernel/linux/linux-yocto_5.10.bb b/meta/recipes-kernel/linux/linux-yocto_5.10.bb
index c62157d850..bbb25f7393 100644
--- a/meta/recipes-kernel/linux/linux-yocto_5.10.bb
+++ b/meta/recipes-kernel/linux/linux-yocto_5.10.bb
@@ -36,7 +36,7 @@ LINUX_VERSION ?= "5.10.87"
DEPENDS += "${@bb.utils.contains('ARCH', 'x86', 'elfutils-native', '', d)}"
DEPENDS += "openssl-native util-linux-native"
-DEPENDS += "gmp-native"
+DEPENDS += "gmp-native libmpc-native"
PV = "${LINUX_VERSION}+git${SRCPV}"
--
2.25.1
^ permalink raw reply related
* [PATCH] linux-yocto: add libmpc-native to DEPENDS
From: Ross Burton @ 2022-01-05 11:27 UTC (permalink / raw)
To: openembedded-core
From: Ross Burton <ross@burtonini.com>
5.10.85 changed how the GCC plugins are built, which means they now
depend on both GMP and MPC to be built. We already depend on gmp-native,
so add libmpc-native aswell.
Signed-off-by: Ross Burton <ross.burton@arm.com>
---
meta/recipes-kernel/linux/linux-yocto_5.10.bb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meta/recipes-kernel/linux/linux-yocto_5.10.bb b/meta/recipes-kernel/linux/linux-yocto_5.10.bb
index c62157d850..bbb25f7393 100644
--- a/meta/recipes-kernel/linux/linux-yocto_5.10.bb
+++ b/meta/recipes-kernel/linux/linux-yocto_5.10.bb
@@ -36,7 +36,7 @@ LINUX_VERSION ?= "5.10.87"
DEPENDS += "${@bb.utils.contains('ARCH', 'x86', 'elfutils-native', '', d)}"
DEPENDS += "openssl-native util-linux-native"
-DEPENDS += "gmp-native"
+DEPENDS += "gmp-native libmpc-native"
PV = "${LINUX_VERSION}+git${SRCPV}"
--
2.25.1
^ permalink raw reply related
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: stop including i915_irq.h from i915_drv.h
From: Patchwork @ 2022-01-05 11:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
In-Reply-To: <20220105102131.988791-1-jani.nikula@intel.com>
== Series Details ==
Series: drm/i915: stop including i915_irq.h from i915_drv.h
URL : https://patchwork.freedesktop.org/series/98500/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply
* Re: [PATCH v13 3/5] arm64: perf: Add userspace counter access disable switch
From: Will Deacon @ 2022-01-05 11:25 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Mark Rutland, Peter Zijlstra, Vince Weaver,
Jonathan Corbet, Catalin Marinas, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
Namhyung Kim, Thomas Gleixner, Borislav Petkov,
the arch/x86 maintainers, H. Peter Anvin,
Linux Kernel Mailing List, Linux ARM, linux-perf-users,
Linux-Renesas
In-Reply-To: <20220104135658.GC1827@willie-the-truck>
On Tue, Jan 04, 2022 at 01:56:59PM +0000, Will Deacon wrote:
> On Tue, Dec 28, 2021 at 12:07:02PM +0100, Geert Uytterhoeven wrote:
> > On Wed, Dec 8, 2021 at 9:19 PM Rob Herring <robh@kernel.org> wrote:
> > > Like x86, some users may want to disable userspace PMU counter
> > > altogether. Add a sysctl 'perf_user_access' file to control userspace
> > > counter access. The default is '0' which is disabled. Writing '1'
> > > enables access.
> > >
> > > Note that x86 supports globally enabling user access by writing '2' to
> > > /sys/bus/event_source/devices/cpu/rdpmc. As there's not existing
> > > userspace support to worry about, this shouldn't be necessary for Arm.
> > > It could be added later if the need arises.
> >
> > Thanks for your patch, which is now commit e2012600810c9ded ("arm64:
> > perf: Add userspace counter access disable switch") in arm64/for-next/core.
> >
> > This is causing two issues on Renesas Salvator-XS with R-Car H3.
> > One during kernel boot:
> >
> > hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7
> > counters available
> > +sysctl duplicate entry: /kernel//perf_user_access
> > +CPU: 0 PID: 1 Comm: swapper/0 Not tainted
> > 5.16.0-rc3-arm64-renesas-00003-ge2012600810c #1420
> > +Hardware name: Renesas Salvator-X 2nd version board based on r8a77951 (DT)
> > +Call trace:
> > + dump_backtrace+0x0/0x190
> > + show_stack+0x14/0x20
> > + dump_stack_lvl+0x88/0xb0
> > + dump_stack+0x14/0x2c
> > + __register_sysctl_table+0x384/0x818
> > + register_sysctl+0x20/0x28
> > + armv8_pmu_init.constprop.0+0x118/0x150
> > + armv8_a57_pmu_init+0x1c/0x28
> > + arm_pmu_device_probe+0x1b4/0x558
> > + armv8_pmu_device_probe+0x18/0x20
> > + platform_probe+0x64/0xd0
> > + really_probe+0xb4/0x2f8
> > + __driver_probe_device+0x74/0xd8
> > + driver_probe_device+0x3c/0xe0
> > + __driver_attach+0x80/0x110
> > + bus_for_each_dev+0x6c/0xc0
> > + driver_attach+0x20/0x28
> > + bus_add_driver+0x138/0x1e0
> > + driver_register+0x60/0x110
> > + __platform_driver_register+0x24/0x30
> > + armv8_pmu_driver_init+0x18/0x20
> > + do_one_initcall+0x15c/0x31c
> > + kernel_init_freeable+0x2f0/0x354
> > + kernel_init+0x20/0x120
> > + ret_from_fork+0x10/0x20
> > hw perfevents: enabled with armv8_cortex_a57 PMU driver, 7
> > counters available
> >
> > Presumably the same entry is added twice, once for the A53 PMU,
> > and a second time for the A57 PMU?
>
> Looks like it, and perhaps that's also what is confusing systemd?
> Rob -- how come you didn't see this during your testing?
>
> Anywho, please can you try the untested diff below?
I just remembered I have a big/little SoC on my desk after borrowing a
NanoPi (RK3399) from Marc Z, so I took this diff for a spin there and
both the kernel and systemd seem happy.
Will
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* Re: [PATCH v5 5/6] rockchip/soc/drivers: Add DTPM description for rk3399
From: Daniel Lezcano @ 2022-01-05 11:25 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring
Cc: rjw, lukasz.luba, heiko, arnd, linux-kernel, linux-pm,
Geert Uytterhoeven, moderated list:ARM/Rockchip SoC support,
open list:ARM/Rockchip SoC support
In-Reply-To: <CAPDyKFqWUJTKte3dM=7xG6EtKR8i9neCCNYFs7Jf1J34TezUEQ@mail.gmail.com>
On 31/12/2021 14:57, Ulf Hansson wrote:
[ ... ]
>> +static struct dtpm_node __initdata rk3399_hierarchy[] = {
>> + [0]{ .name = "rk3399" },
>> + [1]{ .name = "package",
>> + .parent = &rk3399_hierarchy[0] },
>> + [2]{ .name = "/cpus/cpu@0",
>> + .type = DTPM_NODE_DT,
>> + .parent = &rk3399_hierarchy[1] },
>> + [3]{ .name = "/cpus/cpu@1",
>> + .type = DTPM_NODE_DT,
>> + .parent = &rk3399_hierarchy[1] },
>> + [4]{ .name = "/cpus/cpu@2",
>> + .type = DTPM_NODE_DT,
>> + .parent = &rk3399_hierarchy[1] },
>> + [5]{ .name = "/cpus/cpu@3",
>> + .type = DTPM_NODE_DT,
>> + .parent = &rk3399_hierarchy[1] },
>> + [6]{ .name = "/cpus/cpu@100",
>> + .type = DTPM_NODE_DT,
>> + .parent = &rk3399_hierarchy[1] },
>> + [7]{ .name = "/cpus/cpu@101",
>> + .type = DTPM_NODE_DT,
>> + .parent = &rk3399_hierarchy[1] },
>> + [8]{ .name = "rockchip,rk3399-mali",
>> + .type = DTPM_NODE_DT,
>> + .parent = &rk3399_hierarchy[1] },
>> + [9]{ },
>> +};
>
> I will not object to this, as in the end this seems like what we need
> to do, unless we can describe things through generic DT bindings for
> DTPM. Right?
Yes, as asked by Rob, we should try to describe in the kernel first.
> Although, if the above is correct, I need to stress that I am kind of
> worried that this doesn't really scale. We would need to copy lots of
> information from the DTS files into platform specific c-files, to be
> able to describe the DTPM hierarchy.
TBH I don't think it is a lot and it is a __initdata. At least we should
begin with something and see later how to consolidate if it is needed, no?
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