* [PATCH] ethernet: ibmveth: use default_groups in kobj_type
From: Greg Kroah-Hartman @ 2022-01-05 18:41 UTC (permalink / raw)
To: linux-kernel
Cc: Cristobal Forno, Greg Kroah-Hartman, netdev, Paul Mackerras,
Jakub Kicinski, linuxppc-dev, David S. Miller
There are currently 2 ways to create a set of sysfs files for a
kobj_type, through the default_attrs field, and the default_groups
field. Move the ibmveth sysfs code to use default_groups
field which has been the preferred way since aa30f47cf666 ("kobject: Add
support for default attribute groups to kobj_type") so that we can soon
get rid of the obsolete default_attrs field.
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Cristobal Forno <cforno12@linux.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: netdev@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/net/ethernet/ibm/ibmveth.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/ibm/ibmveth.c b/drivers/net/ethernet/ibm/ibmveth.c
index 45ba40cf4d07..22fb0d109a68 100644
--- a/drivers/net/ethernet/ibm/ibmveth.c
+++ b/drivers/net/ethernet/ibm/ibmveth.c
@@ -1890,6 +1890,7 @@ static struct attribute *veth_pool_attrs[] = {
&veth_size_attr,
NULL,
};
+ATTRIBUTE_GROUPS(veth_pool);
static const struct sysfs_ops veth_pool_ops = {
.show = veth_pool_show,
@@ -1899,7 +1900,7 @@ static const struct sysfs_ops veth_pool_ops = {
static struct kobj_type ktype_veth_pool = {
.release = NULL,
.sysfs_ops = &veth_pool_ops,
- .default_attrs = veth_pool_attrs,
+ .default_groups = veth_pool_groups,
};
static int ibmveth_resume(struct device *dev)
--
2.34.1
^ permalink raw reply related
* Re: [PATCH] phy: mapphone-mdm6600: Fix PM disable depth imbalance in phy_mdm6600_probe
From: kernel test robot @ 2022-01-05 18:41 UTC (permalink / raw)
To: kbuild-all
In-Reply-To: <20220105123947.17946-1-linmq006@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 5061 bytes --]
Hi Miaoqian,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.16-rc8 next-20220105]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Miaoqian-Lin/phy-mapphone-mdm6600-Fix-PM-disable-depth-imbalance-in-phy_mdm6600_probe/20220105-204113
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git c9e6606c7fe92b50a02ce51dda82586ebdf99b48
config: hexagon-randconfig-r035-20220105 (https://download.01.org/0day-ci/archive/20220106/202201060211.yT7coTKI-lkp(a)intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project d5b6e30ed3acad794dd0aec400e617daffc6cc3d)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/62cad5a4dd9feab731b40f99e6e0bf7a2429f1ed
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Miaoqian-Lin/phy-mapphone-mdm6600-Fix-PM-disable-depth-imbalance-in-phy_mdm6600_probe/20220105-204113
git checkout 62cad5a4dd9feab731b40f99e6e0bf7a2429f1ed
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash drivers/phy/motorola/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/phy/motorola/phy-mapphone-mdm6600.c:633:1: warning: unused label 'disable_pm' [-Wunused-label]
disable_pm:
^~~~~~~~~~~
1 warning generated.
vim +/disable_pm +633 drivers/phy/motorola/phy-mapphone-mdm6600.c
555
556 static int phy_mdm6600_probe(struct platform_device *pdev)
557 {
558 struct phy_mdm6600 *ddata;
559 int error;
560
561 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
562 if (!ddata)
563 return -ENOMEM;
564
565 INIT_DELAYED_WORK(&ddata->bootup_work,
566 phy_mdm6600_deferred_power_on);
567 INIT_DELAYED_WORK(&ddata->status_work, phy_mdm6600_status);
568 INIT_DELAYED_WORK(&ddata->modem_wake_work, phy_mdm6600_modem_wake);
569 init_completion(&ddata->ack);
570
571 ddata->dev = &pdev->dev;
572 platform_set_drvdata(pdev, ddata);
573
574 /* Active state selected in phy_mdm6600_power_on() */
575 error = pinctrl_pm_select_sleep_state(ddata->dev);
576 if (error)
577 dev_warn(ddata->dev, "%s: error with sleep_state: %i\n",
578 __func__, error);
579
580 error = phy_mdm6600_init_lines(ddata);
581 if (error)
582 return error;
583
584 phy_mdm6600_init_irq(ddata);
585 schedule_delayed_work(&ddata->bootup_work, 0);
586
587 /*
588 * See phy_mdm6600_device_power_on(). We should be able
589 * to remove this eventually when ohci-platform can deal
590 * with -EPROBE_DEFER.
591 */
592 msleep(PHY_MDM6600_PHY_DELAY_MS + 500);
593
594 /*
595 * Enable PM runtime only after PHY has been powered up properly.
596 * It is currently only needed after USB suspends mdm6600 and n_gsm
597 * needs to access the device. We don't want to do this earlier as
598 * gpio mode0 pin doubles as mdm6600 wake-up gpio.
599 */
600 pm_runtime_use_autosuspend(ddata->dev);
601 pm_runtime_set_autosuspend_delay(ddata->dev,
602 MDM6600_MODEM_IDLE_DELAY_MS);
603 pm_runtime_enable(ddata->dev);
604 error = pm_runtime_get_sync(ddata->dev);
605 if (error < 0) {
606 dev_warn(ddata->dev, "failed to wake modem: %i\n", error);
607 pm_runtime_put_noidle(ddata->dev);
608 goto cleanup;
609 }
610
611 ddata->generic_phy = devm_phy_create(ddata->dev, NULL, &gpio_usb_ops);
612 if (IS_ERR(ddata->generic_phy)) {
613 error = PTR_ERR(ddata->generic_phy);
614 goto idle;
615 }
616
617 phy_set_drvdata(ddata->generic_phy, ddata);
618
619 ddata->phy_provider =
620 devm_of_phy_provider_register(ddata->dev,
621 of_phy_simple_xlate);
622 if (IS_ERR(ddata->phy_provider))
623 error = PTR_ERR(ddata->phy_provider);
624
625 idle:
626 pm_runtime_mark_last_busy(ddata->dev);
627 pm_runtime_put_autosuspend(ddata->dev);
628
629 cleanup:
630 if (error < 0)
631 phy_mdm6600_device_power_off(ddata);
632
> 633 disable_pm:
634 pm_runtime_disable(ddata->dev);
635
636 return error;
637 }
638
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply
* Re: [PATCH net-next] net: gemini: allow any RGMII interface mode
From: patchwork-bot+netdevbpf @ 2022-01-05 18:40 UTC (permalink / raw)
To: Russell King
Cc: andrew, hkallweit1, davem, netdev, ulli.kroll, linus.walleij,
kuba, linux-arm-kernel
In-Reply-To: <E1n4mpT-002PLd-Ha@rmk-PC.armlinux.org.uk>
Hello:
This patch was applied to netdev/net-next.git (master)
by Jakub Kicinski <kuba@kernel.org>:
On Tue, 04 Jan 2022 16:38:31 +0000 you wrote:
> The four RGMII interface modes take care of the required RGMII delay
> configuration at the PHY and should not be limited by the network MAC
> driver. Sadly, gemini was only permitting RGMII mode with no delays,
> which would require the required delay to be inserted via PCB tracking
> or by the MAC.
>
> However, there are designs that require the PHY to add the delay, which
> is impossible without Gemini permitting the other three PHY interface
> modes. Fix the driver to allow these.
>
> [...]
Here is the summary with links:
- [net-next] net: gemini: allow any RGMII interface mode
https://git.kernel.org/netdev/net-next/c/4e4f325a0a55
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
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^ permalink raw reply
* [PATCH] ethernet: ibmveth: use default_groups in kobj_type
From: Greg Kroah-Hartman @ 2022-01-05 18:41 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, Michael Ellerman, Benjamin Herrenschmidt,
Paul Mackerras, Cristobal Forno, David S. Miller, Jakub Kicinski,
linuxppc-dev, netdev
There are currently 2 ways to create a set of sysfs files for a
kobj_type, through the default_attrs field, and the default_groups
field. Move the ibmveth sysfs code to use default_groups
field which has been the preferred way since aa30f47cf666 ("kobject: Add
support for default attribute groups to kobj_type") so that we can soon
get rid of the obsolete default_attrs field.
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Cristobal Forno <cforno12@linux.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: netdev@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/net/ethernet/ibm/ibmveth.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/ibm/ibmveth.c b/drivers/net/ethernet/ibm/ibmveth.c
index 45ba40cf4d07..22fb0d109a68 100644
--- a/drivers/net/ethernet/ibm/ibmveth.c
+++ b/drivers/net/ethernet/ibm/ibmveth.c
@@ -1890,6 +1890,7 @@ static struct attribute *veth_pool_attrs[] = {
&veth_size_attr,
NULL,
};
+ATTRIBUTE_GROUPS(veth_pool);
static const struct sysfs_ops veth_pool_ops = {
.show = veth_pool_show,
@@ -1899,7 +1900,7 @@ static const struct sysfs_ops veth_pool_ops = {
static struct kobj_type ktype_veth_pool = {
.release = NULL,
.sysfs_ops = &veth_pool_ops,
- .default_attrs = veth_pool_attrs,
+ .default_groups = veth_pool_groups,
};
static int ibmveth_resume(struct device *dev)
--
2.34.1
^ permalink raw reply related
* Re: [bug] GNOME loses all settings following failure to resume from suspend
From: Chris Murphy @ 2022-01-05 18:40 UTC (permalink / raw)
To: Filipe Manana; +Cc: Chris Murphy, Btrfs BTRFS, Josef Bacik, David Sterba
In-Reply-To: <YdXdtrHb9nTYgFo7@debian9.Home>
On Wed, Jan 5, 2022 at 11:04 AM Filipe Manana <fdmanana@kernel.org> wrote:
>
> Looking at the code before that patch, it explicitly skips fsync after
> a rename pointing out to:
>
> https://btrfs.wiki.kernel.org/index.php/FAQ#What_are_the_crash_guarantees_of_overwrite-by-rename.3F
>
> I'm afraid that information is wrong, perhaps it might have been true in
> some very distant past, but certainly not for many years.
However, the system does suspend correctly and before that there
should be "Filesystems sync" message from the kernel (this is the case
on my laptops, unconfirmed for the GNOME bug case). [1]
If the sequence is:
write to file
no fsync
"filesystem sync" (I guess that's syncfs for all mounted filesystems? no idea)
suspend
crash
Still seems like the file should be either old or new, not 0 length?
> I don't think I have a wiki account enabled, but I'll see if I get that
> updated soon.
Thanks Felipe!
[1] "Filesystems sync" message appears to come from here
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/power/main.c?h=v5.16-rc8#n62
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/power/main.c?h=v5.16-rc8#n195
--
Chris Murphy
^ permalink raw reply
* Re: [PATCH net-next 0/2] Fix RGMII delays for 88E1118
From: patchwork-bot+netdevbpf @ 2022-01-05 18:40 UTC (permalink / raw)
To: Russell King; +Cc: andrew, hkallweit1, clabbe.montjoie, davem, kuba, netdev
In-Reply-To: <YdR3wYFkm4eJApwb@shell.armlinux.org.uk>
Hello:
This series was applied to netdev/net-next.git (master)
by Jakub Kicinski <kuba@kernel.org>:
On Tue, 4 Jan 2022 16:37:21 +0000 you wrote:
> Hi,
>
> This series fixes the RGMII delays for 88E1118 Marvell PHYs, after a
> report by Corentin Labbe that the Marvell driver fails to work.
>
> Patch 1 cleans up the paged register accesses in m88e1118_config_init()
> and patch 2 adds the RGMII delay configuration.
>
> [...]
Here is the summary with links:
- [net-next,1/2] net: phy: marvell: use phy_write_paged() to set MSCR
https://git.kernel.org/netdev/net-next/c/5b8f970309dd
- [net-next,2/2] net: phy: marvell: configure RGMII delays for 88E1118
https://git.kernel.org/netdev/net-next/c/f22725c95ece
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH net-next] net: gemini: allow any RGMII interface mode
From: patchwork-bot+netdevbpf @ 2022-01-05 18:40 UTC (permalink / raw)
To: Russell King
Cc: andrew, hkallweit1, davem, netdev, ulli.kroll, linus.walleij,
kuba, linux-arm-kernel
In-Reply-To: <E1n4mpT-002PLd-Ha@rmk-PC.armlinux.org.uk>
Hello:
This patch was applied to netdev/net-next.git (master)
by Jakub Kicinski <kuba@kernel.org>:
On Tue, 04 Jan 2022 16:38:31 +0000 you wrote:
> The four RGMII interface modes take care of the required RGMII delay
> configuration at the PHY and should not be limited by the network MAC
> driver. Sadly, gemini was only permitting RGMII mode with no delays,
> which would require the required delay to be inserted via PCB tracking
> or by the MAC.
>
> However, there are designs that require the PHY to add the delay, which
> is impossible without Gemini permitting the other three PHY interface
> modes. Fix the driver to allow these.
>
> [...]
Here is the summary with links:
- [net-next] net: gemini: allow any RGMII interface mode
https://git.kernel.org/netdev/net-next/c/4e4f325a0a55
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH v2 net-next 2/7] net: dsa: merge all bools of struct dsa_port into a single u8
From: Vladimir Oltean @ 2022-01-05 18:39 UTC (permalink / raw)
To: Florian Fainelli
Cc: netdev@vger.kernel.org, David S. Miller, Jakub Kicinski,
Andrew Lunn, Vivien Didelot
In-Reply-To: <d41c058c-d20f-2e9f-ea2c-0a26bdb5fea3@gmail.com>
Hi Florian,
On Wed, Jan 05, 2022 at 10:30:54AM -0800, Florian Fainelli wrote:
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Thanks a lot for the review.
I'm a bit on the fence on this patch and the other one for dsa_switch.
The thing is that bit fields are not atomic in C89, so if we update any
of the flags inside dp or ds concurrently (like dp->vlan_filtering),
we're in trouble. Right now this isn't a problem, because most of the
flags are set either during probe, or during ds->ops->setup, or are
serialized by the rtnl_mutex in ways that are there to stay (switchdev
notifiers). That's why I didn't say anything about it. But it may be a
caveat to watch out for in the future. Do you think we need to do
something about it? A lock would not be necessary, strictly speaking.
^ permalink raw reply
* Re: [PATCH v2 net-next 0/7] Cleanup to main DSA structures
From: Florian Fainelli @ 2022-01-05 18:39 UTC (permalink / raw)
To: Vladimir Oltean, netdev
Cc: David S. Miller, Jakub Kicinski, Andrew Lunn, Vivien Didelot
In-Reply-To: <20220105132141.2648876-1-vladimir.oltean@nxp.com>
On 1/5/22 5:21 AM, Vladimir Oltean wrote:
> This series contains changes that do the following:
>
> - struct dsa_port reduced from 576 to 544 bytes, and first cache line a
> bit better organized
> - struct dsa_switch from 160 to 136 bytes, and first cache line a bit
> better organized
> - struct dsa_switch_tree from 112 to 104 bytes, and first cache line a
> bit better organized
>
> No changes compared to v1, just split into a separate patch set.
This is all looking good to me. I suppose we could possibly swap the
'nh' and 'tag_ops' member since dst->tag_ops is used in
dsa_tag_generic_flow_dissect() which is a fast path, what do you think?
--
Florian
^ permalink raw reply
* Re: [PATCH] dma-buf: Move sysfs work out of DMA-BUF export/release path
From: Hridya Valsaraju @ 2022-01-05 18:38 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Sumit Semwal, Christian König, Daniel Vetter, linux-media,
dri-devel, linaro-mm-sig, linux-kernel, john.stultz, surenb,
kaleshsingh, tjmercier, keescook
In-Reply-To: <YdW1hPRvKYjfORvp@kroah.com>
On Wed, Jan 5, 2022 at 7:13 AM Greg Kroah-Hartman
<gregkh@linuxfoundation.org> wrote:
>
> On Tue, Jan 04, 2022 at 03:51:48PM -0800, Hridya Valsaraju wrote:
> > Recently, we noticed an issue where a process went into direct reclaim
> > while holding the kernfs rw semaphore for sysfs in write(exclusive)
> > mode. This caused processes who were doing DMA-BUF exports and releases
> > to go into uninterruptible sleep since they needed to acquire the same
> > semaphore for the DMA-BUF sysfs entry creation/deletion. In order to avoid
> > blocking DMA-BUF export/release for an indeterminate amount of time
> > while another process is holding the sysfs rw semaphore in exclusive
> > mode, this patch moves the per-buffer sysfs file creation/deleteion to
> > a kthread.
> >
> > Fixes: bdb8d06dfefd ("dmabuf: Add the capability to expose DMA-BUF stats in sysfs")
> > Signed-off-by: Hridya Valsaraju <hridya@google.com>
> > ---
> > drivers/dma-buf/dma-buf-sysfs-stats.c | 343 ++++++++++++++++++++++++--
> > include/linux/dma-buf.h | 46 ++++
> > 2 files changed, 366 insertions(+), 23 deletions(-)
>
> Crazy, but if this works in your testing, it looks ok to me. Nice work.
>
> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Thank you for the review Greg :)
^ permalink raw reply
* Re: [PATCH] dma-buf: Move sysfs work out of DMA-BUF export/release path
From: Hridya Valsaraju @ 2022-01-05 18:38 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Daniel Vetter, keescook, linux-kernel, dri-devel,
Christian König, linaro-mm-sig, kaleshsingh, surenb,
tjmercier, linux-media
In-Reply-To: <YdW1hPRvKYjfORvp@kroah.com>
On Wed, Jan 5, 2022 at 7:13 AM Greg Kroah-Hartman
<gregkh@linuxfoundation.org> wrote:
>
> On Tue, Jan 04, 2022 at 03:51:48PM -0800, Hridya Valsaraju wrote:
> > Recently, we noticed an issue where a process went into direct reclaim
> > while holding the kernfs rw semaphore for sysfs in write(exclusive)
> > mode. This caused processes who were doing DMA-BUF exports and releases
> > to go into uninterruptible sleep since they needed to acquire the same
> > semaphore for the DMA-BUF sysfs entry creation/deletion. In order to avoid
> > blocking DMA-BUF export/release for an indeterminate amount of time
> > while another process is holding the sysfs rw semaphore in exclusive
> > mode, this patch moves the per-buffer sysfs file creation/deleteion to
> > a kthread.
> >
> > Fixes: bdb8d06dfefd ("dmabuf: Add the capability to expose DMA-BUF stats in sysfs")
> > Signed-off-by: Hridya Valsaraju <hridya@google.com>
> > ---
> > drivers/dma-buf/dma-buf-sysfs-stats.c | 343 ++++++++++++++++++++++++--
> > include/linux/dma-buf.h | 46 ++++
> > 2 files changed, 366 insertions(+), 23 deletions(-)
>
> Crazy, but if this works in your testing, it looks ok to me. Nice work.
>
> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Thank you for the review Greg :)
^ permalink raw reply
* Re: [PATCH v2 net-next 0/7] Cleanup to main DSA structures
From: Florian Fainelli @ 2022-01-05 18:37 UTC (permalink / raw)
To: Vladimir Oltean, netdev@vger.kernel.org
Cc: David S. Miller, Jakub Kicinski, Andrew Lunn, Vivien Didelot
In-Reply-To: <20220105142838.uzanzmozesap63om@skbuf>
On 1/5/22 6:28 AM, Vladimir Oltean wrote:
> On Wed, Jan 05, 2022 at 03:21:34PM +0200, Vladimir Oltean wrote:
>> This series contains changes that do the following:
>>
>> - struct dsa_port reduced from 576 to 544 bytes, and first cache line a
>> bit better organized
>> - struct dsa_switch from 160 to 136 bytes, and first cache line a bit
>> better organized
>> - struct dsa_switch_tree from 112 to 104 bytes, and first cache line a
>> bit better organized
>>
>> No changes compared to v1, just split into a separate patch set.
>>
>> Vladimir Oltean (7):
>> net: dsa: move dsa_port :: stp_state near dsa_port :: mac
>> net: dsa: merge all bools of struct dsa_port into a single u8
>> net: dsa: move dsa_port :: type near dsa_port :: index
>> net: dsa: merge all bools of struct dsa_switch into a single u32
>> net: dsa: make dsa_switch :: num_ports an unsigned int
>> net: dsa: move dsa_switch_tree :: ports and lags to first cache line
>> net: dsa: combine two holes in struct dsa_switch_tree
>>
>> include/net/dsa.h | 146 +++++++++++++++++++++++++---------------------
>> net/dsa/dsa2.c | 2 +-
>> 2 files changed, 81 insertions(+), 67 deletions(-)
>>
>> --
>> 2.25.1
>>
>
> Let's keep this version for review only (RFC). For the final version I
> just figured that I can use this syntax:
>
> u8 vlan_filtering:1;
>
> /* Managed by DSA on user ports and by drivers on CPU and DSA ports */
> u8 learning:1;
>
> u8 lag_tx_enabled:1;
>
> u8 devlink_port_setup:1;
>
> u8 setup:1;
>
> instead of this syntax:
>
> u8 vlan_filtering:1,
> /* Managed by DSA on user ports and by
> * drivers on CPU and DSA ports
> */
> learning:1,
> lag_tx_enabled:1,
> devlink_port_setup:1,
> setup:1;
>
> which is what I'm going to prefer.
Yes this is indeed more readable. Thanks!
--
Florian
^ permalink raw reply
* [PATCH] efi: use default_groups in kobj_type
From: Greg Kroah-Hartman @ 2022-01-05 18:37 UTC (permalink / raw)
To: linux-kernel; +Cc: Greg Kroah-Hartman, Ard Biesheuvel, linux-efi
There are currently 2 ways to create a set of sysfs files for a
kobj_type, through the default_attrs field, and the default_groups
field. Move the firmware efi sysfs code to use default_groups
field which has been the preferred way since aa30f47cf666 ("kobject: Add
support for default attribute groups to kobj_type") so that we can soon
get rid of the obsolete default_attrs field.
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: linux-efi@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/firmware/efi/efivars.c | 3 ++-
drivers/firmware/efi/esrt.c | 4 +++-
drivers/firmware/efi/runtime-map.c | 3 ++-
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/efi/efivars.c b/drivers/firmware/efi/efivars.c
index e6b16b3a17a8..ea0bc39dc965 100644
--- a/drivers/firmware/efi/efivars.c
+++ b/drivers/firmware/efi/efivars.c
@@ -352,11 +352,12 @@ static struct attribute *def_attrs[] = {
&efivar_attr_raw_var.attr,
NULL,
};
+ATTRIBUTE_GROUPS(def);
static struct kobj_type efivar_ktype = {
.release = efivar_release,
.sysfs_ops = &efivar_attr_ops,
- .default_attrs = def_attrs,
+ .default_groups = def_groups,
};
static ssize_t efivar_create(struct file *filp, struct kobject *kobj,
diff --git a/drivers/firmware/efi/esrt.c b/drivers/firmware/efi/esrt.c
index d5915272141f..2a2f52b017e7 100644
--- a/drivers/firmware/efi/esrt.c
+++ b/drivers/firmware/efi/esrt.c
@@ -146,6 +146,8 @@ static struct attribute *esre1_attrs[] = {
&esre_last_attempt_status.attr,
NULL
};
+ATTRIBUTE_GROUPS(esre1);
+
static void esre_release(struct kobject *kobj)
{
struct esre_entry *entry = to_entry(kobj);
@@ -157,7 +159,7 @@ static void esre_release(struct kobject *kobj)
static struct kobj_type esre1_ktype = {
.release = esre_release,
.sysfs_ops = &esre_attr_ops,
- .default_attrs = esre1_attrs,
+ .default_groups = esre1_groups,
};
diff --git a/drivers/firmware/efi/runtime-map.c b/drivers/firmware/efi/runtime-map.c
index ad9ddefc9dcb..92a3d45a795c 100644
--- a/drivers/firmware/efi/runtime-map.c
+++ b/drivers/firmware/efi/runtime-map.c
@@ -79,6 +79,7 @@ static struct attribute *def_attrs[] = {
&map_attribute_attr.attr,
NULL
};
+ATTRIBUTE_GROUPS(def);
static const struct sysfs_ops map_attr_ops = {
.show = map_attr_show,
@@ -94,7 +95,7 @@ static void map_release(struct kobject *kobj)
static struct kobj_type __refdata map_ktype = {
.sysfs_ops = &map_attr_ops,
- .default_attrs = def_attrs,
+ .default_groups = def_groups,
.release = map_release,
};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 net-next 6/7] net: dsa: move dsa_switch_tree :: ports and lags to first cache line
From: Florian Fainelli @ 2022-01-05 18:34 UTC (permalink / raw)
To: Vladimir Oltean, netdev
Cc: David S. Miller, Jakub Kicinski, Andrew Lunn, Vivien Didelot
In-Reply-To: <20220105132141.2648876-7-vladimir.oltean@nxp.com>
On 1/5/22 5:21 AM, Vladimir Oltean wrote:
> dst->ports is accessed most notably by dsa_master_find_slave(), which is
> invoked in the RX path.
>
> dst->lags is accessed by dsa_lag_dev(), which is invoked in the RX path
> of tag_dsa.c.
>
> dst->tag_ops, dst->default_proto and dst->pd don't need to be in the
> first cache line, so they are moved out by this change.
>
> Before:
>
> pahole -C dsa_switch_tree net/dsa/slave.o
> struct dsa_switch_tree {
> struct list_head list; /* 0 16 */
> struct raw_notifier_head nh; /* 16 8 */
> unsigned int index; /* 24 4 */
> struct kref refcount; /* 28 4 */
> bool setup; /* 32 1 */
>
> /* XXX 7 bytes hole, try to pack */
>
> const struct dsa_device_ops * tag_ops; /* 40 8 */
> enum dsa_tag_protocol default_proto; /* 48 4 */
>
> /* XXX 4 bytes hole, try to pack */
>
> struct dsa_platform_data * pd; /* 56 8 */
> /* --- cacheline 1 boundary (64 bytes) --- */
> struct list_head ports; /* 64 16 */
> struct list_head rtable; /* 80 16 */
> struct net_device * * lags; /* 96 8 */
> unsigned int lags_len; /* 104 4 */
> unsigned int last_switch; /* 108 4 */
>
> /* size: 112, cachelines: 2, members: 13 */
> /* sum members: 101, holes: 2, sum holes: 11 */
> /* last cacheline: 48 bytes */
> };
>
> After:
>
> pahole -C dsa_switch_tree net/dsa/slave.o
> struct dsa_switch_tree {
> struct list_head list; /* 0 16 */
> struct list_head ports; /* 16 16 */
> struct raw_notifier_head nh; /* 32 8 */
> unsigned int index; /* 40 4 */
> struct kref refcount; /* 44 4 */
> struct net_device * * lags; /* 48 8 */
> bool setup; /* 56 1 */
>
> /* XXX 7 bytes hole, try to pack */
>
> /* --- cacheline 1 boundary (64 bytes) --- */
> const struct dsa_device_ops * tag_ops; /* 64 8 */
> enum dsa_tag_protocol default_proto; /* 72 4 */
>
> /* XXX 4 bytes hole, try to pack */
>
> struct dsa_platform_data * pd; /* 80 8 */
> struct list_head rtable; /* 88 16 */
> unsigned int lags_len; /* 104 4 */
> unsigned int last_switch; /* 108 4 */
>
> /* size: 112, cachelines: 2, members: 13 */
> /* sum members: 101, holes: 2, sum holes: 11 */
> /* last cacheline: 48 bytes */
> };
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply
* Re: [PATCH v2 net-next 7/7] net: dsa: combine two holes in struct dsa_switch_tree
From: Florian Fainelli @ 2022-01-05 18:34 UTC (permalink / raw)
To: Vladimir Oltean, netdev
Cc: David S. Miller, Jakub Kicinski, Andrew Lunn, Vivien Didelot
In-Reply-To: <20220105132141.2648876-8-vladimir.oltean@nxp.com>
On 1/5/22 5:21 AM, Vladimir Oltean wrote:
> There is a 7 byte hole after dst->setup and a 4 byte hole after
> dst->default_proto. Combining them, we have a single hole of just 3
> bytes on 64 bit machines.
>
> Before:
>
> pahole -C dsa_switch_tree net/dsa/slave.o
> struct dsa_switch_tree {
> struct list_head list; /* 0 16 */
> struct list_head ports; /* 16 16 */
> struct raw_notifier_head nh; /* 32 8 */
> unsigned int index; /* 40 4 */
> struct kref refcount; /* 44 4 */
> struct net_device * * lags; /* 48 8 */
> bool setup; /* 56 1 */
>
> /* XXX 7 bytes hole, try to pack */
>
> /* --- cacheline 1 boundary (64 bytes) --- */
> const struct dsa_device_ops * tag_ops; /* 64 8 */
> enum dsa_tag_protocol default_proto; /* 72 4 */
>
> /* XXX 4 bytes hole, try to pack */
>
> struct dsa_platform_data * pd; /* 80 8 */
> struct list_head rtable; /* 88 16 */
> unsigned int lags_len; /* 104 4 */
> unsigned int last_switch; /* 108 4 */
>
> /* size: 112, cachelines: 2, members: 13 */
> /* sum members: 101, holes: 2, sum holes: 11 */
> /* last cacheline: 48 bytes */
> };
>
> After:
>
> pahole -C dsa_switch_tree net/dsa/slave.o
> struct dsa_switch_tree {
> struct list_head list; /* 0 16 */
> struct list_head ports; /* 16 16 */
> struct raw_notifier_head nh; /* 32 8 */
> unsigned int index; /* 40 4 */
> struct kref refcount; /* 44 4 */
> struct net_device * * lags; /* 48 8 */
> const struct dsa_device_ops * tag_ops; /* 56 8 */
> /* --- cacheline 1 boundary (64 bytes) --- */
> enum dsa_tag_protocol default_proto; /* 64 4 */
> bool setup; /* 68 1 */
>
> /* XXX 3 bytes hole, try to pack */
>
> struct dsa_platform_data * pd; /* 72 8 */
> struct list_head rtable; /* 80 16 */
> unsigned int lags_len; /* 96 4 */
> unsigned int last_switch; /* 100 4 */
>
> /* size: 104, cachelines: 2, members: 13 */
> /* sum members: 101, holes: 1, sum holes: 3 */
> /* last cacheline: 40 bytes */
> };
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply
* [PATCH v2 3/7] iio: adc: qcom-spmi-rradc: introduce round robin adc
From: Caleb Connolly @ 2022-01-05 18:33 UTC (permalink / raw)
To: caleb.connolly, Jonathan Cameron, Lars-Peter Clausen, Rob Herring,
Andy Gross, Bjorn Andersson, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-msm
Cc: sumit.semwal, amit.pundir, john.stultz
In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org>
The Round Robin ADC is responsible for reading data about the rate of
charge from the USB or DC in jacks, it can also read the battery
ID (resistence) and some temperatures. It is found on the PMI8998 and
PM660 Qualcomm PMICs.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
drivers/iio/adc/Kconfig | 13 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/qcom-spmi-rradc.c | 1070 +++++++++++++++++++++++++++++
3 files changed, 1084 insertions(+)
create mode 100644 drivers/iio/adc/qcom-spmi-rradc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 3363af15a43f..37f18ee4c4c5 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -812,6 +812,19 @@ config QCOM_PM8XXX_XOADC
To compile this driver as a module, choose M here: the module
will be called qcom-pm8xxx-xoadc.
+config QCOM_SPMI_RRADC
+ tristate "Qualcomm SPMI RRADC"
+ depends on MFD_SPMI_PMIC
+ help
+ This is for the PMIC Round Robin ADC driver.
+
+ This driver exposes the battery ID resistor, battery thermal, PMIC die
+ temperature, charger USB in and DC in voltage and current.
+
+ To compile this driver as a module, choose M here: the module will
+ be called qcom-qpmi-rradc.
+
+
config QCOM_SPMI_IADC
tristate "Qualcomm SPMI PMIC current ADC"
depends on SPMI
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d3f53549720c..ca8bad549175 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_NPCM_ADC) += npcm_adc.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o
obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
+obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o
obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o
obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o
diff --git a/drivers/iio/adc/qcom-spmi-rradc.c b/drivers/iio/adc/qcom-spmi-rradc.c
new file mode 100644
index 000000000000..e5c3b249bc0f
--- /dev/null
+++ b/drivers/iio/adc/qcom-spmi-rradc.c
@@ -0,0 +1,1070 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 Linaro Limited.
+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
+ *
+ * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs.
+ */
+
+#include <linux/delay.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/types.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/regmap.h>
+#include <linux/spmi.h>
+#include <linux/types.h>
+#include <asm-generic/unaligned.h>
+#include <linux/units.h>
+#include <soc/qcom/qcom-pmic.h>
+
+#define RR_ADC_EN_CTL 0x46
+#define RR_ADC_SKIN_TEMP_LSB 0x50
+#define RR_ADC_SKIN_TEMP_MSB 0x51
+#define RR_ADC_RR_ADC_CTL 0x52
+#define RR_ADC_ADC_CTL_CONTINUOUS_SEL BIT(3)
+#define RR_ADC_ADC_LOG 0x53
+#define RR_ADC_ADC_LOG_CLR_CTRL BIT(0)
+
+#define RR_ADC_FAKE_BATT_LOW_LSB 0x58
+#define RR_ADC_FAKE_BATT_LOW_MSB 0x59
+#define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A
+#define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B
+
+#define RR_ADC_BATT_ID_CTRL 0x60
+#define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0)
+#define RR_ADC_BATT_ID_TRIGGER 0x61
+#define RR_ADC_BATT_ID_STS 0x62
+#define RR_ADC_BATT_ID_CFG 0x63
+#define BATT_ID_SETTLE_MASK GENMASK(7, 5)
+#define RR_ADC_BATT_ID_5_LSB 0x66
+#define RR_ADC_BATT_ID_5_MSB 0x67
+#define RR_ADC_BATT_ID_15_LSB 0x68
+#define RR_ADC_BATT_ID_15_MSB 0x69
+#define RR_ADC_BATT_ID_150_LSB 0x6A
+#define RR_ADC_BATT_ID_150_MSB 0x6B
+
+#define RR_ADC_BATT_THERM_CTRL 0x70
+#define RR_ADC_BATT_THERM_TRIGGER 0x71
+#define RR_ADC_BATT_THERM_STS 0x72
+#define RR_ADC_BATT_THERM_CFG 0x73
+#define RR_ADC_BATT_THERM_LSB 0x74
+#define RR_ADC_BATT_THERM_MSB 0x75
+#define RR_ADC_BATT_THERM_FREQ 0x76
+
+#define RR_ADC_AUX_THERM_CTRL 0x80
+#define RR_ADC_AUX_THERM_TRIGGER 0x81
+#define RR_ADC_AUX_THERM_STS 0x82
+#define RR_ADC_AUX_THERM_CFG 0x83
+#define RR_ADC_AUX_THERM_LSB 0x84
+#define RR_ADC_AUX_THERM_MSB 0x85
+
+#define RR_ADC_SKIN_HOT 0x86
+#define RR_ADC_SKIN_TOO_HOT 0x87
+
+#define RR_ADC_AUX_THERM_C1 0x88
+#define RR_ADC_AUX_THERM_C2 0x89
+#define RR_ADC_AUX_THERM_C3 0x8A
+#define RR_ADC_AUX_THERM_HALF_RANGE 0x8B
+
+#define RR_ADC_USB_IN_V_CTRL 0x90
+#define RR_ADC_USB_IN_V_TRIGGER 0x91
+#define RR_ADC_USB_IN_V_STS 0x92
+#define RR_ADC_USB_IN_V_LSB 0x94
+#define RR_ADC_USB_IN_V_MSB 0x95
+#define RR_ADC_USB_IN_I_CTRL 0x98
+#define RR_ADC_USB_IN_I_TRIGGER 0x99
+#define RR_ADC_USB_IN_I_STS 0x9A
+#define RR_ADC_USB_IN_I_LSB 0x9C
+#define RR_ADC_USB_IN_I_MSB 0x9D
+
+#define RR_ADC_DC_IN_V_CTRL 0xA0
+#define RR_ADC_DC_IN_V_TRIGGER 0xA1
+#define RR_ADC_DC_IN_V_STS 0xA2
+#define RR_ADC_DC_IN_V_LSB 0xA4
+#define RR_ADC_DC_IN_V_MSB 0xA5
+#define RR_ADC_DC_IN_I_CTRL 0xA8
+#define RR_ADC_DC_IN_I_TRIGGER 0xA9
+#define RR_ADC_DC_IN_I_STS 0xAA
+#define RR_ADC_DC_IN_I_LSB 0xAC
+#define RR_ADC_DC_IN_I_MSB 0xAD
+
+#define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0
+#define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1
+#define RR_ADC_PMI_DIE_TEMP_STS 0xB2
+#define RR_ADC_PMI_DIE_TEMP_CFG 0xB3
+#define RR_ADC_PMI_DIE_TEMP_LSB 0xB4
+#define RR_ADC_PMI_DIE_TEMP_MSB 0xB5
+
+#define RR_ADC_CHARGER_TEMP_CTRL 0xB8
+#define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9
+#define RR_ADC_CHARGER_TEMP_STS 0xBA
+#define RR_ADC_CHARGER_TEMP_CFG 0xBB
+#define RR_ADC_CHARGER_TEMP_LSB 0xBC
+#define RR_ADC_CHARGER_TEMP_MSB 0xBD
+#define RR_ADC_CHARGER_HOT 0xBE
+#define RR_ADC_CHARGER_TOO_HOT 0xBF
+
+#define RR_ADC_GPIO_CTRL 0xC0
+#define RR_ADC_GPIO_TRIGGER 0xC1
+#define RR_ADC_GPIO_STS 0xC2
+#define RR_ADC_GPIO_LSB 0xC4
+#define RR_ADC_GPIO_MSB 0xC5
+
+#define RR_ADC_ATEST_CTRL 0xC8
+#define RR_ADC_ATEST_TRIGGER 0xC9
+#define RR_ADC_ATEST_STS 0xCA
+#define RR_ADC_ATEST_LSB 0xCC
+#define RR_ADC_ATEST_MSB 0xCD
+#define RR_ADC_SEC_ACCESS 0xD0
+
+#define RR_ADC_PERPH_RESET_CTL2 0xD9
+#define RR_ADC_PERPH_RESET_CTL3 0xDA
+#define RR_ADC_PERPH_RESET_CTL4 0xDB
+#define RR_ADC_INT_TEST1 0xE0
+#define RR_ADC_INT_TEST_VAL 0xE1
+
+#define RR_ADC_TM_TRIGGER_CTRLS 0xE2
+#define RR_ADC_TM_ADC_CTRLS 0xE3
+#define RR_ADC_TM_CNL_CTRL 0xE4
+#define RR_ADC_TM_BATT_ID_CTRL 0xE5
+#define RR_ADC_TM_THERM_CTRL 0xE6
+#define RR_ADC_TM_CONV_STS 0xE7
+#define RR_ADC_TM_ADC_READ_LSB 0xE8
+#define RR_ADC_TM_ADC_READ_MSB 0xE9
+#define RR_ADC_TM_ATEST_MUX_1 0xEA
+#define RR_ADC_TM_ATEST_MUX_2 0xEB
+#define RR_ADC_TM_REFERENCES 0xED
+#define RR_ADC_TM_MISC_CTL 0xEE
+#define RR_ADC_TM_RR_CTRL 0xEF
+
+#define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7)
+#define RR_ADC_TRIGGER_CTL BIT(0)
+
+#define RR_ADC_BATT_ID_RANGE 820
+
+#define RR_ADC_BITS 10
+#define RR_ADC_CHAN_MAX_VALUE (1 << RR_ADC_BITS)
+#define RR_ADC_FS_VOLTAGE_MV 2500
+
+/* BATT_THERM 0.25K/LSB */
+#define RR_ADC_BATT_THERM_LSB_K 4
+
+#define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000
+#define RR_ADC_TEMP_FS_VOLTAGE_DEN 3
+#define RR_ADC_DIE_TEMP_OFFSET 601400
+#define RR_ADC_DIE_TEMP_SLOPE 2
+#define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000
+
+#define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168
+#define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784
+#define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433
+#define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655
+#define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001
+#define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403
+#define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898
+#define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596
+#define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779
+#define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496
+#define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000
+#define RR_ADC_CHG_THRESHOLD_SCALE 4
+
+#define RR_ADC_VOLT_INPUT_FACTOR 8
+#define RR_ADC_CURR_INPUT_FACTOR 2000
+#define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886
+#define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9
+#define RR_ADC_CURR_USBIN_660_UV_VAL 579500
+
+#define RR_ADC_GPIO_FS_RANGE 5000
+#define RR_ADC_COHERENT_CHECK_RETRY 5
+#define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16
+
+#define RR_ADC_STS_CHANNEL_READING_MASK 0x3
+#define RR_ADC_STS_CHANNEL_STS 0x2
+
+#define RR_ADC_TP_REV_VERSION1 21
+#define RR_ADC_TP_REV_VERSION2 29
+#define RR_ADC_TP_REV_VERSION3 32
+
+#define RRADC_BATT_ID_DELAY_MAX 8
+
+enum rradc_channel_id {
+ RR_ADC_BATT_ID = 0,
+ RR_ADC_BATT_THERM,
+ RR_ADC_SKIN_TEMP,
+ RR_ADC_USBIN_I,
+ RR_ADC_USBIN_V,
+ RR_ADC_DCIN_I,
+ RR_ADC_DCIN_V,
+ RR_ADC_DIE_TEMP,
+ RR_ADC_CHG_TEMP,
+ RR_ADC_GPIO,
+ RR_ADC_CHG_HOT_TEMP,
+ RR_ADC_CHG_TOO_HOT_TEMP,
+ RR_ADC_SKIN_HOT_TEMP,
+ RR_ADC_SKIN_TOO_HOT_TEMP,
+ RR_ADC_CHAN_MAX
+};
+
+struct rradc_chip;
+
+/**
+ * struct rradc_channel - rradc channel data
+ * @lsb: Channel least significant byte
+ * @status: Channel status address
+ * @size: number of bytes to read
+ * @trigger_addr: Trigger address, trigger is only used on some channels
+ * @trigger_mask: Trigger mask
+ * @scale: Channel scale callback
+ */
+struct rradc_channel {
+ u8 lsb;
+ u8 status;
+ int size;
+ int trigger_addr;
+ int trigger_mask;
+ int (*scale)(struct rradc_chip *chip, u16 adc_code, int *result);
+};
+
+struct rradc_chip {
+ struct device *dev;
+ struct qcom_spmi_pmic *pmic;
+ struct mutex lock;
+ struct regmap *regmap;
+ u32 base;
+ int batt_id_delay;
+ u16 batt_id_data;
+};
+
+static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 };
+static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX];
+static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX];
+
+static int rradc_read(struct rradc_chip *chip, u16 addr, u8 *data, int len)
+{
+ int ret, retry_cnt = 0;
+ u8 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN];
+
+ if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) {
+ dev_err(chip->dev,
+ "Can't read more than %d bytes, but asked to read %d bytes.\n",
+ RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len);
+ return -EINVAL;
+ }
+
+ while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) {
+ ret = regmap_bulk_read(chip->regmap, chip->base + addr, data,
+ len);
+ if (ret < 0) {
+ dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
+ ret);
+ return ret;
+ }
+
+ ret = regmap_bulk_read(chip->regmap, chip->base + addr,
+ data_check, len);
+ if (ret < 0) {
+ dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
+ ret);
+ return ret;
+ }
+
+ if (memcmp(data, data_check, len) != 0) {
+ retry_cnt++;
+ dev_dbg(chip->dev,
+ "coherent read error, retry_cnt:%d\n",
+ retry_cnt);
+ continue;
+ }
+
+ break;
+ }
+
+ if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY)
+ dev_err(chip->dev, "Retry exceeded for coherrency check\n");
+
+ return ret;
+}
+
+static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset,
+ int64_t *slope)
+{
+ if (chip->pmic->subtype == PM660_SUBTYPE) {
+ switch (chip->pmic->fab_id) {
+ case PM660_FAB_ID_GF:
+ *offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV;
+ *slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C;
+ break;
+ case PM660_FAB_ID_TSMC:
+ *offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV;
+ *slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C;
+ break;
+ default:
+ *offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV;
+ *slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C;
+ }
+ } else if (chip->pmic->subtype == PMI8998_SUBTYPE) {
+ switch (chip->pmic->fab_id) {
+ case PMI8998_FAB_ID_GF:
+ *offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV;
+ *slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C;
+ break;
+ case PMI8998_FAB_ID_SMIC:
+ *offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV;
+ *slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C;
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * These functions explicitly cast int64_t to int.
+ * They will never overflow, as the values are small enough.
+ */
+static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code,
+ int *result_ohms)
+{
+ uint32_t current_value;
+ int64_t r_id;
+
+ current_value = chip->batt_id_data;
+ r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV);
+ r_id = div64_s64(r_id, (RR_ADC_CHAN_MAX_VALUE * current_value));
+ *result_ohms = (int)(r_id * MILLI);
+
+ return 0;
+}
+
+static int rradc_post_process_therm(struct rradc_chip *chip, u16 adc_code,
+ int *result_millidegc)
+{
+ int64_t temp;
+
+ /* K = code/4 */
+ temp = ((int64_t)adc_code * MILLI);
+ temp = div64_s64(temp, RR_ADC_BATT_THERM_LSB_K);
+ *result_millidegc = (int)milli_kelvin_to_millicelsius(temp);
+
+ return 0;
+}
+
+static int rradc_post_process_volt(struct rradc_chip *chip, u16 adc_code,
+ int *result_uv)
+{
+ int64_t uv;
+
+ /* 8x input attenuation; 2.5V ADC full scale */
+ uv = ((int64_t)adc_code * RR_ADC_VOLT_INPUT_FACTOR);
+ uv *= (RR_ADC_FS_VOLTAGE_MV * MILLI);
+ uv = div64_s64(uv, RR_ADC_CHAN_MAX_VALUE);
+ *result_uv = (int)uv;
+
+ return 0;
+}
+
+static int rradc_post_process_usbin_curr(struct rradc_chip *chip, u16 adc_code,
+ int *result_ua)
+{
+ int64_t ua;
+
+ /* scale * V/A; 2.5V ADC full scale */
+ ua = ((int64_t)adc_code * RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL);
+ ua *= (RR_ADC_FS_VOLTAGE_MV * MILLI);
+ ua = div64_s64(ua, (RR_ADC_CHAN_MAX_VALUE * 10));
+ *result_ua = (int)ua;
+
+ return 0;
+}
+
+static int rradc_post_process_dcin_curr(struct rradc_chip *chip, u16 adc_code,
+ int *result_ua)
+{
+ int64_t ua;
+
+ /* 0.5 V/A; 2.5V ADC full scale */
+ ua = ((int64_t)adc_code * RR_ADC_CURR_INPUT_FACTOR);
+ ua *= (RR_ADC_FS_VOLTAGE_MV * MILLI);
+ ua = div64_s64(ua, (RR_ADC_CHAN_MAX_VALUE * 1000));
+ *result_ua = (int)ua;
+
+ return 0;
+}
+
+static int rradc_post_process_die_temp(struct rradc_chip *chip, u16 adc_code,
+ int *result_millidegc)
+{
+ int64_t temp;
+
+ temp = ((int64_t)adc_code * RR_ADC_TEMP_FS_VOLTAGE_NUM);
+ temp = div64_s64(temp,
+ (RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MAX_VALUE));
+ temp -= RR_ADC_DIE_TEMP_OFFSET;
+ temp = div64_s64(temp, RR_ADC_DIE_TEMP_SLOPE);
+ temp += RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC;
+ *result_millidegc = (int)temp;
+
+ return 0;
+}
+
+static int rradc_post_process_chg_temp_hot(struct rradc_chip *chip,
+ u16 adc_code, int *result_millidegc)
+{
+ int64_t uv, offset, slope;
+ int ret;
+
+ ret = rradc_get_fab_coeff(chip, &offset, &slope);
+ if (ret < 0) {
+ dev_err(chip->dev, "Unable to get fab id coefficients\n");
+ return -EINVAL;
+ }
+
+ uv = (int64_t)adc_code * RR_ADC_CHG_THRESHOLD_SCALE;
+ uv = uv * RR_ADC_TEMP_FS_VOLTAGE_NUM;
+ uv = div64_s64(uv,
+ (RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MAX_VALUE));
+ uv = offset - uv;
+ uv = div64_s64((uv * MILLI), slope);
+ uv = uv + RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC;
+ *result_millidegc = (int)uv;
+
+ return 0;
+}
+
+static int rradc_post_process_skin_temp_hot(struct rradc_chip *chip,
+ u16 adc_code, int *result_millidegc)
+{
+ int64_t temp;
+
+ temp = (int64_t)adc_code;
+ temp = (div64_s64(temp, 2) - 30) * MILLI;
+ *result_millidegc = (int)temp;
+
+ return 0;
+}
+
+static int rradc_post_process_chg_temp(struct rradc_chip *chip, u16 adc_code,
+ int *result_millidegc)
+{
+ int64_t uv, offset, slope;
+ int ret;
+
+ ret = rradc_get_fab_coeff(chip, &offset, &slope);
+ if (ret < 0) {
+ dev_err(chip->dev, "Unable to get fab id coefficients\n");
+ return -EINVAL;
+ }
+
+ uv = ((int64_t)adc_code * RR_ADC_TEMP_FS_VOLTAGE_NUM);
+ uv = div64_s64(uv,
+ (RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MAX_VALUE));
+ uv = offset - uv;
+ uv = div64_s64((uv * MILLI), slope);
+ uv += RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC;
+ *result_millidegc = (int)uv;
+
+ return 0;
+}
+
+static int rradc_post_process_gpio(struct rradc_chip *chip, u16 adc_code,
+ int *result_mv)
+{
+ int64_t mv;
+
+ /* 5V ADC full scale, 10 bit */
+ mv = ((int64_t)adc_code * RR_ADC_GPIO_FS_RANGE);
+ mv = div64_s64(mv, RR_ADC_CHAN_MAX_VALUE);
+ *result_mv = (int)mv;
+
+ return 0;
+}
+
+static int rradc_enable_continuous_mode(struct rradc_chip *chip)
+{
+ int ret;
+
+ /* Clear channel log */
+ ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_ADC_LOG,
+ RR_ADC_ADC_LOG_CLR_CTRL,
+ RR_ADC_ADC_LOG_CLR_CTRL);
+ if (ret < 0) {
+ dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_ADC_LOG,
+ RR_ADC_ADC_LOG_CLR_CTRL, 0);
+ if (ret < 0) {
+ dev_err(chip->dev, "log ctrl update to not clear failed:%d\n",
+ ret);
+ return ret;
+ }
+
+ /* Switch to continuous mode */
+ ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_RR_ADC_CTL,
+ RR_ADC_ADC_CTL_CONTINUOUS_SEL,
+ RR_ADC_ADC_CTL_CONTINUOUS_SEL);
+ if (ret < 0)
+ dev_err(chip->dev, "Update to continuous mode failed:%d\n",
+ ret);
+
+ return ret;
+}
+
+static int rradc_disable_continuous_mode(struct rradc_chip *chip)
+{
+ int ret;
+
+ /* Switch to non continuous mode */
+ ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_RR_ADC_CTL,
+ RR_ADC_ADC_CTL_CONTINUOUS_SEL, 0);
+ if (ret < 0)
+ dev_err(chip->dev, "Update to non-continuous mode failed:%d\n",
+ ret);
+
+ return ret;
+}
+
+static bool rradc_is_ready(struct rradc_chip *chip,
+ enum rradc_channel_id chan_id)
+{
+ const struct rradc_channel *chan = &rradc_chans[chan_id];
+ int ret;
+ unsigned int status, mask;
+
+ /* BATT_ID STS bit does not get set initially */
+ switch (chan_id) {
+ case RR_ADC_BATT_ID:
+ mask = RR_ADC_STS_CHANNEL_STS;
+ break;
+ default:
+ mask = RR_ADC_STS_CHANNEL_READING_MASK;
+ break;
+ }
+
+ ret = regmap_read(chip->regmap, chip->base + chan->status, &status);
+ if (ret < 0 || !(status & mask))
+ return false;
+
+ return true;
+}
+
+static int rradc_read_status_in_cont_mode(struct rradc_chip *chip,
+ enum rradc_channel_id chan_id)
+{
+ const struct rradc_channel *chan = &rradc_chans[chan_id];
+ const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_id];
+ int ret;
+
+ if (chan->trigger_mask == 0) {
+ dev_err(chip->dev, "Channel doesn't have a trigger mask\n");
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr,
+ chan->trigger_mask, chan->trigger_mask);
+ if (ret < 0) {
+ dev_err(chip->dev,
+ "Failed to apply trigger for channel '%s' ret=%d\n",
+ iio_chan->datasheet_name, ret);
+ return ret;
+ }
+
+ ret = rradc_enable_continuous_mode(chip);
+ if (ret < 0) {
+ dev_err(chip->dev, "Failed to switch to continuous mode\n");
+ goto disable_trigger;
+ }
+
+ if (!rradc_is_ready(chip, chan_id))
+ dev_err(chip->dev, "channel '%s' is not ready\n",
+ iio_chan->datasheet_name);
+
+ ret = rradc_disable_continuous_mode(chip);
+ if (ret < 0)
+ dev_err(chip->dev, "Failed to switch to non continuous mode\n");
+
+disable_trigger:
+ ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr,
+ chan->trigger_mask, 0);
+ if (ret < 0)
+ dev_err(chip->dev,
+ "Failed to apply trigger for channel '%s' ret=%d\n",
+ iio_chan->datasheet_name, ret);
+
+ return ret;
+}
+
+static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip,
+ enum rradc_channel_id chan_id,
+ u16 *data)
+{
+ int ret, batt_id_delay;
+
+ ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
+ RR_ADC_BATT_ID_CTRL_CHANNEL_CONV,
+ RR_ADC_BATT_ID_CTRL_CHANNEL_CONV);
+ if (ret < 0) {
+ dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret);
+ return ret;
+ }
+
+ if (chip->batt_id_delay != -EINVAL) {
+ batt_id_delay =
+ FIELD_PREP(BATT_ID_SETTLE_MASK, chip->batt_id_delay);
+ ret = regmap_update_bits(chip->regmap,
+ chip->base + RR_ADC_BATT_ID_CFG,
+ batt_id_delay, batt_id_delay);
+ if (ret < 0) {
+ dev_err(chip->dev,
+ "BATT_ID settling time config failed:%d\n",
+ ret);
+ goto out_disable_batt_id;
+ }
+ }
+
+ ret = regmap_update_bits(chip->regmap,
+ chip->base + RR_ADC_BATT_ID_TRIGGER,
+ RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL);
+ if (ret < 0) {
+ dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret);
+ goto out_disable_batt_id;
+ }
+
+ ret = rradc_read_status_in_cont_mode(chip, chan_id);
+ if (ret < 0)
+ dev_err(chip->dev, "Error reading in continuous mode:%d\n",
+ ret);
+
+ /*
+ * Reset registers back to default values
+ */
+ ret = regmap_update_bits(chip->regmap,
+ chip->base + RR_ADC_BATT_ID_TRIGGER,
+ RR_ADC_TRIGGER_CTL, 0);
+ if (ret < 0)
+ dev_err(chip->dev, "BATT_ID trigger re-set failed:%d\n", ret);
+
+out_disable_batt_id:
+ ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
+ RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0);
+ if (ret < 0)
+ dev_err(chip->dev, "Disabling BATT ID channel failed:%d\n",
+ ret);
+
+ return ret;
+}
+
+static int rradc_do_conversion(struct rradc_chip *chip,
+ enum rradc_channel_id chan_id, u16 *data)
+{
+ const struct rradc_channel *chan = &rradc_chans[chan_id];
+ const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_id];
+ int ret;
+ u8 buf[6];
+
+ mutex_lock(&chip->lock);
+
+ switch (chan_id) {
+ case RR_ADC_BATT_ID:
+ ret = rradc_prepare_batt_id_conversion(chip, chan_id, data);
+ if (ret < 0) {
+ dev_err(chip->dev, "Battery ID conversion failed:%d\n",
+ ret);
+ goto unlock_out;
+ }
+ break;
+
+ case RR_ADC_USBIN_V:
+ case RR_ADC_DIE_TEMP:
+ ret = rradc_read_status_in_cont_mode(chip, chan_id);
+ if (ret < 0) {
+ dev_err(chip->dev,
+ "Error reading in continuous mode:%d\n", ret);
+ goto unlock_out;
+ }
+ break;
+ case RR_ADC_CHG_HOT_TEMP:
+ case RR_ADC_CHG_TOO_HOT_TEMP:
+ case RR_ADC_SKIN_HOT_TEMP:
+ case RR_ADC_SKIN_TOO_HOT_TEMP:
+ break;
+ default:
+ if (!rradc_is_ready(chip, chan_id)) {
+ /*
+ * Usually this means the channel isn't attached, for example
+ * the in_voltage_usbin_v_input channel will not be ready if
+ * no USB cable is attached
+ */
+ dev_dbg(chip->dev, "channel '%s' is not ready\n",
+ iio_chan->datasheet_name);
+ ret = -ENODATA;
+ goto unlock_out;
+ }
+ break;
+ }
+
+ ret = rradc_read(chip, chan->lsb, buf, chan->size);
+ if (ret) {
+ dev_err(chip->dev, "read data failed\n");
+ goto unlock_out;
+ }
+
+ /*
+ * For the battery ID we read the register for every ID ADC and then
+ * see which one is actually connected.
+ */
+ if (chan_id == RR_ADC_BATT_ID) {
+ u16 batt_id_150 = get_unaligned_le16(buf + 4);
+ u16 batt_id_15 = get_unaligned_le16(buf + 2);
+ u16 batt_id_5 = get_unaligned_le16(buf);
+
+ if (!batt_id_150 && !batt_id_15 && !batt_id_5) {
+ dev_err(chip->dev,
+ "Invalid batt_id values with all zeros\n");
+ ret = -EINVAL;
+ goto unlock_out;
+ }
+
+ if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) {
+ *data = batt_id_150;
+ chip->batt_id_data = 150;
+ } else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) {
+ *data = batt_id_15;
+ chip->batt_id_data = 15;
+ } else {
+ *data = batt_id_5;
+ chip->batt_id_data = 5;
+ }
+ } else {
+ /*
+ * All of the other channels are either 1 or 2 bytes.
+ * We can rely on the second byte being 0 for 1-byte channels.
+ */
+ *data = get_unaligned_le16(buf);
+ }
+
+unlock_out:
+ mutex_unlock(&chip->lock);
+
+ return ret;
+}
+
+static int rradc_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan_spec, int *val,
+ int *val2, long mask)
+{
+ struct rradc_chip *chip = iio_priv(indio_dev);
+ const struct rradc_channel *chan;
+ int ret;
+ u16 adc_code;
+
+ if (chan_spec->address >= RR_ADC_CHAN_MAX) {
+ dev_err(chip->dev, "Invalid channel index:%ld\n",
+ chan_spec->address);
+ return -EINVAL;
+ }
+
+ chan = &rradc_chans[chan_spec->address];
+ ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
+ if (ret < 0)
+ return ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ *val = adc_code;
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_PROCESSED:
+ chan->scale(chip, adc_code, val);
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct iio_info rradc_info = {
+ .read_raw = &rradc_read_raw,
+};
+
+static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = {
+ {
+ .scale = rradc_post_process_batt_id,
+ .lsb = RR_ADC_BATT_ID_5_LSB,
+ .status = RR_ADC_BATT_ID_STS,
+ .size = 6,
+ .trigger_addr = RR_ADC_BATT_ID_TRIGGER,
+ .trigger_mask = BIT(0),
+ },
+ {
+ .scale = rradc_post_process_therm,
+ .lsb = RR_ADC_BATT_THERM_LSB,
+ .status = RR_ADC_BATT_THERM_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_BATT_THERM_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_therm,
+ .lsb = RR_ADC_SKIN_TEMP_LSB,
+ .status = RR_ADC_AUX_THERM_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_AUX_THERM_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_usbin_curr,
+ .lsb = RR_ADC_USB_IN_I_LSB,
+ .status = RR_ADC_USB_IN_I_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_USB_IN_I_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_volt,
+ .lsb = RR_ADC_USB_IN_V_LSB,
+ .status = RR_ADC_USB_IN_V_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_USB_IN_V_TRIGGER,
+ .trigger_mask = BIT(7),
+ },
+ {
+ .scale = rradc_post_process_dcin_curr,
+ .lsb = RR_ADC_DC_IN_I_LSB,
+ .status = RR_ADC_DC_IN_I_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_DC_IN_I_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_volt,
+ .lsb = RR_ADC_DC_IN_V_LSB,
+ .status = RR_ADC_DC_IN_V_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_DC_IN_V_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_die_temp,
+ .lsb = RR_ADC_PMI_DIE_TEMP_LSB,
+ .status = RR_ADC_PMI_DIE_TEMP_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER,
+ .trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE,
+ },
+ {
+ .scale = rradc_post_process_chg_temp,
+ .lsb = RR_ADC_CHARGER_TEMP_LSB,
+ .status = RR_ADC_CHARGER_TEMP_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_gpio,
+ .lsb = RR_ADC_GPIO_LSB,
+ .status = RR_ADC_GPIO_STS,
+ .size = 2,
+ .trigger_addr = RR_ADC_GPIO_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_chg_temp_hot,
+ .lsb = RR_ADC_CHARGER_HOT,
+ .status = RR_ADC_CHARGER_TEMP_STS,
+ .size = 1,
+ .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_chg_temp_hot,
+ .lsb = RR_ADC_CHARGER_TOO_HOT,
+ .status = RR_ADC_CHARGER_TEMP_STS,
+ .size = 1,
+ .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_skin_temp_hot,
+ .lsb = RR_ADC_SKIN_HOT,
+ .status = RR_ADC_AUX_THERM_STS,
+ .size = 1,
+ .trigger_addr = RR_ADC_AUX_THERM_TRIGGER,
+ },
+ {
+ .scale = rradc_post_process_skin_temp_hot,
+ .lsb = RR_ADC_SKIN_TOO_HOT,
+ .status = RR_ADC_AUX_THERM_STS,
+ .size = 1,
+ .trigger_addr = RR_ADC_AUX_THERM_TRIGGER,
+ },
+};
+
+static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = {
+ {
+ .datasheet_name = "batt_id",
+ .type = IIO_RESISTANCE,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = RR_ADC_BATT_ID,
+ },
+ {
+ .datasheet_name = "batt_therm",
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_BATT_THERM,
+ },
+ {
+ .datasheet_name = "skin_temp",
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED)|
+ BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_SKIN_TEMP,
+ },
+ {
+ .datasheet_name = "usbin_i",
+ .type = IIO_CURRENT,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = RR_ADC_USBIN_I,
+ },
+ {
+ .datasheet_name = "usbin_v",
+ .type = IIO_VOLTAGE,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = RR_ADC_USBIN_V,
+ },
+ {
+ .datasheet_name = "dcin_i",
+ .type = IIO_CURRENT,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = RR_ADC_DCIN_I,
+ },
+ {
+ .datasheet_name = "dcin_v",
+ .type = IIO_VOLTAGE,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = RR_ADC_DCIN_V,
+ },
+ {
+ .datasheet_name = "die_temp",
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED)|
+ BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_DIE_TEMP,
+ },
+ {
+ .datasheet_name = "chg_temp",
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED)|
+ BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_CHG_TEMP,
+ },
+ {
+ .datasheet_name = "gpio",
+ .type = IIO_VOLTAGE,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED)|
+ BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_GPIO,
+ },
+ {
+ .datasheet_name = "chg_temp_hot",
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED)|
+ BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_CHG_HOT_TEMP,
+ },
+ {
+ .datasheet_name = "chg_temp_too_hot",
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED)|
+ BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_CHG_TOO_HOT_TEMP,
+ },
+ {
+ .datasheet_name = "skin_temp_hot",
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED)|
+ BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_SKIN_TEMP,
+ },
+ {
+ .datasheet_name = "skin_temp_too_hot",
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED)|
+ BIT(IIO_CHAN_INFO_RAW),
+ .address = RR_ADC_SKIN_TEMP,
+ },
+};
+
+static int rradc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iio_dev *indio_dev;
+ struct rradc_chip *chip;
+ int ret, i;
+
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ chip = iio_priv(indio_dev);
+ chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!chip->regmap) {
+ dev_err(dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
+ }
+
+ chip->dev = dev;
+ mutex_init(&chip->lock);
+
+ ret = device_property_read_u32(dev, "reg", &chip->base);
+ if (ret < 0) {
+ dev_err(chip->dev, "Couldn't find reg address, ret = %d\n",
+ ret);
+ return ret;
+ }
+
+ chip->batt_id_delay = -EINVAL;
+ ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms",
+ &chip->batt_id_delay);
+ if (!ret) {
+ for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) {
+ if (chip->batt_id_delay == batt_id_delays[i])
+ break;
+ }
+ if (i == RRADC_BATT_ID_DELAY_MAX)
+ chip->batt_id_delay = -EINVAL;
+ }
+
+ /* Get the PMIC revision ID, we need to handle some varying coefficients */
+ chip->pmic = (struct qcom_spmi_pmic *)spmi_device_get_drvdata(
+ to_spmi_device(pdev->dev.parent));
+ qcom_pmic_print_info(chip->dev, chip->pmic);
+
+ indio_dev->name = pdev->name;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &rradc_info;
+ indio_dev->channels = rradc_iio_chans;
+ indio_dev->num_channels = RR_ADC_CHAN_MAX;
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static const struct of_device_id rradc_match_table[] = {
+ { .compatible = "qcom,pm660-rradc" },
+ { .compatible = "qcom,pmi8998-rradc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, rradc_match_table);
+
+static struct platform_driver rradc_driver = {
+ .driver = {
+ .name = "qcom-rradc",
+ .of_match_table = rradc_match_table,
+ },
+ .probe = rradc_probe,
+};
+module_platform_driver(rradc_driver);
+
+MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver");
+MODULE_AUTHOR("Caleb Connolly <caleb.connolly@linaro.org>");
+MODULE_LICENSE("GPL v2");
--
2.34.1
^ permalink raw reply related
* [PATCH v2 7/7] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable RRADC
From: Caleb Connolly @ 2022-01-05 18:33 UTC (permalink / raw)
To: caleb.connolly, Jonathan Cameron, Lars-Peter Clausen, Rob Herring,
Andy Gross, Bjorn Andersson, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-msm
Cc: sumit.semwal, amit.pundir, john.stultz
In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org>
Enable the PMI8998 RRADC.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
index 580d4cc1296f..481132b0cee4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
@@ -312,6 +312,10 @@ resin {
};
};
+&pmi8998_rradc {
+ status = "okay";
+};
+
/* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */
&q6afedai {
qi2s@22 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 6/7] arm64: dts: qcom: sdm845-db845c: enable rradc
From: Caleb Connolly @ 2022-01-05 18:33 UTC (permalink / raw)
To: caleb.connolly, Jonathan Cameron, Lars-Peter Clausen, Rob Herring,
Andy Gross, Bjorn Andersson, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-msm
Cc: sumit.semwal, amit.pundir, john.stultz
In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org>
Enable the Round Robin ADC for the db845c.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 13f80a0b6faa..1c452b458121 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -595,6 +595,10 @@ resin {
};
};
+&pmi8998_rradc {
+ status = "okay";
+};
+
/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */
&q6afedai {
qi2s@22 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 5/7] arm64: dts: qcom: sdm845-oneplus: enable rradc
From: Caleb Connolly @ 2022-01-05 18:33 UTC (permalink / raw)
To: caleb.connolly, Jonathan Cameron, Lars-Peter Clausen, Rob Herring,
Andy Gross, Bjorn Andersson, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-msm
Cc: sumit.semwal, amit.pundir, john.stultz
In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org>
Enable the RRADC for the OnePlus 6.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
index 3e04aeb479d1..9feda49b2f12 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
@@ -450,6 +450,10 @@ pinconf {
};
};
+&pmi8998_rradc {
+ status = "okay";
+};
+
&qupv3_id_1 {
status = "okay";
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 4/7] arm64: dts: qcom: pmi8998: add rradc node
From: Caleb Connolly @ 2022-01-05 18:33 UTC (permalink / raw)
To: caleb.connolly, Jonathan Cameron, Lars-Peter Clausen, Rob Herring,
Andy Gross, Bjorn Andersson, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-msm
Cc: sumit.semwal, amit.pundir, john.stultz
In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org>
Add a DT node for the Round Robin ADC found in the PMI8998 PMIC.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
arch/arm64/boot/dts/qcom/pmi8998.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
index 0fef5f113f05..da10668c361d 100644
--- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
@@ -18,6 +18,14 @@ pmi8998_gpio: gpios@c000 {
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ pmi8998_rradc: rradc@4500 {
+ compatible = "qcom,pmi8998-rradc";
+ reg = <0x4500>;
+ #io-channel-cells = <1>;
+
+ status = "disabled";
+ };
};
pmi8998_lsid1: pmic@3 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/7] dt-bindings: iio: adc: document qcom-spmi-rradc
From: Caleb Connolly @ 2022-01-05 18:33 UTC (permalink / raw)
To: caleb.connolly, Jonathan Cameron, Lars-Peter Clausen, Rob Herring,
Andy Gross, Bjorn Andersson, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-msm
Cc: sumit.semwal, amit.pundir, john.stultz, Rob Herring
In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org>
Add dt-binding docs for the Qualcomm SPMI RRADC found in PMICs like
PMI8998 and PMI8994
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/iio/adc/qcom,spmi-rradc.yaml | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
new file mode 100644
index 000000000000..11d47c46a48d
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-rradc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's SPMI PMIC Round Robin ADC
+
+maintainers:
+ - Caleb Connolly <caleb.connolly@linaro.org>
+
+description: |
+ The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to read the
+ voltage, current and temperature for supported peripherals such as the battery thermistor
+ die temperature, charger temperature, USB and DC input voltage / current and battery ID
+ resistor.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pmi8998-rradc
+ - qcom,pm660-rradc
+
+ reg:
+ description: rradc base address and length in the SPMI PMIC register map
+ maxItems: 1
+
+ qcom,batt-id-delay-ms:
+ description:
+ Sets the hardware settling time for the battery ID resistor.
+ enum: [0, 1, 4, 12, 20, 40, 60, 80]
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic_rradc: adc@4500 {
+ compatible = "qcom,pmi8998-rradc";
+ reg = <0x4500>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/7] mfd: qcom-spmi-pmic: expose the PMIC revid information to clients
From: Caleb Connolly @ 2022-01-05 18:33 UTC (permalink / raw)
To: caleb.connolly, Jonathan Cameron, Lars-Peter Clausen, Rob Herring,
Andy Gross, Bjorn Andersson, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-msm
Cc: sumit.semwal, amit.pundir, john.stultz
In-Reply-To: <20220105183353.2505744-1-caleb.connolly@linaro.org>
Some PMIC functions such as the RRADC need to be aware of the PMIC
chip revision information to implement errata or otherwise adjust
behaviour, export the PMIC information to enable this.
This is specifically required to enable the RRADC to adjust
coefficients based on which chip fab the PMIC was produced in,
this can vary per unique device and therefore has to be read at
runtime.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
drivers/mfd/qcom-spmi-pmic.c | 108 +++++++++++++++++------------------
include/soc/qcom/qcom-pmic.h | 63 ++++++++++++++++++++
2 files changed, 114 insertions(+), 57 deletions(-)
create mode 100644 include/soc/qcom/qcom-pmic.h
diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c
index 1cacc00aa6c9..6b75c2f52b74 100644
--- a/drivers/mfd/qcom-spmi-pmic.c
+++ b/drivers/mfd/qcom-spmi-pmic.c
@@ -3,51 +3,24 @@
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
+#include <linux/device.h>
+#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/slab.h>
#include <linux/spmi.h>
#include <linux/regmap.h>
#include <linux/of_platform.h>
+#include <soc/qcom/qcom-pmic.h>
#define PMIC_REV2 0x101
#define PMIC_REV3 0x102
#define PMIC_REV4 0x103
#define PMIC_TYPE 0x104
#define PMIC_SUBTYPE 0x105
-
+#define PMIC_FAB_ID 0x1f2
#define PMIC_TYPE_VALUE 0x51
-#define COMMON_SUBTYPE 0x00
-#define PM8941_SUBTYPE 0x01
-#define PM8841_SUBTYPE 0x02
-#define PM8019_SUBTYPE 0x03
-#define PM8226_SUBTYPE 0x04
-#define PM8110_SUBTYPE 0x05
-#define PMA8084_SUBTYPE 0x06
-#define PMI8962_SUBTYPE 0x07
-#define PMD9635_SUBTYPE 0x08
-#define PM8994_SUBTYPE 0x09
-#define PMI8994_SUBTYPE 0x0a
-#define PM8916_SUBTYPE 0x0b
-#define PM8004_SUBTYPE 0x0c
-#define PM8909_SUBTYPE 0x0d
-#define PM8028_SUBTYPE 0x0e
-#define PM8901_SUBTYPE 0x0f
-#define PM8950_SUBTYPE 0x10
-#define PMI8950_SUBTYPE 0x11
-#define PM8998_SUBTYPE 0x14
-#define PMI8998_SUBTYPE 0x15
-#define PM8005_SUBTYPE 0x18
-#define PM660L_SUBTYPE 0x1A
-#define PM660_SUBTYPE 0x1B
-#define PM8150_SUBTYPE 0x1E
-#define PM8150L_SUBTYPE 0x1f
-#define PM8150B_SUBTYPE 0x20
-#define PMK8002_SUBTYPE 0x21
-#define PM8009_SUBTYPE 0x24
-#define PM8150C_SUBTYPE 0x26
-#define SMB2351_SUBTYPE 0x29
-
static const struct of_device_id pmic_spmi_id_table[] = {
{ .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
{ .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
@@ -81,42 +54,47 @@ static const struct of_device_id pmic_spmi_id_table[] = {
{ }
};
-static void pmic_spmi_show_revid(struct regmap *map, struct device *dev)
+static int pmic_spmi_load_revid(struct regmap *map, struct device *dev,
+ struct qcom_spmi_pmic *pmic)
{
- unsigned int rev2, minor, major, type, subtype;
- const char *name = "unknown";
int ret, i;
- ret = regmap_read(map, PMIC_TYPE, &type);
+ ret = regmap_read(map, PMIC_TYPE, &pmic->type);
if (ret < 0)
- return;
+ return ret;
- if (type != PMIC_TYPE_VALUE)
- return;
+ if (pmic->type != PMIC_TYPE_VALUE)
+ return ret;
- ret = regmap_read(map, PMIC_SUBTYPE, &subtype);
+ ret = regmap_read(map, PMIC_SUBTYPE, &pmic->subtype);
if (ret < 0)
- return;
+ return ret;
for (i = 0; i < ARRAY_SIZE(pmic_spmi_id_table); i++) {
- if (subtype == (unsigned long)pmic_spmi_id_table[i].data)
+ if (pmic->subtype == (unsigned long)pmic_spmi_id_table[i].data)
break;
}
if (i != ARRAY_SIZE(pmic_spmi_id_table))
- name = pmic_spmi_id_table[i].compatible;
+ pmic->name = devm_kstrdup_const(dev, pmic_spmi_id_table[i].compatible, GFP_KERNEL);
- ret = regmap_read(map, PMIC_REV2, &rev2);
+ ret = regmap_read(map, PMIC_REV2, &pmic->rev2);
if (ret < 0)
- return;
+ return ret;
- ret = regmap_read(map, PMIC_REV3, &minor);
+ ret = regmap_read(map, PMIC_REV3, &pmic->minor);
if (ret < 0)
- return;
+ return ret;
- ret = regmap_read(map, PMIC_REV4, &major);
+ ret = regmap_read(map, PMIC_REV4, &pmic->major);
if (ret < 0)
- return;
+ return ret;
+
+ if (pmic->subtype == PMI8998_SUBTYPE || pmic->subtype == PM660_SUBTYPE) {
+ ret = regmap_read(map, PMIC_FAB_ID, &pmic->fab_id);
+ if (ret < 0)
+ return ret;
+ }
/*
* In early versions of PM8941 and PM8226, the major revision number
@@ -124,14 +102,14 @@ static void pmic_spmi_show_revid(struct regmap *map, struct device *dev)
* Increment the major revision number here if the chip is an early
* version of PM8941 or PM8226.
*/
- if ((subtype == PM8941_SUBTYPE || subtype == PM8226_SUBTYPE) &&
- major < 0x02)
- major++;
+ if ((pmic->subtype == PM8941_SUBTYPE || pmic->subtype == PM8226_SUBTYPE) &&
+ pmic->major < 0x02)
+ pmic->major++;
- if (subtype == PM8110_SUBTYPE)
- minor = rev2;
+ if (pmic->subtype == PM8110_SUBTYPE)
+ pmic->minor = pmic->rev2;
- dev_dbg(dev, "%x: %s v%d.%d\n", subtype, name, major, minor);
+ return 0;
}
static const struct regmap_config spmi_regmap_config = {
@@ -144,22 +122,38 @@ static const struct regmap_config spmi_regmap_config = {
static int pmic_spmi_probe(struct spmi_device *sdev)
{
struct regmap *regmap;
+ struct qcom_spmi_pmic *pmic;
regmap = devm_regmap_init_spmi_ext(sdev, &spmi_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
+ pmic = devm_kzalloc(&sdev->dev, sizeof(*pmic), GFP_KERNEL);
+ if (!pmic)
+ return -ENOMEM;
+
/* Only the first slave id for a PMIC contains this information */
- if (sdev->usid % 2 == 0)
- pmic_spmi_show_revid(regmap, &sdev->dev);
+ if (sdev->usid % 2 == 0) {
+ pmic_spmi_load_revid(regmap, &sdev->dev, pmic);
+ spmi_device_set_drvdata(sdev, pmic);
+ qcom_pmic_print_info(&sdev->dev, pmic);
+ }
return devm_of_platform_populate(&sdev->dev);
}
+static void pmic_spmi_remove(struct spmi_device *sdev)
+{
+ struct qcom_spmi_pmic *pmic = spmi_device_get_drvdata(sdev);
+
+ kfree(pmic->name);
+}
+
MODULE_DEVICE_TABLE(of, pmic_spmi_id_table);
static struct spmi_driver pmic_spmi_driver = {
.probe = pmic_spmi_probe,
+ .remove = pmic_spmi_remove,
.driver = {
.name = "pmic-spmi",
.of_match_table = pmic_spmi_id_table,
diff --git a/include/soc/qcom/qcom-pmic.h b/include/soc/qcom/qcom-pmic.h
new file mode 100644
index 000000000000..59114988582d
--- /dev/null
+++ b/include/soc/qcom/qcom-pmic.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2021 Linaro. All rights reserved.
+ * Copyright (c) 2021 Caleb Connolly <caleb.connolly@linaro.org>
+ */
+
+#ifndef __QCOM_PMIC_H__
+#define __QCOM_PMIC_H__
+
+#define COMMON_SUBTYPE 0x00
+#define PM8941_SUBTYPE 0x01
+#define PM8841_SUBTYPE 0x02
+#define PM8019_SUBTYPE 0x03
+#define PM8226_SUBTYPE 0x04
+#define PM8110_SUBTYPE 0x05
+#define PMA8084_SUBTYPE 0x06
+#define PMI8962_SUBTYPE 0x07
+#define PMD9635_SUBTYPE 0x08
+#define PM8994_SUBTYPE 0x09
+#define PMI8994_SUBTYPE 0x0a
+#define PM8916_SUBTYPE 0x0b
+#define PM8004_SUBTYPE 0x0c
+#define PM8909_SUBTYPE 0x0d
+#define PM8028_SUBTYPE 0x0e
+#define PM8901_SUBTYPE 0x0f
+#define PM8950_SUBTYPE 0x10
+#define PMI8950_SUBTYPE 0x11
+#define PM8998_SUBTYPE 0x14
+#define PMI8998_SUBTYPE 0x15
+#define PM8005_SUBTYPE 0x18
+#define PM660L_SUBTYPE 0x1A
+#define PM660_SUBTYPE 0x1B
+#define PM8150_SUBTYPE 0x1E
+#define PM8150L_SUBTYPE 0x1f
+#define PM8150B_SUBTYPE 0x20
+#define PMK8002_SUBTYPE 0x21
+#define PM8009_SUBTYPE 0x24
+#define PM8150C_SUBTYPE 0x26
+#define SMB2351_SUBTYPE 0x29
+
+#define PMI8998_FAB_ID_SMIC 0x11
+#define PMI8998_FAB_ID_GF 0x30
+
+#define PM660_FAB_ID_GF 0x0
+#define PM660_FAB_ID_TSMC 0x2
+#define PM660_FAB_ID_MX 0x3
+
+struct qcom_spmi_pmic {
+ unsigned int type;
+ unsigned int subtype;
+ unsigned int major;
+ unsigned int minor;
+ unsigned int rev2;
+ unsigned int fab_id;
+ const char *name;
+};
+
+static inline void qcom_pmic_print_info(struct device *dev, struct qcom_spmi_pmic *pmic)
+{
+ dev_info(dev, "%x: %s v%d.%d\n",
+ pmic->subtype, pmic->name, pmic->major, pmic->minor);
+}
+
+#endif /* __QCOM_PMIC_H__ */
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/7] iio: adc: introduce Qualcomm SPMI Round Robin ADC
From: Caleb Connolly @ 2022-01-05 18:33 UTC (permalink / raw)
To: caleb.connolly, Jonathan Cameron, Lars-Peter Clausen, Rob Herring,
Andy Gross, Bjorn Andersson, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-msm
Cc: sumit.semwal, amit.pundir, john.stultz
The RRADC is responsible for reading data about the current and
voltage from the USB or DC in jacks, it can also read the battery
ID (resistence) and some temperatures. It is found on the PMI8998 and
PM660 Qualcomm PMICs.
The RRADC has to calibrate some ADC values based on which chip fab
the PMIC was produced in, to facilitate this the patch
("mfd: qcom-spmi-pmic: expose the PMIC revid information to clients")
exposes the PMIC revision information as a struct and registers it
as driver data in the Qualcomm SPMI PMIC driver so that it can be
read by the RRADC.
Changes since v1:
* Rework the RRADC driver based on Jonathan's feedback
* Pick up Rob's reviewed by for the dt-binding patch.
Caleb Connolly (7):
mfd: qcom-spmi-pmic: expose the PMIC revid information to clients
dt-bindings: iio: adc: document qcom-spmi-rradc
iio: adc: qcom-spmi-rradc: introduce round robin adc
arm64: dts: qcom: pmi8998: add rradc node
arm64: dts: qcom: sdm845-oneplus: enable rradc
arm64: dts: qcom: sdm845-db845c: enable rradc
arm64: dts: qcom: sdm845-xiaomi-beryllium: enable RRADC
.../bindings/iio/adc/qcom,spmi-rradc.yaml | 54 +
arch/arm64/boot/dts/qcom/pmi8998.dtsi | 8 +
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 +
.../boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 +
.../boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 4 +
drivers/iio/adc/Kconfig | 13 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/qcom-spmi-rradc.c | 1070 +++++++++++++++++
drivers/mfd/qcom-spmi-pmic.c | 108 +-
include/soc/qcom/qcom-pmic.h | 63 +
10 files changed, 1272 insertions(+), 57 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
create mode 100644 drivers/iio/adc/qcom-spmi-rradc.c
create mode 100644 include/soc/qcom/qcom-pmic.h
--
2.34.1
^ permalink raw reply
* Re: [bug] GNOME loses all settings following failure to resume from suspend
From: Hugo Mills @ 2022-01-05 18:34 UTC (permalink / raw)
To: Filipe Manana; +Cc: Chris Murphy, Btrfs BTRFS, Josef Bacik
In-Reply-To: <YdXdtrHb9nTYgFo7@debian9.Home>
Hi, Filipe,
On Wed, Jan 05, 2022 at 06:04:38PM +0000, Filipe Manana wrote:
> I don't think I have a wiki account enabled, but I'll see if I get that
> updated soon.
If you can't (or don't want to), feel free to put the text you want
to replace it with here, and I'll update the wiki for you...
Hugo.
--
Hugo Mills | "There's a Martian war machine outside -- they want
hugo@... carfax.org.uk | to talk to you about a cure for the common cold."
http://carfax.org.uk/ |
PGP: E2AB1DE4 | Stephen Franklin, Babylon 5
^ permalink raw reply
* [PATCH V3 1/1] nvme: Add verbose error logging
From: Alan Adamson @ 2022-01-05 18:32 UTC (permalink / raw)
To: linux-nvme; +Cc: alan.adamson, kbusch, hch, sagi
In-Reply-To: <20220105183249.22088-1-alan.adamson@oracle.com>
Improves logging of NVMe errors. If NVME_VERBOSE_ERRORS is configured,
a verbose description of the error is logged, otherwise only status codes/bits
is logged.
Verbose logging example:
nvme0n1: Read @ LBA 2304, 1 blocks, Unrecovered Read Error (sct 0x2 / sc 0x81) DNR
Non-verbose logging example:
nvme0n1: Read @ LBA 2304, 1 blocks, NVME Error (sct 0x2 / sc 0x81) DNR
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Alan Adamson <alan.adamson@oracle.com>
Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com>
---
drivers/nvme/host/Kconfig | 8 ++
drivers/nvme/host/Makefile | 2 +-
drivers/nvme/host/core.c | 3 +
drivers/nvme/host/errors.c | 181 +++++++++++++++++++++++++++++++++++++
drivers/nvme/host/nvme.h | 2 +
include/linux/nvme.h | 1 +
6 files changed, 196 insertions(+), 1 deletion(-)
create mode 100644 drivers/nvme/host/errors.c
diff --git a/drivers/nvme/host/Kconfig b/drivers/nvme/host/Kconfig
index dc0450ca23a3..d6d056963c06 100644
--- a/drivers/nvme/host/Kconfig
+++ b/drivers/nvme/host/Kconfig
@@ -24,6 +24,14 @@ config NVME_MULTIPATH
/dev/nvmeXnY device will show up for each NVMe namespace,
even if it is accessible through multiple controllers.
+config NVME_VERBOSE_ERRORS
+ bool "NVMe verbose error reporting"
+ depends on NVME_CORE
+ help
+ This option enables verbose reporting for NVMe errors. The
+ error translation table will grow the kernel image size by
+ about 4 KB.
+
config NVME_HWMON
bool "NVMe hardware monitoring"
depends on (NVME_CORE=y && HWMON=y) || (NVME_CORE=m && HWMON)
diff --git a/drivers/nvme/host/Makefile b/drivers/nvme/host/Makefile
index dfaacd472e5d..ea3d702feb51 100644
--- a/drivers/nvme/host/Makefile
+++ b/drivers/nvme/host/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_NVME_RDMA) += nvme-rdma.o
obj-$(CONFIG_NVME_FC) += nvme-fc.o
obj-$(CONFIG_NVME_TCP) += nvme-tcp.o
-nvme-core-y := core.o ioctl.o
+nvme-core-y := core.o ioctl.o errors.o
nvme-core-$(CONFIG_TRACING) += trace.o
nvme-core-$(CONFIG_NVME_MULTIPATH) += multipath.o
nvme-core-$(CONFIG_BLK_DEV_ZONED) += zns.o
diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 1af8a4513708..fda029a55436 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -354,6 +354,9 @@ void nvme_complete_rq(struct request *req)
switch (nvme_decide_disposition(req)) {
case COMPLETE:
+ if (unlikely(nvme_req(req)->status != NVME_SC_SUCCESS))
+ nvme_error_log(req);
+
nvme_end_req(req);
return;
case RETRY:
diff --git a/drivers/nvme/host/errors.c b/drivers/nvme/host/errors.c
new file mode 100644
index 000000000000..2668d2f584e2
--- /dev/null
+++ b/drivers/nvme/host/errors.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * NVM Express device driver verbose errors
+ * Copyright (c) 2021, Oracle and/or its affiliates
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/blkdev.h>
+#include "nvme.h"
+
+struct nvme_string_table {
+ unsigned int code;
+ const unsigned char *string;
+};
+
+static const struct nvme_string_table nvme_ops[] = {
+ { REQ_OP_READ, "Read" },
+ { REQ_OP_WRITE, "Write" },
+ { REQ_OP_FLUSH, "Flush" },
+ { REQ_OP_DISCARD, "Deallocate (DSM)" },
+ { REQ_OP_WRITE_ZEROES, "Write Zeroes" },
+ { REQ_OP_ZONE_RESET_ALL, "Zone Reset All" },
+ { REQ_OP_ZONE_RESET, "Zone Reset" },
+ { REQ_OP_ZONE_OPEN, "Zone Open" },
+ { REQ_OP_ZONE_CLOSE, "Zone Close" },
+ { REQ_OP_ZONE_FINISH, "Zone Finish" },
+ { REQ_OP_ZONE_APPEND, "Zone Append" },
+};
+#define NVME_OPS_SIZE ARRAY_SIZE(nvme_ops)
+
+#ifdef CONFIG_NVME_VERBOSE_ERRORS
+static const char * const nvme_errors[] = {
+ [NVME_SC_SUCCESS] = "Success",
+ [NVME_SC_INVALID_OPCODE] = "Invalid Command Opcode",
+ [NVME_SC_INVALID_FIELD] = "Invalid Field in Command",
+ [NVME_SC_CMDID_CONFLICT] = "Command ID Conflict",
+ [NVME_SC_DATA_XFER_ERROR] = "Data Transfer Error",
+ [NVME_SC_POWER_LOSS] = "Commands Aborted due to Power Loss Notification",
+ [NVME_SC_INTERNAL] = "Internal Error",
+ [NVME_SC_ABORT_REQ] = "Command Abort Requested",
+ [NVME_SC_ABORT_QUEUE] = "Command Aborted due to SQ Deletion",
+ [NVME_SC_FUSED_FAIL] = "Command Aborted due to Failed Fused Command",
+ [NVME_SC_FUSED_MISSING] = "Command Aborted due to Missing Fused Command",
+ [NVME_SC_INVALID_NS] = "Invalid Namespace or Format",
+ [NVME_SC_CMD_SEQ_ERROR] = "Command Sequence Error",
+ [NVME_SC_SGL_INVALID_LAST] = "Invalid SGL Segment Descriptor",
+ [NVME_SC_SGL_INVALID_COUNT] = "Invalid Number of SGL Descriptors",
+ [NVME_SC_SGL_INVALID_DATA] = "Data SGL Length Invalid",
+ [NVME_SC_SGL_INVALID_METADATA] = "Metadata SGL Length Invalid",
+ [NVME_SC_SGL_INVALID_TYPE] = "SGL Descriptor Type Invalid",
+ [NVME_SC_CMB_INVALID_USE] = "Invalid Use of Controller Memory Buffer",
+ [NVME_SC_PRP_INVALID_OFFSET] = "PRP Offset Invalid",
+ [NVME_SC_ATOMIC_WU_EXCEEDED] = "Atomic Write Unit Exceeded",
+ [NVME_SC_OP_DENIED] = "Operation Denied",
+ [NVME_SC_SGL_INVALID_OFFSET] = "SGL Offset Invalid",
+ [NVME_SC_RESERVED] = "Reserved",
+ [NVME_SC_HOST_ID_INCONSIST] = "Host Identifier Inconsistent Format",
+ [NVME_SC_KA_TIMEOUT_EXPIRED] = "Keep Alive Timeout Expired",
+ [NVME_SC_KA_TIMEOUT_INVALID] = "Keep Alive Timeout Invalid",
+ [NVME_SC_ABORTED_PREEMPT_ABORT] = "Command Aborted due to Preempt and Abort",
+ [NVME_SC_SANITIZE_FAILED] = "Sanitize Failed",
+ [NVME_SC_SANITIZE_IN_PROGRESS] = "Sanitize In Progress",
+ [NVME_SC_SGL_INVALID_GRANULARITY] = "SGL Data Block Granularity Invalid",
+ [NVME_SC_CMD_NOT_SUP_CMB_QUEUE] = "Command Not Supported for Queue in CMB",
+ [NVME_SC_NS_WRITE_PROTECTED] = "Namespace is Write Protected",
+ [NVME_SC_CMD_INTERRUPTED] = "Command Interrupted",
+ [NVME_SC_TRANSIENT_TR_ERR] = "Transient Transport Error",
+ [NVME_SC_INVALID_IO_CMD_SET] = "Invalid IO Command Set",
+ [NVME_SC_LBA_RANGE] = "LBA Out of Range",
+ [NVME_SC_CAP_EXCEEDED] = "Capacity Exceeded",
+ [NVME_SC_NS_NOT_READY] = "Namespace Not Ready",
+ [NVME_SC_RESERVATION_CONFLICT] = "Reservation Conflict",
+ [NVME_SC_FORMAT_IN_PROGRESS] = "Format In Progress",
+ [NVME_SC_CQ_INVALID] = "Completion Queue Invalid",
+ [NVME_SC_QID_INVALID] = "Invalid Queue Identifier",
+ [NVME_SC_QUEUE_SIZE] = "Invalid Queue Size",
+ [NVME_SC_ABORT_LIMIT] = "Abort Command Limit Exceeded",
+ [NVME_SC_ABORT_MISSING] = "Reserved", /* XXX */
+ [NVME_SC_ASYNC_LIMIT] = "Asynchronous Event Request Limit Exceeded",
+ [NVME_SC_FIRMWARE_SLOT] = "Invalid Firmware Slot",
+ [NVME_SC_FIRMWARE_IMAGE] = "Invalid Firmware Image",
+ [NVME_SC_INVALID_VECTOR] = "Invalid Interrupt Vector",
+ [NVME_SC_INVALID_LOG_PAGE] = "Invalid Log Page",
+ [NVME_SC_INVALID_FORMAT] = "Invalid Format",
+ [NVME_SC_FW_NEEDS_CONV_RESET] = "Firmware Activation Requires Conventional Reset",
+ [NVME_SC_INVALID_QUEUE] = "Invalid Queue Deletion",
+ [NVME_SC_FEATURE_NOT_SAVEABLE] = "Feature Identifier Not Saveable",
+ [NVME_SC_FEATURE_NOT_CHANGEABLE] = "Feature Not Changeable",
+ [NVME_SC_FEATURE_NOT_PER_NS] = "Feature Not Namespace Specific",
+ [NVME_SC_FW_NEEDS_SUBSYS_RESET] = "Firmware Activation Requires NVM Subsystem Reset",
+ [NVME_SC_FW_NEEDS_RESET] = "Firmware Activation Requires Reset",
+ [NVME_SC_FW_NEEDS_MAX_TIME] = "Firmware Activation Requires Maximum Time Violation",
+ [NVME_SC_FW_ACTIVATE_PROHIBITED] = "Firmware Activation Prohibited",
+ [NVME_SC_OVERLAPPING_RANGE] = "Overlapping Range",
+ [NVME_SC_NS_INSUFFICIENT_CAP] = "Namespace Insufficient Capacity",
+ [NVME_SC_NS_ID_UNAVAILABLE] = "Namespace Identifier Unavailable",
+ [NVME_SC_NS_ALREADY_ATTACHED] = "Namespace Already Attached",
+ [NVME_SC_NS_IS_PRIVATE] = "Namespace Is Private",
+ [NVME_SC_NS_NOT_ATTACHED] = "Namespace Not Attached",
+ [NVME_SC_THIN_PROV_NOT_SUPP] = "Thin Provisioning Not Supported",
+ [NVME_SC_CTRL_LIST_INVALID] = "Controller List Invalid",
+ [NVME_SC_SELT_TEST_IN_PROGRESS] = "Device Self-test In Progress",
+ [NVME_SC_BP_WRITE_PROHIBITED] = "Boot Partition Write Prohibited",
+ [NVME_SC_CTRL_ID_INVALID] = "Invalid Controller Identifier",
+ [NVME_SC_SEC_CTRL_STATE_INVALID] = "Invalid Secondary Controller State",
+ [NVME_SC_CTRL_RES_NUM_INVALID] = "Invalid Number of Controller Resources",
+ [NVME_SC_RES_ID_INVALID] = "Invalid Resource Identifier",
+ [NVME_SC_PMR_SAN_PROHIBITED] = "Sanitize Prohibited",
+ [NVME_SC_ANA_GROUP_ID_INVALID] = "ANA Group Identifier Invalid",
+ [NVME_SC_ANA_ATTACH_FAILED] = "ANA Attach Failed",
+ [NVME_SC_BAD_ATTRIBUTES] = "Conflicting Attributes",
+ [NVME_SC_INVALID_PI] = "Invalid Protection Information",
+ [NVME_SC_READ_ONLY] = "Attempted Write to Read Only Range",
+ [NVME_SC_ONCS_NOT_SUPPORTED] = "ONCS Not Supported",
+ [NVME_SC_ZONE_BOUNDARY_ERROR] = "Zoned Boundary Error",
+ [NVME_SC_ZONE_FULL] = "Zone Is Full",
+ [NVME_SC_ZONE_READ_ONLY] = "Zone Is Read Only",
+ [NVME_SC_ZONE_OFFLINE] = "Zone Is Offline",
+ [NVME_SC_ZONE_INVALID_WRITE] = "Zone Invalid Write",
+ [NVME_SC_ZONE_TOO_MANY_ACTIVE] = "Too Many Active Zones",
+ [NVME_SC_ZONE_TOO_MANY_OPEN] = "Too Many Open Zones",
+ [NVME_SC_ZONE_INVALID_TRANSITION] = "Invalid Zone State Transition",
+ [NVME_SC_WRITE_FAULT] = "Write Fault",
+ [NVME_SC_READ_ERROR] = "Unrecovered Read Error",
+ [NVME_SC_GUARD_CHECK] = "End-to-end Guard Check Error",
+ [NVME_SC_APPTAG_CHECK] = "End-to-end Application Tag Check Error",
+ [NVME_SC_REFTAG_CHECK] = "End-to-end Reference Tag Check Error",
+ [NVME_SC_COMPARE_FAILED] = "Compare Failure",
+ [NVME_SC_ACCESS_DENIED] = "Access Denied",
+ [NVME_SC_UNWRITTEN_BLOCK] = "Deallocated or Unwritten Logical Block",
+ [NVME_SC_ANA_PERSISTENT_LOSS] = "Asymmetric Access Persistent Loss",
+ [NVME_SC_ANA_INACCESSIBLE] = "Asymmetric Access Inaccessible",
+ [NVME_SC_ANA_TRANSITION] = "Asymmetric Access Transition",
+ [NVME_SC_HOST_PATH_ERROR] = "Host Pathing Error",
+};
+#define NVME_ERRORS_SIZE ARRAY_SIZE(nvme_errors)
+#endif /* CONFIG_NVME_VERBOSE_ERRORS */
+
+void nvme_error_log(struct request *req)
+{
+ struct nvme_ns *ns = req->q->queuedata;
+ struct nvme_request *nr = nvme_req(req);
+ const struct nvme_string_table *entry;
+ const unsigned char *op_str = "Unknown";
+ const unsigned char *err_str = NULL;
+ unsigned int i;
+
+ if (!ns)
+ return;
+
+ for (i = 0, entry = nvme_ops ; i < NVME_OPS_SIZE ; i++)
+ if (entry[i].code == (req->cmd_flags & REQ_OP_MASK))
+ op_str = entry[i].string;
+
+#ifdef CONFIG_NVME_VERBOSE_ERRORS
+ if ((nr->status & 0x7ff) <= NVME_ERRORS_SIZE)
+ err_str = nvme_errors[nr->status & 0x7ff];
+#endif
+ if (err_str == NULL)
+ err_str = "NVME Error";
+
+ pr_err_ratelimited("%s: %s @ LBA %llu, %llu blocks, %s (sct 0x%x / sc 0x%x) %s%s\n",
+ req->rq_disk ? req->rq_disk->disk_name : "?",
+ op_str,
+ (unsigned long long)nvme_sect_to_lba(ns, blk_rq_pos(req)),
+ (unsigned long long)blk_rq_bytes(req) >> ns->lba_shift,
+ err_str,
+ nr->status >> 8 & 7, /* Status Code Type */
+ nr->status & 0xff, /* Status Code */
+ nr->status & NVME_SC_MORE ? "MORE " : "",
+ nr->status & NVME_SC_DNR ? "DNR " : "");
+}
+EXPORT_SYMBOL_GPL(nvme_error_log);
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 9b095ee01364..7edd67b92a6b 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -922,4 +922,6 @@ static inline bool nvme_multi_css(struct nvme_ctrl *ctrl)
return (ctrl->ctrl_config & NVME_CC_CSS_MASK) == NVME_CC_CSS_CSI;
}
+extern void nvme_error_log(struct request *req);
+
#endif /* _NVME_H */
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 855dd9b3e84b..1f946e5bf7c1 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -1636,6 +1636,7 @@ enum {
NVME_SC_HOST_ABORTED_CMD = 0x371,
NVME_SC_CRD = 0x1800,
+ NVME_SC_MORE = 0x2000,
NVME_SC_DNR = 0x4000,
};
--
2.27.0
^ permalink raw reply related
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