* [PATCH 2/3-V1] AM35xx: Add AM35xx intr_clr & sw_rst cntrl reg bit defination
@ 2010-01-11 6:06 hvaibhav
2010-02-05 1:03 ` [APPLIED] [PATCH 2/3-V1] AM35xx: Add AM35xx intr_clr & sw_rst cntrl reg bit Tony Lindgren
0 siblings, 1 reply; 2+ messages in thread
From: hvaibhav @ 2010-01-11 6:06 UTC (permalink / raw)
To: linux-omap; +Cc: tony, khilman, Vaibhav Hiremath
From: Vaibhav Hiremath <hvaibhav@ti.com>
AM3517/05 has few additional control module registers to control
the new IP's, like VPFE, USBOTG, CPGMAC.
This patch adds the bit defination for INTR_CLR and SW_RST control
register.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
arch/arm/plat-omap/include/plat/control.h | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 61e7b8a..efdf9e6 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -274,6 +274,23 @@
#define AM35XX_CPGMAC_FCLK_SHIFT 9
#define AM35XX_VPFE_FCLK_SHIFT 10
+/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
+#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
+#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
+#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
+#define AM35XX_USBOTGSS_INT_CLR BIT(4)
+#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
+#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
+#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
+
+/*AM35XX CONTROL_IP_SW_RESET bits*/
+#define AM35XX_USBOTGSS_SW_RST BIT(0)
+#define AM35XX_CPGMACSS_SW_RST BIT(1)
+#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
+#define AM35XX_HECC_SW_RST BIT(3)
+#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
+
/*
* CONTROL OMAP STATUS register to identify OMAP3 features
*/
--
1.6.2.4
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2010-01-11 6:06 [PATCH 2/3-V1] AM35xx: Add AM35xx intr_clr & sw_rst cntrl reg bit defination hvaibhav
2010-02-05 1:03 ` [APPLIED] [PATCH 2/3-V1] AM35xx: Add AM35xx intr_clr & sw_rst cntrl reg bit Tony Lindgren
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