* [ovmf baseline-only test] 38420: all pass
@ 2015-12-03 4:50 Platform Team regression test user
0 siblings, 0 replies; only message in thread
From: Platform Team regression test user @ 2015-12-03 4:50 UTC (permalink / raw)
To: xen-devel, osstest-admin
This run is configured for baseline tests only.
flight 38420 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/38420/
Perfect :-)
All tests in this flight passed
version targeted for testing:
ovmf c972495ed0a939ed30f5ab5fa14f215b8bbe5ed1
baseline version:
ovmf 911f3dede219d2bb220954768f5e853e0dd976c1
Last test of basis 38417 2015-12-02 05:24:56 Z 0 days
Testing same since 38420 2015-12-02 22:32:27 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Eugene Cohen <eugene@hp.com>
Jeff Fan <jeff.fan@intel.com>
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images
Logs, config files, etc. are available at
http://osstest.xs.citrite.net/~osstest/testlogs/logs
Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary
Push not applicable.
------------------------------------------------------------
commit c972495ed0a939ed30f5ab5fa14f215b8bbe5ed1
Author: Jeff Fan <jeff.fan@intel.com>
Date: Wed Dec 2 00:44:05 2015 +0000
UefiCpuPkg/CpuMpPei: Fix typo and add some comments
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19090 6f19259b-4bc3-4df7-8a09-765794883524
commit f40a7de45070dfa193e47ed0031cc07c275287b3
Author: Jeff Fan <jeff.fan@intel.com>
Date: Wed Dec 2 00:43:45 2015 +0000
UefiCpuPkg/CpuMpPei: Save/Restore CRx/DRx register for APs waking up
PeiStartupAllAPs()/PeiStartupThisAP() will send INIT-SIPI-SIPI to wakeup APs to
execute AP function. However, some registers will be reset after APs received
INIT IPI. We need to restore some registers (For example, CRx/DRx) manually
after APs wakeup.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19089 6f19259b-4bc3-4df7-8a09-765794883524
commit 22cfe73a12ce0dc272d790999dcb5c3d94bc1fc6
Author: Jeff Fan <jeff.fan@intel.com>
Date: Wed Dec 2 00:43:19 2015 +0000
UefiCpuPkg/CpuMpPei: Sync BSP's CRx to APs when initialization
Save BSP's volatile register and sync CRx register to APs when AP 1st wake up.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19088 6f19259b-4bc3-4df7-8a09-765794883524
commit 10c6c206dabc945c77b563d3f489586b21dae184
Author: Jeff Fan <jeff.fan@intel.com>
Date: Wed Dec 2 00:42:59 2015 +0000
UefiCpuPkg/CpuMpPei: Set AP state to CpuStateIdle after initialization
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19087 6f19259b-4bc3-4df7-8a09-765794883524
commit ef1fdb809886ddfeb9e4107919b14414a2fea020
Author: Jeff Fan <jeff.fan@intel.com>
Date: Wed Dec 2 00:42:40 2015 +0000
UefiCpuPkg/CpuMpPei: Add CPU_VOLATILE_REGISTERS & worker functions
Add CPU_VOLATILE_REGISTERS definitions for CRx and DRx required to be restored
after APs received INIT IPI.
Add worker functions SaveVolatileRegisters()/RestoreVolatileRegisters() used to
save/restore CRx and DRx. It also check if Debugging Extensions supported or
not.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19086 6f19259b-4bc3-4df7-8a09-765794883524
commit 24930b5609f7de283b7b8ec16c0de3d54aa211de
Author: Jeff Fan <jeff.fan@intel.com>
Date: Wed Dec 2 00:42:09 2015 +0000
UefiCpuPkg/CpuMpPei: Exchange whole CPU data in SortApicId()
Current implementation only exchanges the APIC ID and BIST, this updating is to
exchange all CPU data.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19085 6f19259b-4bc3-4df7-8a09-765794883524
commit ce6aec3ea31270d40ceb64739c5558bee8a09b01
Author: Eugene Cohen <eugene@hp.com>
Date: Tue Dec 1 18:39:29 2015 +0000
ArmPkg: Convert whole-cache InvalidateInstructionCache to just ASSERT
In SVN 18756 ("disallow whole D-cache maintenance operations")
InvalidateInstructionCache was modified to remove the full data cache
clean but left the full instruction cache invalidate. The change was
made to address issues in the set/way clean methodology but the
resulting code could lead someone to a painful debug. If a component
called this function, the proper code would not be flushed to the PoU,
since the intent of this function is not only to invalidate the I-cache
but to provide coherency after code loading / modification. This change
simply places an ASSERT(FALSE) in this function to avoid this hazard.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19084 6f19259b-4bc3-4df7-8a09-765794883524
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2015-12-03 4:50 [ovmf baseline-only test] 38420: all pass Platform Team regression test user
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