From: sashiko-bot@kernel.org
To: "Hangxiang Ma" <hangxiang.ma@oss.qualcomm.com>
Cc: neil.armstrong@linaro.org, linux-phy@lists.infradead.org,
robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org,
vkoul@kernel.org, olteanv@gmail.com, media-ci@linuxtv.org
Subject: Re: [PATCH v19 08/12] media: qcom: camss: vfe: Add support for VFE 1080
Date: Thu, 08 Oct 2026 07:33:30 +0000 [thread overview]
Message-ID: <sashiko-outbox-163769@kernel.org> (raw)
In-Reply-To: <20261008-kaanapali-camss-v19-8-b2c583ef50e0@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] media: camss: Hardware constraint violation on AUP_UPDATE count
- [High] media: camss: Hardcoded VFE-to-CSID mapping breaks dynamic media routing
- [High] media: camss: Data race on csid->aup_update and csid->rup_update
--
commit f4a9516b2392f133fd18f4aed515b9cb62df16ca
Author: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
media: qcom: camss: vfe: Add support for VFE 1080
Add support for the VFE (Video Front End) 1080 found on Kaanapali SoC.
In the Kaanapali camera subsystem, the front-end blocks are referred to
as TFEs.
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
> new file mode 100644
> index 0000000000000..016857cd10251
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
[ ... ]
> +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
> +{
> + int port_id = line_id;
> +
> + camss_reg_update(vfe->camss, vfe->id, port_id, false);
[Severity: High]
Does hardcoding vfe->id introduce a regression for dynamic media routing?
The Media Controller framework allows dynamic routing, where any CSID source
could be linked to any VFE sink (e.g., CSID[0] to VFE[2]).
Here, camss_reg_update() is called with vfe->id, which indexes the CSID array
directly:
camss.c:camss_reg_update() {
csid = &camss->csid[hw_id];
csid->res->hw_ops->reg_update(csid, port_id, is_clear);
}
If CSID[0] is routed to VFE[2], the VFE buffer queue will update the
registers of CSID[2] instead of the active CSID[0], leaving the active
CSID without its AUP_UPDATE and stalling the stream.
[Severity: High]
Can this introduce a data race regression on the CSID shadow states?
When userspace queues new buffers via vfe_queue_buffer_v2(), it executes from
process context and eventually calls this vfe_reg_update(). This ends up in
__csid_aup_update() which performs an unprotected read-modify-write:
camss-csid-1080.c:__csid_aup_update() {
csid->aup_update |= CSID_RUP_AUP_RDI(port_id);
}
At the same time, the CSID hardware interrupt handler csid_isr() processes
completions and performs a similar unprotected read-modify-write:
camss-csid-1080.c:__csid_aup_rup_clear() {
csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id);
}
Since these modifications can interleave without locks, one CPU's state
update could be lost, potentially corrupting the CSID_AUP_CMD register state.
> +}
[ ... ]
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index 2680a9914765f..3acef6ba97dc9 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
[ ... ]
> @@ -552,7 +554,9 @@ int vfe_enable_output_v2(struct vfe_line *line)
> output->gen2.active_num++;
> ops->vfe_wm_update(vfe, output->wm_idx[0],
> output->buf[i]->addr[0], line);
> - ops->reg_update(vfe, line->id);
> +
> + if (!vfe->res->reg_update_after_csid_config)
> + ops->reg_update(vfe, line->id);
> }
[Severity: High]
Does this introduce a regression by violating the AUP_UPDATE hardware
constraint?
The commit message states that "the number of AUP_UPDATE requests must match
the number of buffers queued to the write master while it is being enabled."
However, if userspace only queued 1 buffer, the loop in vfe_enable_output_v2()
will break early (as it loops up to CAMSS_INIT_BUF_COUNT):
for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++) {
output->buf[i] = vfe_buf_get_pending(output);
if (!output->buf[i])
break;
This means the VFE write master gets configured with only 1 buffer.
Meanwhile, csid_configure_stream() in camss-csid-1080.c unconditionally issues
CAMSS_INIT_BUF_COUNT updates:
for (k = 0; k < CAMSS_INIT_BUF_COUNT; k++)
__csid_aup_update(csid, i);
If the CSID sends 2 AUP_UPDATE commands but the VFE is only configured with
1 buffer, can this cause the hardware to perform out-of-bounds DMA or
trigger an IOMMU fault?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261008-kaanapali-camss-v19-0-b2c583ef50e0@oss.qualcomm.com?part=8
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Hangxiang Ma" <hangxiang.ma@oss.qualcomm.com>
Cc: neil.armstrong@linaro.org, linux-phy@lists.infradead.org,
robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org,
vkoul@kernel.org, olteanv@gmail.com, media-ci@linuxtv.org
Subject: Re: [PATCH v19 08/12] media: qcom: camss: vfe: Add support for VFE 1080
Date: Thu, 08 Oct 2026 07:33:30 +0000 [thread overview]
Message-ID: <sashiko-outbox-163769@kernel.org> (raw)
In-Reply-To: <20261008-kaanapali-camss-v19-8-b2c583ef50e0@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] media: camss: Hardware constraint violation on AUP_UPDATE count
- [High] media: camss: Hardcoded VFE-to-CSID mapping breaks dynamic media routing
- [High] media: camss: Data race on csid->aup_update and csid->rup_update
--
commit f4a9516b2392f133fd18f4aed515b9cb62df16ca
Author: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
media: qcom: camss: vfe: Add support for VFE 1080
Add support for the VFE (Video Front End) 1080 found on Kaanapali SoC.
In the Kaanapali camera subsystem, the front-end blocks are referred to
as TFEs.
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
> new file mode 100644
> index 0000000000000..016857cd10251
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
[ ... ]
> +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
> +{
> + int port_id = line_id;
> +
> + camss_reg_update(vfe->camss, vfe->id, port_id, false);
[Severity: High]
Does hardcoding vfe->id introduce a regression for dynamic media routing?
The Media Controller framework allows dynamic routing, where any CSID source
could be linked to any VFE sink (e.g., CSID[0] to VFE[2]).
Here, camss_reg_update() is called with vfe->id, which indexes the CSID array
directly:
camss.c:camss_reg_update() {
csid = &camss->csid[hw_id];
csid->res->hw_ops->reg_update(csid, port_id, is_clear);
}
If CSID[0] is routed to VFE[2], the VFE buffer queue will update the
registers of CSID[2] instead of the active CSID[0], leaving the active
CSID without its AUP_UPDATE and stalling the stream.
[Severity: High]
Can this introduce a data race regression on the CSID shadow states?
When userspace queues new buffers via vfe_queue_buffer_v2(), it executes from
process context and eventually calls this vfe_reg_update(). This ends up in
__csid_aup_update() which performs an unprotected read-modify-write:
camss-csid-1080.c:__csid_aup_update() {
csid->aup_update |= CSID_RUP_AUP_RDI(port_id);
}
At the same time, the CSID hardware interrupt handler csid_isr() processes
completions and performs a similar unprotected read-modify-write:
camss-csid-1080.c:__csid_aup_rup_clear() {
csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id);
}
Since these modifications can interleave without locks, one CPU's state
update could be lost, potentially corrupting the CSID_AUP_CMD register state.
> +}
[ ... ]
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index 2680a9914765f..3acef6ba97dc9 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
[ ... ]
> @@ -552,7 +554,9 @@ int vfe_enable_output_v2(struct vfe_line *line)
> output->gen2.active_num++;
> ops->vfe_wm_update(vfe, output->wm_idx[0],
> output->buf[i]->addr[0], line);
> - ops->reg_update(vfe, line->id);
> +
> + if (!vfe->res->reg_update_after_csid_config)
> + ops->reg_update(vfe, line->id);
> }
[Severity: High]
Does this introduce a regression by violating the AUP_UPDATE hardware
constraint?
The commit message states that "the number of AUP_UPDATE requests must match
the number of buffers queued to the write master while it is being enabled."
However, if userspace only queued 1 buffer, the loop in vfe_enable_output_v2()
will break early (as it loops up to CAMSS_INIT_BUF_COUNT):
for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++) {
output->buf[i] = vfe_buf_get_pending(output);
if (!output->buf[i])
break;
This means the VFE write master gets configured with only 1 buffer.
Meanwhile, csid_configure_stream() in camss-csid-1080.c unconditionally issues
CAMSS_INIT_BUF_COUNT updates:
for (k = 0; k < CAMSS_INIT_BUF_COUNT; k++)
__csid_aup_update(csid, i);
If the CSID sends 2 AUP_UPDATE commands but the VFE is only configured with
1 buffer, can this cause the hardware to perform out-of-bounds DMA or
trigger an IOMMU fault?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261008-kaanapali-camss-v19-0-b2c583ef50e0@oss.qualcomm.com?part=8
next prev parent reply other threads:[~2026-10-08 7:33 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-08 7:14 [PATCH v19 00/12] media: qcom: camss: Add Kaanapali support Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:14 ` [PATCH v19 01/12] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Kaanapali CSI2 PHY Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:14 ` [PATCH v19 02/12] phy: qcom-mipi-csi2: Parametrise the common status register offset Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 22:08 ` bod
2026-10-08 22:08 ` bod
2026-10-08 7:14 ` [PATCH v19 03/12] phy: qcom-mipi-csi2: Add Kaanapali support Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 22:32 ` bod
2026-10-08 22:32 ` bod
2026-10-08 7:14 ` [PATCH v19 04/12] media: dt-bindings: Add CAMSS device for Kaanapali Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:14 ` [PATCH v19 05/12] media: qcom: camss: Add Kaanapali compatible Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:29 ` sashiko-bot
2026-10-08 7:29 ` sashiko-bot
2026-10-08 7:14 ` [PATCH v19 06/12] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:30 ` sashiko-bot
2026-10-08 7:30 ` sashiko-bot
2026-10-08 22:38 ` bod
2026-10-08 22:38 ` bod
2026-10-08 7:14 ` [PATCH v19 07/12] media: qcom: camss: csid: Add support for CSID 1080 Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:32 ` sashiko-bot
2026-10-08 7:32 ` sashiko-bot
2026-10-08 7:14 ` [PATCH v19 08/12] media: qcom: camss: vfe: Add support for VFE 1080 Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:33 ` sashiko-bot [this message]
2026-10-08 7:33 ` sashiko-bot
2026-10-08 22:50 ` bod
2026-10-08 22:50 ` bod
2026-10-09 2:59 ` Hangxiang Ma
2026-10-09 2:59 ` Hangxiang Ma
2026-10-09 8:39 ` Bryan O'Donoghue
2026-10-09 8:39 ` Bryan O'Donoghue
2026-10-09 11:36 ` Hangxiang Ma
2026-10-09 11:36 ` Hangxiang Ma
2026-10-08 7:14 ` [PATCH v19 09/12] media: qcom: camss: tpg: Add support for v2.4.0 TPG Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:27 ` sashiko-bot
2026-10-08 7:27 ` sashiko-bot
2026-10-08 7:14 ` [PATCH v19 10/12] arm64: dts: qcom: kaanapali: Add CAMSS and CSIPHY block definitions Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 7:38 ` sashiko-bot
2026-10-08 7:38 ` sashiko-bot
2026-10-09 8:40 ` Bryan O'Donoghue
2026-10-09 8:40 ` Bryan O'Donoghue
2026-10-09 8:45 ` hangxiang.ma
2026-10-09 8:45 ` hangxiang.ma
2026-10-08 7:14 ` [PATCH v19 11/12] arm64: dts: qcom: kaanapali: Add CCI controller nodes Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
2026-10-08 16:16 ` Loic Poulain
2026-10-08 16:16 ` Loic Poulain
2026-10-09 4:06 ` Hangxiang Ma
2026-10-09 4:06 ` Hangxiang Ma
2026-10-08 7:14 ` [PATCH v19 12/12] arm64: dts: qcom: kaanapali: Add camera MCLK pinctrl Hangxiang Ma
2026-10-08 7:14 ` Hangxiang Ma
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