[PATCH 0/2] arm64: Add support for Apple M3 and M4 CPUs in KVM

[PATCH 0/2] arm64: Add support for Apple M3 and M4 CPUs in KVM

[Michael Reeves via B4 Relay]

Hi,

This series enables KVM support on Apple Silicon M3 series and base M4
CPUs.

The first patch adds the part numbers and MIDR definitions for M3
(base, Pro and Max) and base M4 CPU cores.

The second patch adds these CPUs to the existing Apple CPU workarounds
list, which is required for KVM to function correctly.

This series was developed from testing on:
- Apple M3 and M3 Pro by Michael Reeves
- Apple M3 Max by Myria Sarvay and Yureka Lilian
- Apple M4 by Yureka Lilian

---
Michael Reeves (1):
      arm64: Apply existing Apple CPU workarounds to M3 and M4

Myria Sarvay (1):
      arm64: Add Apple M3 and M4 CPU part numbers

 arch/arm64/include/asm/cputype.h | 16 ++++++++++++++++
 arch/arm64/kernel/cpu_errata.c   |  8 ++++++++
 2 files changed, 24 insertions(+)
---
base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a
change-id: 20261008-apple-m3-m4-kvm-b7b9b2e34bcd

Best regards,
--  
Michael Reeves <michael.reeves077@gmail.com>

[PATCH 0/2] arm64: Add support for Apple M3 and M4 CPUs in KVM

[Michael Reeves]

Hi,

This series enables KVM support on Apple Silicon M3 series and base M4
CPUs.

The first patch adds the part numbers and MIDR definitions for M3
(base, Pro and Max) and base M4 CPU cores.

The second patch adds these CPUs to the existing Apple CPU workarounds
list, which is required for KVM to function correctly.

This series was developed from testing on:
- Apple M3 and M3 Pro by Michael Reeves
- Apple M3 Max by Myria Sarvay and Yureka Lilian
- Apple M4 by Yureka Lilian

---
Michael Reeves (1):
      arm64: Apply existing Apple CPU workarounds to M3 and M4

Myria Sarvay (1):
      arm64: Add Apple M3 and M4 CPU part numbers

 arch/arm64/include/asm/cputype.h | 16 ++++++++++++++++
 arch/arm64/kernel/cpu_errata.c   |  8 ++++++++
 2 files changed, 24 insertions(+)
---
base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a
change-id: 20261008-apple-m3-m4-kvm-b7b9b2e34bcd

Best regards,
--  
Michael Reeves <michael.reeves077@gmail.com>

[PATCH 1/2] arm64: Add Apple M3 and M4 CPU part numbers

[Michael Reeves via B4 Relay]

From: Myria Sarvay <myrialsarvay@gmail.com>

Add CPU part numbers and MIDR definitions for M3, M3 Pro, M3 Max and
base M4 so CPU workarounds can identify these cores.

Separate M4 core codenames are not known, so use the SoC codename with
ECORE and PCORE suffixes.

Signed-off-by: Myria Sarvay <myrialsarvay@gmail.com>
Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
---
 arch/arm64/include/asm/cputype.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 1fa29616e..ca44c354c 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -155,6 +155,14 @@
 #define APPLE_CPU_PART_M2_AVALANCHE_PRO	0x035
 #define APPLE_CPU_PART_M2_BLIZZARD_MAX	0x038
 #define APPLE_CPU_PART_M2_AVALANCHE_MAX	0x039
+#define APPLE_CPU_PART_M3_SAWTOOTH	0x042
+#define APPLE_CPU_PART_M3_EVEREST	0x043
+#define APPLE_CPU_PART_M3_SAWTOOTH_PRO	0x044
+#define APPLE_CPU_PART_M3_EVEREST_PRO	0x045
+#define APPLE_CPU_PART_M3_SAWTOOTH_MAX	0x048
+#define APPLE_CPU_PART_M3_EVEREST_MAX	0x049
+#define APPLE_CPU_PART_M4_DONAN_ECORE	0x052
+#define APPLE_CPU_PART_M4_DONAN_PCORE	0x053
 
 #define AMPERE_CPU_PART_AMPERE1		0xAC3
 #define AMPERE_CPU_PART_AMPERE1A	0xAC4
@@ -250,6 +258,14 @@
 #define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
 #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
 #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
+#define MIDR_APPLE_M3_SAWTOOTH MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH)
+#define MIDR_APPLE_M3_EVEREST MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST)
+#define MIDR_APPLE_M3_SAWTOOTH_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH_PRO)
+#define MIDR_APPLE_M3_EVEREST_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST_PRO)
+#define MIDR_APPLE_M3_SAWTOOTH_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH_MAX)
+#define MIDR_APPLE_M3_EVEREST_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST_MAX)
+#define MIDR_APPLE_M4_DONAN_ECORE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M4_DONAN_ECORE)
+#define MIDR_APPLE_M4_DONAN_PCORE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M4_DONAN_PCORE)
 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
 #define MIDR_AMPERE1A MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1A)
 #define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)

-- 
2.56.0

[PATCH 1/2] arm64: Add Apple M3 and M4 CPU part numbers

[Michael Reeves]

From: Myria Sarvay <myrialsarvay@gmail.com>

Add CPU part numbers and MIDR definitions for M3, M3 Pro, M3 Max and
base M4 so CPU workarounds can identify these cores.

Separate M4 core codenames are not known, so use the SoC codename with
ECORE and PCORE suffixes.

Signed-off-by: Myria Sarvay <myrialsarvay@gmail.com>
Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
---
 arch/arm64/include/asm/cputype.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 1fa29616e..ca44c354c 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -155,6 +155,14 @@
 #define APPLE_CPU_PART_M2_AVALANCHE_PRO	0x035
 #define APPLE_CPU_PART_M2_BLIZZARD_MAX	0x038
 #define APPLE_CPU_PART_M2_AVALANCHE_MAX	0x039
+#define APPLE_CPU_PART_M3_SAWTOOTH	0x042
+#define APPLE_CPU_PART_M3_EVEREST	0x043
+#define APPLE_CPU_PART_M3_SAWTOOTH_PRO	0x044
+#define APPLE_CPU_PART_M3_EVEREST_PRO	0x045
+#define APPLE_CPU_PART_M3_SAWTOOTH_MAX	0x048
+#define APPLE_CPU_PART_M3_EVEREST_MAX	0x049
+#define APPLE_CPU_PART_M4_DONAN_ECORE	0x052
+#define APPLE_CPU_PART_M4_DONAN_PCORE	0x053
 
 #define AMPERE_CPU_PART_AMPERE1		0xAC3
 #define AMPERE_CPU_PART_AMPERE1A	0xAC4
@@ -250,6 +258,14 @@
 #define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
 #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
 #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
+#define MIDR_APPLE_M3_SAWTOOTH MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH)
+#define MIDR_APPLE_M3_EVEREST MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST)
+#define MIDR_APPLE_M3_SAWTOOTH_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH_PRO)
+#define MIDR_APPLE_M3_EVEREST_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST_PRO)
+#define MIDR_APPLE_M3_SAWTOOTH_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_SAWTOOTH_MAX)
+#define MIDR_APPLE_M3_EVEREST_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M3_EVEREST_MAX)
+#define MIDR_APPLE_M4_DONAN_ECORE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M4_DONAN_ECORE)
+#define MIDR_APPLE_M4_DONAN_PCORE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M4_DONAN_PCORE)
 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
 #define MIDR_AMPERE1A MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1A)
 #define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)

-- 
2.56.0

[PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Michael Reeves via B4 Relay]

From: Michael Reeves <michael.reeves077@gmail.com>

Add M3, M3 Pro, M3 Max and base M4 to apple_cpus so they receive the
existing PMU trap and broken SEIS workarounds needed by KVM.

Co-developed-by: Yureka Lilian <yureka@cyberchaos.dev>
Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
Tested-by: Yureka Lilian <yureka@cyberchaos.dev>
Tested-by: Myria Sarvay <myrialsarvay@gmail.com>
Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
---
 arch/arm64/kernel/cpu_errata.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index e0c094025..8a7703b86 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -288,6 +288,14 @@ static const struct midr_range apple_cpus[] = {
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_PRO),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_PRO),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_ECORE),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_PCORE),
 	{},
 };
 

-- 
2.56.0

[PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Michael Reeves]

Add M3, M3 Pro, M3 Max and base M4 to apple_cpus so they receive the
existing PMU trap and broken SEIS workarounds needed by KVM.

Co-developed-by: Yureka Lilian <yureka@cyberchaos.dev>
Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
Tested-by: Yureka Lilian <yureka@cyberchaos.dev>
Tested-by: Myria Sarvay <myrialsarvay@gmail.com>
Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
---
 arch/arm64/kernel/cpu_errata.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index e0c094025..8a7703b86 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -288,6 +288,14 @@ static const struct midr_range apple_cpus[] = {
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_PRO),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_PRO),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_MAX),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_ECORE),
+	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_PCORE),
 	{},
 };
 

-- 
2.56.0

Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] arm64: missing M3 and M4 from has_vgic_v3 KVM capability array
--

commit adcc2ca70d0cb38584f5c01ccf8a91f249b43c44
Author: Michael Reeves <michael.reeves077@gmail.com>

arm64: Apply existing Apple CPU workarounds to M3 and M4

Add M3, M3 Pro, M3 Max and base M4 to apple_cpus so they receive the
existing PMU trap and broken SEIS workarounds needed by KVM.

> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index e0c09402540ce..8a7703b86f3ef 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -288,6 +288,14 @@ static const struct midr_range apple_cpus[] = {
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
>  	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_PRO),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_PRO),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_SAWTOOTH_MAX),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M3_EVEREST_MAX),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_ECORE),
> +	MIDR_ALL_VERSIONS(MIDR_APPLE_M4_DONAN_PCORE),
>  	{},
>  };

[Severity: High]
Does this commit also need to update the has_vgic_v3 array in
can_trap_icv_dir_el1() in arch/arm64/kernel/cpufeature.c with these M3 and M4
MIDRs?

Because Apple SoCs use AIC instead of a standard physical GIC, they lack the
ARM64_HAS_GICV3_CPUIF CPU capability. To use the hardware vGIC's TDIR (Trap
DIR) feature on Apple Silicon, KVM relies on the has_vgic_v3 array in
can_trap_icv_dir_el1().

Since M3 and M4 are omitted from has_vgic_v3, can_trap_icv_dir_el1() returns
false on M3 and M4, clearing the ARM64_HAS_ICH_HCR_EL2_TDIR capability.

When this capability is missing, KVM's fallback path in
kvm_compute_ich_hcr_trap_bits() forces common_trap = true (setting the
ICH_HCR_EL2.TC bit). This traps all guest GICv3 system register accesses to
EL2 for software emulation, causing a catastrophic performance degradation
for interrupt-heavy virtualization workloads.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261008-apple-m3-m4-kvm-v1-0-7bb4cbf3d63b@gmail.com?part=2

Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Marc Zyngier]

Hi Michael,

On Thu, 08 Oct 2026 13:15:41 +0100,
Michael Reeves via B4 Relay <devnull+michael.reeves077.gmail.com@kernel.org> wrote:
> 
> From: Michael Reeves <michael.reeves077@gmail.com>
> 
> Add M3, M3 Pro, M3 Max and base M4 to apple_cpus so they receive the
> existing PMU trap and broken SEIS workarounds needed by KVM.
>

How have you established that these CPUs suffer from the same SEIS
erratum? I'm all for working around bugs, but I'd like to make sure
the new fancy stuff is indeed just as broken as the old shit...

For the record, the EDKII build in the QEMU EFI package that was in
part of Debian Bullseye was able to trigger the bug semi reliably
(series of writes to ICC_EOIR1_EL1 for interrupts that were never
active). This happens on handover to the guest kernel.

I can provide the binary (and a few scripts) to test this easily.

Should they have been fixed, we can always create a second
implementation list to cover the PMU.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Michael Reeves]

Hi Marc,

> How have you established that these CPUs suffer from the same SEIS
> erratum? I'm all for working around bugs, but I'd like to make sure
> the new fancy stuff is indeed just as broken as the old shit...

We tested both the PMU and SEIS fixes together (as in 7.3, both fixes were
combined into just the one apple_cpu list). It's probably a good idea to test
them in isolation, thanks.

> For the record, the EDKII build in the QEMU EFI package that was in
> part of Debian Bullseye was able to trigger the bug semi reliably
> (series of writes to ICC_EOIR1_EL1 for interrupts that were never
> active). This happens on handover to the guest kernel.
>
> I can provide the binary (and a few scripts) to test this easily.
> Should they have been fixed, we can always create a second
> implementation list to cover the PMU.

Can you please send that so we can try? That would be much
appreciated, thank you.

Thanks,
Michael

Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Marc Zyngier]

On Fri, 09 Oct 2026 01:03:57 +0100,
Michael Reeves <michael.reeves077@gmail.com> wrote:
> 
> > I can provide the binary (and a few scripts) to test this easily.
> > Should they have been fixed, we can always create a second
> > implementation list to cover the PMU.
> 
> Can you please send that so we can try? That would be much
> appreciated, thank you.

I've sent you (and Yureka) details over IRC. If you need help with
setting things up, let me know directly.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Myria Sarvay]

Hi Marc,

(Resending because I forgot to reply all, sorry Marc)

On Fri, Oct 09, 2026 at 09:16:03AM +0100, Marc Zyngier wrote:
> On Fri, 09 Oct 2026 01:03:57 +0100,
> Michael Reeves <michael.reeves077@gmail.com> wrote:
> > 
> > > I can provide the binary (and a few scripts) to test this easily.
> > > Should they have been fixed, we can always create a second
> > > implementation list to cover the PMU.
> > 
> > Can you please send that so we can try? That would be much
> > appreciated, thank you.
> 
> I've sent you (and Yureka) details over IRC. If you need help with
> setting things up, let me know directly.
> 
> Thanks,
> 
> 	M.
> 
> -- 
> Without deviation from the norm, progress is not possible.

I've tested the patches on my M3 Max (t6031-j514c), and without these
patches, it SErrors, and with them (and including the M3/M4 MIDRs in
the has_vgic_v3 list in arch/arm64/kernel/cpufeature.c) it doesn't
SError, and the iso boots correctly to a login getty.

Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Marc Zyngier]

On Sat, 10 Oct 2026 11:54:16 +0100,
Myria Sarvay <myrialsarvay@gmail.com> wrote:
> 
> Hi Marc,
> 
> (Resending because I forgot to reply all, sorry Marc)
> 
> On Fri, Oct 09, 2026 at 09:16:03AM +0100, Marc Zyngier wrote:
> > On Fri, 09 Oct 2026 01:03:57 +0100,
> > Michael Reeves <michael.reeves077@gmail.com> wrote:
> > > 
> > > > I can provide the binary (and a few scripts) to test this easily.
> > > > Should they have been fixed, we can always create a second
> > > > implementation list to cover the PMU.
> > > 
> > > Can you please send that so we can try? That would be much
> > > appreciated, thank you.
> > 
> > I've sent you (and Yureka) details over IRC. If you need help with
> > setting things up, let me know directly.
> > 
> > Thanks,
> > 
> > 	M.
> > 
> > -- 
> > Without deviation from the norm, progress is not possible.
> 
> I've tested the patches on my M3 Max (t6031-j514c), and without these
> patches, it SErrors, and with them (and including the M3/M4 MIDRs in
> the has_vgic_v3 list in arch/arm64/kernel/cpufeature.c) it doesn't
> SError, and the iso boots correctly to a login getty.

Thanks for letting me know.

When you post v2 to fix the has_vgic_v3 list, please collect the
details of what this was tested on in the cover letter, it may become
useful in the future.

Cheers,

	M.

-- 
Without deviation from the norm, progress is not possible.