Re: [PATCH v2 37/56] drm/i915/hdmi: Add FRL port clock valid

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/hdmi: FRL mode_valid rejects valid modes by checking max_rate instead of required rate
--

commit a29948ea9df1fcfe40f2c9e5a0c8d6354286b145
Author: Vandita Kulkarni <vandita.kulkarni@intel.com>

drm/i915/hdmi: Add FRL port clock valid

Introduce hdmi_port_frl_clock_valid() which validates the FRL link
rate against the maximum FRL rate and the source PHY (c10/c20 or LT).

Call this from the FRL mode_valid path.

Since PHY PLL table units are in 10 kbps, add a macro to convert FRL
rate per lane in Gbps to 10 kbps.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b82c636b46f93..8e742165a50ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -2046,6 +2061,7 @@ intel_hdmi_frl_mode_clock_valid(struct intel_connector *connector,
>  	struct intel_hdmi_frl_dfm frl_dfm = {};
>  	int max_rate = hdmi->max_frl_rate;
>  	int lanes = max_rate < 24 ? 3 : 4;
> +	int port_clock;
>  
>  	frl_dfm.config.pixel_clock_nominal_khz = mode->clock;
>  	frl_dfm.config.hactive = mode->hdisplay;
> @@ -2064,7 +2080,9 @@ intel_hdmi_frl_mode_clock_valid(struct intel_connector *connector,
>  	if (!intel_hdmi_frl_dfm_nondsc_requirement_met(&frl_dfm))
>  		return MODE_CLOCK_HIGH;
>  
> -	return MODE_OK;
> +	port_clock = FRL_GBPS_TO_10KBPS(max_rate / lanes);
> +
> +	return hdmi_port_frl_clock_valid(hdmi, port_clock);
>  }

[Severity: Medium]
Does this code reject valid modes by checking the absolute maximum FRL rate
rather than the rate required by the mode?

In intel_hdmi_frl_mode_clock_valid(), port_clock is computed from the absolute
maximum FRL rate (hdmi->max_frl_rate) allowed by the sink EDID and VBT. The
function then checks if the PHY supports this exact max_rate.

However, hdmi->max_frl_rate is never clamped to the PHY's actual capabilities
during initialization. If max_frl_rate exceeds the PHY's capabilities, or if
it evaluates to an invalid non-standard rate, hdmi_port_frl_clock_valid()
returns MODE_CLOCK_RANGE, rejecting all FRL modes.

For example, if an OEM limits the VBT to HDMI_MAX_FRL_RATE_3G,
max_src_frl_rate incorrectly evaluates to 12 Gbps (3 * 4). If the sink supports
>= 18 Gbps, max_frl_rate becomes 12. The port_clock is then computed as
12 / 3 = 4 Gbps (400000 10kbps). Because 400000 is not in the PHY tables, the
PHY check fails.

Does this break FRL entirely on that platform, rejecting even low-bandwidth
modes the PHY could support?

While compute_config iterates through supported rates in later patches,
mode_valid remains hardcoded to test max_rate through the end of the series.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=37