[PATCH 0/5] I2C and pinctrl support for Apple A18 Pro devices

[PATCH 0/5] I2C and pinctrl support for Apple A18 Pro devices

[Yureka Lilian]

Hi,

this series contains two small formatting fixes for the A18 Pro device
trees, and adds the required dt-binding for i2c as well as the dt nodes
for pinctrl and i2c controllers used on the MacBook Neo.
The pinctrl dt-binding was already picked up from the previous series
regarding this topic [1]. The dtbs_check passes when this is applied on
top of linux-next or otherwise combined with said change.

Merge strategy:
The only change in this series outside of the device tree itself is the
apple,t8140-i2c dt-binding. There are no other pending changes to this
file, so it could simply go through the apple-soc tree provided Acked-by
from the respective maintainer.

Link[1]: https://lore.kernel.org/asahi/20260926-apple-pinctrl-t8140-v2-0-620bd11cd2a1@cyberchaos.dev/

Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
---
Yureka Lilian (5):
      arm64: dts: apple: t8140-j700: Fix property ordering
      arm64: dts: apple: t8140: Group cache-related properties of cpus
      dt-bindings: i2c: apple,i2c: Add t8140-i2c compatible
      arm64: dts: apple: t8140: Add pinctrl nodes
      arm64: dts: apple: t8140: Add i2c nodes

 .../devicetree/bindings/i2c/apple,i2c.yaml         |   1 +
 arch/arm64/boot/dts/apple/t8140-j700.dts           |   2 +-
 arch/arm64/boot/dts/apple/t8140.dtsi               | 172 ++++++++++++++++++++-
 3 files changed, 168 insertions(+), 7 deletions(-)
---
base-commit: becb95e45ef0dda9ffb35156d909d3da7a2789c3
change-id: 20261012-apple-a18-pro-dt-pinctrl-i2c-e78158bdd128

Best regards,
--  
Yureka Lilian <yureka@cyberchaos.dev>

[PATCH 1/5] arm64: dts: apple: t8140-j700: Fix property ordering

[Yureka Lilian]

The ordering requirements changed between 7.3 and 7.4.
The original t8140-j700.dtsi was developed against the 7.3
dt-check-style rules. Adjust it to the new ordering.

Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
---
 arch/arm64/boot/dts/apple/t8140-j700.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/apple/t8140-j700.dts b/arch/arm64/boot/dts/apple/t8140-j700.dts
index 227b58a7ce64..15c21c9e3f2b 100644
--- a/arch/arm64/boot/dts/apple/t8140-j700.dts
+++ b/arch/arm64/boot/dts/apple/t8140-j700.dts
@@ -12,8 +12,8 @@
 #include "t8140.dtsi"
 
 / {
-	compatible = "apple,j700", "apple,t8140", "apple,arm-platform";
 	model = "Apple MacBook Neo (A18 Pro, 2026)";
+	compatible = "apple,j700", "apple,t8140", "apple,arm-platform";
 
 	aliases {
 		serial0 = &serial0;

-- 
2.55.0

[PATCH 2/5] arm64: dts: apple: t8140: Group cache-related properties of cpus

[Yureka Lilian]

The dt-check-style from 7.3 raised an issue on the ordering, but
the one from current linux-next allows the cache properties to be
grouped, improving readability.

Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
---
 arch/arm64/boot/dts/apple/t8140.dtsi | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/apple/t8140.dtsi b/arch/arm64/boot/dts/apple/t8140.dtsi
index 150d91bdf6fc..40559da62923 100644
--- a/arch/arm64/boot/dts/apple/t8140.dtsi
+++ b/arch/arm64/boot/dts/apple/t8140.dtsi
@@ -60,8 +60,9 @@ cpu_e0: cpu@0 {
 			compatible = "apple,tahiti-e";
 			reg = <0x0 0x0>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x10000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x10000>;
 			i-cache-size = <0x20000>;
 			next-level-cache = <&l2_cache_0>;
 		};
@@ -71,8 +72,9 @@ cpu_e1: cpu@1 {
 			compatible = "apple,tahiti-e";
 			reg = <0x0 0x1>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x10000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x10000>;
 			i-cache-size = <0x20000>;
 			next-level-cache = <&l2_cache_0>;
 		};
@@ -82,8 +84,9 @@ cpu_e2: cpu@2 {
 			compatible = "apple,tahiti-e";
 			reg = <0x0 0x2>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x10000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x10000>;
 			i-cache-size = <0x20000>;
 			next-level-cache = <&l2_cache_0>;
 		};
@@ -93,8 +96,9 @@ cpu_e3: cpu@3 {
 			compatible = "apple,tahiti-e";
 			reg = <0x0 0x3>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x10000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x10000>;
 			i-cache-size = <0x20000>;
 			next-level-cache = <&l2_cache_0>;
 		};
@@ -104,8 +108,9 @@ cpu_p0: cpu@10100 {
 			compatible = "apple,tahiti-p";
 			reg = <0x0 0x10100>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x20000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x20000>;
 			i-cache-size = <0x30000>;
 			next-level-cache = <&l2_cache_1>;
 		};
@@ -115,8 +120,9 @@ cpu_p1: cpu@10101 {
 			compatible = "apple,tahiti-p";
 			reg = <0x0 0x10101>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x20000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x20000>;
 			i-cache-size = <0x30000>;
 			next-level-cache = <&l2_cache_1>;
 		};

-- 
2.55.0

[PATCH 3/5] dt-bindings: i2c: apple,i2c: Add t8140-i2c compatible

[Yureka Lilian]

The i2c block on the Apple Silicon T8140 (A18 Pro) SoC is compatible
with t8103. Add "apple,t8140-i2c" as SoC specific compatible under
"apple,t8103-i2c".

Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
---
 Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml
index 641f24b0ef4b..ea4ddc838d86 100644
--- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml
@@ -28,6 +28,7 @@ properties:
               - apple,t6031-i2c
               - apple,t8122-i2c
               - apple,t8132-i2c
+              - apple,t8140-i2c
           - const: apple,t8103-i2c
       - items:
           - enum:

-- 
2.55.0

Re: [PATCH 3/5] dt-bindings: i2c: apple,i2c: Add t8140-i2c compatible

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 75 bytes --]

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH 4/5] arm64: dts: apple: t8140: Add pinctrl nodes

[Yureka Lilian]

Add the pin controller nodes present on the Apple Silicon T8140 (A18
Pro) SoC. The pinctrl controllers uses the new apple,t8140-pinctrl
compatible to reflect the requirement for not reading or writing the
registers related to the pins listed in gpio-reserved-ranges.
The pinctrl_ap is a prerequisite for enabling the I2C and PCIe
controllers.

Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
---
 arch/arm64/boot/dts/apple/t8140.dtsi | 114 +++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t8140.dtsi b/arch/arm64/boot/dts/apple/t8140.dtsi
index 40559da62923..339a6b4f283d 100644
--- a/arch/arm64/boot/dts/apple/t8140.dtsi
+++ b/arch/arm64/boot/dts/apple/t8140.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/interrupt-controller/apple-aic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/apple.h>
 
 / {
 	compatible = "apple,t8140", "apple,arm-platform";
@@ -168,6 +169,29 @@ aic: interrupt-controller@301000000 {
 			power-domains = <&ps_aic>;
 		};
 
+		pinctrl_nub: pinctrl@3081f0000 {
+			compatible = "apple,t8140-pinctrl";
+			reg = <0x3 0x081f0000 0x0 0x4000>;
+			power-domains = <&ps_nub_gpio>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_nub 0 0 30>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 473 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 474 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 475 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 476 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 477 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 478 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 479 IRQ_TYPE_LEVEL_HIGH>;
+
+			apple,npins = <30>;
+		};
+
 		pmgr_mini: power-management@308280000 {
 			compatible = "apple,t8140-pmgr", "apple,t8103-pmgr",
 			             "syscon", "simple-mfd";
@@ -185,6 +209,96 @@ wdt: watchdog@3082b0000 {
 			interrupts = <AIC_IRQ 507 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		pinctrl_smc: pinctrl@30c820000 {
+			compatible = "apple,t8140-pinctrl";
+			reg = <0x3 0x0c820000 0x0 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_smc 0 0 6>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 572 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 573 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 574 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 575 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 576 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 577 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 578 IRQ_TYPE_LEVEL_HIGH>;
+
+			apple,npins = <6>;
+		};
+
+		pinctrl_aop: pinctrl@310824000 {
+			compatible = "apple,t8140-pinctrl";
+			reg = <0x3 0x10824000 0x0 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_aop 0 0 57>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 380 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 381 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 382 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 383 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 384 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 385 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 386 IRQ_TYPE_LEVEL_HIGH>;
+
+			apple,npins = <57>;
+		};
+
+		pinctrl_mtp: pinctrl@314838000 {
+			compatible = "apple,t8140-pinctrl";
+			reg = <0x3 0x14838000 0x0 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_mtp 0 0 10>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 1128 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 1129 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 1130 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 1131 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 1132 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 1133 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 1134 IRQ_TYPE_LEVEL_HIGH>;
+
+			apple,npins = <10>;
+		};
+
+		pinctrl_ap: pinctrl@31a000000 {
+			compatible = "apple,t8140-pinctrl";
+			reg = <0x3 0x1a000000 0x0 0x100000>;
+			power-domains = <&ps_gpio>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_ap 0 0 216>;
+			gpio-reserved-ranges = <134 1>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 263 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 264 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 265 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 266 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 267 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
+			             <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>;
+
+			apple,npins = <216>;
+		};
+
 		serial0: serial@385200000 {
 			compatible = "apple,s5l-uart";
 			reg = <0x3 0x85200000 0x0 0x1000>;

-- 
2.55.0

Re: [PATCH 4/5] arm64: dts: apple: t8140: Add pinctrl nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] pinctrl: apple: KASAN slab-out-of-bounds read during regmap initialization
- [High] pinctrl: apple: NULL pointer deref in apple_gpio_set_reg due to lazy regmap init
--

commit cd1bf71ed5d4ae5b51b2eed6ad8a3f10605beb2b
Author: Yureka Lilian <yureka@cyberchaos.dev>

arm64: dts: apple: t8140: Add pinctrl nodes

This commit adds the pin controller nodes present on the Apple Silicon T8140
(A18 Pro) SoC. It introduces the new apple,t8140-pinctrl compatible nodes
like pinctrl_nub and pinctrl_ap, which are prerequisites for enabling the
I2C and PCIe controllers.

> diff --git a/arch/arm64/boot/dts/apple/t8140.dtsi b/arch/arm64/boot/dts/apple/t8140.dtsi
> index 150d91bdf6fcc..339a6b4f283d2 100644
> --- a/arch/arm64/boot/dts/apple/t8140.dtsi
> +++ b/arch/arm64/boot/dts/apple/t8140.dtsi

[ ... ]

> @@ -162,6 +169,29 @@ aic: interrupt-controller@301000000 {
>  			power-domains = <&ps_aic>;
>  		};
>  
> +		pinctrl_nub: pinctrl@3081f0000 {
> +			compatible = "apple,t8140-pinctrl";
> +			reg = <0x3 0x081f0000 0x0 0x4000>;
> +			power-domains = <&ps_nub_gpio>;
> +
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pinctrl_nub 0 0 30>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupt-parent = <&aic>;
> +			interrupts = <AIC_IRQ 473 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 474 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 475 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 476 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 477 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 478 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 479 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			apple,npins = <30>;
> +		};
> +

[Severity: High]
This problem wasn't introduced by this patch, but does adding this node with
npins < 512 trigger a KASAN slab-out-of-bounds read in the driver?

When devm_gpiochip_add_data() is called during probe, gpiolib allocates
a 1-word valid_mask for the 30 pins. When get_direction() calls
apple_gpio_get_reg(), it triggers a lazy regmap initialization via
devm_regmap_init_mmio().

Because the driver statically sets num_reg_defaults_raw = 512 and uses
REGCACHE_FLAT, regcache_hw_init() iterates 512 times, calling
apple_gpio_readable_register() for each index:

drivers/pinctrl/pinctrl-apple-gpio.c:apple_gpio_readable_register() {
	...
	return gpiochip_line_is_valid(&pctl->gpio_chip, reg / 4);
}

Will this pass an unconstrained register index up to 511 directly to
gpiochip_line_is_valid(), causing a deterministic KASAN slab-out-of-bounds
read on the 1-word valid_mask?

If the out-of-bounds read returns 1, could the driver also attempt to read
non-existent hardware registers, triggering unhandled Data Aborts or SErrors?

[ ... ]

> @@ -179,6 +209,96 @@ wdt: watchdog@3082b0000 {
>  			interrupts = <AIC_IRQ 507 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  

[ ... ]

> +		pinctrl_ap: pinctrl@31a000000 {
> +			compatible = "apple,t8140-pinctrl";
> +			reg = <0x3 0x1a000000 0x0 0x100000>;
> +			power-domains = <&ps_gpio>;
> +
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pinctrl_ap 0 0 216>;
> +			gpio-reserved-ranges = <134 1>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupt-parent = <&aic>;
> +			interrupts = <AIC_IRQ 263 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 264 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 265 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 266 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 267 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
> +			             <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			apple,npins = <216>;
> +		};

[Severity: High]
Does exposing these new pinctrl devices to consumers lead to a NULL pointer
dereference in apple_gpio_set_reg() due to lazy regmap initialization?

drivers/pinctrl/pinctrl-apple-gpio.c:apple_gpio_pinctrl_probe() {
	...
	pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
	...
}

Because the pinctrl device is exposed to consumers early before groups,
functions, and the regmap are initialized, what happens if a consumer driver
probes concurrently and requests pins during this window?

drivers/pinctrl/pinctrl-apple-gpio.c:apple_gpio_set_reg() {
	...
	regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
	...
}

Will apple_gpio_pinmux_set() call apple_gpio_set_reg() and unconditionally
dereference the uninitialized (NULL) pctl->map, causing a kernel panic on boot?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012-apple-a18-pro-dt-pinctrl-i2c-v1-0-6c757966a99e@cyberchaos.dev?part=4

[PATCH 5/5] arm64: dts: apple: t8140: Add i2c nodes

[Yureka Lilian]

Add the i2c nodes in the Apple Silicon T8140 (A18 Pro) SoC. In the
MacBook Neo, i2c0 is used for the audio chip while the internal USB hub
and mux are connected to i2c2.

Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
---
 arch/arm64/boot/dts/apple/t8140.dtsi | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t8140.dtsi b/arch/arm64/boot/dts/apple/t8140.dtsi
index 339a6b4f283d..3b4f7695552b 100644
--- a/arch/arm64/boot/dts/apple/t8140.dtsi
+++ b/arch/arm64/boot/dts/apple/t8140.dtsi
@@ -297,6 +297,46 @@ pinctrl_ap: pinctrl@31a000000 {
 			             <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>;
 
 			apple,npins = <216>;
+
+			i2c0_pins: i2c0-pins {
+				pinmux = <APPLE_PINMUX(171, 1)>,
+				         <APPLE_PINMUX(170, 1)>;
+			};
+
+			i2c2_pins: i2c2-pins {
+				pinmux = <APPLE_PINMUX(165, 1)>,
+				         <APPLE_PINMUX(164, 1)>;
+			};
+		};
+
+		i2c0: i2c@385010000 {
+			compatible = "apple,t8140-i2c", "apple,t8103-i2c";
+			reg = <0x3 0x85010000 0x0 0x4000>;
+			clocks = <&clkref>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 1108 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&i2c0_pins>;
+			pinctrl-names = "default";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			power-domains = <&ps_i2c0>;
+
+			status = "disabled";
+		};
+
+		i2c2: i2c@385018000 {
+			compatible = "apple,t8140-i2c", "apple,t8103-i2c";
+			reg = <0x3 0x85018000 0x0 0x4000>;
+			clocks = <&clkref>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 1110 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&i2c2_pins>;
+			pinctrl-names = "default";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			power-domains = <&ps_i2c2>;
+
+			status = "disabled";
 		};
 
 		serial0: serial@385200000 {

-- 
2.55.0