[PATCH v12 00/16] drm/xe/hwmon: Update hwmon thermal mailbox

[PATCH v12 00/16] drm/xe/hwmon: Update hwmon thermal mailbox

[Karthik Poosa]

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This series adds CRI-specific temperature sensor handling to the Xe
hwmon implementation and fixes couple of hwmon issues.

CRI platforms may report unavailable temperature sensors and support
a variable number of VRAM temperature channels depending on platform
configuration. This series adds the required sensor presence checks and
uses platform-reported thermal configuration data to expose only valid
temperature-related hwmon attributes.

The series also corrects the telemetry group selection used for memory
controller temperature reporting.

v2:
 - Address review comments from Sashiko, Badal and Raag.
 - Enable IEEE 754 temperature decoding for MMIO temperature registers.
  - Split sensor validity check into mailbox vs MMIO handling; add
    is_temp_available() / is_temp_is_visible().
 - Temporarily disable memory controller and PCIe temperatures on CRI.

v3:
  - Detect unavailable temperature sensors: rephrase a debug log.
  - Decode mailbox temperatures as 8-bit sign-magnitude values instead of
    s8.
  - Use VRAM temperature sensor count from thermal config on CRI: address
    review comments from sashiko-bot@kernel.org and Rodrigo.
  - Decode CRI temperature registers as IEEE-754: reject temperatures that
    overflow long on 32-bit systems.

v4:
  - Address review comments and issues report from Rodrigo and
    sashiko-bot@kernel.org.
  - Decode mailbox temperatures as 8-bit sign-magnitude values.
  - Cache sensor availability during registration.
  - Enable memory controller and pcie sensors for CRI.
  - Derive the VRAM channel count from the CRI MSU enable mask.
  - Use CRI-specific package and VRAM temperature registers.
  - Handle the CRI memory controller and pcie sensor offsets as per CRI.

v5:
 - Remove the unintended IGT prefix from the patch titles.

v6:
 - Address issues reported by sashiko-bot@kernel.org.
 - Add VRAM individual channel CRI_VRAM_TEMPERATURE_N register for CRI.

v7:
 - Address review comments from Rodrigo.
    - Use ret instead of count in patch 1.
    - Return true for platforms without temperature sentinels support.
    - Rename has_mbx_temp_sentinel to has_temp_sentinel.
    - Add a info flag for pcie sensor offset.
    - Simplify temperature channels config.

v8:
 - Address review comment from Sashiko.
 - Revert the unconditional validation of temperature readings on
   non-sentinel platforms.
   This avoids creating spurious VRAM temperature channels when the
   corresponding sensors are unavailable.
a
v9:
 - Address review comment from Rodrigo.
 - Use helper for pcie sensor offset instead of info field.

v10:
 - Address review comments from sashiko.

v11:
 - Add https://patchwork.freedesktop.org/series/175943/ part of this
   series as patch 16. (Rodrigo)
 - Resubmit to get CI results as v10 didn't have it.

v12:
 - Address review comments from sashiko.

Karthik Poosa (16):
  drm/xe/hwmon: Handle pcode read failures of
    xe_hwmon_pcode_rmw_power_limit
  drm/xe/hwmon: Decode mailbox temperature as sign-magnitude
  drm/xe/hwmon: Fix thermal sensor data handling
  drm/xe/hwmon: Add helpers to validate thermal sensor readings
  drm/xe/hwmon: Handle unavailable memory controller sensors
  drm/xe/hwmon: Detect unavailable PCIe thermal sensors
  drm/xe/hwmon: Consolidate temperature sensor availability checks
  drm/xe/hwmon: Cache temperature availability to reduce probe time
  drm/xe/hwmon: use CRI-specific package and VRAM temperature registers
  drm/xe/hwmon: Add platform-aware VRAM thermal channel support
  drm/xe/hwmon: Decode CRI temperature registers as IEEE-754
  drm/xe/hwmon: Update memory controller temperature offset for CRI
  drm/xe/hwmon: add PCIe temperature support for CRI
  drm/xe/hwmon: Simplify temperature channels config
  drm/xe: Validate thermal sensor count before reads
  drm/xe/hwmon: Propagate all hardware read errors

 drivers/gpu/drm/xe/regs/xe_pcode_regs.h |   4 +
 drivers/gpu/drm/xe/xe_device_types.h    |   4 +
 drivers/gpu/drm/xe/xe_hwmon.c           | 565 ++++++++++++++++++------
 drivers/gpu/drm/xe/xe_pci.c             |   4 +
 drivers/gpu/drm/xe/xe_pci_types.h       |   2 +
 drivers/gpu/drm/xe/xe_pcode_api.h       |   2 -
 6 files changed, 442 insertions(+), 139 deletions(-)

-- 
2.25.1

[PATCH v12 01/16] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit

[Karthik Poosa]

Return early when the pcode read operation fails in
xe_hwmon_pcode_rmw_power_limit() and check the returned error in
callers to avoid updating power limit settings with invalid data.

v2: Check return in xe_hwmon_get_preregistration_info() also. (Sashiko)

Fixes: 8aa7306631f0 ("drm/xe/hwmon: Fix xe_hwmon_power_max_write")
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 56 ++++++++++++++++++++++-------------
 1 file changed, 35 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 5edeac961ec3..0b46572bb3c8 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -232,9 +232,11 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
 						  READ_PSYSGPU_POWER_LIMIT :
 						  READ_PACKAGE_POWER_LIMIT,
 						  prepare_power_limit_param2(hwmon)), &val0, &val1);
-	if (ret)
-		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
+	if (ret) {
+		drm_err(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
 			channel, val0, val1, ret);
+		return ret;
+	}
 
 	if (attr == PL1_HWMON_ATTR)
 		val0 = (val0 & ~clr) | set;
@@ -394,7 +396,9 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channe
 		if (hwmon->xe->info.has_mbx_power_limits) {
 			drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n",
 				PWR_ATTR_TO_STR(attr), channel);
-			xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
+			ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
+			if (ret)
+				goto unlock;
 			xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
 		} else {
 			reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);
@@ -679,15 +683,19 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
 
 	mutex_lock(&hwmon->hwmon_lock);
 
-	if (hwmon->xe->info.has_mbx_power_limits)
-		xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
-	else
+	ret = count;
+	if (hwmon->xe->info.has_mbx_power_limits) {
+		ret = xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
+		if (!ret)
+			ret = count;
+	} else {
 		r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
 				  PWR_LIM_TIME, rxy);
+	}
 
 	mutex_unlock(&hwmon->hwmon_lock);
 
-	return count;
+	return ret;
 }
 
 /* PSYS PL1 */
@@ -1510,23 +1518,29 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 				 "Failed to read power limits, check GPU firmware !\n");
 		} else {
 			drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n");
-			/* Write default limits to read from pcode from now on. */
-			xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR,
-						       CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME,
-						       hwmon->pl1_on_boot[CHANNEL_CARD]);
-			xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR,
-						       CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME,
-						       hwmon->pl1_on_boot[CHANNEL_PKG]);
-			xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR,
-						       CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME,
-						       hwmon->pl2_on_boot[CHANNEL_CARD]);
-			xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR,
-						       CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME,
-						       hwmon->pl2_on_boot[CHANNEL_PKG]);
+
 			hwmon->scl_shift_power = PWR_UNIT;
 			hwmon->scl_shift_energy = ENERGY_UNIT;
 			hwmon->scl_shift_time = TIME_UNIT;
-			hwmon->boot_power_limit_read = true;
+
+			/* Write default limits to read from pcode from now on. */
+			if (xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR,
+							   CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME,
+							   hwmon->pl1_on_boot[CHANNEL_CARD]) ||
+			    xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR,
+							   CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME,
+							   hwmon->pl1_on_boot[CHANNEL_PKG]) ||
+			    xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR,
+							   CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME,
+							   hwmon->pl2_on_boot[CHANNEL_CARD]) ||
+			    xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR,
+							   CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME,
+							   hwmon->pl2_on_boot[CHANNEL_PKG])) {
+				drm_warn(&hwmon->xe->drm,
+					 "Failed to set default power limits !\n");
+			} else {
+				hwmon->boot_power_limit_read = true;
+			}
 		}
 	} else {
 		drm_info(&hwmon->xe->drm, "Using register for power limits\n");
-- 
2.25.1

Re: [PATCH v12 01/16] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/xe/hwmon: PCODE active configuration corruption due to power limit init short-circuit
--

commit 96c45d5f8e540d8e962d44f94ea42a65f2c0cb61
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit

This commit adds error handling for pcode read failures in
xe_hwmon_pcode_rmw_power_limit(). It propagates the error codes back to
callers, including an updated initialization sequence in
xe_hwmon_get_preregistration_info().

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 5edeac961ec33..0b46572bb3c88 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -232,9 +232,11 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
>  						  READ_PSYSGPU_POWER_LIMIT :
>  						  READ_PACKAGE_POWER_LIMIT,
>  						  prepare_power_limit_param2(hwmon)), &val0, &val1);
> -	if (ret)
> -		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
> +	if (ret) {
> +		drm_err(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
>  			channel, val0, val1, ret);
> +		return ret;
> +	}
>  
>  	if (attr == PL1_HWMON_ATTR)
>  		val0 = (val0 & ~clr) | set;
[ ... ]
> @@ -1510,23 +1518,29 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>  				 "Failed to read power limits, check GPU firmware !\n");
>  		} else {
>  			drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n");
> -			/* Write default limits to read from pcode from now on. */
> -			xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR,
> -						       CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME,
> -						       hwmon->pl1_on_boot[CHANNEL_CARD]);
> -			xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR,
> -						       CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME,
> -						       hwmon->pl1_on_boot[CHANNEL_PKG]);
> -			xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR,
> -						       CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME,
> -						       hwmon->pl2_on_boot[CHANNEL_CARD]);
> -			xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR,
> -						       CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME,
> -						       hwmon->pl2_on_boot[CHANNEL_PKG]);
> +
>  			hwmon->scl_shift_power = PWR_UNIT;
>  			hwmon->scl_shift_energy = ENERGY_UNIT;
>  			hwmon->scl_shift_time = TIME_UNIT;
> -			hwmon->boot_power_limit_read = true;
> +
> +			/* Write default limits to read from pcode from now on. */
> +			if (xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR,
> +							   CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME,
> +							   hwmon->pl1_on_boot[CHANNEL_CARD]) ||
> +			    xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR,
> +							   CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME,
> +							   hwmon->pl1_on_boot[CHANNEL_PKG]) ||
> +			    xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR,
> +							   CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME,
> +							   hwmon->pl2_on_boot[CHANNEL_CARD]) ||
> +			    xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR,
> +							   CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME,
> +							   hwmon->pl2_on_boot[CHANNEL_PKG])) {
> +				drm_warn(&hwmon->xe->drm,
> +					 "Failed to set default power limits !\n");
> +			} else {
> +				hwmon->boot_power_limit_read = true;
> +			}

[Severity: High]
Does this code inadvertently leave power limit sysfs files exposed with
boot_power_limit_read set to false when an error occurs?

If any of the initializations fail, the logical OR short-circuits. This skips
the remaining initialization calls and leaves boot_power_limit_read as false,
but the driver continues loading.

When userspace later writes to a power limit via xe_hwmon_power_max_write(), it
calls xe_hwmon_pcode_rmw_power_limit(). Because boot_power_limit_read is false,
the read phase fetches firmware defaults (READ_PL_FROM_FW) instead of active
PCODE limits.

However, the write phase targets the active PCODE registers
(WRITE_PACKAGE_POWER_LIMIT). This asymmetrical read-modify-write silently
overwrites the active PCODE register (including sibling power limit enables and
time windows) with the firmware defaults, corrupting the active hardware
configuration.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261013184939.694945-1-karthik.poosa@intel.com?part=1

[PATCH v12 02/16] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude

[Karthik Poosa]

The mailbox temperature is an 8-bit sign-magnitude value (bit 7 sign,
bits 6:0 magnitude, range -127..127), not two's-complement. Casting the
raw byte to s8 decodes negative readings incorrectly.

Add mbx_temp_decode(), store the raw byte as u8, and use it in
get_mc_temp() and get_pcie_temp() so temperatures are decoded correctly.

Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 0b46572bb3c8..86ae02cc3c3a 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -104,6 +104,10 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
+#define TEMP_MBX_SIGN		BIT(7)
+#define TEMP_MBX_MAG		GENMASK(6, 0)
+
 /* Maximum characters in hwmon label name */
 #define MAX_LABEL_SIZE		16
 
@@ -139,8 +143,8 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
-	/** @value: signed value from each sensor */
-	s8 value[U8_MAX];
+	/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
+	u8 value[U8_MAX];
 	/** @vram_label: vram label names */
 	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
 };
@@ -816,6 +820,14 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	return ret;
 }
 
+/* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
+static int mbx_temp_decode(u8 value)
+{
+	int temp = value & TEMP_MBX_MAG;
+
+	return (value & TEMP_MBX_SIGN) ? -temp : temp;
+}
+
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
@@ -832,7 +844,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 	}
 
 	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
-		average += hwmon->temp.value[i];
+		average += mbx_temp_decode(hwmon->temp.value[i]);
 
 	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
 	*val = average * MILLIDEGREE_PER_DEGREE;
@@ -855,7 +867,7 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
+	*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
 
 	return 0;
 }
-- 
2.25.1

[PATCH v12 03/16] drm/xe/hwmon: Fix thermal sensor data handling

[Karthik Poosa]

Read all required thermal groups in get_mc_temp() and store them in a
dword-aligned buffer, avoiding unaligned pcode accesses and ensuring
correct memory controller temperature reporting.

Store the pcode thermal data and thermal limit words as little-endian,
so their per-byte views match the hardware layout on big-endian hosts.

Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
Fixes: c332fba805d6 ("drm/xe/hwmon: Expose temperature limits")
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 86ae02cc3c3a..b1d57f491057 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -138,13 +138,17 @@ struct xe_hwmon_thermal_info {
 	union {
 		/** @limit: temperatures limits */
 		u8 limit[TEMP_LIMIT_MAX];
-		/** @data: temperature limits in dwords */
-		u32 data[DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32))];
+		/** @data: temperature limits as little-endian dwords */
+		__le32 data[DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32))];
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
-	/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
-	u8 value[U8_MAX];
+	union {
+		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
+		u8 value[U8_MAX + 1];
+		/** @dword: sensor values as little-endian dwords, u32-aligned for pcode reads */
+		__le32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
+	};
 	/** @vram_label: vram label names */
 	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
 };
@@ -798,16 +802,17 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
-	u32 config = 0;
+	u32 config = 0, data0 = 0, data1 = 0;
 	int ret;
 
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
-			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
+			    &data0, &data1);
 	if (ret)
 		return ret;
 
-	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%x val1 0x%x\n",
-		hwmon->temp.data[0], hwmon->temp.data[1]);
+	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%x val1 0x%x\n", data0, data1);
+	hwmon->temp.data[0] = cpu_to_le32(data0);
+	hwmon->temp.data[1] = cpu_to_le32(data1);
 
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
 			    &config, NULL);
@@ -831,16 +836,18 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
-	u32 *dword = (u32 *)hwmon->temp.value;
 	s32 average = 0;
 	int ret, i;
 
-	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
+	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
+		u32 data = 0;
+
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
-				    (dword + i), NULL);
+				    &data, NULL);
 		if (ret)
 			return ret;
-		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
+		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, data);
+		hwmon->temp.dword[i] = cpu_to_le32(data);
 	}
 
 	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
-- 
2.25.1

[PATCH v12 04/16] drm/xe/hwmon: Add helpers to validate thermal sensor readings

[Karthik Poosa]

Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
0xFF indicates the sensor is unavailable.

Gate these checks behind has_temp_sentinel, enabled on CRI currently.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h |  2 ++
 drivers/gpu/drm/xe/xe_hwmon.c        | 20 ++++++++++++++++++++
 drivers/gpu/drm/xe/xe_pci.c          |  2 ++
 drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
 4 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 4e0e1bc040c1..beb0ceaabb3f 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -227,6 +227,8 @@ struct xe_device {
 		u8 has_sriov:1;
 		/** @info.has_sysctrl: Supports System Controller */
 		u8 has_sysctrl:1;
+		/** @info.has_temp_sentinel: Device has temperature-unavailable sentinels */
+		u8 has_temp_sentinel:1;
 		/** @info.has_usm: Device has unified shared memory support */
 		u8 has_usm:1;
 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index b1d57f491057..418e1c503eb5 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -104,6 +104,9 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* Mailbox sentinel reported for an unavailable temperature sensor */
+#define TEMP_MBX_INVALID	0xFF
+
 /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
 #define TEMP_MBX_SIGN		BIT(7)
 #define TEMP_MBX_MAG		GENMASK(6, 0)
@@ -825,6 +828,23 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	return ret;
 }
 
+static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
+{
+	/*
+	 * On platforms lacking temperature sentinel support, a value of 0 is treated
+	 * as invalid. While 0°C is theoretically possible, it is highly unlikely for
+	 * a discrete GPU in normal environments, making it a reasonable fallback
+	 * indicator for invalid or uninitialized temperature readings.
+	 */
+	return hwmon->xe->info.has_temp_sentinel ? value != U32_MAX : value != 0;
+}
+
+/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
+static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
+{
+	return hwmon->xe->info.has_temp_sentinel ? value != TEMP_MBX_INVALID : value != 0;
+}
+
 /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
 static int mbx_temp_decode(u8 value)
 {
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index e44b74b9aa27..111d0aa45b10 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -486,6 +486,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_soc_remapper_telem = true,
 	.has_sriov = true,
 	.has_sysctrl = true,
+	.has_temp_sentinel = true,
 	.max_gt_per_tile = 2,
 	MULTI_LRC_MASK,
 	.require_force_probe = true,
@@ -817,6 +818,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
 		desc->has_sriov;
 	xe->info.has_sysctrl = desc->has_sysctrl;
+	xe->info.has_temp_sentinel = desc->has_temp_sentinel;
 	xe->info.skip_guc_pc = desc->skip_guc_pc;
 	xe->info.skip_pcode = desc->skip_pcode;
 	xe->info.needs_scratch = desc->needs_scratch;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 448bbe5ba1d7..15eedac8467a 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -61,6 +61,7 @@ struct xe_device_desc {
 	u8 has_soc_remapper_telem:1;
 	u8 has_sriov:1;
 	u8 has_sysctrl:1;
+	u8 has_temp_sentinel:1;
 	u8 needs_scratch:1;
 	u8 skip_guc_pc:1;
 	u8 skip_pcode:1;
-- 
2.25.1

Re: [PATCH v12 04/16] drm/xe/hwmon: Add helpers to validate thermal sensor readings

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] hwmon: Validation helpers fail to filter U32_MAX/0xFF on pre-CRI platforms
--

commit 3734bfcfc0e55f578f66176481a816cff2820aea
Author: Karthik Poosa <karthik.poosa@intel.com>
drm/xe/hwmon: Add helpers to validate thermal sensor readings

This commit adds mmio_temp_valid() and mbx_temp_valid() helpers to validate
temperature sensor readings. It introduces has_temp_sentinel to use U32_MAX
or 0xFF as invalid indicators on supported platforms, falling back to checking
for 0 on other platforms.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index b1d57f4910579..418e1c503eb5a 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c

[ ... ]

> @@ -825,6 +828,23 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	return ret;
>  }
>  
> +static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
> +{
> +	/*
> +	 * On platforms lacking temperature sentinel support, a value of 0 is treated
> +	 * as invalid. While 0°C is theoretically possible, it is highly unlikely for
> +	 * a discrete GPU in normal environments, making it a reasonable fallback
> +	 * indicator for invalid or uninitialized temperature readings.
> +	 */
> +	return hwmon->xe->info.has_temp_sentinel ? value != U32_MAX : value != 0;

[Severity: Medium]
Does this allow standard MMIO read failures (U32_MAX) to bypass the filter on
platforms lacking has_temp_sentinel?

If a device on a platform before CRI encounters a PCI read failure returning
U32_MAX, the ternary fallback (value != 0) evaluates to true. Any userspace
read of the hwmon sysfs nodes during such conditions would expose bogus
extreme temperatures instead of properly returning an error.

> +}
> +
> +/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
> +static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
> +{
> +	return hwmon->xe->info.has_temp_sentinel ? value != TEMP_MBX_INVALID : value != 0;

[Severity: Medium]
Does this allow 0xFF (TEMP_MBX_INVALID) to be treated as a valid reading on
platforms lacking has_temp_sentinel?

If a device reads an unpopulated or unavailable mailbox sensor returning 0xFF,
the fallback check (value != 0) evaluates to true. This would bypass the filter
and erroneously decode the reading to -127 degrees Celsius.

> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261013184939.694945-1-karthik.poosa@intel.com?part=4

[PATCH v12 05/16] drm/xe/hwmon: Handle unavailable memory controller sensors

[Karthik Poosa]

Skip memory controller sensors that report invalid readings when
computing the average temperature in get_mc_temp(). Return -ENXIO when
no valid sensor data is available, and allow the helper to be used as
an availability probe by making the output parameter optional.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 418e1c503eb5..2f92ec950614 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -856,8 +856,8 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	int ret, i, count = 0;
 	s32 average = 0;
-	int ret, i;
 
 	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
 		u32 data = 0;
@@ -870,11 +870,23 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 		hwmon->temp.dword[i] = cpu_to_le32(data);
 	}
 
-	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
+	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
+		if (!mbx_temp_valid(hwmon, hwmon->temp.value[i]))
+			continue;
 		average += mbx_temp_decode(hwmon->temp.value[i]);
+		count++;
+	}
+
+	if (!count) {
+		drm_dbg(&hwmon->xe->drm, "Memory controller temperature unavailable!\n");
+		return -ENXIO;
+	}
+
+	average /= count;
+
+	if (val)
+		*val = average * MILLIDEGREE_PER_DEGREE;
 
-	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
-	*val = average * MILLIDEGREE_PER_DEGREE;
 	return 0;
 }
 
-- 
2.25.1

[PATCH v12 06/16] drm/xe/hwmon: Detect unavailable PCIe thermal sensors

[Karthik Poosa]

Return -ENXIO from get_pcie_temp() when the mailbox reports an invalid
reading, so the PCIe sensor can be treated as unavailable. Guard the val
store so the function can be used purely as an availability probe. No
sysfs visibility changes.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 2f92ec950614..4463f32c8d8c 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -906,7 +906,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-	*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
+	if (!mbx_temp_valid(hwmon, data)) {
+		drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n");
+		return -ENXIO;
+	}
+
+	if (val)
+		*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
 
 	return 0;
 }
-- 
2.25.1

[PATCH v12 07/16] drm/xe/hwmon: Consolidate temperature sensor availability checks

[Karthik Poosa]

Replace is_vram_ch_available() with a generalized is_temp_available()
that validates PKG, VRAM, per-channel VRAM, memory controller and PCIe
sensors using the new validity helpers. Rename the existing callers to
the new helper.

Use is_temp_available() from xe_hwmon_temp_is_visible() so attributes for
sensors that are not present are not exposed during hwmon registration.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 64 ++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 4463f32c8d8c..b2f18a32487c 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -1011,19 +1011,39 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
 	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
 }
 
-static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
+static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
-	int vram_id = channel - CHANNEL_VRAM_N;
-	struct xe_reg vram_reg;
+	struct xe_reg reg;
+	u32 reg_val;
 
-	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
-	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
-		return false;
+	switch (channel) {
+	case CHANNEL_PKG:
+	case CHANNEL_VRAM:
+	case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
+		reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
+		if (!xe_reg_is_valid(reg))
+			return false;
+
+		reg_val = xe_mmio_read32(mmio, reg);
+		if (!mmio_temp_valid(hwmon, reg_val)) {
+			drm_dbg(&hwmon->xe->drm,
+				"channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
+			return false;
+		}
+
+		if (channel >= CHANNEL_VRAM_N)
+			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
+				"vram_ch_%d", channel - CHANNEL_VRAM_N);
 
-	/* Create label only for available vram channel */
-	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
-	return true;
+		return true;
+	case CHANNEL_MCTRL:
+		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
+	case CHANNEL_PCIE:
+		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);
+	default:
+		return false;
+	}
 }
 
 static umode_t
@@ -1033,14 +1053,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_emergency:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
-		case CHANNEL_VRAM:
-			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_vram_ch_available(hwmon, channel) &&
+			return (is_temp_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1048,14 +1067,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_crit:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
-		case CHANNEL_VRAM:
-			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_vram_ch_available(hwmon, channel) &&
+			return (is_temp_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1063,7 +1081,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_max:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_MAX] ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -1072,13 +1091,10 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		switch (channel) {
 		case CHANNEL_PKG:
 		case CHANNEL_VRAM:
-			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
-								channel)) ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
+			return is_temp_available(hwmon, channel) ? 0444 : 0;
 		default:
 			return 0;
 		}
-- 
2.25.1

Re: [PATCH v12 07/16] drm/xe/hwmon: Consolidate temperature sensor availability checks

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe/hwmon: dynamic hw queries at probe hide sysfs attributes on timeout
--

commit 4140f9b7c587fc4925ef3079bf0c972416615373
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Consolidate temperature sensor availability checks

This patch introduces a generalized is_temp_available() function to validate
PKG, VRAM, MCTRL, and PCIE temperature sensors. It uses this helper within
xe_hwmon_temp_is_visible() to prevent exposing sysfs attributes for sensors
that are not present during hwmon registration.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 4463f32c8d8cb..b2f18a32487cc 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -1011,19 +1011,39 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
>  	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
>  }
>  
> -static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
> +static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
>  {
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> -	int vram_id = channel - CHANNEL_VRAM_N;
> -	struct xe_reg vram_reg;
> +	struct xe_reg reg;
> +	u32 reg_val;
>  
> -	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> -		return false;
> +	switch (channel) {
> +	case CHANNEL_PKG:
> +	case CHANNEL_VRAM:
> +	case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> +		reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> +		if (!xe_reg_is_valid(reg))
> +			return false;
> +
> +		reg_val = xe_mmio_read32(mmio, reg);
> +		if (!mmio_temp_valid(hwmon, reg_val)) {
> +			drm_dbg(&hwmon->xe->drm,
> +				"channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
> +			return false;
> +		}

[Severity: Medium]
If xe_mmio_read32() returns an uninitialized value (like 0) during early boot,
does returning false here permanently prevent the creation of the sysfs
attribute for this sensor?

In mmio_temp_valid(), 0 is treated as an invalid temperature, which might only
be a temporary state during device probe before the hardware is fully
initialized. Since this is called from the is_visible callback, returning
false will hide the attribute permanently.

> +
> +		if (channel >= CHANNEL_VRAM_N)
> +			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
> +				"vram_ch_%d", channel - CHANNEL_VRAM_N);
>  
> -	/* Create label only for available vram channel */
> -	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
> -	return true;
> +		return true;
> +	case CHANNEL_MCTRL:
> +		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
> +	case CHANNEL_PCIE:
> +		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);

[Severity: Medium]
Do these dynamic PCODE mailbox reads at probe time risk permanently hiding
the MCTRL and PCIE sysfs attributes if there is a transient error?

If get_mc_temp() or get_pcie_temp() encounter a mailbox timeout or other
transient failure when called from xe_hwmon_temp_is_visible(), it evaluates
to false, preventing the hwmon core from creating the sysfs files.

Prior to this patch, MCTRL and PCIE merely checked hwmon->temp.count
statically without issuing a dynamic read.

> +	default:
> +		return false;
> +	}
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261013184939.694945-1-karthik.poosa@intel.com?part=7

[PATCH v12 08/16] drm/xe/hwmon: Cache temperature availability to reduce probe time

[Karthik Poosa]

Avoid probing temperature sensor availability from the hwmon is_visible()
callback. For MCTRL and PCIe channels, that path can trigger repeated
blocking mailbox reads while sysfs attributes are being created, increasing
probe time and making attribute creation sensitive to transient failures.

Probe temperature availability once during preregistration and cache the
result for subsequent visibility checks.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 39 +++++++++++++++++++++++------------
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index b2f18a32487c..b6e2d20de2b7 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -146,6 +146,8 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
+	/** @available: temperature sensor availability cached at registration */
+	bool available[CHANNEL_MAX];
 	union {
 		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
 		u8 value[U8_MAX + 1];
@@ -1011,7 +1013,7 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
 	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
 }
 
-static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
+static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	struct xe_reg reg;
@@ -1032,10 +1034,6 @@ static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 			return false;
 		}
 
-		if (channel >= CHANNEL_VRAM_N)
-			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
-				"vram_ch_%d", channel - CHANNEL_VRAM_N);
-
 		return true;
 	case CHANNEL_MCTRL:
 		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
@@ -1046,6 +1044,22 @@ static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 	}
 }
 
+static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
+{
+	int channel;
+
+	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
+		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
+
+	for (channel = 0; channel < CHANNEL_MAX; channel++) {
+		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
+		if (hwmon->temp.available[channel] &&
+		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
+				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
+	}
+}
+
 static umode_t
 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 {
@@ -1055,11 +1069,11 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_PKG:
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
 		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1069,11 +1083,11 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_PKG:
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
 		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1081,7 +1095,7 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_max:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1094,7 +1108,7 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return is_temp_available(hwmon, channel) ? 0444 : 0;
+			return hwmon->temp.available[channel] ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -1642,8 +1656,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
 			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
 
-	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
-		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
+	xe_hwmon_init_temp_info(hwmon);
 }
 
 int xe_hwmon_register(struct xe_device *xe)
-- 
2.25.1

[PATCH v12 09/16] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers

[Karthik Poosa]

Crescent Island uses different MMIO offsets for package and VRAM
temperature than Battlemage. Add CRI-specific register definitions
and select them in xe_hwmon_get_reg() for REG_TEMP handling.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_pcode_regs.h | 3 +++
 drivers/gpu/drm/xe/xe_hwmon.c           | 9 ++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
index c63b409d7a82..a969661f0c95 100644
--- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
@@ -28,6 +28,9 @@
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
 
 #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
+#define CRI_PACKAGE_TEMPERATURE			XE_REG(0x138344)
+#define CRI_VRAM_TEMPERATURE			XE_REG(0x138348)
 #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
+#define CRI_VRAM_TEMPERATURE_N(n)		XE_REG(0x138a00 + ((n) * (sizeof(u32))))
 
 #endif /* _XE_PCODE_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index b6e2d20de2b7..7ff161cbbcfc 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -276,7 +276,14 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 
 	switch (hwmon_reg) {
 	case REG_TEMP:
-		if (xe->info.platform == XE_BATTLEMAGE || xe->info.platform == XE_CRESCENTISLAND) {
+		if (xe->info.platform == XE_CRESCENTISLAND) {
+			if (channel == CHANNEL_PKG)
+				return CRI_PACKAGE_TEMPERATURE;
+			else if (channel == CHANNEL_VRAM)
+				return CRI_VRAM_TEMPERATURE;
+			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+				return CRI_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
+		} else if (xe->info.platform == XE_BATTLEMAGE) {
 			if (channel == CHANNEL_PKG)
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
-- 
2.25.1

[PATCH v12 10/16] drm/xe/hwmon: Add platform-aware VRAM thermal channel support

[Karthik Poosa]

On CRI, derive the number of available VRAM temperature channels from the
CRI_MSU_VRAM_ENABLE register, where each enabled MSU contributes
VRAM_CHANNELS_PER_MSU channels.
 
Increase the maximum supported VRAM channel count to 80 and use the
derived count to control VRAM sensor enumeration, channel access, and
VRAM label allocation. Add a has_fixed_vram_channels platform flag to
preserve the existing fixed-channel behavior on non-CRI platforms.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_pcode_regs.h |   1 +
 drivers/gpu/drm/xe/xe_device_types.h    |   2 +
 drivers/gpu/drm/xe/xe_hwmon.c           | 162 +++++++++++++++++++++---
 drivers/gpu/drm/xe/xe_pci.c             |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h       |   1 +
 5 files changed, 153 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
index a969661f0c95..d9e4847dd68e 100644
--- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
@@ -28,6 +28,7 @@
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
 
 #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
+#define CRI_MSU_VRAM_ENABLE			XE_REG(0x138340)
 #define CRI_PACKAGE_TEMPERATURE			XE_REG(0x138344)
 #define CRI_VRAM_TEMPERATURE			XE_REG(0x138348)
 #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index beb0ceaabb3f..161ba2b27f47 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -185,6 +185,8 @@ struct xe_device {
 		u8 has_drm_ras:1;
 		/** @info.has_fan_control: Device supports fan control */
 		u8 has_fan_control:1;
+		/** @info.has_fixed_vram_channels: Device has fixed VRAM temperature channels */
+		u8 has_fixed_vram_channels:1;
 		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
 		u8 has_flat_ccs:1;
 		/** @info.has_gsc_nvm: Device has gsc non-volatile memory */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 7ff161cbbcfc..95c4ccefa603 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -39,7 +39,11 @@ enum xe_hwmon_reg_operation {
 	REG_READ64,
 };
 
-#define MAX_VRAM_CHANNELS      (16)
+#define MAX_VRAM_CHANNELS	80
+#define FIXED_VRAM_CHANNELS	16
+
+/* Each MSU enable bit maps to one VRAM subsystem of 4 channels. */
+#define VRAM_CHANNELS_PER_MSU	4
 
 enum xe_hwmon_channel {
 	CHANNEL_CARD,
@@ -48,6 +52,7 @@ enum xe_hwmon_channel {
 	CHANNEL_MCTRL,
 	CHANNEL_PCIE,
 	CHANNEL_VRAM_N,
+	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
 	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
 	CHANNEL_MAX,
 };
@@ -144,18 +149,22 @@ struct xe_hwmon_thermal_info {
 		/** @data: temperature limits as little-endian dwords */
 		__le32 data[DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32))];
 	};
-	/** @count: no of temperature sensors available for the platform */
+	/** @count: temperature sensors count from READ_THERMAL_CONFIG */
 	u8 count;
+	/** @vram_count: exclusive upper bound for VRAM temperature channel indices */
+	u8 vram_count;
 	/** @available: temperature sensor availability cached at registration */
 	bool available[CHANNEL_MAX];
+	/** @msu_mask: VRAM subsystem enable mask read from MMIO */
+	u32 msu_mask;
 	union {
 		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
 		u8 value[U8_MAX + 1];
 		/** @dword: sensor values as little-endian dwords, u32-aligned for pcode reads */
 		__le32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
 	};
-	/** @vram_label: vram label names */
-	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
+	/** @vram_label: vram label names, dynamically allocated based on vram_count */
+	char (*vram_label)[MAX_LABEL_SIZE];
 };
 
 /**
@@ -269,6 +278,14 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
 	return ret;
 }
 
+static bool xe_hwmon_vram_channel_enabled(const struct xe_hwmon *hwmon, int index)
+{
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
+		return hwmon->temp.msu_mask & BIT(index / VRAM_CHANNELS_PER_MSU);
+
+	return true;
+}
+
 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
 				      int channel)
 {
@@ -281,14 +298,16 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 				return CRI_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
 				return CRI_VRAM_TEMPERATURE;
-			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
+				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
 				return CRI_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
 		} else if (xe->info.platform == XE_BATTLEMAGE) {
 			if (channel == CHANNEL_PKG)
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
 				return BMG_VRAM_TEMPERATURE;
-			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
+				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
 				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
 		} else if (xe->info.platform == XE_DG2) {
 			if (channel == CHANNEL_PKG)
@@ -800,6 +819,70 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL),
 	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
 			   HWMON_P_CAP,
@@ -814,9 +897,31 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	u32 config = 0, data0 = 0, data1 = 0;
 	int ret;
 
+	/*
+	 * Only CRI reports dynamic VRAM channel state. Fixed-channel platforms
+	 * set the count up front so those sensors stay visible even if the thermal
+	 * mailbox reads below fail.
+	 */
+	if (hwmon->xe->info.has_fixed_vram_channels)
+		hwmon->temp.vram_count = FIXED_VRAM_CHANNELS;
+
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND) {
+		hwmon->temp.msu_mask = xe_mmio_read32(mmio, CRI_MSU_VRAM_ENABLE);
+		hwmon->temp.vram_count = fls(hwmon->temp.msu_mask) * VRAM_CHANNELS_PER_MSU;
+		drm_dbg(&hwmon->xe->drm, "MSU VRAM enable mask 0x%x, VRAM channel bound %d\n",
+			hwmon->temp.msu_mask, hwmon->temp.vram_count);
+		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS) {
+			drm_warn(&hwmon->xe->drm,
+				 "VRAM channel bound %d exceeds max %d, clamping\n",
+				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
+			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
+		}
+	}
+
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
 			    &data0, &data1);
 	if (ret)
@@ -1034,6 +1139,14 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 		if (!xe_reg_is_valid(reg))
 			return false;
 
+		/*
+		 * On CRI, VRAM channel presence comes from the MSU enable mask
+		 * (applied in xe_hwmon_get_reg()); the temperature register's
+		 * 0xffffffff sentinel is not reliable for VRAM channels.
+		 */
+		if (hwmon->xe->info.platform == XE_CRESCENTISLAND && channel >= CHANNEL_VRAM_N)
+			return true;
+
 		reg_val = xe_mmio_read32(mmio, reg);
 		if (!mmio_temp_valid(hwmon, reg_val)) {
 			drm_dbg(&hwmon->xe->drm,
@@ -1051,20 +1164,31 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 	}
 }
 
-static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
+static int xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
 {
+	struct device *dev = hwmon->xe->drm.dev;
 	int channel;
 
 	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
 		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
 
+	/* vram_count is known only after reading thermal info above. */
+	if (hwmon->temp.vram_count) {
+		hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
+						      MAX_LABEL_SIZE, GFP_KERNEL);
+		if (!hwmon->temp.vram_label)
+			return -ENOMEM;
+	}
+
 	for (channel = 0; channel < CHANNEL_MAX; channel++) {
 		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
-		if (hwmon->temp.available[channel] &&
-		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+		if (hwmon->temp.available[channel] && hwmon->temp.vram_label &&
+		    in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
 				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
 	}
+
+	return 0;
 }
 
 static umode_t
@@ -1560,8 +1684,10 @@ static int xe_hwmon_read_label(struct device *dev,
 			*str = "mctrl";
 		else if (channel == CHANNEL_PCIE)
 			*str = "pcie";
-		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
+		else
+			return -EOPNOTSUPP;
 		return 0;
 	case hwmon_power:
 	case hwmon_energy:
@@ -1589,7 +1715,7 @@ static const struct hwmon_chip_info hwmon_chip_info = {
 	.info = hwmon_info,
 };
 
-static void
+static int
 xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
@@ -1663,7 +1789,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
 			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
 
-	xe_hwmon_init_temp_info(hwmon);
+	return xe_hwmon_init_temp_info(hwmon);
 }
 
 int xe_hwmon_register(struct xe_device *xe)
@@ -1692,7 +1818,9 @@ int xe_hwmon_register(struct xe_device *xe)
 	hwmon->xe = xe;
 	xe->hwmon = hwmon;
 
-	xe_hwmon_get_preregistration_info(hwmon);
+	ret = xe_hwmon_get_preregistration_info(hwmon);
+	if (ret)
+		goto err_null_hwmon;
 
 	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
 
@@ -1702,10 +1830,14 @@ int xe_hwmon_register(struct xe_device *xe)
 								hwmon_groups);
 	if (IS_ERR(hwmon->hwmon_dev)) {
 		drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
-		xe->hwmon = NULL;
-		return PTR_ERR(hwmon->hwmon_dev);
+		ret = PTR_ERR(hwmon->hwmon_dev);
+		goto err_null_hwmon;
 	}
 
 	return 0;
+
+err_null_hwmon:
+	xe->hwmon = NULL;
+	return ret;
 }
 MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY");
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 111d0aa45b10..e754668100cf 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -417,6 +417,7 @@ static const struct xe_device_desc bmg_desc = {
 	.dma_mask_size = 46,
 	.has_display = true,
 	.has_fan_control = true,
+	.has_fixed_vram_channels = true,
 	.has_flat_ccs = 1,
 	.has_mbx_power_limits = true,
 	.has_mbx_thermal_info = true,
@@ -798,6 +799,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_device_uid = desc->has_device_uid;
 	xe->info.has_drm_ras = desc->has_drm_ras;
 	xe->info.has_fan_control = desc->has_fan_control;
+	xe->info.has_fixed_vram_channels = desc->has_fixed_vram_channels;
 	/* runtime fusing may force flat_ccs to disabled later */
 	xe->info.has_flat_ccs = desc->has_flat_ccs;
 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 15eedac8467a..ce0b0f6c5b18 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -43,6 +43,7 @@ struct xe_device_desc {
 	u8 has_device_uid:1;
 	u8 has_drm_ras:1;
 	u8 has_fan_control:1;
+	u8 has_fixed_vram_channels:1;
 	u8 has_flat_ccs:1;
 	u8 has_gsc_nvm:1;
 	u8 has_heci_gscfi:1;
-- 
2.25.1

[PATCH v12 11/16] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754

[Karthik Poosa]

CRI temperature registers encode package and VRAM temperatures as
IEEE-754 floating-point values. Decode these values before exposing
them through hwmon.
 
Use integer-based IEEE-754 decoding since kernel code does not use
floating-point operations and hwmon reports integer temperatures.

v2: Add missing description for parameter 'temperature' in
    xe_hwmon_temperature_decode().

v3: Add missing mmio_temp_valid() check in xe_hwmon_temp_read() for MMIO
    temperature register reads.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
---
 drivers/gpu/drm/xe/xe_hwmon.c | 99 ++++++++++++++++++++++++++++++-----
 1 file changed, 85 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 95c4ccefa603..a57b369215ee 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -1248,6 +1248,70 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	}
 }
 
+#define IEEE754_SIGN		REG_BIT(31)
+#define IEEE754_EXP_MASK	REG_GENMASK(30, 23)
+#define IEEE754_MANTISSA_MASK	REG_GENMASK(22, 0)
+#define IEEE754_EXP_BIAS	127 /* Exponent bias to obtain the actual exponent */
+#define IEEE754_MANTISSA_BITS	23 /* Mantissa width and implicit leading-1 bit position */
+#define IEEE754_EXP_SPECIAL	0xff /* reserved exponent value encoding infinity or NaN */
+
+/**
+ * xe_hwmon_temperature_decode - Decode an IEEE-754 temperature register value
+ * @reg_val: The raw register value to decode
+ * @temperature: Pointer to store the decoded temperature in millidegrees Celsius.
+ *
+ * IEEE-754 single-precision format:
+ *
+ *  31 30                         23 22                         0
+ * +--+-----------------------------+----------------------------+
+ * | S|          exponent           |          fraction          |
+ * +--+-----------------------------+----------------------------+
+ *
+ * value = (-1)^S * 1.fraction * 2^(exponent - 127)
+ *
+ * Return: 0 on success or an error if @reg_val is non-finite or cannot be
+ * represented in millidegrees Celsius.
+ */
+static int xe_hwmon_temperature_decode(u32 reg_val, long *temperature)
+{
+	u32 exponent = REG_FIELD_GET(IEEE754_EXP_MASK, reg_val);
+	u32 mantissa = REG_FIELD_GET(IEEE754_MANTISSA_MASK, reg_val);
+	s64 value;
+	int shift;
+
+	/* Exponent 0xff encodes infinity or NaN. */
+	if (exponent == IEEE754_EXP_SPECIAL)
+		return -EINVAL;
+
+	/* Subnormal values are smaller than one millidegree Celsius. */
+	if (!exponent) {
+		*temperature = 0;
+		return 0;
+	}
+
+	value = (s64)(mantissa | BIT(IEEE754_MANTISSA_BITS)) * MILLIDEGREE_PER_DEGREE;
+	shift = exponent - (IEEE754_EXP_BIAS + IEEE754_MANTISSA_BITS);
+	if (shift >= 0) {
+		if (shift >= BITS_PER_LONG || value > (LONG_MAX >> shift))
+			return -ERANGE;
+		value <<= shift;
+	} else if (shift > -64) {
+		value >>= -shift;
+	} else {
+		value = 0;
+	}
+
+	/* Ensure the magnitude fits in long, which is 32-bit on some arches. */
+	if (value > LONG_MAX)
+		return -ERANGE;
+
+	if (reg_val & IEEE754_SIGN)
+		value = -value;
+
+	*temperature = value;
+	return 0;
+}
+
 static int
 xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 {
@@ -1257,26 +1321,33 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 	switch (attr) {
 	case hwmon_temp_input:
 		switch (channel) {
-		case CHANNEL_PKG:
-		case CHANNEL_VRAM:
-			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
-
-			/* HW register value is in degrees Celsius, convert to millidegrees. */
-			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
-			return 0;
 		case CHANNEL_MCTRL:
 			return get_mc_temp(hwmon, val);
 		case CHANNEL_PCIE:
 			return get_pcie_temp(hwmon, val);
+		case CHANNEL_PKG:
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
-			/*
-			 * This temperature format is 24 bit [31:8] signed integer and 8 bit
-			 * [7:0] fraction.
-			 */
-			*val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) *
-				(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
-				 MILLIDEGREE_PER_DEGREE;
+			if (!mmio_temp_valid(hwmon, reg_val)) {
+				drm_dbg(&hwmon->xe->drm,
+					"channel %d temperature invalid, val 0x%llx\n",
+					channel, reg_val);
+				return -ENXIO;
+			}
+			if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
+				return xe_hwmon_temperature_decode((u32)reg_val, val);
+			} else if (channel >= CHANNEL_VRAM_N) {
+				/*
+				 * This temperature format is 24 bit [31:8] signed integer and 8 bit
+				 * [7:0] fraction for platforms before CRI.
+				 */
+				*val = (s32)REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
+					(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
+					MILLIDEGREE_PER_DEGREE;
+			} else {
+				*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
+			}
 			return 0;
 		default:
 			return -EOPNOTSUPP;
-- 
2.25.1

[PATCH v12 12/16] drm/xe/hwmon: Update memory controller temperature offset for CRI

[Karthik Poosa]

On CRI the memory controller temperatures moved in the READ_THERMAL_DATA
output: they now occupy bytes 16..19 instead of starting at byte 2.

Read and average the CRI memory controller sensors from bytes 16..19,
keeping the existing byte 2..count-1 range for earlier platforms. Only
the group(s) covering the used bytes are fetched.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index a57b369215ee..bccae2ea91fd 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -109,6 +109,10 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* On CRI the memory controller temperatures are READ_THERMAL_DATA bytes 16..19. */
+#define CRI_TEMP_INDEX_MCTRL	16
+#define CRI_TEMP_MCTRL_COUNT	4
+
 /* Mailbox sentinel reported for an unavailable temperature sensor */
 #define TEMP_MBX_INVALID	0xFF
 
@@ -970,12 +974,20 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
-	int ret, i, count = 0;
+	int ret, i, start, end, count = 0;
 	s32 average = 0;
+	u32 data = 0;
 
-	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
-		u32 data = 0;
+	/* CRI relocated the memory controller temperatures to READ_THERMAL_DATA bytes 16..19. */
+	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
+		start = CRI_TEMP_INDEX_MCTRL;
+		end = CRI_TEMP_INDEX_MCTRL + CRI_TEMP_MCTRL_COUNT;
+	} else {
+		start = TEMP_INDEX_MCTRL;
+		end = hwmon->temp.count - 1;
+	}
 
+	for (i = start / sizeof(u32); i < DIV_ROUND_UP(end, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
 				    &data, NULL);
 		if (ret)
@@ -984,7 +996,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 		hwmon->temp.dword[i] = cpu_to_le32(data);
 	}
 
-	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
+	for (i = start; i < end; i++) {
 		if (!mbx_temp_valid(hwmon, hwmon->temp.value[i]))
 			continue;
 		average += mbx_temp_decode(hwmon->temp.value[i]);
-- 
2.25.1

[PATCH v12 13/16] drm/xe/hwmon: add PCIe temperature support for CRI

[Karthik Poosa]

Add the PCIe temperature sensor offset in READ_THERMAL_DATA for CRI.

Refactor PCIe temperature handling to use platform-specific sensor
indices and derive the mailbox group and byte offset from the sensor
index, eliminating special-case decoding logic.

v2:
 - Remove variables group and byte variables in get_pcie_temp().
 - Change xe_hwmon_pcie_temp_index() to take a const struct xe_hwmon *.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c     | 28 ++++++++++++++++++++--------
 drivers/gpu/drm/xe/xe_pcode_api.h |  2 --
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index bccae2ea91fd..3c1f6b70c82d 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -106,12 +106,15 @@ enum sensor_attr_power {
 
 #define PWR_ATTR_TO_STR(attr)	(((attr) == hwmon_power_max) ? "PL1" : "PL2")
 
-/* Index of memory controller in READ_THERMAL_DATA output */
+/* Sensor byte indices in READ_THERMAL_DATA output for BMG. */
 #define TEMP_INDEX_MCTRL	2
+#define TEMP_INDEX_PCIE		10
+#define BMG_G21_TEMP_INDEX_PCIE	8
 
-/* On CRI the memory controller temperatures are READ_THERMAL_DATA bytes 16..19. */
+/* Sensor byte indices in READ_THERMAL_DATA output for CRI. */
 #define CRI_TEMP_INDEX_MCTRL	16
 #define CRI_TEMP_MCTRL_COUNT	4
+#define CRI_TEMP_INDEX_PCIE	20
 
 /* Mailbox sentinel reported for an unavailable temperature sensor */
 #define TEMP_MBX_INVALID	0xFF
@@ -1016,21 +1019,30 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 	return 0;
 }
 
-static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
+static u8 xe_hwmon_pcie_temp_index(const struct xe_hwmon *hwmon)
+{
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
+		return CRI_TEMP_INDEX_PCIE;
+
+	if (hwmon->xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21)
+		return BMG_G21_TEMP_INDEX_PCIE;
+
+	return TEMP_INDEX_PCIE;
+}
+
+static int get_pcie_temp(const struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
 	u32 data = 0;
 	int ret;
 
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA,
-						  PCIE_SENSOR_GROUP_ID), &data, NULL);
+						  xe_hwmon_pcie_temp_index(hwmon) / sizeof(data)),
+						  &data, NULL);
 	if (ret)
 		return ret;
 
-	/* Sensor offset is different for G21 */
-	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
-		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
-
+	data >>= (xe_hwmon_pcie_temp_index(hwmon) % sizeof(data)) * BITS_PER_BYTE;
 	data = REG_FIELD_GET(TEMP_MASK, data);
 	if (!mbx_temp_valid(hwmon, data)) {
 		drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n");
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 94575c476e3d..00c4fc7d0124 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -58,8 +58,6 @@
 #define     READ_THERMAL_LIMITS			0x0
 #define     READ_THERMAL_CONFIG			0x1
 #define     READ_THERMAL_DATA			0x2
-#define       PCIE_SENSOR_GROUP_ID		0x2
-#define       PCIE_SENSOR_MASK			REG_GENMASK(31, 16)
 
 #define   PCODE_LATE_BINDING			0x5C
 #define     GET_CAPABILITY_STATUS		0x0
-- 
2.25.1

Re: [PATCH v12 13/16] drm/xe/hwmon: add PCIe temperature support for CRI

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] hwmon: pcie_temp_index() uses strict equality for CRI unlike get_mc_temp()
--

commit 4122768dbcd48bfed72f1531064229c2807857fd
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: add PCIe temperature support for CRI

This commit adds the PCIe temperature sensor offset in READ_THERMAL_DATA for
the Crescent Island (CRI) platform. It refactors PCIe temperature handling to
use platform-specific sensor indices rather than special-case decoding logic.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index bccae2ea91fdb..3c1f6b70c82dc 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
[ ... ]
> @@ -1016,21 +1019,30 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  	return 0;
>  }
>  
> -static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
> +static u8 xe_hwmon_pcie_temp_index(const struct xe_hwmon *hwmon)
> +{
> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
> +		return CRI_TEMP_INDEX_PCIE;

[Severity: Medium]
Will this strict equality check cause incorrect PCIe temperature readings on
future platforms that inherit this mailbox layout? 

In get_mc_temp(), the driver uses a greater-than-or-equal comparison for the
same platform:

	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
		start = CRI_TEMP_INDEX_MCTRL;

Does xe_hwmon_pcie_temp_index() need to use >= XE_CRESCENTISLAND to match
the behavior of get_mc_temp() and correctly support future platforms?

> +
> +	if (hwmon->xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21)
> +		return BMG_G21_TEMP_INDEX_PCIE;
> +
> +	return TEMP_INDEX_PCIE;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261013184939.694945-1-karthik.poosa@intel.com?part=13

[PATCH v12 14/16] drm/xe/hwmon: Simplify temperature channels config

[Karthik Poosa]

Replace the repeated temperature channels list with an indexed config
array. Use range designators for channels sharing the same attributes.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 104 ++++++----------------------------
 1 file changed, 17 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 3c1f6b70c82d..a54e3c52bd4a 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -803,94 +803,24 @@ static const struct attribute_group *hwmon_groups[] = {
 	NULL
 };
 
+static const u32 hwmon_temp_config[CHANNEL_MAX + 1] = {
+	[CHANNEL_CARD] = HWMON_T_LABEL,
+	[CHANNEL_PKG] = HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT |
+			 HWMON_T_LABEL | HWMON_T_MAX,
+	[CHANNEL_VRAM ... CHANNEL_PCIE] = HWMON_T_CRIT | HWMON_T_EMERGENCY |
+					 HWMON_T_INPUT | HWMON_T_LABEL,
+	[CHANNEL_VRAM_N ... CHANNEL_VRAM_N_MAX] = HWMON_T_CRIT | HWMON_T_EMERGENCY |
+							 HWMON_T_INPUT | HWMON_T_LABEL,
+	[CHANNEL_MAX] = 0, /* hwmon config terminator */
+};
+
+static const struct hwmon_channel_info hwmon_temp_info = {
+	.type = hwmon_temp,
+	.config = hwmon_temp_config,
+};
+
 static const struct hwmon_channel_info * const hwmon_info[] = {
-	HWMON_CHANNEL_INFO(temp,
-			   HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL |
-			   HWMON_T_MAX,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
-			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL),
+	&hwmon_temp_info,
 	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
 			   HWMON_P_CAP,
 			   HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP),
-- 
2.25.1

[PATCH v12 15/16] drm/xe: Validate thermal sensor count before reads

[Karthik Poosa]

Check that READ_THERMAL_CONFIG reports enough thermal entries for the
platform-specific MCTRL range and PCIe sensor index before reading
READ_THERMAL_DATA.

v2:
- Cap the memory controller sensor range at the PCIe sensor index so the
  PCIe temperature is not averaged into the memory controller temperature.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 44 ++++++++++++++++++++++++-----------
 1 file changed, 30 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index a54e3c52bd4a..d14c26e81167 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -904,6 +904,17 @@ static int mbx_temp_decode(u8 value)
 	return (value & TEMP_MBX_SIGN) ? -temp : temp;
 }
 
+static u8 xe_hwmon_pcie_temp_index(const struct xe_hwmon *hwmon)
+{
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
+		return CRI_TEMP_INDEX_PCIE;
+
+	if (hwmon->xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21)
+		return BMG_G21_TEMP_INDEX_PCIE;
+
+	return TEMP_INDEX_PCIE;
+}
+
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
@@ -917,7 +928,14 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 		end = CRI_TEMP_INDEX_MCTRL + CRI_TEMP_MCTRL_COUNT;
 	} else {
 		start = TEMP_INDEX_MCTRL;
-		end = hwmon->temp.count - 1;
+		end = min_t(int, hwmon->temp.count - 1, xe_hwmon_pcie_temp_index(hwmon));
+	}
+
+	if (end <= start || end > hwmon->temp.count) {
+		drm_warn(&hwmon->xe->drm,
+			 "memory controller range [%d, %d) is invalid for temperature count %d\n",
+			 start, end, hwmon->temp.count);
+		return -ENODATA;
 	}
 
 	for (i = start / sizeof(u32); i < DIV_ROUND_UP(end, sizeof(u32)); i++) {
@@ -949,30 +967,28 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 	return 0;
 }
 
-static u8 xe_hwmon_pcie_temp_index(const struct xe_hwmon *hwmon)
-{
-	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
-		return CRI_TEMP_INDEX_PCIE;
-
-	if (hwmon->xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21)
-		return BMG_G21_TEMP_INDEX_PCIE;
-
-	return TEMP_INDEX_PCIE;
-}
-
 static int get_pcie_temp(const struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
 	u32 data = 0;
+	int index;
 	int ret;
 
+	index = xe_hwmon_pcie_temp_index(hwmon);
+	if (index >= hwmon->temp.count) {
+		drm_warn(&hwmon->xe->drm,
+			 "PCIe temperature index %d out of range for temperature count %d\n",
+			 index, hwmon->temp.count);
+		return -ENODATA;
+	}
+
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA,
-						  xe_hwmon_pcie_temp_index(hwmon) / sizeof(data)),
+						  index / sizeof(data)),
 						  &data, NULL);
 	if (ret)
 		return ret;
 
-	data >>= (xe_hwmon_pcie_temp_index(hwmon) % sizeof(data)) * BITS_PER_BYTE;
+	data >>= (index % sizeof(data)) * BITS_PER_BYTE;
 	data = REG_FIELD_GET(TEMP_MASK, data);
 	if (!mbx_temp_valid(hwmon, data)) {
 		drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n");
-- 
2.25.1

[PATCH v12 16/16] drm/xe/hwmon: Propagate all hardware read errors

[Karthik Poosa]

Propagate all failures from pcode and mailbox accesses and fix missed
return-value checks found by Sashiko in
https://patchwork.freedesktop.org/patch/758843/?series=174898&rev=6.

Fixes: 7596d839f622 ("drm/xe/hwmon: Add support to manage power limits though mailbox")
Fixes: 0c5405d3aa4ad ("drm/xe/hwmon: Read energy status from PMT")
Fixes: 25e963a09e059 ("drm/xe/hwmon: Move card reactive critical power under channel card")
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 47 +++++++++++++++++++++--------------
 1 file changed, 29 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index d14c26e81167..e2be7a864d5f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -381,17 +381,20 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
  * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
  * clamped values when read.
  */
-static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *value)
+static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *value)
 {
 	u32 reg_val = 0;
 	struct xe_device *xe = hwmon->xe;
 	struct xe_reg rapl_limit, pkg_power_sku;
 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+	int ret = 0;
 
 	mutex_lock(&hwmon->hwmon_lock);
 
 	if (hwmon->xe->info.has_mbx_power_limits) {
-		xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
+		ret = xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
+		if (ret)
+			goto unlock;
 	} else {
 		rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);
 		pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
@@ -423,6 +426,7 @@ static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, u32 attr, int channe
 	}
 unlock:
 	mutex_unlock(&hwmon->hwmon_lock);
+	return ret;
 }
 
 static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channel, long value)
@@ -445,7 +449,9 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channe
 			ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
 			if (ret)
 				goto unlock;
-			xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
+			ret = xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
+			if (ret)
+				goto unlock;
 		} else {
 			reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);
 			reg_val = xe_mmio_read32(mmio, rapl_limit);
@@ -502,15 +508,18 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channe
 	return ret;
 }
 
-static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int channel,
-					  long *value)
+static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int channel,
+					 long *value)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	u32 reg_val;
+	int ret = 0;
 
 	if (hwmon->xe->info.has_mbx_power_limits) {
 		/* PL1 is rated max if supported. */
-		xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, &reg_val);
+		ret = xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, &reg_val);
+		if (ret)
+			return ret;
 	} else {
 		/*
 		 * This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check
@@ -524,6 +533,7 @@ static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int
 
 	reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
 	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
+	return ret;
 }
 
 /*
@@ -546,7 +556,7 @@ static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int
  * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
  * energyN_input overflows. This at 1000 W is an overflow duration of 278 years.
  */
-static void
+static int
 xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
@@ -557,7 +567,7 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy)
 	/* Energy is supported only for card and pkg */
 	if (channel > CHANNEL_PKG) {
 		*energy = 0;
-		return;
+		return 0;
 	}
 
 	if (hwmon->xe->info.platform == XE_BATTLEMAGE) {
@@ -569,7 +579,7 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy)
 		if (ret != sizeof(pmt_val)) {
 			drm_warn(&hwmon->xe->drm, "energy read from pmt failed, ret %d\n", ret);
 			*energy = 0;
-			return;
+			return ret < 0 ? ret : -EIO;
 		}
 
 		if (channel == CHANNEL_PKG)
@@ -586,6 +596,7 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy)
 
 	*energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
 				  hwmon->scl_shift_energy);
+	return 0;
 }
 
 static ssize_t
@@ -611,7 +622,8 @@ xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *at
 			drm_err(&hwmon->xe->drm,
 				"power interval read fail, ch %d, attr %d, val 0x%08x, ret %d\n",
 				channel, power_attr, reg_val, ret);
-			reg_val = 0;
+			mutex_unlock(&hwmon->hwmon_lock);
+			return ret;
 		}
 	} else {
 		reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT,
@@ -1399,7 +1411,8 @@ xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		}
 	case hwmon_power_crit:
 		if (channel == CHANNEL_CARD) {
-			xe_hwmon_pcode_read_i1(hwmon, &uval);
+			if (xe_hwmon_pcode_read_i1(hwmon, &uval))
+				return 0;
 			return (uval & POWER_SETUP_I1_WATTS) ? 0644 : 0;
 		}
 		break;
@@ -1418,7 +1431,8 @@ xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 			}
 		}
 		if ((!(uval & PWR_LIM_EN)) && channel == CHANNEL_CARD) {
-			xe_hwmon_pcode_read_i1(hwmon, &uval);
+			if (xe_hwmon_pcode_read_i1(hwmon, &uval))
+				return 0;
 			return (uval & POWER_SETUP_I1_WATTS) ? 0444 : 0;
 		}
 		return (uval) ? 0444 : 0;
@@ -1434,11 +1448,9 @@ xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 	switch (attr) {
 	case hwmon_power_max:
 	case hwmon_power_cap:
-		xe_hwmon_power_max_read(hwmon, attr, channel, val);
-		return 0;
+		return xe_hwmon_power_max_read(hwmon, attr, channel, val);
 	case hwmon_power_rated_max:
-		xe_hwmon_power_rated_max_read(hwmon, attr, channel, val);
-		return 0;
+		return xe_hwmon_power_rated_max_read(hwmon, attr, channel, val);
 	case hwmon_power_crit:
 		return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER);
 	default:
@@ -1555,8 +1567,7 @@ xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 {
 	switch (attr) {
 	case hwmon_energy_input:
-		xe_hwmon_energy_get(hwmon, channel, val);
-		return 0;
+		return xe_hwmon_energy_get(hwmon, channel, val);
 	default:
 		return -EOPNOTSUPP;
 	}
-- 
2.25.1

✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox

[Patchwork]

== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox
URL   : https://patchwork.freedesktop.org/series/176071/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[18:58:26] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:58:30] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:58:51] Starting KUnit Kernel (1/1)...
[18:58:51] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:58:51] ================= gpu_buddy (14 subtests) ==================
[18:58:51] [PASSED] gpu_test_buddy_alloc_limit
[18:58:51] [PASSED] gpu_test_buddy_alloc_optimistic
[18:58:51] [PASSED] gpu_test_buddy_alloc_pessimistic
[18:58:51] [PASSED] gpu_test_buddy_alloc_pathological
[18:58:51] [PASSED] gpu_test_buddy_alloc_contiguous
[18:58:51] [PASSED] gpu_test_buddy_alloc_clear
[18:58:51] [PASSED] gpu_test_buddy_alloc_range
[18:58:51] [PASSED] gpu_test_buddy_alloc_range_bias
[18:58:52] [PASSED] gpu_test_buddy_fragmentation_performance
[18:58:53] [PASSED] gpu_test_buddy_dirty_tracker_performance
[18:58:53] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[18:58:53] [PASSED] gpu_test_buddy_offset_aligned_allocation
[18:58:53] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[18:58:53] [PASSED] gpu_test_buddy_addr_to_block
[18:58:53] ==================== [PASSED] gpu_buddy ====================
[18:58:53] ============================================================
[18:58:53] Testing complete. Ran 14 tests: passed: 14
[18:58:53] Elapsed time: 26.928s total, 4.463s configuring, 20.547s building, 1.851s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[18:58:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:58:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:59:29] Starting KUnit Kernel (1/1)...
[18:59:29] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:59:29] ================== guc_buf (11 subtests) ===================
[18:59:29] [PASSED] test_smallest
[18:59:29] [PASSED] test_largest
[18:59:29] [PASSED] test_granular
[18:59:29] [PASSED] test_unique
[18:59:29] [PASSED] test_overlap
[18:59:29] [PASSED] test_reusable
[18:59:29] [PASSED] test_too_big
[18:59:29] [PASSED] test_flush
[18:59:29] [PASSED] test_lookup
[18:59:29] [PASSED] test_data
[18:59:29] [PASSED] test_class
[18:59:29] ===================== [PASSED] guc_buf =====================
[18:59:29] =================== guc_dbm (7 subtests) ===================
[18:59:29] [PASSED] test_empty
[18:59:29] [PASSED] test_default
[18:59:29] ======================== test_size  ========================
[18:59:29] [PASSED] 4
[18:59:29] [PASSED] 8
[18:59:29] [PASSED] 32
[18:59:29] [PASSED] 256
[18:59:29] ==================== [PASSED] test_size ====================
[18:59:29] ======================= test_reuse  ========================
[18:59:29] [PASSED] 4
[18:59:29] [PASSED] 8
[18:59:29] [PASSED] 32
[18:59:29] [PASSED] 256
[18:59:29] =================== [PASSED] test_reuse ====================
[18:59:29] =================== test_range_overlap  ====================
[18:59:29] [PASSED] 4
[18:59:29] [PASSED] 8
[18:59:29] [PASSED] 32
[18:59:29] [PASSED] 256
[18:59:29] =============== [PASSED] test_range_overlap ================
[18:59:29] =================== test_range_compact  ====================
[18:59:29] [PASSED] 4
[18:59:29] [PASSED] 8
[18:59:29] [PASSED] 32
[18:59:29] [PASSED] 256
[18:59:29] =============== [PASSED] test_range_compact ================
[18:59:29] ==================== test_range_spare  =====================
[18:59:29] [PASSED] 4
[18:59:29] [PASSED] 8
[18:59:29] [PASSED] 32
[18:59:29] [PASSED] 256
[18:59:29] ================ [PASSED] test_range_spare =================
[18:59:29] ===================== [PASSED] guc_dbm =====================
[18:59:29] =================== guc_idm (6 subtests) ===================
[18:59:29] [PASSED] bad_init
[18:59:29] [PASSED] no_init
[18:59:29] [PASSED] init_fini
[18:59:29] [PASSED] check_used
[18:59:29] [PASSED] check_quota
[18:59:29] [PASSED] check_all
[18:59:29] ===================== [PASSED] guc_idm =====================
[18:59:29] ============== guc_klv_helpers (13 subtests) ===============
[18:59:29] [PASSED] test_count
[18:59:29] [PASSED] test_encode_u32
[18:59:29] [PASSED] test_encode_u64
[18:59:29] [PASSED] test_encode_string
[18:59:29] [PASSED] test_encode_object_raw
[18:59:29] [PASSED] test_encode_object_klv
[18:59:29] [PASSED] test_encode_object_nested
[18:59:29] [PASSED] test_encode_object_basic
[18:59:29] ===================== test_decode_u16  =====================
[18:59:29] [PASSED] empty
[18:59:29] [PASSED] valid
[18:59:29] [PASSED] max
[18:59:29] [PASSED] big
[18:59:29] [PASSED] long
[18:59:29] ================= [PASSED] test_decode_u16 =================
[18:59:29] ===================== test_decode_u32  =====================
[18:59:29] [PASSED] empty
[18:59:29] [PASSED] valid
[18:59:29] [PASSED] max
[18:59:29] [PASSED] long
[18:59:29] ================= [PASSED] test_decode_u32 =================
[18:59:29] ===================== test_decode_u64  =====================
[18:59:29] [PASSED] empty
[18:59:29] [PASSED] short
[18:59:29] [PASSED] valid
[18:59:29] [PASSED] max
[18:59:29] [PASSED] long
[18:59:29] ================= [PASSED] test_decode_u64 =================
[18:59:29] ===================== test_decode_str  =====================
[18:59:29] [PASSED] empty
[18:59:29] [PASSED] one
[18:59:29] [PASSED] one_trash
[18:59:29] [PASSED] two
[18:59:29] [PASSED] two_trash
[18:59:29] [PASSED] three
[18:59:29] [PASSED] dword
[18:59:29] [PASSED] four
[18:59:29] [PASSED] five
[18:59:29] [PASSED] six
[18:59:29] [PASSED] seven
[18:59:29] [PASSED] qword
[18:59:29] ================= [PASSED] test_decode_str =================
[18:59:29] [PASSED] test_print
[18:59:29] ================= [PASSED] guc_klv_helpers =================
[18:59:29] =================== xe_log (4 subtests) ====================
[18:59:29] [PASSED] demo_cper
[18:59:29] [PASSED] demo_dmesg
[18:59:29] ======================= test_dmesg  ========================
[18:59:29] [PASSED] test_fatal
[18:59:29] [PASSED] test_fatal_tile
[18:59:29] [PASSED] test_fatal_gt
[18:59:29] [PASSED] test_fatal_comp
[18:59:29] [PASSED] test_fatal_comp_tile
[18:59:29] [PASSED] test_fatal_comp_gt
[18:59:29] [PASSED] test_fatal_all
[18:59:29] [PASSED] test_recoverable
[18:59:29] [PASSED] test_recoverable_tile
[18:59:29] [PASSED] test_recoverable_gt
[18:59:29] [PASSED] test_recoverable_comp
[18:59:29] [PASSED] test_recoverable_comp_tile
[18:59:29] [PASSED] test_recoverable_comp_gt
[18:59:29] [PASSED] test_recoverable_all
[18:59:29] [PASSED] test_info
[18:59:29] [PASSED] test_info_tile
[18:59:29] [PASSED] test_info_gt
[18:59:29] [PASSED] test_info_err
[18:59:29] [PASSED] test_info_comp
[18:59:29] [PASSED] test_info_comp_tile
[18:59:29] [PASSED] test_info_comp_gt
[18:59:29] [PASSED] test_info_all
[18:59:29] [PASSED] test_hw_fatal
[18:59:29] [PASSED] test_hw_recoverable
[18:59:29] [PASSED] test_hw_corrected
[18:59:29] [PASSED] test_hw_informational
[18:59:29] =================== [PASSED] test_dmesg ====================
[18:59:29] ====================== test_invalid  =======================
[18:59:29] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[18:59:29] ================== [SKIPPED] test_invalid ==================
[18:59:29] ===================== [PASSED] xe_log ======================
[18:59:29] ================== no_relay (3 subtests) ===================
[18:59:29] [PASSED] xe_drops_guc2pf_if_not_ready
[18:59:29] [PASSED] xe_drops_guc2vf_if_not_ready
[18:59:29] [PASSED] xe_rejects_send_if_not_ready
[18:59:29] ==================== [PASSED] no_relay =====================
[18:59:29] ================== pf_relay (14 subtests) ==================
[18:59:29] [PASSED] pf_rejects_guc2pf_too_short
[18:59:29] [PASSED] pf_rejects_guc2pf_too_long
[18:59:29] [PASSED] pf_rejects_guc2pf_no_payload
[18:59:29] [PASSED] pf_fails_no_payload
[18:59:29] [PASSED] pf_fails_bad_origin
[18:59:29] [PASSED] pf_fails_bad_type
[18:59:29] [PASSED] pf_txn_reports_error
[18:59:29] [PASSED] pf_txn_sends_pf2guc
[18:59:29] [PASSED] pf_sends_pf2guc
[18:59:29] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:59:29] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:59:29] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:59:29] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:59:29] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[18:59:29] ==================== [PASSED] pf_relay =====================
[18:59:29] ================== vf_relay (3 subtests) ===================
[18:59:29] [PASSED] vf_rejects_guc2vf_too_short
[18:59:29] [PASSED] vf_rejects_guc2vf_too_long
[18:59:29] [PASSED] vf_rejects_guc2vf_no_payload
[18:59:29] ==================== [PASSED] vf_relay =====================
[18:59:29] ================ pf_gt_config (9 subtests) =================
[18:59:29] [PASSED] fair_contexts_1vf
[18:59:29] [PASSED] fair_doorbells_1vf
[18:59:29] [PASSED] fair_ggtt_1vf
[18:59:29] ====================== fair_vram_1vf  ======================
[18:59:29] [PASSED] 3.50 GiB
[18:59:29] [PASSED] 11.5 GiB
[18:59:29] [PASSED] 15.5 GiB
[18:59:29] [PASSED] 31.5 GiB
[18:59:29] [PASSED] 63.5 GiB
[18:59:29] [PASSED] 1.91 GiB
[18:59:29] ================== [PASSED] fair_vram_1vf ==================
[18:59:29] ================ fair_vram_1vf_admin_only  =================
[18:59:29] [PASSED] 3.50 GiB
[18:59:29] [PASSED] 11.5 GiB
[18:59:29] [PASSED] 15.5 GiB
[18:59:29] [PASSED] 31.5 GiB
[18:59:29] [PASSED] 63.5 GiB
[18:59:29] [PASSED] 1.91 GiB
[18:59:29] ============ [PASSED] fair_vram_1vf_admin_only =============
[18:59:29] ====================== fair_contexts  ======================
[18:59:29] [PASSED] 1 VF
[18:59:29] [PASSED] 2 VFs
[18:59:29] [PASSED] 3 VFs
[18:59:29] [PASSED] 4 VFs
[18:59:29] [PASSED] 5 VFs
[18:59:29] [PASSED] 6 VFs
[18:59:29] [PASSED] 7 VFs
[18:59:29] [PASSED] 8 VFs
[18:59:29] [PASSED] 9 VFs
[18:59:29] [PASSED] 10 VFs
[18:59:29] [PASSED] 11 VFs
[18:59:29] [PASSED] 12 VFs
[18:59:29] [PASSED] 13 VFs
[18:59:29] [PASSED] 14 VFs
[18:59:29] [PASSED] 15 VFs
[18:59:29] [PASSED] 16 VFs
[18:59:29] [PASSED] 17 VFs
[18:59:29] [PASSED] 18 VFs
[18:59:29] [PASSED] 19 VFs
[18:59:29] [PASSED] 20 VFs
[18:59:29] [PASSED] 21 VFs
[18:59:29] [PASSED] 22 VFs
[18:59:29] [PASSED] 23 VFs
[18:59:29] [PASSED] 24 VFs
[18:59:29] [PASSED] 25 VFs
[18:59:29] [PASSED] 26 VFs
[18:59:29] [PASSED] 27 VFs
[18:59:29] [PASSED] 28 VFs
[18:59:29] [PASSED] 29 VFs
[18:59:29] [PASSED] 30 VFs
[18:59:29] [PASSED] 31 VFs
[18:59:29] [PASSED] 32 VFs
[18:59:29] [PASSED] 33 VFs
[18:59:29] [PASSED] 34 VFs
[18:59:29] [PASSED] 35 VFs
[18:59:29] [PASSED] 36 VFs
[18:59:29] [PASSED] 37 VFs
[18:59:29] [PASSED] 38 VFs
[18:59:29] [PASSED] 39 VFs
[18:59:29] [PASSED] 40 VFs
[18:59:29] [PASSED] 41 VFs
[18:59:29] [PASSED] 42 VFs
[18:59:29] [PASSED] 43 VFs
[18:59:29] [PASSED] 44 VFs
[18:59:29] [PASSED] 45 VFs
[18:59:29] [PASSED] 46 VFs
[18:59:29] [PASSED] 47 VFs
[18:59:29] [PASSED] 48 VFs
[18:59:29] [PASSED] 49 VFs
[18:59:29] [PASSED] 50 VFs
[18:59:29] [PASSED] 51 VFs
[18:59:29] [PASSED] 52 VFs
[18:59:29] [PASSED] 53 VFs
[18:59:29] [PASSED] 54 VFs
[18:59:29] [PASSED] 55 VFs
[18:59:29] [PASSED] 56 VFs
[18:59:29] [PASSED] 57 VFs
[18:59:29] [PASSED] 58 VFs
[18:59:29] [PASSED] 59 VFs
[18:59:29] [PASSED] 60 VFs
[18:59:29] [PASSED] 61 VFs
[18:59:29] [PASSED] 62 VFs
[18:59:29] [PASSED] 63 VFs
[18:59:29] ================== [PASSED] fair_contexts ==================
[18:59:29] ===================== fair_doorbells  ======================
[18:59:29] [PASSED] 1 VF
[18:59:29] [PASSED] 2 VFs
[18:59:29] [PASSED] 3 VFs
[18:59:29] [PASSED] 4 VFs
[18:59:29] [PASSED] 5 VFs
[18:59:29] [PASSED] 6 VFs
[18:59:29] [PASSED] 7 VFs
[18:59:29] [PASSED] 8 VFs
[18:59:29] [PASSED] 9 VFs
[18:59:29] [PASSED] 10 VFs
[18:59:29] [PASSED] 11 VFs
[18:59:29] [PASSED] 12 VFs
[18:59:29] [PASSED] 13 VFs
[18:59:29] [PASSED] 14 VFs
[18:59:29] [PASSED] 15 VFs
[18:59:29] [PASSED] 16 VFs
[18:59:29] [PASSED] 17 VFs
[18:59:29] [PASSED] 18 VFs
[18:59:29] [PASSED] 19 VFs
[18:59:29] [PASSED] 20 VFs
[18:59:29] [PASSED] 21 VFs
[18:59:29] [PASSED] 22 VFs
[18:59:29] [PASSED] 23 VFs
[18:59:29] [PASSED] 24 VFs
[18:59:29] [PASSED] 25 VFs
[18:59:29] [PASSED] 26 VFs
[18:59:29] [PASSED] 27 VFs
[18:59:29] [PASSED] 28 VFs
[18:59:29] [PASSED] 29 VFs
[18:59:29] [PASSED] 30 VFs
[18:59:29] [PASSED] 31 VFs
[18:59:29] [PASSED] 32 VFs
[18:59:29] [PASSED] 33 VFs
[18:59:29] [PASSED] 34 VFs
[18:59:29] [PASSED] 35 VFs
[18:59:29] [PASSED] 36 VFs
[18:59:29] [PASSED] 37 VFs
[18:59:29] [PASSED] 38 VFs
[18:59:29] [PASSED] 39 VFs
[18:59:29] [PASSED] 40 VFs
[18:59:29] [PASSED] 41 VFs
[18:59:29] [PASSED] 42 VFs
[18:59:29] [PASSED] 43 VFs
[18:59:29] [PASSED] 44 VFs
[18:59:29] [PASSED] 45 VFs
[18:59:29] [PASSED] 46 VFs
[18:59:29] [PASSED] 47 VFs
[18:59:29] [PASSED] 48 VFs
[18:59:29] [PASSED] 49 VFs
[18:59:29] [PASSED] 50 VFs
[18:59:29] [PASSED] 51 VFs
[18:59:29] [PASSED] 52 VFs
[18:59:29] [PASSED] 53 VFs
[18:59:29] [PASSED] 54 VFs
[18:59:29] [PASSED] 55 VFs
[18:59:29] [PASSED] 56 VFs
[18:59:29] [PASSED] 57 VFs
[18:59:29] [PASSED] 58 VFs
[18:59:29] [PASSED] 59 VFs
[18:59:29] [PASSED] 60 VFs
[18:59:29] [PASSED] 61 VFs
[18:59:29] [PASSED] 62 VFs
[18:59:29] [PASSED] 63 VFs
[18:59:29] ================= [PASSED] fair_doorbells ==================
[18:59:29] ======================== fair_ggtt  ========================
[18:59:29] [PASSED] 1 VF
[18:59:29] [PASSED] 2 VFs
[18:59:29] [PASSED] 3 VFs
[18:59:29] [PASSED] 4 VFs
[18:59:29] [PASSED] 5 VFs
[18:59:29] [PASSED] 6 VFs
[18:59:29] [PASSED] 7 VFs
[18:59:29] [PASSED] 8 VFs
[18:59:29] [PASSED] 9 VFs
[18:59:29] [PASSED] 10 VFs
[18:59:29] [PASSED] 11 VFs
[18:59:29] [PASSED] 12 VFs
[18:59:29] [PASSED] 13 VFs
[18:59:29] [PASSED] 14 VFs
[18:59:29] [PASSED] 15 VFs
[18:59:29] [PASSED] 16 VFs
[18:59:29] [PASSED] 17 VFs
[18:59:29] [PASSED] 18 VFs
[18:59:29] [PASSED] 19 VFs
[18:59:29] [PASSED] 20 VFs
[18:59:29] [PASSED] 21 VFs
[18:59:29] [PASSED] 22 VFs
[18:59:29] [PASSED] 23 VFs
[18:59:29] [PASSED] 24 VFs
[18:59:29] [PASSED] 25 VFs
[18:59:29] [PASSED] 26 VFs
[18:59:29] [PASSED] 27 VFs
[18:59:29] [PASSED] 28 VFs
[18:59:29] [PASSED] 29 VFs
[18:59:29] [PASSED] 30 VFs
[18:59:29] [PASSED] 31 VFs
[18:59:29] [PASSED] 32 VFs
[18:59:29] [PASSED] 33 VFs
[18:59:29] [PASSED] 34 VFs
[18:59:29] [PASSED] 35 VFs
[18:59:29] [PASSED] 36 VFs
[18:59:29] [PASSED] 37 VFs
[18:59:29] [PASSED] 38 VFs
[18:59:29] [PASSED] 39 VFs
[18:59:29] [PASSED] 40 VFs
[18:59:29] [PASSED] 41 VFs
[18:59:29] [PASSED] 42 VFs
[18:59:29] [PASSED] 43 VFs
[18:59:29] [PASSED] 44 VFs
[18:59:29] [PASSED] 45 VFs
[18:59:29] [PASSED] 46 VFs
[18:59:29] [PASSED] 47 VFs
[18:59:29] [PASSED] 48 VFs
[18:59:29] [PASSED] 49 VFs
[18:59:29] [PASSED] 50 VFs
[18:59:29] [PASSED] 51 VFs
[18:59:29] [PASSED] 52 VFs
[18:59:29] [PASSED] 53 VFs
[18:59:29] [PASSED] 54 VFs
[18:59:29] [PASSED] 55 VFs
[18:59:29] [PASSED] 56 VFs
[18:59:29] [PASSED] 57 VFs
[18:59:29] [PASSED] 58 VFs
[18:59:29] [PASSED] 59 VFs
[18:59:29] [PASSED] 60 VFs
[18:59:29] [PASSED] 61 VFs
[18:59:29] [PASSED] 62 VFs
[18:59:29] [PASSED] 63 VFs
[18:59:29] ==================== [PASSED] fair_ggtt ====================
[18:59:29] ======================== fair_vram  ========================
[18:59:29] [PASSED] 1 VF
[18:59:29] [PASSED] 2 VFs
[18:59:29] [PASSED] 3 VFs
[18:59:29] [PASSED] 4 VFs
[18:59:29] [PASSED] 5 VFs
[18:59:29] [PASSED] 6 VFs
[18:59:29] [PASSED] 7 VFs
[18:59:29] [PASSED] 8 VFs
[18:59:29] [PASSED] 9 VFs
[18:59:29] [PASSED] 10 VFs
[18:59:29] [PASSED] 11 VFs
[18:59:29] [PASSED] 12 VFs
[18:59:29] [PASSED] 13 VFs
[18:59:29] [PASSED] 14 VFs
[18:59:29] [PASSED] 15 VFs
[18:59:29] [PASSED] 16 VFs
[18:59:29] [PASSED] 17 VFs
[18:59:29] [PASSED] 18 VFs
[18:59:29] [PASSED] 19 VFs
[18:59:29] [PASSED] 20 VFs
[18:59:29] [PASSED] 21 VFs
[18:59:29] [PASSED] 22 VFs
[18:59:29] [PASSED] 23 VFs
[18:59:29] [PASSED] 24 VFs
[18:59:29] [PASSED] 25 VFs
[18:59:29] [PASSED] 26 VFs
[18:59:29] [PASSED] 27 VFs
[18:59:29] [PASSED] 28 VFs
[18:59:29] [PASSED] 29 VFs
[18:59:29] [PASSED] 30 VFs
[18:59:29] [PASSED] 31 VFs
[18:59:29] [PASSED] 32 VFs
[18:59:29] [PASSED] 33 VFs
[18:59:29] [PASSED] 34 VFs
[18:59:29] [PASSED] 35 VFs
[18:59:29] [PASSED] 36 VFs
[18:59:29] [PASSED] 37 VFs
[18:59:29] [PASSED] 38 VFs
[18:59:29] [PASSED] 39 VFs
[18:59:29] [PASSED] 40 VFs
[18:59:29] [PASSED] 41 VFs
[18:59:29] [PASSED] 42 VFs
[18:59:29] [PASSED] 43 VFs
[18:59:29] [PASSED] 44 VFs
[18:59:29] [PASSED] 45 VFs
[18:59:29] [PASSED] 46 VFs
[18:59:29] [PASSED] 47 VFs
[18:59:29] [PASSED] 48 VFs
[18:59:29] [PASSED] 49 VFs
[18:59:29] [PASSED] 50 VFs
[18:59:29] [PASSED] 51 VFs
[18:59:29] [PASSED] 52 VFs
[18:59:29] [PASSED] 53 VFs
[18:59:29] [PASSED] 54 VFs
[18:59:29] [PASSED] 55 VFs
[18:59:29] [PASSED] 56 VFs
[18:59:29] [PASSED] 57 VFs
[18:59:29] [PASSED] 58 VFs
[18:59:29] [PASSED] 59 VFs
[18:59:29] [PASSED] 60 VFs
[18:59:29] [PASSED] 61 VFs
[18:59:29] [PASSED] 62 VFs
[18:59:29] [PASSED] 63 VFs
[18:59:29] ==================== [PASSED] fair_vram ====================
[18:59:29] ================== [PASSED] pf_gt_config ===================
[18:59:29] ===================== lmtt (1 subtest) =====================
[18:59:29] ======================== test_ops  =========================
[18:59:29] [PASSED] 2-level
[18:59:29] [PASSED] multi-level
[18:59:29] ==================== [PASSED] test_ops =====================
[18:59:29] ====================== [PASSED] lmtt =======================
[18:59:29] ================= sriov_packet (1 subtest) =================
[18:59:29] [PASSED] test_descriptor_init
[18:59:29] ================== [PASSED] sriov_packet ===================
[18:59:29] ================= pf_service (11 subtests) =================
[18:59:29] [PASSED] pf_negotiate_any
[18:59:29] [PASSED] pf_negotiate_base_match
[18:59:29] [PASSED] pf_negotiate_base_newer
[18:59:29] [PASSED] pf_negotiate_base_next
[18:59:29] [SKIPPED] pf_negotiate_base_older (no older minor)
[18:59:29] [PASSED] pf_negotiate_base_prev
[18:59:29] [PASSED] pf_negotiate_latest_match
[18:59:29] [PASSED] pf_negotiate_latest_newer
[18:59:29] [PASSED] pf_negotiate_latest_next
[18:59:29] [SKIPPED] pf_negotiate_latest_older (no older minor)
[18:59:29] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[18:59:29] =================== [PASSED] pf_service ====================
[18:59:29] ================= xe_guc_g2g (2 subtests) ==================
[18:59:29] ============== xe_live_guc_g2g_kunit_default  ==============
[18:59:29] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[18:59:29] ============== xe_live_guc_g2g_kunit_allmem  ===============
[18:59:29] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[18:59:29] =================== [SKIPPED] xe_guc_g2g ===================
[18:59:29] =================== xe_mocs (2 subtests) ===================
[18:59:29] ================ xe_live_mocs_kernel_kunit  ================
[18:59:29] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[18:59:29] ================ xe_live_mocs_reset_kunit  =================
[18:59:29] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[18:59:29] ==================== [SKIPPED] xe_mocs =====================
[18:59:29] ================= xe_migrate (2 subtests) ==================
[18:59:29] ================= xe_migrate_sanity_kunit  =================
[18:59:29] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[18:59:29] ================== xe_validate_ccs_kunit  ==================
[18:59:29] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[18:59:29] =================== [SKIPPED] xe_migrate ===================
[18:59:29] ================== xe_dma_buf (1 subtest) ==================
[18:59:29] ==================== xe_dma_buf_kunit  =====================
[18:59:29] ================ [SKIPPED] xe_dma_buf_kunit ================
[18:59:29] =================== [SKIPPED] xe_dma_buf ===================
[18:59:29] ================= xe_bo_shrink (1 subtest) =================
[18:59:29] =================== xe_bo_shrink_kunit  ====================
[18:59:29] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[18:59:29] ================== [SKIPPED] xe_bo_shrink ==================
[18:59:29] ==================== xe_bo (2 subtests) ====================
[18:59:29] ================== xe_ccs_migrate_kunit  ===================
[18:59:29] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[18:59:29] ==================== xe_bo_evict_kunit  ====================
[18:59:29] =============== [SKIPPED] xe_bo_evict_kunit ================
[18:59:29] ===================== [SKIPPED] xe_bo ======================
[18:59:29] =================== xe_any (9 subtests) ====================
[18:59:29] [PASSED] test_to_xe
[18:59:29] [PASSED] test_to_dev
[18:59:29] [PASSED] test_to_pdev
[18:59:29] [PASSED] test_to_drm
[18:59:29] [PASSED] test_if_pdev
[18:59:29] [PASSED] test_if_xe
[18:59:29] [PASSED] test_if_tile
[18:59:29] [PASSED] test_if_gt
[18:59:29] [PASSED] test_to_id
[18:59:29] ===================== [PASSED] xe_any ======================
[18:59:29] ==================== args (13 subtests) ====================
[18:59:29] [PASSED] count_args_test
[18:59:29] [PASSED] call_args_example
[18:59:29] [PASSED] call_args_test
[18:59:29] [PASSED] drop_first_arg_example
[18:59:29] [PASSED] drop_first_arg_test
[18:59:29] [PASSED] first_arg_example
[18:59:29] [PASSED] first_arg_test
[18:59:29] [PASSED] last_arg_example
[18:59:29] [PASSED] last_arg_test
[18:59:29] [PASSED] pick_arg_example
[18:59:29] [PASSED] if_args_example
[18:59:29] [PASSED] if_args_test
[18:59:29] [PASSED] sep_comma_example
[18:59:29] ====================== [PASSED] args =======================
[18:59:29] =================== xe_pci (3 subtests) ====================
[18:59:29] ==================== check_graphics_ip  ====================
[18:59:29] [PASSED] 12.00 Xe_LP
[18:59:29] [PASSED] 12.10 Xe_LP+
[18:59:29] [PASSED] 12.55 Xe_HPG
[18:59:29] [PASSED] 12.60 Xe_HPC
[18:59:29] [PASSED] 12.70 Xe_LPG
[18:59:29] [PASSED] 12.71 Xe_LPG
[18:59:29] [PASSED] 12.74 Xe_LPG+
[18:59:29] [PASSED] 20.01 Xe2_HPG
[18:59:29] [PASSED] 20.02 Xe2_HPG
[18:59:29] [PASSED] 20.04 Xe2_LPG
[18:59:29] [PASSED] 30.00 Xe3_LPG
[18:59:29] [PASSED] 30.01 Xe3_LPG
[18:59:29] [PASSED] 30.03 Xe3_LPG
[18:59:29] [PASSED] 30.04 Xe3_LPG
[18:59:29] [PASSED] 30.05 Xe3_LPG
[18:59:29] [PASSED] 35.10 Xe3p_LPG
[18:59:29] [PASSED] 35.11 Xe3p_XPC
[18:59:29] ================ [PASSED] check_graphics_ip ================
[18:59:29] ===================== check_media_ip  ======================
[18:59:29] [PASSED] 12.00 Xe_M
[18:59:29] [PASSED] 12.55 Xe_HPM
[18:59:29] [PASSED] 13.00 Xe_LPM+
[18:59:29] [PASSED] 13.01 Xe2_HPM
[18:59:29] [PASSED] 20.00 Xe2_LPM
[18:59:29] [PASSED] 30.00 Xe3_LPM
[18:59:29] [PASSED] 30.02 Xe3_LPM
[18:59:29] [PASSED] 35.00 Xe3p_LPM
[18:59:29] [PASSED] 35.03 Xe3p_HPM
[18:59:29] ================= [PASSED] check_media_ip ==================
[18:59:29] =================== check_platform_desc  ===================
[18:59:29] [PASSED] 0x9A60 (TIGERLAKE)
[18:59:29] [PASSED] 0x9A68 (TIGERLAKE)
[18:59:29] [PASSED] 0x9A70 (TIGERLAKE)
[18:59:29] [PASSED] 0x9A40 (TIGERLAKE)
[18:59:29] [PASSED] 0x9A49 (TIGERLAKE)
[18:59:29] [PASSED] 0x9A59 (TIGERLAKE)
[18:59:29] [PASSED] 0x9A78 (TIGERLAKE)
[18:59:29] [PASSED] 0x9AC0 (TIGERLAKE)
[18:59:29] [PASSED] 0x9AC9 (TIGERLAKE)
[18:59:29] [PASSED] 0x9AD9 (TIGERLAKE)
[18:59:29] [PASSED] 0x9AF8 (TIGERLAKE)
[18:59:29] [PASSED] 0x4C80 (ROCKETLAKE)
[18:59:29] [PASSED] 0x4C8A (ROCKETLAKE)
[18:59:29] [PASSED] 0x4C8B (ROCKETLAKE)
[18:59:29] [PASSED] 0x4C8C (ROCKETLAKE)
[18:59:29] [PASSED] 0x4C90 (ROCKETLAKE)
[18:59:29] [PASSED] 0x4C9A (ROCKETLAKE)
[18:59:29] [PASSED] 0x4680 (ALDERLAKE_S)
[18:59:29] [PASSED] 0x4682 (ALDERLAKE_S)
[18:59:29] [PASSED] 0x4688 (ALDERLAKE_S)
[18:59:29] [PASSED] 0x468A (ALDERLAKE_S)
[18:59:29] [PASSED] 0x468B (ALDERLAKE_S)
[18:59:29] [PASSED] 0x4690 (ALDERLAKE_S)
[18:59:29] [PASSED] 0x4692 (ALDERLAKE_S)
[18:59:29] [PASSED] 0x4693 (ALDERLAKE_S)
[18:59:29] [PASSED] 0x46A0 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46A1 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46A2 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46A3 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46A6 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46A8 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46AA (ALDERLAKE_P)
[18:59:29] [PASSED] 0x462A (ALDERLAKE_P)
[18:59:29] [PASSED] 0x4626 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x4628 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46B0 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46B1 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46B2 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46B3 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46C0 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46C1 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46C2 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46C3 (ALDERLAKE_P)
[18:59:29] [PASSED] 0x46D0 (ALDERLAKE_N)
[18:59:29] [PASSED] 0x46D1 (ALDERLAKE_N)
[18:59:29] [PASSED] 0x46D2 (ALDERLAKE_N)
[18:59:29] [PASSED] 0x46D3 (ALDERLAKE_N)
[18:59:29] [PASSED] 0x46D4 (ALDERLAKE_N)
[18:59:29] [PASSED] 0xA721 (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA7A1 (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA7A9 (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA7AC (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA7AD (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA720 (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA7A0 (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA7A8 (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA7AA (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA7AB (ALDERLAKE_P)
[18:59:29] [PASSED] 0xA780 (ALDERLAKE_S)
[18:59:29] [PASSED] 0xA781 (ALDERLAKE_S)
[18:59:29] [PASSED] 0xA782 (ALDERLAKE_S)
[18:59:29] [PASSED] 0xA783 (ALDERLAKE_S)
[18:59:29] [PASSED] 0xA788 (ALDERLAKE_S)
[18:59:29] [PASSED] 0xA789 (ALDERLAKE_S)
[18:59:29] [PASSED] 0xA78A (ALDERLAKE_S)
[18:59:29] [PASSED] 0xA78B (ALDERLAKE_S)
[18:59:29] [PASSED] 0x4905 (DG1)
[18:59:29] [PASSED] 0x4906 (DG1)
[18:59:29] [PASSED] 0x4907 (DG1)
[18:59:29] [PASSED] 0x4908 (DG1)
[18:59:29] [PASSED] 0x4909 (DG1)
[18:59:29] [PASSED] 0x56C0 (DG2)
[18:59:29] [PASSED] 0x56C2 (DG2)
[18:59:29] [PASSED] 0x56C1 (DG2)
[18:59:29] [PASSED] 0x7D51 (METEORLAKE)
[18:59:29] [PASSED] 0x7DD1 (METEORLAKE)
[18:59:29] [PASSED] 0x7D41 (METEORLAKE)
[18:59:29] [PASSED] 0x7D67 (METEORLAKE)
[18:59:29] [PASSED] 0xB640 (METEORLAKE)
[18:59:29] [PASSED] 0x56A0 (DG2)
[18:59:29] [PASSED] 0x56A1 (DG2)
[18:59:29] [PASSED] 0x56A2 (DG2)
[18:59:29] [PASSED] 0x56BE (DG2)
[18:59:29] [PASSED] 0x56BF (DG2)
[18:59:29] [PASSED] 0x5690 (DG2)
[18:59:29] [PASSED] 0x5691 (DG2)
[18:59:29] [PASSED] 0x5692 (DG2)
[18:59:29] [PASSED] 0x56A5 (DG2)
[18:59:29] [PASSED] 0x56A6 (DG2)
[18:59:29] [PASSED] 0x56B0 (DG2)
[18:59:29] [PASSED] 0x56B1 (DG2)
[18:59:29] [PASSED] 0x56BA (DG2)
[18:59:29] [PASSED] 0x56BB (DG2)
[18:59:29] [PASSED] 0x56BC (DG2)
[18:59:29] [PASSED] 0x56BD (DG2)
[18:59:29] [PASSED] 0x5693 (DG2)
[18:59:29] [PASSED] 0x5694 (DG2)
[18:59:29] [PASSED] 0x5695 (DG2)
[18:59:29] [PASSED] 0x56A3 (DG2)
[18:59:29] [PASSED] 0x56A4 (DG2)
[18:59:29] [PASSED] 0x56B2 (DG2)
[18:59:29] [PASSED] 0x56B3 (DG2)
[18:59:29] [PASSED] 0x5696 (DG2)
[18:59:29] [PASSED] 0x5697 (DG2)
[18:59:29] [PASSED] 0xB69 (PVC)
[18:59:29] [PASSED] 0xB6E (PVC)
[18:59:29] [PASSED] 0xBD4 (PVC)
[18:59:29] [PASSED] 0xBD5 (PVC)
[18:59:29] [PASSED] 0xBD6 (PVC)
[18:59:29] [PASSED] 0xBD7 (PVC)
[18:59:29] [PASSED] 0xBD8 (PVC)
[18:59:29] [PASSED] 0xBD9 (PVC)
[18:59:29] [PASSED] 0xBDA (PVC)
[18:59:29] [PASSED] 0xBDB (PVC)
[18:59:29] [PASSED] 0xBE0 (PVC)
[18:59:29] [PASSED] 0xBE1 (PVC)
[18:59:29] [PASSED] 0xBE5 (PVC)
[18:59:29] [PASSED] 0x7D40 (METEORLAKE)
[18:59:29] [PASSED] 0x7D45 (METEORLAKE)
[18:59:29] [PASSED] 0x7D55 (METEORLAKE)
[18:59:29] [PASSED] 0x7D60 (METEORLAKE)
[18:59:29] [PASSED] 0x7DD5 (METEORLAKE)
[18:59:29] [PASSED] 0x6420 (LUNARLAKE)
[18:59:29] [PASSED] 0x64A0 (LUNARLAKE)
[18:59:29] [PASSED] 0x64B0 (LUNARLAKE)
[18:59:29] [PASSED] 0xE202 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE209 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE20B (BATTLEMAGE)
[18:59:29] [PASSED] 0xE20C (BATTLEMAGE)
[18:59:29] [PASSED] 0xE20D (BATTLEMAGE)
[18:59:29] [PASSED] 0xE210 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE211 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE212 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE216 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE220 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE221 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE222 (BATTLEMAGE)
[18:59:29] [PASSED] 0xE223 (BATTLEMAGE)
[18:59:29] [PASSED] 0xB080 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB081 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB082 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB083 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB084 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB085 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB086 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB087 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB08F (PANTHERLAKE)
[18:59:29] [PASSED] 0xB090 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB0A0 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB0A1 (PANTHERLAKE)
[18:59:29] [PASSED] 0xB0B0 (PANTHERLAKE)
[18:59:29] [PASSED] 0xFD80 (PANTHERLAKE)
[18:59:29] [PASSED] 0xFD81 (PANTHERLAKE)
[18:59:29] [PASSED] 0xD740 (NOVALAKE_S)
[18:59:29] [PASSED] 0xD741 (NOVALAKE_S)
[18:59:29] [PASSED] 0xD742 (NOVALAKE_S)
[18:59:29] [PASSED] 0xD743 (NOVALAKE_S)
[18:59:29] [PASSED] 0xD745 (NOVALAKE_S)
[18:59:29] [PASSED] 0xD74A (NOVALAKE_S)
[18:59:29] [PASSED] 0xD74B (NOVALAKE_S)
[18:59:29] [PASSED] 0x674C (CRESCENTISLAND)
[18:59:29] [PASSED] 0x674D (CRESCENTISLAND)
[18:59:29] [PASSED] 0x674E (CRESCENTISLAND)
[18:59:29] [PASSED] 0x674F (CRESCENTISLAND)
[18:59:29] [PASSED] 0x6750 (CRESCENTISLAND)
[18:59:29] [PASSED] 0x6751 (CRESCENTISLAND)
[18:59:29] [PASSED] 0xD750 (NOVALAKE_P)
[18:59:29] [PASSED] 0xD751 (NOVALAKE_P)
[18:59:29] [PASSED] 0xD752 (NOVALAKE_P)
[18:59:29] [PASSED] 0xD753 (NOVALAKE_P)
[18:59:29] [PASSED] 0xD754 (NOVALAKE_P)
[18:59:29] [PASSED] 0xD755 (NOVALAKE_P)
[18:59:29] [PASSED] 0xD756 (NOVALAKE_P)
[18:59:29] [PASSED] 0xD757 (NOVALAKE_P)
[18:59:29] [PASSED] 0xD75F (NOVALAKE_P)
[18:59:29] =============== [PASSED] check_platform_desc ===============
[18:59:29] ===================== [PASSED] xe_pci ======================
[18:59:29] ============= xe_rtp_tables_test (5 subtests) ==============
[18:59:29] ================== xe_rtp_table_gt_test  ===================
[18:59:29] [PASSED] gt_was/14011060649
[18:59:29] [PASSED] gt_was/14011059788
[18:59:29] [PASSED] gt_was/14015795083
[18:59:29] [PASSED] gt_was/16021867713
[18:59:29] [PASSED] gt_was/14019449301
[18:59:29] [PASSED] gt_was/16028005424
[18:59:29] [PASSED] gt_was/14026578760
[18:59:29] [PASSED] gt_was/1409420604
[18:59:29] [PASSED] gt_was/1408615072
[18:59:29] [PASSED] gt_was/22010523718
[18:59:29] [PASSED] gt_was/14011006942
[18:59:29] [PASSED] gt_was/14014830051
[18:59:29] [PASSED] gt_was/18018781329
[18:59:29] [PASSED] gt_was/1509235366
[18:59:29] [PASSED] gt_was/18018781329
[18:59:29] [PASSED] gt_was/16016694945
[18:59:29] [PASSED] gt_was/14018575942
[18:59:29] [PASSED] gt_was/22016670082
[18:59:29] [PASSED] gt_was/22016670082
[18:59:29] [PASSED] gt_was/14017421178
[18:59:29] [PASSED] gt_was/16025250150
[18:59:29] [PASSED] gt_was/14021871409
[18:59:29] [PASSED] gt_was/16021865536
[18:59:29] [PASSED] gt_was/14021486841
[18:59:29] [PASSED] gt_was/14025160223
[18:59:29] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[18:59:29] [PASSED] gt_was/14025635424
[18:59:29] [PASSED] gt_was/16028005424
[18:59:29] ============== [PASSED] xe_rtp_table_gt_test ===============
[18:59:29] ================== xe_rtp_table_gt_test  ===================
[18:59:29] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[18:59:29] [PASSED] gt_tunings/Tuning: 32B Access Enable
[18:59:29] [PASSED] gt_tunings/Tuning: L3 cache
[18:59:29] [PASSED] gt_tunings/Tuning: L3 cache - media
[18:59:29] [PASSED] gt_tunings/Tuning: Compression Overfetch
[18:59:29] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[18:59:29] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[18:59:29] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[18:59:29] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[18:59:29] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[18:59:29] [PASSED] gt_tunings/Tuning: Stateless compression control
[18:59:29] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[18:59:29] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[18:59:29] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[18:59:29] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[18:59:29] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[18:59:29] ============== [PASSED] xe_rtp_table_gt_test ===============
[18:59:29] ================== xe_rtp_table_oob_test  ==================
[18:59:29] [PASSED] oob_was/1607983814
[18:59:29] [PASSED] oob_was/16010904313
[18:59:29] [PASSED] oob_was/18022495364
[18:59:29] [PASSED] oob_was/22012773006
[18:59:29] [PASSED] oob_was/14014475959
[18:59:29] [PASSED] oob_was/22011391025
[18:59:29] [PASSED] oob_was/22012727170
[18:59:29] [PASSED] oob_was/22012727685
[18:59:29] [PASSED] oob_was/22016596838
[18:59:29] [PASSED] oob_was/18020744125
[18:59:29] [PASSED] oob_was/1409600907
[18:59:29] [PASSED] oob_was/22014953428
[18:59:29] [PASSED] oob_was/16017236439
[18:59:29] [PASSED] oob_was/14019821291
[18:59:29] [PASSED] oob_was/14015076503
[18:59:29] [PASSED] oob_was/22016122933
[18:59:29] [PASSED] oob_was/14018913170
[18:59:29] [PASSED] oob_was/14018094691
[18:59:29] [PASSED] oob_was/18024947630
[18:59:29] [PASSED] oob_was/16022287689
[18:59:29] [PASSED] oob_was/13011645652
[18:59:29] [PASSED] oob_was/14022293748
[18:59:29] [PASSED] oob_was/22019794406
[18:59:29] [PASSED] oob_was/22019338487
[18:59:29] [PASSED] oob_was/16023588340
[18:59:29] [PASSED] oob_was/14019789679
[18:59:29] [PASSED] oob_was/14022866841
[18:59:29] [PASSED] oob_was/16021333562
[18:59:29] [PASSED] oob_was/14016712196
[18:59:29] [PASSED] oob_was/14015568240
[18:59:29] [PASSED] oob_was/18013179988
[18:59:29] [PASSED] oob_was/1508761755
[18:59:29] [PASSED] oob_was/16023105232
[18:59:29] [PASSED] oob_was/16026508708
[18:59:29] [PASSED] oob_was/14020001231
[18:59:29] [PASSED] oob_was/16023683509
[18:59:29] [PASSED] oob_was/14025515070
[18:59:29] [PASSED] oob_was/15015404425_disable
[18:59:29] [PASSED] oob_was/16026007364
[18:59:29] [PASSED] oob_was/14020316580
[18:59:29] [PASSED] oob_was/14025883347
[18:59:29] [PASSED] oob_was/16029380221
[18:59:29] [PASSED] oob_was/22022079272
[18:59:29] [PASSED] oob_was/16029897822
[18:59:29] [PASSED] oob_was/14027054324
[18:59:29] [PASSED] oob_was/14025941587
[18:59:29] [PASSED] oob_was/16030224309
[18:59:29] ============== [PASSED] xe_rtp_table_oob_test ==============
[18:59:29] ================ xe_rtp_table_dev_oob_test  ================
[18:59:29] [PASSED] device_oob_was/22010954014
[18:59:29] [PASSED] device_oob_was/15015404425
[18:59:29] [PASSED] device_oob_was/22019338487_display
[18:59:29] [PASSED] device_oob_was/14022085890
[18:59:29] [PASSED] device_oob_was/14026539277
[18:59:29] [PASSED] device_oob_was/14026633728
[18:59:29] [PASSED] device_oob_was/14026746987
[18:59:29] [PASSED] device_oob_was/14026779378
[18:59:29] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[18:59:29] ========== xe_rtp_table_missing_upper_bound_test  ==========
[18:59:29] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[18:59:29] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[18:59:29] [PASSED] register_whitelist/1806527549
[18:59:29] [PASSED] register_whitelist/allow_read_ctx_timestamp
[18:59:29] [PASSED] register_whitelist/allow_read_queue_timestamp
[18:59:29] [PASSED] register_whitelist/16014440446
[18:59:29] [PASSED] register_whitelist/16017236439
[18:59:29] [PASSED] register_whitelist/16020183090
[18:59:29] [PASSED] register_whitelist/14024997852
[18:59:29] [PASSED] register_whitelist/14024997852
[18:59:29] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[18:59:29] =============== [PASSED] xe_rtp_tables_test ================
[18:59:29] =================== xe_rtp (3 subtests) ====================
[18:59:29] =================== xe_rtp_rules_tests  ====================
[18:59:29] [PASSED] no
[18:59:29] [PASSED] yes
[18:59:29] [PASSED] no-and-no
[18:59:29] [PASSED] no-and-yes
[18:59:29] [PASSED] yes-and-no
[18:59:29] [PASSED] yes-and-yes
[18:59:29] [PASSED] no-or-no
[18:59:29] [PASSED] no-or-yes
[18:59:29] [PASSED] yes-or-no
[18:59:29] [PASSED] yes-or-yes
[18:59:29] [PASSED] no-yes-or-yes-no
[18:59:29] [PASSED] no-yes-or-yes-yes
[18:59:29] [PASSED] yes-yes-or-no-yes
[18:59:29] [PASSED] yes-yes-or-yes-yes
[18:59:29] [PASSED] no-no-or-yes-or-no
[18:59:29] [PASSED] or
[18:59:29] [PASSED] or-yes
[18:59:29] [PASSED] or-no
[18:59:29] [PASSED] yes-or
[18:59:29] [PASSED] no-or
[18:59:29] [PASSED] no-or-or-yes
[18:59:29] [PASSED] yes-or-or-no
[18:59:29] [PASSED] no-or-or-no
[18:59:29] [PASSED] missing-context-engine-class
[18:59:29] [PASSED] missing-context-engine-class-or-yes
[18:59:29] [PASSED] missing-context-engine-class-or-or-yes
[18:59:29] =============== [PASSED] xe_rtp_rules_tests ================
[18:59:29] =============== xe_rtp_process_to_sr_tests  ================
[18:59:29] [PASSED] coalesce-same-reg
[18:59:29] [PASSED] coalesce-same-reg-literal-and-func
[18:59:29] [PASSED] no-match-no-add
[18:59:29] [PASSED] two-regs-two-entries
[18:59:29] [PASSED] clr-one-set-other
[18:59:29] [PASSED] set-field
[18:59:29] [PASSED] conflict-duplicate
[18:59:29] [PASSED] conflict-not-disjoint
[18:59:29] [PASSED] conflict-not-disjoint-literal-and-func
[18:59:29] [PASSED] conflict-reg-type
[18:59:29] [PASSED] bad-mcr-reg-forced-to-regular
[18:59:29] [PASSED] bad-regular-reg-forced-to-mcr
[18:59:29] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[18:59:29] ================== xe_rtp_process_tests  ===================
[18:59:29] [PASSED] active1
[18:59:29] [PASSED] active2
[18:59:29] [PASSED] active-inactive
[18:59:29] [PASSED] inactive-active
[18:59:29] [PASSED] inactive-active-inactive
[18:59:29] [PASSED] inactive-inactive-inactive
[18:59:29] ============== [PASSED] xe_rtp_process_tests ===============
[18:59:29] ===================== [PASSED] xe_rtp ======================
[18:59:29] ==================== xe_wa (1 subtest) =====================
[18:59:29] ======================== xe_wa_gt  =========================
[18:59:29] [PASSED] TIGERLAKE B0
[18:59:29] [PASSED] DG1 A0
[18:59:29] [PASSED] DG1 B0
[18:59:29] [PASSED] ALDERLAKE_S A0
[18:59:29] [PASSED] ALDERLAKE_S B0
[18:59:29] [PASSED] ALDERLAKE_S C0
[18:59:29] [PASSED] ALDERLAKE_S D0
[18:59:29] [PASSED] ALDERLAKE_P A0
[18:59:29] [PASSED] ALDERLAKE_P B0
[18:59:29] [PASSED] ALDERLAKE_P C0
[18:59:29] [PASSED] ALDERLAKE_S RPLS D0
[18:59:29] [PASSED] ALDERLAKE_P RPLU E0
[18:59:29] [PASSED] DG2 G10 C0
[18:59:29] [PASSED] DG2 G11 B1
[18:59:29] [PASSED] DG2 G12 A1
[18:59:29] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:59:29] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:59:29] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[18:59:29] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[18:59:29] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[18:59:29] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[18:59:29] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[18:59:29] ==================== [PASSED] xe_wa_gt =====================
[18:59:29] ====================== [PASSED] xe_wa ======================
[18:59:29] ============================================================
[18:59:29] Testing complete. Ran 821 tests: passed: 793, skipped: 28
[18:59:29] Elapsed time: 36.385s total, 1.819s configuring, 33.850s building, 0.708s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[18:59:29] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:59:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:59:56] Starting KUnit Kernel (1/1)...
[18:59:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:59:56] ============ drm_test_pick_cmdline (2 subtests) ============
[18:59:56] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[18:59:56] =============== drm_test_pick_cmdline_named  ===============
[18:59:56] [PASSED] NTSC
[18:59:56] [PASSED] NTSC-J
[18:59:57] [PASSED] PAL
[18:59:57] [PASSED] PAL-M
[18:59:57] =========== [PASSED] drm_test_pick_cmdline_named ===========
[18:59:57] ============== [PASSED] drm_test_pick_cmdline ==============
[18:59:57] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[18:59:57] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[18:59:57] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[18:59:57] =========== drm_validate_clone_mode (2 subtests) ===========
[18:59:57] ============== drm_test_check_in_clone_mode  ===============
[18:59:57] [PASSED] in_clone_mode
[18:59:57] [PASSED] not_in_clone_mode
[18:59:57] ========== [PASSED] drm_test_check_in_clone_mode ===========
[18:59:57] =============== drm_test_check_valid_clones  ===============
[18:59:57] [PASSED] not_in_clone_mode
[18:59:57] [PASSED] valid_clone
[18:59:57] [PASSED] invalid_clone
[18:59:57] =========== [PASSED] drm_test_check_valid_clones ===========
[18:59:57] ============= [PASSED] drm_validate_clone_mode =============
[18:59:57] ============= drm_validate_modeset (1 subtest) =============
[18:59:57] [PASSED] drm_test_check_connector_changed_modeset
[18:59:57] ============== [PASSED] drm_validate_modeset ===============
[18:59:57] ====== drm_test_bridge_get_current_state (1 subtest) =======
[18:59:57] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[18:59:57] ======== [PASSED] drm_test_bridge_get_current_state ========
[18:59:57] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[18:59:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[18:59:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[18:59:57] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[18:59:57] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[18:59:57] ============== drm_bridge_alloc (2 subtests) ===============
[18:59:57] [PASSED] drm_test_drm_bridge_alloc_basic
[18:59:57] [PASSED] drm_test_drm_bridge_alloc_get_put
[18:59:57] ================ [PASSED] drm_bridge_alloc =================
[18:59:57] ============= drm_bridge_bus_fmt (5 subtests) ==============
[18:59:57] [PASSED] drm_test_bridge_rgb_yuv_rgb
[18:59:57] [PASSED] drm_test_bridge_must_convert_to_yuv444
[18:59:57] [PASSED] drm_test_bridge_hdmi_auto_rgb
[18:59:57] [PASSED] drm_test_bridge_auto_first
[18:59:57] [PASSED] drm_test_bridge_rgb_yuv_no_path
[18:59:57] =============== [PASSED] drm_bridge_bus_fmt ================
[18:59:57] ============= drm_cmdline_parser (40 subtests) =============
[18:59:57] [PASSED] drm_test_cmdline_force_d_only
[18:59:57] [PASSED] drm_test_cmdline_force_D_only_dvi
[18:59:57] [PASSED] drm_test_cmdline_force_D_only_hdmi
[18:59:57] [PASSED] drm_test_cmdline_force_D_only_not_digital
[18:59:57] [PASSED] drm_test_cmdline_force_e_only
[18:59:57] [PASSED] drm_test_cmdline_res
[18:59:57] [PASSED] drm_test_cmdline_res_vesa
[18:59:57] [PASSED] drm_test_cmdline_res_vesa_rblank
[18:59:57] [PASSED] drm_test_cmdline_res_rblank
[18:59:57] [PASSED] drm_test_cmdline_res_bpp
[18:59:57] [PASSED] drm_test_cmdline_res_refresh
[18:59:57] [PASSED] drm_test_cmdline_res_bpp_refresh
[18:59:57] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[18:59:57] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[18:59:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[18:59:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[18:59:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[18:59:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[18:59:57] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[18:59:57] [PASSED] drm_test_cmdline_res_margins_force_on
[18:59:57] [PASSED] drm_test_cmdline_res_vesa_margins
[18:59:57] [PASSED] drm_test_cmdline_name
[18:59:57] [PASSED] drm_test_cmdline_name_bpp
[18:59:57] [PASSED] drm_test_cmdline_name_option
[18:59:57] [PASSED] drm_test_cmdline_name_bpp_option
[18:59:57] [PASSED] drm_test_cmdline_rotate_0
[18:59:57] [PASSED] drm_test_cmdline_rotate_90
[18:59:57] [PASSED] drm_test_cmdline_rotate_180
[18:59:57] [PASSED] drm_test_cmdline_rotate_270
[18:59:57] [PASSED] drm_test_cmdline_hmirror
[18:59:57] [PASSED] drm_test_cmdline_vmirror
[18:59:57] [PASSED] drm_test_cmdline_margin_options
[18:59:57] [PASSED] drm_test_cmdline_multiple_options
[18:59:57] [PASSED] drm_test_cmdline_bpp_extra_and_option
[18:59:57] [PASSED] drm_test_cmdline_extra_and_option
[18:59:57] [PASSED] drm_test_cmdline_freestanding_options
[18:59:57] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[18:59:57] [PASSED] drm_test_cmdline_panel_orientation
[18:59:57] ================ drm_test_cmdline_invalid  =================
[18:59:57] [PASSED] margin_only
[18:59:57] [PASSED] interlace_only
[18:59:57] [PASSED] res_missing_x
[18:59:57] [PASSED] res_missing_y
[18:59:57] [PASSED] res_bad_y
[18:59:57] [PASSED] res_missing_y_bpp
[18:59:57] [PASSED] res_bad_bpp
[18:59:57] [PASSED] res_bad_refresh
[18:59:57] [PASSED] res_bpp_refresh_force_on_off
[18:59:57] [PASSED] res_invalid_mode
[18:59:57] [PASSED] res_bpp_wrong_place_mode
[18:59:57] [PASSED] name_bpp_refresh
[18:59:57] [PASSED] name_refresh
[18:59:57] [PASSED] name_refresh_wrong_mode
[18:59:57] [PASSED] name_refresh_invalid_mode
[18:59:57] [PASSED] rotate_multiple
[18:59:57] [PASSED] rotate_invalid_val
[18:59:57] [PASSED] rotate_truncated
[18:59:57] [PASSED] invalid_option
[18:59:57] [PASSED] invalid_tv_option
[18:59:57] [PASSED] truncated_tv_option
[18:59:57] ============ [PASSED] drm_test_cmdline_invalid =============
[18:59:57] =============== drm_test_cmdline_tv_options  ===============
[18:59:57] [PASSED] NTSC
[18:59:57] [PASSED] NTSC_443
[18:59:57] [PASSED] NTSC_J
[18:59:57] [PASSED] PAL
[18:59:57] [PASSED] PAL_M
[18:59:57] [PASSED] PAL_N
[18:59:57] [PASSED] SECAM
[18:59:57] [PASSED] MONO_525
[18:59:57] [PASSED] MONO_625
[18:59:57] =========== [PASSED] drm_test_cmdline_tv_options ===========
[18:59:57] =============== [PASSED] drm_cmdline_parser ================
[18:59:57] ========== drmm_connector_hdmi_init (20 subtests) ==========
[18:59:57] [PASSED] drm_test_connector_hdmi_init_valid
[18:59:57] [PASSED] drm_test_connector_hdmi_init_bpc_8
[18:59:57] [PASSED] drm_test_connector_hdmi_init_bpc_10
[18:59:57] [PASSED] drm_test_connector_hdmi_init_bpc_12
[18:59:57] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[18:59:57] [PASSED] drm_test_connector_hdmi_init_bpc_null
[18:59:57] [PASSED] drm_test_connector_hdmi_init_formats_empty
[18:59:57] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[18:59:57] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[18:59:57] [PASSED] supported_formats=0x9 yuv420_allowed=1
[18:59:57] [PASSED] supported_formats=0x9 yuv420_allowed=0
[18:59:57] [PASSED] supported_formats=0x5 yuv420_allowed=1
[18:59:57] [PASSED] supported_formats=0x5 yuv420_allowed=0
[18:59:57] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[18:59:57] [PASSED] drm_test_connector_hdmi_init_null_ddc
[18:59:57] [PASSED] drm_test_connector_hdmi_init_null_product
[18:59:57] [PASSED] drm_test_connector_hdmi_init_null_vendor
[18:59:57] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[18:59:57] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[18:59:57] [PASSED] drm_test_connector_hdmi_init_product_valid
[18:59:57] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[18:59:57] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[18:59:57] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[18:59:57] ========= drm_test_connector_hdmi_init_type_valid  =========
[18:59:57] [PASSED] HDMI-A
[18:59:57] [PASSED] HDMI-B
[18:59:57] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[18:59:57] ======== drm_test_connector_hdmi_init_type_invalid  ========
[18:59:57] [PASSED] Unknown
[18:59:57] [PASSED] VGA
[18:59:57] [PASSED] DVI-I
[18:59:57] [PASSED] DVI-D
[18:59:57] [PASSED] DVI-A
[18:59:57] [PASSED] Composite
[18:59:57] [PASSED] SVIDEO
[18:59:57] [PASSED] LVDS
[18:59:57] [PASSED] Component
[18:59:57] [PASSED] DIN
[18:59:57] [PASSED] DP
[18:59:57] [PASSED] TV
[18:59:57] [PASSED] eDP
[18:59:57] [PASSED] Virtual
[18:59:57] [PASSED] DSI
[18:59:57] [PASSED] DPI
[18:59:57] [PASSED] Writeback
[18:59:57] [PASSED] SPI
[18:59:57] [PASSED] USB
[18:59:57] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[18:59:57] ============ [PASSED] drmm_connector_hdmi_init =============
[18:59:57] ============= drmm_connector_init (3 subtests) =============
[18:59:57] [PASSED] drm_test_drmm_connector_init
[18:59:57] [PASSED] drm_test_drmm_connector_init_null_ddc
[18:59:57] ========= drm_test_drmm_connector_init_type_valid  =========
[18:59:57] [PASSED] Unknown
[18:59:57] [PASSED] VGA
[18:59:57] [PASSED] DVI-I
[18:59:57] [PASSED] DVI-D
[18:59:57] [PASSED] DVI-A
[18:59:57] [PASSED] Composite
[18:59:57] [PASSED] SVIDEO
[18:59:57] [PASSED] LVDS
[18:59:57] [PASSED] Component
[18:59:57] [PASSED] DIN
[18:59:57] [PASSED] DP
[18:59:57] [PASSED] HDMI-A
[18:59:57] [PASSED] HDMI-B
[18:59:57] [PASSED] TV
[18:59:57] [PASSED] eDP
[18:59:57] [PASSED] Virtual
[18:59:57] [PASSED] DSI
[18:59:57] [PASSED] DPI
[18:59:57] [PASSED] Writeback
[18:59:57] [PASSED] SPI
[18:59:57] [PASSED] USB
[18:59:57] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[18:59:57] =============== [PASSED] drmm_connector_init ===============
[18:59:57] ========= drm_connector_dynamic_init (6 subtests) ==========
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_init
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_init_properties
[18:59:57] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[18:59:57] [PASSED] Unknown
[18:59:57] [PASSED] VGA
[18:59:57] [PASSED] DVI-I
[18:59:57] [PASSED] DVI-D
[18:59:57] [PASSED] DVI-A
[18:59:57] [PASSED] Composite
[18:59:57] [PASSED] SVIDEO
[18:59:57] [PASSED] LVDS
[18:59:57] [PASSED] Component
[18:59:57] [PASSED] DIN
[18:59:57] [PASSED] DP
[18:59:57] [PASSED] HDMI-A
[18:59:57] [PASSED] HDMI-B
[18:59:57] [PASSED] TV
[18:59:57] [PASSED] eDP
[18:59:57] [PASSED] Virtual
[18:59:57] [PASSED] DSI
[18:59:57] [PASSED] DPI
[18:59:57] [PASSED] Writeback
[18:59:57] [PASSED] SPI
[18:59:57] [PASSED] USB
[18:59:57] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[18:59:57] ======== drm_test_drm_connector_dynamic_init_name  =========
[18:59:57] [PASSED] Unknown
[18:59:57] [PASSED] VGA
[18:59:57] [PASSED] DVI-I
[18:59:57] [PASSED] DVI-D
[18:59:57] [PASSED] DVI-A
[18:59:57] [PASSED] Composite
[18:59:57] [PASSED] SVIDEO
[18:59:57] [PASSED] LVDS
[18:59:57] [PASSED] Component
[18:59:57] [PASSED] DIN
[18:59:57] [PASSED] DP
[18:59:57] [PASSED] HDMI-A
[18:59:57] [PASSED] HDMI-B
[18:59:57] [PASSED] TV
[18:59:57] [PASSED] eDP
[18:59:57] [PASSED] Virtual
[18:59:57] [PASSED] DSI
[18:59:57] [PASSED] DPI
[18:59:57] [PASSED] Writeback
[18:59:57] [PASSED] SPI
[18:59:57] [PASSED] USB
[18:59:57] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[18:59:57] =========== [PASSED] drm_connector_dynamic_init ============
[18:59:57] ==== drm_connector_dynamic_register_early (4 subtests) =====
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[18:59:57] ====== [PASSED] drm_connector_dynamic_register_early =======
[18:59:57] ======= drm_connector_dynamic_register (7 subtests) ========
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[18:59:57] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[18:59:57] ========= [PASSED] drm_connector_dynamic_register ==========
[18:59:57] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[18:59:57] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[18:59:57] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[18:59:57] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[18:59:57] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[18:59:57] ========== drm_test_get_tv_mode_from_name_valid  ===========
[18:59:57] [PASSED] NTSC
[18:59:57] [PASSED] NTSC-443
[18:59:57] [PASSED] NTSC-J
[18:59:57] [PASSED] PAL
[18:59:57] [PASSED] PAL-M
[18:59:57] [PASSED] PAL-N
[18:59:57] [PASSED] SECAM
[18:59:57] [PASSED] Mono
[18:59:57] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[18:59:57] [PASSED] drm_test_get_tv_mode_from_name_truncated
[18:59:57] ============ [PASSED] drm_get_tv_mode_from_name ============
[18:59:57] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[18:59:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[18:59:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[18:59:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[18:59:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[18:59:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[18:59:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[18:59:57] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[18:59:57] [PASSED] VIC 96
[18:59:57] [PASSED] VIC 97
[18:59:57] [PASSED] VIC 101
[18:59:57] [PASSED] VIC 102
[18:59:57] [PASSED] VIC 106
[18:59:57] [PASSED] VIC 107
[18:59:57] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[18:59:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[18:59:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[18:59:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[18:59:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[18:59:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[18:59:57] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[18:59:57] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[18:59:57] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[18:59:57] [PASSED] Automatic
[18:59:57] [PASSED] Full
[18:59:57] [PASSED] Limited 16:235
[18:59:57] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[18:59:57] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[18:59:57] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[18:59:57] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[18:59:57] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[18:59:57] [PASSED] RGB
[18:59:57] [PASSED] YUV 4:2:0
[18:59:57] [PASSED] YUV 4:2:2
[18:59:57] [PASSED] YUV 4:4:4
[18:59:57] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[18:59:57] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[18:59:57] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[18:59:57] ============= drm_damage_helper (21 subtests) ==============
[18:59:57] [PASSED] drm_test_damage_iter_no_damage
[18:59:57] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[18:59:57] [PASSED] drm_test_damage_iter_no_damage_src_moved
[18:59:57] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[18:59:57] [PASSED] drm_test_damage_iter_no_damage_not_visible
[18:59:57] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[18:59:57] [PASSED] drm_test_damage_iter_no_damage_no_fb
[18:59:57] [PASSED] drm_test_damage_iter_simple_damage
[18:59:57] [PASSED] drm_test_damage_iter_single_damage
[18:59:57] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[18:59:57] [PASSED] drm_test_damage_iter_single_damage_outside_src
[18:59:57] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[18:59:57] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[18:59:57] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[18:59:57] [PASSED] drm_test_damage_iter_single_damage_src_moved
[18:59:57] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[18:59:57] [PASSED] drm_test_damage_iter_damage
[18:59:57] [PASSED] drm_test_damage_iter_damage_one_intersect
[18:59:57] [PASSED] drm_test_damage_iter_damage_one_outside
[18:59:57] [PASSED] drm_test_damage_iter_damage_src_moved
[18:59:57] [PASSED] drm_test_damage_iter_damage_not_visible
[18:59:57] ================ [PASSED] drm_damage_helper ================
[18:59:57] ============== drm_dp_mst_helper (3 subtests) ==============
[18:59:57] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[18:59:57] [PASSED] Clock 154000 BPP 30 DSC disabled
[18:59:57] [PASSED] Clock 234000 BPP 30 DSC disabled
[18:59:57] [PASSED] Clock 297000 BPP 24 DSC disabled
[18:59:57] [PASSED] Clock 332880 BPP 24 DSC enabled
[18:59:57] [PASSED] Clock 324540 BPP 24 DSC enabled
[18:59:57] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[18:59:57] ============== drm_test_dp_mst_calc_pbn_div  ===============
[18:59:57] [PASSED] Link rate 2000000 lane count 4
[18:59:57] [PASSED] Link rate 2000000 lane count 2
[18:59:57] [PASSED] Link rate 2000000 lane count 1
[18:59:57] [PASSED] Link rate 1350000 lane count 4
[18:59:57] [PASSED] Link rate 1350000 lane count 2
[18:59:57] [PASSED] Link rate 1350000 lane count 1
[18:59:57] [PASSED] Link rate 1000000 lane count 4
[18:59:57] [PASSED] Link rate 1000000 lane count 2
[18:59:57] [PASSED] Link rate 1000000 lane count 1
[18:59:57] [PASSED] Link rate 810000 lane count 4
[18:59:57] [PASSED] Link rate 810000 lane count 2
[18:59:57] [PASSED] Link rate 810000 lane count 1
[18:59:57] [PASSED] Link rate 540000 lane count 4
[18:59:57] [PASSED] Link rate 540000 lane count 2
[18:59:57] [PASSED] Link rate 540000 lane count 1
[18:59:57] [PASSED] Link rate 270000 lane count 4
[18:59:57] [PASSED] Link rate 270000 lane count 2
[18:59:57] [PASSED] Link rate 270000 lane count 1
[18:59:57] [PASSED] Link rate 162000 lane count 4
[18:59:57] [PASSED] Link rate 162000 lane count 2
[18:59:57] [PASSED] Link rate 162000 lane count 1
[18:59:57] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[18:59:57] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[18:59:57] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[18:59:57] [PASSED] DP_POWER_UP_PHY with port number
[18:59:57] [PASSED] DP_POWER_DOWN_PHY with port number
[18:59:57] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[18:59:57] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[18:59:57] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[18:59:57] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[18:59:57] [PASSED] DP_QUERY_PAYLOAD with port number
[18:59:57] [PASSED] DP_QUERY_PAYLOAD with VCPI
[18:59:57] [PASSED] DP_REMOTE_DPCD_READ with port number
[18:59:57] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[18:59:57] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[18:59:57] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[18:59:57] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[18:59:57] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[18:59:57] [PASSED] DP_REMOTE_I2C_READ with port number
[18:59:57] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[18:59:57] [PASSED] DP_REMOTE_I2C_READ with transactions array
[18:59:57] [PASSED] DP_REMOTE_I2C_WRITE with port number
[18:59:57] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[18:59:57] [PASSED] DP_REMOTE_I2C_WRITE with data array
[18:59:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[18:59:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[18:59:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[18:59:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[18:59:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[18:59:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[18:59:57] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[18:59:57] ================ [PASSED] drm_dp_mst_helper ================
[18:59:57] ================== drm_exec (7 subtests) ===================
[18:59:57] [PASSED] sanitycheck
[18:59:57] [PASSED] test_lock
[18:59:57] [PASSED] test_lock_unlock
[18:59:57] [PASSED] test_duplicates
[18:59:57] [PASSED] test_prepare
[18:59:57] [PASSED] test_prepare_array
[18:59:57] [PASSED] test_multiple_loops
[18:59:57] ==================== [PASSED] drm_exec =====================
[18:59:57] =========== drm_format_helper_test (17 subtests) ===========
[18:59:57] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[18:59:57] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[18:59:57] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[18:59:57] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[18:59:57] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[18:59:57] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[18:59:57] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[18:59:57] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[18:59:57] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[18:59:57] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[18:59:57] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[18:59:57] ============== drm_test_fb_xrgb8888_to_mono  ===============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[18:59:57] ==================== drm_test_fb_swab  =====================
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ================ [PASSED] drm_test_fb_swab =================
[18:59:57] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[18:59:57] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[18:59:57] [PASSED] single_pixel_source_buffer
[18:59:57] [PASSED] single_pixel_clip_rectangle
[18:59:57] [PASSED] well_known_colors
[18:59:57] [PASSED] destination_pitch
[18:59:57] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[18:59:57] ================= drm_test_fb_clip_offset  =================
[18:59:57] [PASSED] pass through
[18:59:57] [PASSED] horizontal offset
[18:59:57] [PASSED] vertical offset
[18:59:57] [PASSED] horizontal and vertical offset
[18:59:57] [PASSED] horizontal offset (custom pitch)
[18:59:57] [PASSED] vertical offset (custom pitch)
[18:59:57] [PASSED] horizontal and vertical offset (custom pitch)
[18:59:57] ============= [PASSED] drm_test_fb_clip_offset =============
[18:59:57] =================== drm_test_fb_memcpy  ====================
[18:59:57] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[18:59:57] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[18:59:57] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[18:59:57] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[18:59:57] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[18:59:57] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[18:59:57] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[18:59:57] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[18:59:57] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[18:59:57] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[18:59:57] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[18:59:57] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[18:59:57] =============== [PASSED] drm_test_fb_memcpy ================
[18:59:57] ============= [PASSED] drm_format_helper_test ==============
[18:59:57] ================= drm_format (18 subtests) =================
[18:59:57] [PASSED] drm_test_format_block_width_invalid
[18:59:57] [PASSED] drm_test_format_block_width_one_plane
[18:59:57] [PASSED] drm_test_format_block_width_two_plane
[18:59:57] [PASSED] drm_test_format_block_width_three_plane
[18:59:57] [PASSED] drm_test_format_block_width_tiled
[18:59:57] [PASSED] drm_test_format_block_height_invalid
[18:59:57] [PASSED] drm_test_format_block_height_one_plane
[18:59:57] [PASSED] drm_test_format_block_height_two_plane
[18:59:57] [PASSED] drm_test_format_block_height_three_plane
[18:59:57] [PASSED] drm_test_format_block_height_tiled
[18:59:57] [PASSED] drm_test_format_min_pitch_invalid
[18:59:57] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[18:59:57] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[18:59:57] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[18:59:57] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[18:59:57] [PASSED] drm_test_format_min_pitch_two_plane
[18:59:57] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[18:59:57] [PASSED] drm_test_format_min_pitch_tiled
[18:59:57] =================== [PASSED] drm_format ====================
[18:59:57] ============== drm_framebuffer (10 subtests) ===============
[18:59:57] ========== drm_test_framebuffer_check_src_coords  ==========
[18:59:57] [PASSED] Success: source fits into fb
[18:59:57] [PASSED] Fail: overflowing fb with x-axis coordinate
[18:59:57] [PASSED] Fail: overflowing fb with y-axis coordinate
[18:59:57] [PASSED] Fail: overflowing fb with source width
[18:59:57] [PASSED] Fail: overflowing fb with source height
[18:59:57] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[18:59:57] [PASSED] drm_test_framebuffer_cleanup
[18:59:57] =============== drm_test_framebuffer_create  ===============
[18:59:57] [PASSED] ABGR8888 normal sizes
[18:59:57] [PASSED] ABGR8888 max sizes
[18:59:57] [PASSED] ABGR8888 pitch greater than min required
[18:59:57] [PASSED] ABGR8888 pitch less than min required
[18:59:57] [PASSED] ABGR8888 Invalid width
[18:59:57] [PASSED] ABGR8888 Invalid buffer handle
[18:59:57] [PASSED] No pixel format
[18:59:57] [PASSED] ABGR8888 Width 0
[18:59:57] [PASSED] ABGR8888 Height 0
[18:59:57] [PASSED] ABGR8888 Out of bound height * pitch combination
[18:59:57] [PASSED] ABGR8888 Large buffer offset
[18:59:57] [PASSED] ABGR8888 Buffer offset for inexistent plane
[18:59:57] [PASSED] ABGR8888 Invalid flag
[18:59:57] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[18:59:57] [PASSED] ABGR8888 Valid buffer modifier
[18:59:57] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[18:59:57] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[18:59:57] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[18:59:57] [PASSED] NV12 Normal sizes
[18:59:57] [PASSED] NV12 Max sizes
[18:59:57] [PASSED] NV12 Invalid pitch
[18:59:57] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[18:59:57] [PASSED] NV12 different  modifier per-plane
[18:59:57] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[18:59:57] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[18:59:57] [PASSED] NV12 Modifier for inexistent plane
[18:59:57] [PASSED] NV12 Handle for inexistent plane
[18:59:57] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[18:59:57] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[18:59:57] [PASSED] YVU420 Normal sizes
[18:59:57] [PASSED] YVU420 Max sizes
[18:59:57] [PASSED] YVU420 Invalid pitch
[18:59:57] [PASSED] YVU420 Different pitches
[18:59:57] [PASSED] YVU420 Different buffer offsets/pitches
[18:59:57] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[18:59:57] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[18:59:57] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[18:59:57] [PASSED] YVU420 Valid modifier
[18:59:57] [PASSED] YVU420 Different modifiers per plane
[18:59:57] [PASSED] YVU420 Modifier for inexistent plane
[18:59:57] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[18:59:57] [PASSED] X0L2 Normal sizes
[18:59:57] [PASSED] X0L2 Max sizes
[18:59:57] [PASSED] X0L2 Invalid pitch
[18:59:57] [PASSED] X0L2 Pitch greater than minimum required
[18:59:57] [PASSED] X0L2 Handle for inexistent plane
[18:59:57] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[18:59:57] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[18:59:57] [PASSED] X0L2 Valid modifier
[18:59:57] [PASSED] X0L2 Modifier for inexistent plane
[18:59:57] =========== [PASSED] drm_test_framebuffer_create ===========
[18:59:57] [PASSED] drm_test_framebuffer_free
[18:59:57] [PASSED] drm_test_framebuffer_init
[18:59:57] [PASSED] drm_test_framebuffer_init_bad_format
[18:59:57] [PASSED] drm_test_framebuffer_init_dev_mismatch
[18:59:57] [PASSED] drm_test_framebuffer_lookup
[18:59:57] [PASSED] drm_test_framebuffer_lookup_inexistent
[18:59:57] [PASSED] drm_test_framebuffer_modifiers_not_supported
[18:59:57] ================= [PASSED] drm_framebuffer =================
[18:59:57] ================ drm_gem_shmem (8 subtests) ================
[18:59:57] [PASSED] drm_gem_shmem_test_obj_create
[18:59:57] [PASSED] drm_gem_shmem_test_obj_create_private
[18:59:57] [PASSED] drm_gem_shmem_test_pin_pages
[18:59:57] [PASSED] drm_gem_shmem_test_vmap
[18:59:57] [PASSED] drm_gem_shmem_test_get_sg_table
[18:59:57] [PASSED] drm_gem_shmem_test_get_pages_sgt
[18:59:57] [PASSED] drm_gem_shmem_test_madvise
[18:59:57] [PASSED] drm_gem_shmem_test_purge
[18:59:57] ================== [PASSED] drm_gem_shmem ==================
[18:59:57] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[18:59:57] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[18:59:57] [PASSED] Automatic
[18:59:57] [PASSED] Full
[18:59:57] [PASSED] Limited 16:235
[18:59:57] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[18:59:57] [PASSED] drm_test_check_disable_connector
[18:59:57] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[18:59:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[18:59:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[18:59:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[18:59:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[18:59:57] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[18:59:57] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[18:59:57] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[18:59:57] [PASSED] drm_test_check_output_bpc_dvi
[18:59:57] [PASSED] drm_test_check_output_bpc_format_vic_1
[18:59:57] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[18:59:57] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[18:59:57] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[18:59:57] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[18:59:57] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[18:59:57] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[18:59:57] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[18:59:57] ============ drm_test_check_hdmi_color_format  =============
[18:59:57] [PASSED] AUTO -> RGB
[18:59:57] [PASSED] YCBCR422 -> YUV422
[18:59:57] [PASSED] YCBCR420 -> YUV420
[18:59:57] [PASSED] YCBCR444 -> YUV444
[18:59:57] [PASSED] RGB -> RGB
[18:59:57] ======== [PASSED] drm_test_check_hdmi_color_format =========
[18:59:57] ======== drm_test_check_hdmi_color_format_420_only  ========
[18:59:57] [PASSED] RGB should fail
[18:59:57] [PASSED] YUV444 should fail
[18:59:57] [PASSED] YUV422 should fail
[18:59:57] [PASSED] YUV420 should work
[18:59:57] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[18:59:57] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[18:59:57] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[18:59:57] [PASSED] drm_test_check_broadcast_rgb_value
[18:59:57] [PASSED] drm_test_check_bpc_8_value
[18:59:57] [PASSED] drm_test_check_bpc_10_value
[18:59:57] [PASSED] drm_test_check_bpc_12_value
[18:59:57] [PASSED] drm_test_check_format_value
[18:59:57] [PASSED] drm_test_check_tmds_char_value
[18:59:57] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[18:59:57] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[18:59:57] [PASSED] drm_test_check_mode_valid
[18:59:57] [PASSED] drm_test_check_mode_valid_reject
[18:59:57] [PASSED] drm_test_check_mode_valid_reject_rate
[18:59:57] [PASSED] drm_test_check_mode_valid_reject_max_clock
[18:59:57] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[18:59:57] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[18:59:57] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[18:59:57] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[18:59:57] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[18:59:57] [PASSED] drm_test_check_infoframes
[18:59:57] [PASSED] drm_test_check_reject_avi_infoframe
[18:59:57] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[18:59:57] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[18:59:57] [PASSED] drm_test_check_reject_audio_infoframe
[18:59:57] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[18:59:57] ================= drm_managed (2 subtests) =================
[18:59:57] [PASSED] drm_test_managed_release_action
[18:59:57] [PASSED] drm_test_managed_run_action
[18:59:57] =================== [PASSED] drm_managed ===================
[18:59:57] =================== drm_mm (6 subtests) ====================
[18:59:57] [PASSED] drm_test_mm_init
[18:59:57] [PASSED] drm_test_mm_debug
[18:59:57] [PASSED] drm_test_mm_align32
[18:59:57] [PASSED] drm_test_mm_align64
[18:59:57] [PASSED] drm_test_mm_lowest
[18:59:57] [PASSED] drm_test_mm_highest
[18:59:57] ===================== [PASSED] drm_mm ======================
[18:59:57] ============= drm_modes_analog_tv (5 subtests) =============
[18:59:57] [PASSED] drm_test_modes_analog_tv_mono_576i
[18:59:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[18:59:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[18:59:57] [PASSED] drm_test_modes_analog_tv_pal_576i
[18:59:57] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[18:59:57] =============== [PASSED] drm_modes_analog_tv ===============
[18:59:57] ============== drm_panic_helper (3 subtests) ===============
[18:59:57] ============= drm_test_panic_screen_user_map  ==============
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[18:59:57] ========= [PASSED] drm_test_panic_screen_user_map ==========
[18:59:57] ============= drm_test_panic_screen_user_page  =============
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[18:59:57] ========= [PASSED] drm_test_panic_screen_user_page =========
[18:59:57] ========== drm_test_panic_screen_user_set_pixel  ===========
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[18:59:57] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[18:59:57] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[18:59:57] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[18:59:57] ================ [PASSED] drm_panic_helper =================
[18:59:57] ============== drm_plane_helper (2 subtests) ===============
[18:59:57] =============== drm_test_check_plane_state  ================
[18:59:57] [PASSED] clipping_simple
[18:59:57] [PASSED] clipping_rotate_reflect
[18:59:57] [PASSED] positioning_simple
[18:59:57] [PASSED] upscaling
[18:59:57] [PASSED] downscaling
[18:59:57] [PASSED] rounding1
[18:59:57] [PASSED] rounding2
[18:59:57] [PASSED] rounding3
[18:59:57] [PASSED] rounding4
[18:59:57] =========== [PASSED] drm_test_check_plane_state ============
[18:59:57] =========== drm_test_check_invalid_plane_state  ============
[18:59:57] [PASSED] positioning_invalid
[18:59:57] [PASSED] upscaling_invalid
[18:59:57] [PASSED] downscaling_invalid
[18:59:57] ======= [PASSED] drm_test_check_invalid_plane_state ========
[18:59:57] ================ [PASSED] drm_plane_helper =================
[18:59:57] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[18:59:57] ====== drm_test_connector_helper_tv_get_modes_check  =======
[18:59:57] [PASSED] None
[18:59:57] [PASSED] PAL
[18:59:57] [PASSED] NTSC
[18:59:57] [PASSED] Both, NTSC Default
[18:59:57] [PASSED] Both, PAL Default
[18:59:57] [PASSED] Both, NTSC Default, with PAL on command-line
[18:59:57] [PASSED] Both, PAL Default, with NTSC on command-line
[18:59:57] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[18:59:57] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[18:59:57] ================== drm_rect (9 subtests) ===================
[18:59:57] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[18:59:57] [PASSED] drm_test_rect_clip_scaled_not_clipped
[18:59:57] [PASSED] drm_test_rect_clip_scaled_clipped
[18:59:57] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[18:59:57] ================= drm_test_rect_intersect  =================
[18:59:57] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[18:59:57] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[18:59:57] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[18:59:57] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[18:59:57] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[18:59:57] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[18:59:57] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[18:59:57] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[18:59:57] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[18:59:57] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[18:59:57] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[18:59:57] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[18:59:57] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[18:59:57] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[18:59:57] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[18:59:57] ============= [PASSED] drm_test_rect_intersect =============
[18:59:57] ================ drm_test_rect_calc_hscale  ================
[18:59:57] [PASSED] normal use
[18:59:57] [PASSED] out of max range
[18:59:57] [PASSED] out of min range
[18:59:57] [PASSED] zero dst
[18:59:57] [PASSED] negative src
[18:59:57] [PASSED] negative dst
[18:59:57] ============ [PASSED] drm_test_rect_calc_hscale ============
[18:59:57] ================ drm_test_rect_calc_vscale  ================
[18:59:57] [PASSED] normal use
[18:59:57] [PASSED] out of max range
[18:59:57] [PASSED] out of min range
[18:59:57] [PASSED] zero dst
[18:59:57] [PASSED] negative src
[18:59:57] [PASSED] negative dst
[18:59:57] ============ [PASSED] drm_test_rect_calc_vscale ============
[18:59:57] ================== drm_test_rect_rotate  ===================
[18:59:57] [PASSED] reflect-x
[18:59:57] [PASSED] reflect-y
[18:59:57] [PASSED] rotate-0
[18:59:57] [PASSED] rotate-90
[18:59:57] [PASSED] rotate-180
[18:59:57] [PASSED] rotate-270
[18:59:57] ============== [PASSED] drm_test_rect_rotate ===============
[18:59:57] ================ drm_test_rect_rotate_inv  =================
[18:59:57] [PASSED] reflect-x
[18:59:57] [PASSED] reflect-y
[18:59:57] [PASSED] rotate-0
[18:59:57] [PASSED] rotate-90
[18:59:57] [PASSED] rotate-180
[18:59:57] [PASSED] rotate-270
[18:59:57] ============ [PASSED] drm_test_rect_rotate_inv =============
[18:59:57] ==================== [PASSED] drm_rect =====================
[18:59:57] ============ drm_sysfb_modeset_test (1 subtest) ============
[18:59:57] ============ drm_test_sysfb_build_fourcc_list  =============
[18:59:57] [PASSED] no native formats
[18:59:57] [PASSED] XRGB8888 as native format
[18:59:57] [PASSED] remove duplicates
[18:59:57] [PASSED] convert alpha formats
[18:59:57] [PASSED] random formats
[18:59:57] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[18:59:57] ============= [PASSED] drm_sysfb_modeset_test ==============
[18:59:57] ================== drm_fixp (2 subtests) ===================
[18:59:57] [PASSED] drm_test_int2fixp
[18:59:57] [PASSED] drm_test_sm2fixp
[18:59:57] ==================== [PASSED] drm_fixp =====================
[18:59:57] ============================================================
[18:59:57] Testing complete. Ran 667 tests: passed: 667
[18:59:57] Elapsed time: 27.367s total, 1.875s configuring, 25.027s building, 0.456s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[18:59:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:59:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:00:09] Starting KUnit Kernel (1/1)...
[19:00:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:00:09] ================= ttm_device (5 subtests) ==================
[19:00:09] [PASSED] ttm_device_init_basic
[19:00:09] [PASSED] ttm_device_init_multiple
[19:00:09] [PASSED] ttm_device_fini_basic
[19:00:09] [PASSED] ttm_device_init_no_vma_man
[19:00:09] ================== ttm_device_init_pools  ==================
[19:00:09] [PASSED] No DMA allocations, no DMA32 required
[19:00:09] [PASSED] DMA allocations, DMA32 required
[19:00:09] [PASSED] No DMA allocations, DMA32 required
[19:00:09] [PASSED] DMA allocations, no DMA32 required
[19:00:09] ============== [PASSED] ttm_device_init_pools ==============
[19:00:09] =================== [PASSED] ttm_device ====================
[19:00:09] ================== ttm_pool (8 subtests) ===================
[19:00:09] ================== ttm_pool_alloc_basic  ===================
[19:00:09] [PASSED] One page
[19:00:09] [PASSED] More than one page
[19:00:09] [PASSED] Above the allocation limit
[19:00:09] [PASSED] One page, with coherent DMA mappings enabled
[19:00:09] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:00:09] ============== [PASSED] ttm_pool_alloc_basic ===============
[19:00:09] ============== ttm_pool_alloc_basic_dma_addr  ==============
[19:00:09] [PASSED] One page
[19:00:09] [PASSED] More than one page
[19:00:09] [PASSED] Above the allocation limit
[19:00:09] [PASSED] One page, with coherent DMA mappings enabled
[19:00:09] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:00:09] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[19:00:09] [PASSED] ttm_pool_alloc_order_caching_match
[19:00:09] [PASSED] ttm_pool_alloc_caching_mismatch
[19:00:09] [PASSED] ttm_pool_alloc_order_mismatch
[19:00:09] [PASSED] ttm_pool_free_dma_alloc
[19:00:09] [PASSED] ttm_pool_free_no_dma_alloc
[19:00:09] [PASSED] ttm_pool_fini_basic
[19:00:09] ==================== [PASSED] ttm_pool =====================
[19:00:09] ================ ttm_resource (8 subtests) =================
[19:00:09] ================= ttm_resource_init_basic  =================
[19:00:09] [PASSED] Init resource in TTM_PL_SYSTEM
[19:00:09] [PASSED] Init resource in TTM_PL_VRAM
[19:00:09] [PASSED] Init resource in a private placement
[19:00:09] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[19:00:09] ============= [PASSED] ttm_resource_init_basic =============
[19:00:09] [PASSED] ttm_resource_init_pinned
[19:00:09] [PASSED] ttm_resource_fini_basic
[19:00:09] [PASSED] ttm_resource_manager_init_basic
[19:00:09] [PASSED] ttm_resource_manager_usage_basic
[19:00:09] [PASSED] ttm_resource_manager_set_used_basic
[19:00:09] [PASSED] ttm_sys_man_alloc_basic
[19:00:09] [PASSED] ttm_sys_man_free_basic
[19:00:09] ================== [PASSED] ttm_resource ===================
[19:00:09] =================== ttm_tt (15 subtests) ===================
[19:00:09] ==================== ttm_tt_init_basic  ====================
[19:00:09] [PASSED] Page-aligned size
[19:00:09] [PASSED] Extra pages requested
[19:00:09] ================ [PASSED] ttm_tt_init_basic ================
[19:00:09] [PASSED] ttm_tt_init_misaligned
[19:00:09] [PASSED] ttm_tt_fini_basic
[19:00:09] [PASSED] ttm_tt_fini_sg
[19:00:09] [PASSED] ttm_tt_fini_shmem
[19:00:09] [PASSED] ttm_tt_create_basic
[19:00:09] [PASSED] ttm_tt_create_invalid_bo_type
[19:00:09] [PASSED] ttm_tt_create_ttm_exists
[19:00:09] [PASSED] ttm_tt_create_failed
[19:00:09] [PASSED] ttm_tt_destroy_basic
[19:00:09] [PASSED] ttm_tt_populate_null_ttm
[19:00:09] [PASSED] ttm_tt_populate_populated_ttm
[19:00:09] [PASSED] ttm_tt_unpopulate_basic
[19:00:09] [PASSED] ttm_tt_unpopulate_empty_ttm
[19:00:09] [PASSED] ttm_tt_swapin_basic
[19:00:09] ===================== [PASSED] ttm_tt ======================
[19:00:09] =================== ttm_bo (14 subtests) ===================
[19:00:09] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[19:00:09] [PASSED] Cannot be interrupted and sleeps
[19:00:09] [PASSED] Cannot be interrupted, locks straight away
[19:00:09] [PASSED] Can be interrupted, sleeps
[19:00:09] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[19:00:09] [PASSED] ttm_bo_reserve_locked_no_sleep
[19:00:09] [PASSED] ttm_bo_reserve_no_wait_ticket
[19:00:09] [PASSED] ttm_bo_reserve_double_resv
[19:00:09] [PASSED] ttm_bo_reserve_interrupted
[19:00:09] [PASSED] ttm_bo_reserve_deadlock
[19:00:09] [PASSED] ttm_bo_unreserve_basic
[19:00:09] [PASSED] ttm_bo_unreserve_pinned
[19:00:09] [PASSED] ttm_bo_unreserve_bulk
[19:00:09] [PASSED] ttm_bo_fini_basic
[19:00:09] [PASSED] ttm_bo_fini_shared_resv
[19:00:09] [PASSED] ttm_bo_pin_basic
[19:00:09] [PASSED] ttm_bo_pin_unpin_resource
[19:00:09] [PASSED] ttm_bo_multiple_pin_one_unpin
[19:00:09] ===================== [PASSED] ttm_bo ======================
[19:00:09] ============== ttm_bo_validate (22 subtests) ===============
[19:00:09] ============== ttm_bo_init_reserved_sys_man  ===============
[19:00:09] [PASSED] Buffer object for userspace
[19:00:09] [PASSED] Kernel buffer object
[19:00:09] [PASSED] Shared buffer object
[19:00:09] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[19:00:09] ============== ttm_bo_init_reserved_mock_man  ==============
[19:00:09] [PASSED] Buffer object for userspace
[19:00:09] [PASSED] Kernel buffer object
[19:00:09] [PASSED] Shared buffer object
[19:00:09] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[19:00:09] [PASSED] ttm_bo_init_reserved_resv
[19:00:09] ================== ttm_bo_validate_basic  ==================
[19:00:09] [PASSED] Buffer object for userspace
[19:00:09] [PASSED] Kernel buffer object
[19:00:09] [PASSED] Shared buffer object
[19:00:09] ============== [PASSED] ttm_bo_validate_basic ==============
[19:00:09] [PASSED] ttm_bo_validate_invalid_placement
[19:00:09] ============= ttm_bo_validate_same_placement  ==============
[19:00:09] [PASSED] System manager
[19:00:09] [PASSED] VRAM manager
[19:00:09] ========= [PASSED] ttm_bo_validate_same_placement ==========
[19:00:09] [PASSED] ttm_bo_validate_failed_alloc
[19:00:09] [PASSED] ttm_bo_validate_pinned
[19:00:09] [PASSED] ttm_bo_validate_busy_placement
[19:00:09] ================ ttm_bo_validate_multihop  =================
[19:00:09] [PASSED] Buffer object for userspace
[19:00:09] [PASSED] Kernel buffer object
[19:00:09] [PASSED] Shared buffer object
[19:00:09] ============ [PASSED] ttm_bo_validate_multihop =============
[19:00:09] ========== ttm_bo_validate_no_placement_signaled  ==========
[19:00:09] [PASSED] Buffer object in system domain, no page vector
[19:00:09] [PASSED] Buffer object in system domain with an existing page vector
[19:00:09] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[19:00:09] ======== ttm_bo_validate_no_placement_not_signaled  ========
[19:00:09] [PASSED] Buffer object for userspace
[19:00:09] [PASSED] Kernel buffer object
[19:00:09] [PASSED] Shared buffer object
[19:00:09] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[19:00:09] [PASSED] ttm_bo_validate_move_fence_signaled
[19:00:09] ========= ttm_bo_validate_move_fence_not_signaled  =========
[19:00:09] [PASSED] Waits for GPU
[19:00:09] [PASSED] Tries to lock straight away
[19:00:09] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[19:00:09] [PASSED] ttm_bo_validate_swapout
[19:00:09] [PASSED] ttm_bo_validate_happy_evict
[19:00:09] [PASSED] ttm_bo_validate_all_pinned_evict
[19:00:09] [PASSED] ttm_bo_validate_allowed_only_evict
[19:00:09] [PASSED] ttm_bo_validate_deleted_evict
[19:00:09] [PASSED] ttm_bo_validate_busy_domain_evict
[19:00:09] [PASSED] ttm_bo_validate_evict_gutting
[19:00:09] [PASSED] ttm_bo_validate_recrusive_evict
[19:00:09] ================= [PASSED] ttm_bo_validate =================
[19:00:09] ============================================================
[19:00:09] Testing complete. Ran 102 tests: passed: 102
[19:00:09] Elapsed time: 12.178s total, 1.802s configuring, 10.161s building, 0.176s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[19:00:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:00:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:00:20] Starting KUnit Kernel (1/1)...
[19:00:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:00:20] =============== dma-buf-fence (12 subtests) ================
[19:00:20] [PASSED] test_sanitycheck
[19:00:20] [PASSED] test_signaling
[19:00:20] [PASSED] test_add_callback
[19:00:20] [PASSED] test_late_add_callback
[19:00:20] [PASSED] test_rm_callback
[19:00:20] [PASSED] test_late_rm_callback
[19:00:20] [PASSED] test_status
[19:00:20] [PASSED] test_error
[19:00:20] [PASSED] test_wait
[19:00:20] [PASSED] test_wait_timeout
[19:00:20] [PASSED] test_stub
[19:00:20] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[19:00:20] ================== [PASSED] dma-buf-fence ==================
[19:00:20] ============ dma-buf-fence-chain (11 subtests) =============
[19:00:20] [PASSED] test_sanitycheck
[19:00:20] [PASSED] test_find_seqno
[19:00:20] [PASSED] test_find_signaled
[19:00:20] [PASSED] test_find_out_of_order
[19:00:25] [PASSED] test_find_gap
[19:00:25] [PASSED] test_find_race
[19:00:25] [PASSED] test_signal_forward
[19:00:25] [PASSED] test_signal_backward
[19:00:25] [PASSED] test_wait_forward
[19:00:25] [PASSED] test_wait_backward
[19:00:25] [PASSED] test_wait_random
[19:00:25] =============== [PASSED] dma-buf-fence-chain ===============
[19:00:25] ============ dma-buf-fence-unwrap (10 subtests) ============
[19:00:25] [PASSED] test_sanitycheck
[19:00:25] [PASSED] test_unwrap_array
[19:00:25] [PASSED] test_unwrap_chain
[19:00:25] [PASSED] test_unwrap_chain_array
[19:00:25] [PASSED] test_unwrap_merge
[19:00:25] [PASSED] test_unwrap_merge_duplicate
[19:00:25] [PASSED] test_unwrap_merge_seqno
[19:00:25] [PASSED] test_unwrap_merge_order
[19:00:25] [PASSED] test_unwrap_merge_complex
[19:00:25] [PASSED] test_unwrap_merge_complex_seqno
[19:00:25] ============== [PASSED] dma-buf-fence-unwrap ===============
[19:00:25] ================ dma-buf-resv (5 subtests) =================
[19:00:25] [PASSED] test_sanitycheck
[19:00:25] ===================== test_signaling  ======================
[19:00:25] [PASSED] kernel
[19:00:25] [PASSED] write
[19:00:25] [PASSED] read
[19:00:25] [PASSED] bookkeep
[19:00:25] ================= [PASSED] test_signaling ==================
[19:00:25] ====================== test_for_each  ======================
[19:00:25] [PASSED] kernel
[19:00:25] [PASSED] write
[19:00:25] [PASSED] read
[19:00:25] [PASSED] bookkeep
[19:00:25] ================== [PASSED] test_for_each ==================
[19:00:25] ================= test_for_each_unlocked  ==================
[19:00:25] [PASSED] kernel
[19:00:25] [PASSED] write
[19:00:25] [PASSED] read
[19:00:25] [PASSED] bookkeep
[19:00:25] ============= [PASSED] test_for_each_unlocked ==============
[19:00:25] ===================== test_get_fences  =====================
[19:00:25] [PASSED] kernel
[19:00:25] [PASSED] write
[19:00:25] [PASSED] read
[19:00:25] [PASSED] bookkeep
[19:00:25] ================= [PASSED] test_get_fences =================
[19:00:25] ================== [PASSED] dma-buf-resv ===================
[19:00:25] ============================================================
[19:00:25] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[19:00:25] Elapsed time: 15.814s total, 1.847s configuring, 8.696s building, 5.263s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel