* [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework
@ 2026-10-14 10:53 Mika Kahola
2026-10-14 10:53 ` [PATCH v2 1/4] drm/i915/dpll: move " Mika Kahola
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Mika Kahola @ 2026-10-14 10:53 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, Mika Kahola
This is v2 of [1], with the following changes
- apply WA to all ports with C10 phy connected. With this change
the WCL with C10 phy on both ports A and B is now supported.
[1] https://lore.kernel.org/intel-xe/20261009103552.1864818-1-mika.kahola@intel.com/
Mika Kahola (4):
drm/i915/dpll: move the PLL power save W/A to the display W/A
framework
drm/i915/lt_phy: split out intel_lt_phy_pll_calc_state_from_table()
drm/i915/lt_phy: drop the unused pll argument from
intel_lt_phy_pll_enable()
drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 60 ++++------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
.../drm/i915/display/intel_display_reset.c | 4 +-
.../gpu/drm/i915/display/intel_display_wa.c | 2 +
.../gpu/drm/i915/display/intel_display_wa.h | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 34 +++++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
drivers/gpu/drm/i915/display/intel_lt_phy.c | 103 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 +-
9 files changed, 136 insertions(+), 73 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/4] drm/i915/dpll: move the PLL power save W/A to the display W/A framework
2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
@ 2026-10-14 10:53 ` Mika Kahola
2026-10-14 13:45 ` Mika Kahola
2026-10-14 10:53 ` [PATCH v2 2/4] drm/i915/lt_phy: split out intel_lt_phy_pll_calc_state_from_table() Mika Kahola
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Mika Kahola @ 2026-10-14 10:53 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, Mika Kahola
The condition for W/A 14022081154 was open-coded as a DISPLAY_VER()
check in intel_cx0_pll_power_save_wa(), which also walked the encoders
itself. Neither is specific to the C10 PHY.
Add intel_dpll_power_save_wa(), holding the W/A condition as
INTEL_DISPLAY_WA_14022081154 and the encoder walk, and leave
intel_cx0_pll_power_save_wa() with only the C10 PHY sequence for a
single encoder.
The spec lists the W/A for PTL+, so use DISPLAY_VER() >= 30 instead of
the == 30 the code had. No functional change: the sequence is C10 PHY
specific and intel_encoder_is_c10phy() is never true on display ver 35.
While at it, let the drm_WARN_ON() on the table lookup check the return
value.
BSpec: 74151
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 60 +++++++------------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
.../drm/i915/display/intel_display_reset.c | 4 +-
.../gpu/drm/i915/display/intel_display_wa.c | 2 +
.../gpu/drm/i915/display/intel_display_wa.h | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 31 +++++++++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
7 files changed, 57 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b83f0afaa9b5..73162b3cfc1e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3700,54 +3700,34 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
/*
* WA 14022081154
- * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle
- * system power. After a system reset (cold boot, S3/4/5, warm reset) if a dedicated
- * PHY is not being brought up shortly, use these steps to move the PHY to the lowest
- * power state to save power. For PTL the workaround is needed only for port A. Port B
- * is not connected.
- *
- * 1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.
- * This brings lanes out of reset and enables the PLL to allow powerdown to be moved
- * to the Disable state.
- * 2. Follow PLL Disable Sequence. This moves powerdown to the Disable state and disables the PLL.
+ * C10 PHY part of the sequence, see intel_dpll_power_save_wa().
*/
-void intel_cx0_pll_power_save_wa(struct intel_display *display)
+void intel_cx0_pll_power_save_wa(struct intel_encoder *encoder)
{
- struct intel_encoder *encoder;
+ struct intel_display *display = to_intel_display(encoder);
+ struct intel_cx0pll_state pll_state = {};
+ int port_clock = 162000;
+ int lane_count = 4;
+ int err;
- if (DISPLAY_VER(display) != 30)
+ if (!intel_encoder_is_c10phy(encoder))
return;
- for_each_intel_encoder(display->drm, encoder) {
- struct intel_cx0pll_state pll_state = {};
- int port_clock = 162000;
- int lane_count = 4;
-
- if (!intel_encoder_is_dig_port(encoder))
- continue;
-
- if (!intel_encoder_is_c10phy(encoder))
- continue;
-
- if (intel_cx0_pll_is_enabled(encoder))
- continue;
+ if (intel_cx0_pll_is_enabled(encoder))
+ return;
- if (intel_c10pll_calc_state_from_table(encoder,
- mtl_c10_edp_tables,
- true, port_clock, lane_count,
- &pll_state) < 0) {
- drm_WARN_ON(display->drm,
- "Unable to calc C10 state from the tables\n");
- continue;
- }
+ err = intel_c10pll_calc_state_from_table(encoder, mtl_c10_edp_tables,
+ true, port_clock, lane_count,
+ &pll_state);
+ if (drm_WARN_ON(display->drm, err))
+ return;
- drm_dbg_kms(display->drm,
- "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
- encoder->base.base.id, encoder->base.name);
+ drm_dbg_kms(display->drm,
+ "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
+ encoder->base.base.id, encoder->base.name);
- intel_cx0pll_enable(encoder, &pll_state);
- intel_cx0pll_disable(encoder);
- }
+ intel_cx0pll_enable(encoder, &pll_state);
+ intel_cx0pll_disable(encoder);
}
static void intel_c10pll_verify_clock(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 95c20eb4b4b7..b63916bfeca7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -78,7 +78,7 @@ bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
void intel_cx0pll_verify_plls(struct intel_display *display);
-void intel_cx0_pll_power_save_wa(struct intel_display *display);
+void intel_cx0_pll_power_save_wa(struct intel_encoder *encoder);
void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c
index 504ec7043cd9..375201798413 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reset.c
+++ b/drivers/gpu/drm/i915/display/intel_display_reset.c
@@ -9,12 +9,12 @@
#include <drm/drm_print.h>
#include "intel_clock_gating.h"
-#include "intel_cx0_phy.h"
#include "intel_display_core.h"
#include "intel_display_driver.h"
#include "intel_display_reset.h"
#include "intel_display_types.h"
#include "intel_display_utils.h"
+#include "intel_dpll_mgr.h"
#include "intel_hotplug.h"
#include "intel_pps.h"
@@ -100,7 +100,7 @@ void intel_display_reset_finish(struct intel_display *display, bool test_only)
intel_pps_unlock_regs_wa(display);
intel_display_driver_init_hw(display);
intel_clock_gating_init(display->drm);
- intel_cx0_pll_power_save_wa(display);
+ intel_dpll_power_save_wa(display);
intel_hpd_init(display);
ret = __intel_display_driver_resume(display, state, ctx);
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 888676693f5e..eeddf10a4071 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -111,6 +111,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
return DISPLAY_VERx100(display) == 3000 ||
DISPLAY_VERx100(display) == 2000 ||
DISPLAY_VERx100(display) == 1401;
+ case INTEL_DISPLAY_WA_14022081154:
+ return DISPLAY_VER(display) >= 30;
case INTEL_DISPLAY_WA_14025769978:
return DISPLAY_VER(display) == 35;
case INTEL_DISPLAY_WA_14026643300:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index 425a300840aa..acb45fa59aef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -33,6 +33,7 @@ enum intel_display_wa {
INTEL_DISPLAY_WA_14014143976,
INTEL_DISPLAY_WA_14016740474,
INTEL_DISPLAY_WA_14020863754,
+ INTEL_DISPLAY_WA_14022081154,
INTEL_DISPLAY_WA_14025769978,
INTEL_DISPLAY_WA_14026643300,
INTEL_DISPLAY_WA_15013987218,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bfd6f0a19725..e899b2eb0871 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -33,6 +33,7 @@
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_display_utils.h"
+#include "intel_display_wa.h"
#include "intel_dkl_phy.h"
#include "intel_dkl_phy_regs.h"
#include "intel_dpio_phy.h"
@@ -5220,12 +5221,40 @@ static void sanitize_dpll_state(struct intel_display *display,
_intel_disable_shared_dpll(display, pll);
}
+/*
+ * WA 14022081154
+ * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle
+ * system power. After a system reset (cold boot, S3/4/5, warm reset) if a dedicated
+ * PHY is not being brought up shortly, use these steps to move the PHY to the lowest
+ * power state to save power. For PTL the workaround is needed only for port A. Port B
+ * is not connected.
+ *
+ * 1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.
+ * This brings lanes out of reset and enables the PLL to allow powerdown to be moved
+ * to the Disable state.
+ * 2. Follow PLL Disable Sequence. This moves powerdown to the Disable state and disables the PLL.
+ */
+void intel_dpll_power_save_wa(struct intel_display *display)
+{
+ struct intel_encoder *encoder;
+
+ if (!intel_display_wa(display, INTEL_DISPLAY_WA_14022081154))
+ return;
+
+ for_each_intel_encoder(display->drm, encoder) {
+ if (!intel_encoder_is_dig_port(encoder))
+ continue;
+
+ intel_cx0_pll_power_save_wa(encoder);
+ }
+}
+
void intel_dpll_sanitize_state(struct intel_display *display)
{
struct intel_dpll *pll;
int i;
- intel_cx0_pll_power_save_wa(display);
+ intel_dpll_power_save_wa(display);
for_each_dpll(display, pll, i)
sanitize_dpll_state(display, pll);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f4b84733a58c..0beb8d99fd5e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -461,6 +461,7 @@ void intel_dpll_swap_state(struct intel_atomic_state *state);
void intel_dpll_init(struct intel_display *display);
void intel_dpll_update_ref_clks(struct intel_display *display);
void intel_dpll_readout_hw_state(struct intel_display *display);
+void intel_dpll_power_save_wa(struct intel_display *display);
void intel_dpll_sanitize_state(struct intel_display *display);
void intel_dpll_dump_hw_state(struct intel_display *display,
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/4] drm/i915/lt_phy: split out intel_lt_phy_pll_calc_state_from_table()
2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
2026-10-14 10:53 ` [PATCH v2 1/4] drm/i915/dpll: move " Mika Kahola
@ 2026-10-14 10:53 ` Mika Kahola
2026-10-14 10:53 ` [PATCH v2 3/4] drm/i915/lt_phy: drop the unused pll argument from intel_lt_phy_pll_enable() Mika Kahola
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Mika Kahola @ 2026-10-14 10:53 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, Mika Kahola
The PLL table walk in intel_lt_phy_pll_calc_state() is only reachable
with a crtc_state. Split it into a helper taking the port clock and
lane count directly, and pass the output type in as is_dp/is_edp, like
intel_c10pll_calc_state_from_table() on the C10 side.
intel_lt_phy_pll_is_ssc_enabled() loses its crtc_state argument for the
same reason, matching intel_cx0pll_update_ssc().
No functional change.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_lt_phy.c | 71 +++++++++++++--------
1 file changed, 45 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 86492651b01d..c626246b71f9 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1329,12 +1329,11 @@ intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
}
static bool
-intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
- struct intel_encoder *encoder)
+intel_lt_phy_pll_is_ssc_enabled(struct intel_encoder *encoder, bool is_dp)
{
struct intel_display *display = to_intel_display(encoder);
- if (intel_crtc_has_dp_encoder(crtc_state)) {
+ if (is_dp) {
if (intel_panel_use_ssc(display)) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -1740,14 +1739,45 @@ intel_lt_phy_calc_port_clock(struct intel_display *display,
return clk;
}
+static int
+intel_lt_phy_pll_calc_state_from_table(struct intel_encoder *encoder,
+ const struct intel_lt_phy_pll_params *tables,
+ bool is_dp, bool is_edp,
+ int port_clock, int lane_count,
+ struct intel_lt_phy_pll_state *pll_state)
+{
+ struct intel_display *display = to_intel_display(encoder);
+ int i;
+
+ for (i = 0; tables[i].name; i++) {
+ int clock = intel_lt_phy_calc_port_clock(display, tables[i].state);
+
+ drm_WARN_ON(display->drm, !intel_dpll_clock_matches(clock, tables[i].clock_rate));
+ if (intel_dpll_clock_matches(port_clock, clock)) {
+ *pll_state = *tables[i].state;
+
+ if (is_edp)
+ pll_state->config[2] = 1;
+
+ pll_state->ssc_enabled = intel_lt_phy_pll_is_ssc_enabled(encoder, is_dp);
+ pll_state->lane_count = lane_count;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
int
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder,
struct intel_dpll_hw_state *hw_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
+ bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
+ bool is_edp = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP);
const struct intel_lt_phy_pll_params *tables;
- int i;
+ int err;
memset(hw_state, 0, sizeof(*hw_state));
@@ -1755,30 +1785,19 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
if (!tables)
return -EINVAL;
- for (i = 0; tables[i].name; i++) {
- int clock = intel_lt_phy_calc_port_clock(display, tables[i].state);
+ err = intel_lt_phy_pll_calc_state_from_table(encoder, tables, is_dp, is_edp,
+ crtc_state->port_clock,
+ crtc_state->lane_count,
+ &hw_state->ltpll);
- drm_WARN_ON(display->drm, !intel_dpll_clock_matches(clock, tables[i].clock_rate));
- if (intel_dpll_clock_matches(crtc_state->port_clock, clock)) {
- hw_state->ltpll = *tables[i].state;
- if (intel_crtc_has_dp_encoder(crtc_state)) {
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
- hw_state->ltpll.config[2] = 1;
- }
- hw_state->ltpll.ssc_enabled =
- intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
- hw_state->ltpll.lane_count = crtc_state->lane_count;
- return 0;
- }
- }
+ if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return err;
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
- hw_state->ltpll.lane_count = crtc_state->lane_count;
- return intel_lt_phy_calculate_hdmi_state(&hw_state->ltpll,
- crtc_state->port_clock);
- }
+ /* For HDMI PLLs use the HDMI algorithm, if there are no precomputed tables */
+ hw_state->ltpll.lane_count = crtc_state->lane_count;
- return -EINVAL;
+ return intel_lt_phy_calculate_hdmi_state(&hw_state->ltpll,
+ crtc_state->port_clock);
}
void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state)
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/4] drm/i915/lt_phy: drop the unused pll argument from intel_lt_phy_pll_enable()
2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
2026-10-14 10:53 ` [PATCH v2 1/4] drm/i915/dpll: move " Mika Kahola
2026-10-14 10:53 ` [PATCH v2 2/4] drm/i915/lt_phy: split out intel_lt_phy_pll_calc_state_from_table() Mika Kahola
@ 2026-10-14 10:53 ` Mika Kahola
2026-10-14 10:58 ` sashiko-bot
2026-10-14 10:53 ` [PATCH v2 4/4] drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms Mika Kahola
` (4 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Mika Kahola @ 2026-10-14 10:53 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, Mika Kahola
intel_lt_phy_pll_enable() never looks at the pll, it is there only
because intel_xe3plpd_pll_enable() forwards its own arguments. Drop it
so callers that have no pll do not have to pass NULL.
No functional change.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_lt_phy.c | 3 +--
drivers/gpu/drm/i915/display/intel_lt_phy.h | 1 -
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index c626246b71f9..e05fd23b8a65 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1924,7 +1924,6 @@ intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
}
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
- struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_display *display = to_intel_display(encoder);
@@ -2300,7 +2299,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state);
+ intel_lt_phy_pll_enable(encoder, dpll_hw_state);
}
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 16de39484779..368ceedb1e0a 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -19,7 +19,6 @@ struct intel_crtc;
struct intel_lt_phy_pll_state;
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
- struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
int
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/4] drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms
2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
` (2 preceding siblings ...)
2026-10-14 10:53 ` [PATCH v2 3/4] drm/i915/lt_phy: drop the unused pll argument from intel_lt_phy_pll_enable() Mika Kahola
@ 2026-10-14 10:53 ` Mika Kahola
2026-10-14 11:10 ` sashiko-bot
2026-10-14 13:46 ` Mika Kahola
2026-10-14 11:26 ` ✓ CI.KUnit: success for Move the PLL power save W/A to the display W/A framework (rev2) Patchwork
` (3 subsequent siblings)
7 siblings, 2 replies; 13+ messages in thread
From: Mika Kahola @ 2026-10-14 10:53 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: imre.deak, Mika Kahola
W/A 14022081154 covers PTL+, but only the C10 PHY sequence was ever
implemented. Port A is an LT PHY on display ver 35, so
intel_dpll_power_save_wa() had nothing to run there and the PHY was
left in the reset power state that blocks S0ix.
Add the LT PHY sequence and dispatch on the PHY type. The PLL state is
calculated from the eDP tables at RBR as the C10 sequence does, so the
throwaway state it brings the PLL up with is marked as eDP.
BSpec: 74151
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++-
drivers/gpu/drm/i915/display/intel_lt_phy.c | 29 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_lt_phy.h | 1 +
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e899b2eb0871..9f34574775da 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -5245,7 +5245,10 @@ void intel_dpll_power_save_wa(struct intel_display *display)
if (!intel_encoder_is_dig_port(encoder))
continue;
- intel_cx0_pll_power_save_wa(encoder);
+ if (HAS_LT_PHY(display))
+ intel_lt_phy_pll_power_save_wa(encoder);
+ else
+ intel_cx0_pll_power_save_wa(encoder);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index e05fd23b8a65..d286d33a03ea 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2313,6 +2313,35 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
}
+/*
+ * WA 14022081154
+ * LT PHY part of the sequence, see intel_dpll_power_save_wa().
+ */
+void intel_lt_phy_pll_power_save_wa(struct intel_encoder *encoder)
+{
+ struct intel_display *display = to_intel_display(encoder);
+ struct intel_dpll_hw_state hw_state = {};
+ int port_clock = 162000;
+ int lane_count = 4;
+ int err;
+
+ if (intel_lt_phy_pll_is_enabled(encoder))
+ return;
+
+ err = intel_lt_phy_pll_calc_state_from_table(encoder, xe3plpd_lt_edp_tables,
+ true, true, port_clock, lane_count,
+ &hw_state.ltpll);
+ if (drm_WARN_ON(display->drm, err))
+ return;
+
+ drm_dbg_kms(display->drm,
+ "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
+ encoder->base.base.id, encoder->base.name);
+
+ intel_lt_phy_pll_enable(encoder, &hw_state);
+ intel_lt_phy_pll_disable(encoder);
+}
+
static void intel_lt_phy_pll_verify_clock(struct intel_display *display,
int precomputed_clock,
const char *pll_state_name,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 368ceedb1e0a..a918012b71e8 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -47,6 +47,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
+void intel_lt_phy_pll_power_save_wa(struct intel_encoder *encoder);
void intel_lt_phy_verify_plls(struct intel_display *display);
#endif /* __INTEL_LT_PHY_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/4] drm/i915/lt_phy: drop the unused pll argument from intel_lt_phy_pll_enable()
2026-10-14 10:53 ` [PATCH v2 3/4] drm/i915/lt_phy: drop the unused pll argument from intel_lt_phy_pll_enable() Mika Kahola
@ 2026-10-14 10:58 ` sashiko-bot
0 siblings, 0 replies; 13+ messages in thread
From: sashiko-bot @ 2026-10-14 10:58 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Unnecessary dead argument left in intel_xe3plpd_pll_enable()
--
commit f2396c693af5e8056514c60f30bea8044eae04b7
Author: Mika Kahola <mika.kahola@intel.com>
drm/i915/lt_phy: drop the unused pll argument from intel_lt_phy_pll_enable()
intel_lt_phy_pll_enable() never looks at the pll, it is there only
because intel_xe3plpd_pll_enable() forwards its own arguments. Drop it
so callers that have no pll do not have to pass NULL.
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index c626246b71f91..e05fd23b8a651 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
[ ... ]
> @@ -2300,7 +2299,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> - intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state);
> + intel_lt_phy_pll_enable(encoder, dpll_hw_state);
> }
[Severity: Low]
Could we also drop the pll argument from intel_xe3plpd_pll_enable()?
Since the commit message mentions that intel_lt_phy_pll_enable() only had it
because intel_xe3plpd_pll_enable() forwards its own arguments, leaving it in
intel_xe3plpd_pll_enable() means we still have a dead argument here.
Dropping it from intel_xe3plpd_pll_enable() (and its caller in
intel_dpll_mgr.c) would make the API consistent, especially since its
counterpart intel_xe3plpd_pll_disable() takes only an encoder.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261014105306.2761683-1-mika.kahola@intel.com?part=3
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 4/4] drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms
2026-10-14 10:53 ` [PATCH v2 4/4] drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms Mika Kahola
@ 2026-10-14 11:10 ` sashiko-bot
2026-10-14 13:46 ` Mika Kahola
1 sibling, 0 replies; 13+ messages in thread
From: sashiko-bot @ 2026-10-14 11:10 UTC (permalink / raw)
To: Mika Kahola, intel-gfx, intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/lt_phy: missing TBT alt mode check in power save W/A
--
commit 64f624396c6597f36365729f25b701c8533785f7
Author: Mika Kahola <mika.kahola@intel.com>
drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms
This commit adds the LT PHY sequence for the PLL power save workaround
and dispatches based on the PHY type. The PLL state is calculated from the eDP
tables at RBR as the C10 sequence does.
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e899b2eb08711..9f34574775da2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -5245,7 +5245,10 @@ void intel_dpll_power_save_wa(struct intel_display *display)
> if (!intel_encoder_is_dig_port(encoder))
> continue;
>
> - intel_cx0_pll_power_save_wa(encoder);
> + if (HAS_LT_PHY(display))
> + intel_lt_phy_pll_power_save_wa(encoder);
> + else
> + intel_cx0_pll_power_save_wa(encoder);
[Severity: High]
Does this platform-wide dispatch route all digital ports to the LT PHY
workaround on platforms with HAS_LT_PHY(display), including TC ports?
It appears this checks the platform capability rather than the actual PHY type
of the encoder, which may lead to applying the LT PHY workaround unconditionally
across different digital ports.
[ ... ]
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index e05fd23b8a651..d286d33a03eae 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2313,6 +2313,35 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
>
> }
>
> +/*
> + * WA 14022081154
> + * LT PHY part of the sequence, see intel_dpll_power_save_wa().
> + */
> +void intel_lt_phy_pll_power_save_wa(struct intel_encoder *encoder)
> +{
[ ... ]
> + drm_dbg_kms(display->drm,
> + "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
> + encoder->base.base.id, encoder->base.name);
> +
> + intel_lt_phy_pll_enable(encoder, &hw_state);
> + intel_lt_phy_pll_disable(encoder);
[Severity: High]
Can this bypass TBT alt mode checks and corrupt Thunderbolt-owned shared port
registers?
During driver initialization and reset sequences (such as intel_display_reset()
calling intel_dpll_power_save_wa()), this executes automatically. If the system
boots with an active TBT alt mode display, the LT PHY PLL is likely disabled
since TBT uses a separate clocking path.
This causes intel_lt_phy_pll_is_enabled(encoder) to return false, leading to
blindly executing intel_lt_phy_pll_enable() and intel_lt_phy_pll_disable().
Without the intel_tc_port_in_tbt_alt_mode() safety guard found in other
functions like intel_xe3plpd_pll_disable(), this bypass might overwrite the
port's clock select mask and assert MacCLK resets, potentially breaking active
TBT displays.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261014105306.2761683-1-mika.kahola@intel.com?part=4
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ CI.KUnit: success for Move the PLL power save W/A to the display W/A framework (rev2)
2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
` (3 preceding siblings ...)
2026-10-14 10:53 ` [PATCH v2 4/4] drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms Mika Kahola
@ 2026-10-14 11:26 ` Patchwork
2026-10-14 11:48 ` ✓ i915.CI.BAT: " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-10-14 11:26 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-xe
== Series Details ==
Series: Move the PLL power save W/A to the display W/A framework (rev2)
URL : https://patchwork.freedesktop.org/series/175834/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[11:24:20] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:24:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:24:45] Starting KUnit Kernel (1/1)...
[11:24:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:24:45] ================= gpu_buddy (14 subtests) ==================
[11:24:45] [PASSED] gpu_test_buddy_alloc_limit
[11:24:45] [PASSED] gpu_test_buddy_alloc_optimistic
[11:24:45] [PASSED] gpu_test_buddy_alloc_pessimistic
[11:24:45] [PASSED] gpu_test_buddy_alloc_pathological
[11:24:45] [PASSED] gpu_test_buddy_alloc_contiguous
[11:24:45] [PASSED] gpu_test_buddy_alloc_clear
[11:24:45] [PASSED] gpu_test_buddy_alloc_range
[11:24:45] [PASSED] gpu_test_buddy_alloc_range_bias
[11:24:46] [PASSED] gpu_test_buddy_fragmentation_performance
[11:24:47] [PASSED] gpu_test_buddy_dirty_tracker_performance
[11:24:47] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[11:24:47] [PASSED] gpu_test_buddy_offset_aligned_allocation
[11:24:47] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[11:24:47] [PASSED] gpu_test_buddy_addr_to_block
[11:24:47] ==================== [PASSED] gpu_buddy ====================
[11:24:47] ============================================================
[11:24:47] Testing complete. Ran 14 tests: passed: 14
[11:24:47] Elapsed time: 27.110s total, 4.439s configuring, 20.752s building, 1.860s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:24:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:24:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:25:23] Starting KUnit Kernel (1/1)...
[11:25:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:25:24] ================== guc_buf (11 subtests) ===================
[11:25:24] [PASSED] test_smallest
[11:25:24] [PASSED] test_largest
[11:25:24] [PASSED] test_granular
[11:25:24] [PASSED] test_unique
[11:25:24] [PASSED] test_overlap
[11:25:24] [PASSED] test_reusable
[11:25:24] [PASSED] test_too_big
[11:25:24] [PASSED] test_flush
[11:25:24] [PASSED] test_lookup
[11:25:24] [PASSED] test_data
[11:25:24] [PASSED] test_class
[11:25:24] ===================== [PASSED] guc_buf =====================
[11:25:24] =================== guc_dbm (7 subtests) ===================
[11:25:24] [PASSED] test_empty
[11:25:24] [PASSED] test_default
[11:25:24] ======================== test_size ========================
[11:25:24] [PASSED] 4
[11:25:24] [PASSED] 8
[11:25:24] [PASSED] 32
[11:25:24] [PASSED] 256
[11:25:24] ==================== [PASSED] test_size ====================
[11:25:24] ======================= test_reuse ========================
[11:25:24] [PASSED] 4
[11:25:24] [PASSED] 8
[11:25:24] [PASSED] 32
[11:25:24] [PASSED] 256
[11:25:24] =================== [PASSED] test_reuse ====================
[11:25:24] =================== test_range_overlap ====================
[11:25:24] [PASSED] 4
[11:25:24] [PASSED] 8
[11:25:24] [PASSED] 32
[11:25:24] [PASSED] 256
[11:25:24] =============== [PASSED] test_range_overlap ================
[11:25:24] =================== test_range_compact ====================
[11:25:24] [PASSED] 4
[11:25:24] [PASSED] 8
[11:25:24] [PASSED] 32
[11:25:24] [PASSED] 256
[11:25:24] =============== [PASSED] test_range_compact ================
[11:25:24] ==================== test_range_spare =====================
[11:25:24] [PASSED] 4
[11:25:24] [PASSED] 8
[11:25:24] [PASSED] 32
[11:25:24] [PASSED] 256
[11:25:24] ================ [PASSED] test_range_spare =================
[11:25:24] ===================== [PASSED] guc_dbm =====================
[11:25:24] =================== guc_idm (6 subtests) ===================
[11:25:24] [PASSED] bad_init
[11:25:24] [PASSED] no_init
[11:25:24] [PASSED] init_fini
[11:25:24] [PASSED] check_used
[11:25:24] [PASSED] check_quota
[11:25:24] [PASSED] check_all
[11:25:24] ===================== [PASSED] guc_idm =====================
[11:25:24] ============== guc_klv_helpers (13 subtests) ===============
[11:25:24] [PASSED] test_count
[11:25:24] [PASSED] test_encode_u32
[11:25:24] [PASSED] test_encode_u64
[11:25:24] [PASSED] test_encode_string
[11:25:24] [PASSED] test_encode_object_raw
[11:25:24] [PASSED] test_encode_object_klv
[11:25:24] [PASSED] test_encode_object_nested
[11:25:24] [PASSED] test_encode_object_basic
[11:25:24] ===================== test_decode_u16 =====================
[11:25:24] [PASSED] empty
[11:25:24] [PASSED] valid
[11:25:24] [PASSED] max
[11:25:24] [PASSED] big
[11:25:24] [PASSED] long
[11:25:24] ================= [PASSED] test_decode_u16 =================
[11:25:24] ===================== test_decode_u32 =====================
[11:25:24] [PASSED] empty
[11:25:24] [PASSED] valid
[11:25:24] [PASSED] max
[11:25:24] [PASSED] long
[11:25:24] ================= [PASSED] test_decode_u32 =================
[11:25:24] ===================== test_decode_u64 =====================
[11:25:24] [PASSED] empty
[11:25:24] [PASSED] short
[11:25:24] [PASSED] valid
[11:25:24] [PASSED] max
[11:25:24] [PASSED] long
[11:25:24] ================= [PASSED] test_decode_u64 =================
[11:25:24] ===================== test_decode_str =====================
[11:25:24] [PASSED] empty
[11:25:24] [PASSED] one
[11:25:24] [PASSED] one_trash
[11:25:24] [PASSED] two
[11:25:24] [PASSED] two_trash
[11:25:24] [PASSED] three
[11:25:24] [PASSED] dword
[11:25:24] [PASSED] four
[11:25:24] [PASSED] five
[11:25:24] [PASSED] six
[11:25:24] [PASSED] seven
[11:25:24] [PASSED] qword
[11:25:24] ================= [PASSED] test_decode_str =================
[11:25:24] [PASSED] test_print
[11:25:24] ================= [PASSED] guc_klv_helpers =================
[11:25:24] =================== xe_log (4 subtests) ====================
[11:25:24] [PASSED] demo_cper
[11:25:24] [PASSED] demo_dmesg
[11:25:24] ======================= test_dmesg ========================
[11:25:24] [PASSED] test_fatal
[11:25:24] [PASSED] test_fatal_tile
[11:25:24] [PASSED] test_fatal_gt
[11:25:24] [PASSED] test_fatal_comp
[11:25:24] [PASSED] test_fatal_comp_tile
[11:25:24] [PASSED] test_fatal_comp_gt
[11:25:24] [PASSED] test_fatal_all
[11:25:24] [PASSED] test_recoverable
[11:25:24] [PASSED] test_recoverable_tile
[11:25:24] [PASSED] test_recoverable_gt
[11:25:24] [PASSED] test_recoverable_comp
[11:25:24] [PASSED] test_recoverable_comp_tile
[11:25:24] [PASSED] test_recoverable_comp_gt
[11:25:24] [PASSED] test_recoverable_all
[11:25:24] [PASSED] test_info
[11:25:24] [PASSED] test_info_tile
[11:25:24] [PASSED] test_info_gt
[11:25:24] [PASSED] test_info_err
[11:25:24] [PASSED] test_info_comp
[11:25:24] [PASSED] test_info_comp_tile
[11:25:24] [PASSED] test_info_comp_gt
[11:25:24] [PASSED] test_info_all
[11:25:24] [PASSED] test_hw_fatal
[11:25:24] [PASSED] test_hw_recoverable
[11:25:24] [PASSED] test_hw_corrected
[11:25:24] [PASSED] test_hw_informational
[11:25:24] =================== [PASSED] test_dmesg ====================
[11:25:24] ====================== test_invalid =======================
[11:25:24] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[11:25:24] ================== [SKIPPED] test_invalid ==================
[11:25:24] ===================== [PASSED] xe_log ======================
[11:25:24] ================== no_relay (3 subtests) ===================
[11:25:24] [PASSED] xe_drops_guc2pf_if_not_ready
[11:25:24] [PASSED] xe_drops_guc2vf_if_not_ready
[11:25:24] [PASSED] xe_rejects_send_if_not_ready
[11:25:24] ==================== [PASSED] no_relay =====================
[11:25:24] ================== pf_relay (14 subtests) ==================
[11:25:24] [PASSED] pf_rejects_guc2pf_too_short
[11:25:24] [PASSED] pf_rejects_guc2pf_too_long
[11:25:24] [PASSED] pf_rejects_guc2pf_no_payload
[11:25:24] [PASSED] pf_fails_no_payload
[11:25:24] [PASSED] pf_fails_bad_origin
[11:25:24] [PASSED] pf_fails_bad_type
[11:25:24] [PASSED] pf_txn_reports_error
[11:25:24] [PASSED] pf_txn_sends_pf2guc
[11:25:24] [PASSED] pf_sends_pf2guc
[11:25:24] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:25:24] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:25:24] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:25:24] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:25:24] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:25:24] ==================== [PASSED] pf_relay =====================
[11:25:24] ================== vf_relay (3 subtests) ===================
[11:25:24] [PASSED] vf_rejects_guc2vf_too_short
[11:25:24] [PASSED] vf_rejects_guc2vf_too_long
[11:25:24] [PASSED] vf_rejects_guc2vf_no_payload
[11:25:24] ==================== [PASSED] vf_relay =====================
[11:25:24] ================ pf_gt_config (9 subtests) =================
[11:25:24] [PASSED] fair_contexts_1vf
[11:25:24] [PASSED] fair_doorbells_1vf
[11:25:24] [PASSED] fair_ggtt_1vf
[11:25:24] ====================== fair_vram_1vf ======================
[11:25:24] [PASSED] 3.50 GiB
[11:25:24] [PASSED] 11.5 GiB
[11:25:24] [PASSED] 15.5 GiB
[11:25:24] [PASSED] 31.5 GiB
[11:25:24] [PASSED] 63.5 GiB
[11:25:24] [PASSED] 1.91 GiB
[11:25:24] ================== [PASSED] fair_vram_1vf ==================
[11:25:24] ================ fair_vram_1vf_admin_only =================
[11:25:24] [PASSED] 3.50 GiB
[11:25:24] [PASSED] 11.5 GiB
[11:25:24] [PASSED] 15.5 GiB
[11:25:24] [PASSED] 31.5 GiB
[11:25:24] [PASSED] 63.5 GiB
[11:25:24] [PASSED] 1.91 GiB
[11:25:24] ============ [PASSED] fair_vram_1vf_admin_only =============
[11:25:24] ====================== fair_contexts ======================
[11:25:24] [PASSED] 1 VF
[11:25:24] [PASSED] 2 VFs
[11:25:24] [PASSED] 3 VFs
[11:25:24] [PASSED] 4 VFs
[11:25:24] [PASSED] 5 VFs
[11:25:24] [PASSED] 6 VFs
[11:25:24] [PASSED] 7 VFs
[11:25:24] [PASSED] 8 VFs
[11:25:24] [PASSED] 9 VFs
[11:25:24] [PASSED] 10 VFs
[11:25:24] [PASSED] 11 VFs
[11:25:24] [PASSED] 12 VFs
[11:25:24] [PASSED] 13 VFs
[11:25:24] [PASSED] 14 VFs
[11:25:24] [PASSED] 15 VFs
[11:25:24] [PASSED] 16 VFs
[11:25:24] [PASSED] 17 VFs
[11:25:24] [PASSED] 18 VFs
[11:25:24] [PASSED] 19 VFs
[11:25:24] [PASSED] 20 VFs
[11:25:24] [PASSED] 21 VFs
[11:25:24] [PASSED] 22 VFs
[11:25:24] [PASSED] 23 VFs
[11:25:24] [PASSED] 24 VFs
[11:25:24] [PASSED] 25 VFs
[11:25:24] [PASSED] 26 VFs
[11:25:24] [PASSED] 27 VFs
[11:25:24] [PASSED] 28 VFs
[11:25:24] [PASSED] 29 VFs
[11:25:24] [PASSED] 30 VFs
[11:25:24] [PASSED] 31 VFs
[11:25:24] [PASSED] 32 VFs
[11:25:24] [PASSED] 33 VFs
[11:25:24] [PASSED] 34 VFs
[11:25:24] [PASSED] 35 VFs
[11:25:24] [PASSED] 36 VFs
[11:25:24] [PASSED] 37 VFs
[11:25:24] [PASSED] 38 VFs
[11:25:24] [PASSED] 39 VFs
[11:25:24] [PASSED] 40 VFs
[11:25:24] [PASSED] 41 VFs
[11:25:24] [PASSED] 42 VFs
[11:25:24] [PASSED] 43 VFs
[11:25:24] [PASSED] 44 VFs
[11:25:24] [PASSED] 45 VFs
[11:25:24] [PASSED] 46 VFs
[11:25:24] [PASSED] 47 VFs
[11:25:24] [PASSED] 48 VFs
[11:25:24] [PASSED] 49 VFs
[11:25:24] [PASSED] 50 VFs
[11:25:24] [PASSED] 51 VFs
[11:25:24] [PASSED] 52 VFs
[11:25:24] [PASSED] 53 VFs
[11:25:24] [PASSED] 54 VFs
[11:25:24] [PASSED] 55 VFs
[11:25:24] [PASSED] 56 VFs
[11:25:24] [PASSED] 57 VFs
[11:25:24] [PASSED] 58 VFs
[11:25:24] [PASSED] 59 VFs
[11:25:24] [PASSED] 60 VFs
[11:25:24] [PASSED] 61 VFs
[11:25:24] [PASSED] 62 VFs
[11:25:24] [PASSED] 63 VFs
[11:25:24] ================== [PASSED] fair_contexts ==================
[11:25:24] ===================== fair_doorbells ======================
[11:25:24] [PASSED] 1 VF
[11:25:24] [PASSED] 2 VFs
[11:25:24] [PASSED] 3 VFs
[11:25:24] [PASSED] 4 VFs
[11:25:24] [PASSED] 5 VFs
[11:25:24] [PASSED] 6 VFs
[11:25:24] [PASSED] 7 VFs
[11:25:24] [PASSED] 8 VFs
[11:25:24] [PASSED] 9 VFs
[11:25:24] [PASSED] 10 VFs
[11:25:24] [PASSED] 11 VFs
[11:25:24] [PASSED] 12 VFs
[11:25:24] [PASSED] 13 VFs
[11:25:24] [PASSED] 14 VFs
[11:25:24] [PASSED] 15 VFs
[11:25:24] [PASSED] 16 VFs
[11:25:24] [PASSED] 17 VFs
[11:25:24] [PASSED] 18 VFs
[11:25:24] [PASSED] 19 VFs
[11:25:24] [PASSED] 20 VFs
[11:25:24] [PASSED] 21 VFs
[11:25:24] [PASSED] 22 VFs
[11:25:24] [PASSED] 23 VFs
[11:25:24] [PASSED] 24 VFs
[11:25:24] [PASSED] 25 VFs
[11:25:24] [PASSED] 26 VFs
[11:25:24] [PASSED] 27 VFs
[11:25:24] [PASSED] 28 VFs
[11:25:24] [PASSED] 29 VFs
[11:25:24] [PASSED] 30 VFs
[11:25:24] [PASSED] 31 VFs
[11:25:24] [PASSED] 32 VFs
[11:25:24] [PASSED] 33 VFs
[11:25:24] [PASSED] 34 VFs
[11:25:24] [PASSED] 35 VFs
[11:25:24] [PASSED] 36 VFs
[11:25:24] [PASSED] 37 VFs
[11:25:24] [PASSED] 38 VFs
[11:25:24] [PASSED] 39 VFs
[11:25:24] [PASSED] 40 VFs
[11:25:24] [PASSED] 41 VFs
[11:25:24] [PASSED] 42 VFs
[11:25:24] [PASSED] 43 VFs
[11:25:24] [PASSED] 44 VFs
[11:25:24] [PASSED] 45 VFs
[11:25:24] [PASSED] 46 VFs
[11:25:24] [PASSED] 47 VFs
[11:25:24] [PASSED] 48 VFs
[11:25:24] [PASSED] 49 VFs
[11:25:24] [PASSED] 50 VFs
[11:25:24] [PASSED] 51 VFs
[11:25:24] [PASSED] 52 VFs
[11:25:24] [PASSED] 53 VFs
[11:25:24] [PASSED] 54 VFs
[11:25:24] [PASSED] 55 VFs
[11:25:24] [PASSED] 56 VFs
[11:25:24] [PASSED] 57 VFs
[11:25:24] [PASSED] 58 VFs
[11:25:24] [PASSED] 59 VFs
[11:25:24] [PASSED] 60 VFs
[11:25:24] [PASSED] 61 VFs
[11:25:24] [PASSED] 62 VFs
[11:25:24] [PASSED] 63 VFs
[11:25:24] ================= [PASSED] fair_doorbells ==================
[11:25:24] ======================== fair_ggtt ========================
[11:25:24] [PASSED] 1 VF
[11:25:24] [PASSED] 2 VFs
[11:25:24] [PASSED] 3 VFs
[11:25:24] [PASSED] 4 VFs
[11:25:24] [PASSED] 5 VFs
[11:25:24] [PASSED] 6 VFs
[11:25:24] [PASSED] 7 VFs
[11:25:24] [PASSED] 8 VFs
[11:25:24] [PASSED] 9 VFs
[11:25:24] [PASSED] 10 VFs
[11:25:24] [PASSED] 11 VFs
[11:25:24] [PASSED] 12 VFs
[11:25:24] [PASSED] 13 VFs
[11:25:24] [PASSED] 14 VFs
[11:25:24] [PASSED] 15 VFs
[11:25:24] [PASSED] 16 VFs
[11:25:24] [PASSED] 17 VFs
[11:25:24] [PASSED] 18 VFs
[11:25:24] [PASSED] 19 VFs
[11:25:24] [PASSED] 20 VFs
[11:25:24] [PASSED] 21 VFs
[11:25:24] [PASSED] 22 VFs
[11:25:24] [PASSED] 23 VFs
[11:25:24] [PASSED] 24 VFs
[11:25:24] [PASSED] 25 VFs
[11:25:24] [PASSED] 26 VFs
[11:25:24] [PASSED] 27 VFs
[11:25:24] [PASSED] 28 VFs
[11:25:24] [PASSED] 29 VFs
[11:25:24] [PASSED] 30 VFs
[11:25:24] [PASSED] 31 VFs
[11:25:24] [PASSED] 32 VFs
[11:25:24] [PASSED] 33 VFs
[11:25:24] [PASSED] 34 VFs
[11:25:24] [PASSED] 35 VFs
[11:25:24] [PASSED] 36 VFs
[11:25:24] [PASSED] 37 VFs
[11:25:24] [PASSED] 38 VFs
[11:25:24] [PASSED] 39 VFs
[11:25:24] [PASSED] 40 VFs
[11:25:24] [PASSED] 41 VFs
[11:25:24] [PASSED] 42 VFs
[11:25:24] [PASSED] 43 VFs
[11:25:24] [PASSED] 44 VFs
[11:25:24] [PASSED] 45 VFs
[11:25:24] [PASSED] 46 VFs
[11:25:24] [PASSED] 47 VFs
[11:25:24] [PASSED] 48 VFs
[11:25:24] [PASSED] 49 VFs
[11:25:24] [PASSED] 50 VFs
[11:25:24] [PASSED] 51 VFs
[11:25:24] [PASSED] 52 VFs
[11:25:24] [PASSED] 53 VFs
[11:25:24] [PASSED] 54 VFs
[11:25:24] [PASSED] 55 VFs
[11:25:24] [PASSED] 56 VFs
[11:25:24] [PASSED] 57 VFs
[11:25:24] [PASSED] 58 VFs
[11:25:24] [PASSED] 59 VFs
[11:25:24] [PASSED] 60 VFs
[11:25:24] [PASSED] 61 VFs
[11:25:24] [PASSED] 62 VFs
[11:25:24] [PASSED] 63 VFs
[11:25:24] ==================== [PASSED] fair_ggtt ====================
[11:25:24] ======================== fair_vram ========================
[11:25:24] [PASSED] 1 VF
[11:25:24] [PASSED] 2 VFs
[11:25:24] [PASSED] 3 VFs
[11:25:24] [PASSED] 4 VFs
[11:25:24] [PASSED] 5 VFs
[11:25:24] [PASSED] 6 VFs
[11:25:24] [PASSED] 7 VFs
[11:25:24] [PASSED] 8 VFs
[11:25:24] [PASSED] 9 VFs
[11:25:24] [PASSED] 10 VFs
[11:25:24] [PASSED] 11 VFs
[11:25:24] [PASSED] 12 VFs
[11:25:24] [PASSED] 13 VFs
[11:25:24] [PASSED] 14 VFs
[11:25:24] [PASSED] 15 VFs
[11:25:24] [PASSED] 16 VFs
[11:25:24] [PASSED] 17 VFs
[11:25:24] [PASSED] 18 VFs
[11:25:24] [PASSED] 19 VFs
[11:25:24] [PASSED] 20 VFs
[11:25:24] [PASSED] 21 VFs
[11:25:24] [PASSED] 22 VFs
[11:25:24] [PASSED] 23 VFs
[11:25:24] [PASSED] 24 VFs
[11:25:24] [PASSED] 25 VFs
[11:25:24] [PASSED] 26 VFs
[11:25:24] [PASSED] 27 VFs
[11:25:24] [PASSED] 28 VFs
[11:25:24] [PASSED] 29 VFs
[11:25:24] [PASSED] 30 VFs
[11:25:24] [PASSED] 31 VFs
[11:25:24] [PASSED] 32 VFs
[11:25:24] [PASSED] 33 VFs
[11:25:24] [PASSED] 34 VFs
[11:25:24] [PASSED] 35 VFs
[11:25:24] [PASSED] 36 VFs
[11:25:24] [PASSED] 37 VFs
[11:25:24] [PASSED] 38 VFs
[11:25:24] [PASSED] 39 VFs
[11:25:24] [PASSED] 40 VFs
[11:25:24] [PASSED] 41 VFs
[11:25:24] [PASSED] 42 VFs
[11:25:24] [PASSED] 43 VFs
[11:25:24] [PASSED] 44 VFs
[11:25:24] [PASSED] 45 VFs
[11:25:24] [PASSED] 46 VFs
[11:25:24] [PASSED] 47 VFs
[11:25:24] [PASSED] 48 VFs
[11:25:24] [PASSED] 49 VFs
[11:25:24] [PASSED] 50 VFs
[11:25:24] [PASSED] 51 VFs
[11:25:24] [PASSED] 52 VFs
[11:25:24] [PASSED] 53 VFs
[11:25:24] [PASSED] 54 VFs
[11:25:24] [PASSED] 55 VFs
[11:25:24] [PASSED] 56 VFs
[11:25:24] [PASSED] 57 VFs
[11:25:24] [PASSED] 58 VFs
[11:25:24] [PASSED] 59 VFs
[11:25:24] [PASSED] 60 VFs
[11:25:24] [PASSED] 61 VFs
[11:25:24] [PASSED] 62 VFs
[11:25:24] [PASSED] 63 VFs
[11:25:24] ==================== [PASSED] fair_vram ====================
[11:25:24] ================== [PASSED] pf_gt_config ===================
[11:25:24] ===================== lmtt (1 subtest) =====================
[11:25:24] ======================== test_ops =========================
[11:25:24] [PASSED] 2-level
[11:25:24] [PASSED] multi-level
[11:25:24] ==================== [PASSED] test_ops =====================
[11:25:24] ====================== [PASSED] lmtt =======================
[11:25:24] ================= sriov_packet (1 subtest) =================
[11:25:24] [PASSED] test_descriptor_init
[11:25:24] ================== [PASSED] sriov_packet ===================
[11:25:24] ================= pf_service (11 subtests) =================
[11:25:24] [PASSED] pf_negotiate_any
[11:25:24] [PASSED] pf_negotiate_base_match
[11:25:24] [PASSED] pf_negotiate_base_newer
[11:25:24] [PASSED] pf_negotiate_base_next
[11:25:24] [SKIPPED] pf_negotiate_base_older (no older minor)
[11:25:24] [PASSED] pf_negotiate_base_prev
[11:25:24] [PASSED] pf_negotiate_latest_match
[11:25:24] [PASSED] pf_negotiate_latest_newer
[11:25:24] [PASSED] pf_negotiate_latest_next
[11:25:24] [SKIPPED] pf_negotiate_latest_older (no older minor)
[11:25:24] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[11:25:24] =================== [PASSED] pf_service ====================
[11:25:24] ================= xe_guc_g2g (2 subtests) ==================
[11:25:24] ============== xe_live_guc_g2g_kunit_default ==============
[11:25:24] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:25:24] ============== xe_live_guc_g2g_kunit_allmem ===============
[11:25:24] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:25:24] =================== [SKIPPED] xe_guc_g2g ===================
[11:25:24] =================== xe_mocs (2 subtests) ===================
[11:25:24] ================ xe_live_mocs_kernel_kunit ================
[11:25:24] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:25:24] ================ xe_live_mocs_reset_kunit =================
[11:25:24] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:25:24] ==================== [SKIPPED] xe_mocs =====================
[11:25:24] ================= xe_migrate (2 subtests) ==================
[11:25:24] ================= xe_migrate_sanity_kunit =================
[11:25:24] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:25:24] ================== xe_validate_ccs_kunit ==================
[11:25:24] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:25:24] =================== [SKIPPED] xe_migrate ===================
[11:25:24] ================== xe_dma_buf (1 subtest) ==================
[11:25:24] ==================== xe_dma_buf_kunit =====================
[11:25:24] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:25:24] =================== [SKIPPED] xe_dma_buf ===================
[11:25:24] ================= xe_bo_shrink (1 subtest) =================
[11:25:24] =================== xe_bo_shrink_kunit ====================
[11:25:24] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:25:24] ================== [SKIPPED] xe_bo_shrink ==================
[11:25:24] ==================== xe_bo (2 subtests) ====================
[11:25:24] ================== xe_ccs_migrate_kunit ===================
[11:25:24] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:25:24] ==================== xe_bo_evict_kunit ====================
[11:25:24] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:25:24] ===================== [SKIPPED] xe_bo ======================
[11:25:24] =================== xe_any (9 subtests) ====================
[11:25:24] [PASSED] test_to_xe
[11:25:24] [PASSED] test_to_dev
[11:25:24] [PASSED] test_to_pdev
[11:25:24] [PASSED] test_to_drm
[11:25:24] [PASSED] test_if_pdev
[11:25:24] [PASSED] test_if_xe
[11:25:24] [PASSED] test_if_tile
[11:25:24] [PASSED] test_if_gt
[11:25:24] [PASSED] test_to_id
[11:25:24] ===================== [PASSED] xe_any ======================
[11:25:24] ==================== args (13 subtests) ====================
[11:25:24] [PASSED] count_args_test
[11:25:24] [PASSED] call_args_example
[11:25:24] [PASSED] call_args_test
[11:25:24] [PASSED] drop_first_arg_example
[11:25:24] [PASSED] drop_first_arg_test
[11:25:24] [PASSED] first_arg_example
[11:25:24] [PASSED] first_arg_test
[11:25:24] [PASSED] last_arg_example
[11:25:24] [PASSED] last_arg_test
[11:25:24] [PASSED] pick_arg_example
[11:25:24] [PASSED] if_args_example
[11:25:24] [PASSED] if_args_test
[11:25:24] [PASSED] sep_comma_example
[11:25:24] ====================== [PASSED] args =======================
[11:25:24] =================== xe_pci (3 subtests) ====================
[11:25:24] ==================== check_graphics_ip ====================
[11:25:24] [PASSED] 12.00 Xe_LP
[11:25:24] [PASSED] 12.10 Xe_LP+
[11:25:24] [PASSED] 12.55 Xe_HPG
[11:25:24] [PASSED] 12.60 Xe_HPC
[11:25:24] [PASSED] 12.70 Xe_LPG
[11:25:24] [PASSED] 12.71 Xe_LPG
[11:25:24] [PASSED] 12.74 Xe_LPG+
[11:25:24] [PASSED] 20.01 Xe2_HPG
[11:25:24] [PASSED] 20.02 Xe2_HPG
[11:25:24] [PASSED] 20.04 Xe2_LPG
[11:25:24] [PASSED] 30.00 Xe3_LPG
[11:25:24] [PASSED] 30.01 Xe3_LPG
[11:25:24] [PASSED] 30.03 Xe3_LPG
[11:25:24] [PASSED] 30.04 Xe3_LPG
[11:25:24] [PASSED] 30.05 Xe3_LPG
[11:25:24] [PASSED] 35.10 Xe3p_LPG
[11:25:24] [PASSED] 35.11 Xe3p_XPC
[11:25:24] ================ [PASSED] check_graphics_ip ================
[11:25:24] ===================== check_media_ip ======================
[11:25:24] [PASSED] 12.00 Xe_M
[11:25:24] [PASSED] 12.55 Xe_HPM
[11:25:24] [PASSED] 13.00 Xe_LPM+
[11:25:24] [PASSED] 13.01 Xe2_HPM
[11:25:24] [PASSED] 20.00 Xe2_LPM
[11:25:24] [PASSED] 30.00 Xe3_LPM
[11:25:24] [PASSED] 30.02 Xe3_LPM
[11:25:24] [PASSED] 35.00 Xe3p_LPM
[11:25:24] [PASSED] 35.03 Xe3p_HPM
[11:25:24] ================= [PASSED] check_media_ip ==================
[11:25:24] =================== check_platform_desc ===================
[11:25:24] [PASSED] 0x9A60 (TIGERLAKE)
[11:25:24] [PASSED] 0x9A68 (TIGERLAKE)
[11:25:24] [PASSED] 0x9A70 (TIGERLAKE)
[11:25:24] [PASSED] 0x9A40 (TIGERLAKE)
[11:25:24] [PASSED] 0x9A49 (TIGERLAKE)
[11:25:24] [PASSED] 0x9A59 (TIGERLAKE)
[11:25:24] [PASSED] 0x9A78 (TIGERLAKE)
[11:25:24] [PASSED] 0x9AC0 (TIGERLAKE)
[11:25:24] [PASSED] 0x9AC9 (TIGERLAKE)
[11:25:24] [PASSED] 0x9AD9 (TIGERLAKE)
[11:25:24] [PASSED] 0x9AF8 (TIGERLAKE)
[11:25:24] [PASSED] 0x4C80 (ROCKETLAKE)
[11:25:24] [PASSED] 0x4C8A (ROCKETLAKE)
[11:25:24] [PASSED] 0x4C8B (ROCKETLAKE)
[11:25:24] [PASSED] 0x4C8C (ROCKETLAKE)
[11:25:24] [PASSED] 0x4C90 (ROCKETLAKE)
[11:25:24] [PASSED] 0x4C9A (ROCKETLAKE)
[11:25:24] [PASSED] 0x4680 (ALDERLAKE_S)
[11:25:24] [PASSED] 0x4682 (ALDERLAKE_S)
[11:25:24] [PASSED] 0x4688 (ALDERLAKE_S)
[11:25:24] [PASSED] 0x468A (ALDERLAKE_S)
[11:25:24] [PASSED] 0x468B (ALDERLAKE_S)
[11:25:24] [PASSED] 0x4690 (ALDERLAKE_S)
[11:25:24] [PASSED] 0x4692 (ALDERLAKE_S)
[11:25:24] [PASSED] 0x4693 (ALDERLAKE_S)
[11:25:24] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46AA (ALDERLAKE_P)
[11:25:24] [PASSED] 0x462A (ALDERLAKE_P)
[11:25:24] [PASSED] 0x4626 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x4628 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:25:24] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:25:24] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:25:24] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:25:24] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:25:24] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:25:24] [PASSED] 0xA721 (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA720 (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:25:24] [PASSED] 0xA780 (ALDERLAKE_S)
[11:25:24] [PASSED] 0xA781 (ALDERLAKE_S)
[11:25:24] [PASSED] 0xA782 (ALDERLAKE_S)
[11:25:24] [PASSED] 0xA783 (ALDERLAKE_S)
[11:25:24] [PASSED] 0xA788 (ALDERLAKE_S)
[11:25:24] [PASSED] 0xA789 (ALDERLAKE_S)
[11:25:24] [PASSED] 0xA78A (ALDERLAKE_S)
[11:25:24] [PASSED] 0xA78B (ALDERLAKE_S)
[11:25:24] [PASSED] 0x4905 (DG1)
[11:25:24] [PASSED] 0x4906 (DG1)
[11:25:24] [PASSED] 0x4907 (DG1)
[11:25:24] [PASSED] 0x4908 (DG1)
[11:25:24] [PASSED] 0x4909 (DG1)
[11:25:24] [PASSED] 0x56C0 (DG2)
[11:25:24] [PASSED] 0x56C2 (DG2)
[11:25:24] [PASSED] 0x56C1 (DG2)
[11:25:24] [PASSED] 0x7D51 (METEORLAKE)
[11:25:24] [PASSED] 0x7DD1 (METEORLAKE)
[11:25:24] [PASSED] 0x7D41 (METEORLAKE)
[11:25:24] [PASSED] 0x7D67 (METEORLAKE)
[11:25:24] [PASSED] 0xB640 (METEORLAKE)
[11:25:24] [PASSED] 0x56A0 (DG2)
[11:25:24] [PASSED] 0x56A1 (DG2)
[11:25:24] [PASSED] 0x56A2 (DG2)
[11:25:24] [PASSED] 0x56BE (DG2)
[11:25:24] [PASSED] 0x56BF (DG2)
[11:25:24] [PASSED] 0x5690 (DG2)
[11:25:24] [PASSED] 0x5691 (DG2)
[11:25:24] [PASSED] 0x5692 (DG2)
[11:25:24] [PASSED] 0x56A5 (DG2)
[11:25:24] [PASSED] 0x56A6 (DG2)
[11:25:24] [PASSED] 0x56B0 (DG2)
[11:25:24] [PASSED] 0x56B1 (DG2)
[11:25:24] [PASSED] 0x56BA (DG2)
[11:25:24] [PASSED] 0x56BB (DG2)
[11:25:24] [PASSED] 0x56BC (DG2)
[11:25:24] [PASSED] 0x56BD (DG2)
[11:25:24] [PASSED] 0x5693 (DG2)
[11:25:24] [PASSED] 0x5694 (DG2)
[11:25:24] [PASSED] 0x5695 (DG2)
[11:25:24] [PASSED] 0x56A3 (DG2)
[11:25:24] [PASSED] 0x56A4 (DG2)
[11:25:24] [PASSED] 0x56B2 (DG2)
[11:25:24] [PASSED] 0x56B3 (DG2)
[11:25:24] [PASSED] 0x5696 (DG2)
[11:25:24] [PASSED] 0x5697 (DG2)
[11:25:24] [PASSED] 0xB69 (PVC)
[11:25:24] [PASSED] 0xB6E (PVC)
[11:25:24] [PASSED] 0xBD4 (PVC)
[11:25:24] [PASSED] 0xBD5 (PVC)
[11:25:24] [PASSED] 0xBD6 (PVC)
[11:25:24] [PASSED] 0xBD7 (PVC)
[11:25:24] [PASSED] 0xBD8 (PVC)
[11:25:24] [PASSED] 0xBD9 (PVC)
[11:25:24] [PASSED] 0xBDA (PVC)
[11:25:24] [PASSED] 0xBDB (PVC)
[11:25:24] [PASSED] 0xBE0 (PVC)
[11:25:24] [PASSED] 0xBE1 (PVC)
[11:25:24] [PASSED] 0xBE5 (PVC)
[11:25:24] [PASSED] 0x7D40 (METEORLAKE)
[11:25:24] [PASSED] 0x7D45 (METEORLAKE)
[11:25:24] [PASSED] 0x7D55 (METEORLAKE)
[11:25:24] [PASSED] 0x7D60 (METEORLAKE)
[11:25:24] [PASSED] 0x7DD5 (METEORLAKE)
[11:25:24] [PASSED] 0x6420 (LUNARLAKE)
[11:25:24] [PASSED] 0x64A0 (LUNARLAKE)
[11:25:24] [PASSED] 0x64B0 (LUNARLAKE)
[11:25:24] [PASSED] 0xE202 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE209 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE20B (BATTLEMAGE)
[11:25:24] [PASSED] 0xE20C (BATTLEMAGE)
[11:25:24] [PASSED] 0xE20D (BATTLEMAGE)
[11:25:24] [PASSED] 0xE210 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE211 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE212 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE216 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE220 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE221 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE222 (BATTLEMAGE)
[11:25:24] [PASSED] 0xE223 (BATTLEMAGE)
[11:25:24] [PASSED] 0xB080 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB081 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB082 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB083 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB084 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB085 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB086 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB087 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB08F (PANTHERLAKE)
[11:25:24] [PASSED] 0xB090 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB0A1 (PANTHERLAKE)
[11:25:24] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:25:24] [PASSED] 0xFD80 (PANTHERLAKE)
[11:25:24] [PASSED] 0xFD81 (PANTHERLAKE)
[11:25:24] [PASSED] 0xD740 (NOVALAKE_S)
[11:25:24] [PASSED] 0xD741 (NOVALAKE_S)
[11:25:24] [PASSED] 0xD742 (NOVALAKE_S)
[11:25:24] [PASSED] 0xD743 (NOVALAKE_S)
[11:25:24] [PASSED] 0xD745 (NOVALAKE_S)
[11:25:24] [PASSED] 0xD74A (NOVALAKE_S)
[11:25:24] [PASSED] 0xD74B (NOVALAKE_S)
[11:25:24] [PASSED] 0x674C (CRESCENTISLAND)
[11:25:24] [PASSED] 0x674D (CRESCENTISLAND)
[11:25:24] [PASSED] 0x674E (CRESCENTISLAND)
[11:25:24] [PASSED] 0x674F (CRESCENTISLAND)
[11:25:24] [PASSED] 0x6750 (CRESCENTISLAND)
[11:25:24] [PASSED] 0x6751 (CRESCENTISLAND)
[11:25:24] [PASSED] 0xD750 (NOVALAKE_P)
[11:25:24] [PASSED] 0xD751 (NOVALAKE_P)
[11:25:24] [PASSED] 0xD752 (NOVALAKE_P)
[11:25:24] [PASSED] 0xD753 (NOVALAKE_P)
[11:25:24] [PASSED] 0xD754 (NOVALAKE_P)
[11:25:24] [PASSED] 0xD755 (NOVALAKE_P)
[11:25:24] [PASSED] 0xD756 (NOVALAKE_P)
[11:25:24] [PASSED] 0xD757 (NOVALAKE_P)
[11:25:24] [PASSED] 0xD75F (NOVALAKE_P)
[11:25:24] =============== [PASSED] check_platform_desc ===============
[11:25:24] ===================== [PASSED] xe_pci ======================
[11:25:24] ============= xe_rtp_tables_test (5 subtests) ==============
[11:25:24] ================== xe_rtp_table_gt_test ===================
[11:25:24] [PASSED] gt_was/14011060649
[11:25:24] [PASSED] gt_was/14011059788
[11:25:24] [PASSED] gt_was/14015795083
[11:25:24] [PASSED] gt_was/16021867713
[11:25:24] [PASSED] gt_was/14019449301
[11:25:24] [PASSED] gt_was/16028005424
[11:25:24] [PASSED] gt_was/14026578760
[11:25:24] [PASSED] gt_was/1409420604
[11:25:24] [PASSED] gt_was/1408615072
[11:25:24] [PASSED] gt_was/22010523718
[11:25:24] [PASSED] gt_was/14011006942
[11:25:24] [PASSED] gt_was/14014830051
[11:25:24] [PASSED] gt_was/18018781329
[11:25:24] [PASSED] gt_was/1509235366
[11:25:24] [PASSED] gt_was/18018781329
[11:25:24] [PASSED] gt_was/16016694945
[11:25:24] [PASSED] gt_was/14018575942
[11:25:24] [PASSED] gt_was/22016670082
[11:25:24] [PASSED] gt_was/22016670082
[11:25:24] [PASSED] gt_was/14017421178
[11:25:24] [PASSED] gt_was/16025250150
[11:25:24] [PASSED] gt_was/14021871409
[11:25:24] [PASSED] gt_was/16021865536
[11:25:24] [PASSED] gt_was/14021486841
[11:25:24] [PASSED] gt_was/14025160223
[11:25:24] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[11:25:24] [PASSED] gt_was/14025635424
[11:25:24] [PASSED] gt_was/16028005424
[11:25:24] ============== [PASSED] xe_rtp_table_gt_test ===============
[11:25:24] ================== xe_rtp_table_gt_test ===================
[11:25:24] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[11:25:24] [PASSED] gt_tunings/Tuning: 32B Access Enable
[11:25:24] [PASSED] gt_tunings/Tuning: L3 cache
[11:25:24] [PASSED] gt_tunings/Tuning: L3 cache - media
[11:25:24] [PASSED] gt_tunings/Tuning: Compression Overfetch
[11:25:24] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[11:25:24] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[11:25:24] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[11:25:24] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[11:25:24] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[11:25:24] [PASSED] gt_tunings/Tuning: Stateless compression control
[11:25:24] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[11:25:24] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[11:25:24] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[11:25:24] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[11:25:24] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[11:25:24] ============== [PASSED] xe_rtp_table_gt_test ===============
[11:25:24] ================== xe_rtp_table_oob_test ==================
[11:25:24] [PASSED] oob_was/1607983814
[11:25:24] [PASSED] oob_was/16010904313
[11:25:24] [PASSED] oob_was/18022495364
[11:25:24] [PASSED] oob_was/22012773006
[11:25:24] [PASSED] oob_was/14014475959
[11:25:24] [PASSED] oob_was/22011391025
[11:25:24] [PASSED] oob_was/22012727170
[11:25:24] [PASSED] oob_was/22012727685
[11:25:24] [PASSED] oob_was/22016596838
[11:25:24] [PASSED] oob_was/18020744125
[11:25:24] [PASSED] oob_was/1409600907
[11:25:24] [PASSED] oob_was/22014953428
[11:25:24] [PASSED] oob_was/16017236439
[11:25:24] [PASSED] oob_was/14019821291
[11:25:24] [PASSED] oob_was/14015076503
[11:25:24] [PASSED] oob_was/22016122933
[11:25:24] [PASSED] oob_was/14018913170
[11:25:24] [PASSED] oob_was/14018094691
[11:25:24] [PASSED] oob_was/18024947630
[11:25:24] [PASSED] oob_was/16022287689
[11:25:24] [PASSED] oob_was/13011645652
[11:25:24] [PASSED] oob_was/14022293748
[11:25:24] [PASSED] oob_was/22019794406
[11:25:24] [PASSED] oob_was/22019338487
[11:25:24] [PASSED] oob_was/16023588340
[11:25:24] [PASSED] oob_was/14019789679
[11:25:24] [PASSED] oob_was/14022866841
[11:25:24] [PASSED] oob_was/16021333562
[11:25:24] [PASSED] oob_was/14016712196
[11:25:24] [PASSED] oob_was/14015568240
[11:25:24] [PASSED] oob_was/18013179988
[11:25:24] [PASSED] oob_was/1508761755
[11:25:24] [PASSED] oob_was/16023105232
[11:25:24] [PASSED] oob_was/16026508708
[11:25:24] [PASSED] oob_was/14020001231
[11:25:24] [PASSED] oob_was/16023683509
[11:25:24] [PASSED] oob_was/14025515070
[11:25:24] [PASSED] oob_was/15015404425_disable
[11:25:24] [PASSED] oob_was/16026007364
[11:25:24] [PASSED] oob_was/14020316580
[11:25:24] [PASSED] oob_was/14025883347
[11:25:24] [PASSED] oob_was/16029380221
[11:25:24] [PASSED] oob_was/22022079272
[11:25:24] [PASSED] oob_was/16029897822
[11:25:24] [PASSED] oob_was/14027054324
[11:25:24] [PASSED] oob_was/14025941587
[11:25:24] [PASSED] oob_was/16030224309
[11:25:24] ============== [PASSED] xe_rtp_table_oob_test ==============
[11:25:24] ================ xe_rtp_table_dev_oob_test ================
[11:25:24] [PASSED] device_oob_was/22010954014
[11:25:24] [PASSED] device_oob_was/15015404425
[11:25:24] [PASSED] device_oob_was/22019338487_display
[11:25:24] [PASSED] device_oob_was/14022085890
[11:25:24] [PASSED] device_oob_was/14026539277
[11:25:24] [PASSED] device_oob_was/14026633728
[11:25:24] [PASSED] device_oob_was/14026746987
[11:25:24] [PASSED] device_oob_was/14026779378
[11:25:24] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[11:25:24] ========== xe_rtp_table_missing_upper_bound_test ==========
[11:25:24] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[11:25:24] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[11:25:24] [PASSED] register_whitelist/1806527549
[11:25:24] [PASSED] register_whitelist/allow_read_ctx_timestamp
[11:25:24] [PASSED] register_whitelist/allow_read_queue_timestamp
[11:25:24] [PASSED] register_whitelist/16014440446
[11:25:24] [PASSED] register_whitelist/16017236439
[11:25:24] [PASSED] register_whitelist/16020183090
[11:25:24] [PASSED] register_whitelist/14024997852
[11:25:24] [PASSED] register_whitelist/14024997852
[11:25:24] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[11:25:24] =============== [PASSED] xe_rtp_tables_test ================
[11:25:24] =================== xe_rtp (3 subtests) ====================
[11:25:24] =================== xe_rtp_rules_tests ====================
[11:25:24] [PASSED] no
[11:25:24] [PASSED] yes
[11:25:24] [PASSED] no-and-no
[11:25:24] [PASSED] no-and-yes
[11:25:24] [PASSED] yes-and-no
[11:25:24] [PASSED] yes-and-yes
[11:25:24] [PASSED] no-or-no
[11:25:24] [PASSED] no-or-yes
[11:25:24] [PASSED] yes-or-no
[11:25:24] [PASSED] yes-or-yes
[11:25:24] [PASSED] no-yes-or-yes-no
[11:25:24] [PASSED] no-yes-or-yes-yes
[11:25:24] [PASSED] yes-yes-or-no-yes
[11:25:24] [PASSED] yes-yes-or-yes-yes
[11:25:24] [PASSED] no-no-or-yes-or-no
[11:25:24] [PASSED] or
[11:25:24] [PASSED] or-yes
[11:25:24] [PASSED] or-no
[11:25:24] [PASSED] yes-or
[11:25:24] [PASSED] no-or
[11:25:24] [PASSED] no-or-or-yes
[11:25:24] [PASSED] yes-or-or-no
[11:25:24] [PASSED] no-or-or-no
[11:25:24] [PASSED] missing-context-engine-class
[11:25:24] [PASSED] missing-context-engine-class-or-yes
[11:25:24] [PASSED] missing-context-engine-class-or-or-yes
[11:25:24] =============== [PASSED] xe_rtp_rules_tests ================
[11:25:24] =============== xe_rtp_process_to_sr_tests ================
[11:25:24] [PASSED] coalesce-same-reg
[11:25:24] [PASSED] coalesce-same-reg-literal-and-func
[11:25:24] [PASSED] no-match-no-add
[11:25:24] [PASSED] two-regs-two-entries
[11:25:24] [PASSED] clr-one-set-other
[11:25:24] [PASSED] set-field
[11:25:24] [PASSED] conflict-duplicate
[11:25:24] [PASSED] conflict-not-disjoint
[11:25:24] [PASSED] conflict-not-disjoint-literal-and-func
[11:25:24] [PASSED] conflict-reg-type
[11:25:24] [PASSED] bad-mcr-reg-forced-to-regular
[11:25:24] [PASSED] bad-regular-reg-forced-to-mcr
[11:25:24] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:25:24] ================== xe_rtp_process_tests ===================
[11:25:24] [PASSED] active1
[11:25:24] [PASSED] active2
[11:25:24] [PASSED] active-inactive
[11:25:24] [PASSED] inactive-active
[11:25:24] [PASSED] inactive-active-inactive
[11:25:24] [PASSED] inactive-inactive-inactive
[11:25:24] ============== [PASSED] xe_rtp_process_tests ===============
[11:25:24] ===================== [PASSED] xe_rtp ======================
[11:25:24] ==================== xe_wa (1 subtest) =====================
[11:25:24] ======================== xe_wa_gt =========================
[11:25:24] [PASSED] TIGERLAKE B0
[11:25:24] [PASSED] DG1 A0
[11:25:24] [PASSED] DG1 B0
[11:25:24] [PASSED] ALDERLAKE_S A0
[11:25:24] [PASSED] ALDERLAKE_S B0
[11:25:24] [PASSED] ALDERLAKE_S C0
[11:25:24] [PASSED] ALDERLAKE_S D0
[11:25:24] [PASSED] ALDERLAKE_P A0
[11:25:24] [PASSED] ALDERLAKE_P B0
[11:25:24] [PASSED] ALDERLAKE_P C0
[11:25:24] [PASSED] ALDERLAKE_S RPLS D0
[11:25:24] [PASSED] ALDERLAKE_P RPLU E0
[11:25:24] [PASSED] DG2 G10 C0
[11:25:24] [PASSED] DG2 G11 B1
[11:25:24] [PASSED] DG2 G12 A1
[11:25:24] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:25:24] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:25:24] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:25:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:25:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:25:24] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:25:24] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:25:24] ==================== [PASSED] xe_wa_gt =====================
[11:25:24] ====================== [PASSED] xe_wa ======================
[11:25:24] ============================================================
[11:25:24] Testing complete. Ran 821 tests: passed: 793, skipped: 28
[11:25:24] Elapsed time: 37.093s total, 1.857s configuring, 34.470s building, 0.715s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:25:24] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:25:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:25:51] Starting KUnit Kernel (1/1)...
[11:25:51] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:25:51] ============ drm_test_pick_cmdline (2 subtests) ============
[11:25:51] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:25:51] =============== drm_test_pick_cmdline_named ===============
[11:25:51] [PASSED] NTSC
[11:25:51] [PASSED] NTSC-J
[11:25:51] [PASSED] PAL
[11:25:51] [PASSED] PAL-M
[11:25:51] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:25:51] ============== [PASSED] drm_test_pick_cmdline ==============
[11:25:51] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:25:51] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:25:51] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:25:51] =========== drm_validate_clone_mode (2 subtests) ===========
[11:25:51] ============== drm_test_check_in_clone_mode ===============
[11:25:51] [PASSED] in_clone_mode
[11:25:51] [PASSED] not_in_clone_mode
[11:25:51] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:25:51] =============== drm_test_check_valid_clones ===============
[11:25:51] [PASSED] not_in_clone_mode
[11:25:51] [PASSED] valid_clone
[11:25:51] [PASSED] invalid_clone
[11:25:51] =========== [PASSED] drm_test_check_valid_clones ===========
[11:25:51] ============= [PASSED] drm_validate_clone_mode =============
[11:25:51] ============= drm_validate_modeset (1 subtest) =============
[11:25:51] [PASSED] drm_test_check_connector_changed_modeset
[11:25:51] ============== [PASSED] drm_validate_modeset ===============
[11:25:51] ====== drm_test_bridge_get_current_state (1 subtest) =======
[11:25:51] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:25:51] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:25:51] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:25:51] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:25:51] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:25:51] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[11:25:51] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:25:51] ============== drm_bridge_alloc (2 subtests) ===============
[11:25:51] [PASSED] drm_test_drm_bridge_alloc_basic
[11:25:51] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:25:51] ================ [PASSED] drm_bridge_alloc =================
[11:25:51] ============= drm_bridge_bus_fmt (5 subtests) ==============
[11:25:51] [PASSED] drm_test_bridge_rgb_yuv_rgb
[11:25:51] [PASSED] drm_test_bridge_must_convert_to_yuv444
[11:25:51] [PASSED] drm_test_bridge_hdmi_auto_rgb
[11:25:51] [PASSED] drm_test_bridge_auto_first
[11:25:51] [PASSED] drm_test_bridge_rgb_yuv_no_path
[11:25:51] =============== [PASSED] drm_bridge_bus_fmt ================
[11:25:51] ============= drm_cmdline_parser (40 subtests) =============
[11:25:51] [PASSED] drm_test_cmdline_force_d_only
[11:25:51] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:25:51] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:25:51] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:25:51] [PASSED] drm_test_cmdline_force_e_only
[11:25:51] [PASSED] drm_test_cmdline_res
[11:25:51] [PASSED] drm_test_cmdline_res_vesa
[11:25:51] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:25:51] [PASSED] drm_test_cmdline_res_rblank
[11:25:51] [PASSED] drm_test_cmdline_res_bpp
[11:25:51] [PASSED] drm_test_cmdline_res_refresh
[11:25:51] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:25:51] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:25:51] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:25:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:25:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:25:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:25:51] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:25:51] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:25:51] [PASSED] drm_test_cmdline_res_margins_force_on
[11:25:51] [PASSED] drm_test_cmdline_res_vesa_margins
[11:25:51] [PASSED] drm_test_cmdline_name
[11:25:51] [PASSED] drm_test_cmdline_name_bpp
[11:25:51] [PASSED] drm_test_cmdline_name_option
[11:25:51] [PASSED] drm_test_cmdline_name_bpp_option
[11:25:51] [PASSED] drm_test_cmdline_rotate_0
[11:25:51] [PASSED] drm_test_cmdline_rotate_90
[11:25:51] [PASSED] drm_test_cmdline_rotate_180
[11:25:51] [PASSED] drm_test_cmdline_rotate_270
[11:25:51] [PASSED] drm_test_cmdline_hmirror
[11:25:51] [PASSED] drm_test_cmdline_vmirror
[11:25:51] [PASSED] drm_test_cmdline_margin_options
[11:25:51] [PASSED] drm_test_cmdline_multiple_options
[11:25:51] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:25:51] [PASSED] drm_test_cmdline_extra_and_option
[11:25:51] [PASSED] drm_test_cmdline_freestanding_options
[11:25:51] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:25:51] [PASSED] drm_test_cmdline_panel_orientation
[11:25:51] ================ drm_test_cmdline_invalid =================
[11:25:51] [PASSED] margin_only
[11:25:51] [PASSED] interlace_only
[11:25:51] [PASSED] res_missing_x
[11:25:51] [PASSED] res_missing_y
[11:25:51] [PASSED] res_bad_y
[11:25:51] [PASSED] res_missing_y_bpp
[11:25:51] [PASSED] res_bad_bpp
[11:25:51] [PASSED] res_bad_refresh
[11:25:51] [PASSED] res_bpp_refresh_force_on_off
[11:25:51] [PASSED] res_invalid_mode
[11:25:51] [PASSED] res_bpp_wrong_place_mode
[11:25:51] [PASSED] name_bpp_refresh
[11:25:51] [PASSED] name_refresh
[11:25:51] [PASSED] name_refresh_wrong_mode
[11:25:51] [PASSED] name_refresh_invalid_mode
[11:25:51] [PASSED] rotate_multiple
[11:25:51] [PASSED] rotate_invalid_val
[11:25:51] [PASSED] rotate_truncated
[11:25:51] [PASSED] invalid_option
[11:25:51] [PASSED] invalid_tv_option
[11:25:51] [PASSED] truncated_tv_option
[11:25:51] ============ [PASSED] drm_test_cmdline_invalid =============
[11:25:51] =============== drm_test_cmdline_tv_options ===============
[11:25:51] [PASSED] NTSC
[11:25:51] [PASSED] NTSC_443
[11:25:51] [PASSED] NTSC_J
[11:25:51] [PASSED] PAL
[11:25:51] [PASSED] PAL_M
[11:25:51] [PASSED] PAL_N
[11:25:51] [PASSED] SECAM
[11:25:51] [PASSED] MONO_525
[11:25:51] [PASSED] MONO_625
[11:25:51] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:25:51] =============== [PASSED] drm_cmdline_parser ================
[11:25:51] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:25:51] [PASSED] drm_test_connector_hdmi_init_valid
[11:25:51] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:25:51] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:25:51] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:25:51] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:25:51] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:25:51] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:25:51] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:25:51] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:25:51] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:25:51] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:25:51] [PASSED] supported_formats=0x5 yuv420_allowed=1
[11:25:51] [PASSED] supported_formats=0x5 yuv420_allowed=0
[11:25:51] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:25:51] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:25:51] [PASSED] drm_test_connector_hdmi_init_null_product
[11:25:51] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:25:51] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:25:51] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:25:51] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:25:51] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:25:51] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:25:51] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:25:51] ========= drm_test_connector_hdmi_init_type_valid =========
[11:25:51] [PASSED] HDMI-A
[11:25:51] [PASSED] HDMI-B
[11:25:51] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:25:51] ======== drm_test_connector_hdmi_init_type_invalid ========
[11:25:51] [PASSED] Unknown
[11:25:51] [PASSED] VGA
[11:25:51] [PASSED] DVI-I
[11:25:51] [PASSED] DVI-D
[11:25:51] [PASSED] DVI-A
[11:25:51] [PASSED] Composite
[11:25:51] [PASSED] SVIDEO
[11:25:51] [PASSED] LVDS
[11:25:51] [PASSED] Component
[11:25:51] [PASSED] DIN
[11:25:51] [PASSED] DP
[11:25:51] [PASSED] TV
[11:25:51] [PASSED] eDP
[11:25:51] [PASSED] Virtual
[11:25:51] [PASSED] DSI
[11:25:51] [PASSED] DPI
[11:25:51] [PASSED] Writeback
[11:25:51] [PASSED] SPI
[11:25:51] [PASSED] USB
[11:25:51] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:25:51] ============ [PASSED] drmm_connector_hdmi_init =============
[11:25:51] ============= drmm_connector_init (3 subtests) =============
[11:25:51] [PASSED] drm_test_drmm_connector_init
[11:25:51] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:25:51] ========= drm_test_drmm_connector_init_type_valid =========
[11:25:51] [PASSED] Unknown
[11:25:51] [PASSED] VGA
[11:25:51] [PASSED] DVI-I
[11:25:51] [PASSED] DVI-D
[11:25:51] [PASSED] DVI-A
[11:25:51] [PASSED] Composite
[11:25:51] [PASSED] SVIDEO
[11:25:51] [PASSED] LVDS
[11:25:51] [PASSED] Component
[11:25:51] [PASSED] DIN
[11:25:51] [PASSED] DP
[11:25:51] [PASSED] HDMI-A
[11:25:51] [PASSED] HDMI-B
[11:25:51] [PASSED] TV
[11:25:51] [PASSED] eDP
[11:25:51] [PASSED] Virtual
[11:25:51] [PASSED] DSI
[11:25:51] [PASSED] DPI
[11:25:51] [PASSED] Writeback
[11:25:51] [PASSED] SPI
[11:25:51] [PASSED] USB
[11:25:51] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:25:51] =============== [PASSED] drmm_connector_init ===============
[11:25:51] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_init
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:25:51] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[11:25:51] [PASSED] Unknown
[11:25:51] [PASSED] VGA
[11:25:51] [PASSED] DVI-I
[11:25:51] [PASSED] DVI-D
[11:25:51] [PASSED] DVI-A
[11:25:51] [PASSED] Composite
[11:25:51] [PASSED] SVIDEO
[11:25:51] [PASSED] LVDS
[11:25:51] [PASSED] Component
[11:25:51] [PASSED] DIN
[11:25:51] [PASSED] DP
[11:25:51] [PASSED] HDMI-A
[11:25:51] [PASSED] HDMI-B
[11:25:51] [PASSED] TV
[11:25:51] [PASSED] eDP
[11:25:51] [PASSED] Virtual
[11:25:51] [PASSED] DSI
[11:25:51] [PASSED] DPI
[11:25:51] [PASSED] Writeback
[11:25:51] [PASSED] SPI
[11:25:51] [PASSED] USB
[11:25:51] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:25:51] ======== drm_test_drm_connector_dynamic_init_name =========
[11:25:51] [PASSED] Unknown
[11:25:51] [PASSED] VGA
[11:25:51] [PASSED] DVI-I
[11:25:51] [PASSED] DVI-D
[11:25:51] [PASSED] DVI-A
[11:25:51] [PASSED] Composite
[11:25:51] [PASSED] SVIDEO
[11:25:51] [PASSED] LVDS
[11:25:51] [PASSED] Component
[11:25:51] [PASSED] DIN
[11:25:51] [PASSED] DP
[11:25:51] [PASSED] HDMI-A
[11:25:51] [PASSED] HDMI-B
[11:25:51] [PASSED] TV
[11:25:51] [PASSED] eDP
[11:25:51] [PASSED] Virtual
[11:25:51] [PASSED] DSI
[11:25:51] [PASSED] DPI
[11:25:51] [PASSED] Writeback
[11:25:51] [PASSED] SPI
[11:25:51] [PASSED] USB
[11:25:51] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:25:51] =========== [PASSED] drm_connector_dynamic_init ============
[11:25:51] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:25:51] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:25:51] ======= drm_connector_dynamic_register (7 subtests) ========
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:25:51] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:25:51] ========= [PASSED] drm_connector_dynamic_register ==========
[11:25:51] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:25:51] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:25:51] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:25:51] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:25:51] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:25:51] ========== drm_test_get_tv_mode_from_name_valid ===========
[11:25:51] [PASSED] NTSC
[11:25:51] [PASSED] NTSC-443
[11:25:51] [PASSED] NTSC-J
[11:25:51] [PASSED] PAL
[11:25:51] [PASSED] PAL-M
[11:25:51] [PASSED] PAL-N
[11:25:51] [PASSED] SECAM
[11:25:51] [PASSED] Mono
[11:25:51] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:25:51] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:25:51] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:25:51] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:25:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:25:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:25:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:25:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:25:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:25:51] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:25:51] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[11:25:51] [PASSED] VIC 96
[11:25:51] [PASSED] VIC 97
[11:25:51] [PASSED] VIC 101
[11:25:51] [PASSED] VIC 102
[11:25:51] [PASSED] VIC 106
[11:25:51] [PASSED] VIC 107
[11:25:51] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:25:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:25:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:25:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:25:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:25:51] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:25:51] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:25:51] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:25:51] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[11:25:51] [PASSED] Automatic
[11:25:51] [PASSED] Full
[11:25:51] [PASSED] Limited 16:235
[11:25:51] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:25:51] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:25:51] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:25:51] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:25:51] === drm_test_drm_hdmi_connector_get_output_format_name ====
[11:25:51] [PASSED] RGB
[11:25:51] [PASSED] YUV 4:2:0
[11:25:51] [PASSED] YUV 4:2:2
[11:25:51] [PASSED] YUV 4:4:4
[11:25:51] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:25:51] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:25:51] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:25:51] ============= drm_damage_helper (21 subtests) ==============
[11:25:51] [PASSED] drm_test_damage_iter_no_damage
[11:25:51] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:25:51] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:25:51] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:25:51] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:25:51] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:25:51] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:25:51] [PASSED] drm_test_damage_iter_simple_damage
[11:25:51] [PASSED] drm_test_damage_iter_single_damage
[11:25:51] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:25:51] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:25:51] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:25:51] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:25:51] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:25:51] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:25:51] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:25:51] [PASSED] drm_test_damage_iter_damage
[11:25:51] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:25:51] [PASSED] drm_test_damage_iter_damage_one_outside
[11:25:51] [PASSED] drm_test_damage_iter_damage_src_moved
[11:25:51] [PASSED] drm_test_damage_iter_damage_not_visible
[11:25:51] ================ [PASSED] drm_damage_helper ================
[11:25:51] ============== drm_dp_mst_helper (3 subtests) ==============
[11:25:51] ============== drm_test_dp_mst_calc_pbn_mode ==============
[11:25:51] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:25:51] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:25:51] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:25:51] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:25:51] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:25:51] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:25:51] ============== drm_test_dp_mst_calc_pbn_div ===============
[11:25:51] [PASSED] Link rate 2000000 lane count 4
[11:25:51] [PASSED] Link rate 2000000 lane count 2
[11:25:51] [PASSED] Link rate 2000000 lane count 1
[11:25:51] [PASSED] Link rate 1350000 lane count 4
[11:25:51] [PASSED] Link rate 1350000 lane count 2
[11:25:51] [PASSED] Link rate 1350000 lane count 1
[11:25:51] [PASSED] Link rate 1000000 lane count 4
[11:25:51] [PASSED] Link rate 1000000 lane count 2
[11:25:51] [PASSED] Link rate 1000000 lane count 1
[11:25:51] [PASSED] Link rate 810000 lane count 4
[11:25:51] [PASSED] Link rate 810000 lane count 2
[11:25:51] [PASSED] Link rate 810000 lane count 1
[11:25:51] [PASSED] Link rate 540000 lane count 4
[11:25:51] [PASSED] Link rate 540000 lane count 2
[11:25:51] [PASSED] Link rate 540000 lane count 1
[11:25:51] [PASSED] Link rate 270000 lane count 4
[11:25:51] [PASSED] Link rate 270000 lane count 2
[11:25:51] [PASSED] Link rate 270000 lane count 1
[11:25:51] [PASSED] Link rate 162000 lane count 4
[11:25:51] [PASSED] Link rate 162000 lane count 2
[11:25:51] [PASSED] Link rate 162000 lane count 1
[11:25:51] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:25:51] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[11:25:51] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:25:51] [PASSED] DP_POWER_UP_PHY with port number
[11:25:51] [PASSED] DP_POWER_DOWN_PHY with port number
[11:25:51] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:25:51] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:25:51] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:25:51] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:25:51] [PASSED] DP_QUERY_PAYLOAD with port number
[11:25:51] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:25:51] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:25:51] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:25:51] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:25:51] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:25:51] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:25:51] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:25:51] [PASSED] DP_REMOTE_I2C_READ with port number
[11:25:51] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:25:51] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:25:51] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:25:51] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:25:51] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:25:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:25:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:25:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:25:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:25:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:25:51] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:25:51] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:25:51] ================ [PASSED] drm_dp_mst_helper ================
[11:25:51] ================== drm_exec (7 subtests) ===================
[11:25:51] [PASSED] sanitycheck
[11:25:51] [PASSED] test_lock
[11:25:51] [PASSED] test_lock_unlock
[11:25:51] [PASSED] test_duplicates
[11:25:51] [PASSED] test_prepare
[11:25:51] [PASSED] test_prepare_array
[11:25:51] [PASSED] test_multiple_loops
[11:25:51] ==================== [PASSED] drm_exec =====================
[11:25:51] =========== drm_format_helper_test (17 subtests) ===========
[11:25:51] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:25:51] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:25:51] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:25:51] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:25:51] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:25:51] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:25:51] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:25:51] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:25:51] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:25:51] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:25:51] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:25:51] ============== drm_test_fb_xrgb8888_to_mono ===============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:25:51] ==================== drm_test_fb_swab =====================
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ================ [PASSED] drm_test_fb_swab =================
[11:25:51] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:25:51] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[11:25:51] [PASSED] single_pixel_source_buffer
[11:25:51] [PASSED] single_pixel_clip_rectangle
[11:25:51] [PASSED] well_known_colors
[11:25:51] [PASSED] destination_pitch
[11:25:51] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:25:51] ================= drm_test_fb_clip_offset =================
[11:25:51] [PASSED] pass through
[11:25:51] [PASSED] horizontal offset
[11:25:51] [PASSED] vertical offset
[11:25:51] [PASSED] horizontal and vertical offset
[11:25:51] [PASSED] horizontal offset (custom pitch)
[11:25:51] [PASSED] vertical offset (custom pitch)
[11:25:51] [PASSED] horizontal and vertical offset (custom pitch)
[11:25:51] ============= [PASSED] drm_test_fb_clip_offset =============
[11:25:51] =================== drm_test_fb_memcpy ====================
[11:25:51] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:25:51] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:25:51] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:25:51] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:25:51] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:25:51] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:25:51] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:25:51] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:25:51] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:25:51] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:25:51] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:25:51] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:25:51] =============== [PASSED] drm_test_fb_memcpy ================
[11:25:51] ============= [PASSED] drm_format_helper_test ==============
[11:25:51] ================= drm_format (18 subtests) =================
[11:25:51] [PASSED] drm_test_format_block_width_invalid
[11:25:51] [PASSED] drm_test_format_block_width_one_plane
[11:25:51] [PASSED] drm_test_format_block_width_two_plane
[11:25:51] [PASSED] drm_test_format_block_width_three_plane
[11:25:51] [PASSED] drm_test_format_block_width_tiled
[11:25:51] [PASSED] drm_test_format_block_height_invalid
[11:25:51] [PASSED] drm_test_format_block_height_one_plane
[11:25:51] [PASSED] drm_test_format_block_height_two_plane
[11:25:51] [PASSED] drm_test_format_block_height_three_plane
[11:25:51] [PASSED] drm_test_format_block_height_tiled
[11:25:51] [PASSED] drm_test_format_min_pitch_invalid
[11:25:51] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:25:51] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:25:51] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:25:51] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:25:51] [PASSED] drm_test_format_min_pitch_two_plane
[11:25:51] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:25:51] [PASSED] drm_test_format_min_pitch_tiled
[11:25:51] =================== [PASSED] drm_format ====================
[11:25:51] ============== drm_framebuffer (10 subtests) ===============
[11:25:51] ========== drm_test_framebuffer_check_src_coords ==========
[11:25:51] [PASSED] Success: source fits into fb
[11:25:51] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:25:51] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:25:51] [PASSED] Fail: overflowing fb with source width
[11:25:51] [PASSED] Fail: overflowing fb with source height
[11:25:51] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:25:51] [PASSED] drm_test_framebuffer_cleanup
[11:25:51] =============== drm_test_framebuffer_create ===============
[11:25:51] [PASSED] ABGR8888 normal sizes
[11:25:51] [PASSED] ABGR8888 max sizes
[11:25:51] [PASSED] ABGR8888 pitch greater than min required
[11:25:51] [PASSED] ABGR8888 pitch less than min required
[11:25:51] [PASSED] ABGR8888 Invalid width
[11:25:51] [PASSED] ABGR8888 Invalid buffer handle
[11:25:51] [PASSED] No pixel format
[11:25:51] [PASSED] ABGR8888 Width 0
[11:25:51] [PASSED] ABGR8888 Height 0
[11:25:51] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:25:51] [PASSED] ABGR8888 Large buffer offset
[11:25:51] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:25:51] [PASSED] ABGR8888 Invalid flag
[11:25:51] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:25:51] [PASSED] ABGR8888 Valid buffer modifier
[11:25:51] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:25:51] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:25:51] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:25:51] [PASSED] NV12 Normal sizes
[11:25:51] [PASSED] NV12 Max sizes
[11:25:51] [PASSED] NV12 Invalid pitch
[11:25:51] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:25:51] [PASSED] NV12 different modifier per-plane
[11:25:51] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:25:51] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:25:51] [PASSED] NV12 Modifier for inexistent plane
[11:25:51] [PASSED] NV12 Handle for inexistent plane
[11:25:51] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:25:51] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:25:51] [PASSED] YVU420 Normal sizes
[11:25:51] [PASSED] YVU420 Max sizes
[11:25:51] [PASSED] YVU420 Invalid pitch
[11:25:51] [PASSED] YVU420 Different pitches
[11:25:51] [PASSED] YVU420 Different buffer offsets/pitches
[11:25:51] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:25:51] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:25:51] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:25:51] [PASSED] YVU420 Valid modifier
[11:25:51] [PASSED] YVU420 Different modifiers per plane
[11:25:51] [PASSED] YVU420 Modifier for inexistent plane
[11:25:51] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:25:51] [PASSED] X0L2 Normal sizes
[11:25:51] [PASSED] X0L2 Max sizes
[11:25:51] [PASSED] X0L2 Invalid pitch
[11:25:51] [PASSED] X0L2 Pitch greater than minimum required
[11:25:51] [PASSED] X0L2 Handle for inexistent plane
[11:25:51] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:25:51] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:25:51] [PASSED] X0L2 Valid modifier
[11:25:51] [PASSED] X0L2 Modifier for inexistent plane
[11:25:51] =========== [PASSED] drm_test_framebuffer_create ===========
[11:25:51] [PASSED] drm_test_framebuffer_free
[11:25:51] [PASSED] drm_test_framebuffer_init
[11:25:51] [PASSED] drm_test_framebuffer_init_bad_format
[11:25:51] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:25:51] [PASSED] drm_test_framebuffer_lookup
[11:25:51] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:25:51] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:25:51] ================= [PASSED] drm_framebuffer =================
[11:25:51] ================ drm_gem_shmem (8 subtests) ================
[11:25:51] [PASSED] drm_gem_shmem_test_obj_create
[11:25:51] [PASSED] drm_gem_shmem_test_obj_create_private
[11:25:51] [PASSED] drm_gem_shmem_test_pin_pages
[11:25:51] [PASSED] drm_gem_shmem_test_vmap
[11:25:51] [PASSED] drm_gem_shmem_test_get_sg_table
[11:25:51] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:25:51] [PASSED] drm_gem_shmem_test_madvise
[11:25:51] [PASSED] drm_gem_shmem_test_purge
[11:25:51] ================== [PASSED] drm_gem_shmem ==================
[11:25:51] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:25:51] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[11:25:51] [PASSED] Automatic
[11:25:51] [PASSED] Full
[11:25:51] [PASSED] Limited 16:235
[11:25:51] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:25:51] [PASSED] drm_test_check_disable_connector
[11:25:51] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:25:51] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:25:51] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:25:51] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:25:51] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:25:51] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:25:51] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:25:51] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:25:51] [PASSED] drm_test_check_output_bpc_dvi
[11:25:51] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:25:51] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:25:51] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:25:51] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:25:51] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:25:51] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:25:51] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:25:51] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:25:51] ============ drm_test_check_hdmi_color_format =============
[11:25:51] [PASSED] AUTO -> RGB
[11:25:51] [PASSED] YCBCR422 -> YUV422
[11:25:51] [PASSED] YCBCR420 -> YUV420
[11:25:51] [PASSED] YCBCR444 -> YUV444
[11:25:51] [PASSED] RGB -> RGB
[11:25:51] ======== [PASSED] drm_test_check_hdmi_color_format =========
[11:25:51] ======== drm_test_check_hdmi_color_format_420_only ========
[11:25:51] [PASSED] RGB should fail
[11:25:51] [PASSED] YUV444 should fail
[11:25:51] [PASSED] YUV422 should fail
[11:25:51] [PASSED] YUV420 should work
[11:25:51] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[11:25:51] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:25:51] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:25:51] [PASSED] drm_test_check_broadcast_rgb_value
[11:25:51] [PASSED] drm_test_check_bpc_8_value
[11:25:51] [PASSED] drm_test_check_bpc_10_value
[11:25:51] [PASSED] drm_test_check_bpc_12_value
[11:25:51] [PASSED] drm_test_check_format_value
[11:25:51] [PASSED] drm_test_check_tmds_char_value
[11:25:51] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:25:51] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[11:25:51] [PASSED] drm_test_check_mode_valid
[11:25:51] [PASSED] drm_test_check_mode_valid_reject
[11:25:51] [PASSED] drm_test_check_mode_valid_reject_rate
[11:25:51] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:25:51] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[11:25:51] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[11:25:51] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[11:25:51] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:25:51] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[11:25:51] [PASSED] drm_test_check_infoframes
[11:25:51] [PASSED] drm_test_check_reject_avi_infoframe
[11:25:51] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[11:25:51] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[11:25:51] [PASSED] drm_test_check_reject_audio_infoframe
[11:25:51] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[11:25:51] ================= drm_managed (2 subtests) =================
[11:25:51] [PASSED] drm_test_managed_release_action
[11:25:51] [PASSED] drm_test_managed_run_action
[11:25:51] =================== [PASSED] drm_managed ===================
[11:25:51] =================== drm_mm (6 subtests) ====================
[11:25:51] [PASSED] drm_test_mm_init
[11:25:51] [PASSED] drm_test_mm_debug
[11:25:51] [PASSED] drm_test_mm_align32
[11:25:51] [PASSED] drm_test_mm_align64
[11:25:51] [PASSED] drm_test_mm_lowest
[11:25:51] [PASSED] drm_test_mm_highest
[11:25:51] ===================== [PASSED] drm_mm ======================
[11:25:51] ============= drm_modes_analog_tv (5 subtests) =============
[11:25:51] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:25:51] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:25:51] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:25:51] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:25:51] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:25:51] =============== [PASSED] drm_modes_analog_tv ===============
[11:25:51] ============== drm_panic_helper (3 subtests) ===============
[11:25:51] ============= drm_test_panic_screen_user_map ==============
[11:25:51] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[11:25:51] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[11:25:51] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[11:25:51] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[11:25:51] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[11:25:51] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[11:25:51] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[11:25:51] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[11:25:52] ========= [PASSED] drm_test_panic_screen_user_map ==========
[11:25:52] ============= drm_test_panic_screen_user_page =============
[11:25:52] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[11:25:52] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[11:25:52] ========= [PASSED] drm_test_panic_screen_user_page =========
[11:25:52] ========== drm_test_panic_screen_user_set_pixel ===========
[11:25:52] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[11:25:52] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[11:25:52] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[11:25:52] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[11:25:52] ================ [PASSED] drm_panic_helper =================
[11:25:52] ============== drm_plane_helper (2 subtests) ===============
[11:25:52] =============== drm_test_check_plane_state ================
[11:25:52] [PASSED] clipping_simple
[11:25:52] [PASSED] clipping_rotate_reflect
[11:25:52] [PASSED] positioning_simple
[11:25:52] [PASSED] upscaling
[11:25:52] [PASSED] downscaling
[11:25:52] [PASSED] rounding1
[11:25:52] [PASSED] rounding2
[11:25:52] [PASSED] rounding3
[11:25:52] [PASSED] rounding4
[11:25:52] =========== [PASSED] drm_test_check_plane_state ============
[11:25:52] =========== drm_test_check_invalid_plane_state ============
[11:25:52] [PASSED] positioning_invalid
[11:25:52] [PASSED] upscaling_invalid
[11:25:52] [PASSED] downscaling_invalid
[11:25:52] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:25:52] ================ [PASSED] drm_plane_helper =================
[11:25:52] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:25:52] ====== drm_test_connector_helper_tv_get_modes_check =======
[11:25:52] [PASSED] None
[11:25:52] [PASSED] PAL
[11:25:52] [PASSED] NTSC
[11:25:52] [PASSED] Both, NTSC Default
[11:25:52] [PASSED] Both, PAL Default
[11:25:52] [PASSED] Both, NTSC Default, with PAL on command-line
[11:25:52] [PASSED] Both, PAL Default, with NTSC on command-line
[11:25:52] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:25:52] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:25:52] ================== drm_rect (9 subtests) ===================
[11:25:52] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:25:52] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:25:52] [PASSED] drm_test_rect_clip_scaled_clipped
[11:25:52] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:25:52] ================= drm_test_rect_intersect =================
[11:25:52] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:25:52] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:25:52] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:25:52] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:25:52] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:25:52] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:25:52] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:25:52] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:25:52] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:25:52] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:25:52] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:25:52] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:25:52] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:25:52] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:25:52] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:25:52] ============= [PASSED] drm_test_rect_intersect =============
[11:25:52] ================ drm_test_rect_calc_hscale ================
[11:25:52] [PASSED] normal use
[11:25:52] [PASSED] out of max range
[11:25:52] [PASSED] out of min range
[11:25:52] [PASSED] zero dst
[11:25:52] [PASSED] negative src
[11:25:52] [PASSED] negative dst
[11:25:52] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:25:52] ================ drm_test_rect_calc_vscale ================
[11:25:52] [PASSED] normal use
[11:25:52] [PASSED] out of max range
[11:25:52] [PASSED] out of min range
[11:25:52] [PASSED] zero dst
[11:25:52] [PASSED] negative src
[11:25:52] [PASSED] negative dst
[11:25:52] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:25:52] ================== drm_test_rect_rotate ===================
[11:25:52] [PASSED] reflect-x
[11:25:52] [PASSED] reflect-y
[11:25:52] [PASSED] rotate-0
[11:25:52] [PASSED] rotate-90
[11:25:52] [PASSED] rotate-180
[11:25:52] [PASSED] rotate-270
[11:25:52] ============== [PASSED] drm_test_rect_rotate ===============
[11:25:52] ================ drm_test_rect_rotate_inv =================
[11:25:52] [PASSED] reflect-x
[11:25:52] [PASSED] reflect-y
[11:25:52] [PASSED] rotate-0
[11:25:52] [PASSED] rotate-90
[11:25:52] [PASSED] rotate-180
[11:25:52] [PASSED] rotate-270
[11:25:52] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:25:52] ==================== [PASSED] drm_rect =====================
[11:25:52] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:25:52] ============ drm_test_sysfb_build_fourcc_list =============
[11:25:52] [PASSED] no native formats
[11:25:52] [PASSED] XRGB8888 as native format
[11:25:52] [PASSED] remove duplicates
[11:25:52] [PASSED] convert alpha formats
[11:25:52] [PASSED] random formats
[11:25:52] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:25:52] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:25:52] ================== drm_fixp (2 subtests) ===================
[11:25:52] [PASSED] drm_test_int2fixp
[11:25:52] [PASSED] drm_test_sm2fixp
[11:25:52] ==================== [PASSED] drm_fixp =====================
[11:25:52] ============================================================
[11:25:52] Testing complete. Ran 667 tests: passed: 667
[11:25:52] Elapsed time: 27.396s total, 1.762s configuring, 25.219s building, 0.412s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:25:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:25:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:26:04] Starting KUnit Kernel (1/1)...
[11:26:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:26:04] ================= ttm_device (5 subtests) ==================
[11:26:04] [PASSED] ttm_device_init_basic
[11:26:04] [PASSED] ttm_device_init_multiple
[11:26:04] [PASSED] ttm_device_fini_basic
[11:26:04] [PASSED] ttm_device_init_no_vma_man
[11:26:04] ================== ttm_device_init_pools ==================
[11:26:04] [PASSED] No DMA allocations, no DMA32 required
[11:26:04] [PASSED] DMA allocations, DMA32 required
[11:26:04] [PASSED] No DMA allocations, DMA32 required
[11:26:04] [PASSED] DMA allocations, no DMA32 required
[11:26:04] ============== [PASSED] ttm_device_init_pools ==============
[11:26:04] =================== [PASSED] ttm_device ====================
[11:26:04] ================== ttm_pool (8 subtests) ===================
[11:26:04] ================== ttm_pool_alloc_basic ===================
[11:26:04] [PASSED] One page
[11:26:04] [PASSED] More than one page
[11:26:04] [PASSED] Above the allocation limit
[11:26:04] [PASSED] One page, with coherent DMA mappings enabled
[11:26:04] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:26:04] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:26:04] ============== ttm_pool_alloc_basic_dma_addr ==============
[11:26:04] [PASSED] One page
[11:26:04] [PASSED] More than one page
[11:26:04] [PASSED] Above the allocation limit
[11:26:04] [PASSED] One page, with coherent DMA mappings enabled
[11:26:04] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:26:04] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:26:04] [PASSED] ttm_pool_alloc_order_caching_match
[11:26:04] [PASSED] ttm_pool_alloc_caching_mismatch
[11:26:04] [PASSED] ttm_pool_alloc_order_mismatch
[11:26:04] [PASSED] ttm_pool_free_dma_alloc
[11:26:04] [PASSED] ttm_pool_free_no_dma_alloc
[11:26:04] [PASSED] ttm_pool_fini_basic
[11:26:04] ==================== [PASSED] ttm_pool =====================
[11:26:04] ================ ttm_resource (8 subtests) =================
[11:26:04] ================= ttm_resource_init_basic =================
[11:26:04] [PASSED] Init resource in TTM_PL_SYSTEM
[11:26:04] [PASSED] Init resource in TTM_PL_VRAM
[11:26:04] [PASSED] Init resource in a private placement
[11:26:04] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:26:04] ============= [PASSED] ttm_resource_init_basic =============
[11:26:04] [PASSED] ttm_resource_init_pinned
[11:26:04] [PASSED] ttm_resource_fini_basic
[11:26:04] [PASSED] ttm_resource_manager_init_basic
[11:26:04] [PASSED] ttm_resource_manager_usage_basic
[11:26:04] [PASSED] ttm_resource_manager_set_used_basic
[11:26:04] [PASSED] ttm_sys_man_alloc_basic
[11:26:04] [PASSED] ttm_sys_man_free_basic
[11:26:04] ================== [PASSED] ttm_resource ===================
[11:26:04] =================== ttm_tt (15 subtests) ===================
[11:26:04] ==================== ttm_tt_init_basic ====================
[11:26:04] [PASSED] Page-aligned size
[11:26:04] [PASSED] Extra pages requested
[11:26:04] ================ [PASSED] ttm_tt_init_basic ================
[11:26:04] [PASSED] ttm_tt_init_misaligned
[11:26:04] [PASSED] ttm_tt_fini_basic
[11:26:04] [PASSED] ttm_tt_fini_sg
[11:26:04] [PASSED] ttm_tt_fini_shmem
[11:26:04] [PASSED] ttm_tt_create_basic
[11:26:04] [PASSED] ttm_tt_create_invalid_bo_type
[11:26:04] [PASSED] ttm_tt_create_ttm_exists
[11:26:04] [PASSED] ttm_tt_create_failed
[11:26:04] [PASSED] ttm_tt_destroy_basic
[11:26:04] [PASSED] ttm_tt_populate_null_ttm
[11:26:04] [PASSED] ttm_tt_populate_populated_ttm
[11:26:04] [PASSED] ttm_tt_unpopulate_basic
[11:26:04] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:26:04] [PASSED] ttm_tt_swapin_basic
[11:26:04] ===================== [PASSED] ttm_tt ======================
[11:26:04] =================== ttm_bo (14 subtests) ===================
[11:26:04] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[11:26:04] [PASSED] Cannot be interrupted and sleeps
[11:26:04] [PASSED] Cannot be interrupted, locks straight away
[11:26:04] [PASSED] Can be interrupted, sleeps
[11:26:04] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:26:04] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:26:04] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:26:04] [PASSED] ttm_bo_reserve_double_resv
[11:26:04] [PASSED] ttm_bo_reserve_interrupted
[11:26:04] [PASSED] ttm_bo_reserve_deadlock
[11:26:04] [PASSED] ttm_bo_unreserve_basic
[11:26:04] [PASSED] ttm_bo_unreserve_pinned
[11:26:04] [PASSED] ttm_bo_unreserve_bulk
[11:26:04] [PASSED] ttm_bo_fini_basic
[11:26:04] [PASSED] ttm_bo_fini_shared_resv
[11:26:04] [PASSED] ttm_bo_pin_basic
[11:26:04] [PASSED] ttm_bo_pin_unpin_resource
[11:26:04] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:26:04] ===================== [PASSED] ttm_bo ======================
[11:26:04] ============== ttm_bo_validate (22 subtests) ===============
[11:26:04] ============== ttm_bo_init_reserved_sys_man ===============
[11:26:04] [PASSED] Buffer object for userspace
[11:26:04] [PASSED] Kernel buffer object
[11:26:04] [PASSED] Shared buffer object
[11:26:04] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:26:04] ============== ttm_bo_init_reserved_mock_man ==============
[11:26:04] [PASSED] Buffer object for userspace
[11:26:04] [PASSED] Kernel buffer object
[11:26:04] [PASSED] Shared buffer object
[11:26:04] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:26:04] [PASSED] ttm_bo_init_reserved_resv
[11:26:04] ================== ttm_bo_validate_basic ==================
[11:26:04] [PASSED] Buffer object for userspace
[11:26:04] [PASSED] Kernel buffer object
[11:26:04] [PASSED] Shared buffer object
[11:26:04] ============== [PASSED] ttm_bo_validate_basic ==============
[11:26:04] [PASSED] ttm_bo_validate_invalid_placement
[11:26:04] ============= ttm_bo_validate_same_placement ==============
[11:26:04] [PASSED] System manager
[11:26:04] [PASSED] VRAM manager
[11:26:04] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:26:04] [PASSED] ttm_bo_validate_failed_alloc
[11:26:04] [PASSED] ttm_bo_validate_pinned
[11:26:04] [PASSED] ttm_bo_validate_busy_placement
[11:26:04] ================ ttm_bo_validate_multihop =================
[11:26:04] [PASSED] Buffer object for userspace
[11:26:04] [PASSED] Kernel buffer object
[11:26:04] [PASSED] Shared buffer object
[11:26:04] ============ [PASSED] ttm_bo_validate_multihop =============
[11:26:04] ========== ttm_bo_validate_no_placement_signaled ==========
[11:26:04] [PASSED] Buffer object in system domain, no page vector
[11:26:04] [PASSED] Buffer object in system domain with an existing page vector
[11:26:04] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:26:04] ======== ttm_bo_validate_no_placement_not_signaled ========
[11:26:04] [PASSED] Buffer object for userspace
[11:26:04] [PASSED] Kernel buffer object
[11:26:04] [PASSED] Shared buffer object
[11:26:04] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:26:04] [PASSED] ttm_bo_validate_move_fence_signaled
[11:26:04] ========= ttm_bo_validate_move_fence_not_signaled =========
[11:26:04] [PASSED] Waits for GPU
[11:26:04] [PASSED] Tries to lock straight away
[11:26:04] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:26:04] [PASSED] ttm_bo_validate_swapout
[11:26:04] [PASSED] ttm_bo_validate_happy_evict
[11:26:04] [PASSED] ttm_bo_validate_all_pinned_evict
[11:26:04] [PASSED] ttm_bo_validate_allowed_only_evict
[11:26:04] [PASSED] ttm_bo_validate_deleted_evict
[11:26:04] [PASSED] ttm_bo_validate_busy_domain_evict
[11:26:04] [PASSED] ttm_bo_validate_evict_gutting
[11:26:04] [PASSED] ttm_bo_validate_recrusive_evict
[11:26:04] ================= [PASSED] ttm_bo_validate =================
[11:26:04] ============================================================
[11:26:04] Testing complete. Ran 102 tests: passed: 102
[11:26:04] Elapsed time: 12.231s total, 1.824s configuring, 10.192s building, 0.184s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[11:26:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:26:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:26:15] Starting KUnit Kernel (1/1)...
[11:26:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:26:15] =============== dma-buf-fence (12 subtests) ================
[11:26:15] [PASSED] test_sanitycheck
[11:26:15] [PASSED] test_signaling
[11:26:15] [PASSED] test_add_callback
[11:26:15] [PASSED] test_late_add_callback
[11:26:15] [PASSED] test_rm_callback
[11:26:15] [PASSED] test_late_rm_callback
[11:26:15] [PASSED] test_status
[11:26:15] [PASSED] test_error
[11:26:15] [PASSED] test_wait
[11:26:15] [PASSED] test_wait_timeout
[11:26:15] [PASSED] test_stub
[11:26:15] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[11:26:15] ================== [PASSED] dma-buf-fence ==================
[11:26:15] ============ dma-buf-fence-chain (11 subtests) =============
[11:26:15] [PASSED] test_sanitycheck
[11:26:15] [PASSED] test_find_seqno
[11:26:15] [PASSED] test_find_signaled
[11:26:15] [PASSED] test_find_out_of_order
[11:26:20] [PASSED] test_find_gap
[11:26:20] [PASSED] test_find_race
[11:26:20] [PASSED] test_signal_forward
[11:26:20] [PASSED] test_signal_backward
[11:26:20] [PASSED] test_wait_forward
[11:26:20] [PASSED] test_wait_backward
[11:26:20] [PASSED] test_wait_random
[11:26:20] =============== [PASSED] dma-buf-fence-chain ===============
[11:26:20] ============ dma-buf-fence-unwrap (10 subtests) ============
[11:26:20] [PASSED] test_sanitycheck
[11:26:20] [PASSED] test_unwrap_array
[11:26:20] [PASSED] test_unwrap_chain
[11:26:20] [PASSED] test_unwrap_chain_array
[11:26:20] [PASSED] test_unwrap_merge
[11:26:20] [PASSED] test_unwrap_merge_duplicate
[11:26:20] [PASSED] test_unwrap_merge_seqno
[11:26:20] [PASSED] test_unwrap_merge_order
[11:26:20] [PASSED] test_unwrap_merge_complex
[11:26:20] [PASSED] test_unwrap_merge_complex_seqno
[11:26:20] ============== [PASSED] dma-buf-fence-unwrap ===============
[11:26:20] ================ dma-buf-resv (5 subtests) =================
[11:26:20] [PASSED] test_sanitycheck
[11:26:20] ===================== test_signaling ======================
[11:26:20] [PASSED] kernel
[11:26:20] [PASSED] write
[11:26:20] [PASSED] read
[11:26:20] [PASSED] bookkeep
[11:26:20] ================= [PASSED] test_signaling ==================
[11:26:20] ====================== test_for_each ======================
[11:26:20] [PASSED] kernel
[11:26:20] [PASSED] write
[11:26:20] [PASSED] read
[11:26:20] [PASSED] bookkeep
[11:26:20] ================== [PASSED] test_for_each ==================
[11:26:20] ================= test_for_each_unlocked ==================
[11:26:20] [PASSED] kernel
[11:26:20] [PASSED] write
[11:26:20] [PASSED] read
[11:26:20] [PASSED] bookkeep
[11:26:20] ============= [PASSED] test_for_each_unlocked ==============
[11:26:20] ===================== test_get_fences =====================
[11:26:20] [PASSED] kernel
[11:26:20] [PASSED] write
[11:26:20] [PASSED] read
[11:26:20] [PASSED] bookkeep
[11:26:20] ================= [PASSED] test_get_fences =================
[11:26:20] ================== [PASSED] dma-buf-resv ===================
[11:26:20] ============================================================
[11:26:20] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[11:26:20] Elapsed time: 15.896s total, 1.875s configuring, 8.749s building, 5.260s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ i915.CI.BAT: success for Move the PLL power save W/A to the display W/A framework (rev2)
2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
` (4 preceding siblings ...)
2026-10-14 11:26 ` ✓ CI.KUnit: success for Move the PLL power save W/A to the display W/A framework (rev2) Patchwork
@ 2026-10-14 11:48 ` Patchwork
2026-10-14 15:26 ` ✓ CI.KUnit: success for Move the PLL power save W/A to the display W/A framework (rev4) Patchwork
2026-10-14 17:52 ` ✗ Xe.CI.BAT: failure for Move the PLL power save W/A to the display W/A framework (rev2) Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-10-14 11:48 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 1111 bytes --]
== Series Details ==
Series: Move the PLL power save W/A to the display W/A framework (rev2)
URL : https://patchwork.freedesktop.org/series/175835/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_19336 -> Patchwork_175835v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_175835v2/index.html
Participating hosts (39 -> 37)
------------------------------
Missing (2): bat-dg2-14 bat-dg2-13
Changes
-------
No changes found
Build changes
-------------
* Linux: CI_DRM_19336 -> Patchwork_175835v2
CI-20190529: 20190529
CI_DRM_19336: c06d7623a198463e9aa2d09a3c33d96fe66ea662 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_9145: 05c13a14f7f8bcda7bff83b8aa033c3c47a4b1fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_175835v2: c06d7623a198463e9aa2d09a3c33d96fe66ea662 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_175835v2/index.html
[-- Attachment #2: Type: text/html, Size: 1676 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/4] drm/i915/dpll: move the PLL power save W/A to the display W/A framework
2026-10-14 10:53 ` [PATCH v2 1/4] drm/i915/dpll: move " Mika Kahola
@ 2026-10-14 13:45 ` Mika Kahola
0 siblings, 0 replies; 13+ messages in thread
From: Mika Kahola @ 2026-10-14 13:45 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Mika Kahola
The condition for W/A 14022081154 was open-coded as a DISPLAY_VER()
check in intel_cx0_pll_power_save_wa(), which also walked the encoders
itself. Neither is specific to the C10 PHY.
Add intel_dpll_power_save_wa(), holding the W/A condition as
INTEL_DISPLAY_WA_14022081154 and the encoder walk, and leave
intel_cx0_pll_power_save_wa() with only the C10 PHY sequence for a
single encoder.
The spec lists the W/A for PTL+, so use DISPLAY_VER() >= 30 instead of
the == 30 the code had. No functional change: the sequence is C10 PHY
specific and intel_encoder_is_c10phy() is never true on display ver 35.
While at it, let the drm_WARN_ON() on the table lookup check the return
value.
BSpec: 74151
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 59 ++++++-------------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
.../drm/i915/display/intel_display_reset.c | 4 +-
.../gpu/drm/i915/display/intel_display_wa.c | 2 +
.../gpu/drm/i915/display/intel_display_wa.h | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 34 ++++++++++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
7 files changed, 58 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b83f0afaa9b5..92cb370d724c 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3700,54 +3700,31 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
/*
* WA 14022081154
- * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle
- * system power. After a system reset (cold boot, S3/4/5, warm reset) if a dedicated
- * PHY is not being brought up shortly, use these steps to move the PHY to the lowest
- * power state to save power. For PTL the workaround is needed only for port A. Port B
- * is not connected.
- *
- * 1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.
- * This brings lanes out of reset and enables the PLL to allow powerdown to be moved
- * to the Disable state.
- * 2. Follow PLL Disable Sequence. This moves powerdown to the Disable state and disables the PLL.
+ * C10 PHY part of the sequence, see intel_dpll_power_save_wa().
*/
-void intel_cx0_pll_power_save_wa(struct intel_display *display)
+void intel_cx0_pll_power_save_wa(struct intel_encoder *encoder)
{
- struct intel_encoder *encoder;
+ struct intel_display *display = to_intel_display(encoder);
+ struct intel_cx0pll_state pll_state = {};
+ int port_clock = 162000;
+ int lane_count = 4;
+ int err;
- if (DISPLAY_VER(display) != 30)
+ if (intel_cx0_pll_is_enabled(encoder))
return;
- for_each_intel_encoder(display->drm, encoder) {
- struct intel_cx0pll_state pll_state = {};
- int port_clock = 162000;
- int lane_count = 4;
-
- if (!intel_encoder_is_dig_port(encoder))
- continue;
-
- if (!intel_encoder_is_c10phy(encoder))
- continue;
-
- if (intel_cx0_pll_is_enabled(encoder))
- continue;
-
- if (intel_c10pll_calc_state_from_table(encoder,
- mtl_c10_edp_tables,
- true, port_clock, lane_count,
- &pll_state) < 0) {
- drm_WARN_ON(display->drm,
- "Unable to calc C10 state from the tables\n");
- continue;
- }
+ err = intel_c10pll_calc_state_from_table(encoder, mtl_c10_edp_tables,
+ true, port_clock, lane_count,
+ &pll_state);
+ if (drm_WARN_ON(display->drm, err))
+ return;
- drm_dbg_kms(display->drm,
- "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
- encoder->base.base.id, encoder->base.name);
+ drm_dbg_kms(display->drm,
+ "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
+ encoder->base.base.id, encoder->base.name);
- intel_cx0pll_enable(encoder, &pll_state);
- intel_cx0pll_disable(encoder);
- }
+ intel_cx0pll_enable(encoder, &pll_state);
+ intel_cx0pll_disable(encoder);
}
static void intel_c10pll_verify_clock(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 95c20eb4b4b7..b63916bfeca7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -78,7 +78,7 @@ bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
void intel_cx0pll_verify_plls(struct intel_display *display);
-void intel_cx0_pll_power_save_wa(struct intel_display *display);
+void intel_cx0_pll_power_save_wa(struct intel_encoder *encoder);
void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c
index 504ec7043cd9..375201798413 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reset.c
+++ b/drivers/gpu/drm/i915/display/intel_display_reset.c
@@ -9,12 +9,12 @@
#include <drm/drm_print.h>
#include "intel_clock_gating.h"
-#include "intel_cx0_phy.h"
#include "intel_display_core.h"
#include "intel_display_driver.h"
#include "intel_display_reset.h"
#include "intel_display_types.h"
#include "intel_display_utils.h"
+#include "intel_dpll_mgr.h"
#include "intel_hotplug.h"
#include "intel_pps.h"
@@ -100,7 +100,7 @@ void intel_display_reset_finish(struct intel_display *display, bool test_only)
intel_pps_unlock_regs_wa(display);
intel_display_driver_init_hw(display);
intel_clock_gating_init(display->drm);
- intel_cx0_pll_power_save_wa(display);
+ intel_dpll_power_save_wa(display);
intel_hpd_init(display);
ret = __intel_display_driver_resume(display, state, ctx);
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 888676693f5e..eeddf10a4071 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -111,6 +111,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
return DISPLAY_VERx100(display) == 3000 ||
DISPLAY_VERx100(display) == 2000 ||
DISPLAY_VERx100(display) == 1401;
+ case INTEL_DISPLAY_WA_14022081154:
+ return DISPLAY_VER(display) >= 30;
case INTEL_DISPLAY_WA_14025769978:
return DISPLAY_VER(display) == 35;
case INTEL_DISPLAY_WA_14026643300:
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index 425a300840aa..acb45fa59aef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -33,6 +33,7 @@ enum intel_display_wa {
INTEL_DISPLAY_WA_14014143976,
INTEL_DISPLAY_WA_14016740474,
INTEL_DISPLAY_WA_14020863754,
+ INTEL_DISPLAY_WA_14022081154,
INTEL_DISPLAY_WA_14025769978,
INTEL_DISPLAY_WA_14026643300,
INTEL_DISPLAY_WA_15013987218,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bfd6f0a19725..65cc028a90da 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -33,6 +33,7 @@
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_display_utils.h"
+#include "intel_display_wa.h"
#include "intel_dkl_phy.h"
#include "intel_dkl_phy_regs.h"
#include "intel_dpio_phy.h"
@@ -5220,12 +5221,43 @@ static void sanitize_dpll_state(struct intel_display *display,
_intel_disable_shared_dpll(display, pll);
}
+/*
+ * WA 14022081154
+ * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle
+ * system power. After a system reset (cold boot, S3/4/5, warm reset) if a dedicated
+ * PHY is not being brought up shortly, use these steps to move the PHY to the lowest
+ * power state to save power. For PTL the workaround is needed only for port A. Port B
+ * is not connected.
+ *
+ * 1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.
+ * This brings lanes out of reset and enables the PLL to allow powerdown to be moved
+ * to the Disable state.
+ * 2. Follow PLL Disable Sequence. This moves powerdown to the Disable state and disables the PLL.
+ */
+void intel_dpll_power_save_wa(struct intel_display *display)
+{
+ struct intel_encoder *encoder;
+
+ if (!intel_display_wa(display, INTEL_DISPLAY_WA_14022081154))
+ return;
+
+ for_each_intel_encoder(display->drm, encoder) {
+ if (!intel_encoder_is_dig_port(encoder))
+ continue;
+
+ if (!intel_encoder_is_c10phy(encoder))
+ continue;
+
+ intel_cx0_pll_power_save_wa(encoder);
+ }
+}
+
void intel_dpll_sanitize_state(struct intel_display *display)
{
struct intel_dpll *pll;
int i;
- intel_cx0_pll_power_save_wa(display);
+ intel_dpll_power_save_wa(display);
for_each_dpll(display, pll, i)
sanitize_dpll_state(display, pll);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f4b84733a58c..0beb8d99fd5e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -461,6 +461,7 @@ void intel_dpll_swap_state(struct intel_atomic_state *state);
void intel_dpll_init(struct intel_display *display);
void intel_dpll_update_ref_clks(struct intel_display *display);
void intel_dpll_readout_hw_state(struct intel_display *display);
+void intel_dpll_power_save_wa(struct intel_display *display);
void intel_dpll_sanitize_state(struct intel_display *display);
void intel_dpll_dump_hw_state(struct intel_display *display,
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/4] drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms
2026-10-14 10:53 ` [PATCH v2 4/4] drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms Mika Kahola
2026-10-14 11:10 ` sashiko-bot
@ 2026-10-14 13:46 ` Mika Kahola
1 sibling, 0 replies; 13+ messages in thread
From: Mika Kahola @ 2026-10-14 13:46 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Mika Kahola
W/A 14022081154 covers PTL+, but only the C10 PHY sequence was ever
implemented. Port A is an LT PHY on display ver 35, so
intel_dpll_power_save_wa() had nothing to run there and the PHY was
left in the reset power state that blocks S0ix.
Add the LT PHY sequence and dispatch on the PHY type. The PLL state is
calculated from the eDP tables at RBR as the C10 sequence does, so the
throwaway state it brings the PLL up with is marked as eDP.
BSpec: 74151
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++-
drivers/gpu/drm/i915/display/intel_lt_phy.c | 29 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_lt_phy.h | 1 +
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 65cc028a90da..df416a05e66d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -5248,7 +5248,10 @@ void intel_dpll_power_save_wa(struct intel_display *display)
if (!intel_encoder_is_c10phy(encoder))
continue;
- intel_cx0_pll_power_save_wa(encoder);
+ if (HAS_LT_PHY(display))
+ intel_lt_phy_pll_power_save_wa(encoder);
+ else
+ intel_cx0_pll_power_save_wa(encoder);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index e05fd23b8a65..d286d33a03ea 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2313,6 +2313,35 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
}
+/*
+ * WA 14022081154
+ * LT PHY part of the sequence, see intel_dpll_power_save_wa().
+ */
+void intel_lt_phy_pll_power_save_wa(struct intel_encoder *encoder)
+{
+ struct intel_display *display = to_intel_display(encoder);
+ struct intel_dpll_hw_state hw_state = {};
+ int port_clock = 162000;
+ int lane_count = 4;
+ int err;
+
+ if (intel_lt_phy_pll_is_enabled(encoder))
+ return;
+
+ err = intel_lt_phy_pll_calc_state_from_table(encoder, xe3plpd_lt_edp_tables,
+ true, true, port_clock, lane_count,
+ &hw_state.ltpll);
+ if (drm_WARN_ON(display->drm, err))
+ return;
+
+ drm_dbg_kms(display->drm,
+ "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
+ encoder->base.base.id, encoder->base.name);
+
+ intel_lt_phy_pll_enable(encoder, &hw_state);
+ intel_lt_phy_pll_disable(encoder);
+}
+
static void intel_lt_phy_pll_verify_clock(struct intel_display *display,
int precomputed_clock,
const char *pll_state_name,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 368ceedb1e0a..a918012b71e8 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -47,6 +47,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
+void intel_lt_phy_pll_power_save_wa(struct intel_encoder *encoder);
void intel_lt_phy_verify_plls(struct intel_display *display);
#endif /* __INTEL_LT_PHY_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✓ CI.KUnit: success for Move the PLL power save W/A to the display W/A framework (rev4)
2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
` (5 preceding siblings ...)
2026-10-14 11:48 ` ✓ i915.CI.BAT: " Patchwork
@ 2026-10-14 15:26 ` Patchwork
2026-10-14 17:52 ` ✗ Xe.CI.BAT: failure for Move the PLL power save W/A to the display W/A framework (rev2) Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-10-14 15:26 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-xe
== Series Details ==
Series: Move the PLL power save W/A to the display W/A framework (rev4)
URL : https://patchwork.freedesktop.org/series/175834/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[15:24:11] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:24:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:24:36] Starting KUnit Kernel (1/1)...
[15:24:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:24:36] ================= gpu_buddy (14 subtests) ==================
[15:24:36] [PASSED] gpu_test_buddy_alloc_limit
[15:24:36] [PASSED] gpu_test_buddy_alloc_optimistic
[15:24:36] [PASSED] gpu_test_buddy_alloc_pessimistic
[15:24:36] [PASSED] gpu_test_buddy_alloc_pathological
[15:24:36] [PASSED] gpu_test_buddy_alloc_contiguous
[15:24:36] [PASSED] gpu_test_buddy_alloc_clear
[15:24:36] [PASSED] gpu_test_buddy_alloc_range
[15:24:37] [PASSED] gpu_test_buddy_alloc_range_bias
[15:24:37] [PASSED] gpu_test_buddy_fragmentation_performance
[15:24:38] [PASSED] gpu_test_buddy_dirty_tracker_performance
[15:24:38] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[15:24:38] [PASSED] gpu_test_buddy_offset_aligned_allocation
[15:24:38] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[15:24:38] [PASSED] gpu_test_buddy_addr_to_block
[15:24:38] ==================== [PASSED] gpu_buddy ====================
[15:24:38] ============================================================
[15:24:38] Testing complete. Ran 14 tests: passed: 14
[15:24:38] Elapsed time: 27.439s total, 4.440s configuring, 20.881s building, 2.058s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:24:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:24:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:25:15] Starting KUnit Kernel (1/1)...
[15:25:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:25:15] ================== guc_buf (11 subtests) ===================
[15:25:15] [PASSED] test_smallest
[15:25:15] [PASSED] test_largest
[15:25:15] [PASSED] test_granular
[15:25:15] [PASSED] test_unique
[15:25:15] [PASSED] test_overlap
[15:25:15] [PASSED] test_reusable
[15:25:15] [PASSED] test_too_big
[15:25:15] [PASSED] test_flush
[15:25:15] [PASSED] test_lookup
[15:25:15] [PASSED] test_data
[15:25:15] [PASSED] test_class
[15:25:15] ===================== [PASSED] guc_buf =====================
[15:25:15] =================== guc_dbm (7 subtests) ===================
[15:25:15] [PASSED] test_empty
[15:25:15] [PASSED] test_default
[15:25:15] ======================== test_size ========================
[15:25:15] [PASSED] 4
[15:25:15] [PASSED] 8
[15:25:15] [PASSED] 32
[15:25:15] [PASSED] 256
[15:25:15] ==================== [PASSED] test_size ====================
[15:25:15] ======================= test_reuse ========================
[15:25:15] [PASSED] 4
[15:25:15] [PASSED] 8
[15:25:15] [PASSED] 32
[15:25:15] [PASSED] 256
[15:25:15] =================== [PASSED] test_reuse ====================
[15:25:15] =================== test_range_overlap ====================
[15:25:15] [PASSED] 4
[15:25:15] [PASSED] 8
[15:25:15] [PASSED] 32
[15:25:15] [PASSED] 256
[15:25:15] =============== [PASSED] test_range_overlap ================
[15:25:15] =================== test_range_compact ====================
[15:25:15] [PASSED] 4
[15:25:15] [PASSED] 8
[15:25:15] [PASSED] 32
[15:25:15] [PASSED] 256
[15:25:15] =============== [PASSED] test_range_compact ================
[15:25:15] ==================== test_range_spare =====================
[15:25:15] [PASSED] 4
[15:25:15] [PASSED] 8
[15:25:15] [PASSED] 32
[15:25:15] [PASSED] 256
[15:25:15] ================ [PASSED] test_range_spare =================
[15:25:15] ===================== [PASSED] guc_dbm =====================
[15:25:15] =================== guc_idm (6 subtests) ===================
[15:25:15] [PASSED] bad_init
[15:25:15] [PASSED] no_init
[15:25:15] [PASSED] init_fini
[15:25:15] [PASSED] check_used
[15:25:15] [PASSED] check_quota
[15:25:15] [PASSED] check_all
[15:25:15] ===================== [PASSED] guc_idm =====================
[15:25:15] ============== guc_klv_helpers (13 subtests) ===============
[15:25:15] [PASSED] test_count
[15:25:15] [PASSED] test_encode_u32
[15:25:15] [PASSED] test_encode_u64
[15:25:15] [PASSED] test_encode_string
[15:25:15] [PASSED] test_encode_object_raw
[15:25:15] [PASSED] test_encode_object_klv
[15:25:15] [PASSED] test_encode_object_nested
[15:25:15] [PASSED] test_encode_object_basic
[15:25:15] ===================== test_decode_u16 =====================
[15:25:15] [PASSED] empty
[15:25:15] [PASSED] valid
[15:25:15] [PASSED] max
[15:25:15] [PASSED] big
[15:25:15] [PASSED] long
[15:25:15] ================= [PASSED] test_decode_u16 =================
[15:25:15] ===================== test_decode_u32 =====================
[15:25:15] [PASSED] empty
[15:25:15] [PASSED] valid
[15:25:15] [PASSED] max
[15:25:15] [PASSED] long
[15:25:15] ================= [PASSED] test_decode_u32 =================
[15:25:15] ===================== test_decode_u64 =====================
[15:25:15] [PASSED] empty
[15:25:15] [PASSED] short
[15:25:15] [PASSED] valid
[15:25:15] [PASSED] max
[15:25:15] [PASSED] long
[15:25:15] ================= [PASSED] test_decode_u64 =================
[15:25:15] ===================== test_decode_str =====================
[15:25:15] [PASSED] empty
[15:25:15] [PASSED] one
[15:25:15] [PASSED] one_trash
[15:25:15] [PASSED] two
[15:25:15] [PASSED] two_trash
[15:25:15] [PASSED] three
[15:25:15] [PASSED] dword
[15:25:15] [PASSED] four
[15:25:15] [PASSED] five
[15:25:15] [PASSED] six
[15:25:15] [PASSED] seven
[15:25:15] [PASSED] qword
[15:25:15] ================= [PASSED] test_decode_str =================
[15:25:15] [PASSED] test_print
[15:25:15] ================= [PASSED] guc_klv_helpers =================
[15:25:15] =================== xe_log (4 subtests) ====================
[15:25:15] [PASSED] demo_cper
[15:25:15] [PASSED] demo_dmesg
[15:25:15] ======================= test_dmesg ========================
[15:25:15] [PASSED] test_fatal
[15:25:15] [PASSED] test_fatal_tile
[15:25:15] [PASSED] test_fatal_gt
[15:25:15] [PASSED] test_fatal_comp
[15:25:15] [PASSED] test_fatal_comp_tile
[15:25:15] [PASSED] test_fatal_comp_gt
[15:25:15] [PASSED] test_fatal_all
[15:25:15] [PASSED] test_recoverable
[15:25:15] [PASSED] test_recoverable_tile
[15:25:15] [PASSED] test_recoverable_gt
[15:25:15] [PASSED] test_recoverable_comp
[15:25:15] [PASSED] test_recoverable_comp_tile
[15:25:15] [PASSED] test_recoverable_comp_gt
[15:25:15] [PASSED] test_recoverable_all
[15:25:15] [PASSED] test_info
[15:25:15] [PASSED] test_info_tile
[15:25:15] [PASSED] test_info_gt
[15:25:15] [PASSED] test_info_err
[15:25:15] [PASSED] test_info_comp
[15:25:15] [PASSED] test_info_comp_tile
[15:25:15] [PASSED] test_info_comp_gt
[15:25:15] [PASSED] test_info_all
[15:25:15] [PASSED] test_hw_fatal
[15:25:15] [PASSED] test_hw_recoverable
[15:25:15] [PASSED] test_hw_corrected
[15:25:15] [PASSED] test_hw_informational
[15:25:15] =================== [PASSED] test_dmesg ====================
[15:25:15] ====================== test_invalid =======================
[15:25:15] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[15:25:15] ================== [SKIPPED] test_invalid ==================
[15:25:15] ===================== [PASSED] xe_log ======================
[15:25:15] ================== no_relay (3 subtests) ===================
[15:25:15] [PASSED] xe_drops_guc2pf_if_not_ready
[15:25:15] [PASSED] xe_drops_guc2vf_if_not_ready
[15:25:15] [PASSED] xe_rejects_send_if_not_ready
[15:25:15] ==================== [PASSED] no_relay =====================
[15:25:15] ================== pf_relay (14 subtests) ==================
[15:25:15] [PASSED] pf_rejects_guc2pf_too_short
[15:25:15] [PASSED] pf_rejects_guc2pf_too_long
[15:25:15] [PASSED] pf_rejects_guc2pf_no_payload
[15:25:15] [PASSED] pf_fails_no_payload
[15:25:15] [PASSED] pf_fails_bad_origin
[15:25:15] [PASSED] pf_fails_bad_type
[15:25:15] [PASSED] pf_txn_reports_error
[15:25:15] [PASSED] pf_txn_sends_pf2guc
[15:25:15] [PASSED] pf_sends_pf2guc
[15:25:15] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:25:15] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:25:15] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:25:15] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:25:15] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:25:15] ==================== [PASSED] pf_relay =====================
[15:25:15] ================== vf_relay (3 subtests) ===================
[15:25:15] [PASSED] vf_rejects_guc2vf_too_short
[15:25:15] [PASSED] vf_rejects_guc2vf_too_long
[15:25:15] [PASSED] vf_rejects_guc2vf_no_payload
[15:25:15] ==================== [PASSED] vf_relay =====================
[15:25:15] ================ pf_gt_config (9 subtests) =================
[15:25:15] [PASSED] fair_contexts_1vf
[15:25:15] [PASSED] fair_doorbells_1vf
[15:25:15] [PASSED] fair_ggtt_1vf
[15:25:15] ====================== fair_vram_1vf ======================
[15:25:15] [PASSED] 3.50 GiB
[15:25:15] [PASSED] 11.5 GiB
[15:25:15] [PASSED] 15.5 GiB
[15:25:15] [PASSED] 31.5 GiB
[15:25:15] [PASSED] 63.5 GiB
[15:25:15] [PASSED] 1.91 GiB
[15:25:15] ================== [PASSED] fair_vram_1vf ==================
[15:25:15] ================ fair_vram_1vf_admin_only =================
[15:25:15] [PASSED] 3.50 GiB
[15:25:15] [PASSED] 11.5 GiB
[15:25:15] [PASSED] 15.5 GiB
[15:25:15] [PASSED] 31.5 GiB
[15:25:15] [PASSED] 63.5 GiB
[15:25:15] [PASSED] 1.91 GiB
[15:25:15] ============ [PASSED] fair_vram_1vf_admin_only =============
[15:25:15] ====================== fair_contexts ======================
[15:25:15] [PASSED] 1 VF
[15:25:15] [PASSED] 2 VFs
[15:25:15] [PASSED] 3 VFs
[15:25:15] [PASSED] 4 VFs
[15:25:15] [PASSED] 5 VFs
[15:25:15] [PASSED] 6 VFs
[15:25:15] [PASSED] 7 VFs
[15:25:15] [PASSED] 8 VFs
[15:25:15] [PASSED] 9 VFs
[15:25:15] [PASSED] 10 VFs
[15:25:15] [PASSED] 11 VFs
[15:25:15] [PASSED] 12 VFs
[15:25:15] [PASSED] 13 VFs
[15:25:15] [PASSED] 14 VFs
[15:25:15] [PASSED] 15 VFs
[15:25:15] [PASSED] 16 VFs
[15:25:15] [PASSED] 17 VFs
[15:25:15] [PASSED] 18 VFs
[15:25:15] [PASSED] 19 VFs
[15:25:15] [PASSED] 20 VFs
[15:25:15] [PASSED] 21 VFs
[15:25:15] [PASSED] 22 VFs
[15:25:15] [PASSED] 23 VFs
[15:25:15] [PASSED] 24 VFs
[15:25:15] [PASSED] 25 VFs
[15:25:15] [PASSED] 26 VFs
[15:25:15] [PASSED] 27 VFs
[15:25:15] [PASSED] 28 VFs
[15:25:15] [PASSED] 29 VFs
[15:25:15] [PASSED] 30 VFs
[15:25:15] [PASSED] 31 VFs
[15:25:15] [PASSED] 32 VFs
[15:25:15] [PASSED] 33 VFs
[15:25:15] [PASSED] 34 VFs
[15:25:15] [PASSED] 35 VFs
[15:25:15] [PASSED] 36 VFs
[15:25:15] [PASSED] 37 VFs
[15:25:15] [PASSED] 38 VFs
[15:25:15] [PASSED] 39 VFs
[15:25:15] [PASSED] 40 VFs
[15:25:15] [PASSED] 41 VFs
[15:25:15] [PASSED] 42 VFs
[15:25:15] [PASSED] 43 VFs
[15:25:15] [PASSED] 44 VFs
[15:25:15] [PASSED] 45 VFs
[15:25:15] [PASSED] 46 VFs
[15:25:15] [PASSED] 47 VFs
[15:25:15] [PASSED] 48 VFs
[15:25:15] [PASSED] 49 VFs
[15:25:15] [PASSED] 50 VFs
[15:25:15] [PASSED] 51 VFs
[15:25:15] [PASSED] 52 VFs
[15:25:15] [PASSED] 53 VFs
[15:25:15] [PASSED] 54 VFs
[15:25:15] [PASSED] 55 VFs
[15:25:15] [PASSED] 56 VFs
[15:25:15] [PASSED] 57 VFs
[15:25:15] [PASSED] 58 VFs
[15:25:15] [PASSED] 59 VFs
[15:25:15] [PASSED] 60 VFs
[15:25:15] [PASSED] 61 VFs
[15:25:15] [PASSED] 62 VFs
[15:25:15] [PASSED] 63 VFs
[15:25:15] ================== [PASSED] fair_contexts ==================
[15:25:15] ===================== fair_doorbells ======================
[15:25:15] [PASSED] 1 VF
[15:25:15] [PASSED] 2 VFs
[15:25:15] [PASSED] 3 VFs
[15:25:15] [PASSED] 4 VFs
[15:25:15] [PASSED] 5 VFs
[15:25:15] [PASSED] 6 VFs
[15:25:15] [PASSED] 7 VFs
[15:25:15] [PASSED] 8 VFs
[15:25:15] [PASSED] 9 VFs
[15:25:15] [PASSED] 10 VFs
[15:25:15] [PASSED] 11 VFs
[15:25:15] [PASSED] 12 VFs
[15:25:15] [PASSED] 13 VFs
[15:25:15] [PASSED] 14 VFs
[15:25:15] [PASSED] 15 VFs
[15:25:15] [PASSED] 16 VFs
[15:25:15] [PASSED] 17 VFs
[15:25:15] [PASSED] 18 VFs
[15:25:15] [PASSED] 19 VFs
[15:25:15] [PASSED] 20 VFs
[15:25:15] [PASSED] 21 VFs
[15:25:15] [PASSED] 22 VFs
[15:25:15] [PASSED] 23 VFs
[15:25:15] [PASSED] 24 VFs
[15:25:15] [PASSED] 25 VFs
[15:25:15] [PASSED] 26 VFs
[15:25:15] [PASSED] 27 VFs
[15:25:15] [PASSED] 28 VFs
[15:25:15] [PASSED] 29 VFs
[15:25:15] [PASSED] 30 VFs
[15:25:15] [PASSED] 31 VFs
[15:25:15] [PASSED] 32 VFs
[15:25:15] [PASSED] 33 VFs
[15:25:15] [PASSED] 34 VFs
[15:25:15] [PASSED] 35 VFs
[15:25:15] [PASSED] 36 VFs
[15:25:15] [PASSED] 37 VFs
[15:25:15] [PASSED] 38 VFs
[15:25:15] [PASSED] 39 VFs
[15:25:15] [PASSED] 40 VFs
[15:25:15] [PASSED] 41 VFs
[15:25:15] [PASSED] 42 VFs
[15:25:15] [PASSED] 43 VFs
[15:25:15] [PASSED] 44 VFs
[15:25:15] [PASSED] 45 VFs
[15:25:15] [PASSED] 46 VFs
[15:25:15] [PASSED] 47 VFs
[15:25:15] [PASSED] 48 VFs
[15:25:15] [PASSED] 49 VFs
[15:25:15] [PASSED] 50 VFs
[15:25:15] [PASSED] 51 VFs
[15:25:15] [PASSED] 52 VFs
[15:25:15] [PASSED] 53 VFs
[15:25:15] [PASSED] 54 VFs
[15:25:15] [PASSED] 55 VFs
[15:25:15] [PASSED] 56 VFs
[15:25:15] [PASSED] 57 VFs
[15:25:15] [PASSED] 58 VFs
[15:25:15] [PASSED] 59 VFs
[15:25:15] [PASSED] 60 VFs
[15:25:15] [PASSED] 61 VFs
[15:25:15] [PASSED] 62 VFs
[15:25:15] [PASSED] 63 VFs
[15:25:15] ================= [PASSED] fair_doorbells ==================
[15:25:15] ======================== fair_ggtt ========================
[15:25:15] [PASSED] 1 VF
[15:25:15] [PASSED] 2 VFs
[15:25:15] [PASSED] 3 VFs
[15:25:15] [PASSED] 4 VFs
[15:25:15] [PASSED] 5 VFs
[15:25:15] [PASSED] 6 VFs
[15:25:15] [PASSED] 7 VFs
[15:25:15] [PASSED] 8 VFs
[15:25:15] [PASSED] 9 VFs
[15:25:15] [PASSED] 10 VFs
[15:25:15] [PASSED] 11 VFs
[15:25:15] [PASSED] 12 VFs
[15:25:15] [PASSED] 13 VFs
[15:25:15] [PASSED] 14 VFs
[15:25:15] [PASSED] 15 VFs
[15:25:15] [PASSED] 16 VFs
[15:25:15] [PASSED] 17 VFs
[15:25:15] [PASSED] 18 VFs
[15:25:15] [PASSED] 19 VFs
[15:25:15] [PASSED] 20 VFs
[15:25:15] [PASSED] 21 VFs
[15:25:15] [PASSED] 22 VFs
[15:25:15] [PASSED] 23 VFs
[15:25:15] [PASSED] 24 VFs
[15:25:15] [PASSED] 25 VFs
[15:25:15] [PASSED] 26 VFs
[15:25:15] [PASSED] 27 VFs
[15:25:15] [PASSED] 28 VFs
[15:25:15] [PASSED] 29 VFs
[15:25:15] [PASSED] 30 VFs
[15:25:15] [PASSED] 31 VFs
[15:25:15] [PASSED] 32 VFs
[15:25:15] [PASSED] 33 VFs
[15:25:15] [PASSED] 34 VFs
[15:25:15] [PASSED] 35 VFs
[15:25:15] [PASSED] 36 VFs
[15:25:15] [PASSED] 37 VFs
[15:25:15] [PASSED] 38 VFs
[15:25:15] [PASSED] 39 VFs
[15:25:16] [PASSED] 40 VFs
[15:25:16] [PASSED] 41 VFs
[15:25:16] [PASSED] 42 VFs
[15:25:16] [PASSED] 43 VFs
[15:25:16] [PASSED] 44 VFs
[15:25:16] [PASSED] 45 VFs
[15:25:16] [PASSED] 46 VFs
[15:25:16] [PASSED] 47 VFs
[15:25:16] [PASSED] 48 VFs
[15:25:16] [PASSED] 49 VFs
[15:25:16] [PASSED] 50 VFs
[15:25:16] [PASSED] 51 VFs
[15:25:16] [PASSED] 52 VFs
[15:25:16] [PASSED] 53 VFs
[15:25:16] [PASSED] 54 VFs
[15:25:16] [PASSED] 55 VFs
[15:25:16] [PASSED] 56 VFs
[15:25:16] [PASSED] 57 VFs
[15:25:16] [PASSED] 58 VFs
[15:25:16] [PASSED] 59 VFs
[15:25:16] [PASSED] 60 VFs
[15:25:16] [PASSED] 61 VFs
[15:25:16] [PASSED] 62 VFs
[15:25:16] [PASSED] 63 VFs
[15:25:16] ==================== [PASSED] fair_ggtt ====================
[15:25:16] ======================== fair_vram ========================
[15:25:16] [PASSED] 1 VF
[15:25:16] [PASSED] 2 VFs
[15:25:16] [PASSED] 3 VFs
[15:25:16] [PASSED] 4 VFs
[15:25:16] [PASSED] 5 VFs
[15:25:16] [PASSED] 6 VFs
[15:25:16] [PASSED] 7 VFs
[15:25:16] [PASSED] 8 VFs
[15:25:16] [PASSED] 9 VFs
[15:25:16] [PASSED] 10 VFs
[15:25:16] [PASSED] 11 VFs
[15:25:16] [PASSED] 12 VFs
[15:25:16] [PASSED] 13 VFs
[15:25:16] [PASSED] 14 VFs
[15:25:16] [PASSED] 15 VFs
[15:25:16] [PASSED] 16 VFs
[15:25:16] [PASSED] 17 VFs
[15:25:16] [PASSED] 18 VFs
[15:25:16] [PASSED] 19 VFs
[15:25:16] [PASSED] 20 VFs
[15:25:16] [PASSED] 21 VFs
[15:25:16] [PASSED] 22 VFs
[15:25:16] [PASSED] 23 VFs
[15:25:16] [PASSED] 24 VFs
[15:25:16] [PASSED] 25 VFs
[15:25:16] [PASSED] 26 VFs
[15:25:16] [PASSED] 27 VFs
[15:25:16] [PASSED] 28 VFs
[15:25:16] [PASSED] 29 VFs
[15:25:16] [PASSED] 30 VFs
[15:25:16] [PASSED] 31 VFs
[15:25:16] [PASSED] 32 VFs
[15:25:16] [PASSED] 33 VFs
[15:25:16] [PASSED] 34 VFs
[15:25:16] [PASSED] 35 VFs
[15:25:16] [PASSED] 36 VFs
[15:25:16] [PASSED] 37 VFs
[15:25:16] [PASSED] 38 VFs
[15:25:16] [PASSED] 39 VFs
[15:25:16] [PASSED] 40 VFs
[15:25:16] [PASSED] 41 VFs
[15:25:16] [PASSED] 42 VFs
[15:25:16] [PASSED] 43 VFs
[15:25:16] [PASSED] 44 VFs
[15:25:16] [PASSED] 45 VFs
[15:25:16] [PASSED] 46 VFs
[15:25:16] [PASSED] 47 VFs
[15:25:16] [PASSED] 48 VFs
[15:25:16] [PASSED] 49 VFs
[15:25:16] [PASSED] 50 VFs
[15:25:16] [PASSED] 51 VFs
[15:25:16] [PASSED] 52 VFs
[15:25:16] [PASSED] 53 VFs
[15:25:16] [PASSED] 54 VFs
[15:25:16] [PASSED] 55 VFs
[15:25:16] [PASSED] 56 VFs
[15:25:16] [PASSED] 57 VFs
[15:25:16] [PASSED] 58 VFs
[15:25:16] [PASSED] 59 VFs
[15:25:16] [PASSED] 60 VFs
[15:25:16] [PASSED] 61 VFs
[15:25:16] [PASSED] 62 VFs
[15:25:16] [PASSED] 63 VFs
[15:25:16] ==================== [PASSED] fair_vram ====================
[15:25:16] ================== [PASSED] pf_gt_config ===================
[15:25:16] ===================== lmtt (1 subtest) =====================
[15:25:16] ======================== test_ops =========================
[15:25:16] [PASSED] 2-level
[15:25:16] [PASSED] multi-level
[15:25:16] ==================== [PASSED] test_ops =====================
[15:25:16] ====================== [PASSED] lmtt =======================
[15:25:16] ================= sriov_packet (1 subtest) =================
[15:25:16] [PASSED] test_descriptor_init
[15:25:16] ================== [PASSED] sriov_packet ===================
[15:25:16] ================= pf_service (11 subtests) =================
[15:25:16] [PASSED] pf_negotiate_any
[15:25:16] [PASSED] pf_negotiate_base_match
[15:25:16] [PASSED] pf_negotiate_base_newer
[15:25:16] [PASSED] pf_negotiate_base_next
[15:25:16] [SKIPPED] pf_negotiate_base_older (no older minor)
[15:25:16] [PASSED] pf_negotiate_base_prev
[15:25:16] [PASSED] pf_negotiate_latest_match
[15:25:16] [PASSED] pf_negotiate_latest_newer
[15:25:16] [PASSED] pf_negotiate_latest_next
[15:25:16] [SKIPPED] pf_negotiate_latest_older (no older minor)
[15:25:16] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[15:25:16] =================== [PASSED] pf_service ====================
[15:25:16] ================= xe_guc_g2g (2 subtests) ==================
[15:25:16] ============== xe_live_guc_g2g_kunit_default ==============
[15:25:16] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[15:25:16] ============== xe_live_guc_g2g_kunit_allmem ===============
[15:25:16] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[15:25:16] =================== [SKIPPED] xe_guc_g2g ===================
[15:25:16] =================== xe_mocs (2 subtests) ===================
[15:25:16] ================ xe_live_mocs_kernel_kunit ================
[15:25:16] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:25:16] ================ xe_live_mocs_reset_kunit =================
[15:25:16] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:25:16] ==================== [SKIPPED] xe_mocs =====================
[15:25:16] ================= xe_migrate (2 subtests) ==================
[15:25:16] ================= xe_migrate_sanity_kunit =================
[15:25:16] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:25:16] ================== xe_validate_ccs_kunit ==================
[15:25:16] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:25:16] =================== [SKIPPED] xe_migrate ===================
[15:25:16] ================== xe_dma_buf (1 subtest) ==================
[15:25:16] ==================== xe_dma_buf_kunit =====================
[15:25:16] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:25:16] =================== [SKIPPED] xe_dma_buf ===================
[15:25:16] ================= xe_bo_shrink (1 subtest) =================
[15:25:16] =================== xe_bo_shrink_kunit ====================
[15:25:16] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:25:16] ================== [SKIPPED] xe_bo_shrink ==================
[15:25:16] ==================== xe_bo (2 subtests) ====================
[15:25:16] ================== xe_ccs_migrate_kunit ===================
[15:25:16] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:25:16] ==================== xe_bo_evict_kunit ====================
[15:25:16] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:25:16] ===================== [SKIPPED] xe_bo ======================
[15:25:16] =================== xe_any (9 subtests) ====================
[15:25:16] [PASSED] test_to_xe
[15:25:16] [PASSED] test_to_dev
[15:25:16] [PASSED] test_to_pdev
[15:25:16] [PASSED] test_to_drm
[15:25:16] [PASSED] test_if_pdev
[15:25:16] [PASSED] test_if_xe
[15:25:16] [PASSED] test_if_tile
[15:25:16] [PASSED] test_if_gt
[15:25:16] [PASSED] test_to_id
[15:25:16] ===================== [PASSED] xe_any ======================
[15:25:16] ==================== args (13 subtests) ====================
[15:25:16] [PASSED] count_args_test
[15:25:16] [PASSED] call_args_example
[15:25:16] [PASSED] call_args_test
[15:25:16] [PASSED] drop_first_arg_example
[15:25:16] [PASSED] drop_first_arg_test
[15:25:16] [PASSED] first_arg_example
[15:25:16] [PASSED] first_arg_test
[15:25:16] [PASSED] last_arg_example
[15:25:16] [PASSED] last_arg_test
[15:25:16] [PASSED] pick_arg_example
[15:25:16] [PASSED] if_args_example
[15:25:16] [PASSED] if_args_test
[15:25:16] [PASSED] sep_comma_example
[15:25:16] ====================== [PASSED] args =======================
[15:25:16] =================== xe_pci (3 subtests) ====================
[15:25:16] ==================== check_graphics_ip ====================
[15:25:16] [PASSED] 12.00 Xe_LP
[15:25:16] [PASSED] 12.10 Xe_LP+
[15:25:16] [PASSED] 12.55 Xe_HPG
[15:25:16] [PASSED] 12.60 Xe_HPC
[15:25:16] [PASSED] 12.70 Xe_LPG
[15:25:16] [PASSED] 12.71 Xe_LPG
[15:25:16] [PASSED] 12.74 Xe_LPG+
[15:25:16] [PASSED] 20.01 Xe2_HPG
[15:25:16] [PASSED] 20.02 Xe2_HPG
[15:25:16] [PASSED] 20.04 Xe2_LPG
[15:25:16] [PASSED] 30.00 Xe3_LPG
[15:25:16] [PASSED] 30.01 Xe3_LPG
[15:25:16] [PASSED] 30.03 Xe3_LPG
[15:25:16] [PASSED] 30.04 Xe3_LPG
[15:25:16] [PASSED] 30.05 Xe3_LPG
[15:25:16] [PASSED] 35.10 Xe3p_LPG
[15:25:16] [PASSED] 35.11 Xe3p_XPC
[15:25:16] ================ [PASSED] check_graphics_ip ================
[15:25:16] ===================== check_media_ip ======================
[15:25:16] [PASSED] 12.00 Xe_M
[15:25:16] [PASSED] 12.55 Xe_HPM
[15:25:16] [PASSED] 13.00 Xe_LPM+
[15:25:16] [PASSED] 13.01 Xe2_HPM
[15:25:16] [PASSED] 20.00 Xe2_LPM
[15:25:16] [PASSED] 30.00 Xe3_LPM
[15:25:16] [PASSED] 30.02 Xe3_LPM
[15:25:16] [PASSED] 35.00 Xe3p_LPM
[15:25:16] [PASSED] 35.03 Xe3p_HPM
[15:25:16] ================= [PASSED] check_media_ip ==================
[15:25:16] =================== check_platform_desc ===================
[15:25:16] [PASSED] 0x9A60 (TIGERLAKE)
[15:25:16] [PASSED] 0x9A68 (TIGERLAKE)
[15:25:16] [PASSED] 0x9A70 (TIGERLAKE)
[15:25:16] [PASSED] 0x9A40 (TIGERLAKE)
[15:25:16] [PASSED] 0x9A49 (TIGERLAKE)
[15:25:16] [PASSED] 0x9A59 (TIGERLAKE)
[15:25:16] [PASSED] 0x9A78 (TIGERLAKE)
[15:25:16] [PASSED] 0x9AC0 (TIGERLAKE)
[15:25:16] [PASSED] 0x9AC9 (TIGERLAKE)
[15:25:16] [PASSED] 0x9AD9 (TIGERLAKE)
[15:25:16] [PASSED] 0x9AF8 (TIGERLAKE)
[15:25:16] [PASSED] 0x4C80 (ROCKETLAKE)
[15:25:16] [PASSED] 0x4C8A (ROCKETLAKE)
[15:25:16] [PASSED] 0x4C8B (ROCKETLAKE)
[15:25:16] [PASSED] 0x4C8C (ROCKETLAKE)
[15:25:16] [PASSED] 0x4C90 (ROCKETLAKE)
[15:25:16] [PASSED] 0x4C9A (ROCKETLAKE)
[15:25:16] [PASSED] 0x4680 (ALDERLAKE_S)
[15:25:16] [PASSED] 0x4682 (ALDERLAKE_S)
[15:25:16] [PASSED] 0x4688 (ALDERLAKE_S)
[15:25:16] [PASSED] 0x468A (ALDERLAKE_S)
[15:25:16] [PASSED] 0x468B (ALDERLAKE_S)
[15:25:16] [PASSED] 0x4690 (ALDERLAKE_S)
[15:25:16] [PASSED] 0x4692 (ALDERLAKE_S)
[15:25:16] [PASSED] 0x4693 (ALDERLAKE_S)
[15:25:16] [PASSED] 0x46A0 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46A1 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46A2 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46A3 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46A6 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46A8 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46AA (ALDERLAKE_P)
[15:25:16] [PASSED] 0x462A (ALDERLAKE_P)
[15:25:16] [PASSED] 0x4626 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x4628 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46B0 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46B1 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46B2 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46B3 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46C0 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46C1 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46C2 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46C3 (ALDERLAKE_P)
[15:25:16] [PASSED] 0x46D0 (ALDERLAKE_N)
[15:25:16] [PASSED] 0x46D1 (ALDERLAKE_N)
[15:25:16] [PASSED] 0x46D2 (ALDERLAKE_N)
[15:25:16] [PASSED] 0x46D3 (ALDERLAKE_N)
[15:25:16] [PASSED] 0x46D4 (ALDERLAKE_N)
[15:25:16] [PASSED] 0xA721 (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA7A1 (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA7A9 (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA7AC (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA7AD (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA720 (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA7A0 (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA7A8 (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA7AA (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA7AB (ALDERLAKE_P)
[15:25:16] [PASSED] 0xA780 (ALDERLAKE_S)
[15:25:16] [PASSED] 0xA781 (ALDERLAKE_S)
[15:25:16] [PASSED] 0xA782 (ALDERLAKE_S)
[15:25:16] [PASSED] 0xA783 (ALDERLAKE_S)
[15:25:16] [PASSED] 0xA788 (ALDERLAKE_S)
[15:25:16] [PASSED] 0xA789 (ALDERLAKE_S)
[15:25:16] [PASSED] 0xA78A (ALDERLAKE_S)
[15:25:16] [PASSED] 0xA78B (ALDERLAKE_S)
[15:25:16] [PASSED] 0x4905 (DG1)
[15:25:16] [PASSED] 0x4906 (DG1)
[15:25:16] [PASSED] 0x4907 (DG1)
[15:25:16] [PASSED] 0x4908 (DG1)
[15:25:16] [PASSED] 0x4909 (DG1)
[15:25:16] [PASSED] 0x56C0 (DG2)
[15:25:16] [PASSED] 0x56C2 (DG2)
[15:25:16] [PASSED] 0x56C1 (DG2)
[15:25:16] [PASSED] 0x7D51 (METEORLAKE)
[15:25:16] [PASSED] 0x7DD1 (METEORLAKE)
[15:25:16] [PASSED] 0x7D41 (METEORLAKE)
[15:25:16] [PASSED] 0x7D67 (METEORLAKE)
[15:25:16] [PASSED] 0xB640 (METEORLAKE)
[15:25:16] [PASSED] 0x56A0 (DG2)
[15:25:16] [PASSED] 0x56A1 (DG2)
[15:25:16] [PASSED] 0x56A2 (DG2)
[15:25:16] [PASSED] 0x56BE (DG2)
[15:25:16] [PASSED] 0x56BF (DG2)
[15:25:16] [PASSED] 0x5690 (DG2)
[15:25:16] [PASSED] 0x5691 (DG2)
[15:25:16] [PASSED] 0x5692 (DG2)
[15:25:16] [PASSED] 0x56A5 (DG2)
[15:25:16] [PASSED] 0x56A6 (DG2)
[15:25:16] [PASSED] 0x56B0 (DG2)
[15:25:16] [PASSED] 0x56B1 (DG2)
[15:25:16] [PASSED] 0x56BA (DG2)
[15:25:16] [PASSED] 0x56BB (DG2)
[15:25:16] [PASSED] 0x56BC (DG2)
[15:25:16] [PASSED] 0x56BD (DG2)
[15:25:16] [PASSED] 0x5693 (DG2)
[15:25:16] [PASSED] 0x5694 (DG2)
[15:25:16] [PASSED] 0x5695 (DG2)
[15:25:16] [PASSED] 0x56A3 (DG2)
[15:25:16] [PASSED] 0x56A4 (DG2)
[15:25:16] [PASSED] 0x56B2 (DG2)
[15:25:16] [PASSED] 0x56B3 (DG2)
[15:25:16] [PASSED] 0x5696 (DG2)
[15:25:16] [PASSED] 0x5697 (DG2)
[15:25:16] [PASSED] 0xB69 (PVC)
[15:25:16] [PASSED] 0xB6E (PVC)
[15:25:16] [PASSED] 0xBD4 (PVC)
[15:25:16] [PASSED] 0xBD5 (PVC)
[15:25:16] [PASSED] 0xBD6 (PVC)
[15:25:16] [PASSED] 0xBD7 (PVC)
[15:25:16] [PASSED] 0xBD8 (PVC)
[15:25:16] [PASSED] 0xBD9 (PVC)
[15:25:16] [PASSED] 0xBDA (PVC)
[15:25:16] [PASSED] 0xBDB (PVC)
[15:25:16] [PASSED] 0xBE0 (PVC)
[15:25:16] [PASSED] 0xBE1 (PVC)
[15:25:16] [PASSED] 0xBE5 (PVC)
[15:25:16] [PASSED] 0x7D40 (METEORLAKE)
[15:25:16] [PASSED] 0x7D45 (METEORLAKE)
[15:25:16] [PASSED] 0x7D55 (METEORLAKE)
[15:25:16] [PASSED] 0x7D60 (METEORLAKE)
[15:25:16] [PASSED] 0x7DD5 (METEORLAKE)
[15:25:16] [PASSED] 0x6420 (LUNARLAKE)
[15:25:16] [PASSED] 0x64A0 (LUNARLAKE)
[15:25:16] [PASSED] 0x64B0 (LUNARLAKE)
[15:25:16] [PASSED] 0xE202 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE209 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE20B (BATTLEMAGE)
[15:25:16] [PASSED] 0xE20C (BATTLEMAGE)
[15:25:16] [PASSED] 0xE20D (BATTLEMAGE)
[15:25:16] [PASSED] 0xE210 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE211 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE212 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE216 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE220 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE221 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE222 (BATTLEMAGE)
[15:25:16] [PASSED] 0xE223 (BATTLEMAGE)
[15:25:16] [PASSED] 0xB080 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB081 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB082 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB083 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB084 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB085 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB086 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB087 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB08F (PANTHERLAKE)
[15:25:16] [PASSED] 0xB090 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB0A0 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB0A1 (PANTHERLAKE)
[15:25:16] [PASSED] 0xB0B0 (PANTHERLAKE)
[15:25:16] [PASSED] 0xFD80 (PANTHERLAKE)
[15:25:16] [PASSED] 0xFD81 (PANTHERLAKE)
[15:25:16] [PASSED] 0xD740 (NOVALAKE_S)
[15:25:16] [PASSED] 0xD741 (NOVALAKE_S)
[15:25:16] [PASSED] 0xD742 (NOVALAKE_S)
[15:25:16] [PASSED] 0xD743 (NOVALAKE_S)
[15:25:16] [PASSED] 0xD745 (NOVALAKE_S)
[15:25:16] [PASSED] 0xD74A (NOVALAKE_S)
[15:25:16] [PASSED] 0xD74B (NOVALAKE_S)
[15:25:16] [PASSED] 0x674C (CRESCENTISLAND)
[15:25:16] [PASSED] 0x674D (CRESCENTISLAND)
[15:25:16] [PASSED] 0x674E (CRESCENTISLAND)
[15:25:16] [PASSED] 0x674F (CRESCENTISLAND)
[15:25:16] [PASSED] 0x6750 (CRESCENTISLAND)
[15:25:16] [PASSED] 0x6751 (CRESCENTISLAND)
[15:25:16] [PASSED] 0xD750 (NOVALAKE_P)
[15:25:16] [PASSED] 0xD751 (NOVALAKE_P)
[15:25:16] [PASSED] 0xD752 (NOVALAKE_P)
[15:25:16] [PASSED] 0xD753 (NOVALAKE_P)
[15:25:16] [PASSED] 0xD754 (NOVALAKE_P)
[15:25:16] [PASSED] 0xD755 (NOVALAKE_P)
[15:25:16] [PASSED] 0xD756 (NOVALAKE_P)
[15:25:16] [PASSED] 0xD757 (NOVALAKE_P)
[15:25:16] [PASSED] 0xD75F (NOVALAKE_P)
[15:25:16] =============== [PASSED] check_platform_desc ===============
[15:25:16] ===================== [PASSED] xe_pci ======================
[15:25:16] ============= xe_rtp_tables_test (5 subtests) ==============
[15:25:16] ================== xe_rtp_table_gt_test ===================
[15:25:16] [PASSED] gt_was/14011060649
[15:25:16] [PASSED] gt_was/14011059788
[15:25:16] [PASSED] gt_was/14015795083
[15:25:16] [PASSED] gt_was/16021867713
[15:25:16] [PASSED] gt_was/14019449301
[15:25:16] [PASSED] gt_was/16028005424
[15:25:16] [PASSED] gt_was/14026578760
[15:25:16] [PASSED] gt_was/1409420604
[15:25:16] [PASSED] gt_was/1408615072
[15:25:16] [PASSED] gt_was/22010523718
[15:25:16] [PASSED] gt_was/14011006942
[15:25:16] [PASSED] gt_was/14014830051
[15:25:16] [PASSED] gt_was/18018781329
[15:25:16] [PASSED] gt_was/1509235366
[15:25:16] [PASSED] gt_was/18018781329
[15:25:16] [PASSED] gt_was/16016694945
[15:25:16] [PASSED] gt_was/14018575942
[15:25:16] [PASSED] gt_was/22016670082
[15:25:16] [PASSED] gt_was/22016670082
[15:25:16] [PASSED] gt_was/14017421178
[15:25:16] [PASSED] gt_was/16025250150
[15:25:16] [PASSED] gt_was/14021871409
[15:25:16] [PASSED] gt_was/16021865536
[15:25:16] [PASSED] gt_was/14021486841
[15:25:16] [PASSED] gt_was/14025160223
[15:25:16] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[15:25:16] [PASSED] gt_was/14025635424
[15:25:16] [PASSED] gt_was/16028005424
[15:25:16] ============== [PASSED] xe_rtp_table_gt_test ===============
[15:25:16] ================== xe_rtp_table_gt_test ===================
[15:25:16] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[15:25:16] [PASSED] gt_tunings/Tuning: 32B Access Enable
[15:25:16] [PASSED] gt_tunings/Tuning: L3 cache
[15:25:16] [PASSED] gt_tunings/Tuning: L3 cache - media
[15:25:16] [PASSED] gt_tunings/Tuning: Compression Overfetch
[15:25:16] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[15:25:16] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[15:25:16] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[15:25:16] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[15:25:16] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[15:25:16] [PASSED] gt_tunings/Tuning: Stateless compression control
[15:25:16] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[15:25:16] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[15:25:16] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[15:25:16] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[15:25:16] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[15:25:16] ============== [PASSED] xe_rtp_table_gt_test ===============
[15:25:16] ================== xe_rtp_table_oob_test ==================
[15:25:16] [PASSED] oob_was/1607983814
[15:25:16] [PASSED] oob_was/16010904313
[15:25:16] [PASSED] oob_was/18022495364
[15:25:16] [PASSED] oob_was/22012773006
[15:25:16] [PASSED] oob_was/14014475959
[15:25:16] [PASSED] oob_was/22011391025
[15:25:16] [PASSED] oob_was/22012727170
[15:25:16] [PASSED] oob_was/22012727685
[15:25:16] [PASSED] oob_was/22016596838
[15:25:16] [PASSED] oob_was/18020744125
[15:25:16] [PASSED] oob_was/1409600907
[15:25:16] [PASSED] oob_was/22014953428
[15:25:16] [PASSED] oob_was/16017236439
[15:25:16] [PASSED] oob_was/14019821291
[15:25:16] [PASSED] oob_was/14015076503
[15:25:16] [PASSED] oob_was/22016122933
[15:25:16] [PASSED] oob_was/14018913170
[15:25:16] [PASSED] oob_was/14018094691
[15:25:16] [PASSED] oob_was/18024947630
[15:25:16] [PASSED] oob_was/16022287689
[15:25:16] [PASSED] oob_was/13011645652
[15:25:16] [PASSED] oob_was/14022293748
[15:25:16] [PASSED] oob_was/22019794406
[15:25:16] [PASSED] oob_was/22019338487
[15:25:16] [PASSED] oob_was/16023588340
[15:25:16] [PASSED] oob_was/14019789679
[15:25:16] [PASSED] oob_was/14022866841
[15:25:16] [PASSED] oob_was/16021333562
[15:25:16] [PASSED] oob_was/14016712196
[15:25:16] [PASSED] oob_was/14015568240
[15:25:16] [PASSED] oob_was/18013179988
[15:25:16] [PASSED] oob_was/1508761755
[15:25:16] [PASSED] oob_was/16023105232
[15:25:16] [PASSED] oob_was/16026508708
[15:25:16] [PASSED] oob_was/14020001231
[15:25:16] [PASSED] oob_was/16023683509
[15:25:16] [PASSED] oob_was/14025515070
[15:25:16] [PASSED] oob_was/15015404425_disable
[15:25:16] [PASSED] oob_was/16026007364
[15:25:16] [PASSED] oob_was/14020316580
[15:25:16] [PASSED] oob_was/14025883347
[15:25:16] [PASSED] oob_was/16029380221
[15:25:16] [PASSED] oob_was/22022079272
[15:25:16] [PASSED] oob_was/16029897822
[15:25:16] [PASSED] oob_was/14027054324
[15:25:16] [PASSED] oob_was/14025941587
[15:25:16] [PASSED] oob_was/16030224309
[15:25:16] ============== [PASSED] xe_rtp_table_oob_test ==============
[15:25:16] ================ xe_rtp_table_dev_oob_test ================
[15:25:16] [PASSED] device_oob_was/22010954014
[15:25:16] [PASSED] device_oob_was/15015404425
[15:25:16] [PASSED] device_oob_was/22019338487_display
[15:25:16] [PASSED] device_oob_was/14022085890
[15:25:16] [PASSED] device_oob_was/14026539277
[15:25:16] [PASSED] device_oob_was/14026633728
[15:25:16] [PASSED] device_oob_was/14026746987
[15:25:16] [PASSED] device_oob_was/14026779378
[15:25:16] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[15:25:16] ========== xe_rtp_table_missing_upper_bound_test ==========
[15:25:16] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[15:25:16] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[15:25:16] [PASSED] register_whitelist/1806527549
[15:25:16] [PASSED] register_whitelist/allow_read_ctx_timestamp
[15:25:16] [PASSED] register_whitelist/allow_read_queue_timestamp
[15:25:16] [PASSED] register_whitelist/16014440446
[15:25:16] [PASSED] register_whitelist/16017236439
[15:25:16] [PASSED] register_whitelist/16020183090
[15:25:16] [PASSED] register_whitelist/14024997852
[15:25:16] [PASSED] register_whitelist/14024997852
[15:25:16] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[15:25:16] =============== [PASSED] xe_rtp_tables_test ================
[15:25:16] =================== xe_rtp (3 subtests) ====================
[15:25:16] =================== xe_rtp_rules_tests ====================
[15:25:16] [PASSED] no
[15:25:16] [PASSED] yes
[15:25:16] [PASSED] no-and-no
[15:25:16] [PASSED] no-and-yes
[15:25:16] [PASSED] yes-and-no
[15:25:16] [PASSED] yes-and-yes
[15:25:16] [PASSED] no-or-no
[15:25:16] [PASSED] no-or-yes
[15:25:16] [PASSED] yes-or-no
[15:25:16] [PASSED] yes-or-yes
[15:25:16] [PASSED] no-yes-or-yes-no
[15:25:16] [PASSED] no-yes-or-yes-yes
[15:25:16] [PASSED] yes-yes-or-no-yes
[15:25:16] [PASSED] yes-yes-or-yes-yes
[15:25:16] [PASSED] no-no-or-yes-or-no
[15:25:16] [PASSED] or
[15:25:16] [PASSED] or-yes
[15:25:16] [PASSED] or-no
[15:25:16] [PASSED] yes-or
[15:25:16] [PASSED] no-or
[15:25:16] [PASSED] no-or-or-yes
[15:25:16] [PASSED] yes-or-or-no
[15:25:16] [PASSED] no-or-or-no
[15:25:16] [PASSED] missing-context-engine-class
[15:25:16] [PASSED] missing-context-engine-class-or-yes
[15:25:16] [PASSED] missing-context-engine-class-or-or-yes
[15:25:16] =============== [PASSED] xe_rtp_rules_tests ================
[15:25:16] =============== xe_rtp_process_to_sr_tests ================
[15:25:16] [PASSED] coalesce-same-reg
[15:25:16] [PASSED] coalesce-same-reg-literal-and-func
[15:25:16] [PASSED] no-match-no-add
[15:25:16] [PASSED] two-regs-two-entries
[15:25:16] [PASSED] clr-one-set-other
[15:25:16] [PASSED] set-field
[15:25:16] [PASSED] conflict-duplicate
[15:25:16] [PASSED] conflict-not-disjoint
[15:25:16] [PASSED] conflict-not-disjoint-literal-and-func
[15:25:16] [PASSED] conflict-reg-type
[15:25:16] [PASSED] bad-mcr-reg-forced-to-regular
[15:25:16] [PASSED] bad-regular-reg-forced-to-mcr
[15:25:16] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:25:16] ================== xe_rtp_process_tests ===================
[15:25:16] [PASSED] active1
[15:25:16] [PASSED] active2
[15:25:16] [PASSED] active-inactive
[15:25:16] [PASSED] inactive-active
[15:25:16] [PASSED] inactive-active-inactive
[15:25:16] [PASSED] inactive-inactive-inactive
[15:25:16] ============== [PASSED] xe_rtp_process_tests ===============
[15:25:16] ===================== [PASSED] xe_rtp ======================
[15:25:16] ==================== xe_wa (1 subtest) =====================
[15:25:16] ======================== xe_wa_gt =========================
[15:25:16] [PASSED] TIGERLAKE B0
[15:25:16] [PASSED] DG1 A0
[15:25:16] [PASSED] DG1 B0
[15:25:16] [PASSED] ALDERLAKE_S A0
[15:25:16] [PASSED] ALDERLAKE_S B0
[15:25:16] [PASSED] ALDERLAKE_S C0
[15:25:16] [PASSED] ALDERLAKE_S D0
[15:25:16] [PASSED] ALDERLAKE_P A0
[15:25:16] [PASSED] ALDERLAKE_P B0
[15:25:16] [PASSED] ALDERLAKE_P C0
[15:25:16] [PASSED] ALDERLAKE_S RPLS D0
[15:25:16] [PASSED] ALDERLAKE_P RPLU E0
[15:25:16] [PASSED] DG2 G10 C0
[15:25:16] [PASSED] DG2 G11 B1
[15:25:16] [PASSED] DG2 G12 A1
[15:25:16] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:25:16] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:25:16] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[15:25:16] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[15:25:16] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[15:25:16] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[15:25:16] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[15:25:16] ==================== [PASSED] xe_wa_gt =====================
[15:25:16] ====================== [PASSED] xe_wa ======================
[15:25:16] ============================================================
[15:25:16] Testing complete. Ran 821 tests: passed: 793, skipped: 28
[15:25:16] Elapsed time: 37.334s total, 1.837s configuring, 34.731s building, 0.714s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:25:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:25:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:25:43] Starting KUnit Kernel (1/1)...
[15:25:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:25:43] ============ drm_test_pick_cmdline (2 subtests) ============
[15:25:43] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:25:43] =============== drm_test_pick_cmdline_named ===============
[15:25:43] [PASSED] NTSC
[15:25:43] [PASSED] NTSC-J
[15:25:43] [PASSED] PAL
[15:25:43] [PASSED] PAL-M
[15:25:43] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:25:43] ============== [PASSED] drm_test_pick_cmdline ==============
[15:25:43] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:25:43] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:25:43] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:25:43] =========== drm_validate_clone_mode (2 subtests) ===========
[15:25:43] ============== drm_test_check_in_clone_mode ===============
[15:25:43] [PASSED] in_clone_mode
[15:25:43] [PASSED] not_in_clone_mode
[15:25:43] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:25:43] =============== drm_test_check_valid_clones ===============
[15:25:43] [PASSED] not_in_clone_mode
[15:25:43] [PASSED] valid_clone
[15:25:43] [PASSED] invalid_clone
[15:25:43] =========== [PASSED] drm_test_check_valid_clones ===========
[15:25:43] ============= [PASSED] drm_validate_clone_mode =============
[15:25:43] ============= drm_validate_modeset (1 subtest) =============
[15:25:43] [PASSED] drm_test_check_connector_changed_modeset
[15:25:43] ============== [PASSED] drm_validate_modeset ===============
[15:25:43] ====== drm_test_bridge_get_current_state (1 subtest) =======
[15:25:43] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:25:43] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:25:43] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[15:25:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:25:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:25:43] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[15:25:43] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:25:43] ============== drm_bridge_alloc (2 subtests) ===============
[15:25:43] [PASSED] drm_test_drm_bridge_alloc_basic
[15:25:43] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:25:43] ================ [PASSED] drm_bridge_alloc =================
[15:25:43] ============= drm_bridge_bus_fmt (5 subtests) ==============
[15:25:43] [PASSED] drm_test_bridge_rgb_yuv_rgb
[15:25:43] [PASSED] drm_test_bridge_must_convert_to_yuv444
[15:25:43] [PASSED] drm_test_bridge_hdmi_auto_rgb
[15:25:43] [PASSED] drm_test_bridge_auto_first
[15:25:43] [PASSED] drm_test_bridge_rgb_yuv_no_path
[15:25:43] =============== [PASSED] drm_bridge_bus_fmt ================
[15:25:43] ============= drm_cmdline_parser (40 subtests) =============
[15:25:43] [PASSED] drm_test_cmdline_force_d_only
[15:25:43] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:25:43] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:25:43] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:25:43] [PASSED] drm_test_cmdline_force_e_only
[15:25:43] [PASSED] drm_test_cmdline_res
[15:25:43] [PASSED] drm_test_cmdline_res_vesa
[15:25:43] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:25:43] [PASSED] drm_test_cmdline_res_rblank
[15:25:43] [PASSED] drm_test_cmdline_res_bpp
[15:25:43] [PASSED] drm_test_cmdline_res_refresh
[15:25:43] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:25:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:25:43] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:25:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:25:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:25:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:25:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:25:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:25:43] [PASSED] drm_test_cmdline_res_margins_force_on
[15:25:43] [PASSED] drm_test_cmdline_res_vesa_margins
[15:25:43] [PASSED] drm_test_cmdline_name
[15:25:43] [PASSED] drm_test_cmdline_name_bpp
[15:25:43] [PASSED] drm_test_cmdline_name_option
[15:25:43] [PASSED] drm_test_cmdline_name_bpp_option
[15:25:43] [PASSED] drm_test_cmdline_rotate_0
[15:25:43] [PASSED] drm_test_cmdline_rotate_90
[15:25:43] [PASSED] drm_test_cmdline_rotate_180
[15:25:43] [PASSED] drm_test_cmdline_rotate_270
[15:25:43] [PASSED] drm_test_cmdline_hmirror
[15:25:43] [PASSED] drm_test_cmdline_vmirror
[15:25:43] [PASSED] drm_test_cmdline_margin_options
[15:25:43] [PASSED] drm_test_cmdline_multiple_options
[15:25:43] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:25:43] [PASSED] drm_test_cmdline_extra_and_option
[15:25:43] [PASSED] drm_test_cmdline_freestanding_options
[15:25:43] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:25:43] [PASSED] drm_test_cmdline_panel_orientation
[15:25:43] ================ drm_test_cmdline_invalid =================
[15:25:43] [PASSED] margin_only
[15:25:43] [PASSED] interlace_only
[15:25:43] [PASSED] res_missing_x
[15:25:43] [PASSED] res_missing_y
[15:25:43] [PASSED] res_bad_y
[15:25:43] [PASSED] res_missing_y_bpp
[15:25:43] [PASSED] res_bad_bpp
[15:25:43] [PASSED] res_bad_refresh
[15:25:43] [PASSED] res_bpp_refresh_force_on_off
[15:25:43] [PASSED] res_invalid_mode
[15:25:43] [PASSED] res_bpp_wrong_place_mode
[15:25:43] [PASSED] name_bpp_refresh
[15:25:43] [PASSED] name_refresh
[15:25:43] [PASSED] name_refresh_wrong_mode
[15:25:43] [PASSED] name_refresh_invalid_mode
[15:25:43] [PASSED] rotate_multiple
[15:25:43] [PASSED] rotate_invalid_val
[15:25:43] [PASSED] rotate_truncated
[15:25:43] [PASSED] invalid_option
[15:25:43] [PASSED] invalid_tv_option
[15:25:43] [PASSED] truncated_tv_option
[15:25:43] ============ [PASSED] drm_test_cmdline_invalid =============
[15:25:43] =============== drm_test_cmdline_tv_options ===============
[15:25:43] [PASSED] NTSC
[15:25:43] [PASSED] NTSC_443
[15:25:43] [PASSED] NTSC_J
[15:25:43] [PASSED] PAL
[15:25:43] [PASSED] PAL_M
[15:25:43] [PASSED] PAL_N
[15:25:43] [PASSED] SECAM
[15:25:43] [PASSED] MONO_525
[15:25:43] [PASSED] MONO_625
[15:25:43] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:25:43] =============== [PASSED] drm_cmdline_parser ================
[15:25:43] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:25:43] [PASSED] drm_test_connector_hdmi_init_valid
[15:25:43] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:25:43] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:25:43] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:25:43] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:25:43] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:25:43] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:25:43] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:25:43] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:25:43] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:25:43] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:25:43] [PASSED] supported_formats=0x5 yuv420_allowed=1
[15:25:43] [PASSED] supported_formats=0x5 yuv420_allowed=0
[15:25:43] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:25:43] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:25:43] [PASSED] drm_test_connector_hdmi_init_null_product
[15:25:43] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:25:43] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:25:43] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:25:43] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:25:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:25:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:25:43] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:25:43] ========= drm_test_connector_hdmi_init_type_valid =========
[15:25:43] [PASSED] HDMI-A
[15:25:43] [PASSED] HDMI-B
[15:25:43] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:25:43] ======== drm_test_connector_hdmi_init_type_invalid ========
[15:25:43] [PASSED] Unknown
[15:25:43] [PASSED] VGA
[15:25:43] [PASSED] DVI-I
[15:25:43] [PASSED] DVI-D
[15:25:43] [PASSED] DVI-A
[15:25:43] [PASSED] Composite
[15:25:43] [PASSED] SVIDEO
[15:25:43] [PASSED] LVDS
[15:25:43] [PASSED] Component
[15:25:43] [PASSED] DIN
[15:25:43] [PASSED] DP
[15:25:43] [PASSED] TV
[15:25:43] [PASSED] eDP
[15:25:43] [PASSED] Virtual
[15:25:43] [PASSED] DSI
[15:25:43] [PASSED] DPI
[15:25:43] [PASSED] Writeback
[15:25:43] [PASSED] SPI
[15:25:43] [PASSED] USB
[15:25:43] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:25:43] ============ [PASSED] drmm_connector_hdmi_init =============
[15:25:43] ============= drmm_connector_init (3 subtests) =============
[15:25:43] [PASSED] drm_test_drmm_connector_init
[15:25:43] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:25:43] ========= drm_test_drmm_connector_init_type_valid =========
[15:25:43] [PASSED] Unknown
[15:25:43] [PASSED] VGA
[15:25:43] [PASSED] DVI-I
[15:25:43] [PASSED] DVI-D
[15:25:43] [PASSED] DVI-A
[15:25:43] [PASSED] Composite
[15:25:43] [PASSED] SVIDEO
[15:25:43] [PASSED] LVDS
[15:25:43] [PASSED] Component
[15:25:43] [PASSED] DIN
[15:25:43] [PASSED] DP
[15:25:43] [PASSED] HDMI-A
[15:25:43] [PASSED] HDMI-B
[15:25:43] [PASSED] TV
[15:25:43] [PASSED] eDP
[15:25:43] [PASSED] Virtual
[15:25:43] [PASSED] DSI
[15:25:43] [PASSED] DPI
[15:25:43] [PASSED] Writeback
[15:25:43] [PASSED] SPI
[15:25:43] [PASSED] USB
[15:25:43] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:25:43] =============== [PASSED] drmm_connector_init ===============
[15:25:43] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_init
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:25:43] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[15:25:43] [PASSED] Unknown
[15:25:43] [PASSED] VGA
[15:25:43] [PASSED] DVI-I
[15:25:43] [PASSED] DVI-D
[15:25:43] [PASSED] DVI-A
[15:25:43] [PASSED] Composite
[15:25:43] [PASSED] SVIDEO
[15:25:43] [PASSED] LVDS
[15:25:43] [PASSED] Component
[15:25:43] [PASSED] DIN
[15:25:43] [PASSED] DP
[15:25:43] [PASSED] HDMI-A
[15:25:43] [PASSED] HDMI-B
[15:25:43] [PASSED] TV
[15:25:43] [PASSED] eDP
[15:25:43] [PASSED] Virtual
[15:25:43] [PASSED] DSI
[15:25:43] [PASSED] DPI
[15:25:43] [PASSED] Writeback
[15:25:43] [PASSED] SPI
[15:25:43] [PASSED] USB
[15:25:43] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:25:43] ======== drm_test_drm_connector_dynamic_init_name =========
[15:25:43] [PASSED] Unknown
[15:25:43] [PASSED] VGA
[15:25:43] [PASSED] DVI-I
[15:25:43] [PASSED] DVI-D
[15:25:43] [PASSED] DVI-A
[15:25:43] [PASSED] Composite
[15:25:43] [PASSED] SVIDEO
[15:25:43] [PASSED] LVDS
[15:25:43] [PASSED] Component
[15:25:43] [PASSED] DIN
[15:25:43] [PASSED] DP
[15:25:43] [PASSED] HDMI-A
[15:25:43] [PASSED] HDMI-B
[15:25:43] [PASSED] TV
[15:25:43] [PASSED] eDP
[15:25:43] [PASSED] Virtual
[15:25:43] [PASSED] DSI
[15:25:43] [PASSED] DPI
[15:25:43] [PASSED] Writeback
[15:25:43] [PASSED] SPI
[15:25:43] [PASSED] USB
[15:25:43] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:25:43] =========== [PASSED] drm_connector_dynamic_init ============
[15:25:43] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:25:43] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:25:43] ======= drm_connector_dynamic_register (7 subtests) ========
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:25:43] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:25:43] ========= [PASSED] drm_connector_dynamic_register ==========
[15:25:43] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:25:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:25:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:25:43] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:25:43] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:25:43] ========== drm_test_get_tv_mode_from_name_valid ===========
[15:25:43] [PASSED] NTSC
[15:25:43] [PASSED] NTSC-443
[15:25:43] [PASSED] NTSC-J
[15:25:43] [PASSED] PAL
[15:25:43] [PASSED] PAL-M
[15:25:43] [PASSED] PAL-N
[15:25:43] [PASSED] SECAM
[15:25:43] [PASSED] Mono
[15:25:43] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:25:43] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:25:43] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:25:43] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:25:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:25:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:25:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:25:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:25:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:25:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:25:43] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[15:25:43] [PASSED] VIC 96
[15:25:43] [PASSED] VIC 97
[15:25:43] [PASSED] VIC 101
[15:25:43] [PASSED] VIC 102
[15:25:43] [PASSED] VIC 106
[15:25:43] [PASSED] VIC 107
[15:25:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:25:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:25:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:25:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:25:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:25:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:25:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:25:43] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:25:43] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[15:25:43] [PASSED] Automatic
[15:25:43] [PASSED] Full
[15:25:43] [PASSED] Limited 16:235
[15:25:43] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:25:43] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:25:43] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:25:43] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:25:43] === drm_test_drm_hdmi_connector_get_output_format_name ====
[15:25:43] [PASSED] RGB
[15:25:43] [PASSED] YUV 4:2:0
[15:25:43] [PASSED] YUV 4:2:2
[15:25:43] [PASSED] YUV 4:4:4
[15:25:43] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:25:43] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:25:43] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:25:43] ============= drm_damage_helper (21 subtests) ==============
[15:25:43] [PASSED] drm_test_damage_iter_no_damage
[15:25:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:25:43] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:25:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:25:43] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:25:43] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:25:43] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:25:43] [PASSED] drm_test_damage_iter_simple_damage
[15:25:43] [PASSED] drm_test_damage_iter_single_damage
[15:25:43] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:25:43] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:25:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:25:43] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:25:43] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:25:43] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:25:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:25:43] [PASSED] drm_test_damage_iter_damage
[15:25:43] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:25:43] [PASSED] drm_test_damage_iter_damage_one_outside
[15:25:43] [PASSED] drm_test_damage_iter_damage_src_moved
[15:25:43] [PASSED] drm_test_damage_iter_damage_not_visible
[15:25:43] ================ [PASSED] drm_damage_helper ================
[15:25:43] ============== drm_dp_mst_helper (3 subtests) ==============
[15:25:43] ============== drm_test_dp_mst_calc_pbn_mode ==============
[15:25:43] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:25:43] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:25:43] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:25:43] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:25:43] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:25:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:25:43] ============== drm_test_dp_mst_calc_pbn_div ===============
[15:25:43] [PASSED] Link rate 2000000 lane count 4
[15:25:43] [PASSED] Link rate 2000000 lane count 2
[15:25:43] [PASSED] Link rate 2000000 lane count 1
[15:25:43] [PASSED] Link rate 1350000 lane count 4
[15:25:43] [PASSED] Link rate 1350000 lane count 2
[15:25:43] [PASSED] Link rate 1350000 lane count 1
[15:25:43] [PASSED] Link rate 1000000 lane count 4
[15:25:43] [PASSED] Link rate 1000000 lane count 2
[15:25:43] [PASSED] Link rate 1000000 lane count 1
[15:25:43] [PASSED] Link rate 810000 lane count 4
[15:25:43] [PASSED] Link rate 810000 lane count 2
[15:25:43] [PASSED] Link rate 810000 lane count 1
[15:25:43] [PASSED] Link rate 540000 lane count 4
[15:25:43] [PASSED] Link rate 540000 lane count 2
[15:25:43] [PASSED] Link rate 540000 lane count 1
[15:25:43] [PASSED] Link rate 270000 lane count 4
[15:25:43] [PASSED] Link rate 270000 lane count 2
[15:25:43] [PASSED] Link rate 270000 lane count 1
[15:25:43] [PASSED] Link rate 162000 lane count 4
[15:25:43] [PASSED] Link rate 162000 lane count 2
[15:25:43] [PASSED] Link rate 162000 lane count 1
[15:25:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:25:43] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[15:25:43] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:25:43] [PASSED] DP_POWER_UP_PHY with port number
[15:25:43] [PASSED] DP_POWER_DOWN_PHY with port number
[15:25:43] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:25:43] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:25:43] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:25:43] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:25:43] [PASSED] DP_QUERY_PAYLOAD with port number
[15:25:43] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:25:43] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:25:43] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:25:43] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:25:43] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:25:43] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:25:43] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:25:43] [PASSED] DP_REMOTE_I2C_READ with port number
[15:25:43] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:25:43] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:25:43] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:25:43] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:25:43] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:25:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:25:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:25:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:25:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:25:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:25:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:25:43] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:25:43] ================ [PASSED] drm_dp_mst_helper ================
[15:25:43] ================== drm_exec (7 subtests) ===================
[15:25:43] [PASSED] sanitycheck
[15:25:43] [PASSED] test_lock
[15:25:43] [PASSED] test_lock_unlock
[15:25:43] [PASSED] test_duplicates
[15:25:43] [PASSED] test_prepare
[15:25:43] [PASSED] test_prepare_array
[15:25:43] [PASSED] test_multiple_loops
[15:25:43] ==================== [PASSED] drm_exec =====================
[15:25:43] =========== drm_format_helper_test (17 subtests) ===========
[15:25:43] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:25:43] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:25:43] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:25:43] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:25:43] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:25:43] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:25:43] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:25:43] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:25:43] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:25:43] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:25:43] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:25:43] ============== drm_test_fb_xrgb8888_to_mono ===============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:25:43] ==================== drm_test_fb_swab =====================
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ================ [PASSED] drm_test_fb_swab =================
[15:25:43] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:25:43] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[15:25:43] [PASSED] single_pixel_source_buffer
[15:25:43] [PASSED] single_pixel_clip_rectangle
[15:25:43] [PASSED] well_known_colors
[15:25:43] [PASSED] destination_pitch
[15:25:43] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:25:43] ================= drm_test_fb_clip_offset =================
[15:25:43] [PASSED] pass through
[15:25:43] [PASSED] horizontal offset
[15:25:43] [PASSED] vertical offset
[15:25:43] [PASSED] horizontal and vertical offset
[15:25:43] [PASSED] horizontal offset (custom pitch)
[15:25:43] [PASSED] vertical offset (custom pitch)
[15:25:43] [PASSED] horizontal and vertical offset (custom pitch)
[15:25:43] ============= [PASSED] drm_test_fb_clip_offset =============
[15:25:43] =================== drm_test_fb_memcpy ====================
[15:25:43] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:25:43] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:25:43] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:25:43] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:25:43] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:25:43] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:25:43] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:25:43] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:25:43] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:25:43] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:25:43] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:25:43] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:25:43] =============== [PASSED] drm_test_fb_memcpy ================
[15:25:43] ============= [PASSED] drm_format_helper_test ==============
[15:25:43] ================= drm_format (18 subtests) =================
[15:25:43] [PASSED] drm_test_format_block_width_invalid
[15:25:43] [PASSED] drm_test_format_block_width_one_plane
[15:25:43] [PASSED] drm_test_format_block_width_two_plane
[15:25:43] [PASSED] drm_test_format_block_width_three_plane
[15:25:43] [PASSED] drm_test_format_block_width_tiled
[15:25:43] [PASSED] drm_test_format_block_height_invalid
[15:25:43] [PASSED] drm_test_format_block_height_one_plane
[15:25:43] [PASSED] drm_test_format_block_height_two_plane
[15:25:43] [PASSED] drm_test_format_block_height_three_plane
[15:25:43] [PASSED] drm_test_format_block_height_tiled
[15:25:43] [PASSED] drm_test_format_min_pitch_invalid
[15:25:43] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:25:43] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:25:43] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:25:43] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:25:43] [PASSED] drm_test_format_min_pitch_two_plane
[15:25:43] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:25:43] [PASSED] drm_test_format_min_pitch_tiled
[15:25:43] =================== [PASSED] drm_format ====================
[15:25:43] ============== drm_framebuffer (10 subtests) ===============
[15:25:43] ========== drm_test_framebuffer_check_src_coords ==========
[15:25:43] [PASSED] Success: source fits into fb
[15:25:43] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:25:43] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:25:43] [PASSED] Fail: overflowing fb with source width
[15:25:43] [PASSED] Fail: overflowing fb with source height
[15:25:43] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:25:43] [PASSED] drm_test_framebuffer_cleanup
[15:25:43] =============== drm_test_framebuffer_create ===============
[15:25:43] [PASSED] ABGR8888 normal sizes
[15:25:43] [PASSED] ABGR8888 max sizes
[15:25:43] [PASSED] ABGR8888 pitch greater than min required
[15:25:43] [PASSED] ABGR8888 pitch less than min required
[15:25:43] [PASSED] ABGR8888 Invalid width
[15:25:43] [PASSED] ABGR8888 Invalid buffer handle
[15:25:43] [PASSED] No pixel format
[15:25:43] [PASSED] ABGR8888 Width 0
[15:25:43] [PASSED] ABGR8888 Height 0
[15:25:43] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:25:43] [PASSED] ABGR8888 Large buffer offset
[15:25:43] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:25:43] [PASSED] ABGR8888 Invalid flag
[15:25:43] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:25:43] [PASSED] ABGR8888 Valid buffer modifier
[15:25:43] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:25:43] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:25:43] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:25:43] [PASSED] NV12 Normal sizes
[15:25:43] [PASSED] NV12 Max sizes
[15:25:43] [PASSED] NV12 Invalid pitch
[15:25:43] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:25:43] [PASSED] NV12 different modifier per-plane
[15:25:43] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:25:43] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:25:43] [PASSED] NV12 Modifier for inexistent plane
[15:25:43] [PASSED] NV12 Handle for inexistent plane
[15:25:43] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:25:43] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:25:43] [PASSED] YVU420 Normal sizes
[15:25:43] [PASSED] YVU420 Max sizes
[15:25:43] [PASSED] YVU420 Invalid pitch
[15:25:43] [PASSED] YVU420 Different pitches
[15:25:43] [PASSED] YVU420 Different buffer offsets/pitches
[15:25:43] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:25:43] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:25:43] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:25:43] [PASSED] YVU420 Valid modifier
[15:25:43] [PASSED] YVU420 Different modifiers per plane
[15:25:43] [PASSED] YVU420 Modifier for inexistent plane
[15:25:43] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:25:43] [PASSED] X0L2 Normal sizes
[15:25:43] [PASSED] X0L2 Max sizes
[15:25:43] [PASSED] X0L2 Invalid pitch
[15:25:43] [PASSED] X0L2 Pitch greater than minimum required
[15:25:43] [PASSED] X0L2 Handle for inexistent plane
[15:25:43] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:25:43] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:25:43] [PASSED] X0L2 Valid modifier
[15:25:43] [PASSED] X0L2 Modifier for inexistent plane
[15:25:43] =========== [PASSED] drm_test_framebuffer_create ===========
[15:25:43] [PASSED] drm_test_framebuffer_free
[15:25:43] [PASSED] drm_test_framebuffer_init
[15:25:43] [PASSED] drm_test_framebuffer_init_bad_format
[15:25:43] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:25:43] [PASSED] drm_test_framebuffer_lookup
[15:25:43] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:25:43] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:25:43] ================= [PASSED] drm_framebuffer =================
[15:25:43] ================ drm_gem_shmem (8 subtests) ================
[15:25:43] [PASSED] drm_gem_shmem_test_obj_create
[15:25:43] [PASSED] drm_gem_shmem_test_obj_create_private
[15:25:43] [PASSED] drm_gem_shmem_test_pin_pages
[15:25:43] [PASSED] drm_gem_shmem_test_vmap
[15:25:43] [PASSED] drm_gem_shmem_test_get_sg_table
[15:25:43] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:25:43] [PASSED] drm_gem_shmem_test_madvise
[15:25:43] [PASSED] drm_gem_shmem_test_purge
[15:25:43] ================== [PASSED] drm_gem_shmem ==================
[15:25:43] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:25:43] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[15:25:43] [PASSED] Automatic
[15:25:43] [PASSED] Full
[15:25:43] [PASSED] Limited 16:235
[15:25:43] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:25:43] [PASSED] drm_test_check_disable_connector
[15:25:43] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:25:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:25:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:25:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:25:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:25:43] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:25:43] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:25:43] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:25:43] [PASSED] drm_test_check_output_bpc_dvi
[15:25:43] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:25:43] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:25:43] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:25:43] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:25:43] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:25:43] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:25:43] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:25:43] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:25:43] ============ drm_test_check_hdmi_color_format =============
[15:25:43] [PASSED] AUTO -> RGB
[15:25:43] [PASSED] YCBCR422 -> YUV422
[15:25:43] [PASSED] YCBCR420 -> YUV420
[15:25:43] [PASSED] YCBCR444 -> YUV444
[15:25:43] [PASSED] RGB -> RGB
[15:25:43] ======== [PASSED] drm_test_check_hdmi_color_format =========
[15:25:43] ======== drm_test_check_hdmi_color_format_420_only ========
[15:25:43] [PASSED] RGB should fail
[15:25:43] [PASSED] YUV444 should fail
[15:25:43] [PASSED] YUV422 should fail
[15:25:43] [PASSED] YUV420 should work
[15:25:43] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[15:25:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:25:43] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:25:43] [PASSED] drm_test_check_broadcast_rgb_value
[15:25:43] [PASSED] drm_test_check_bpc_8_value
[15:25:43] [PASSED] drm_test_check_bpc_10_value
[15:25:43] [PASSED] drm_test_check_bpc_12_value
[15:25:43] [PASSED] drm_test_check_format_value
[15:25:43] [PASSED] drm_test_check_tmds_char_value
[15:25:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:25:43] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[15:25:43] [PASSED] drm_test_check_mode_valid
[15:25:43] [PASSED] drm_test_check_mode_valid_reject
[15:25:43] [PASSED] drm_test_check_mode_valid_reject_rate
[15:25:43] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:25:43] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[15:25:43] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[15:25:43] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[15:25:43] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:25:43] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[15:25:43] [PASSED] drm_test_check_infoframes
[15:25:43] [PASSED] drm_test_check_reject_avi_infoframe
[15:25:43] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[15:25:43] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[15:25:43] [PASSED] drm_test_check_reject_audio_infoframe
[15:25:43] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[15:25:43] ================= drm_managed (2 subtests) =================
[15:25:43] [PASSED] drm_test_managed_release_action
[15:25:43] [PASSED] drm_test_managed_run_action
[15:25:43] =================== [PASSED] drm_managed ===================
[15:25:43] =================== drm_mm (6 subtests) ====================
[15:25:43] [PASSED] drm_test_mm_init
[15:25:43] [PASSED] drm_test_mm_debug
[15:25:43] [PASSED] drm_test_mm_align32
[15:25:43] [PASSED] drm_test_mm_align64
[15:25:43] [PASSED] drm_test_mm_lowest
[15:25:43] [PASSED] drm_test_mm_highest
[15:25:43] ===================== [PASSED] drm_mm ======================
[15:25:43] ============= drm_modes_analog_tv (5 subtests) =============
[15:25:43] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:25:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:25:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:25:43] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:25:43] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:25:43] =============== [PASSED] drm_modes_analog_tv ===============
[15:25:43] ============== drm_panic_helper (3 subtests) ===============
[15:25:43] ============= drm_test_panic_screen_user_map ==============
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:25:43] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:25:43] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:25:43] ========= [PASSED] drm_test_panic_screen_user_map ==========
[15:25:43] ============= drm_test_panic_screen_user_page =============
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:25:43] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:25:43] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:25:43] ========= [PASSED] drm_test_panic_screen_user_page =========
[15:25:43] ========== drm_test_panic_screen_user_set_pixel ===========
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:25:43] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:25:44] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:25:44] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:25:44] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:25:44] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:25:44] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:25:44] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[15:25:44] ================ [PASSED] drm_panic_helper =================
[15:25:44] ============== drm_plane_helper (2 subtests) ===============
[15:25:44] =============== drm_test_check_plane_state ================
[15:25:44] [PASSED] clipping_simple
[15:25:44] [PASSED] clipping_rotate_reflect
[15:25:44] [PASSED] positioning_simple
[15:25:44] [PASSED] upscaling
[15:25:44] [PASSED] downscaling
[15:25:44] [PASSED] rounding1
[15:25:44] [PASSED] rounding2
[15:25:44] [PASSED] rounding3
[15:25:44] [PASSED] rounding4
[15:25:44] =========== [PASSED] drm_test_check_plane_state ============
[15:25:44] =========== drm_test_check_invalid_plane_state ============
[15:25:44] [PASSED] positioning_invalid
[15:25:44] [PASSED] upscaling_invalid
[15:25:44] [PASSED] downscaling_invalid
[15:25:44] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:25:44] ================ [PASSED] drm_plane_helper =================
[15:25:44] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:25:44] ====== drm_test_connector_helper_tv_get_modes_check =======
[15:25:44] [PASSED] None
[15:25:44] [PASSED] PAL
[15:25:44] [PASSED] NTSC
[15:25:44] [PASSED] Both, NTSC Default
[15:25:44] [PASSED] Both, PAL Default
[15:25:44] [PASSED] Both, NTSC Default, with PAL on command-line
[15:25:44] [PASSED] Both, PAL Default, with NTSC on command-line
[15:25:44] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:25:44] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:25:44] ================== drm_rect (9 subtests) ===================
[15:25:44] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:25:44] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:25:44] [PASSED] drm_test_rect_clip_scaled_clipped
[15:25:44] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:25:44] ================= drm_test_rect_intersect =================
[15:25:44] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:25:44] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:25:44] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:25:44] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:25:44] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:25:44] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:25:44] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:25:44] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:25:44] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:25:44] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:25:44] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:25:44] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:25:44] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:25:44] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:25:44] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:25:44] ============= [PASSED] drm_test_rect_intersect =============
[15:25:44] ================ drm_test_rect_calc_hscale ================
[15:25:44] [PASSED] normal use
[15:25:44] [PASSED] out of max range
[15:25:44] [PASSED] out of min range
[15:25:44] [PASSED] zero dst
[15:25:44] [PASSED] negative src
[15:25:44] [PASSED] negative dst
[15:25:44] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:25:44] ================ drm_test_rect_calc_vscale ================
[15:25:44] [PASSED] normal use
[15:25:44] [PASSED] out of max range
[15:25:44] [PASSED] out of min range
[15:25:44] [PASSED] zero dst
[15:25:44] [PASSED] negative src
[15:25:44] [PASSED] negative dst
[15:25:44] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:25:44] ================== drm_test_rect_rotate ===================
[15:25:44] [PASSED] reflect-x
[15:25:44] [PASSED] reflect-y
[15:25:44] [PASSED] rotate-0
[15:25:44] [PASSED] rotate-90
[15:25:44] [PASSED] rotate-180
[15:25:44] [PASSED] rotate-270
[15:25:44] ============== [PASSED] drm_test_rect_rotate ===============
[15:25:44] ================ drm_test_rect_rotate_inv =================
[15:25:44] [PASSED] reflect-x
[15:25:44] [PASSED] reflect-y
[15:25:44] [PASSED] rotate-0
[15:25:44] [PASSED] rotate-90
[15:25:44] [PASSED] rotate-180
[15:25:44] [PASSED] rotate-270
[15:25:44] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:25:44] ==================== [PASSED] drm_rect =====================
[15:25:44] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:25:44] ============ drm_test_sysfb_build_fourcc_list =============
[15:25:44] [PASSED] no native formats
[15:25:44] [PASSED] XRGB8888 as native format
[15:25:44] [PASSED] remove duplicates
[15:25:44] [PASSED] convert alpha formats
[15:25:44] [PASSED] random formats
[15:25:44] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:25:44] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:25:44] ================== drm_fixp (2 subtests) ===================
[15:25:44] [PASSED] drm_test_int2fixp
[15:25:44] [PASSED] drm_test_sm2fixp
[15:25:44] ==================== [PASSED] drm_fixp =====================
[15:25:44] ============================================================
[15:25:44] Testing complete. Ran 667 tests: passed: 667
[15:25:44] Elapsed time: 27.672s total, 1.832s configuring, 25.419s building, 0.416s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:25:44] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:25:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:25:56] Starting KUnit Kernel (1/1)...
[15:25:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:25:56] ================= ttm_device (5 subtests) ==================
[15:25:56] [PASSED] ttm_device_init_basic
[15:25:56] [PASSED] ttm_device_init_multiple
[15:25:56] [PASSED] ttm_device_fini_basic
[15:25:56] [PASSED] ttm_device_init_no_vma_man
[15:25:56] ================== ttm_device_init_pools ==================
[15:25:56] [PASSED] No DMA allocations, no DMA32 required
[15:25:56] [PASSED] DMA allocations, DMA32 required
[15:25:56] [PASSED] No DMA allocations, DMA32 required
[15:25:56] [PASSED] DMA allocations, no DMA32 required
[15:25:56] ============== [PASSED] ttm_device_init_pools ==============
[15:25:56] =================== [PASSED] ttm_device ====================
[15:25:56] ================== ttm_pool (8 subtests) ===================
[15:25:56] ================== ttm_pool_alloc_basic ===================
[15:25:56] [PASSED] One page
[15:25:56] [PASSED] More than one page
[15:25:56] [PASSED] Above the allocation limit
[15:25:56] [PASSED] One page, with coherent DMA mappings enabled
[15:25:56] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:25:56] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:25:56] ============== ttm_pool_alloc_basic_dma_addr ==============
[15:25:56] [PASSED] One page
[15:25:56] [PASSED] More than one page
[15:25:56] [PASSED] Above the allocation limit
[15:25:56] [PASSED] One page, with coherent DMA mappings enabled
[15:25:56] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:25:56] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:25:56] [PASSED] ttm_pool_alloc_order_caching_match
[15:25:56] [PASSED] ttm_pool_alloc_caching_mismatch
[15:25:56] [PASSED] ttm_pool_alloc_order_mismatch
[15:25:56] [PASSED] ttm_pool_free_dma_alloc
[15:25:56] [PASSED] ttm_pool_free_no_dma_alloc
[15:25:56] [PASSED] ttm_pool_fini_basic
[15:25:56] ==================== [PASSED] ttm_pool =====================
[15:25:56] ================ ttm_resource (8 subtests) =================
[15:25:56] ================= ttm_resource_init_basic =================
[15:25:56] [PASSED] Init resource in TTM_PL_SYSTEM
[15:25:56] [PASSED] Init resource in TTM_PL_VRAM
[15:25:56] [PASSED] Init resource in a private placement
[15:25:56] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:25:56] ============= [PASSED] ttm_resource_init_basic =============
[15:25:56] [PASSED] ttm_resource_init_pinned
[15:25:56] [PASSED] ttm_resource_fini_basic
[15:25:56] [PASSED] ttm_resource_manager_init_basic
[15:25:56] [PASSED] ttm_resource_manager_usage_basic
[15:25:56] [PASSED] ttm_resource_manager_set_used_basic
[15:25:56] [PASSED] ttm_sys_man_alloc_basic
[15:25:56] [PASSED] ttm_sys_man_free_basic
[15:25:56] ================== [PASSED] ttm_resource ===================
[15:25:56] =================== ttm_tt (15 subtests) ===================
[15:25:56] ==================== ttm_tt_init_basic ====================
[15:25:56] [PASSED] Page-aligned size
[15:25:56] [PASSED] Extra pages requested
[15:25:56] ================ [PASSED] ttm_tt_init_basic ================
[15:25:56] [PASSED] ttm_tt_init_misaligned
[15:25:56] [PASSED] ttm_tt_fini_basic
[15:25:56] [PASSED] ttm_tt_fini_sg
[15:25:56] [PASSED] ttm_tt_fini_shmem
[15:25:56] [PASSED] ttm_tt_create_basic
[15:25:56] [PASSED] ttm_tt_create_invalid_bo_type
[15:25:56] [PASSED] ttm_tt_create_ttm_exists
[15:25:56] [PASSED] ttm_tt_create_failed
[15:25:56] [PASSED] ttm_tt_destroy_basic
[15:25:56] [PASSED] ttm_tt_populate_null_ttm
[15:25:56] [PASSED] ttm_tt_populate_populated_ttm
[15:25:56] [PASSED] ttm_tt_unpopulate_basic
[15:25:56] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:25:56] [PASSED] ttm_tt_swapin_basic
[15:25:56] ===================== [PASSED] ttm_tt ======================
[15:25:56] =================== ttm_bo (14 subtests) ===================
[15:25:56] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[15:25:56] [PASSED] Cannot be interrupted and sleeps
[15:25:56] [PASSED] Cannot be interrupted, locks straight away
[15:25:56] [PASSED] Can be interrupted, sleeps
[15:25:56] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:25:56] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:25:56] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:25:56] [PASSED] ttm_bo_reserve_double_resv
[15:25:56] [PASSED] ttm_bo_reserve_interrupted
[15:25:56] [PASSED] ttm_bo_reserve_deadlock
[15:25:56] [PASSED] ttm_bo_unreserve_basic
[15:25:56] [PASSED] ttm_bo_unreserve_pinned
[15:25:56] [PASSED] ttm_bo_unreserve_bulk
[15:25:56] [PASSED] ttm_bo_fini_basic
[15:25:56] [PASSED] ttm_bo_fini_shared_resv
[15:25:56] [PASSED] ttm_bo_pin_basic
[15:25:56] [PASSED] ttm_bo_pin_unpin_resource
[15:25:56] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:25:56] ===================== [PASSED] ttm_bo ======================
[15:25:56] ============== ttm_bo_validate (22 subtests) ===============
[15:25:56] ============== ttm_bo_init_reserved_sys_man ===============
[15:25:56] [PASSED] Buffer object for userspace
[15:25:56] [PASSED] Kernel buffer object
[15:25:56] [PASSED] Shared buffer object
[15:25:56] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:25:56] ============== ttm_bo_init_reserved_mock_man ==============
[15:25:56] [PASSED] Buffer object for userspace
[15:25:56] [PASSED] Kernel buffer object
[15:25:56] [PASSED] Shared buffer object
[15:25:56] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:25:56] [PASSED] ttm_bo_init_reserved_resv
[15:25:56] ================== ttm_bo_validate_basic ==================
[15:25:56] [PASSED] Buffer object for userspace
[15:25:56] [PASSED] Kernel buffer object
[15:25:56] [PASSED] Shared buffer object
[15:25:56] ============== [PASSED] ttm_bo_validate_basic ==============
[15:25:56] [PASSED] ttm_bo_validate_invalid_placement
[15:25:56] ============= ttm_bo_validate_same_placement ==============
[15:25:56] [PASSED] System manager
[15:25:56] [PASSED] VRAM manager
[15:25:56] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:25:56] [PASSED] ttm_bo_validate_failed_alloc
[15:25:56] [PASSED] ttm_bo_validate_pinned
[15:25:56] [PASSED] ttm_bo_validate_busy_placement
[15:25:56] ================ ttm_bo_validate_multihop =================
[15:25:56] [PASSED] Buffer object for userspace
[15:25:56] [PASSED] Kernel buffer object
[15:25:56] [PASSED] Shared buffer object
[15:25:56] ============ [PASSED] ttm_bo_validate_multihop =============
[15:25:56] ========== ttm_bo_validate_no_placement_signaled ==========
[15:25:56] [PASSED] Buffer object in system domain, no page vector
[15:25:56] [PASSED] Buffer object in system domain with an existing page vector
[15:25:56] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:25:56] ======== ttm_bo_validate_no_placement_not_signaled ========
[15:25:56] [PASSED] Buffer object for userspace
[15:25:56] [PASSED] Kernel buffer object
[15:25:56] [PASSED] Shared buffer object
[15:25:56] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:25:56] [PASSED] ttm_bo_validate_move_fence_signaled
[15:25:56] ========= ttm_bo_validate_move_fence_not_signaled =========
[15:25:56] [PASSED] Waits for GPU
[15:25:56] [PASSED] Tries to lock straight away
[15:25:56] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:25:56] [PASSED] ttm_bo_validate_swapout
[15:25:56] [PASSED] ttm_bo_validate_happy_evict
[15:25:56] [PASSED] ttm_bo_validate_all_pinned_evict
[15:25:56] [PASSED] ttm_bo_validate_allowed_only_evict
[15:25:56] [PASSED] ttm_bo_validate_deleted_evict
[15:25:56] [PASSED] ttm_bo_validate_busy_domain_evict
[15:25:56] [PASSED] ttm_bo_validate_evict_gutting
[15:25:56] [PASSED] ttm_bo_validate_recrusive_evict
[15:25:56] ================= [PASSED] ttm_bo_validate =================
[15:25:56] ============================================================
[15:25:56] Testing complete. Ran 102 tests: passed: 102
[15:25:56] Elapsed time: 12.182s total, 1.797s configuring, 10.170s building, 0.187s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[15:25:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:25:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:26:07] Starting KUnit Kernel (1/1)...
[15:26:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:26:07] =============== dma-buf-fence (12 subtests) ================
[15:26:07] [PASSED] test_sanitycheck
[15:26:07] [PASSED] test_signaling
[15:26:07] [PASSED] test_add_callback
[15:26:07] [PASSED] test_late_add_callback
[15:26:07] [PASSED] test_rm_callback
[15:26:07] [PASSED] test_late_rm_callback
[15:26:07] [PASSED] test_status
[15:26:07] [PASSED] test_error
[15:26:07] [PASSED] test_wait
[15:26:07] [PASSED] test_wait_timeout
[15:26:07] [PASSED] test_stub
[15:26:07] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[15:26:07] ================== [PASSED] dma-buf-fence ==================
[15:26:07] ============ dma-buf-fence-chain (11 subtests) =============
[15:26:07] [PASSED] test_sanitycheck
[15:26:07] [PASSED] test_find_seqno
[15:26:07] [PASSED] test_find_signaled
[15:26:07] [PASSED] test_find_out_of_order
[15:26:12] [PASSED] test_find_gap
[15:26:12] [PASSED] test_find_race
[15:26:12] [PASSED] test_signal_forward
[15:26:12] [PASSED] test_signal_backward
[15:26:12] [PASSED] test_wait_forward
[15:26:12] [PASSED] test_wait_backward
[15:26:12] [PASSED] test_wait_random
[15:26:12] =============== [PASSED] dma-buf-fence-chain ===============
[15:26:12] ============ dma-buf-fence-unwrap (11 subtests) ============
[15:26:12] [PASSED] test_sanitycheck
[15:26:12] [PASSED] test_unwrap_array
[15:26:12] [PASSED] test_unwrap_chain
[15:26:12] [PASSED] test_unwrap_chain_array
[15:26:12] [PASSED] test_unwrap_merge
[15:26:12] [PASSED] test_unwrap_merge_duplicate
[15:26:12] [PASSED] test_unwrap_merge_seqno
[15:26:12] [PASSED] test_unwrap_merge_order
[15:26:12] [PASSED] test_unwrap_merge_complex
[15:26:12] [PASSED] test_unwrap_merge_complex_seqno
[15:26:12] [PASSED] test_dedup_empty
[15:26:12] ============== [PASSED] dma-buf-fence-unwrap ===============
[15:26:12] ================ dma-buf-resv (5 subtests) =================
[15:26:12] [PASSED] test_sanitycheck
[15:26:12] ===================== test_signaling ======================
[15:26:12] [PASSED] kernel
[15:26:12] [PASSED] write
[15:26:12] [PASSED] read
[15:26:12] [PASSED] bookkeep
[15:26:12] ================= [PASSED] test_signaling ==================
[15:26:12] ====================== test_for_each ======================
[15:26:12] [PASSED] kernel
[15:26:12] [PASSED] write
[15:26:12] [PASSED] read
[15:26:12] [PASSED] bookkeep
[15:26:12] ================== [PASSED] test_for_each ==================
[15:26:12] ================= test_for_each_unlocked ==================
[15:26:12] [PASSED] kernel
[15:26:12] [PASSED] write
[15:26:12] [PASSED] read
[15:26:12] [PASSED] bookkeep
[15:26:12] ============= [PASSED] test_for_each_unlocked ==============
[15:26:12] ===================== test_get_fences =====================
[15:26:12] [PASSED] kernel
[15:26:12] [PASSED] write
[15:26:12] [PASSED] read
[15:26:12] [PASSED] bookkeep
[15:26:12] ================= [PASSED] test_get_fences =================
[15:26:12] ================== [PASSED] dma-buf-resv ===================
[15:26:12] ============================================================
[15:26:12] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[15:26:12] Elapsed time: 16.065s total, 1.882s configuring, 8.811s building, 5.335s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Xe.CI.BAT: failure for Move the PLL power save W/A to the display W/A framework (rev2)
2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
` (6 preceding siblings ...)
2026-10-14 15:26 ` ✓ CI.KUnit: success for Move the PLL power save W/A to the display W/A framework (rev4) Patchwork
@ 2026-10-14 17:52 ` Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-10-14 17:52 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 5873 bytes --]
== Series Details ==
Series: Move the PLL power save W/A to the display W/A framework (rev2)
URL : https://patchwork.freedesktop.org/series/175834/
State : failure
== Summary ==
CI Bug Log - changes from xe-5946-c06d7623a198463e9aa2d09a3c33d96fe66ea662_BAT -> xe-pw-175834v2_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-175834v2_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-175834v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (14 -> 15)
------------------------------
Additional (1): bat-ptl-vm
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-175834v2_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@xe_module_load@load:
- bat-nvls-2: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5946-c06d7623a198463e9aa2d09a3c33d96fe66ea662/bat-nvls-2/igt@xe_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-nvls-2/igt@xe_module_load@load.html
- bat-nvls-1: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5946-c06d7623a198463e9aa2d09a3c33d96fe66ea662/bat-nvls-1/igt@xe_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-nvls-1/igt@xe_module_load@load.html
Known issues
------------
Here are the changes found in xe-pw-175834v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- bat-nvls-1: [PASS][5] -> [DMESG-WARN][6] ([Intel XE#8762] / [Intel XE#9069])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5946-c06d7623a198463e9aa2d09a3c33d96fe66ea662/bat-nvls-1/igt@core_hotunplug@unbind-rebind.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-nvls-1/igt@core_hotunplug@unbind-rebind.html
- bat-nvls-2: [PASS][7] -> [DMESG-WARN][8] ([Intel XE#8762] / [Intel XE#9069])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5946-c06d7623a198463e9aa2d09a3c33d96fe66ea662/bat-nvls-2/igt@core_hotunplug@unbind-rebind.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-nvls-2/igt@core_hotunplug@unbind-rebind.html
* igt@xe_evict@evict-beng-small-cm:
- bat-ptl-vm: NOTRUN -> [SKIP][9] ([Intel XE#5764]) +11 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-ptl-vm/igt@xe_evict@evict-beng-small-cm.html
* igt@xe_exec_balancer@no-exec-cm-virtual-basic:
- bat-ptl-vm: NOTRUN -> [SKIP][10] ([Intel XE#7482]) +17 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-ptl-vm/igt@xe_exec_balancer@no-exec-cm-virtual-basic.html
* igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd:
- bat-ptl-vm: NOTRUN -> [SKIP][11] ([Intel XE#8364]) +13 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-ptl-vm/igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd.html
* igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
- bat-ptl-vm: NOTRUN -> [SKIP][12] ([Intel XE#5775]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-ptl-vm/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html
* igt@xe_mmap@vram:
- bat-ptl-vm: NOTRUN -> [SKIP][13] ([Intel XE#5776])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-ptl-vm/igt@xe_mmap@vram.html
* igt@xe_pat@pat-index-xehpc:
- bat-ptl-vm: NOTRUN -> [SKIP][14] ([Intel XE#5777] / [Intel XE#7590])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-ptl-vm/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pat@pat-index-xelp:
- bat-ptl-vm: NOTRUN -> [SKIP][15] ([Intel XE#5771] / [Intel XE#7590])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-ptl-vm/igt@xe_pat@pat-index-xelp.html
* igt@xe_pat@pat-index-xelpg:
- bat-ptl-vm: NOTRUN -> [SKIP][16] ([Intel XE#5780] / [Intel XE#7590])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/bat-ptl-vm/igt@xe_pat@pat-index-xelpg.html
[Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
[Intel XE#5771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5771
[Intel XE#5775]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5775
[Intel XE#5776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5776
[Intel XE#5777]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5777
[Intel XE#5780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5780
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8762]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8762
[Intel XE#9069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9069
Build changes
-------------
* IGT: IGT_9145 -> IGT_9146
* Linux: xe-5946-c06d7623a198463e9aa2d09a3c33d96fe66ea662 -> xe-pw-175834v2
IGT_9145: 05c13a14f7f8bcda7bff83b8aa033c3c47a4b1fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_9146: 9e6040664f13f0767bb4d1028b422b7ee00425dc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5946-c06d7623a198463e9aa2d09a3c33d96fe66ea662: c06d7623a198463e9aa2d09a3c33d96fe66ea662
xe-pw-175834v2: 175834v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-175834v2/index.html
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2026-10-14 10:53 [PATCH v2 0/4] Move the PLL power save W/A to the display W/A framework Mika Kahola
2026-10-14 10:53 ` [PATCH v2 1/4] drm/i915/dpll: move " Mika Kahola
2026-10-14 13:45 ` Mika Kahola
2026-10-14 10:53 ` [PATCH v2 2/4] drm/i915/lt_phy: split out intel_lt_phy_pll_calc_state_from_table() Mika Kahola
2026-10-14 10:53 ` [PATCH v2 3/4] drm/i915/lt_phy: drop the unused pll argument from intel_lt_phy_pll_enable() Mika Kahola
2026-10-14 10:58 ` sashiko-bot
2026-10-14 10:53 ` [PATCH v2 4/4] drm/i915/lt_phy: apply the PLL power save W/A on LT PHY platforms Mika Kahola
2026-10-14 11:10 ` sashiko-bot
2026-10-14 13:46 ` Mika Kahola
2026-10-14 11:26 ` ✓ CI.KUnit: success for Move the PLL power save W/A to the display W/A framework (rev2) Patchwork
2026-10-14 11:48 ` ✓ i915.CI.BAT: " Patchwork
2026-10-14 15:26 ` ✓ CI.KUnit: success for Move the PLL power save W/A to the display W/A framework (rev4) Patchwork
2026-10-14 17:52 ` ✗ Xe.CI.BAT: failure for Move the PLL power save W/A to the display W/A framework (rev2) Patchwork
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