* [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC
@ 2026-10-15 2:37 Shawn Guo
2026-10-15 2:37 ` [PATCH v2 1/7] arm64: dts: qcom: Introduce lemans-embedded.dtsi as a placeholder Shawn Guo
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Shawn Guo @ 2026-10-15 2:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Deepti Jaggi, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
While the patchset [1] supports SA8255P as a standalone SoC, this series
offers an alternative by introducing SA8255P as a Lemans family SoC.
Lemans family has two variants: Embedded variant (IQ9/SA8775P) where
platform resources like clocks, regulators, interconnects etc. are
managed by HLOS, and GearVM variant (SA8255P) where they are managed by
a VM acting as SCMI server. All Lemans family SoCs actually share the
same hardware configurations like memory maps, interrupts, DMAs, etc.
This patchset moves those platform resources out of lemans.dtsi and gets
them accommodated in lemans-embedded.dtsi, so that lemans.dtsi can cover
GearVM variant as well, i.e. lemans-gearvm.dtsi includes lemans.dtsi and
overrides/adds properties as needed.
Changes for v2:
- Rebase on next-20261009
- Drop patch "arm64: dts: qcom: lemans: Move PCIe devices into soc node"
which has been applied
- Drop patch "arm64: dts: qcom: Rename lemans-auto.dtsi to
lemans-sa8775p.dtsi", as lemans-auto.dtsi has been removed along with
sa8775p-ride boards
- Follow Nord naming to rename lemans-iq9.dtsi to lemans-embedded.dtsi,
lemans-sa8255p.dtsi to lemans-gearvm.dtsi and sa8255p-ride.dts to
lemans-sa8255p-ride.dts
- Move linux,pci-domain of PCIe RC/EP into lemans-embedded.dtsi, so that
lemans-gearvm.dtsi no longer needs /delete-property/
- New patch "arm64: dts: qcom: lemans: Add label for firmware and
reserved-memory", so that lemans-gearvm.dtsi can override them by
label instead of duplicating the node hierarchy
- Add SCMI power/perf domains for QUP I2C and SPI controllers in
lemans-gearvm.dtsi
- Link to v1: https://lore.kernel.org/all/20260409091100.474358-1-shengchao.guo@oss.qualcomm.com/
[1] https://lore.kernel.org/all/20260304-b4-scmi-upstream-v5-0-f8fc763d8da0@oss.qualcomm.com/
Nikunj Kela (2):
dt-bindings: arm: qcom: add SA8255p Ride board
arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support
Shawn Guo (5):
arm64: dts: qcom: Introduce lemans-embedded.dtsi as a placeholder
arm64: dts: qcom: lemans: Move pinctrl states into
lemans-embedded.dtsi
arm64: dts: qcom: lemans: Move platform resources into
lemans-embedded.dtsi
arm64: dts: qcom: lemans: Add label for firmware and reserved-memory
arm64: dts: qcom: Add device tree for Lemans GearVM variant
.../devicetree/bindings/arm/qcom.yaml | 5 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/lemans-embedded.dtsi | 3685 +++++++++++++++++
arch/arm64/boot/dts/qcom/lemans-evk.dts | 2 +-
arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi | 3232 +++++++++++++++
.../boot/dts/qcom/lemans-sa8255p-ride.dts | 222 +
arch/arm64/boot/dts/qcom/lemans.dtsi | 3369 +--------------
arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs9100-ride.dts | 2 +-
9 files changed, 7154 insertions(+), 3366 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/7] arm64: dts: qcom: Introduce lemans-embedded.dtsi as a placeholder
2026-10-15 2:37 [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC Shawn Guo
@ 2026-10-15 2:37 ` Shawn Guo
2026-10-15 2:37 ` [PATCH v2 2/7] arm64: dts: qcom: lemans: Move pinctrl states into lemans-embedded.dtsi Shawn Guo
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Shawn Guo @ 2026-10-15 2:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Deepti Jaggi, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
Lemans is a Qualcomm SoC family that includes not only the Embedded
variant (IQ9/SA8775P) where platform resources are managed by HLOS, but
also the GearVM variant (SA8255P) where resources are managed by a VM
as SCMI server. The current lemans.dtsi covers the former variant only.
Introduce lemans-embedded.dtsi as a placeholder for now, while later
changes will move Embedded variant settings in there and introduce
GearVM variant support.
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-embedded.dtsi | 6 ++++++
arch/arm64/boot/dts/qcom/lemans-evk.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs9100-ride.dts | 2 +-
4 files changed, 9 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
diff --git a/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi b/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
new file mode 100644
index 000000000000..80d8c75e4895
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include "lemans.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index 23cf20f9a178..603a3fa18994 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -10,7 +10,7 @@
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "lemans.dtsi"
+#include "lemans-embedded.dtsi"
#include "lemans-pmics.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
index 7fc2de0d3d5e..a2c70018e571 100644
--- a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
@@ -4,7 +4,7 @@
*/
/dts-v1/;
-#include "lemans.dtsi"
+#include "lemans-embedded.dtsi"
#include "lemans-pmics.dtsi"
#include "lemans-ride-common.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts
index b0c5fdde56ae..7597b4f27e78 100644
--- a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts
@@ -4,7 +4,7 @@
*/
/dts-v1/;
-#include "lemans.dtsi"
+#include "lemans-embedded.dtsi"
#include "lemans-pmics.dtsi"
#include "lemans-ride-common.dtsi"
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/7] arm64: dts: qcom: lemans: Move pinctrl states into lemans-embedded.dtsi
2026-10-15 2:37 [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC Shawn Guo
2026-10-15 2:37 ` [PATCH v2 1/7] arm64: dts: qcom: Introduce lemans-embedded.dtsi as a placeholder Shawn Guo
@ 2026-10-15 2:37 ` Shawn Guo
2026-10-15 2:37 ` [PATCH v2 3/7] arm64: dts: qcom: lemans: Move platform resources " Shawn Guo
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Shawn Guo @ 2026-10-15 2:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Deepti Jaggi, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
The lemans.dtsi will become a base devicetree shared by all Lemans
series SoCs. Move those pinctrl states into lemans-embedded.dtsi as
they are used by Embedded variant (IQ9/SA8775P) only.
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-embedded.dtsi | 808 ++++++++++++++++++
arch/arm64/boot/dts/qcom/lemans.dtsi | 806 -----------------
2 files changed, 808 insertions(+), 806 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi b/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
index 80d8c75e4895..107db7a74756 100644
--- a/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
@@ -4,3 +4,811 @@
*/
#include "lemans.dtsi"
+
+&tlmm {
+ dp0_hot_plug_det: dp0-hot-plug-det-state {
+ pins = "gpio101";
+ function = "edp0_hot";
+ bias-disable;
+ };
+
+ dp1_hot_plug_det: dp1-hot-plug-det-state {
+ pins = "gpio102";
+ function = "edp1_hot";
+ bias-disable;
+ };
+
+ hs0_mi2s_active: hs0-mi2s-active-state {
+ pins = "gpio114", "gpio115", "gpio116", "gpio117";
+ function = "hs0_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ hs2_mi2s_active: hs2-mi2s-active-state {
+ pins = "gpio122", "gpio123", "gpio124", "gpio125";
+ function = "hs2_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cci0_0_default: cci0-0-default-state {
+ pins = "gpio60", "gpio61";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ pins = "gpio60", "gpio61";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ pins = "gpio52", "gpio53";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ pins = "gpio52", "gpio53";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ pins = "gpio62", "gpio63";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ pins = "gpio62", "gpio63";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ pins = "gpio54", "gpio55";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ pins = "gpio54", "gpio55";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci2_0_default: cci2-0-default-state {
+ pins = "gpio64", "gpio65";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ cci2_0_sleep: cci2-0-sleep-state {
+ pins = "gpio64", "gpio65";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci2_1_default: cci2-1-default-state {
+ pins = "gpio56", "gpio57";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ cci2_1_sleep: cci2-1-sleep-state {
+ pins = "gpio56", "gpio57";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci3_0_default: cci3-0-default-state {
+ pins = "gpio66", "gpio67";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ cci3_0_sleep: cci3-0-sleep-state {
+ pins = "gpio66", "gpio67";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci3_1_default: cci3-1-default-state {
+ pins = "gpio58", "gpio59";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ cci3_1_sleep: cci3-1-sleep-state {
+ pins = "gpio58", "gpio59";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_i2c0_default: qup-i2c0-state {
+ pins = "gpio20", "gpio21";
+ function = "qup0_se0";
+ };
+
+ qup_i2c1_default: qup-i2c1-state {
+ pins = "gpio24", "gpio25";
+ function = "qup0_se1";
+ };
+
+ qup_i2c2_default: qup-i2c2-state {
+ pins = "gpio36", "gpio37";
+ function = "qup0_se2";
+ };
+
+ qup_i2c3_default: qup-i2c3-state {
+ pins = "gpio28", "gpio29";
+ function = "qup0_se3";
+ };
+
+ qup_i2c4_default: qup-i2c4-state {
+ pins = "gpio32", "gpio33";
+ function = "qup0_se4";
+ };
+
+ qup_i2c5_default: qup-i2c5-state {
+ pins = "gpio36", "gpio37";
+ function = "qup0_se5";
+ };
+
+ qup_i2c7_default: qup-i2c7-state {
+ pins = "gpio40", "gpio41";
+ function = "qup1_se0";
+ };
+
+ qup_i2c8_default: qup-i2c8-state {
+ pins = "gpio42", "gpio43";
+ function = "qup1_se1";
+ };
+
+ qup_i2c9_default: qup-i2c9-state {
+ pins = "gpio46", "gpio47";
+ function = "qup1_se2";
+ };
+
+ qup_i2c10_default: qup-i2c10-state {
+ pins = "gpio44", "gpio45";
+ function = "qup1_se3";
+ };
+
+ qup_i2c11_default: qup-i2c11-state {
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ };
+
+ qup_i2c12_default: qup-i2c12-state {
+ pins = "gpio52", "gpio53";
+ function = "qup1_se5";
+ };
+
+ qup_i2c13_default: qup-i2c13-state {
+ pins = "gpio56", "gpio57";
+ function = "qup1_se6";
+ };
+
+ qup_i2c14_default: qup-i2c14-state {
+ pins = "gpio80", "gpio81";
+ function = "qup2_se0";
+ };
+
+ qup_i2c15_default: qup-i2c15-state {
+ pins = "gpio84", "gpio85";
+ function = "qup2_se1";
+ };
+
+ qup_i2c16_default: qup-i2c16-state {
+ pins = "gpio86", "gpio87";
+ function = "qup2_se2";
+ };
+
+ qup_i2c17_default: qup-i2c17-state {
+ pins = "gpio91", "gpio92";
+ function = "qup2_se3";
+ };
+
+ qup_i2c18_default: qup-i2c18-state {
+ pins = "gpio95", "gpio96";
+ function = "qup2_se4";
+ };
+
+ qup_i2c19_default: qup-i2c19-state {
+ pins = "gpio99", "gpio100";
+ function = "qup2_se5";
+ };
+
+ qup_i2c20_default: qup-i2c20-state {
+ pins = "gpio97", "gpio98";
+ function = "qup2_se6";
+ };
+
+ qup_i2c21_default: qup-i2c21-state {
+ pins = "gpio13", "gpio14";
+ function = "qup3_se0";
+ };
+
+ qup_spi0_default: qup-spi0-state {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "qup0_se0";
+ };
+
+ qup_spi1_default: qup-spi1-state {
+ pins = "gpio24", "gpio25", "gpio26", "gpio27";
+ function = "qup0_se1";
+ };
+
+ qup_spi2_default: qup-spi2-state {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39";
+ function = "qup0_se2";
+ };
+
+ qup_spi3_default: qup-spi3-state {
+ pins = "gpio28", "gpio29", "gpio30", "gpio31";
+ function = "qup0_se3";
+ };
+
+ qup_spi4_default: qup-spi4-state {
+ pins = "gpio32", "gpio33", "gpio34", "gpio35";
+ function = "qup0_se4";
+ };
+
+ qup_spi5_default: qup-spi5-state {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39";
+ function = "qup0_se5";
+ };
+
+ qup_spi7_default: qup-spi7-state {
+ pins = "gpio40", "gpio41", "gpio42", "gpio43";
+ function = "qup1_se0";
+ };
+
+ qup_spi8_default: qup-spi8-state {
+ pins = "gpio42", "gpio43", "gpio40", "gpio41";
+ function = "qup1_se1";
+ };
+
+ qup_spi9_default: qup-spi9-state {
+ pins = "gpio46", "gpio47", "gpio44", "gpio45";
+ function = "qup1_se2";
+ };
+
+ qup_spi10_default: qup-spi10-state {
+ pins = "gpio44", "gpio45", "gpio46", "gpio47";
+ function = "qup1_se3";
+ };
+
+ qup_spi11_default: qup-spi11-state {
+ pins = "gpio48", "gpio49", "gpio50", "gpio51";
+ function = "qup1_se4";
+ };
+
+ qup_spi12_default: qup-spi12-state {
+ pins = "gpio52", "gpio53", "gpio54", "gpio55";
+ function = "qup1_se5";
+ };
+
+ qup_spi14_default: qup-spi14-state {
+ pins = "gpio80", "gpio81", "gpio82", "gpio83";
+ function = "qup2_se0";
+ };
+
+ qup_spi15_default: qup-spi15-state {
+ pins = "gpio84", "gpio85", "gpio99", "gpio100";
+ function = "qup2_se1";
+ };
+
+ qup_spi16_default: qup-spi16-state {
+ pins = "gpio86", "gpio87", "gpio88", "gpio89";
+ function = "qup2_se2";
+ };
+
+ qup_spi17_default: qup-spi17-state {
+ pins = "gpio91", "gpio92", "gpio93", "gpio94";
+ function = "qup2_se3";
+ };
+
+ qup_spi18_default: qup-spi18-state {
+ pins = "gpio95", "gpio96", "gpio97", "gpio98";
+ function = "qup2_se4";
+ };
+
+ qup_spi19_default: qup-spi19-state {
+ pins = "gpio99", "gpio100", "gpio84", "gpio85";
+ function = "qup2_se5";
+ };
+
+ qup_spi20_default: qup-spi20-state {
+ pins = "gpio97", "gpio98", "gpio95", "gpio96";
+ function = "qup2_se6";
+ };
+
+ qup_spi21_default: qup-spi21-state {
+ pins = "gpio13", "gpio14", "gpio15", "gpio16";
+ function = "qup3_se0";
+ };
+
+ qup_uart0_default: qup-uart0-state {
+ qup_uart0_cts: qup-uart0-cts-pins {
+ pins = "gpio20";
+ function = "qup0_se0";
+ };
+
+ qup_uart0_rts: qup-uart0-rts-pins {
+ pins = "gpio21";
+ function = "qup0_se0";
+ };
+
+ qup_uart0_tx: qup-uart0-tx-pins {
+ pins = "gpio22";
+ function = "qup0_se0";
+ };
+
+ qup_uart0_rx: qup-uart0-rx-pins {
+ pins = "gpio23";
+ function = "qup0_se0";
+ };
+ };
+
+ qup_uart1_default: qup-uart1-state {
+ qup_uart1_cts: qup-uart1-cts-pins {
+ pins = "gpio24";
+ function = "qup0_se1";
+ };
+
+ qup_uart1_rts: qup-uart1-rts-pins {
+ pins = "gpio25";
+ function = "qup0_se1";
+ };
+
+ qup_uart1_tx: qup-uart1-tx-pins {
+ pins = "gpio26";
+ function = "qup0_se1";
+ };
+
+ qup_uart1_rx: qup-uart1-rx-pins {
+ pins = "gpio27";
+ function = "qup0_se1";
+ };
+ };
+
+ qup_uart2_default: qup-uart2-state {
+ qup_uart2_cts: qup-uart2-cts-pins {
+ pins = "gpio36";
+ function = "qup0_se2";
+ };
+
+ qup_uart2_rts: qup-uart2-rts-pins {
+ pins = "gpio37";
+ function = "qup0_se2";
+ };
+
+ qup_uart2_tx: qup-uart2-tx-pins {
+ pins = "gpio38";
+ function = "qup0_se2";
+ };
+
+ qup_uart2_rx: qup-uart2-rx-pins {
+ pins = "gpio39";
+ function = "qup0_se2";
+ };
+ };
+
+ qup_uart3_default: qup-uart3-state {
+ qup_uart3_cts: qup-uart3-cts-pins {
+ pins = "gpio28";
+ function = "qup0_se3";
+ };
+
+ qup_uart3_rts: qup-uart3-rts-pins {
+ pins = "gpio29";
+ function = "qup0_se3";
+ };
+
+ qup_uart3_tx: qup-uart3-tx-pins {
+ pins = "gpio30";
+ function = "qup0_se3";
+ };
+
+ qup_uart3_rx: qup-uart3-rx-pins {
+ pins = "gpio31";
+ function = "qup0_se3";
+ };
+ };
+
+ qup_uart4_default: qup-uart4-state {
+ qup_uart4_cts: qup-uart4-cts-pins {
+ pins = "gpio32";
+ function = "qup0_se4";
+ };
+
+ qup_uart4_rts: qup-uart4-rts-pins {
+ pins = "gpio33";
+ function = "qup0_se4";
+ };
+
+ qup_uart4_tx: qup-uart4-tx-pins {
+ pins = "gpio34";
+ function = "qup0_se4";
+ };
+
+ qup_uart4_rx: qup-uart4-rx-pins {
+ pins = "gpio35";
+ function = "qup0_se4";
+ };
+ };
+
+ qup_uart5_default: qup-uart5-state {
+ qup_uart5_cts: qup-uart5-cts-pins {
+ pins = "gpio36";
+ function = "qup0_se5";
+ };
+
+ qup_uart5_rts: qup-uart5-rts-pins {
+ pins = "gpio37";
+ function = "qup0_se5";
+ };
+
+ qup_uart5_tx: qup-uart5-tx-pins {
+ pins = "gpio38";
+ function = "qup0_se5";
+ };
+
+ qup_uart5_rx: qup-uart5-rx-pins {
+ pins = "gpio39";
+ function = "qup0_se5";
+ };
+ };
+
+ qup_uart7_default: qup-uart7-state {
+ qup_uart7_cts: qup-uart7-cts-pins {
+ pins = "gpio40";
+ function = "qup1_se0";
+ };
+
+ qup_uart7_rts: qup-uart7-rts-pins {
+ pins = "gpio41";
+ function = "qup1_se0";
+ };
+
+ qup_uart7_tx: qup-uart7-tx-pins {
+ pins = "gpio42";
+ function = "qup1_se0";
+ };
+
+ qup_uart7_rx: qup-uart7-rx-pins {
+ pins = "gpio43";
+ function = "qup1_se0";
+ };
+ };
+
+ qup_uart8_default: qup-uart8-state {
+ qup_uart8_cts: qup-uart8-cts-pins {
+ pins = "gpio42";
+ function = "qup1_se1";
+ };
+
+ qup_uart8_rts: qup-uart8-rts-pins {
+ pins = "gpio43";
+ function = "qup1_se1";
+ };
+
+ qup_uart8_tx: qup-uart8-tx-pins {
+ pins = "gpio40";
+ function = "qup1_se1";
+ };
+
+ qup_uart8_rx: qup-uart8-rx-pins {
+ pins = "gpio41";
+ function = "qup1_se1";
+ };
+ };
+
+ qup_uart9_default: qup-uart9-state {
+ qup_uart9_cts: qup-uart9-cts-pins {
+ pins = "gpio46";
+ function = "qup1_se2";
+ };
+
+ qup_uart9_rts: qup-uart9-rts-pins {
+ pins = "gpio47";
+ function = "qup1_se2";
+ };
+
+ qup_uart9_tx: qup-uart9-tx-pins {
+ pins = "gpio44";
+ function = "qup1_se2";
+ };
+
+ qup_uart9_rx: qup-uart9-rx-pins {
+ pins = "gpio45";
+ function = "qup1_se2";
+ };
+ };
+
+ qup_uart10_default: qup-uart10-state {
+ pins = "gpio46", "gpio47";
+ function = "qup1_se3";
+ };
+
+ qup_uart11_default: qup-uart11-state {
+ qup_uart11_cts: qup-uart11-cts-pins {
+ pins = "gpio48";
+ function = "qup1_se4";
+ };
+
+ qup_uart11_rts: qup-uart11-rts-pins {
+ pins = "gpio49";
+ function = "qup1_se4";
+ };
+
+ qup_uart11_tx: qup-uart11-tx-pins {
+ pins = "gpio50";
+ function = "qup1_se4";
+ };
+
+ qup_uart11_rx: qup-uart11-rx-pins {
+ pins = "gpio51";
+ function = "qup1_se4";
+ };
+ };
+
+ qup_uart12_default: qup-uart12-state {
+ qup_uart12_cts: qup-uart12-cts-pins {
+ pins = "gpio52";
+ function = "qup1_se5";
+ };
+
+ qup_uart12_rts: qup-uart12-rts-pins {
+ pins = "gpio53";
+ function = "qup1_se5";
+ };
+
+ qup_uart12_tx: qup-uart12-tx-pins {
+ pins = "gpio54";
+ function = "qup1_se5";
+ };
+
+ qup_uart12_rx: qup-uart12-rx-pins {
+ pins = "gpio55";
+ function = "qup1_se5";
+ };
+ };
+
+ qup_uart14_default: qup-uart14-state {
+ qup_uart14_cts: qup-uart14-cts-pins {
+ pins = "gpio80";
+ function = "qup2_se0";
+ };
+
+ qup_uart14_rts: qup-uart14-rts-pins {
+ pins = "gpio81";
+ function = "qup2_se0";
+ };
+
+ qup_uart14_tx: qup-uart14-tx-pins {
+ pins = "gpio82";
+ function = "qup2_se0";
+ };
+
+ qup_uart14_rx: qup-uart14-rx-pins {
+ pins = "gpio83";
+ function = "qup2_se0";
+ };
+ };
+
+ qup_uart15_default: qup-uart15-state {
+ qup_uart15_cts: qup-uart15-cts-pins {
+ pins = "gpio84";
+ function = "qup2_se1";
+ };
+
+ qup_uart15_rts: qup-uart15-rts-pins {
+ pins = "gpio85";
+ function = "qup2_se1";
+ };
+
+ qup_uart15_tx: qup-uart15-tx-pins {
+ pins = "gpio99";
+ function = "qup2_se1";
+ };
+
+ qup_uart15_rx: qup-uart15-rx-pins {
+ pins = "gpio100";
+ function = "qup2_se1";
+ };
+ };
+
+ qup_uart16_default: qup-uart16-state {
+ qup_uart16_cts: qup-uart16-cts-pins {
+ pins = "gpio86";
+ function = "qup2_se2";
+ };
+
+ qup_uart16_rts: qup-uart16-rts-pins {
+ pins = "gpio87";
+ function = "qup2_se2";
+ };
+
+ qup_uart16_tx: qup-uart16-tx-pins {
+ pins = "gpio88";
+ function = "qup2_se2";
+ };
+
+ qup_uart16_rx: qup-uart16-rx-pins {
+ pins = "gpio89";
+ function = "qup2_se2";
+ };
+ };
+
+ qup_uart17_default: qup-uart17-state {
+ qup_uart17_cts: qup-uart17-cts-pins {
+ pins = "gpio91";
+ function = "qup2_se3";
+ };
+
+ qup_uart17_rts: qup0-uart17-rts-pins {
+ pins = "gpio92";
+ function = "qup2_se3";
+ };
+
+ qup_uart17_tx: qup0-uart17-tx-pins {
+ pins = "gpio93";
+ function = "qup2_se3";
+ };
+
+ qup_uart17_rx: qup0-uart17-rx-pins {
+ pins = "gpio94";
+ function = "qup2_se3";
+ };
+ };
+
+ qup_uart18_default: qup-uart18-state {
+ qup_uart18_cts: qup-uart18-cts-pins {
+ pins = "gpio95";
+ function = "qup2_se4";
+ };
+
+ qup_uart18_rts: qup-uart18-rts-pins {
+ pins = "gpio96";
+ function = "qup2_se4";
+ };
+
+ qup_uart18_tx: qup-uart18-tx-pins {
+ pins = "gpio97";
+ function = "qup2_se4";
+ };
+
+ qup_uart18_rx: qup-uart18-rx-pins {
+ pins = "gpio98";
+ function = "qup2_se4";
+ };
+ };
+
+ qup_uart19_default: qup-uart19-state {
+ qup_uart19_cts: qup-uart19-cts-pins {
+ pins = "gpio99";
+ function = "qup2_se5";
+ };
+
+ qup_uart19_rts: qup-uart19-rts-pins {
+ pins = "gpio100";
+ function = "qup2_se5";
+ };
+
+ qup_uart19_tx: qup-uart19-tx-pins {
+ pins = "gpio84";
+ function = "qup2_se5";
+ };
+
+ qup_uart19_rx: qup-uart19-rx-pins {
+ pins = "gpio85";
+ function = "qup2_se5";
+ };
+ };
+
+ qup_uart20_default: qup-uart20-state {
+ qup_uart20_cts: qup-uart20-cts-pins {
+ pins = "gpio97";
+ function = "qup2_se6";
+ };
+
+ qup_uart20_rts: qup-uart20-rts-pins {
+ pins = "gpio98";
+ function = "qup2_se6";
+ };
+
+ qup_uart20_tx: qup-uart20-tx-pins {
+ pins = "gpio95";
+ function = "qup2_se6";
+ };
+
+ qup_uart20_rx: qup-uart20-rx-pins {
+ pins = "gpio96";
+ function = "qup2_se6";
+ };
+ };
+
+ qup_uart21_default: qup-uart21-state {
+ qup_uart21_cts: qup-uart21-cts-pins {
+ pins = "gpio13";
+ function = "qup3_se0";
+ };
+
+ qup_uart21_rts: qup-uart21-rts-pins {
+ pins = "gpio14";
+ function = "qup3_se0";
+ };
+
+ qup_uart21_tx: qup-uart21-tx-pins {
+ pins = "gpio15";
+ function = "qup3_se0";
+ };
+
+ qup_uart21_rx: qup-uart21-rx-pins {
+ pins = "gpio16";
+ function = "qup3_se0";
+ };
+ };
+
+ sdc_default: sdc-default-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc_sleep: sdc-sleep-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 1fdb72fa5518..7547042d8e85 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -6004,812 +6004,6 @@ tlmm: pinctrl@f000000 {
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 149>;
wakeup-parent = <&pdc>;
-
- dp0_hot_plug_det: dp0-hot-plug-det-state {
- pins = "gpio101";
- function = "edp0_hot";
- bias-disable;
- };
-
- dp1_hot_plug_det: dp1-hot-plug-det-state {
- pins = "gpio102";
- function = "edp1_hot";
- bias-disable;
- };
-
- hs0_mi2s_active: hs0-mi2s-active-state {
- pins = "gpio114", "gpio115", "gpio116", "gpio117";
- function = "hs0_mi2s";
- drive-strength = <8>;
- bias-disable;
- };
-
- hs2_mi2s_active: hs2-mi2s-active-state {
- pins = "gpio122", "gpio123", "gpio124", "gpio125";
- function = "hs2_mi2s";
- drive-strength = <8>;
- bias-disable;
- };
-
- cci0_0_default: cci0-0-default-state {
- pins = "gpio60", "gpio61";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-up = <2200>;
- };
-
- cci0_0_sleep: cci0-0-sleep-state {
- pins = "gpio60", "gpio61";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- cci0_1_default: cci0-1-default-state {
- pins = "gpio52", "gpio53";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-up = <2200>;
- };
-
- cci0_1_sleep: cci0-1-sleep-state {
- pins = "gpio52", "gpio53";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- cci1_0_default: cci1-0-default-state {
- pins = "gpio62", "gpio63";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-up = <2200>;
- };
-
- cci1_0_sleep: cci1-0-sleep-state {
- pins = "gpio62", "gpio63";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- cci1_1_default: cci1-1-default-state {
- pins = "gpio54", "gpio55";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-up = <2200>;
- };
-
- cci1_1_sleep: cci1-1-sleep-state {
- pins = "gpio54", "gpio55";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- cci2_0_default: cci2-0-default-state {
- pins = "gpio64", "gpio65";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-up = <2200>;
- };
-
- cci2_0_sleep: cci2-0-sleep-state {
- pins = "gpio64", "gpio65";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- cci2_1_default: cci2-1-default-state {
- pins = "gpio56", "gpio57";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-up = <2200>;
- };
-
- cci2_1_sleep: cci2-1-sleep-state {
- pins = "gpio56", "gpio57";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- cci3_0_default: cci3-0-default-state {
- pins = "gpio66", "gpio67";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-up = <2200>;
- };
-
- cci3_0_sleep: cci3-0-sleep-state {
- pins = "gpio66", "gpio67";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- cci3_1_default: cci3-1-default-state {
- pins = "gpio58", "gpio59";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-up = <2200>;
- };
-
- cci3_1_sleep: cci3-1-sleep-state {
- pins = "gpio58", "gpio59";
- function = "cci_i2c";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- qup_i2c0_default: qup-i2c0-state {
- pins = "gpio20", "gpio21";
- function = "qup0_se0";
- };
-
- qup_i2c1_default: qup-i2c1-state {
- pins = "gpio24", "gpio25";
- function = "qup0_se1";
- };
-
- qup_i2c2_default: qup-i2c2-state {
- pins = "gpio36", "gpio37";
- function = "qup0_se2";
- };
-
- qup_i2c3_default: qup-i2c3-state {
- pins = "gpio28", "gpio29";
- function = "qup0_se3";
- };
-
- qup_i2c4_default: qup-i2c4-state {
- pins = "gpio32", "gpio33";
- function = "qup0_se4";
- };
-
- qup_i2c5_default: qup-i2c5-state {
- pins = "gpio36", "gpio37";
- function = "qup0_se5";
- };
-
- qup_i2c7_default: qup-i2c7-state {
- pins = "gpio40", "gpio41";
- function = "qup1_se0";
- };
-
- qup_i2c8_default: qup-i2c8-state {
- pins = "gpio42", "gpio43";
- function = "qup1_se1";
- };
-
- qup_i2c9_default: qup-i2c9-state {
- pins = "gpio46", "gpio47";
- function = "qup1_se2";
- };
-
- qup_i2c10_default: qup-i2c10-state {
- pins = "gpio44", "gpio45";
- function = "qup1_se3";
- };
-
- qup_i2c11_default: qup-i2c11-state {
- pins = "gpio48", "gpio49";
- function = "qup1_se4";
- };
-
- qup_i2c12_default: qup-i2c12-state {
- pins = "gpio52", "gpio53";
- function = "qup1_se5";
- };
-
- qup_i2c13_default: qup-i2c13-state {
- pins = "gpio56", "gpio57";
- function = "qup1_se6";
- };
-
- qup_i2c14_default: qup-i2c14-state {
- pins = "gpio80", "gpio81";
- function = "qup2_se0";
- };
-
- qup_i2c15_default: qup-i2c15-state {
- pins = "gpio84", "gpio85";
- function = "qup2_se1";
- };
-
- qup_i2c16_default: qup-i2c16-state {
- pins = "gpio86", "gpio87";
- function = "qup2_se2";
- };
-
- qup_i2c17_default: qup-i2c17-state {
- pins = "gpio91", "gpio92";
- function = "qup2_se3";
- };
-
- qup_i2c18_default: qup-i2c18-state {
- pins = "gpio95", "gpio96";
- function = "qup2_se4";
- };
-
- qup_i2c19_default: qup-i2c19-state {
- pins = "gpio99", "gpio100";
- function = "qup2_se5";
- };
-
- qup_i2c20_default: qup-i2c20-state {
- pins = "gpio97", "gpio98";
- function = "qup2_se6";
- };
-
- qup_i2c21_default: qup-i2c21-state {
- pins = "gpio13", "gpio14";
- function = "qup3_se0";
- };
-
- qup_spi0_default: qup-spi0-state {
- pins = "gpio20", "gpio21", "gpio22", "gpio23";
- function = "qup0_se0";
- };
-
- qup_spi1_default: qup-spi1-state {
- pins = "gpio24", "gpio25", "gpio26", "gpio27";
- function = "qup0_se1";
- };
-
- qup_spi2_default: qup-spi2-state {
- pins = "gpio36", "gpio37", "gpio38", "gpio39";
- function = "qup0_se2";
- };
-
- qup_spi3_default: qup-spi3-state {
- pins = "gpio28", "gpio29", "gpio30", "gpio31";
- function = "qup0_se3";
- };
-
- qup_spi4_default: qup-spi4-state {
- pins = "gpio32", "gpio33", "gpio34", "gpio35";
- function = "qup0_se4";
- };
-
- qup_spi5_default: qup-spi5-state {
- pins = "gpio36", "gpio37", "gpio38", "gpio39";
- function = "qup0_se5";
- };
-
- qup_spi7_default: qup-spi7-state {
- pins = "gpio40", "gpio41", "gpio42", "gpio43";
- function = "qup1_se0";
- };
-
- qup_spi8_default: qup-spi8-state {
- pins = "gpio42", "gpio43", "gpio40", "gpio41";
- function = "qup1_se1";
- };
-
- qup_spi9_default: qup-spi9-state {
- pins = "gpio46", "gpio47", "gpio44", "gpio45";
- function = "qup1_se2";
- };
-
- qup_spi10_default: qup-spi10-state {
- pins = "gpio44", "gpio45", "gpio46", "gpio47";
- function = "qup1_se3";
- };
-
- qup_spi11_default: qup-spi11-state {
- pins = "gpio48", "gpio49", "gpio50", "gpio51";
- function = "qup1_se4";
- };
-
- qup_spi12_default: qup-spi12-state {
- pins = "gpio52", "gpio53", "gpio54", "gpio55";
- function = "qup1_se5";
- };
-
- qup_spi14_default: qup-spi14-state {
- pins = "gpio80", "gpio81", "gpio82", "gpio83";
- function = "qup2_se0";
- };
-
- qup_spi15_default: qup-spi15-state {
- pins = "gpio84", "gpio85", "gpio99", "gpio100";
- function = "qup2_se1";
- };
-
- qup_spi16_default: qup-spi16-state {
- pins = "gpio86", "gpio87", "gpio88", "gpio89";
- function = "qup2_se2";
- };
-
- qup_spi17_default: qup-spi17-state {
- pins = "gpio91", "gpio92", "gpio93", "gpio94";
- function = "qup2_se3";
- };
-
- qup_spi18_default: qup-spi18-state {
- pins = "gpio95", "gpio96", "gpio97", "gpio98";
- function = "qup2_se4";
- };
-
- qup_spi19_default: qup-spi19-state {
- pins = "gpio99", "gpio100", "gpio84", "gpio85";
- function = "qup2_se5";
- };
-
- qup_spi20_default: qup-spi20-state {
- pins = "gpio97", "gpio98", "gpio95", "gpio96";
- function = "qup2_se6";
- };
-
- qup_spi21_default: qup-spi21-state {
- pins = "gpio13", "gpio14", "gpio15", "gpio16";
- function = "qup3_se0";
- };
-
- qup_uart0_default: qup-uart0-state {
- qup_uart0_cts: qup-uart0-cts-pins {
- pins = "gpio20";
- function = "qup0_se0";
- };
-
- qup_uart0_rts: qup-uart0-rts-pins {
- pins = "gpio21";
- function = "qup0_se0";
- };
-
- qup_uart0_tx: qup-uart0-tx-pins {
- pins = "gpio22";
- function = "qup0_se0";
- };
-
- qup_uart0_rx: qup-uart0-rx-pins {
- pins = "gpio23";
- function = "qup0_se0";
- };
- };
-
- qup_uart1_default: qup-uart1-state {
- qup_uart1_cts: qup-uart1-cts-pins {
- pins = "gpio24";
- function = "qup0_se1";
- };
-
- qup_uart1_rts: qup-uart1-rts-pins {
- pins = "gpio25";
- function = "qup0_se1";
- };
-
- qup_uart1_tx: qup-uart1-tx-pins {
- pins = "gpio26";
- function = "qup0_se1";
- };
-
- qup_uart1_rx: qup-uart1-rx-pins {
- pins = "gpio27";
- function = "qup0_se1";
- };
- };
-
- qup_uart2_default: qup-uart2-state {
- qup_uart2_cts: qup-uart2-cts-pins {
- pins = "gpio36";
- function = "qup0_se2";
- };
-
- qup_uart2_rts: qup-uart2-rts-pins {
- pins = "gpio37";
- function = "qup0_se2";
- };
-
- qup_uart2_tx: qup-uart2-tx-pins {
- pins = "gpio38";
- function = "qup0_se2";
- };
-
- qup_uart2_rx: qup-uart2-rx-pins {
- pins = "gpio39";
- function = "qup0_se2";
- };
- };
-
- qup_uart3_default: qup-uart3-state {
- qup_uart3_cts: qup-uart3-cts-pins {
- pins = "gpio28";
- function = "qup0_se3";
- };
-
- qup_uart3_rts: qup-uart3-rts-pins {
- pins = "gpio29";
- function = "qup0_se3";
- };
-
- qup_uart3_tx: qup-uart3-tx-pins {
- pins = "gpio30";
- function = "qup0_se3";
- };
-
- qup_uart3_rx: qup-uart3-rx-pins {
- pins = "gpio31";
- function = "qup0_se3";
- };
- };
-
- qup_uart4_default: qup-uart4-state {
- qup_uart4_cts: qup-uart4-cts-pins {
- pins = "gpio32";
- function = "qup0_se4";
- };
-
- qup_uart4_rts: qup-uart4-rts-pins {
- pins = "gpio33";
- function = "qup0_se4";
- };
-
- qup_uart4_tx: qup-uart4-tx-pins {
- pins = "gpio34";
- function = "qup0_se4";
- };
-
- qup_uart4_rx: qup-uart4-rx-pins {
- pins = "gpio35";
- function = "qup0_se4";
- };
- };
-
- qup_uart5_default: qup-uart5-state {
- qup_uart5_cts: qup-uart5-cts-pins {
- pins = "gpio36";
- function = "qup0_se5";
- };
-
- qup_uart5_rts: qup-uart5-rts-pins {
- pins = "gpio37";
- function = "qup0_se5";
- };
-
- qup_uart5_tx: qup-uart5-tx-pins {
- pins = "gpio38";
- function = "qup0_se5";
- };
-
- qup_uart5_rx: qup-uart5-rx-pins {
- pins = "gpio39";
- function = "qup0_se5";
- };
- };
-
- qup_uart7_default: qup-uart7-state {
- qup_uart7_cts: qup-uart7-cts-pins {
- pins = "gpio40";
- function = "qup1_se0";
- };
-
- qup_uart7_rts: qup-uart7-rts-pins {
- pins = "gpio41";
- function = "qup1_se0";
- };
-
- qup_uart7_tx: qup-uart7-tx-pins {
- pins = "gpio42";
- function = "qup1_se0";
- };
-
- qup_uart7_rx: qup-uart7-rx-pins {
- pins = "gpio43";
- function = "qup1_se0";
- };
- };
-
- qup_uart8_default: qup-uart8-state {
- qup_uart8_cts: qup-uart8-cts-pins {
- pins = "gpio42";
- function = "qup1_se1";
- };
-
- qup_uart8_rts: qup-uart8-rts-pins {
- pins = "gpio43";
- function = "qup1_se1";
- };
-
- qup_uart8_tx: qup-uart8-tx-pins {
- pins = "gpio40";
- function = "qup1_se1";
- };
-
- qup_uart8_rx: qup-uart8-rx-pins {
- pins = "gpio41";
- function = "qup1_se1";
- };
- };
-
- qup_uart9_default: qup-uart9-state {
- qup_uart9_cts: qup-uart9-cts-pins {
- pins = "gpio46";
- function = "qup1_se2";
- };
-
- qup_uart9_rts: qup-uart9-rts-pins {
- pins = "gpio47";
- function = "qup1_se2";
- };
-
- qup_uart9_tx: qup-uart9-tx-pins {
- pins = "gpio44";
- function = "qup1_se2";
- };
-
- qup_uart9_rx: qup-uart9-rx-pins {
- pins = "gpio45";
- function = "qup1_se2";
- };
- };
-
- qup_uart10_default: qup-uart10-state {
- pins = "gpio46", "gpio47";
- function = "qup1_se3";
- };
-
- qup_uart11_default: qup-uart11-state {
- qup_uart11_cts: qup-uart11-cts-pins {
- pins = "gpio48";
- function = "qup1_se4";
- };
-
- qup_uart11_rts: qup-uart11-rts-pins {
- pins = "gpio49";
- function = "qup1_se4";
- };
-
- qup_uart11_tx: qup-uart11-tx-pins {
- pins = "gpio50";
- function = "qup1_se4";
- };
-
- qup_uart11_rx: qup-uart11-rx-pins {
- pins = "gpio51";
- function = "qup1_se4";
- };
- };
-
- qup_uart12_default: qup-uart12-state {
- qup_uart12_cts: qup-uart12-cts-pins {
- pins = "gpio52";
- function = "qup1_se5";
- };
-
- qup_uart12_rts: qup-uart12-rts-pins {
- pins = "gpio53";
- function = "qup1_se5";
- };
-
- qup_uart12_tx: qup-uart12-tx-pins {
- pins = "gpio54";
- function = "qup1_se5";
- };
-
- qup_uart12_rx: qup-uart12-rx-pins {
- pins = "gpio55";
- function = "qup1_se5";
- };
- };
-
- qup_uart14_default: qup-uart14-state {
- qup_uart14_cts: qup-uart14-cts-pins {
- pins = "gpio80";
- function = "qup2_se0";
- };
-
- qup_uart14_rts: qup-uart14-rts-pins {
- pins = "gpio81";
- function = "qup2_se0";
- };
-
- qup_uart14_tx: qup-uart14-tx-pins {
- pins = "gpio82";
- function = "qup2_se0";
- };
-
- qup_uart14_rx: qup-uart14-rx-pins {
- pins = "gpio83";
- function = "qup2_se0";
- };
- };
-
- qup_uart15_default: qup-uart15-state {
- qup_uart15_cts: qup-uart15-cts-pins {
- pins = "gpio84";
- function = "qup2_se1";
- };
-
- qup_uart15_rts: qup-uart15-rts-pins {
- pins = "gpio85";
- function = "qup2_se1";
- };
-
- qup_uart15_tx: qup-uart15-tx-pins {
- pins = "gpio99";
- function = "qup2_se1";
- };
-
- qup_uart15_rx: qup-uart15-rx-pins {
- pins = "gpio100";
- function = "qup2_se1";
- };
- };
-
- qup_uart16_default: qup-uart16-state {
- qup_uart16_cts: qup-uart16-cts-pins {
- pins = "gpio86";
- function = "qup2_se2";
- };
-
- qup_uart16_rts: qup-uart16-rts-pins {
- pins = "gpio87";
- function = "qup2_se2";
- };
-
- qup_uart16_tx: qup-uart16-tx-pins {
- pins = "gpio88";
- function = "qup2_se2";
- };
-
- qup_uart16_rx: qup-uart16-rx-pins {
- pins = "gpio89";
- function = "qup2_se2";
- };
- };
-
- qup_uart17_default: qup-uart17-state {
- qup_uart17_cts: qup-uart17-cts-pins {
- pins = "gpio91";
- function = "qup2_se3";
- };
-
- qup_uart17_rts: qup0-uart17-rts-pins {
- pins = "gpio92";
- function = "qup2_se3";
- };
-
- qup_uart17_tx: qup0-uart17-tx-pins {
- pins = "gpio93";
- function = "qup2_se3";
- };
-
- qup_uart17_rx: qup0-uart17-rx-pins {
- pins = "gpio94";
- function = "qup2_se3";
- };
- };
-
- qup_uart18_default: qup-uart18-state {
- qup_uart18_cts: qup-uart18-cts-pins {
- pins = "gpio95";
- function = "qup2_se4";
- };
-
- qup_uart18_rts: qup-uart18-rts-pins {
- pins = "gpio96";
- function = "qup2_se4";
- };
-
- qup_uart18_tx: qup-uart18-tx-pins {
- pins = "gpio97";
- function = "qup2_se4";
- };
-
- qup_uart18_rx: qup-uart18-rx-pins {
- pins = "gpio98";
- function = "qup2_se4";
- };
- };
-
- qup_uart19_default: qup-uart19-state {
- qup_uart19_cts: qup-uart19-cts-pins {
- pins = "gpio99";
- function = "qup2_se5";
- };
-
- qup_uart19_rts: qup-uart19-rts-pins {
- pins = "gpio100";
- function = "qup2_se5";
- };
-
- qup_uart19_tx: qup-uart19-tx-pins {
- pins = "gpio84";
- function = "qup2_se5";
- };
-
- qup_uart19_rx: qup-uart19-rx-pins {
- pins = "gpio85";
- function = "qup2_se5";
- };
- };
-
- qup_uart20_default: qup-uart20-state {
- qup_uart20_cts: qup-uart20-cts-pins {
- pins = "gpio97";
- function = "qup2_se6";
- };
-
- qup_uart20_rts: qup-uart20-rts-pins {
- pins = "gpio98";
- function = "qup2_se6";
- };
-
- qup_uart20_tx: qup-uart20-tx-pins {
- pins = "gpio95";
- function = "qup2_se6";
- };
-
- qup_uart20_rx: qup-uart20-rx-pins {
- pins = "gpio96";
- function = "qup2_se6";
- };
- };
-
- qup_uart21_default: qup-uart21-state {
- qup_uart21_cts: qup-uart21-cts-pins {
- pins = "gpio13";
- function = "qup3_se0";
- };
-
- qup_uart21_rts: qup-uart21-rts-pins {
- pins = "gpio14";
- function = "qup3_se0";
- };
-
- qup_uart21_tx: qup-uart21-tx-pins {
- pins = "gpio15";
- function = "qup3_se0";
- };
-
- qup_uart21_rx: qup-uart21-rx-pins {
- pins = "gpio16";
- function = "qup3_se0";
- };
- };
-
- sdc_default: sdc-default-state {
- clk-pins {
- pins = "sdc1_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "sdc1_cmd";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdc_sleep: sdc-sleep-state {
- clk-pins {
- pins = "sdc1_clk";
- drive-strength = <2>;
- bias-bus-hold;
- };
-
- cmd-pins {
- pins = "sdc1_cmd";
- drive-strength = <2>;
- bias-bus-hold;
- };
-
- data-pins {
- pins = "sdc1_data";
- drive-strength = <2>;
- bias-bus-hold;
- };
- };
};
sram: sram@146d8000 {
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/7] arm64: dts: qcom: lemans: Move platform resources into lemans-embedded.dtsi
2026-10-15 2:37 [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC Shawn Guo
2026-10-15 2:37 ` [PATCH v2 1/7] arm64: dts: qcom: Introduce lemans-embedded.dtsi as a placeholder Shawn Guo
2026-10-15 2:37 ` [PATCH v2 2/7] arm64: dts: qcom: lemans: Move pinctrl states into lemans-embedded.dtsi Shawn Guo
@ 2026-10-15 2:37 ` Shawn Guo
2026-10-15 2:48 ` sashiko-bot
2026-10-15 2:37 ` [PATCH v2 4/7] arm64: dts: qcom: lemans: Add label for firmware and reserved-memory Shawn Guo
` (3 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Shawn Guo @ 2026-10-15 2:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Deepti Jaggi, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
Devicetree lemans-embedded.dtsi was created for Lemans Embedded variant
where platform resource like clocks, regulator, interconnects, pinctrls
and PHYs are managed by Linux. Move them from lemans.dtsi to
lemans-embedded.dtsi, so that lemans.dtsi could be used by GearVM
variant.
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-embedded.dtsi | 2871 +++++++++++++++++
arch/arm64/boot/dts/qcom/lemans.dtsi | 2559 +--------------
2 files changed, 2875 insertions(+), 2555 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi b/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
index 107db7a74756..3733c0b7bace 100644
--- a/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
@@ -3,8 +3,2770 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
+#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
+#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
+#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
#include "lemans.dtsi"
+/ {
+ clocks {
+ xo_board_clk: xo-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1862400000 {
+ opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1939200000 {
+ opp-hz = /bits/ 64 <1939200000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2265600000 {
+ opp-hz = /bits/ 64 <2265600000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2361600000 {
+ opp-hz = /bits/ 64 <2361600000>;
+ opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
+ };
+
+ opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
+ };
+
+ opp-2553600000 {
+ opp-hz = /bits/ 64 <2553600000>;
+ opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
+ };
+ };
+
+ cpu4_opp_table: opp-table-cpu4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
+ };
+
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1862400000 {
+ opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-1939200000 {
+ opp-hz = /bits/ 64 <1939200000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
+ };
+
+ opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2265600000 {
+ opp-hz = /bits/ 64 <2265600000>;
+ opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
+ };
+
+ opp-2361600000 {
+ opp-hz = /bits/ 64 <2361600000>;
+ opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
+ };
+
+ opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
+ };
+
+ opp-2553600000 {
+ opp-hz = /bits/ 64 <2553600000>;
+ opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
+ };
+ };
+
+ clk_virt: interconnect-clk-virt {
+ compatible = "qcom,sa8775p-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-mc-virt {
+ compatible = "qcom,sa8775p-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ qup_opp_table_100mhz: opp-table-qup100mhz {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
+};
+
+&cpu4 {
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
+};
+
+&cpu5 {
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
+};
+
+&cpu6 {
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
+};
+
+&cpu7 {
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
+};
+
+&adreno_smmu {
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+};
+
+&camss {
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb_clk",
+ "cpas_vfe_lite",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "icp_ahb",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "top";
+};
+
+&cci0 {
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&cci1 {
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&cci2 {
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_2_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ pinctrl-0 = <&cci2_0_default &cci2_1_default>;
+ pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&cci3 {
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_3_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ pinctrl-0 = <&cci3_0_default &cci3_1_default>;
+ pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
+&cpu_bwmon0 {
+ compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+};
+
+&cpu_bwmon1 {
+ compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+};
+
+&crypto {
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+};
+
+&cpufreq_hw {
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+};
+
+ðernet1 {
+ clocks = <&gcc GCC_EMAC1_AXI_CLK>,
+ <&gcc GCC_EMAC1_SLV_AHB_CLK>,
+ <&gcc GCC_EMAC1_PTP_CLK>,
+ <&gcc GCC_EMAC1_PHY_AUX_CLK>;
+ clock-names = "stmmaceth",
+ "pclk",
+ "ptp_ref",
+ "phyaux";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-mac",
+ "mac-mem";
+
+ power-domains = <&gcc EMAC1_GDSC>;
+
+ phys = <&serdes1>;
+ phy-names = "serdes";
+};
+
+ðernet0 {
+ clocks = <&gcc GCC_EMAC0_AXI_CLK>,
+ <&gcc GCC_EMAC0_SLV_AHB_CLK>,
+ <&gcc GCC_EMAC0_PTP_CLK>,
+ <&gcc GCC_EMAC0_PHY_AUX_CLK>;
+ clock-names = "stmmaceth",
+ "pclk",
+ "ptp_ref",
+ "phyaux";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-mac",
+ "mac-mem";
+
+ power-domains = <&gcc EMAC0_GDSC>;
+
+ phys = <&serdes0>;
+ phy-names = "serdes";
+};
+
+&gmu {
+ compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+ };
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-405000000 {
+ opp-hz = /bits/ 64 <405000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <5285156>;
+ opp-supported-hw = <0x3>;
+ };
+
+ opp-530000000 {
+ opp-hz = /bits/ 64 <530000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <12484375>;
+ opp-supported-hw = <0x2>;
+ };
+
+ opp-676000000 {
+ opp-hz = /bits/ 64 <676000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <8171875>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-778000000 {
+ opp-hz = /bits/ 64 <778000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <10687500>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <12484375>;
+ opp-supported-hw = <0x1>;
+ };
+ };
+};
+
+&iris {
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd SA8775P_MX>,
+ <&rpmhpd SA8775P_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx";
+ operating-points-v2 = <&iris_opp_table>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
+ reset-names = "bus";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-533000000 {
+ opp-hz = /bits/ 64 <533000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-560000000 {
+ opp-hz = /bits/ 64 <560000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+};
+
+&llcc_bwmon {
+ compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+};
+
+&mdss0 {
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ mdss0_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0x0 0x0ae94400 0x0 0x200>,
+ <0x0 0x0ae94600 0x0 0x280>,
+ <0x0 0x0ae94900 0x0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss0_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0x0 0x0ae96400 0x0 0x200>,
+ <0x0 0x0ae96600 0x0 0x280>,
+ <0x0 0x0ae96900 0x0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss0_dp0_phy: phy@aec2a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+
+ reg = <0x0 0x0aec2a00 0x0 0x200>,
+ <0x0 0x0aec2200 0x0 0xd0>,
+ <0x0 0x0aec2600 0x0 0xd0>,
+ <0x0 0x0aec2000 0x0 0x1c8>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss0_dp1_phy: phy@aec5a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+
+ reg = <0x0 0x0aec5a00 0x0 0x200>,
+ <0x0 0x0aec5200 0x0 0xd0>,
+ <0x0 0x0aec5600 0x0 0xd0>,
+ <0x0 0x0aec5000 0x0 0x1c8>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+};
+
+&mdss0_mdp {
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+};
+
+&mdss0_dsi0 {
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>;
+ phys = <&mdss0_dsi0_phy>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ refgen-supply = <&refgen>;
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+};
+
+&mdss0_dsi1 {
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
+ phys = <&mdss0_dsi1_phy>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ refgen-supply = <&refgen>;
+};
+
+&mdss0_dp0 {
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+ assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp0_phy 0>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>;
+ phys = <&mdss0_dp0_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-162000000 {
+ opp-hz = /bits/ 64 <162000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+};
+
+&mdss0_dp1 {
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel";
+ assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp1_phy 0>,
+ <&mdss0_dp1_phy 1>,
+ <&mdss0_dp1_phy 1>;
+ phys = <&mdss0_dp1_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+};
+
+&mdss1 {
+ interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ mdss1_dp0_phy: phy@220c2a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+ reg = <0x0 0x220c2a00 0x0 0x200>,
+ <0x0 0x220c2200 0x0 0xd0>,
+ <0x0 0x220c2600 0x0 0xd0>,
+ <0x0 0x220c2000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp1_phy: phy@220c5a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+ reg = <0x0 0x220c5a00 0x0 0x200>,
+ <0x0 0x220c5200 0x0 0xd0>,
+ <0x0 0x220c5600 0x0 0xd0>,
+ <0x0 0x220c5000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+};
+
+&mdss1_mdp {
+ clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+};
+
+&mdss1_dp0 {
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp0_phy 0>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>;
+ phys = <&mdss1_dp0_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+};
+
+&mdss1_dp1 {
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel";
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp1_phy 0>,
+ <&mdss1_dp1_phy 1>,
+ <&mdss1_dp1_phy 1>;
+ phys = <&mdss1_dp1_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+};
+
+&pcie0 {
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ linux,pci-domain = <0>;
+};
+
+&pcie0_ep {
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "core";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ linux,pci-domain = <0>;
+};
+
+&pcie1 {
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_1_BCR>,
+ <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc PCIE_1_GDSC>;
+
+ linux,pci-domain = <1>;
+};
+
+&pcie1_ep {
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "core";
+
+ power-domains = <&gcc PCIE_1_GDSC>;
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ linux,pci-domain = <1>;
+};
+
+&pcie1_port0 {
+ phys = <&pcie1_phy>;
+};
+
+&pcieport0 {
+ phys = <&pcie0_phy>;
+};
+
+&qupv3_id_0 {
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+
+ i2c0: i2c@980000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c0_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi0: spi@980000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi0_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart0: serial@980000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart0_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c1: i2c@984000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c1_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi1: spi@984000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi1_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart1: serial@984000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart1_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c2: i2c@988000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c2_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi2: spi@988000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi2_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart2: serial@988000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart2_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c3: i2c@98c000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c3_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi3: spi@98c000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi3_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart3: serial@98c000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart3_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c4: i2c@990000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c4_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi4: spi@990000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi4_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart4: serial@990000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart4_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c5: i2c@994000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c5_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi5: spi@994000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi5_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart5: serial@994000 {
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+};
+
+&qupv3_id_1 {
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+
+ i2c7: i2c@a80000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c7_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi7: spi@a80000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi7_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart7: serial@a80000 {
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ };
+
+ i2c8: i2c@a84000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c8_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi8: spi@a84000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi8_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart8: serial@a84000 {
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-0 = <&qup_uart8_default>;
+ pinctrl-names = "default";
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ };
+
+ i2c9: i2c@a88000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c9_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi9: spi@a88000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi9_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart9: serial@a88000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c10: i2c@a8c000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c10_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi10: spi@a8c000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi10_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart10: serial@a8c000 {
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-0 = <&qup_uart10_default>;
+ pinctrl-names = "default";
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0
+ &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_QUP_1 0>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ };
+
+ i2c11: i2c@a90000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c11_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi11: spi@a90000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi11_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart11: serial@a90000 {
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-0 = <&qup_uart11_default>;
+ pinctrl-names = "default";
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ };
+
+ i2c12: i2c@a94000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c12_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi12: spi@a94000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi12_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart12: serial@a94000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart12_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c13: i2c@a98000 {
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c13_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+};
+
+&qupv3_id_2 {
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+
+ i2c14: i2c@880000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c14_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi14: spi@880000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi14_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart14: serial@880000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart14_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c15: i2c@884000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c15_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi15: spi@884000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi15_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart15: serial@884000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart15_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c16: i2c@888000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c16_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi16: spi@888000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi16_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart16: serial@888000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart16_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c17: i2c@88c000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c17_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi17: spi@88c000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi17_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart17: serial@88c000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart17_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c18: i2c@890000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c18_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi18: spi@890000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi18_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart18: serial@890000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart18_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c19: i2c@894000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c19_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi19: spi@894000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi19_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart19: serial@894000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart19_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ i2c20: i2c@898000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c20_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi20: spi@898000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi20_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart20: serial@898000 {
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart20_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+};
+
+&qupv3_id_3 {
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
+
+ i2c21: i2c@b80000 {
+ clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_i2c21_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ spi21: spi@b80000 {
+ clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_spi21_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ uart21: serial@b80000 {
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
+ interconnect-names = "qup-core", "qup-config";
+ pinctrl-0 = <&qup_uart21_default>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+ };
+};
+
+&remoteproc_adsp {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SA8775P_LCX>,
+ <&rpmhpd SA8775P_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0
+ &mc_virt SLAVE_EBI1 0>;
+
+};
+
+&remoteproc_cdsp0 {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SA8775P_CX>,
+ <&rpmhpd SA8775P_MXC>,
+ <&rpmhpd SA8775P_NSP0>;
+ power-domain-names = "cx", "mxc", "nsp";
+
+ interconnects = <&nspa_noc MASTER_CDSP_PROC 0
+ &mc_virt SLAVE_EBI1 0>;
+};
+
+&remoteproc_cdsp1 {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SA8775P_CX>,
+ <&rpmhpd SA8775P_MXC>,
+ <&rpmhpd SA8775P_NSP1>;
+ power-domain-names = "cx", "mxc", "nsp";
+
+ interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0
+ &mc_virt SLAVE_EBI1 0>;
+};
+
+&remoteproc_gpdsp0 {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SA8775P_CX>,
+ <&rpmhpd SA8775P_MXC>;
+ power-domain-names = "cx", "mxc";
+
+ interconnects = <&gpdsp_anoc MASTER_DSP0 0
+ &config_noc SLAVE_CLK_CTL 0>;
+};
+
+&remoteproc_gpdsp1 {
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SA8775P_CX>,
+ <&rpmhpd SA8775P_MXC>;
+ power-domain-names = "cx", "mxc";
+
+ interconnects = <&gpdsp_anoc MASTER_DSP1 0
+ &config_noc SLAVE_CLK_CTL 0>;
+};
+
+&sdhc {
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>;
+ clock-names = "iface",
+ "core";
+
+ interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ operating-points-v2 = <&sdhc_opp_table>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ resets = <&gcc GCC_SDCC1_BCR>;
+
+ sdhc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1800000 400000>;
+ opp-avg-kBps = <100000 0>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <390000 0>;
+ };
+ };
+};
+
+&soc {
+ gcc: clock-controller@100000 {
+ compatible = "qcom,sa8775p-gcc";
+ reg = <0x0 0x00100000 0x0 0xc7018>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <&usb_0_qmpphy>,
+ <&usb_1_qmpphy>,
+ <0>,
+ <0>,
+ <0>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ };
+
+ config_noc: interconnect@14c0000 {
+ compatible = "qcom,sa8775p-config-noc";
+ reg = <0x0 0x014c0000 0x0 0x13080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,sa8775p-system-noc";
+ reg = <0x0 0x01680000 0x0 0x15080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16c0000 {
+ compatible = "qcom,sa8775p-aggre1-noc";
+ reg = <0x0 0x016c0000 0x0 0x18080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,sa8775p-aggre2-noc";
+ reg = <0x0 0x01700000 0x0 0x1b080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
+ <&rpmhcc RPMH_IPA_CLK>;
+ };
+
+ pcie_anoc: interconnect@1760000 {
+ compatible = "qcom,sa8775p-pcie-anoc";
+ reg = <0x0 0x01760000 0x0 0xc080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpdsp_anoc: interconnect@1780000 {
+ compatible = "qcom,sa8775p-gpdsp-anoc";
+ reg = <0x0 0x01780000 0x0 0xe080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@17a0000 {
+ compatible = "qcom,sa8775p-mmss-noc";
+ reg = <0x0 0x017a0000 0x0 0x40000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ pcie0_phy: phy@1c04000 {
+ compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
+ reg = <0x0 0x1c04000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@1c14000 {
+ compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
+ reg = <0x0 0x1c14000 0x0 0x4000>;
+
+ clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sa8775p-qmp-ufs-phy";
+ reg = <0x0 0x01d87000 0x0 0xe10>;
+ /*
+ * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
+ * enables the CXO clock to eDP *and* UFS PHY.
+ */
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "ref", "ref_aux", "qref";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ ice: crypto@1d88000 {
+ compatible = "qcom,sa8775p-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x01d88000 0x0 0x18000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>;
+ clock-names = "core",
+ "iface";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ compatible = "qcom,sa8775p-lpass-ag-noc";
+ reg = <0x0 0x03c40000 0x0 0x17200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ usb_0_hsphy: phy@88e4000 {
+ compatible = "qcom,sa8775p-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e4000 0 0x120>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_1_hsphy: phy@88e6000 {
+ compatible = "qcom,sa8775p-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e6000 0 0x120>;
+ clocks = <&gcc GCC_USB_CLKREF_EN>;
+ clock-names = "ref";
+ resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy: phy@88e7000 {
+ compatible = "qcom,sa8775p-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e7000 0 0x120>;
+ clocks = <&gcc GCC_USB_CLKREF_EN>;
+ clock-names = "ref";
+ resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_0_qmpphy: phy@88e8000 {
+ compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
+ reg = <0 0x088e8000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_CLKREF_EN>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb3_prim_phy_pipe_clk_src";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_1_qmpphy: phy@88ea000 {
+ compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
+ reg = <0 0x088ea000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+ <&gcc GCC_USB_CLKREF_EN>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_SEC_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb3_sec_phy_pipe_clk_src";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ refgen: regulator@891c000 {
+ compatible = "qcom,sa8775p-refgen-regulator",
+ "qcom,sm8250-refgen-regulator";
+ reg = <0x0 0x0891c000 0x0 0x84>;
+ };
+
+ dc_noc: interconnect@90e0000 {
+ compatible = "qcom,sa8775p-dc-noc";
+ reg = <0x0 0x090e0000 0x0 0x5080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect@9100000 {
+ compatible = "qcom,sa8775p-gem-noc";
+ reg = <0x0 0x09100000 0x0 0xf6080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sa8775p-gpucc";
+ reg = <0x0 0x03d90000 0x0 0xa000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ serdes0: phy@8901000 {
+ compatible = "qcom,sa8775p-dwmac-sgmii-phy";
+ reg = <0x0 0x08901000 0x0 0xe10>;
+ clocks = <&gcc GCC_SGMI_CLKREF_EN>;
+ clock-names = "sgmi_ref";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ serdes1: phy@8902000 {
+ compatible = "qcom,sa8775p-dwmac-sgmii-phy";
+ reg = <0x0 0x08902000 0x0 0xe10>;
+ clocks = <&gcc GCC_SGMI_CLKREF_EN>;
+ clock-names = "sgmi_ref";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ videocc: clock-controller@abf0000 {
+ compatible = "qcom,sa8775p-videocc";
+ reg = <0x0 0x0abf0000 0x0 0x10000>;
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,sa8775p-camcc";
+ reg = <0x0 0x0ade0000 0x0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc0: clock-controller@af00000 {
+ compatible = "qcom,sa8775p-dispcc0";
+ reg = <0x0 0x0af00000 0x0 0x20000>;
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
+ <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
+ <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ apps_rsc: rsc@18200000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x18200000 0x0 0x10000>,
+ <0x0 0x18210000 0x0 0x10000>,
+ <0x0 0x18220000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 0>;
+ label = "apps_rsc";
+ power-domains = <&system_pd>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sa8775p-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board_clk>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sa8775p-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-0 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp-1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp-2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp-3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp-5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp-7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp-8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ epss_l3_cl0: interconnect@18590000 {
+ compatible = "qcom,sa8775p-epss-l3",
+ "qcom,epss-l3";
+ reg = <0x0 0x18590000 0x0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
+ epss_l3_cl1: interconnect@18592000 {
+ compatible = "qcom,sa8775p-epss-l3",
+ "qcom,epss-l3";
+ reg = <0x0 0x18592000 0x0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
+ dispcc1: clock-controller@22100000 {
+ compatible = "qcom,sa8775p-dispcc1";
+ reg = <0x0 0x22100000 0x0 0x20000>;
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
+ <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
+ <0>, <0>, <0>, <0>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ nspa_noc: interconnect@260c0000 {
+ compatible = "qcom,sa8775p-nspa-noc";
+ reg = <0x0 0x260c0000 0x0 0x16080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ nspb_noc: interconnect@2a0c0000 {
+ compatible = "qcom,sa8775p-nspb-noc";
+ reg = <0x0 0x2a0c0000 0x0 0x16080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+};
+
&tlmm {
dp0_hot_plug_det: dp0-hot-plug-det-state {
pins = "gpio101";
@@ -812,3 +3574,112 @@ data-pins {
};
};
};
+
+&ufs_mem_hc {
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ freq-table-hz = <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ qcom,ice = <&ice>;
+};
+
+&usb_0 {
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+};
+
+&usb_1 {
+ clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ power-domains = <&gcc USB30_SEC_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_SEC_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+};
+
+&usb_2 {
+ clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ power-domains = <&gcc USB20_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB20_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+};
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 7547042d8e85..821c86409c5d 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -4,23 +4,11 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
-#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
-#include <dt-bindings/clock/qcom,rpmh.h>
-#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
-#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
-#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
-#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
-#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
-#include <dt-bindings/interconnect/qcom,osm-l3.h>
-#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
-#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
-#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -29,18 +17,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
- clocks {
- xo_board_clk: xo-board-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
-
- sleep_clk: sleep-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
- };
-
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -57,11 +33,6 @@ cpu0: cpu@0 {
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
- operating-points-v2 = <&cpu0_opp_table>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&epss_l3_cl0 MASTER_EPSS_L3_APPS
- &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -87,11 +58,6 @@ cpu1: cpu@100 {
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
- operating-points-v2 = <&cpu0_opp_table>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&epss_l3_cl0 MASTER_EPSS_L3_APPS
- &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -112,11 +78,6 @@ cpu2: cpu@200 {
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
- operating-points-v2 = <&cpu0_opp_table>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&epss_l3_cl0 MASTER_EPSS_L3_APPS
- &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -137,11 +98,6 @@ cpu3: cpu@300 {
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
- operating-points-v2 = <&cpu0_opp_table>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&epss_l3_cl0 MASTER_EPSS_L3_APPS
- &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -162,11 +118,6 @@ cpu4: cpu@10000 {
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
- operating-points-v2 = <&cpu4_opp_table>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&epss_l3_cl1 MASTER_EPSS_L3_APPS
- &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -193,11 +144,6 @@ cpu5: cpu@10100 {
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
- operating-points-v2 = <&cpu4_opp_table>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&epss_l3_cl1 MASTER_EPSS_L3_APPS
- &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -218,11 +164,6 @@ cpu6: cpu@10200 {
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
- operating-points-v2 = <&cpu4_opp_table>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&epss_l3_cl1 MASTER_EPSS_L3_APPS
- &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -243,11 +184,6 @@ cpu7: cpu@10300 {
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
dynamic-power-coefficient = <100>;
- operating-points-v2 = <&cpu4_opp_table>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&epss_l3_cl1 MASTER_EPSS_L3_APPS
- &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -327,176 +263,6 @@ cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
};
};
- cpu0_opp_table: opp-table-cpu0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-1267200000 {
- opp-hz = /bits/ 64 <1267200000>;
- opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
- };
-
- opp-1363200000 {
- opp-hz = /bits/ 64 <1363200000>;
- opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
- };
-
- opp-1459200000 {
- opp-hz = /bits/ 64 <1459200000>;
- opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
- };
-
- opp-1536000000 {
- opp-hz = /bits/ 64 <1536000000>;
- opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
- };
-
- opp-1632000000 {
- opp-hz = /bits/ 64 <1632000000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-1708800000 {
- opp-hz = /bits/ 64 <1708800000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-1785600000 {
- opp-hz = /bits/ 64 <1785600000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-1862400000 {
- opp-hz = /bits/ 64 <1862400000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-1939200000 {
- opp-hz = /bits/ 64 <1939200000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-2016000000 {
- opp-hz = /bits/ 64 <2016000000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-2112000000 {
- opp-hz = /bits/ 64 <2112000000>;
- opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
- };
-
- opp-2188800000 {
- opp-hz = /bits/ 64 <2188800000>;
- opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
- };
-
- opp-2265600000 {
- opp-hz = /bits/ 64 <2265600000>;
- opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
- };
-
- opp-2361600000 {
- opp-hz = /bits/ 64 <2361600000>;
- opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
- };
-
- opp-2457600000 {
- opp-hz = /bits/ 64 <2457600000>;
- opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
- };
-
- opp-2553600000 {
- opp-hz = /bits/ 64 <2553600000>;
- opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
- };
- };
-
- cpu4_opp_table: opp-table-cpu4 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-1267200000 {
- opp-hz = /bits/ 64 <1267200000>;
- opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
- };
-
- opp-1363200000 {
- opp-hz = /bits/ 64 <1363200000>;
- opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
- };
-
- opp-1459200000 {
- opp-hz = /bits/ 64 <1459200000>;
- opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
- };
-
- opp-1536000000 {
- opp-hz = /bits/ 64 <1536000000>;
- opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
- };
-
- opp-1632000000 {
- opp-hz = /bits/ 64 <1632000000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-1708800000 {
- opp-hz = /bits/ 64 <1708800000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-1785600000 {
- opp-hz = /bits/ 64 <1785600000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-1862400000 {
- opp-hz = /bits/ 64 <1862400000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-1939200000 {
- opp-hz = /bits/ 64 <1939200000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-2016000000 {
- opp-hz = /bits/ 64 <2016000000>;
- opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
- };
-
- opp-2112000000 {
- opp-hz = /bits/ 64 <2112000000>;
- opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
- };
-
- opp-2188800000 {
- opp-hz = /bits/ 64 <2188800000>;
- opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
- };
-
- opp-2265600000 {
- opp-hz = /bits/ 64 <2265600000>;
- opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
- };
-
- opp-2361600000 {
- opp-hz = /bits/ 64 <2361600000>;
- opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
- };
-
- opp-2457600000 {
- opp-hz = /bits/ 64 <2457600000>;
- opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
- };
-
- opp-2553600000 {
- opp-hz = /bits/ 64 <2553600000>;
- opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
- };
- };
-
dummy-sink {
compatible = "arm,coresight-dummy-sink";
@@ -518,33 +284,12 @@ scm {
};
};
- clk_virt: interconnect-clk-virt {
- compatible = "qcom,sa8775p-clk-virt";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- mc_virt: interconnect-mc-virt {
- compatible = "qcom,sa8775p-mc-virt";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
/* Will be updated by the bootloader. */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x0>;
};
- qup_opp_table_100mhz: opp-table-qup100mhz {
- compatible = "operating-points-v2";
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
- };
-
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -985,30 +730,6 @@ soc: soc@0 {
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
- gcc: clock-controller@100000 {
- compatible = "qcom,sa8775p-gcc";
- reg = <0x0 0x00100000 0x0 0xc7018>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&sleep_clk>,
- <0>,
- <0>,
- <0>,
- <&usb_0_qmpphy>,
- <&usb_1_qmpphy>,
- <0>,
- <0>,
- <0>,
- <&pcie0_phy>,
- <&pcie1_phy>,
- <0>,
- <0>,
- <0>;
- power-domains = <&rpmhpd SA8775P_CX>;
- };
-
ipcc: mailbox@408000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x00408000 0x0 0x1000>;
@@ -1056,9 +777,6 @@ qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
ranges;
- clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
- <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
- clock-names = "m-ahb", "s-ahb";
iommus = <&apps_smmu 0x5a3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
@@ -1070,20 +788,6 @@ i2c14: i2c@880000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c14_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1097,20 +801,6 @@ spi14: spi@880000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi14_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1122,16 +812,6 @@ uart14: serial@880000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart14_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1141,20 +821,6 @@ i2c15: i2c@884000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c15_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1168,20 +834,6 @@ spi15: spi@884000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi15_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1193,16 +845,6 @@ uart15: serial@884000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart15_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1212,20 +854,6 @@ i2c16: i2c@888000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c16_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1237,20 +865,6 @@ spi16: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi16_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1264,16 +878,6 @@ uart16: serial@888000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart16_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1283,20 +887,6 @@ i2c17: i2c@88c000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c17_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1310,20 +900,6 @@ spi17: spi@88c000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi17_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1335,16 +911,6 @@ uart17: serial@88c000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart17_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1352,20 +918,6 @@ i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c18_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1381,20 +933,6 @@ spi18: spi@890000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi18_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1406,16 +944,6 @@ uart18: serial@890000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart18_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1425,20 +953,6 @@ i2c19: i2c@894000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c19_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1452,20 +966,6 @@ spi19: spi@894000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi19_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1477,16 +977,6 @@ uart19: serial@894000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart19_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1496,20 +986,6 @@ i2c20: i2c@898000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c20_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
<&gpi_dma2 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1523,20 +999,6 @@ spi20: spi@898000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi20_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
<&gpi_dma2 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1548,16 +1010,6 @@ uart20: serial@898000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart20_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1591,9 +1043,6 @@ qupv3_id_0: geniqup@9c0000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- clock-names = "m-ahb", "s-ahb";
- clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
- <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0x403 0x0>;
status = "disabled";
@@ -1603,20 +1052,6 @@ i2c0: i2c@980000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c0_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1630,20 +1065,6 @@ spi0: spi@980000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi0_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1655,16 +1076,6 @@ uart0: serial@980000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x980000 0x0 0x4000>;
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart0_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1674,20 +1085,6 @@ i2c1: i2c@984000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c1_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1701,20 +1098,6 @@ spi1: spi@984000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi1_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1726,16 +1109,6 @@ uart1: serial@984000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x984000 0x0 0x4000>;
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart1_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1745,20 +1118,6 @@ i2c2: i2c@988000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c2_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1772,20 +1131,6 @@ spi2: spi@988000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi2_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1797,16 +1142,6 @@ uart2: serial@988000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x988000 0x0 0x4000>;
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart2_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1816,20 +1151,6 @@ i2c3: i2c@98c000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c3_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1843,20 +1164,6 @@ spi3: spi@98c000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi3_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1868,16 +1175,6 @@ uart3: serial@98c000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x98c000 0x0 0x4000>;
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart3_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1887,20 +1184,6 @@ i2c4: i2c@990000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c4_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1914,20 +1197,6 @@ spi4: spi@990000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi4_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1939,16 +1208,6 @@ uart4: serial@990000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x990000 0x0 0x4000>;
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart4_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1958,20 +1217,6 @@ i2c5: i2c@994000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c5_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1985,20 +1230,6 @@ spi5: spi@994000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi5_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2010,16 +1241,6 @@ uart5: serial@994000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x994000 0x0 0x4000>;
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart5_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
};
@@ -2052,9 +1273,6 @@ qupv3_id_1: geniqup@ac0000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- clock-names = "m-ahb", "s-ahb";
- clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
- <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x443 0x0>;
status = "disabled";
@@ -2064,20 +1282,6 @@ i2c7: i2c@a80000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c7_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2091,20 +1295,6 @@ spi7: spi@a80000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi7_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2116,17 +1306,6 @@ uart7: serial@a80000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "se";
- clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
- pinctrl-0 = <&qup_uart7_default>;
- pinctrl-names = "default";
- interconnect-names = "qup-core", "qup-config";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
- power-domains = <&rpmhpd SA8775P_CX>;
- operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
@@ -2136,20 +1315,6 @@ i2c8: i2c@a84000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c8_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2163,20 +1328,6 @@ spi8: spi@a84000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi8_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2188,17 +1339,6 @@ uart8: serial@a84000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "se";
- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
- pinctrl-0 = <&qup_uart8_default>;
- pinctrl-names = "default";
- interconnect-names = "qup-core", "qup-config";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
- power-domains = <&rpmhpd SA8775P_CX>;
- operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
@@ -2208,20 +1348,6 @@ i2c9: i2c@a88000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c9_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2235,20 +1361,6 @@ spi9: spi@a88000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi9_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2260,16 +1372,6 @@ uart9: serial@a88000 {
compatible = "qcom,geni-uart";
reg = <0x0 0xa88000 0x0 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart9_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -2279,20 +1381,6 @@ i2c10: i2c@a8c000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c10_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2306,20 +1394,6 @@ spi10: spi@a8c000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi10_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2331,17 +1405,6 @@ uart10: serial@a8c000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "se";
- clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
- pinctrl-0 = <&qup_uart10_default>;
- pinctrl-names = "default";
- interconnect-names = "qup-core", "qup-config";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 0
- &clk_virt SLAVE_QUP_CORE_1 0>,
- <&gem_noc MASTER_APPSS_PROC 0
- &config_noc SLAVE_QUP_1 0>;
- power-domains = <&rpmhpd SA8775P_CX>;
- operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
@@ -2351,20 +1414,6 @@ i2c11: i2c@a90000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c11_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2378,20 +1427,6 @@ spi11: spi@a90000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi11_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2403,17 +1438,6 @@ uart11: serial@a90000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "se";
- clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
- pinctrl-0 = <&qup_uart11_default>;
- pinctrl-names = "default";
- interconnect-names = "qup-core", "qup-config";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
- power-domains = <&rpmhpd SA8775P_CX>;
- operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
@@ -2423,20 +1447,6 @@ i2c12: i2c@a94000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c12_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2450,20 +1460,6 @@ spi12: spi@a94000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi12_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2475,16 +1471,6 @@ uart12: serial@a94000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_uart12_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core", "qup-config";
- power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -2494,20 +1480,6 @@ i2c13: i2c@a98000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c13_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
- <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2537,9 +1509,6 @@ qupv3_id_3: geniqup@bc0000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
- clock-names = "m-ahb", "s-ahb";
- clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
- <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
iommus = <&apps_smmu 0x43 0x0>;
status = "disabled";
@@ -2549,20 +1518,6 @@ i2c21: i2c@b80000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_i2c21_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
- <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>,
<&gpi_dma3 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2576,20 +1531,6 @@ spi21: spi@b80000 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
- clock-names = "se";
- pinctrl-0 = <&qup_spi21_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
- <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "qup-core",
- "qup-config",
- "qup-memory";
- power-domains = <&rpmhpd SA8775P_CX>;
dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>,
<&gpi_dma3 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2601,17 +1542,6 @@ uart21: serial@b80000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00b80000 0x0 0x4000>;
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "se";
- clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
- interconnect-names = "qup-core", "qup-config";
- pinctrl-0 = <&qup_uart21_default>;
- pinctrl-names = "default";
- interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
- &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>;
- power-domains = <&rpmhpd SA8775P_CX>;
- operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
};
@@ -2621,62 +1551,6 @@ rng: rng@10d2000 {
reg = <0 0x010d2000 0 0x1000>;
};
- config_noc: interconnect@14c0000 {
- compatible = "qcom,sa8775p-config-noc";
- reg = <0x0 0x014c0000 0x0 0x13080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- system_noc: interconnect@1680000 {
- compatible = "qcom,sa8775p-system-noc";
- reg = <0x0 0x01680000 0x0 0x15080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- aggre1_noc: interconnect@16c0000 {
- compatible = "qcom,sa8775p-aggre1-noc";
- reg = <0x0 0x016c0000 0x0 0x18080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
- <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
- };
-
- aggre2_noc: interconnect@1700000 {
- compatible = "qcom,sa8775p-aggre2-noc";
- reg = <0x0 0x01700000 0x0 0x1b080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
- <&rpmhcc RPMH_IPA_CLK>;
- };
-
- pcie_anoc: interconnect@1760000 {
- compatible = "qcom,sa8775p-pcie-anoc";
- reg = <0x0 0x01760000 0x0 0xc080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- gpdsp_anoc: interconnect@1780000 {
- compatible = "qcom,sa8775p-gpdsp-anoc";
- reg = <0x0 0x01780000 0x0 0xe080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- mmss_noc: interconnect@17a0000 {
- compatible = "qcom,sa8775p-mmss-noc";
- reg = <0x0 0x017a0000 0x0 0x40000>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c00000 0x0 0x3000>,
@@ -2696,7 +1570,6 @@ pcie0: pcie@1c00000 {
dma-coherent;
- linux,pci-domain = <0>;
num-lanes = <2>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
@@ -2724,35 +1597,9 @@ pcie0: pcie@1c00000 {
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
- <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
-
- clock-names = "aux",
- "cfg",
- "bus_master",
- "bus_slave",
- "slave_q2a";
-
- assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
- assigned-clock-rates = <19200000>;
-
- interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
- interconnect-names = "pcie-mem", "cpu-pcie";
-
iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>,
<0x100 &pcie_smmu 0x0001 0x0 0x1>;
- resets = <&gcc GCC_PCIE_0_BCR>,
- <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
- reset-names = "pci",
- "link_down";
-
- power-domains = <&gcc PCIE_0_GDSC>;
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55>;
@@ -2764,8 +1611,6 @@ pcieport0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
- phys = <&pcie0_phy>;
-
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2783,69 +1628,15 @@ pcie0_ep: pcie-ep@1c00000 {
<0x0 0x40005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
"mmio", "dma";
-
- clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
- <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
-
- clock-names = "aux",
- "cfg",
- "bus_master",
- "bus_slave",
- "slave_q2a";
-
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell", "dma";
- interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
- interconnect-names = "pcie-mem", "cpu-pcie";
-
dma-coherent;
iommus = <&pcie_smmu 0x0000 0x7f>;
- resets = <&gcc GCC_PCIE_0_BCR>;
- reset-names = "core";
- power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
num-lanes = <2>;
- linux,pci-domain = <0>;
-
- status = "disabled";
- };
-
- pcie0_phy: phy@1c04000 {
- compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
- reg = <0x0 0x1c04000 0x0 0x2000>;
-
- clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
- <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_CLKREF_EN>,
- <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
- <&gcc GCC_PCIE_0_PIPE_CLK>,
- <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
- clock-names = "aux",
- "cfg_ahb",
- "ref",
- "rchng",
- "pipe",
- "pipediv2";
-
- assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
- assigned-clock-rates = <100000000>;
-
- resets = <&gcc GCC_PCIE_0_PHY_BCR>;
- reset-names = "phy";
-
- #clock-cells = <0>;
- clock-output-names = "pcie_0_pipe_clk";
-
- #phy-cells = <0>;
status = "disabled";
};
@@ -2869,7 +1660,6 @@ pcie1: pcie@1c10000 {
dma-coherent;
- linux,pci-domain = <1>;
num-lanes = <4>;
interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
@@ -2897,35 +1687,9 @@ pcie1: pcie@1c10000 {
<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
- <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
- <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
-
- clock-names = "aux",
- "cfg",
- "bus_master",
- "bus_slave",
- "slave_q2a";
-
- assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
- assigned-clock-rates = <19200000>;
-
- interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
- interconnect-names = "pcie-mem", "cpu-pcie";
-
iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>,
<0x100 &pcie_smmu 0x0081 0x0 0x1>;
- resets = <&gcc GCC_PCIE_1_BCR>,
- <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
- reset-names = "pci",
- "link_down";
-
- power-domains = <&gcc PCIE_1_GDSC>;
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
@@ -2936,8 +1700,6 @@ pcie1_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
- phys = <&pcie1_phy>;
-
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2956,68 +1718,15 @@ pcie1_ep: pcie-ep@1c10000 {
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
"mmio", "dma";
- clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
- <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
- <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
-
- clock-names = "aux",
- "cfg",
- "bus_master",
- "bus_slave",
- "slave_q2a";
-
interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell", "dma";
- interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
- interconnect-names = "pcie-mem", "cpu-pcie";
-
dma-coherent;
iommus = <&pcie_smmu 0x80 0x7f>;
- resets = <&gcc GCC_PCIE_1_BCR>;
- reset-names = "core";
- power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
num-lanes = <4>;
- linux,pci-domain = <1>;
-
- status = "disabled";
- };
-
- pcie1_phy: phy@1c14000 {
- compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
- reg = <0x0 0x1c14000 0x0 0x4000>;
-
- clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
- <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_CLKREF_EN>,
- <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
- <&gcc GCC_PCIE_1_PIPE_CLK>,
- <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
- clock-names = "aux",
- "cfg_ahb",
- "ref",
- "rchng",
- "pipe",
- "pipediv2";
-
- assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
- assigned-clock-rates = <100000000>;
-
- resets = <&gcc GCC_PCIE_1_PHY_BCR>;
- reset-names = "phy";
-
- #clock-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk";
-
- #phy-cells = <0>;
status = "disabled";
};
@@ -3026,73 +1735,12 @@ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy>;
- phy-names = "ufsphy";
lanes-per-direction = <2>;
- #reset-cells = <1>;
- resets = <&gcc GCC_UFS_PHY_BCR>;
- reset-names = "rst";
- power-domains = <&gcc UFS_PHY_GDSC>;
- required-opps = <&rpmhpd_opp_nom>;
iommus = <&apps_smmu 0x100 0x0>;
dma-coherent;
- clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
- <&gcc GCC_UFS_PHY_AHB_CLK>,
- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- clock-names = "core_clk",
- "bus_aggr_clk",
- "iface_clk",
- "core_clk_unipro",
- "ref_clk",
- "tx_lane0_sync_clk",
- "rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
- freq-table-hz = <75000000 300000000>,
- <0 0>,
- <0 0>,
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
- qcom,ice = <&ice>;
status = "disabled";
};
- ufs_mem_phy: phy@1d87000 {
- compatible = "qcom,sa8775p-qmp-ufs-phy";
- reg = <0x0 0x01d87000 0x0 0xe10>;
- /*
- * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
- * enables the CXO clock to eDP *and* UFS PHY.
- */
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
- <&gcc GCC_EDP_REF_CLKREF_EN>;
- clock-names = "ref", "ref_aux", "qref";
- power-domains = <&gcc UFS_PHY_GDSC>;
- resets = <&ufs_mem_hc 0>;
- reset-names = "ufsphy";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- ice: crypto@1d88000 {
- compatible = "qcom,sa8775p-inline-crypto-engine",
- "qcom,inline-crypto-engine";
- reg = <0x0 0x01d88000 0x0 0x18000>;
- clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
- <&gcc GCC_UFS_PHY_AHB_CLK>;
- clock-names = "core",
- "iface";
- power-domains = <&gcc UFS_PHY_GDSC>;
- };
-
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
@@ -3113,16 +1761,6 @@ crypto: crypto@1dfa000 {
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x480 0x0>,
<&apps_smmu 0x481 0x0>;
- interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "memory";
- };
-
- lpass_ag_noc: interconnect@3c40000 {
- compatible = "qcom,sa8775p-lpass-ag-noc";
- reg = <0x0 0x03c40000 0x0 0x17200>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
};
ctcu@4001000 {
@@ -4305,171 +2943,19 @@ sdhc: mmc@87c4000 {
interrupt-names = "hc_irq",
"pwr_irq";
- clocks = <&gcc GCC_SDCC1_AHB_CLK>,
- <&gcc GCC_SDCC1_APPS_CLK>;
- clock-names = "iface",
- "core";
-
- interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>;
- interconnect-names = "sdhc-ddr",
- "cpu-sdhc";
-
iommus = <&apps_smmu 0x0 0x0>;
dma-coherent;
- operating-points-v2 = <&sdhc_opp_table>;
- power-domains = <&rpmhpd SA8775P_CX>;
- resets = <&gcc GCC_SDCC1_BCR>;
-
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
status = "disabled";
-
- sdhc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <1800000 400000>;
- opp-avg-kBps = <100000 0>;
- };
-
- opp-384000000 {
- opp-hz = /bits/ 64 <384000000>;
- required-opps = <&rpmhpd_opp_nom>;
- opp-peak-kBps = <5400000 1600000>;
- opp-avg-kBps = <390000 0>;
- };
- };
- };
-
- usb_0_hsphy: phy@88e4000 {
- compatible = "qcom,sa8775p-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e4000 0 0x120>;
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_1_hsphy: phy@88e6000 {
- compatible = "qcom,sa8775p-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e6000 0 0x120>;
- clocks = <&gcc GCC_USB_CLKREF_EN>;
- clock-names = "ref";
- resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy: phy@88e7000 {
- compatible = "qcom,sa8775p-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e7000 0 0x120>;
- clocks = <&gcc GCC_USB_CLKREF_EN>;
- clock-names = "ref";
- resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_0_qmpphy: phy@88e8000 {
- compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
- reg = <0 0x088e8000 0 0x2000>;
-
- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
- <&gcc GCC_USB_CLKREF_EN>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "aux", "ref", "com_aux", "pipe";
-
- resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
- <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
- reset-names = "phy", "phy_phy";
-
- power-domains = <&gcc USB30_PRIM_GDSC>;
-
- #clock-cells = <0>;
- clock-output-names = "usb3_prim_phy_pipe_clk_src";
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_1_qmpphy: phy@88ea000 {
- compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
- reg = <0 0x088ea000 0 0x2000>;
-
- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&gcc GCC_USB_CLKREF_EN>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
- <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "aux", "ref", "com_aux", "pipe";
-
- resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
- <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
- reset-names = "phy", "phy_phy";
-
- power-domains = <&gcc USB30_SEC_GDSC>;
-
- #clock-cells = <0>;
- clock-output-names = "usb3_sec_phy_pipe_clk_src";
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- refgen: regulator@891c000 {
- compatible = "qcom,sa8775p-refgen-regulator",
- "qcom,sm8250-refgen-regulator";
- reg = <0x0 0x0891c000 0x0 0x84>;
- };
-
- dc_noc: interconnect@90e0000 {
- compatible = "qcom,sa8775p-dc-noc";
- reg = <0x0 0x090e0000 0x0 0x5080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- gem_noc: interconnect@9100000 {
- compatible = "qcom,sa8775p-gem-noc";
- reg = <0x0 0x09100000 0x0 0xf6080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
};
usb_0: usb@a600000 {
compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a600000 0 0xfc100>;
- clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_USB30_PRIM_MASTER_CLK>,
- <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
- clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
-
- assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_PRIM_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <200000000>;
-
interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
@@ -4483,20 +2969,9 @@ usb_0: usb@a600000 {
"dm_hs_phy_irq",
"ss_phy_irq";
- power-domains = <&gcc USB30_PRIM_GDSC>;
- required-opps = <&rpmhpd_opp_nom>;
-
- resets = <&gcc GCC_USB30_PRIM_BCR>;
-
- interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
- interconnect-names = "usb-ddr", "apps-usb";
-
wakeup-source;
iommus = <&apps_smmu 0x080 0x0>;
- phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
- phy-names = "usb2-phy", "usb3-phy";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
@@ -4527,17 +3002,6 @@ usb_1: usb@a800000 {
compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a800000 0 0xfc100>;
- clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
- <&gcc GCC_USB30_SEC_MASTER_CLK>,
- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
- <&gcc GCC_USB30_SEC_SLEEP_CLK>,
- <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
- clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
-
- assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_SEC_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <200000000>;
-
interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
@@ -4551,20 +3015,9 @@ usb_1: usb@a800000 {
"dm_hs_phy_irq",
"ss_phy_irq";
- power-domains = <&gcc USB30_SEC_GDSC>;
- required-opps = <&rpmhpd_opp_nom>;
-
- resets = <&gcc GCC_USB30_SEC_BCR>;
-
- interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
- interconnect-names = "usb-ddr", "apps-usb";
-
wakeup-source;
iommus = <&apps_smmu 0x0a0 0x0>;
- phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
- phy-names = "usb2-phy", "usb3-phy";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
@@ -4575,17 +3028,6 @@ usb_2: usb@a400000 {
compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a400000 0 0xfc100>;
- clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
- <&gcc GCC_USB20_MASTER_CLK>,
- <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
- <&gcc GCC_USB20_SLEEP_CLK>,
- <&gcc GCC_USB20_MOCK_UTMI_CLK>;
- clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
-
- assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
- <&gcc GCC_USB20_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <200000000>;
-
interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
@@ -4597,21 +3039,10 @@ usb_2: usb@a400000 {
"dp_hs_phy_irq",
"dm_hs_phy_irq";
- power-domains = <&gcc USB20_PRIM_GDSC>;
- required-opps = <&rpmhpd_opp_nom>;
-
- resets = <&gcc GCC_USB20_PRIM_BCR>;
-
- interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
- interconnect-names = "usb-ddr", "apps-usb";
-
qcom,select-utmi-as-pipe-clk;
wakeup-source;
iommus = <&apps_smmu 0x020 0x0>;
- phys = <&usb_2_hsphy>;
- phy-names = "usb2-phy";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
@@ -4647,11 +3078,7 @@ gpu: gpu@3d00000 {
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0 0xc00>,
<&adreno_smmu 1 0xc00>;
- operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
- interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "gfx-mem";
#cooling-cells = <2>;
nvmem-cells = <&gpu_speed_bin>;
@@ -4662,49 +3089,9 @@ gpu: gpu@3d00000 {
gpu_zap_shader: zap-shader {
memory-region = <&pil_gpu_mem>;
};
-
- gpu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-405000000 {
- opp-hz = /bits/ 64 <405000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
- opp-peak-kBps = <5285156>;
- opp-supported-hw = <0x3>;
- };
-
- opp-530000000 {
- opp-hz = /bits/ 64 <530000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
- opp-peak-kBps = <12484375>;
- opp-supported-hw = <0x2>;
- };
-
- opp-676000000 {
- opp-hz = /bits/ 64 <676000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
- opp-peak-kBps = <8171875>;
- opp-supported-hw = <0x1>;
- };
-
- opp-778000000 {
- opp-hz = /bits/ 64 <778000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
- opp-peak-kBps = <10687500>;
- opp-supported-hw = <0x1>;
- };
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
- opp-peak-kBps = <12484375>;
- opp-supported-hw = <0x1>;
- };
- };
};
gmu: gmu@3d6a000 {
- compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu";
reg = <0x0 0x03d6a000 0x0 0x34000>,
<0x0 0x03de0000 0x0 0x10000>,
<0x0 0x0b290000 0x0 0x10000>;
@@ -4712,49 +3099,7 @@ gmu: gmu@3d6a000 {
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
- clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
- <&gpucc GPU_CC_CXO_CLK>,
- <&gcc GCC_DDRSS_GPU_AXI_CLK>,
- <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
- <&gpucc GPU_CC_AHB_CLK>,
- <&gpucc GPU_CC_HUB_CX_INT_CLK>,
- <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
- clock-names = "gmu",
- "cxo",
- "axi",
- "memnoc",
- "ahb",
- "hub",
- "smmu_vote";
- power-domains = <&gpucc GPU_CC_CX_GDSC>,
- <&gpucc GPU_CC_GX_GDSC>;
- power-domain-names = "cx",
- "gx";
iommus = <&adreno_smmu 5 0xc00>;
- operating-points-v2 = <&gmu_opp_table>;
-
- gmu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
- };
- };
- };
-
- gpucc: clock-controller@3d90000 {
- compatible = "qcom,sa8775p-gpucc";
- reg = <0x0 0x03d90000 0x0 0xa000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_GPU_GPLL0_CLK_SRC>,
- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
- clock-names = "bi_tcxo",
- "gcc_gpu_gpll0_clk_src",
- "gcc_gpu_gpll0_div_clk_src";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
};
adreno_smmu: iommu@3da0000 {
@@ -4764,21 +3109,6 @@ adreno_smmu: iommu@3da0000 {
#iommu-cells = <2>;
#global-interrupts = <2>;
dma-coherent;
- power-domains = <&gpucc GPU_CC_CX_GDSC>;
- clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
- <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
- <&gpucc GPU_CC_AHB_CLK>,
- <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
- <&gpucc GPU_CC_CX_GMU_CLK>,
- <&gpucc GPU_CC_HUB_CX_INT_CLK>,
- <&gpucc GPU_CC_HUB_AON_CLK>;
- clock-names = "gcc_gpu_memnoc_gfx_clk",
- "gcc_gpu_snoc_dvm_gfx_clk",
- "gpu_cc_ahb_clk",
- "gpu_cc_hlos1_vote_gpu_smmu_clk",
- "gpu_cc_cx_gmu_clk",
- "gpu_cc_hub_cx_int_clk",
- "gpu_cc_hub_aon_clk";
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
@@ -4793,30 +3123,9 @@ adreno_smmu: iommu@3da0000 {
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
};
- serdes0: phy@8901000 {
- compatible = "qcom,sa8775p-dwmac-sgmii-phy";
- reg = <0x0 0x08901000 0x0 0xe10>;
- clocks = <&gcc GCC_SGMI_CLKREF_EN>;
- clock-names = "sgmi_ref";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- serdes1: phy@8902000 {
- compatible = "qcom,sa8775p-dwmac-sgmii-phy";
- reg = <0x0 0x08902000 0x0 0xe10>;
- clocks = <&gcc GCC_SGMI_CLKREF_EN>;
- clock-names = "sgmi_ref";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- pmu@9091000 {
- compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ llcc_bwmon: pmu@9091000 {
reg = <0x0 0x9091000 0x0 0x1000>;
interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
- interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&llcc_bwmon_opp_table>;
@@ -4865,12 +3174,9 @@ opp-9 {
};
};
- pmu@90b5400 {
- compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
+ cpu_bwmon0: pmu@90b5400 {
reg = <0x0 0x90b5400 0x0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
@@ -4893,15 +3199,11 @@ opp-3 {
opp-peak-kBps = <16265000>;
};
};
-
};
- pmu@90b6400 {
- compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
+ cpu_bwmon1: pmu@90b6400 {
reg = <0x0 0x90b6400 0x0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
};
@@ -4931,102 +3233,20 @@ iris: video-codec@aa00000 {
reg = <0x0 0x0aa00000 0x0 0xf0000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
- <&videocc VIDEO_CC_MVS0_GDSC>,
- <&rpmhpd SA8775P_MX>,
- <&rpmhpd SA8775P_MMCX>;
- power-domain-names = "venus",
- "vcodec0",
- "mxc",
- "mmcx";
- operating-points-v2 = <&iris_opp_table>;
-
- clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
- <&videocc VIDEO_CC_MVS0C_CLK>,
- <&videocc VIDEO_CC_MVS0_CLK>;
- clock-names = "iface",
- "core",
- "vcodec0_core";
-
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "cpu-cfg",
- "video-mem";
-
memory-region = <&pil_video_mem>;
- resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
- reset-names = "bus";
-
iommus = <&apps_smmu 0x0880 0x0400>,
<&apps_smmu 0x0887 0x0400>;
dma-coherent;
status = "disabled";
-
- iris_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-366000000 {
- opp-hz = /bits/ 64 <366000000>;
- required-opps = <&rpmhpd_opp_svs_l1>,
- <&rpmhpd_opp_svs_l1>;
- };
-
- opp-444000000 {
- opp-hz = /bits/ 64 <444000000>;
- required-opps = <&rpmhpd_opp_svs_l1>,
- <&rpmhpd_opp_nom>;
- };
-
- opp-533000000 {
- opp-hz = /bits/ 64 <533000000>;
- required-opps = <&rpmhpd_opp_nom>,
- <&rpmhpd_opp_turbo>;
- };
-
- opp-560000000 {
- opp-hz = /bits/ 64 <560000000>;
- required-opps = <&rpmhpd_opp_nom>,
- <&rpmhpd_opp_turbo_l1>;
- };
- };
- };
-
- videocc: clock-controller@abf0000 {
- compatible = "qcom,sa8775p-videocc";
- reg = <0x0 0x0abf0000 0x0 0x10000>;
- clocks = <&gcc GCC_VIDEO_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&rpmhcc RPMH_CXO_CLK_A>,
- <&sleep_clk>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
};
cci0: cci@ac13000 {
compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac13000 0x0 0x1000>;
-
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
- power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
-
- clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
- <&camcc CAM_CC_CPAS_AHB_CLK>,
- <&camcc CAM_CC_CCI_0_CLK>;
- clock-names = "camnoc_axi",
- "cpas_ahb",
- "cci";
-
- pinctrl-0 = <&cci0_0_default &cci0_1_default>;
- pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
- pinctrl-names = "default", "sleep";
-
#address-cells = <1>;
#size-cells = <0>;
@@ -5050,22 +3270,8 @@ cci0_i2c1: i2c-bus@1 {
cci1: cci@ac14000 {
compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac14000 0x0 0x1000>;
-
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
- power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
-
- clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
- <&camcc CAM_CC_CPAS_AHB_CLK>,
- <&camcc CAM_CC_CCI_1_CLK>;
- clock-names = "camnoc_axi",
- "cpas_ahb",
- "cci";
-
- pinctrl-0 = <&cci1_0_default &cci1_1_default>;
- pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
- pinctrl-names = "default", "sleep";
-
#address-cells = <1>;
#size-cells = <0>;
@@ -5089,22 +3295,8 @@ cci1_i2c1: i2c-bus@1 {
cci2: cci@ac15000 {
compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac15000 0x0 0x1000>;
-
interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
- power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
-
- clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
- <&camcc CAM_CC_CPAS_AHB_CLK>,
- <&camcc CAM_CC_CCI_2_CLK>;
- clock-names = "camnoc_axi",
- "cpas_ahb",
- "cci";
-
- pinctrl-0 = <&cci2_0_default &cci2_1_default>;
- pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
- pinctrl-names = "default", "sleep";
-
#address-cells = <1>;
#size-cells = <0>;
@@ -5128,22 +3320,8 @@ cci2_i2c1: i2c-bus@1 {
cci3: cci@ac16000 {
compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac16000 0x0 0x1000>;
-
interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>;
- power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
-
- clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
- <&camcc CAM_CC_CPAS_AHB_CLK>,
- <&camcc CAM_CC_CCI_3_CLK>;
- clock-names = "camnoc_axi",
- "cpas_ahb",
- "cci";
-
- pinctrl-0 = <&cci3_0_default &cci3_1_default>;
- pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>;
- pinctrl-names = "default", "sleep";
-
#address-cells = <1>;
#size-cells = <0>;
@@ -5212,63 +3390,6 @@ camss: isp@ac78000 {
"vfe_lite3",
"vfe_lite4";
- clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
- <&camcc CAM_CC_CORE_AHB_CLK>,
- <&camcc CAM_CC_CPAS_AHB_CLK>,
- <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
- <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
- <&camcc CAM_CC_CPAS_IFE_0_CLK>,
- <&camcc CAM_CC_CPAS_IFE_1_CLK>,
- <&camcc CAM_CC_CSID_CLK>,
- <&camcc CAM_CC_CSIPHY0_CLK>,
- <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
- <&camcc CAM_CC_CSIPHY1_CLK>,
- <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
- <&camcc CAM_CC_CSIPHY2_CLK>,
- <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
- <&camcc CAM_CC_CSIPHY3_CLK>,
- <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
- <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
- <&gcc GCC_CAMERA_HF_AXI_CLK>,
- <&gcc GCC_CAMERA_SF_AXI_CLK>,
- <&camcc CAM_CC_ICP_AHB_CLK>,
- <&camcc CAM_CC_IFE_0_CLK>,
- <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
- <&camcc CAM_CC_IFE_1_CLK>,
- <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
- <&camcc CAM_CC_IFE_LITE_CLK>,
- <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
- <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
- <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
- clock-names = "camnoc_axi",
- "core_ahb",
- "cpas_ahb",
- "cpas_fast_ahb_clk",
- "cpas_vfe_lite",
- "cpas_vfe0",
- "cpas_vfe1",
- "csid",
- "csiphy0",
- "csiphy0_timer",
- "csiphy1",
- "csiphy1_timer",
- "csiphy2",
- "csiphy2_timer",
- "csiphy3",
- "csiphy3_timer",
- "csiphy_rx",
- "gcc_axi_hf",
- "gcc_axi_sf",
- "icp_ahb",
- "vfe0",
- "vfe0_fast_ahb",
- "vfe1",
- "vfe1_fast_ahb",
- "vfe_lite",
- "vfe_lite_ahb",
- "vfe_lite_cphy_rx",
- "vfe_lite_csid";
-
interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
@@ -5312,18 +3433,8 @@ camss: isp@ac78000 {
"vfe_lite3",
"vfe_lite4";
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
- <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "ahb",
- "hf_0";
-
iommus = <&apps_smmu 0x3400 0x20>;
- power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
- power-domain-names = "top";
-
status = "disabled";
ports {
@@ -5348,43 +3459,11 @@ port@3 {
};
};
- camcc: clock-controller@ade0000 {
- compatible = "qcom,sa8775p-camcc";
- reg = <0x0 0x0ade0000 0x0 0x20000>;
- clocks = <&gcc GCC_CAMERA_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&rpmhcc RPMH_CXO_CLK_A>,
- <&sleep_clk>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
mdss0: display-subsystem@ae00000 {
compatible = "qcom,sa8775p-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
reg-names = "mdss";
- /* same path used twice */
- interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
- interconnect-names = "mdp0-mem",
- "mdp1-mem",
- "cpu-cfg";
-
- resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
-
- power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
-
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_DISP_HF_AXI_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
-
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
@@ -5403,23 +3482,6 @@ mdss0_mdp: display-controller@ae01000 {
<0x0 0x0aeb0000 0x0 0x3000>;
reg-names = "mdp", "vbif";
- clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
- clock-names = "nrt_bus",
- "iface",
- "lut",
- "core",
- "vsync";
-
- assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <19200000>;
-
- operating-points-v2 = <&mdss0_mdp_opp_table>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
-
interrupt-parent = <&mdss0>;
interrupts = <0>;
@@ -5459,30 +3521,6 @@ dpu_intf2_out: endpoint {
};
};
};
-
- mdss0_mdp_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-375000000 {
- opp-hz = /bits/ 64 <375000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- required-opps = <&rpmhpd_opp_nom>;
- };
-
- opp-575000000 {
- opp-hz = /bits/ 64 <575000000>;
- required-opps = <&rpmhpd_opp_turbo>;
- };
-
- opp-650000000 {
- opp-hz = /bits/ 64 <650000000>;
- required-opps = <&rpmhpd_opp_turbo_l1>;
- };
- };
};
mdss0_dsi0: dsi@ae94000 {
@@ -5493,29 +3531,6 @@ mdss0_dsi0: dsi@ae94000 {
interrupt-parent = <&mdss0>;
interrupts = <4>;
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_DISP_HF_AXI_CLK>;
- clock-names = "byte",
- "byte_intf",
- "pixel",
- "core",
- "iface",
- "bus";
- assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
- <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>;
- phys = <&mdss0_dsi0_phy>;
-
- operating-points-v2 = <&mdss_dsi_opp_table>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
-
- refgen-supply = <&refgen>;
-
#address-cells = <1>;
#size-cells = <0>;
@@ -5539,34 +3554,6 @@ port@1 {
mdss0_dsi0_out: endpoint { };
};
};
-
- mdss_dsi_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-358000000 {
- opp-hz = /bits/ 64 <358000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
- };
- };
-
- mdss0_dsi0_phy: phy@ae94400 {
- compatible = "qcom,sa8775p-dsi-phy-5nm";
- reg = <0x0 0x0ae94400 0x0 0x200>,
- <0x0 0x0ae94600 0x0 0x280>,
- <0x0 0x0ae94900 0x0 0x27c>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
-
- status = "disabled";
};
mdss0_dsi1: dsi@ae96000 {
@@ -5577,29 +3564,6 @@ mdss0_dsi1: dsi@ae96000 {
interrupt-parent = <&mdss0>;
interrupts = <5>;
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_DISP_HF_AXI_CLK>;
- clock-names = "byte",
- "byte_intf",
- "pixel",
- "core",
- "iface",
- "bus";
- assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
- <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
- phys = <&mdss0_dsi1_phy>;
-
- operating-points-v2 = <&mdss_dsi_opp_table>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
-
- refgen-supply = <&refgen>;
-
#address-cells = <1>;
#size-cells = <0>;
@@ -5625,67 +3589,6 @@ port@1 {
};
};
- mdss0_dsi1_phy: phy@ae96400 {
- compatible = "qcom,sa8775p-dsi-phy-5nm";
- reg = <0x0 0x0ae96400 0x0 0x200>,
- <0x0 0x0ae96600 0x0 0x280>,
- <0x0 0x0ae96900 0x0 0x27c>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
-
- status = "disabled";
- };
-
- mdss0_dp0_phy: phy@aec2a00 {
- compatible = "qcom,sa8775p-edp-phy";
-
- reg = <0x0 0x0aec2a00 0x0 0x200>,
- <0x0 0x0aec2200 0x0 0xd0>,
- <0x0 0x0aec2600 0x0 0xd0>,
- <0x0 0x0aec2000 0x0 0x1c8>;
-
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_EDP_REF_CLKREF_EN>;
- clock-names = "aux",
- "cfg_ahb",
- "ref";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- mdss0_dp1_phy: phy@aec5a00 {
- compatible = "qcom,sa8775p-edp-phy";
-
- reg = <0x0 0x0aec5a00 0x0 0x200>,
- <0x0 0x0aec5200 0x0 0xd0>,
- <0x0 0x0aec5600 0x0 0xd0>,
- <0x0 0x0aec5000 0x0 0x1c8>;
-
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_EDP_REF_CLKREF_EN>;
- clock-names = "aux",
- "cfg_ahb",
- "ref";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
mdss0_dp0: displayport-controller@af54000 {
compatible = "qcom,sa8775p-dp";
@@ -5702,38 +3605,6 @@ mdss0_dp0: displayport-controller@af54000 {
interrupt-parent = <&mdss0>;
interrupts = <12>;
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
- clock-names = "core_iface",
- "core_aux",
- "ctrl_link",
- "ctrl_link_iface",
- "stream_pixel",
- "stream_1_pixel",
- "stream_2_pixel",
- "stream_3_pixel";
- assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp0_phy 0>,
- <&mdss0_dp0_phy 1>,
- <&mdss0_dp0_phy 1>,
- <&mdss0_dp0_phy 1>,
- <&mdss0_dp0_phy 1>;
- phys = <&mdss0_dp0_phy>;
- phy-names = "dp";
-
- operating-points-v2 = <&dp_opp_table>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
-
#sound-dai-cells = <0>;
status = "disabled";
@@ -5756,30 +3627,6 @@ port@1 {
mdss0_dp0_out: endpoint { };
};
};
-
- dp_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-162000000 {
- opp-hz = /bits/ 64 <162000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- };
-
- opp-270000000 {
- opp-hz = /bits/ 64 <270000000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
-
- opp-540000000 {
- opp-hz = /bits/ 64 <540000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
-
- opp-810000000 {
- opp-hz = /bits/ 64 <810000000>;
- required-opps = <&rpmhpd_opp_nom>;
- };
- };
};
mdss0_dp1: displayport-controller@af5c000 {
@@ -5798,30 +3645,6 @@ mdss0_dp1: displayport-controller@af5c000 {
interrupt-parent = <&mdss0>;
interrupts = <13>;
- clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
- clock-names = "core_iface",
- "core_aux",
- "ctrl_link",
- "ctrl_link_iface",
- "stream_pixel",
- "stream_1_pixel";
- assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp1_phy 0>,
- <&mdss0_dp1_phy 1>,
- <&mdss0_dp1_phy 1>;
- phys = <&mdss0_dp1_phy>;
- phy-names = "dp";
-
- operating-points-v2 = <&dp_opp_table>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
-
#sound-dai-cells = <0>;
status = "disabled";
@@ -5847,25 +3670,6 @@ port@1 {
};
};
- dispcc0: clock-controller@af00000 {
- compatible = "qcom,sa8775p-dispcc0";
- reg = <0x0 0x0af00000 0x0 0x20000>;
- clocks = <&gcc GCC_DISP_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&rpmhcc RPMH_CXO_CLK_A>,
- <&sleep_clk>,
- <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
- <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
- <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
- <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>,
- <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
- <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>,
@@ -6315,95 +4119,6 @@ frame@17c2d000 {
};
};
- apps_rsc: rsc@18200000 {
- compatible = "qcom,rpmh-rsc";
- reg = <0x0 0x18200000 0x0 0x10000>,
- <0x0 0x18210000 0x0 0x10000>,
- <0x0 0x18220000 0x0 0x10000>;
- reg-names = "drv-0", "drv-1", "drv-2";
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- qcom,tcs-offset = <0xd00>;
- qcom,drv-id = <2>;
- qcom,tcs-config = <ACTIVE_TCS 2>,
- <SLEEP_TCS 3>,
- <WAKE_TCS 3>,
- <CONTROL_TCS 0>;
- label = "apps_rsc";
- power-domains = <&system_pd>;
-
- apps_bcm_voter: bcm-voter {
- compatible = "qcom,bcm-voter";
- };
-
- rpmhcc: clock-controller {
- compatible = "qcom,sa8775p-rpmh-clk";
- #clock-cells = <1>;
- clock-names = "xo";
- clocks = <&xo_board_clk>;
- };
-
- rpmhpd: power-controller {
- compatible = "qcom,sa8775p-rpmhpd";
- #power-domain-cells = <1>;
- operating-points-v2 = <&rpmhpd_opp_table>;
-
- rpmhpd_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- rpmhpd_opp_ret: opp-0 {
- opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
- };
-
- rpmhpd_opp_min_svs: opp-1 {
- opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
- };
-
- rpmhpd_opp_low_svs: opp-2 {
- opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
- };
-
- rpmhpd_opp_svs: opp-3 {
- opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
- };
-
- rpmhpd_opp_svs_l1: opp-4 {
- opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
- };
-
- rpmhpd_opp_nom: opp-5 {
- opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
- };
-
- rpmhpd_opp_nom_l1: opp-6 {
- opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
- };
-
- rpmhpd_opp_nom_l2: opp-7 {
- opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
- };
-
- rpmhpd_opp_turbo: opp-8 {
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
- };
-
- rpmhpd_opp_turbo_l1: opp-9 {
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
- };
- };
- };
- };
-
- epss_l3_cl0: interconnect@18590000 {
- compatible = "qcom,sa8775p-epss-l3",
- "qcom,epss-l3";
- reg = <0x0 0x18590000 0x0 0x1000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
- clock-names = "xo", "alternate";
- #interconnect-cells = <1>;
- };
-
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sa8775p-cpufreq-epss",
"qcom,cpufreq-epss";
@@ -6415,21 +4130,9 @@ cpufreq_hw: cpufreq@18591000 {
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
- clock-names = "xo", "alternate";
-
#freq-domain-cells = <1>;
};
- epss_l3_cl1: interconnect@18592000 {
- compatible = "qcom,sa8775p-epss-l3",
- "qcom,epss-l3";
- reg = <0x0 0x18592000 0x0 0x1000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
- clock-names = "xo", "alternate";
- #interconnect-cells = <1>;
- };
-
remoteproc_gpdsp0: remoteproc@20c00000 {
compatible = "qcom,sa8775p-gpdsp0-pas";
reg = <0x0 0x20c00000 0x0 0x10000>;
@@ -6442,16 +4145,6 @@ remoteproc_gpdsp0: remoteproc@20c00000 {
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd SA8775P_CX>,
- <&rpmhpd SA8775P_MXC>;
- power-domain-names = "cx", "mxc";
-
- interconnects = <&gpdsp_anoc MASTER_DSP0 0
- &config_noc SLAVE_CLK_CTL 0>;
-
memory-region = <&pil_gdsp0_mem>;
qcom,qmp = <&aoss_qmp>;
@@ -6514,16 +4207,6 @@ remoteproc_gpdsp1: remoteproc@21c00000 {
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd SA8775P_CX>,
- <&rpmhpd SA8775P_MXC>;
- power-domain-names = "cx", "mxc";
-
- interconnects = <&gpdsp_anoc MASTER_DSP1 0
- &config_noc SLAVE_CLK_CTL 0>;
-
memory-region = <&pil_gdsp1_mem>;
qcom,qmp = <&aoss_qmp>;
@@ -6579,24 +4262,6 @@ mdss1: display-subsystem@22000000 {
reg = <0x0 0x22000000 0x0 0x1000>;
reg-names = "mdss";
- interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
- interconnect-names = "mdp0-mem",
- "mdp1-mem",
- "cpu-cfg";
-
- resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
-
- power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
-
- clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_DISP1_HF_AXI_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
-
interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
@@ -6609,29 +4274,12 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
status = "disabled";
- display-controller@22001000 {
+ mdss1_mdp: display-controller@22001000 {
compatible = "qcom,sa8775p-dpu";
reg = <0x0 0x22001000 0x0 0x8f000>,
<0x0 0x220b0000 0x0 0x3000>;
reg-names = "mdp", "vbif";
- clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
- clock-names = "nrt_bus",
- "iface",
- "lut",
- "core",
- "vsync";
-
- assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <19200000>;
-
- operating-points-v2 = <&mdss0_mdp_opp_table>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
-
interrupt-parent = <&mdss1>;
interrupts = <0>;
@@ -6657,46 +4305,6 @@ dpu1_intf4_out: endpoint {
};
};
- mdss1_dp0_phy: phy@220c2a00 {
- compatible = "qcom,sa8775p-edp-phy";
- reg = <0x0 0x220c2a00 0x0 0x200>,
- <0x0 0x220c2200 0x0 0xd0>,
- <0x0 0x220c2600 0x0 0xd0>,
- <0x0 0x220c2000 0x0 0x1c8>;
-
- clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_EDP_REF_CLKREF_EN>;
- clock-names = "aux",
- "cfg_ahb",
- "ref";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- mdss1_dp1_phy: phy@220c5a00 {
- compatible = "qcom,sa8775p-edp-phy";
- reg = <0x0 0x220c5a00 0x0 0x200>,
- <0x0 0x220c5200 0x0 0xd0>,
- <0x0 0x220c5600 0x0 0xd0>,
- <0x0 0x220c5000 0x0 0x1c8>;
-
- clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_EDP_REF_CLKREF_EN>;
- clock-names = "aux",
- "cfg_ahb",
- "ref";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
mdss1_dp0: displayport-controller@22154000 {
compatible = "qcom,sa8775p-dp";
reg = <0x0 0x22154000 0x0 0x104>,
@@ -6712,38 +4320,6 @@ mdss1_dp0: displayport-controller@22154000 {
interrupt-parent = <&mdss1>;
interrupts = <12>;
- clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
- clock-names = "core_iface",
- "core_aux",
- "ctrl_link",
- "ctrl_link_iface",
- "stream_pixel",
- "stream_1_pixel",
- "stream_2_pixel",
- "stream_3_pixel";
- assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp0_phy 0>,
- <&mdss1_dp0_phy 1>,
- <&mdss1_dp0_phy 1>,
- <&mdss1_dp0_phy 1>,
- <&mdss1_dp0_phy 1>;
- phys = <&mdss1_dp0_phy>;
- phy-names = "dp";
-
- operating-points-v2 = <&dp_opp_table>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
-
#sound-dai-cells = <0>;
status = "disabled";
@@ -6783,30 +4359,6 @@ mdss1_dp1: displayport-controller@2215c000 {
interrupt-parent = <&mdss1>;
interrupts = <13>;
- clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
- clock-names = "core_iface",
- "core_aux",
- "ctrl_link",
- "ctrl_link_iface",
- "stream_pixel",
- "stream_1_pixel";
- assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
- <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp1_phy 0>,
- <&mdss1_dp1_phy 1>,
- <&mdss1_dp1_phy 1>;
- phys = <&mdss1_dp1_phy>;
- phy-names = "dp";
-
- operating-points-v2 = <&dp_opp_table>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
-
#sound-dai-cells = <0>;
status = "disabled";
@@ -6833,22 +4385,6 @@ port@1 {
};
};
- dispcc1: clock-controller@22100000 {
- compatible = "qcom,sa8775p-dispcc1";
- reg = <0x0 0x22100000 0x0 0x20000>;
- clocks = <&gcc GCC_DISP_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&rpmhcc RPMH_CXO_CLK_A>,
- <&sleep_clk>,
- <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
- <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
- <0>, <0>, <0>, <0>;
- power-domains = <&rpmhpd SA8775P_MMCX>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
ethernet1: ethernet@23000000 {
compatible = "qcom,sa8775p-ethqos";
reg = <0x0 0x23000000 0x0 0x10000>,
@@ -6859,27 +4395,6 @@ ethernet1: ethernet@23000000 {
<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "sfty";
- clocks = <&gcc GCC_EMAC1_AXI_CLK>,
- <&gcc GCC_EMAC1_SLV_AHB_CLK>,
- <&gcc GCC_EMAC1_PTP_CLK>,
- <&gcc GCC_EMAC1_PHY_AUX_CLK>;
- clock-names = "stmmaceth",
- "pclk",
- "ptp_ref",
- "phyaux";
-
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>,
- <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "cpu-mac",
- "mac-mem";
-
- power-domains = <&gcc EMAC1_GDSC>;
-
- phys = <&serdes1>;
- phy-names = "serdes";
-
iommus = <&apps_smmu 0x140 0xf>;
dma-coherent;
@@ -6901,27 +4416,6 @@ ethernet0: ethernet@23040000 {
<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "sfty";
- clocks = <&gcc GCC_EMAC0_AXI_CLK>,
- <&gcc GCC_EMAC0_SLV_AHB_CLK>,
- <&gcc GCC_EMAC0_PTP_CLK>,
- <&gcc GCC_EMAC0_PHY_AUX_CLK>;
- clock-names = "stmmaceth",
- "pclk",
- "ptp_ref",
- "phyaux";
-
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>,
- <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "cpu-mac",
- "mac-mem";
-
- power-domains = <&gcc EMAC0_GDSC>;
-
- phys = <&serdes0>;
- phy-names = "serdes";
-
iommus = <&apps_smmu 0x120 0xf>;
dma-coherent;
@@ -6933,13 +4427,6 @@ &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>,
status = "disabled";
};
- nspa_noc: interconnect@260c0000 {
- compatible = "qcom,sa8775p-nspa-noc";
- reg = <0x0 0x260c0000 0x0 0x16080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
remoteproc_cdsp0: remoteproc@26300000 {
compatible = "qcom,sa8775p-cdsp0-pas";
reg = <0x0 0x26300000 0x0 0x10000>;
@@ -6952,17 +4439,6 @@ remoteproc_cdsp0: remoteproc@26300000 {
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd SA8775P_CX>,
- <&rpmhpd SA8775P_MXC>,
- <&rpmhpd SA8775P_NSP0>;
- power-domain-names = "cx", "mxc", "nsp";
-
- interconnects = <&nspa_noc MASTER_CDSP_PROC 0
- &mc_virt SLAVE_EBI1 0>;
-
memory-region = <&pil_cdsp0_mem>;
qcom,qmp = <&aoss_qmp>;
@@ -7072,13 +4548,6 @@ compute-cb@11 {
};
};
- nspb_noc: interconnect@2a0c0000 {
- compatible = "qcom,sa8775p-nspb-noc";
- reg = <0x0 0x2a0c0000 0x0 0x16080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
remoteproc_cdsp1: remoteproc@2a300000 {
compatible = "qcom,sa8775p-cdsp1-pas";
reg = <0x0 0x2a300000 0x0 0x10000>;
@@ -7091,17 +4560,6 @@ remoteproc_cdsp1: remoteproc@2a300000 {
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd SA8775P_CX>,
- <&rpmhpd SA8775P_MXC>,
- <&rpmhpd SA8775P_NSP1>;
- power-domain-names = "cx", "mxc", "nsp";
-
- interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0
- &mc_virt SLAVE_EBI1 0>;
-
memory-region = <&pil_cdsp1_mem>;
qcom,qmp = <&aoss_qmp>;
@@ -7247,15 +4705,6 @@ remoteproc_adsp: remoteproc@30000000 {
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack";
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd SA8775P_LCX>,
- <&rpmhpd SA8775P_LMX>;
- power-domain-names = "lcx", "lmx";
-
- interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
-
memory-region = <&pil_adsp_mem>;
qcom,qmp = <&aoss_qmp>;
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 4/7] arm64: dts: qcom: lemans: Add label for firmware and reserved-memory
2026-10-15 2:37 [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC Shawn Guo
` (2 preceding siblings ...)
2026-10-15 2:37 ` [PATCH v2 3/7] arm64: dts: qcom: lemans: Move platform resources " Shawn Guo
@ 2026-10-15 2:37 ` Shawn Guo
2026-10-15 2:37 ` [PATCH v2 5/7] arm64: dts: qcom: Add device tree for Lemans GearVM variant Shawn Guo
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Shawn Guo @ 2026-10-15 2:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Deepti Jaggi, devicetree, linux-arm-msm, linux-kernel, Shawn Guo
Add label for firmware and reserved-memory node to make it easier for user
to override the default configuration.
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 821c86409c5d..c71b1a48c383 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -276,7 +276,7 @@ eud_in: endpoint {
};
};
- firmware {
+ firmware: firmware {
scm {
compatible = "qcom,scm-sa8775p", "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
@@ -365,7 +365,7 @@ system_pd: power-domain-system {
};
};
- reserved-memory {
+ reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 5/7] arm64: dts: qcom: Add device tree for Lemans GearVM variant
2026-10-15 2:37 [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC Shawn Guo
` (3 preceding siblings ...)
2026-10-15 2:37 ` [PATCH v2 4/7] arm64: dts: qcom: lemans: Add label for firmware and reserved-memory Shawn Guo
@ 2026-10-15 2:37 ` Shawn Guo
2026-10-15 2:37 ` [PATCH v2 6/7] dt-bindings: arm: qcom: add SA8255p Ride board Shawn Guo
2026-10-15 2:37 ` [PATCH v2 7/7] arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support Shawn Guo
6 siblings, 0 replies; 10+ messages in thread
From: Shawn Guo @ 2026-10-15 2:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Deepti Jaggi, devicetree, linux-arm-msm, linux-kernel, Shawn Guo,
Shazad Hussain, Nikunj Kela
Add lemans-gearvm.dtsi for Lemans GearVM variant (SA8255P) that utilizes
firmware to configure platform resources such as clocks, interconnects
and TLMM.
Device drivers request these resources through the SCMI power, reset and
performance protocols. Assign each device driver a dedicated SCMI
channel and Tx/Rx doorbells to support parallel resource requests and
aggregation in the SCMI platform server. Operate the SCMI server stack
in an SMP-enabled VM using the Qualcomm SMC/HVC transport driver for
communication.
Group resource operations to improve abstraction and reduce the number of
SCMI requests. Follow the SCMI-based resource management approach
demonstrated by Qualcomm at Linaro Connect 2024 [1].
[1] https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte
Co-developed-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
Signed-off-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Co-developed-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi | 3232 +++++++++++++++++++
1 file changed, 3232 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
diff --git a/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi b/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
new file mode 100644
index 000000000000..4c155cbc7975
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
@@ -0,0 +1,3232 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include "lemans.dtsi"
+
+/delete-node/ &xbl_boot_mem;
+/delete-node/ &pil_adsp_mem;
+/delete-node/ &q6_adsp_dtb_mem;
+/delete-node/ &q6_gdsp0_dtb_mem;
+/delete-node/ &pil_gdsp0_mem;
+/delete-node/ &pil_gdsp1_mem;
+/delete-node/ &q6_gdsp1_dtb_mem;
+/delete-node/ &q6_cdsp0_dtb_mem;
+/delete-node/ &pil_cdsp0_mem;
+/delete-node/ &pil_gpu_mem;
+/delete-node/ &q6_cdsp1_dtb_mem;
+/delete-node/ &pil_cdsp1_mem;
+/delete-node/ &pil_cvp_mem;
+/delete-node/ &pil_video_mem;
+/delete-node/ &scmi_mem;
+/delete-node/ &firmware_reserved_mem;
+
+/ {
+ clocks {
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&xo_board_clk>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ #clock-cells = <0>;
+ };
+
+ gpll0_board_clk: gpll0-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ xo_board_clk: xo-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+};
+
+&adreno_smmu {
+ power-domains = <&scmi15_pd 0>;
+};
+
+&cpufreq_hw {
+ clocks = <&bi_tcxo_div2>, <&gpll0_board_clk>;
+ clock-names = "xo", "alternate";
+};
+
+&firmware {
+ scm {
+ memory-region = <&tz_ffi_mem>;
+ };
+
+ scmi0: scmi-0 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem0>;
+
+ interrupts = <GIC_SPI 963 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi0_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi0_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi0_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi1: scmi-1 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem1>;
+
+ interrupts = <GIC_SPI 964 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi1_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi1_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi1_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi2: scmi-2 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem2>;
+
+ interrupts = <GIC_SPI 965 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi2_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi2_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi2_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi3: scmi-3 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem3>;
+
+ interrupts = <GIC_SPI 966 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi3_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi3_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi3_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi4: scmi-4 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem4>;
+
+ interrupts = <GIC_SPI 967 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi4_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi4_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi4_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi5: scmi-5 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem5>;
+
+ interrupts = <GIC_SPI 968 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi5_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi5_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi5_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi6: scmi-6 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem6>;
+
+ interrupts = <GIC_SPI 969 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi6_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi6_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi6_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi7: scmi-7 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem7>;
+
+ interrupts = <GIC_SPI 970 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi7_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi7_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi7_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi8: scmi-8 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem8>;
+
+ interrupts = <GIC_SPI 971 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi8_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi8_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi8_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi9: scmi-9 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem9>;
+
+ interrupts = <GIC_SPI 972 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi9_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi9_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi9_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi10: scmi-10 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem10>;
+
+ interrupts = <GIC_SPI 973 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi10_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi10_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi10_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi11: scmi-11 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem11>;
+
+ interrupts = <GIC_SPI 974 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi11_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi11_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi11_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi12: scmi-12 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem12>;
+
+ interrupts = <GIC_SPI 975 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi12_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi12_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi12_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi13: scmi-13 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem13>;
+
+ interrupts = <GIC_SPI 976 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi13_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi13_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi13_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi14: scmi-14 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem14>;
+
+ interrupts = <GIC_SPI 977 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi14_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi14_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi14_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi15: scmi-15 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem15>;
+
+ interrupts = <GIC_SPI 978 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi15_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi15_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi15_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi16: scmi-16 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem16>;
+
+ interrupts = <GIC_SPI 979 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi16_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi16_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi16_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi17: scmi-17 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem17>;
+
+ interrupts = <GIC_SPI 980 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi17_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi17_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi17_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi18: scmi-18 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem18>;
+
+ interrupts = <GIC_SPI 981 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi18_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi18_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi18_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi19: scmi-19 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem19>;
+
+ interrupts = <GIC_SPI 982 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi19_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi19_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi19_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi20: scmi-20 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem20>;
+
+ interrupts = <GIC_SPI 983 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi20_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi20_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi20_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi21: scmi-21 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem21>;
+
+ interrupts = <GIC_SPI 984 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi21_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi21_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi21_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi22: scmi-22 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem22>;
+
+ interrupts = <GIC_SPI 985 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi22_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi22_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi22_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi23: scmi-23 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem23>;
+
+ interrupts = <GIC_SPI 986 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi23_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ scmi24: scmi-24 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem24>;
+
+ interrupts = <GIC_SPI 987 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi24_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi24_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi24_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi25: scmi-25 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem25>;
+
+ interrupts = <GIC_ESPI 0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi25_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi25_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi25_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi26: scmi-26 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem26>;
+
+ interrupts = <GIC_ESPI 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi26_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi26_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi26_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi27: scmi-27 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem27>;
+
+ interrupts = <GIC_ESPI 2 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi27_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi27_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi27_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi28: scmi-28 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem28>;
+
+ interrupts = <GIC_ESPI 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi28_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi28_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi28_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi29: scmi-29 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem29>;
+
+ interrupts = <GIC_ESPI 4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi29_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi29_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi29_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi30: scmi-30 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem30>;
+
+ interrupts = <GIC_ESPI 5 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi30_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi30_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi30_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi31: scmi-31 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem31>;
+
+ interrupts = <GIC_ESPI 6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi31_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi31_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi31_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi32: scmi-32 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem32>;
+
+ interrupts = <GIC_ESPI 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi32_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi32_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi32_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi33: scmi-33 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem33>;
+
+ interrupts = <GIC_ESPI 8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi33_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi33_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi33_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi34: scmi-34 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem34>;
+
+ interrupts = <GIC_ESPI 9 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi34_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi34_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi34_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi35: scmi-35 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem35>;
+
+ interrupts = <GIC_ESPI 10 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi35_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi35_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi35_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi36: scmi-36 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem36>;
+
+ interrupts = <GIC_ESPI 11 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi36_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi36_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi36_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi37: scmi-37 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem37>;
+
+ interrupts = <GIC_ESPI 12 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi37_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi37_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi37_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi38: scmi-38 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem38>;
+
+ interrupts = <GIC_ESPI 13 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi38_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi38_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi38_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi39: scmi-39 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem39>;
+
+ interrupts = <GIC_ESPI 14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi39_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi39_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi39_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi40: scmi-40 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem40>;
+
+ interrupts = <GIC_ESPI 15 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi40_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi40_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi40_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi41: scmi-41 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem41>;
+
+ interrupts = <GIC_ESPI 16 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi41_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi41_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi41_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi42: scmi-42 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem42>;
+
+ interrupts = <GIC_ESPI 17 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi42_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi42_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi42_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi43: scmi-43 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem43>;
+
+ interrupts = <GIC_ESPI 18 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi43_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi43_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi43_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi44: scmi-44 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem44>;
+
+ interrupts = <GIC_ESPI 19 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi44_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi44_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi44_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi45: scmi-45 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem45>;
+
+ interrupts = <GIC_ESPI 20 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi45_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi45_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi45_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi46: scmi-46 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem46>;
+
+ interrupts = <GIC_ESPI 21 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi46_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi46_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi46_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi47: scmi-47 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem47>;
+
+ interrupts = <GIC_ESPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi47_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi47_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi47_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi48: scmi-48 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem48>;
+
+ interrupts = <GIC_ESPI 23 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi48_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi48_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi48_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi49: scmi-49 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem49>;
+
+ interrupts = <GIC_ESPI 24 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi49_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi49_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi49_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi50: scmi-50 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem50>;
+
+ interrupts = <GIC_ESPI 25 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi50_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi50_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi50_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi51: scmi-51 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem51>;
+
+ interrupts = <GIC_ESPI 26 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi51_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi51_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi51_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi52: scmi-52 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem52>;
+
+ interrupts = <GIC_ESPI 27 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi52_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi52_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi52_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi53: scmi-53 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem53>;
+
+ interrupts = <GIC_ESPI 28 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi53_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi53_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi53_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi54: scmi-54 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem54>;
+
+ interrupts = <GIC_ESPI 29 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi54_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi54_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi54_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi55: scmi-55 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem55>;
+
+ interrupts = <GIC_ESPI 30 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi55_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi55_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi55_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi56: scmi-56 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem56>;
+
+ interrupts = <GIC_ESPI 31 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi56_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi56_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi56_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi57: scmi-57 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem57>;
+
+ interrupts = <GIC_ESPI 32 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi57_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi57_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi57_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi58: scmi-58 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem58>;
+
+ interrupts = <GIC_ESPI 33 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi58_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi58_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi58_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi59: scmi-59 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem59>;
+
+ interrupts = <GIC_ESPI 34 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi59_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi59_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi59_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi60: scmi-60 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem60>;
+
+ interrupts = <GIC_ESPI 35 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi60_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi60_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi60_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi61: scmi-61 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem61>;
+
+ interrupts = <GIC_ESPI 36 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi61_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi61_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi61_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi62: scmi-62 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem62>;
+
+ interrupts = <GIC_ESPI 37 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi62_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi62_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi62_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+
+ scmi63: scmi-63 {
+ compatible = "qcom,scmi-smc";
+ arm,smc-id = <0xc6008012>;
+ shmem = <&shmem63>;
+
+ interrupts = <GIC_ESPI 38 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a2p";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ arm,max-msg = <10>;
+ arm,max-msg-size = <256>;
+ arm,max-rx-timeout-ms = <3000>;
+
+ status = "disabled";
+
+ scmi63_pd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi63_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi63_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+};
+
+&qupv3_id_0 {
+ compatible = "qcom,sa8255p-geni-se-qup";
+
+ i2c0: i2c@980000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 0>,
+ <&scmi11_dvfs 0>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi0: spi@980000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 0>,
+ <&scmi11_dvfs 0>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart0: serial@980000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 0>,
+ <&scmi11_dvfs 0>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c1: i2c@984000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 1>,
+ <&scmi11_dvfs 1>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi1: spi@984000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 1>,
+ <&scmi11_dvfs 1>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart1: serial@984000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 1>,
+ <&scmi11_dvfs 1>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 2>,
+ <&scmi11_dvfs 2>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 2>,
+ <&scmi11_dvfs 2>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart2: serial@988000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 2>,
+ <&scmi11_dvfs 2>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c3: i2c@98c000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 3>,
+ <&scmi11_dvfs 3>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi3: spi@98c000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 3>,
+ <&scmi11_dvfs 3>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart3: serial@98c000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 3>,
+ <&scmi11_dvfs 3>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c4: i2c@990000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 4>,
+ <&scmi11_dvfs 4>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi4: spi@990000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 4>,
+ <&scmi11_dvfs 4>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart4: serial@990000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 4>,
+ <&scmi11_dvfs 4>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 5>,
+ <&scmi11_dvfs 5>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi5: spi@994000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 5>,
+ <&scmi11_dvfs 5>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart5: serial@994000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 5>,
+ <&scmi11_dvfs 5>;
+ power-domain-names = "power",
+ "perf";
+ };
+};
+
+&qupv3_id_1 {
+ compatible = "qcom,sa8255p-geni-se-qup";
+
+ i2c7: i2c@a80000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 7>,
+ <&scmi11_dvfs 7>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi7: spi@a80000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 7>,
+ <&scmi11_dvfs 7>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart7: serial@a80000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 7>,
+ <&scmi11_dvfs 7>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c8: i2c@a84000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 8>,
+ <&scmi11_dvfs 8>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi8: spi@a84000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 8>,
+ <&scmi11_dvfs 8>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart8: serial@a84000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 8>,
+ <&scmi11_dvfs 8>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c9: i2c@a88000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 9>,
+ <&scmi11_dvfs 9>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi9: spi@a88000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 9>,
+ <&scmi11_dvfs 9>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart9: serial@a88000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 9>,
+ <&scmi11_dvfs 9>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c10: i2c@a8c000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 10>,
+ <&scmi11_dvfs 10>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi10: spi@a8c000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 10>,
+ <&scmi11_dvfs 10>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart10: serial@a8c000 {
+ compatible = "qcom,sa8255p-geni-debug-uart";
+ power-domains = <&scmi11_pd 10>,
+ <&scmi11_dvfs 10>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c11: i2c@a90000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 11>,
+ <&scmi11_dvfs 11>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi11: spi@a90000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 11>,
+ <&scmi11_dvfs 11>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart11: serial@a90000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 11>,
+ <&scmi11_dvfs 11>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c12: i2c@a94000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 12>,
+ <&scmi11_dvfs 12>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi12: spi@a94000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 12>,
+ <&scmi11_dvfs 12>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart12: serial@a94000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 12>,
+ <&scmi11_dvfs 12>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c13: i2c@a98000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 13>,
+ <&scmi11_dvfs 13>;
+ power-domain-names = "power",
+ "perf";
+ };
+};
+
+&qupv3_id_2 {
+ compatible = "qcom,sa8255p-geni-se-qup";
+
+ i2c14: i2c@880000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 14>,
+ <&scmi11_dvfs 14>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi14: spi@880000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 14>,
+ <&scmi11_dvfs 14>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart14: serial@880000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 14>,
+ <&scmi11_dvfs 14>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c15: i2c@884000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 15>,
+ <&scmi11_dvfs 15>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi15: spi@884000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 15>,
+ <&scmi11_dvfs 15>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart15: serial@884000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 15>,
+ <&scmi11_dvfs 15>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c16: i2c@888000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 16>,
+ <&scmi11_dvfs 16>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi16: spi@888000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 16>,
+ <&scmi11_dvfs 16>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart16: serial@888000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 16>,
+ <&scmi11_dvfs 16>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c17: i2c@88c000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 17>,
+ <&scmi11_dvfs 17>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi17: spi@88c000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 17>,
+ <&scmi11_dvfs 17>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart17: serial@88c000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 17>,
+ <&scmi11_dvfs 17>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c18: i2c@890000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 18>,
+ <&scmi11_dvfs 18>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi18: spi@890000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 18>,
+ <&scmi11_dvfs 18>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart18: serial@890000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 18>,
+ <&scmi11_dvfs 18>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c19: i2c@894000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 19>,
+ <&scmi11_dvfs 19>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi19: spi@894000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 19>,
+ <&scmi11_dvfs 19>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart19: serial@894000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 19>,
+ <&scmi11_dvfs 19>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ i2c20: i2c@898000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 20>,
+ <&scmi11_dvfs 20>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi20: spi@898000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 20>,
+ <&scmi11_dvfs 20>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart20: serial@898000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 20>,
+ <&scmi11_dvfs 20>;
+ power-domain-names = "power",
+ "perf";
+ };
+};
+
+&qupv3_id_3 {
+ compatible = "qcom,sa8255p-geni-se-qup";
+
+ i2c21: i2c@b80000 {
+ compatible = "qcom,sa8255p-geni-i2c";
+ power-domains = <&scmi11_pd 21>,
+ <&scmi11_dvfs 21>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ spi21: spi@b80000 {
+ compatible = "qcom,sa8255p-geni-spi";
+ power-domains = <&scmi11_pd 21>,
+ <&scmi11_dvfs 21>;
+ power-domain-names = "power",
+ "perf";
+ };
+
+ uart21: serial@b80000 {
+ compatible = "qcom,sa8255p-geni-uart";
+ power-domains = <&scmi11_pd 21>,
+ <&scmi11_dvfs 21>;
+ power-domain-names = "power",
+ "perf";
+ };
+};
+
+&pcie0_ep {
+ compatible = "qcom,sa8255p-pcie-ep";
+ power-domains = <&scmi5_pd 1>;
+};
+
+&pcie1_ep {
+ compatible = "qcom,sa8255p-pcie-ep";
+ power-domains = <&scmi6_pd 1>;
+};
+
+&reserved_memory {
+ xbl_boot_mem: xbl-boot@90700000 {
+ reg = <0x0 0x90700000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz_ffi_mem: tz-ffi@91c00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x91c00000 0x0 0x1400000>;
+ no-map;
+ };
+
+ pil_adsp_mem: pil-adsp@95c00000 {
+ reg = <0x0 0x95c00000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_adsp_dtb_mem: q6-adsp-dtb@97a00000 {
+ reg = <0x0 0x97a00000 0x0 0x80000>;
+ no-map;
+ };
+
+ pil_gdsp0_dtb_mem: pil-gdsp0-dtb@97a80000 {
+ reg = <0x0 0x97a80000 0x0 0x80000>;
+ no-map;
+ };
+
+ pil_gdsp0_mem: pil-gdsp0@97b00000 {
+ reg = <0x0 0x97b00000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_gdsp1_mem: pil-gdsp1@99900000 {
+ reg = <0x0 0x99900000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_gdsp1_dtb_mem: pil-gdsp1-dtb@9b700000 {
+ reg = <0x0 0x9b700000 0x0 0x80000>;
+ no-map;
+ };
+
+ pil_cdsp0_dtb_mem: pil-cdsp0-dtb@9b780000 {
+ reg = <0x0 0x9b780000 0x0 0x80000>;
+ no-map;
+ };
+
+ pil_cdsp0_mem: pil-cdsp0@9b800000 {
+ reg = <0x0 0x9b800000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_gpu_mem: pil-gpu@9d600000 {
+ reg = <0x0 0x9d600000 0x0 0x2000>;
+ no-map;
+ };
+
+ pil_cdsp1_dtb_mem: pil-cdsp1-dtb@9d680000 {
+ reg = <0x0 0x9d680000 0x0 0x80000>;
+ no-map;
+ };
+
+ pil_cdsp1_mem: pil-cdsp1@9d700000 {
+ reg = <0x0 0x9d700000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_cvp_mem: pil-cvp@9f500000 {
+ reg = <0x0 0x9f500000 0x0 0x700000>;
+ no-map;
+ };
+
+ pil_video_mem: pil-video@9fc00000 {
+ reg = <0x0 0x9fc00000 0x0 0x700000>;
+ no-map;
+ };
+
+ audio_config_mem: audio-config-region@ac600000 {
+ reg = <0x0 0xac600000 0x0 0xa00000>;
+ no-map;
+ };
+
+ audio_mdf_mem: audio-mdf-region@ad000000 {
+ reg = <0x0 0xad000000 0x0 0x2000000>;
+ no-map;
+ };
+
+ firmware_mem: firmware-region@b0000000 {
+ reg = <0x0 0xb0000000 0x0 0x800000>;
+ no-map;
+ };
+
+ hyptz_reserved_mem: hyptz-reserved@beb00000 {
+ reg = <0x0 0xbeb00000 0x0 0x11500000>;
+ no-map;
+ };
+
+ shmem0: scmi-mem@d0000000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0000000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem1: scmi-mem@d0001000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0001000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem2: scmi-mem@d0002000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0002000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem3: scmi-mem@d0003000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0003000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem4: scmi-mem@d0004000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0004000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem5: scmi-mem@d0005000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0005000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem6: scmi-mem@d0006000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0006000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem7: scmi-mem@d0007000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0007000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem8: scmi-mem@d0008000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0008000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem9: scmi-mem@d0009000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0009000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem10: scmi-mem@d000a000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd000a000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem11: scmi-mem@d000b000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd000b000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem12: scmi-mem@d000c000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd000c000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem13: scmi-mem@d000d000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd000d000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem14: scmi-mem@d000e000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd000e000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem15: scmi-mem@d000f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd000f000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem16: scmi-mem@d0010000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0010000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem17: scmi-mem@d0011000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0011000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem18: scmi-mem@d0012000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0012000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem19: scmi-mem@d0013000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0013000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem20: scmi-mem@d0014000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0014000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem21: scmi-mem@d0015000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0015000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem22: scmi-mem@d0016000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0016000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem23: scmi-mem@d0017000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0017000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem24: scmi-mem@d0018000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0018000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem25: scmi-mem@d0019000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0019000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem26: scmi-mem@d001a000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd001a000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem27: scmi-mem@d001b000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd001b000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem28: scmi-mem@d001c000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd001c000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem29: scmi-mem@d001d000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd001d000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem30: scmi-mem@d001e000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd001e000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem31: scmi-mem@d001f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd001f000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem32: scmi-mem@d0020000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0020000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem33: scmi-mem@d0021000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0021000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem34: scmi-mem@d0022000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0022000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem35: scmi-mem@d0023000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0023000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem36: scmi-mem@d0024000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0024000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem37: scmi-mem@d0025000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0025000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem38: scmi-mem@d0026000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0026000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem39: scmi-mem@d0027000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0027000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem40: scmi-mem@d0028000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0028000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem41: scmi-mem@d0029000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0029000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem42: scmi-mem@d002a000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd002a000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem43: scmi-mem@d002b000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd002b000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem44: scmi-mem@d002c000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd002c000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem45: scmi-mem@d002d000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd002d000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem46: scmi-mem@d002e000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd002e000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem47: scmi-mem@d002f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd002f000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem48: scmi-mem@d0030000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0030000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem49: scmi-mem@d0031000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0031000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem50: scmi-mem@d0032000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0032000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem51: scmi-mem@d0033000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0033000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem52: scmi-mem@d0034000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0034000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem53: scmi-mem@d0035000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0035000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem54: scmi-mem@d0036000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0036000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem55: scmi-mem@d0037000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0037000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem56: scmi-mem@d0038000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0038000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem57: scmi-mem@d0039000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0039000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem58: scmi-mem@d003a000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd003a000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem59: scmi-mem@d003b000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd003b000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem60: scmi-mem@d003c000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd003c000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem61: scmi-mem@d003d000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd003d000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem62: scmi-mem@d003e000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd003e000 0x0 0x1000>;
+ no-map;
+ };
+
+ shmem63: scmi-mem@d003f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd003f000 0x0 0x1000>;
+ no-map;
+ };
+
+ firmware_logs_mem: firmware-logs@d0040000 {
+ reg = <0x0 0xd0040000 0x0 0x10000>;
+ no-map;
+ };
+
+ firmware_audio_mem: firmware-audio@d0050000 {
+ reg = <0x0 0xd0050000 0x0 0x4000>;
+ no-map;
+ };
+
+ firmware_camera_mem: firmware-camera@d0054000 {
+ no-map;
+ reg = <0x0 0xd0054000 0x0 0x2000>;
+ };
+
+ firmware_reserved_mem: firmware-reserved@d0056000 {
+ reg = <0x0 0xd0056000 0x0 0x9a000>;
+ no-map;
+ };
+
+ firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
+ reg = <0x0 0xd00f0000 0x0 0x10000>;
+ no-map;
+ };
+
+ tags_mem: tags@d0100000 {
+ reg = <0x0 0xd0100000 0x0 0x1200000>;
+ no-map;
+ };
+
+ qtee_mem: qtee@d1300000 {
+ reg = <0x0 0xd1300000 0x0 0x500000>;
+ no-map;
+ };
+
+ deepsleep_backup_mem: deepsleep-backup@d1800000 {
+ reg = <0x0 0xd1800000 0x0 0x100000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted-apps@d1900000 {
+ reg = <0x0 0xd1900000 0x0 0x3800000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@db100000 {
+ reg = <0x0 0xdb100000 0x0 0x100000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw@db200000 {
+ reg = <0x0 0xdb200000 0x0 0x100000>;
+ no-map;
+ };
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+};
+
+&ufs_mem_hc {
+ compatible = "qcom,sa8255p-ufshc";
+ power-domains = <&scmi3_pd 0>;
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 6/7] dt-bindings: arm: qcom: add SA8255p Ride board
2026-10-15 2:37 [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC Shawn Guo
` (4 preceding siblings ...)
2026-10-15 2:37 ` [PATCH v2 5/7] arm64: dts: qcom: Add device tree for Lemans GearVM variant Shawn Guo
@ 2026-10-15 2:37 ` Shawn Guo
2026-10-15 2:37 ` [PATCH v2 7/7] arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support Shawn Guo
6 siblings, 0 replies; 10+ messages in thread
From: Shawn Guo @ 2026-10-15 2:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Deepti Jaggi, devicetree, linux-arm-msm, linux-kernel,
Nikunj Kela, Krzysztof Kozlowski, Bartosz Golaszewski, Shawn Guo
From: Nikunj Kela <quic_nkela@quicinc.com>
Document the SA8255p SoC and its reference board: sa8255p-ride.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 121ca557ce1e..415567b085db 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -490,6 +490,11 @@ properties:
- qcom,sa8155p-adp
- const: qcom,sa8155p
+ - items:
+ - enum:
+ - qcom,sa8255p-ride
+ - const: qcom,sa8255p
+
- items:
- enum:
- qcom,sa8295p-adp
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 7/7] arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support
2026-10-15 2:37 [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC Shawn Guo
` (5 preceding siblings ...)
2026-10-15 2:37 ` [PATCH v2 6/7] dt-bindings: arm: qcom: add SA8255p Ride board Shawn Guo
@ 2026-10-15 2:37 ` Shawn Guo
2026-10-15 2:48 ` sashiko-bot
6 siblings, 1 reply; 10+ messages in thread
From: Shawn Guo @ 2026-10-15 2:37 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Deepti Jaggi, devicetree, linux-arm-msm, linux-kernel,
Nikunj Kela, Shazad Hussain, Bartosz Golaszewski, Shawn Guo
From: Nikunj Kela <quic_nkela@quicinc.com>
Add initial device tree support for the Lemans SA8255P Ride board. Enable
UFS storage, UART10 as the serial console, PCIe EP interfaces, thermal
zones for PMM8654AU sensors, and SCMI protocol nodes.
Co-developed-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
Signed-off-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Co-developed-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/lemans-sa8255p-ride.dts | 222 ++++++++++++++++++
2 files changed, 223 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 88230c4e00ea..c2d2dc1019c8 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -63,6 +63,7 @@ lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb
lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb
+dtb-$(CONFIG_ARCH_QCOM) += lemans-sa8255p-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += mahua-lenovo-thinkpad-t14s-gen7-lcd.dtb
dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb
diff --git a/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
new file mode 100644
index 000000000000..4273f47c3dff
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "lemans-gearvm.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SA8255P Ride";
+ compatible = "qcom,sa8255p-ride", "qcom,sa8255p";
+
+ aliases {
+ serial0 = &uart10;
+ serial1 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ thermal-zones {
+ pmm8654au_0_thermal: pm8255-0-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scmi23_sensor 0>;
+
+ trips {
+ trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ pmm8654au_1_thermal: pm8255-1-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scmi23_sensor 1>;
+
+ trips {
+ trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ pmm8654au_2_thermal: pm8255-2-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scmi23_sensor 2>;
+
+ trips {
+ trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ pmm8654au_3_thermal: pm8255-3-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&scmi23_sensor 3>;
+
+ trips {
+ trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&gpll0_board_clk {
+ clock-frequency = <300000000>;
+};
+
+&pcie0_ep {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_ep_clkreq_default &pcie0_ep_perst_default
+ &pcie0_ep_wake_default>;
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_ep_clkreq_default &pcie1_ep_perst_default
+ &pcie1_ep_wake_default>;
+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&scmi3 {
+ status = "okay";
+};
+
+&scmi4 {
+ status = "okay";
+};
+
+&scmi5 {
+ status = "okay";
+};
+
+&scmi6 {
+ status = "okay";
+};
+
+&scmi11 {
+ status = "okay";
+};
+
+&scmi15 {
+ status = "okay";
+};
+
+&scmi23 {
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart10 {
+ status = "okay";
+};
+
+&tlmm {
+ pcie0_ep_clkreq_default: pcie0-ep-clkreq-default-state {
+ pins = "gpio1";
+ function = "pcie0_clkreq";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie0_ep_perst_default: pcie0-ep-perst-default-state {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-down;
+ };
+
+ pcie0_ep_wake_default: pcie0-ep-wake-default-state {
+ pins = "gpio0";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie1_ep_clkreq_default: pcie1-ep-clkreq-default-state {
+ pins = "gpio3";
+ function = "pcie1_clkreq";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie1_ep_perst_default: pcie1-ep-perst-default-state {
+ pins = "gpio4";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ pcie1_ep_wake_default: pcie1-ep-wake-default-state {
+ pins = "gpio5";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&ufs_mem_hc {
+ status = "okay";
+};
+
+&xo_board_clk {
+ clock-frequency = <38400000>;
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support
2026-10-15 2:37 ` [PATCH v2 7/7] arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support Shawn Guo
@ 2026-10-15 2:48 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-10-15 2:48 UTC (permalink / raw)
To: Shawn Guo; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] dts: qcom: missing status = "okay" for pcie0_ep and pcie1_ep
- [Medium] dts: qcom: incorrect polarity for PCIe EP wake-gpios
--
commit 3fa46fe28ef2e9d52dd0b40b57be7d7192538595
Author: Nikunj Kela <quic_nkela@quicinc.com>
arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support
Add initial device tree support for the Lemans SA8255P Ride board. Enable
UFS storage, UART10 as the serial console, PCIe EP interfaces, thermal
zones for PMM8654AU sensors, and SCMI protocol nodes.
> diff --git a/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
> new file mode 100644
> index 0000000000000..4273f47c3dffc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts
[ ... ]
> +&pcie0_ep {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie0_ep_clkreq_default &pcie0_ep_perst_default
> + &pcie0_ep_wake_default>;
> + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
[Severity: Medium]
Since the commit message states this patch enables the PCIe EP interfaces,
should pcie0_ep include a status = "okay"; property?
Without explicitly overriding the status, the node will likely remain
disabled as typically defined in the base device tree, preventing the kernel
from probing the controller.
> + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
[Severity: Medium]
Is the polarity for the wake-gpios correct here?
The PCIe WAKE# signal is architecturally active-low and open-drain. By
configuring it as GPIO_ACTIVE_HIGH, the physical pad will be driven low
when the driver intends to initialize or deassert it, and high when
asserting it.
Could this invert the wake signal and break PCIe endpoint power management
wakeups?
> +};
> +
> +&pcie1_ep {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_ep_clkreq_default &pcie1_ep_perst_default
> + &pcie1_ep_wake_default>;
> + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
[Severity: Medium]
Similarly, should pcie1_ep also include a status = "okay"; property to
ensure it is enabled?
> + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
[Severity: Medium]
Does this wake-gpios configuration also suffer from the same active-low
signal inversion issue as pcie0_ep?
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261015023711.721837-1-shengchao.guo@oss.qualcomm.com?part=7
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/7] arm64: dts: qcom: lemans: Move platform resources into lemans-embedded.dtsi
2026-10-15 2:37 ` [PATCH v2 3/7] arm64: dts: qcom: lemans: Move platform resources " Shawn Guo
@ 2026-10-15 2:48 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-10-15 2:48 UTC (permalink / raw)
To: Shawn Guo; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dts: Incorrect removal of 'compatible' from base DTSI nodes
--
commit f8600c852f6da5600fb82650c04f9b466cb80549
Author: Shawn Guo <shengchao.guo@oss.qualcomm.com>
arm64: dts: qcom: lemans: Move platform resources into lemans-embedded.dtsi
This commit moves platform resources like clocks, regulators, and interconnects
from the base lemans.dtsi to the lemans-embedded.dtsi file. This isolates
these managed configurations so the base devicetree can be shared with the
GearVM variant.
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 7547042d8e851..821c86409c5da 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
[ ... ]
> @@ -4662,49 +3089,9 @@ gpu: gpu@3d00000 {
[ ... ]
> gmu: gmu@3d6a000 {
> - compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu";
[Severity: Medium]
Does this leave the GMU node structurally incomplete for other variants?
A compatible string is typically a fundamental description of the hardware IP
rather than a dynamically managed platform resource. Removing it from the base
lemans.dtsi means that any environment (like the incoming GearVM variant)
including this file will inherit a node that has "reg" and "interrupts" but
lacks a compatible string.
Will this break devicetree schema validation and prevent proper driver binding
for variants that do not include lemans-embedded.dtsi?
> reg = <0x0 0x03d6a000 0x0 0x34000>,
> <0x0 0x03de0000 0x0 0x10000>,
> <0x0 0x0b290000 0x0 0x10000>;
[ ... ]
> - pmu@9091000 {
> - compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> + llcc_bwmon: pmu@9091000 {
[Severity: Medium]
Similarly, does removing the compatible string for the llcc_bwmon node here
leave it incomplete in the base devicetree?
> reg = <0x0 0x9091000 0x0 0x1000>;
> interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
[ ... ]
> - pmu@90b5400 {
> - compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
> + cpu_bwmon0: pmu@90b5400 {
[Severity: Medium]
Does this also incorrectly strip the hardware description from the cpu_bwmon0
node for environments relying only on lemans.dtsi?
> reg = <0x0 0x90b5400 0x0 0x600>;
> interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
[ ... ]
> - pmu@90b6400 {
> - compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon";
> + cpu_bwmon1: pmu@90b6400 {
[Severity: Medium]
Does this also incorrectly strip the hardware description from the cpu_bwmon1
node for environments relying only on lemans.dtsi?
> reg = <0x0 0x90b6400 0x0 0x600>;
> interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261015023711.721837-1-shengchao.guo@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2026-10-15 2:48 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-15 2:37 [PATCH v2 0/7] arm64: dts: qcom: Introduce SA8255P as Lemans family SoC Shawn Guo
2026-10-15 2:37 ` [PATCH v2 1/7] arm64: dts: qcom: Introduce lemans-embedded.dtsi as a placeholder Shawn Guo
2026-10-15 2:37 ` [PATCH v2 2/7] arm64: dts: qcom: lemans: Move pinctrl states into lemans-embedded.dtsi Shawn Guo
2026-10-15 2:37 ` [PATCH v2 3/7] arm64: dts: qcom: lemans: Move platform resources " Shawn Guo
2026-10-15 2:48 ` sashiko-bot
2026-10-15 2:37 ` [PATCH v2 4/7] arm64: dts: qcom: lemans: Add label for firmware and reserved-memory Shawn Guo
2026-10-15 2:37 ` [PATCH v2 5/7] arm64: dts: qcom: Add device tree for Lemans GearVM variant Shawn Guo
2026-10-15 2:37 ` [PATCH v2 6/7] dt-bindings: arm: qcom: add SA8255p Ride board Shawn Guo
2026-10-15 2:37 ` [PATCH v2 7/7] arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support Shawn Guo
2026-10-15 2:48 ` sashiko-bot
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