* [PATCH v5 0/7] riscv: eswin: eic7700: Add support for clocks, resets, pinctrl, HSP bus, I2C and watchdog
@ 2026-10-15 12:54 ` Pinkesh Vaghela
0 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
Changes in v5:
- Rebased the patches to master branch of linux-next tree having
latest tag: next-20261014.
- Updated dts file
- Arranged the nodes in alphabetical order.
- Removed the board-wide GPIO pinctrl state and attached GPIO84 to
its gpio-leds consumer.
- Moved the invariant I2C pinctrl states from board overrides into
the corresponding SoC controller nodes.
- Removed enabling watchdog nodes and describe them as enabled at
SoC level.
- Updated dtsi file
- Added pinctrl property to all I2C controller nodes.
- Sorted the always-on I2C controllers by unit address.
- Removed default property "disabled" from all watchdog nodes.
- Updated pinctrl.dtsi file
- Resolve missing space issue.
- Annotate all nodes with /omit-if-no-ref/.
- Removed duplicated base pins from the quad-SPI pin states.
- Split UART1 RTS/CTS from its TX/RX pin state.
- Added "Acked-by" tag of "Andi Shyti" for the I2C binding patch
(i.e. Patch 5).
- Link to v4: https://lore.kernel.org/lkml/20260814070007.1662455-1-pinkesh.vaghela@einfochips.com/
Pinkesh Vaghela (1):
riscv: dts: eswin: add hsp bus node
Pritesh Patel (5):
riscv: dts: eswin: add reset generator for EIC7700 SoC
riscv: dts: eswin: add clock generator for EIC7700 SoC
dt-bindings: i2c: dw: add ESWIN EIC7700 SoC I2C controller
riscv: dts: eswin: add I2C controller support
riscv: dts: eswin: add watchdog support
Yulin Lu (1):
riscv: dts: eswin: eic7700: add pinctrl support
.../bindings/i2c/snps,designware-i2c.yaml | 1 +
.../dts/eswin/eic7700-hifive-premier-p550.dts | 91 ++
.../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 1065 +++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 255 ++++
4 files changed, 1412 insertions(+)
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v5 1/7] riscv: dts: eswin: add reset generator for EIC7700 SoC
2026-10-15 12:54 ` Pinkesh Vaghela
@ 2026-10-15 12:54 ` Pinkesh Vaghela
-1 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add reset generator node for EIC7700 SoC
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
arch/riscv/boot/dts/eswin/eic7700.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c3ed93008bca..430a210f01e6 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -4,6 +4,7 @@
*/
/dts-v1/;
+#include <dt-bindings/reset/eswin,eic7700-reset.h>
/ {
#address-cells = <2>;
@@ -341,5 +342,11 @@ gpioD: gpio-port@3 {
#gpio-cells = <2>;
};
};
+
+ reset: reset-controller@51828300 {
+ compatible = "eswin,eic7700-reset";
+ reg = <0x0 0x51828300 0x0 0x200>;
+ #reset-cells = <1>;
+ };
};
};
--
2.34.1
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 1/7] riscv: dts: eswin: add reset generator for EIC7700 SoC
@ 2026-10-15 12:54 ` Pinkesh Vaghela
0 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add reset generator node for EIC7700 SoC
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
arch/riscv/boot/dts/eswin/eic7700.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c3ed93008bca..430a210f01e6 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -4,6 +4,7 @@
*/
/dts-v1/;
+#include <dt-bindings/reset/eswin,eic7700-reset.h>
/ {
#address-cells = <2>;
@@ -341,5 +342,11 @@ gpioD: gpio-port@3 {
#gpio-cells = <2>;
};
};
+
+ reset: reset-controller@51828300 {
+ compatible = "eswin,eic7700-reset";
+ reg = <0x0 0x51828300 0x0 0x200>;
+ #reset-cells = <1>;
+ };
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v5 2/7] riscv: dts: eswin: add clock generator for EIC7700 SoC
2026-10-15 12:54 ` Pinkesh Vaghela
@ 2026-10-15 12:54 ` Pinkesh Vaghela
-1 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add clock generator node for EIC7700 SoC.
HiFive Premier P550 boards have 24MHz crystal oscillator to provide
the input clock.
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../boot/dts/eswin/eic7700-hifive-premier-p550.dts | 5 +++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 131ed1fc6b2e..a5c76b14a38f 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -20,6 +20,11 @@ chosen {
};
};
+&osc {
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 430a210f01e6..b3a230870315 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -4,6 +4,7 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/eswin,eic7700-clock.h>
#include <dt-bindings/reset/eswin,eic7700-reset.h>
/ {
@@ -203,6 +204,11 @@ pmu {
<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
};
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
ranges;
@@ -343,6 +349,13 @@ gpioD: gpio-port@3 {
};
};
+ clk: clock-controller@51828000 {
+ compatible = "eswin,eic7700-clock";
+ reg = <0x0 0x51828000 0x0 0x300>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
reset: reset-controller@51828300 {
compatible = "eswin,eic7700-reset";
reg = <0x0 0x51828300 0x0 0x200>;
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 2/7] riscv: dts: eswin: add clock generator for EIC7700 SoC
@ 2026-10-15 12:54 ` Pinkesh Vaghela
0 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add clock generator node for EIC7700 SoC.
HiFive Premier P550 boards have 24MHz crystal oscillator to provide
the input clock.
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../boot/dts/eswin/eic7700-hifive-premier-p550.dts | 5 +++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 131ed1fc6b2e..a5c76b14a38f 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -20,6 +20,11 @@ chosen {
};
};
+&osc {
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 430a210f01e6..b3a230870315 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -4,6 +4,7 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/eswin,eic7700-clock.h>
#include <dt-bindings/reset/eswin,eic7700-reset.h>
/ {
@@ -203,6 +204,11 @@ pmu {
<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
};
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
ranges;
@@ -343,6 +349,13 @@ gpioD: gpio-port@3 {
};
};
+ clk: clock-controller@51828000 {
+ compatible = "eswin,eic7700-clock";
+ reg = <0x0 0x51828000 0x0 0x300>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
reset: reset-controller@51828300 {
compatible = "eswin,eic7700-reset";
reg = <0x0 0x51828300 0x0 0x200>;
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v5 3/7] riscv: dts: eswin: eic7700: add pinctrl support
2026-10-15 12:54 ` Pinkesh Vaghela
@ 2026-10-15 12:54 ` Pinkesh Vaghela
-1 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Yulin Lu <luyulin@eswincomputing.com>
Add pinctrl node and related pin configuration for EIC7700 SoC
Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../dts/eswin/eic7700-hifive-premier-p550.dts | 34 +
.../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 1065 +++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 5 +
3 files changed, 1104 insertions(+)
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index a5c76b14a38f..afae15bda70a 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "eic7700.dtsi"
+#include "eic7700-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
@@ -18,6 +20,30 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio84_pins>;
+
+ led-0 {
+ gpios = <&gpioC 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ vcc_1v8: regulator-vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&gpio84_pins {
+ bias-disable;
+ input-disable;
};
&osc {
@@ -25,10 +51,18 @@ &osc {
clock-output-names = "osc_24m";
};
+&pinctrl {
+ vrgmii-supply = <&vcc_1v8>;
+};
+
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
};
&uart2 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
new file mode 100644
index 000000000000..c11f42e79c6e
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
@@ -0,0 +1,1065 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
+ *
+ * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+&pinctrl {
+ default-pins-grp {
+ /omit-if-no-ref/
+ sata_act_led_pins: sata-act-led-pins {
+ pins = "gpio27";
+ function = "sata";
+ };
+
+ /omit-if-no-ref/
+ emmc_led_ctrl_pins: emmc-led-ctrl-pins {
+ pins = "gpio29";
+ function = "emmc";
+ };
+
+ /omit-if-no-ref/
+ sd0_led_ctrl_pins: sd0-led-ctrl-pins {
+ pins = "gpio34";
+ function = "sdio";
+ };
+
+ /omit-if-no-ref/
+ sd1_led_ctrl_pins: sd1-led-ctrl-pins {
+ pins = "spi1_d2";
+ function = "sdio";
+ };
+
+ /omit-if-no-ref/
+ i2c6_pins: i2c6-pins {
+ pins = "uart1_cts", "uart1_rts";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c7_pins: i2c7-pins {
+ pins = "uart2_tx", "uart2_rx";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c9_pins: i2c9-pins {
+ pins = "spi1_d0", "spi1_d1";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ pwm1_pins: pwm1-pins {
+ pins = "spi1_d3";
+ function = "pwm";
+ };
+
+ /omit-if-no-ref/
+ pwm2_pins: pwm2-pins {
+ pins = "spi1_cs1_n";
+ function = "pwm";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi_xtrig0_pins: mipi-csi-xtrig0-pins {
+ pins = "gpio92";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi_xtrig1_pins: mipi-csi-xtrig1-pins {
+ pins = "gpio93";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ dual_spi2_pins: dual-spi2-pins {
+ pins = "spi2_cs0_n", "jtag0_tck", "jtag0_tms", "jtag0_tdi";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ quad_spi2_pins: quad-spi2-pins {
+ pins = "spi2_cs1_n", "jtag0_tdo", "gpio5";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ gpio1_pins: gpio1-pins {
+ pins = "jtag0_tck";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio2_pins: gpio2-pins {
+ pins = "jtag0_tms";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio3_pins: gpio3-pins {
+ pins = "jtag0_tdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio4_pins: gpio4-pins {
+ pins = "jtag0_tdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio6_pins: gpio6-pins {
+ pins = "spi2_cs0_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio7_pins: gpio7-pins {
+ pins = "jtag1_tck";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio8_pins: gpio8-pins {
+ pins = "jtag1_tms";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio9_pins: gpio9-pins {
+ pins = "jtag1_tdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio10_pins: gpio10-pins {
+ pins = "jtag1_tdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio12_pins: gpio12-pins {
+ pins = "spi2_cs1_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio13_pins: gpio13-pins {
+ pins = "mode_set0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio14_pins: gpio14-pins {
+ pins = "mode_set1";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio15_pins: gpio15-pins {
+ pins = "mode_set2";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio16_pins: gpio16-pins {
+ pins = "mode_set3";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio17_pins: gpio17-pins {
+ pins = "jtag2_trst";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio18_pins: gpio18-pins {
+ pins = "i2s0_bclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio19_pins: gpio19-pins {
+ pins = "i2s0_wclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio20_pins: gpio20-pins {
+ pins = "i2s0_sdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio21_pins: gpio21-pins {
+ pins = "i2s0_sdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio22_pins: gpio22-pins {
+ pins = "i2s_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio23_pins: gpio23-pins {
+ pins = "i2s2_bclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio24_pins: gpio24-pins {
+ pins = "i2s2_wclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio25_pins: gpio25-pins {
+ pins = "i2s2_sdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio26_pins: gpio26-pins {
+ pins = "i2s2_sdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio29_pins: gpio29-pins {
+ pins = "gpio29";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio30_pins: gpio30-pins {
+ pins = "i2s1_bclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio31_pins: gpio31-pins {
+ pins = "i2s1_wclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio32_pins: gpio32-pins {
+ pins = "i2s1_sdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio33_pins: gpio33-pins {
+ pins = "i2s1_sdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio34_pins: gpio34-pins {
+ pins = "gpio34";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio35_pins: gpio35-pins {
+ pins = "spi1_cs0_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio36_pins: gpio36-pins {
+ pins = "spi1_clk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio37_pins: gpio37-pins {
+ pins = "spi1_d0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio38_pins: gpio38-pins {
+ pins = "spi1_d1";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio39_pins: gpio39-pins {
+ pins = "spi1_d2";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio40_pins: gpio40-pins {
+ pins = "spi1_d3";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio41_pins: gpio41-pins {
+ pins = "spi1_cs1_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio42_pins: gpio42-pins {
+ pins = "usb0_pwren";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio43_pins: gpio43-pins {
+ pins = "usb1_pwren";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio44_pins: gpio44-pins {
+ pins = "i2c0_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio45_pins: gpio45-pins {
+ pins = "i2c0_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio46_pins: gpio46-pins {
+ pins = "i2c1_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio47_pins: gpio47-pins {
+ pins = "i2c1_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio48_pins: gpio48-pins {
+ pins = "i2c2_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio49_pins: gpio49-pins {
+ pins = "i2c2_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio50_pins: gpio50-pins {
+ pins = "i2c3_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio51_pins: gpio51-pins {
+ pins = "i2c3_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio52_pins: gpio52-pins {
+ pins = "i2c4_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio53_pins: gpio53-pins {
+ pins = "i2c4_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio54_pins: gpio54-pins {
+ pins = "i2c5_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio55_pins: gpio55-pins {
+ pins = "i2c5_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio56_pins: gpio56-pins {
+ pins = "uart0_tx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio57_pins: gpio57-pins {
+ pins = "uart0_rx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio58_pins: gpio58-pins {
+ pins = "uart1_tx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio59_pins: gpio59-pins {
+ pins = "uart1_rx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio60_pins: gpio60-pins {
+ pins = "uart1_cts";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio61_pins: gpio61-pins {
+ pins = "uart1_rts";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio62_pins: gpio62-pins {
+ pins = "uart2_tx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio63_pins: gpio63-pins {
+ pins = "uart2_rx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio64_pins: gpio64-pins {
+ pins = "jtag2_tck";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio65_pins: gpio65-pins {
+ pins = "jtag2_tms";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio66_pins: gpio66-pins {
+ pins = "jtag2_tdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio67_pins: gpio67-pins {
+ pins = "jtag2_tdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio68_pins: gpio68-pins {
+ pins = "fan_pwm";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio69_pins: gpio69-pins {
+ pins = "fan_tach";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio70_pins: gpio70-pins {
+ pins = "mipi_csi0_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio71_pins: gpio71-pins {
+ pins = "mipi_csi0_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio72_pins: gpio72-pins {
+ pins = "mipi_csi0_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio73_pins: gpio73-pins {
+ pins = "mipi_csi1_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio74_pins: gpio74-pins {
+ pins = "mipi_csi1_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio75_pins: gpio75-pins {
+ pins = "mipi_csi1_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio76_pins: gpio76-pins {
+ pins = "mipi_csi2_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio77_pins: gpio77-pins {
+ pins = "mipi_csi2_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio78_pins: gpio78-pins {
+ pins = "mipi_csi2_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio79_pins: gpio79-pins {
+ pins = "mipi_csi3_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio80_pins: gpio80-pins {
+ pins = "mipi_csi3_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio81_pins: gpio81-pins {
+ pins = "mipi_csi3_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio82_pins: gpio82-pins {
+ pins = "mipi_csi4_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio83_pins: gpio83-pins {
+ pins = "mipi_csi4_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio84_pins: gpio84-pins {
+ pins = "mipi_csi4_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio85_pins: gpio85-pins {
+ pins = "mipi_csi5_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio86_pins: gpio86-pins {
+ pins = "mipi_csi5_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio87_pins: gpio87-pins {
+ pins = "mipi_csi5_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio88_pins: gpio88-pins {
+ pins = "spi3_cs_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio89_pins: gpio89-pins {
+ pins = "spi3_clk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio90_pins: gpio90-pins {
+ pins = "spi3_di";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio91_pins: gpio91-pins {
+ pins = "spi3_do";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio92_pins: gpio92-pins {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio93_pins: gpio93-pins {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio94_pins: gpio94-pins {
+ pins = "s_mode";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio95_pins: gpio95-pins {
+ pins = "gpio95";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio96_pins: gpio96-pins {
+ pins = "spi0_cs_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio97_pins: gpio97-pins {
+ pins = "spi0_clk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio98_pins: gpio98-pins {
+ pins = "spi0_d0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio99_pins: gpio99-pins {
+ pins = "spi0_d1";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio100_pins: gpio100-pins {
+ pins = "spi0_d2";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio101_pins: gpio101-pins {
+ pins = "spi0_d3";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio102_pins: gpio102-pins {
+ pins = "i2c10_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio103_pins: gpio103-pins {
+ pins = "i2c10_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio104_pins: gpio104-pins {
+ pins = "i2c11_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio105_pins: gpio105-pins {
+ pins = "i2c11_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio107_pins: gpio107-pins {
+ pins = "boot_sel0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio108_pins: gpio108-pins {
+ pins = "boot_sel1";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio109_pins: gpio109-pins {
+ pins = "boot_sel2";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio110_pins: gpio110-pins {
+ pins = "boot_sel3";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ uart3_pins: uart3-pins {
+ pins = "gpio92", "gpio93";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ uart4_pins: uart4-pins {
+ pins = "spi1_d0", "spi1_d1";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ gpio0_pins: gpio0-pins {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio5_pins: gpio5-pins {
+ pins = "gpio5";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio11_pins: gpio11-pins {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio27_pins: gpio27-pins {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio28_pins: gpio28-pins {
+ pins = "gpio28";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio106_pins: gpio106-pins {
+ pins = "gpio106";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio111_pins: gpio111-pins {
+ pins = "gpio111";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ chip_mode_pins: chip-mode-pins {
+ pins = "chip_mode";
+ function = "chip_mode";
+ };
+
+ /omit-if-no-ref/
+ sdio0_pins: sdio0-pins {
+ pins = "mode_set0", "mode_set1";
+ function = "sdio";
+ };
+
+ /omit-if-no-ref/
+ sdio1_pins: sdio1-pins {
+ pins = "mode_set2", "mode_set3";
+ function = "sdio";
+ };
+
+ /omit-if-no-ref/
+ jtag0_pins: jtag0-pins {
+ pins = "jtag0_tck", "jtag0_tms", "jtag0_tdi", "jtag0_tdo";
+ function = "jtag";
+ };
+
+ /omit-if-no-ref/
+ jtag1_pins: jtag1-pins {
+ pins = "jtag1_tck", "jtag1_tms", "jtag1_tdi", "jtag1_tdo";
+ function = "jtag";
+ };
+
+ /omit-if-no-ref/
+ jtag2_pins: jtag2-pins {
+ pins = "jtag2_trst", "jtag2_tck", "jtag2_tms", "jtag2_tdi",
+ "jtag2_tdo";
+ function = "jtag";
+ };
+
+ /omit-if-no-ref/
+ pcie_pins: pcie-pins {
+ pins = "pcie_clkreq_n", "pcie_wake_n", "pcie_perst_n";
+ function = "pcie";
+ };
+
+ /omit-if-no-ref/
+ hdmi_pins: hdmi-pins {
+ pins = "hdmi_scl", "hdmi_sda", "hdmi_cec";
+ function = "hdmi";
+ };
+
+ /omit-if-no-ref/
+ rgmii0_pins: rgmii0-pins {
+ pins = "rgmii0_clk_125", "rgmii0_txen", "rgmii0_txclk", "rgmii0_txd0",
+ "rgmii0_txd1", "rgmii0_txd2", "rgmii0_txd3", "rgmii0_rxclk",
+ "rgmii0_rxdv", "rgmii0_rxd0", "rgmii0_rxd1", "rgmii0_rxd2",
+ "rgmii0_rxd3", "rgmii0_mdc", "rgmii0_mdio", "rgmii0_intb";
+ function = "rgmii";
+ };
+
+ /omit-if-no-ref/
+ rgmii1_pins: rgmii1-pins {
+ pins = "rgmii1_clk_125", "rgmii1_txen", "rgmii1_txclk", "rgmii1_txd0",
+ "rgmii1_txd1", "rgmii1_txd2", "rgmii1_txd3", "rgmii1_rxclk",
+ "rgmii1_rxdv", "rgmii1_rxd0", "rgmii1_rxd1", "rgmii1_rxd2",
+ "rgmii1_rxd3", "rgmii1_mdc", "rgmii1_mdio", "rgmii1_intb";
+ function = "rgmii";
+ };
+
+ /omit-if-no-ref/
+ i2s0_pins: i2s0-pins {
+ pins = "i2s0_bclk", "i2s0_wclk", "i2s0_sdi", "i2s0_sdo", "i2s_mclk";
+ function = "i2s";
+ };
+
+ /omit-if-no-ref/
+ i2s1_pins: i2s1-pins {
+ pins = "i2s1_bclk", "i2s1_wclk", "i2s1_sdi", "i2s1_sdo", "i2s_mclk";
+ function = "i2s";
+ };
+
+ /omit-if-no-ref/
+ i2s2_pins: i2s2-pins {
+ pins = "i2s2_bclk", "i2s2_wclk", "i2s2_sdi", "i2s2_sdo", "i2s_mclk";
+ function = "i2s";
+ };
+
+ /omit-if-no-ref/
+ usb0_pwren_pins: usb0-pwren-pins {
+ pins = "usb0_pwren";
+ function = "usb";
+ };
+
+ /omit-if-no-ref/
+ usb1_pwren_pins: usb1-pwren-pins {
+ pins = "usb1_pwren";
+ function = "usb";
+ };
+
+ /omit-if-no-ref/
+ i2c0_pins: i2c0-pins {
+ pins = "i2c0_scl", "i2c0_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c1_pins: i2c1-pins {
+ pins = "i2c1_scl", "i2c1_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c2_pins: i2c2-pins {
+ pins = "i2c2_scl", "i2c2_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c3_pins: i2c3-pins {
+ pins = "i2c3_scl", "i2c3_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c4_pins: i2c4-pins {
+ pins = "i2c4_scl", "i2c4_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c5_pins: i2c5-pins {
+ pins = "i2c5_scl", "i2c5_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c8_pins: i2c8-pins {
+ pins = "gpio92", "gpio93";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c10_pins: i2c10-pins {
+ pins = "i2c10_scl", "i2c10_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c11_pins: i2c11-pins {
+ pins = "i2c11_scl", "i2c11_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ uart0_pins: uart0-pins {
+ pins = "uart0_tx", "uart0_rx";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ uart1_pins: uart1-pins {
+ pins = "uart1_tx", "uart1_rx";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ uart1_cts_rts_pins: uart1-cts-rts-pins {
+ pins = "uart1_cts", "uart1_rts";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ uart2_pins: uart2-pins {
+ pins = "uart2_tx", "uart2_rx";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ fan_pwm_pins: fan-pwm-pins {
+ pins = "fan_pwm";
+ function = "pwm";
+ };
+
+ /omit-if-no-ref/
+ fan_tach_pins: fan-tach-pins {
+ pins = "fan_tach";
+ function = "fan_tach";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi0_pins: mipi-csi0-pins {
+ pins = "mipi_csi0_xvs", "mipi_csi0_xhs", "mipi_csi0_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi1_pins: mipi-csi1-pins {
+ pins = "mipi_csi1_xvs", "mipi_csi1_xhs", "mipi_csi1_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi2_pins: mipi-csi2-pins {
+ pins = "mipi_csi2_xvs", "mipi_csi2_xhs", "mipi_csi2_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi3_pins: mipi-csi3-pins {
+ pins = "mipi_csi3_xvs", "mipi_csi3_xhs", "mipi_csi3_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi4_pins: mipi-csi4-pins {
+ pins = "mipi_csi4_xvs", "mipi_csi4_xhs", "mipi_csi4_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi5_pins: mipi-csi5-pins {
+ pins = "mipi_csi5_xvs", "mipi_csi5_xhs", "mipi_csi5_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ s_mode_pins: s-mode-pins {
+ pins = "s_mode";
+ function = "s_mode";
+ };
+
+ /omit-if-no-ref/
+ boot_sel0_pins: boot-sel0-pins {
+ pins = "boot_sel0";
+ function = "boot_sel";
+ };
+
+ /omit-if-no-ref/
+ boot_sel1_pins: boot-sel1-pins {
+ pins = "boot_sel1";
+ function = "boot_sel";
+ };
+
+ /omit-if-no-ref/
+ boot_sel2_pins: boot-sel2-pins {
+ pins = "boot_sel2";
+ function = "boot_sel";
+ };
+
+ /omit-if-no-ref/
+ boot_sel3_pins: boot-sel3-pins {
+ pins = "boot_sel3";
+ function = "boot_sel";
+ };
+
+ /omit-if-no-ref/
+ ddr_ref_clk_sel_pins: ddr-ref-clk-sel-pins {
+ pins = "gpio95";
+ function = "ddr_ref_clk_sel";
+ };
+
+ /omit-if-no-ref/
+ lpddr_ref_clk_pins: lpddr-ref-clk-pins {
+ pins = "lpddr_ref_clk";
+ function = "lpddr_ref_clk";
+ };
+
+ /omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ pins = "spi0_cs_n", "spi0_clk", "spi0_d0", "spi0_d1", "spi0_d2",
+ "spi0_d3";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ dual_spi1_pins: dual-spi1-pins {
+ pins = "spi1_cs0_n", "spi1_clk", "spi1_d0", "spi1_d1";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ quad_spi1_pins: quad-spi1-pins {
+ pins = "spi1_cs1_n", "spi1_d2", "spi1_d3";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ spi3_pins: spi3-pins {
+ pins = "spi3_cs_n", "spi3_clk", "spi3_di", "spi3_do";
+ function = "spi";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index b3a230870315..b16e3e28632c 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -349,6 +349,11 @@ gpioD: gpio-port@3 {
};
};
+ pinctrl: pinctrl@51600080 {
+ compatible = "eswin,eic7700-pinctrl";
+ reg = <0x0 0x51600080 0x0 0x1fff80>;
+ };
+
clk: clock-controller@51828000 {
compatible = "eswin,eic7700-clock";
reg = <0x0 0x51828000 0x0 0x300>;
--
2.34.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 3/7] riscv: dts: eswin: eic7700: add pinctrl support
@ 2026-10-15 12:54 ` Pinkesh Vaghela
0 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Yulin Lu <luyulin@eswincomputing.com>
Add pinctrl node and related pin configuration for EIC7700 SoC
Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../dts/eswin/eic7700-hifive-premier-p550.dts | 34 +
.../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 1065 +++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 5 +
3 files changed, 1104 insertions(+)
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index a5c76b14a38f..afae15bda70a 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "eic7700.dtsi"
+#include "eic7700-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
@@ -18,6 +20,30 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio84_pins>;
+
+ led-0 {
+ gpios = <&gpioC 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ vcc_1v8: regulator-vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&gpio84_pins {
+ bias-disable;
+ input-disable;
};
&osc {
@@ -25,10 +51,18 @@ &osc {
clock-output-names = "osc_24m";
};
+&pinctrl {
+ vrgmii-supply = <&vcc_1v8>;
+};
+
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
};
&uart2 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
new file mode 100644
index 000000000000..c11f42e79c6e
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
@@ -0,0 +1,1065 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
+ *
+ * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+&pinctrl {
+ default-pins-grp {
+ /omit-if-no-ref/
+ sata_act_led_pins: sata-act-led-pins {
+ pins = "gpio27";
+ function = "sata";
+ };
+
+ /omit-if-no-ref/
+ emmc_led_ctrl_pins: emmc-led-ctrl-pins {
+ pins = "gpio29";
+ function = "emmc";
+ };
+
+ /omit-if-no-ref/
+ sd0_led_ctrl_pins: sd0-led-ctrl-pins {
+ pins = "gpio34";
+ function = "sdio";
+ };
+
+ /omit-if-no-ref/
+ sd1_led_ctrl_pins: sd1-led-ctrl-pins {
+ pins = "spi1_d2";
+ function = "sdio";
+ };
+
+ /omit-if-no-ref/
+ i2c6_pins: i2c6-pins {
+ pins = "uart1_cts", "uart1_rts";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c7_pins: i2c7-pins {
+ pins = "uart2_tx", "uart2_rx";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c9_pins: i2c9-pins {
+ pins = "spi1_d0", "spi1_d1";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ pwm1_pins: pwm1-pins {
+ pins = "spi1_d3";
+ function = "pwm";
+ };
+
+ /omit-if-no-ref/
+ pwm2_pins: pwm2-pins {
+ pins = "spi1_cs1_n";
+ function = "pwm";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi_xtrig0_pins: mipi-csi-xtrig0-pins {
+ pins = "gpio92";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi_xtrig1_pins: mipi-csi-xtrig1-pins {
+ pins = "gpio93";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ dual_spi2_pins: dual-spi2-pins {
+ pins = "spi2_cs0_n", "jtag0_tck", "jtag0_tms", "jtag0_tdi";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ quad_spi2_pins: quad-spi2-pins {
+ pins = "spi2_cs1_n", "jtag0_tdo", "gpio5";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ gpio1_pins: gpio1-pins {
+ pins = "jtag0_tck";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio2_pins: gpio2-pins {
+ pins = "jtag0_tms";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio3_pins: gpio3-pins {
+ pins = "jtag0_tdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio4_pins: gpio4-pins {
+ pins = "jtag0_tdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio6_pins: gpio6-pins {
+ pins = "spi2_cs0_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio7_pins: gpio7-pins {
+ pins = "jtag1_tck";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio8_pins: gpio8-pins {
+ pins = "jtag1_tms";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio9_pins: gpio9-pins {
+ pins = "jtag1_tdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio10_pins: gpio10-pins {
+ pins = "jtag1_tdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio12_pins: gpio12-pins {
+ pins = "spi2_cs1_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio13_pins: gpio13-pins {
+ pins = "mode_set0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio14_pins: gpio14-pins {
+ pins = "mode_set1";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio15_pins: gpio15-pins {
+ pins = "mode_set2";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio16_pins: gpio16-pins {
+ pins = "mode_set3";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio17_pins: gpio17-pins {
+ pins = "jtag2_trst";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio18_pins: gpio18-pins {
+ pins = "i2s0_bclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio19_pins: gpio19-pins {
+ pins = "i2s0_wclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio20_pins: gpio20-pins {
+ pins = "i2s0_sdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio21_pins: gpio21-pins {
+ pins = "i2s0_sdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio22_pins: gpio22-pins {
+ pins = "i2s_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio23_pins: gpio23-pins {
+ pins = "i2s2_bclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio24_pins: gpio24-pins {
+ pins = "i2s2_wclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio25_pins: gpio25-pins {
+ pins = "i2s2_sdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio26_pins: gpio26-pins {
+ pins = "i2s2_sdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio29_pins: gpio29-pins {
+ pins = "gpio29";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio30_pins: gpio30-pins {
+ pins = "i2s1_bclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio31_pins: gpio31-pins {
+ pins = "i2s1_wclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio32_pins: gpio32-pins {
+ pins = "i2s1_sdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio33_pins: gpio33-pins {
+ pins = "i2s1_sdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio34_pins: gpio34-pins {
+ pins = "gpio34";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio35_pins: gpio35-pins {
+ pins = "spi1_cs0_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio36_pins: gpio36-pins {
+ pins = "spi1_clk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio37_pins: gpio37-pins {
+ pins = "spi1_d0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio38_pins: gpio38-pins {
+ pins = "spi1_d1";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio39_pins: gpio39-pins {
+ pins = "spi1_d2";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio40_pins: gpio40-pins {
+ pins = "spi1_d3";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio41_pins: gpio41-pins {
+ pins = "spi1_cs1_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio42_pins: gpio42-pins {
+ pins = "usb0_pwren";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio43_pins: gpio43-pins {
+ pins = "usb1_pwren";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio44_pins: gpio44-pins {
+ pins = "i2c0_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio45_pins: gpio45-pins {
+ pins = "i2c0_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio46_pins: gpio46-pins {
+ pins = "i2c1_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio47_pins: gpio47-pins {
+ pins = "i2c1_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio48_pins: gpio48-pins {
+ pins = "i2c2_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio49_pins: gpio49-pins {
+ pins = "i2c2_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio50_pins: gpio50-pins {
+ pins = "i2c3_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio51_pins: gpio51-pins {
+ pins = "i2c3_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio52_pins: gpio52-pins {
+ pins = "i2c4_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio53_pins: gpio53-pins {
+ pins = "i2c4_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio54_pins: gpio54-pins {
+ pins = "i2c5_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio55_pins: gpio55-pins {
+ pins = "i2c5_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio56_pins: gpio56-pins {
+ pins = "uart0_tx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio57_pins: gpio57-pins {
+ pins = "uart0_rx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio58_pins: gpio58-pins {
+ pins = "uart1_tx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio59_pins: gpio59-pins {
+ pins = "uart1_rx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio60_pins: gpio60-pins {
+ pins = "uart1_cts";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio61_pins: gpio61-pins {
+ pins = "uart1_rts";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio62_pins: gpio62-pins {
+ pins = "uart2_tx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio63_pins: gpio63-pins {
+ pins = "uart2_rx";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio64_pins: gpio64-pins {
+ pins = "jtag2_tck";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio65_pins: gpio65-pins {
+ pins = "jtag2_tms";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio66_pins: gpio66-pins {
+ pins = "jtag2_tdi";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio67_pins: gpio67-pins {
+ pins = "jtag2_tdo";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio68_pins: gpio68-pins {
+ pins = "fan_pwm";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio69_pins: gpio69-pins {
+ pins = "fan_tach";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio70_pins: gpio70-pins {
+ pins = "mipi_csi0_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio71_pins: gpio71-pins {
+ pins = "mipi_csi0_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio72_pins: gpio72-pins {
+ pins = "mipi_csi0_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio73_pins: gpio73-pins {
+ pins = "mipi_csi1_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio74_pins: gpio74-pins {
+ pins = "mipi_csi1_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio75_pins: gpio75-pins {
+ pins = "mipi_csi1_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio76_pins: gpio76-pins {
+ pins = "mipi_csi2_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio77_pins: gpio77-pins {
+ pins = "mipi_csi2_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio78_pins: gpio78-pins {
+ pins = "mipi_csi2_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio79_pins: gpio79-pins {
+ pins = "mipi_csi3_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio80_pins: gpio80-pins {
+ pins = "mipi_csi3_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio81_pins: gpio81-pins {
+ pins = "mipi_csi3_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio82_pins: gpio82-pins {
+ pins = "mipi_csi4_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio83_pins: gpio83-pins {
+ pins = "mipi_csi4_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio84_pins: gpio84-pins {
+ pins = "mipi_csi4_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio85_pins: gpio85-pins {
+ pins = "mipi_csi5_xvs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio86_pins: gpio86-pins {
+ pins = "mipi_csi5_xhs";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio87_pins: gpio87-pins {
+ pins = "mipi_csi5_mclk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio88_pins: gpio88-pins {
+ pins = "spi3_cs_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio89_pins: gpio89-pins {
+ pins = "spi3_clk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio90_pins: gpio90-pins {
+ pins = "spi3_di";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio91_pins: gpio91-pins {
+ pins = "spi3_do";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio92_pins: gpio92-pins {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio93_pins: gpio93-pins {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio94_pins: gpio94-pins {
+ pins = "s_mode";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio95_pins: gpio95-pins {
+ pins = "gpio95";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio96_pins: gpio96-pins {
+ pins = "spi0_cs_n";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio97_pins: gpio97-pins {
+ pins = "spi0_clk";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio98_pins: gpio98-pins {
+ pins = "spi0_d0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio99_pins: gpio99-pins {
+ pins = "spi0_d1";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio100_pins: gpio100-pins {
+ pins = "spi0_d2";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio101_pins: gpio101-pins {
+ pins = "spi0_d3";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio102_pins: gpio102-pins {
+ pins = "i2c10_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio103_pins: gpio103-pins {
+ pins = "i2c10_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio104_pins: gpio104-pins {
+ pins = "i2c11_scl";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio105_pins: gpio105-pins {
+ pins = "i2c11_sda";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio107_pins: gpio107-pins {
+ pins = "boot_sel0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio108_pins: gpio108-pins {
+ pins = "boot_sel1";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio109_pins: gpio109-pins {
+ pins = "boot_sel2";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio110_pins: gpio110-pins {
+ pins = "boot_sel3";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ uart3_pins: uart3-pins {
+ pins = "gpio92", "gpio93";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ uart4_pins: uart4-pins {
+ pins = "spi1_d0", "spi1_d1";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ gpio0_pins: gpio0-pins {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio5_pins: gpio5-pins {
+ pins = "gpio5";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio11_pins: gpio11-pins {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio27_pins: gpio27-pins {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio28_pins: gpio28-pins {
+ pins = "gpio28";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio106_pins: gpio106-pins {
+ pins = "gpio106";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ gpio111_pins: gpio111-pins {
+ pins = "gpio111";
+ function = "gpio";
+ };
+
+ /omit-if-no-ref/
+ chip_mode_pins: chip-mode-pins {
+ pins = "chip_mode";
+ function = "chip_mode";
+ };
+
+ /omit-if-no-ref/
+ sdio0_pins: sdio0-pins {
+ pins = "mode_set0", "mode_set1";
+ function = "sdio";
+ };
+
+ /omit-if-no-ref/
+ sdio1_pins: sdio1-pins {
+ pins = "mode_set2", "mode_set3";
+ function = "sdio";
+ };
+
+ /omit-if-no-ref/
+ jtag0_pins: jtag0-pins {
+ pins = "jtag0_tck", "jtag0_tms", "jtag0_tdi", "jtag0_tdo";
+ function = "jtag";
+ };
+
+ /omit-if-no-ref/
+ jtag1_pins: jtag1-pins {
+ pins = "jtag1_tck", "jtag1_tms", "jtag1_tdi", "jtag1_tdo";
+ function = "jtag";
+ };
+
+ /omit-if-no-ref/
+ jtag2_pins: jtag2-pins {
+ pins = "jtag2_trst", "jtag2_tck", "jtag2_tms", "jtag2_tdi",
+ "jtag2_tdo";
+ function = "jtag";
+ };
+
+ /omit-if-no-ref/
+ pcie_pins: pcie-pins {
+ pins = "pcie_clkreq_n", "pcie_wake_n", "pcie_perst_n";
+ function = "pcie";
+ };
+
+ /omit-if-no-ref/
+ hdmi_pins: hdmi-pins {
+ pins = "hdmi_scl", "hdmi_sda", "hdmi_cec";
+ function = "hdmi";
+ };
+
+ /omit-if-no-ref/
+ rgmii0_pins: rgmii0-pins {
+ pins = "rgmii0_clk_125", "rgmii0_txen", "rgmii0_txclk", "rgmii0_txd0",
+ "rgmii0_txd1", "rgmii0_txd2", "rgmii0_txd3", "rgmii0_rxclk",
+ "rgmii0_rxdv", "rgmii0_rxd0", "rgmii0_rxd1", "rgmii0_rxd2",
+ "rgmii0_rxd3", "rgmii0_mdc", "rgmii0_mdio", "rgmii0_intb";
+ function = "rgmii";
+ };
+
+ /omit-if-no-ref/
+ rgmii1_pins: rgmii1-pins {
+ pins = "rgmii1_clk_125", "rgmii1_txen", "rgmii1_txclk", "rgmii1_txd0",
+ "rgmii1_txd1", "rgmii1_txd2", "rgmii1_txd3", "rgmii1_rxclk",
+ "rgmii1_rxdv", "rgmii1_rxd0", "rgmii1_rxd1", "rgmii1_rxd2",
+ "rgmii1_rxd3", "rgmii1_mdc", "rgmii1_mdio", "rgmii1_intb";
+ function = "rgmii";
+ };
+
+ /omit-if-no-ref/
+ i2s0_pins: i2s0-pins {
+ pins = "i2s0_bclk", "i2s0_wclk", "i2s0_sdi", "i2s0_sdo", "i2s_mclk";
+ function = "i2s";
+ };
+
+ /omit-if-no-ref/
+ i2s1_pins: i2s1-pins {
+ pins = "i2s1_bclk", "i2s1_wclk", "i2s1_sdi", "i2s1_sdo", "i2s_mclk";
+ function = "i2s";
+ };
+
+ /omit-if-no-ref/
+ i2s2_pins: i2s2-pins {
+ pins = "i2s2_bclk", "i2s2_wclk", "i2s2_sdi", "i2s2_sdo", "i2s_mclk";
+ function = "i2s";
+ };
+
+ /omit-if-no-ref/
+ usb0_pwren_pins: usb0-pwren-pins {
+ pins = "usb0_pwren";
+ function = "usb";
+ };
+
+ /omit-if-no-ref/
+ usb1_pwren_pins: usb1-pwren-pins {
+ pins = "usb1_pwren";
+ function = "usb";
+ };
+
+ /omit-if-no-ref/
+ i2c0_pins: i2c0-pins {
+ pins = "i2c0_scl", "i2c0_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c1_pins: i2c1-pins {
+ pins = "i2c1_scl", "i2c1_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c2_pins: i2c2-pins {
+ pins = "i2c2_scl", "i2c2_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c3_pins: i2c3-pins {
+ pins = "i2c3_scl", "i2c3_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c4_pins: i2c4-pins {
+ pins = "i2c4_scl", "i2c4_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c5_pins: i2c5-pins {
+ pins = "i2c5_scl", "i2c5_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c8_pins: i2c8-pins {
+ pins = "gpio92", "gpio93";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c10_pins: i2c10-pins {
+ pins = "i2c10_scl", "i2c10_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ i2c11_pins: i2c11-pins {
+ pins = "i2c11_scl", "i2c11_sda";
+ function = "i2c";
+ };
+
+ /omit-if-no-ref/
+ uart0_pins: uart0-pins {
+ pins = "uart0_tx", "uart0_rx";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ uart1_pins: uart1-pins {
+ pins = "uart1_tx", "uart1_rx";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ uart1_cts_rts_pins: uart1-cts-rts-pins {
+ pins = "uart1_cts", "uart1_rts";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ uart2_pins: uart2-pins {
+ pins = "uart2_tx", "uart2_rx";
+ function = "uart";
+ };
+
+ /omit-if-no-ref/
+ fan_pwm_pins: fan-pwm-pins {
+ pins = "fan_pwm";
+ function = "pwm";
+ };
+
+ /omit-if-no-ref/
+ fan_tach_pins: fan-tach-pins {
+ pins = "fan_tach";
+ function = "fan_tach";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi0_pins: mipi-csi0-pins {
+ pins = "mipi_csi0_xvs", "mipi_csi0_xhs", "mipi_csi0_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi1_pins: mipi-csi1-pins {
+ pins = "mipi_csi1_xvs", "mipi_csi1_xhs", "mipi_csi1_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi2_pins: mipi-csi2-pins {
+ pins = "mipi_csi2_xvs", "mipi_csi2_xhs", "mipi_csi2_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi3_pins: mipi-csi3-pins {
+ pins = "mipi_csi3_xvs", "mipi_csi3_xhs", "mipi_csi3_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi4_pins: mipi-csi4-pins {
+ pins = "mipi_csi4_xvs", "mipi_csi4_xhs", "mipi_csi4_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ mipi_csi5_pins: mipi-csi5-pins {
+ pins = "mipi_csi5_xvs", "mipi_csi5_xhs", "mipi_csi5_mclk";
+ function = "mipi_csi";
+ };
+
+ /omit-if-no-ref/
+ s_mode_pins: s-mode-pins {
+ pins = "s_mode";
+ function = "s_mode";
+ };
+
+ /omit-if-no-ref/
+ boot_sel0_pins: boot-sel0-pins {
+ pins = "boot_sel0";
+ function = "boot_sel";
+ };
+
+ /omit-if-no-ref/
+ boot_sel1_pins: boot-sel1-pins {
+ pins = "boot_sel1";
+ function = "boot_sel";
+ };
+
+ /omit-if-no-ref/
+ boot_sel2_pins: boot-sel2-pins {
+ pins = "boot_sel2";
+ function = "boot_sel";
+ };
+
+ /omit-if-no-ref/
+ boot_sel3_pins: boot-sel3-pins {
+ pins = "boot_sel3";
+ function = "boot_sel";
+ };
+
+ /omit-if-no-ref/
+ ddr_ref_clk_sel_pins: ddr-ref-clk-sel-pins {
+ pins = "gpio95";
+ function = "ddr_ref_clk_sel";
+ };
+
+ /omit-if-no-ref/
+ lpddr_ref_clk_pins: lpddr-ref-clk-pins {
+ pins = "lpddr_ref_clk";
+ function = "lpddr_ref_clk";
+ };
+
+ /omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ pins = "spi0_cs_n", "spi0_clk", "spi0_d0", "spi0_d1", "spi0_d2",
+ "spi0_d3";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ dual_spi1_pins: dual-spi1-pins {
+ pins = "spi1_cs0_n", "spi1_clk", "spi1_d0", "spi1_d1";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ quad_spi1_pins: quad-spi1-pins {
+ pins = "spi1_cs1_n", "spi1_d2", "spi1_d3";
+ function = "spi";
+ };
+
+ /omit-if-no-ref/
+ spi3_pins: spi3-pins {
+ pins = "spi3_cs_n", "spi3_clk", "spi3_di", "spi3_do";
+ function = "spi";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index b3a230870315..b16e3e28632c 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -349,6 +349,11 @@ gpioD: gpio-port@3 {
};
};
+ pinctrl: pinctrl@51600080 {
+ compatible = "eswin,eic7700-pinctrl";
+ reg = <0x0 0x51600080 0x0 0x1fff80>;
+ };
+
clk: clock-controller@51828000 {
compatible = "eswin,eic7700-clock";
reg = <0x0 0x51828000 0x0 0x300>;
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v5 4/7] riscv: dts: eswin: add hsp bus node
2026-10-15 12:54 ` Pinkesh Vaghela
@ 2026-10-15 12:54 ` Pinkesh Vaghela
-1 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
Add an HSP bus node to manage the HSP CFG clock used by HSP
peripherals. This clock is required for accessing both the HSP CSR
registers and the register spaces of HSP peripheral devices.
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index b16e3e28632c..771a88645d83 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -252,6 +252,19 @@ plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
};
+ hsp: bus@50400000 {
+ compatible = "simple-pm-bus";
+ ranges = <0x0 0x50400000 0x0 0x50400000 0x0 0xa0000>;
+ clocks = <&clk EIC7700_CLK_GATE_HSP_CFG_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ syscon: syscon@50440000 {
+ compatible = "eswin,eic7700-syscfg", "syscon";
+ reg = <0x0 0x50440000 0x0 0x2000>;
+ };
+ };
+
uart0: serial@50900000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x50900000 0x0 0x10000>;
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 4/7] riscv: dts: eswin: add hsp bus node
@ 2026-10-15 12:54 ` Pinkesh Vaghela
0 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
Add an HSP bus node to manage the HSP CFG clock used by HSP
peripherals. This clock is required for accessing both the HSP CSR
registers and the register spaces of HSP peripheral devices.
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index b16e3e28632c..771a88645d83 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -252,6 +252,19 @@ plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
};
+ hsp: bus@50400000 {
+ compatible = "simple-pm-bus";
+ ranges = <0x0 0x50400000 0x0 0x50400000 0x0 0xa0000>;
+ clocks = <&clk EIC7700_CLK_GATE_HSP_CFG_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ syscon: syscon@50440000 {
+ compatible = "eswin,eic7700-syscfg", "syscon";
+ reg = <0x0 0x50440000 0x0 0x2000>;
+ };
+ };
+
uart0: serial@50900000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x50900000 0x0 0x10000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: eswin: add hsp bus node
2026-10-15 12:54 ` Pinkesh Vaghela
(?)
@ 2026-10-15 13:09 ` sashiko-bot
-1 siblings, 0 replies; 17+ messages in thread
From: sashiko-bot @ 2026-10-15 13:09 UTC (permalink / raw)
To: Pinkesh Vaghela, devicetree; +Cc: robh, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dts: unclocked syscon MMIO access due to missing clocks property
--
commit 411f5ceff131ac2449926a00c5f169d3aa665b6d
Author: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
riscv: dts: eswin: add hsp bus node
This commit adds an HSP bus node to manage the HSP CFG clock used by HSP
peripherals. This clock is required for accessing both the HSP CSR registers
and the register spaces of HSP peripheral devices.
> diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> @@ -252,6 +252,19 @@ plic: interrupt-controller@c000000 {
> #interrupt-cells = <1>;
> };
>
> + hsp: bus@50400000 {
> + compatible = "simple-pm-bus";
> + ranges = <0x0 0x50400000 0x0 0x50400000 0x0 0xa0000>;
> + clocks = <&clk EIC7700_CLK_GATE_HSP_CFG_CLK>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + syscon: syscon@50440000 {
> + compatible = "eswin,eic7700-syscfg", "syscon";
> + reg = <0x0 0x50440000 0x0 0x2000>;
> + };
[Severity: High]
Will accessing this syscon node result in an unclocked MMIO fault?
The syscon node lacks a clocks property and seems to rely on the parent
simple-pm-bus for clocks. However, generic syscon does not trigger parent
runtime PM.
When looking at of_syscon_register() in drivers/mfd/syscon.c, it only attaches
a clock if the clocks property is present on the syscon node itself:
drivers/mfd/syscon.c:of_syscon_register() {
...
if (check_res) {
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
/* clock is optional */
if (ret != -ENOENT)
goto err_clk;
} else {
ret = regmap_mmio_attach_clk(regmap, clk);
...
}
Meanwhile, looking at simple_pm_bus_probe() in drivers/bus/simple-pm-bus.c,
the simple-pm-bus only enables runtime PM:
drivers/bus/simple-pm-bus.c:simple_pm_bus_probe() {
...
pm_runtime_enable(&pdev->dev);
if (np)
of_platform_populate(np, NULL, lookup, &pdev->dev);
...
}
Since simple-pm-bus strictly relies on children to wake it up, and syscon
bypasses platform_device PM entirely, the bus is never resumed. Does this
mean any driver or debugfs interface accessing the eswin,eic7700-syscfg
regmap will perform MMIO without enabling the HSP_CFG_CLK?
> + };
> +
> uart0: serial@50900000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x0 0x50900000 0x0 0x10000>;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261015125454.1381941-1-pinkesh.vaghela@einfochips.com?part=4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v5 5/7] dt-bindings: i2c: dw: add ESWIN EIC7700 SoC I2C controller
2026-10-15 12:54 ` Pinkesh Vaghela
@ 2026-10-15 12:54 ` Pinkesh Vaghela
-1 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add compatible string for the DesignWare-based I2C controllers present
in ESWIN EIC7700 SoC.
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index a73e2a6e0833..76f09b68bd51 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -54,6 +54,7 @@ properties:
- const: snps,designware-i2c
- items:
- enum:
+ - eswin,eic7700-i2c
- mobileye,eyeq6lplus-i2c
- mscc,ocelot-i2c
- sophgo,sg2044-i2c
--
2.34.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 5/7] dt-bindings: i2c: dw: add ESWIN EIC7700 SoC I2C controller
@ 2026-10-15 12:54 ` Pinkesh Vaghela
0 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add compatible string for the DesignWare-based I2C controllers present
in ESWIN EIC7700 SoC.
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index a73e2a6e0833..76f09b68bd51 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -54,6 +54,7 @@ properties:
- const: snps,designware-i2c
- items:
- enum:
+ - eswin,eic7700-i2c
- mobileye,eyeq6lplus-i2c
- mscc,ocelot-i2c
- sophgo,sg2044-i2c
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v5 6/7] riscv: dts: eswin: add I2C controller support
2026-10-15 12:54 ` Pinkesh Vaghela
@ 2026-10-15 12:54 ` Pinkesh Vaghela
-1 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add I2C nodes for EIC7700 SoC.
Also add nodes for corresponding slave devices in dts file and
enable them for HiFive Premier P550 board
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../dts/eswin/eic7700-hifive-premier-p550.dts | 52 +++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 181 ++++++++++++++++++
2 files changed, 233 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index afae15bda70a..8ff19a48e209 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -41,6 +41,58 @@ vcc_1v8: regulator-vcc1v8 {
};
};
+&aon_i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+};
+
+&aon_i2c1 {
+ status = "okay";
+
+ adc@10 {
+ compatible = "microchip,pac1934";
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@1 {
+ reg = <0x1>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_SOM";
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_SOC";
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_CPU";
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_LPDDR";
+ };
+ };
+
+ power-sensor@44 {
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ #io-channel-cells = <1>;
+ label = "sys_power";
+ shunt-resistor = <1000>;
+ };
+};
+
&gpio84_pins {
bias-disable;
input-disable;
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 771a88645d83..c0aa91b357ff 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -315,6 +315,156 @@ uart4: serial@50940000 {
status = "disabled";
};
+ i2c0: i2c@50950000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50950000 0x0 0x8000>;
+ interrupts = <105>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C0_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ resets = <&reset EIC7700_RESET_I2C0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@50960000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50960000 0x0 0x8000>;
+ interrupts = <106>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C1_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ resets = <&reset EIC7700_RESET_I2C1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@50970000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50970000 0x0 0x8000>;
+ interrupts = <107>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C2_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ resets = <&reset EIC7700_RESET_I2C2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@50980000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50980000 0x0 0x8000>;
+ interrupts = <108>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C3_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ resets = <&reset EIC7700_RESET_I2C3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@50990000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50990000 0x0 0x8000>;
+ interrupts = <109>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C4_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ resets = <&reset EIC7700_RESET_I2C4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@509a0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509a0000 0x0 0x8000>;
+ interrupts = <110>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C5_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ resets = <&reset EIC7700_RESET_I2C5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@509b0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509b0000 0x0 0x8000>;
+ interrupts = <111>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C6_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ resets = <&reset EIC7700_RESET_I2C6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@509c0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509c0000 0x0 0x8000>;
+ interrupts = <112>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C7_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pins>;
+ resets = <&reset EIC7700_RESET_I2C7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@509d0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509d0000 0x0 0x8000>;
+ interrupts = <113>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C8_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8_pins>;
+ resets = <&reset EIC7700_RESET_I2C8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@509e0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509e0000 0x0 0x8000>;
+ interrupts = <114>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C9_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c9_pins>;
+ resets = <&reset EIC7700_RESET_I2C9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gpio@51600000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x51600000 0x0 0x80>;
@@ -379,5 +529,36 @@ reset: reset-controller@51828300 {
reg = <0x0 0x51828300 0x0 0x200>;
#reset-cells = <1>;
};
+
+ aon_i2c0: i2c@51830000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x51830000 0x0 0x8000>;
+ interrupts = <290>;
+ clocks = <&clk EIC7700_CLK_GATE_AON_I2C0_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c10_pins>;
+ resets = <&reset EIC7700_RESET_ANO0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ aon_i2c1: i2c@51838000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x51838000 0x0 0x8000>;
+ interrupts = <291>;
+ clocks = <&clk EIC7700_CLK_GATE_AON_I2C1_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c11_pins>;
+ resets = <&reset EIC7700_RESET_ANO1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
};
};
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 6/7] riscv: dts: eswin: add I2C controller support
@ 2026-10-15 12:54 ` Pinkesh Vaghela
0 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add I2C nodes for EIC7700 SoC.
Also add nodes for corresponding slave devices in dts file and
enable them for HiFive Premier P550 board
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../dts/eswin/eic7700-hifive-premier-p550.dts | 52 +++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 181 ++++++++++++++++++
2 files changed, 233 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index afae15bda70a..8ff19a48e209 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -41,6 +41,58 @@ vcc_1v8: regulator-vcc1v8 {
};
};
+&aon_i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+};
+
+&aon_i2c1 {
+ status = "okay";
+
+ adc@10 {
+ compatible = "microchip,pac1934";
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@1 {
+ reg = <0x1>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_SOM";
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_SOC";
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_CPU";
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_LPDDR";
+ };
+ };
+
+ power-sensor@44 {
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ #io-channel-cells = <1>;
+ label = "sys_power";
+ shunt-resistor = <1000>;
+ };
+};
+
&gpio84_pins {
bias-disable;
input-disable;
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 771a88645d83..c0aa91b357ff 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -315,6 +315,156 @@ uart4: serial@50940000 {
status = "disabled";
};
+ i2c0: i2c@50950000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50950000 0x0 0x8000>;
+ interrupts = <105>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C0_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ resets = <&reset EIC7700_RESET_I2C0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@50960000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50960000 0x0 0x8000>;
+ interrupts = <106>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C1_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ resets = <&reset EIC7700_RESET_I2C1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@50970000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50970000 0x0 0x8000>;
+ interrupts = <107>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C2_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ resets = <&reset EIC7700_RESET_I2C2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@50980000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50980000 0x0 0x8000>;
+ interrupts = <108>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C3_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ resets = <&reset EIC7700_RESET_I2C3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@50990000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x50990000 0x0 0x8000>;
+ interrupts = <109>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C4_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ resets = <&reset EIC7700_RESET_I2C4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@509a0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509a0000 0x0 0x8000>;
+ interrupts = <110>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C5_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ resets = <&reset EIC7700_RESET_I2C5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@509b0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509b0000 0x0 0x8000>;
+ interrupts = <111>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C6_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ resets = <&reset EIC7700_RESET_I2C6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@509c0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509c0000 0x0 0x8000>;
+ interrupts = <112>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C7_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pins>;
+ resets = <&reset EIC7700_RESET_I2C7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@509d0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509d0000 0x0 0x8000>;
+ interrupts = <113>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C8_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8_pins>;
+ resets = <&reset EIC7700_RESET_I2C8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@509e0000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x509e0000 0x0 0x8000>;
+ interrupts = <114>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C9_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c9_pins>;
+ resets = <&reset EIC7700_RESET_I2C9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gpio@51600000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x51600000 0x0 0x80>;
@@ -379,5 +529,36 @@ reset: reset-controller@51828300 {
reg = <0x0 0x51828300 0x0 0x200>;
#reset-cells = <1>;
};
+
+ aon_i2c0: i2c@51830000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x51830000 0x0 0x8000>;
+ interrupts = <290>;
+ clocks = <&clk EIC7700_CLK_GATE_AON_I2C0_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c10_pins>;
+ resets = <&reset EIC7700_RESET_ANO0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ aon_i2c1: i2c@51838000 {
+ compatible = "eswin,eic7700-i2c", "snps,designware-i2c";
+ reg = <0x0 0x51838000 0x0 0x8000>;
+ interrupts = <291>;
+ clocks = <&clk EIC7700_CLK_GATE_AON_I2C1_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c11_pins>;
+ resets = <&reset EIC7700_RESET_ANO1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v5 7/7] riscv: dts: eswin: add watchdog support
2026-10-15 12:54 ` Pinkesh Vaghela
@ 2026-10-15 12:54 ` Pinkesh Vaghela
-1 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
EIC7700 have four DesignWare watchdog controllers that are
integrated to SoC.
The controllers use only SoC-internal register, interrupt, clock and
reset resources and have no board-level dependencies, so describe them
as available in the SoC DTSI.
Each watchdog counter is driven by its corresponding LSP APB clock.
The NOC_WDREF clock belongs to the separate NoC watchdog and is not
used by these controller instances.
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
arch/riscv/boot/dts/eswin/eic7700.dtsi | 36 ++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c0aa91b357ff..ec58a3aaf582 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -265,6 +265,42 @@ syscon: syscon@50440000 {
};
};
+ wdt0: watchdog@50800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50800000 0x0 0x4000>;
+ interrupts = <87>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT0>;
+ };
+
+ wdt1: watchdog@50804000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50804000 0x0 0x4000>;
+ interrupts = <88>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT1>;
+ };
+
+ wdt2: watchdog@50808000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50808000 0x0 0x4000>;
+ interrupts = <89>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT2>;
+ };
+
+ wdt3: watchdog@5080c000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x5080c000 0x0 0x4000>;
+ interrupts = <90>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT3>;
+ };
+
uart0: serial@50900000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x50900000 0x0 0x10000>;
--
2.34.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 7/7] riscv: dts: eswin: add watchdog support
@ 2026-10-15 12:54 ` Pinkesh Vaghela
0 siblings, 0 replies; 17+ messages in thread
From: Pinkesh Vaghela @ 2026-10-15 12:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Andi Shyti,
Mika Westerberg, linux-i2c, devicetree, linux-kernel, linux-riscv,
Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
From: Pritesh Patel <pritesh.patel@einfochips.com>
EIC7700 have four DesignWare watchdog controllers that are
integrated to SoC.
The controllers use only SoC-internal register, interrupt, clock and
reset resources and have no board-level dependencies, so describe them
as available in the SoC DTSI.
Each watchdog counter is driven by its corresponding LSP APB clock.
The NOC_WDREF clock belongs to the separate NoC watchdog and is not
used by these controller instances.
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
arch/riscv/boot/dts/eswin/eic7700.dtsi | 36 ++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c0aa91b357ff..ec58a3aaf582 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -265,6 +265,42 @@ syscon: syscon@50440000 {
};
};
+ wdt0: watchdog@50800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50800000 0x0 0x4000>;
+ interrupts = <87>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT0>;
+ };
+
+ wdt1: watchdog@50804000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50804000 0x0 0x4000>;
+ interrupts = <88>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT1>;
+ };
+
+ wdt2: watchdog@50808000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50808000 0x0 0x4000>;
+ interrupts = <89>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT2>;
+ };
+
+ wdt3: watchdog@5080c000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x5080c000 0x0 0x4000>;
+ interrupts = <90>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT3>;
+ };
+
uart0: serial@50900000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x50900000 0x0 0x10000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread