[PATCH 0/2] drm/panthor: Consistently delegate shader power

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* [PATCH 0/2] drm/panthor: Consistently delegate shader power
@ 2026-10-15 13:10 Daniel Stone
  2026-10-15 13:10 ` [PATCH 1/2] drm/panthor: Add neural-engine presence and power bits for v14+ Daniel Stone
  2026-10-15 13:10 ` [PATCH 2/2] drm/panthor: Delegate neural power domain to CSF when present Daniel Stone
  0 siblings, 2 replies; 5+ messages in thread
From: Daniel Stone @ 2026-10-15 13:10 UTC (permalink / raw)
  To: dri-devel
  Cc: boris.brezillon, laura.nao, adrian.larumbe, daniel.almeida,
	liviu.dudau

Hi,
When trying to bring up a v14 platform, one trap I fell into was
inconsistent power-domain delegation. When delegating a domain, all of
its child domains need to be already delegated, so the firmware can
exercise effective control.

We unconditionally delegate the L2 domain to firmware power management,
along with the tiler and shader domains, however the neural-engine power
domain is also a child of L2 and not delegated. Failing to do this
results in the firmware going into a loop when attempting to power up
the shader cores for the first time.

Cheers,
Daniel

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/2] drm/panthor: Add neural-engine presence and power bits for v14+
  2026-10-15 13:10 [PATCH 0/2] drm/panthor: Consistently delegate shader power Daniel Stone
@ 2026-10-15 13:10 ` Daniel Stone
  2026-10-15 13:10 ` [PATCH 2/2] drm/panthor: Delegate neural power domain to CSF when present Daniel Stone
  1 sibling, 0 replies; 5+ messages in thread
From: Daniel Stone @ 2026-10-15 13:10 UTC (permalink / raw)
  To: dri-devel
  Cc: boris.brezillon, laura.nao, adrian.larumbe, daniel.almeida,
	liviu.dudau

Mali v14+ can optionally feature a neural engine. This is not currently
used by Panthor, but add the bare-minimum bits required to detect the
engine's presence and control its power.

Signed-off-by: Daniel Stone <daniels@collabora.com>
---
 drivers/gpu/drm/panthor/panthor_gpu_regs.h | 1 +
 drivers/gpu/drm/panthor/panthor_hw.h       | 6 ++++++
 drivers/gpu/drm/panthor/panthor_pwr_regs.h | 7 +++++++
 3 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
index 4c5b953796e4f..5340966caef37 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
@@ -67,6 +67,7 @@
 
 #define GPU_FEATURES					0x60
 #define   GPU_FEATURES_RAY_INTERSECTION			BIT(2)
+#define   GPU_FEATURES_NEURAL_ENGINE			BIT(4)
 #define   GPU_FEATURES_RAY_TRAVERSAL			BIT(5)
 
 #define GPU_TIMESTAMP_OFFSET				0x88
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index f797663893b2d..924faea27061a 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -61,4 +61,10 @@ static inline bool panthor_hw_has_pwr_ctrl(struct panthor_device *ptdev)
 	return GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >= 14;
 }
 
+static inline bool panthor_hw_has_neural(struct panthor_device *ptdev)
+{
+	return (GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >= 14 &&
+	        ptdev->gpu_info.gpu_features & GPU_FEATURES_NEURAL_ENGINE);
+}
+
 #endif /* __PANTHOR_HW_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_pwr_regs.h b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
index 9cf7a715066f8..80d8e1e522298 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
@@ -20,12 +20,14 @@
 #define   PWR_STATUS_ALLOW_L2				BIT_U64(0)
 #define   PWR_STATUS_ALLOW_TILER			BIT_U64(1)
 #define   PWR_STATUS_ALLOW_SHADER			BIT_U64(8)
+#define   PWR_STATUS_ALLOW_NEURAL			BIT_U64(9)
 #define   PWR_STATUS_ALLOW_BASE				BIT_U64(14)
 #define   PWR_STATUS_ALLOW_STACK			BIT_U64(15)
 #define   PWR_STATUS_DOMAIN_ALLOWED(x)			BIT_U64(x)
 #define   PWR_STATUS_DELEGATED_L2			BIT_U64(16)
 #define   PWR_STATUS_DELEGATED_TILER			BIT_U64(17)
 #define   PWR_STATUS_DELEGATED_SHADER			BIT_U64(24)
+#define   PWR_STATUS_DELEGATED_NEURAL			BIT_U64(25)
 #define   PWR_STATUS_DELEGATED_BASE			BIT_U64(30)
 #define   PWR_STATUS_DELEGATED_STACK			BIT_U64(31)
 #define   PWR_STATUS_DELEGATED_SHIFT			16
@@ -48,6 +50,7 @@
 #define   PWR_COMMAND_DOMAIN_L2				0
 #define   PWR_COMMAND_DOMAIN_TILER			1
 #define   PWR_COMMAND_DOMAIN_SHADER			8
+#define   PWR_COMMAND_DOMAIN_NEURAL			9
 #define   PWR_COMMAND_DOMAIN_BASE			14
 #define   PWR_COMMAND_DOMAIN_STACK			15
 #define   PWR_COMMAND_SUBDOMAIN_RTU			BIT(0)
@@ -68,6 +71,10 @@
 #define PWR_SHADER_READY				0x208
 #define PWR_SHADER_PWRTRANS				0x210
 #define PWR_SHADER_PWRACTIVE				0x218
+#define PWR_NEURAL_PRESENT				0x240
+#define PWR_NEURAL_READY				0x248
+#define PWR_NEURAL_PWRTRANS				0x250
+#define PWR_NEURAL_PWRACTIVE				0x258
 #define PWR_BASE_PRESENT				0x380
 #define PWR_BASE_READY					0x388
 #define PWR_BASE_PWRTRANS				0x390
-- 
2.47.3


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 2/2] drm/panthor: Delegate neural power domain to CSF when present
  2026-10-15 13:10 [PATCH 0/2] drm/panthor: Consistently delegate shader power Daniel Stone
  2026-10-15 13:10 ` [PATCH 1/2] drm/panthor: Add neural-engine presence and power bits for v14+ Daniel Stone
@ 2026-10-15 13:10 ` Daniel Stone
  2026-10-15 13:18   ` sashiko-bot
  1 sibling, 1 reply; 5+ messages in thread
From: Daniel Stone @ 2026-10-15 13:10 UTC (permalink / raw)
  To: dri-devel
  Cc: boris.brezillon, laura.nao, adrian.larumbe, daniel.almeida,
	liviu.dudau

As the neural power domain is a child of the L2 power domain, control
over the L2 domain cannot be delegated to CSF unless the neural domain
has first been delegated. Given that we delegate all power control on
v14+, this eventually causes a hard lock-up and/or firmware OOPS when we
try to power on anything due to the inconsistent delegation state.

Fixes: ee4f9af07933 ("drm/panthor: Implement L2 power on/off via PWR_CONTROL")
Signed-off-by: Daniel Stone <daniels@collabora.com>
---
 drivers/gpu/drm/panthor/panthor_pwr.c | 31 ++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index dd7b6ef8ea209..23954c863cc26 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -146,6 +146,8 @@ static const char *get_domain_name(u8 domain)
 		return "Base";
 	case PWR_COMMAND_DOMAIN_STACK:
 		return "Stack";
+	case PWR_COMMAND_DOMAIN_NEURAL:
+		return "Neural";
 	}
 	return "Unknown";
 }
@@ -163,6 +165,8 @@ static u32 get_domain_base(u8 domain)
 		return PWR_BASE_PRESENT;
 	case PWR_COMMAND_DOMAIN_STACK:
 		return PWR_STACK_PRESENT;
+	case PWR_COMMAND_DOMAIN_NEURAL:
+		return PWR_NEURAL_PRESENT;
 	}
 	return 0;
 }
@@ -229,6 +233,15 @@ static void panthor_pwr_debug_info_show(struct panthor_device *ptdev)
 	drm_info(&ptdev->base, "SHADER_PRESENT:  0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PRESENT));
 	drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PWRTRANS));
 	drm_info(&ptdev->base, "SHADER_READY:    0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_READY));
+
+	if (panthor_hw_has_neural(ptdev)) {
+		drm_info(&ptdev->base, "NEURAL_PRESENT:  0x%016llx",
+			 gpu_read64(pwr->iomem, PWR_NEURAL_PRESENT));
+		drm_info(&ptdev->base, "NEURAL_PWRTRANS: 0x%016llx",
+			 gpu_read64(pwr->iomem, PWR_NEURAL_PWRTRANS));
+		drm_info(&ptdev->base, "NEURAL_READY:    0x%016llx",
+			 gpu_read64(pwr->iomem, PWR_NEURAL_READY));
+	}
 }
 
 static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd, u32 domain,
@@ -405,9 +418,15 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
 	if (!ptdev->pwr)
 		return 0;
 
+	if (panthor_hw_has_neural(ptdev)) {
+		ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
+		if (ret)
+			return ret;
+	}
+
 	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
 	if (ret)
-		return ret;
+		return err_retract_neural;
 
 	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_TILER);
 	if (ret)
@@ -415,6 +434,8 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
 
 	return 0;
 
+err_retract_neural:
+	retract_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
 err_retract_shader:
 	retract_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
 
@@ -517,6 +538,7 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
 	struct panthor_pwr *pwr = ptdev->pwr;
 	const u64 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
 	const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
+	const bool has_neural = panthor_hw_has_neural(ptdev);
 
 	/* Abort if L2 power off constraints are not satisfied */
 	if (!(pwr_status & l2_allow_mask)) {
@@ -530,6 +552,13 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
 	 * host control to be powered down in the right order before powering
 	 * down the L2.
 	 */
+	if (has_neural &&
+	    panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_NEURAL))
+		return;
+
+	if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER))
+		return;
+
 	if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER))
 		return;
 
-- 
2.47.3


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH 2/2] drm/panthor: Delegate neural power domain to CSF when present
  2026-10-15 13:10 ` [PATCH 2/2] drm/panthor: Delegate neural power domain to CSF when present Daniel Stone
@ 2026-10-15 13:18   ` sashiko-bot
  2026-10-15 13:45     ` Daniel Stone
  0 siblings, 1 reply; 5+ messages in thread
From: sashiko-bot @ 2026-10-15 13:18 UTC (permalink / raw)
  To: Daniel Stone, dri-devel

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] panthor: resource leak due to incorrect LIFO label ordering in error path
- [Medium] panthor: incorrect hardware teardown order and duplicate TILER power-off
- [Low] panthor: build failure due to returning a label identifier
--

commit e4aa5571cda90f71765f06232acbfee948feed3e
Author: Daniel Stone <daniels@collabora.com>

drm/panthor: Delegate neural power domain to CSF when present

As the neural power domain is a child of the L2 power domain, control
over the L2 domain cannot be delegated to CSF unless the neural domain
has first been delegated. Given that we delegate all power control on
v14+, this eventually causes a hard lock-up and/or firmware OOPS when we
try to power on anything due to the inconsistent delegation state.

Fixes: ee4f9af07933 ("drm/panthor: Implement L2 power on/off via PWR_CONTROL")

> diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
> index dd7b6ef8ea209..23954c863cc26 100644
> --- a/drivers/gpu/drm/panthor/panthor_pwr.c
> +++ b/drivers/gpu/drm/panthor/panthor_pwr.c

[ ... ]

> @@ -405,9 +418,15 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
>  	if (!ptdev->pwr)
>  		return 0;
>  
> +	if (panthor_hw_has_neural(ptdev)) {
> +		ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
>  	if (ret)
> -		return ret;
> +		return err_retract_neural;

[Severity: Low]
Will this cause a build failure?

Because err_retract_neural is a label and not a declared variable, returning it
is invalid C syntax and results in a compiler error. Should this be a
goto err_retract_neural; instead?

>  	ret = delegate_domain(ptdev, PWR_COMMAND_DOMAIN_TILER);
>  	if (ret)
> @@ -415,6 +434,8 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
>  
>  	return 0;
>  
> +err_retract_neural:
> +	retract_domain(ptdev, PWR_COMMAND_DOMAIN_NEURAL);
>  err_retract_shader:
>  	retract_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER);
>  

[Severity: Medium]
Does this error path leak the NEURAL domain delegation?

The domains are delegated in the order: NEURAL -> SHADER -> TILER. On failure,
they typically must be retracted in reverse order. However, the error labels
are ordered with err_retract_neural: placed before err_retract_shader:.

If TILER delegation fails, the code executes goto err_retract_shader;, retracts
the SHADER domain, and immediately returns, bypassing the err_retract_neural:
block above it.

Should the labels be swapped to correctly implement the teardown?

[ ... ]

> @@ -530,6 +552,13 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
>  	 * host control to be powered down in the right order before powering
>  	 * down the L2.
>  	 */
> +	if (has_neural &&
> +	    panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_NEURAL))
> +		return;
> +
> +	if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER))
> +		return;
> +
>  	if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER))
>  		return;
>  

[Severity: Medium]
Does this execute an incorrect hardware teardown order and duplicate the TILER
power-off?

The NEURAL power-off block is placed above the existing TILER and SHADER blocks,
while also duplicating the TILER block. This causes
panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER) to execute twice.

The execution sequence becomes NEURAL -> TILER -> TILER -> SHADER. This violates
the strict teardown order required by the hardware (delegation is NEURAL ->
SHADER -> TILER, so teardown must be TILER -> SHADER -> NEURAL).

Could this lead to invalid hardware states or timeouts?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261015131301.711153-1-daniels@collabora.com?part=2

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 2/2] drm/panthor: Delegate neural power domain to CSF when present
  2026-10-15 13:18   ` sashiko-bot
@ 2026-10-15 13:45     ` Daniel Stone
  0 siblings, 0 replies; 5+ messages in thread
From: Daniel Stone @ 2026-10-15 13:45 UTC (permalink / raw)
  To: sashiko-reviews; +Cc: Daniel Stone, dri-devel

On Thu, 15 Oct 2026 at 14:18, <sashiko-bot@kernel.org> wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [Medium] panthor: resource leak due to incorrect LIFO label ordering in error path
> - [Medium] panthor: incorrect hardware teardown order and duplicate TILER power-off
> - [Low] panthor: build failure due to returning a label identifier

Well, that's tremendously embarrassing. Will follow up with v2 sent
from the branch that both builds and works, not the one full of rebase
detritus.

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2026-10-15 13:45 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-15 13:10 [PATCH 0/2] drm/panthor: Consistently delegate shader power Daniel Stone
2026-10-15 13:10 ` [PATCH 1/2] drm/panthor: Add neural-engine presence and power bits for v14+ Daniel Stone
2026-10-15 13:10 ` [PATCH 2/2] drm/panthor: Delegate neural power domain to CSF when present Daniel Stone
2026-10-15 13:18   ` sashiko-bot
2026-10-15 13:45     ` Daniel Stone

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