[PATCH 0/6] Tegra264 GB10B boards the bus

[PATCH 0/6] Tegra264 GB10B boards the bus

[Mikko Perttunen]

The integrated GB10B GPU on the Tegra264 SoC is connected to an internal
PCIe bus. However, it won't enumerate on the bus unless its BPMP-managed
power domain is enabled.

This series uses the PCI pwrctrl framework to allow enabling the power
domain before enumerating the bus, and adds the device tree changes
necessary to make the GPU appear.

Patch 1 adds the ats-supported property to the Tegra264 PCI controller's
device tree bindings.

Patches 2 and 3 enable the pwrctrl framework to detect device tree nodes
with a power-domains property as needing a pwrctrl device, and add the
GB10B's PCI IDs to the match table.

Patch 4 updates the Tegra264 PCI controller driver to call into
pwrctrl to power up the endpoint devices.

Patches 5 and 6 describe the GB10B in the Tegra264 device tree and
enable the PCI controller (and ATS support) in the SoC device tree since
it is chip-internal.

All patches are independent of each other (apart from patch 6 causing
device tree warnings unless the binding patch is applied).

Thank you,
Mikko

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
Mikko Perttunen (6):
      dt-bindings: PCI: tegra264: Allow the ats-supported property
      PCI/pwrctrl: Enable pwrctrl for devices powered by a power domain
      PCI/pwrctrl: Add the Tegra264 iGPU to the generic match table
      PCI: tegra264: Power endpoint devices before enumeration
      arm64: tegra: Add node for the GB10B GPU on Tegra264
      arm64: tegra: Enable and mark the Tegra264 GPU PCIe controller as ATS supported

 .../bindings/pci/nvidia,tegra264-pcie.yaml         |  5 +++++
 arch/arm64/boot/dts/nvidia/tegra264.dtsi           |  8 +++++++-
 drivers/pci/controller/Kconfig                     |  1 +
 drivers/pci/controller/pcie-tegra264.c             | 22 ++++++++++++++++++++--
 drivers/pci/pwrctrl/core.c                         |  7 +++++--
 drivers/pci/pwrctrl/generic.c                      |  4 ++++
 6 files changed, 42 insertions(+), 5 deletions(-)
---
base-commit: 8f7df005a7564bd7ffa75da9c3085d5b996f1e16
change-id: 20261021-b4-t264-igpu-pci-8b94cf0b91ee

[PATCH 1/6] dt-bindings: PCI: tegra264: Allow the ats-supported property

[Mikko Perttunen]

The C0 controller on Tegra264 is connected to the integrated GPU, which
issues ATS requests. Add the ats-supported property to allow marking
ATS as supported on the controller.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
index f0114defc04e..3b4f31a4a4c2 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
@@ -34,6 +34,11 @@ properties:
 
   dma-coherent: true
 
+  ats-supported:
+    description:
+      Indicates that the controller supports ATS.
+    type: boolean
+
   nvidia,bpmp:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     description: |

-- 
2.55.0

Re: [PATCH 1/6] dt-bindings: PCI: tegra264: Allow the ats-supported property

[sashiko-bot]

> The C0 controller on Tegra264 is connected to the integrated GPU, which
> issues ATS requests. Add the ats-supported property to allow marking
> ATS as supported on the controller.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-b4-t264-igpu-pci-v1-0-4d843dda0b02@nvidia.com?part=1

[PATCH 2/6] PCI/pwrctrl: Enable pwrctrl for devices powered by a power domain

[Mikko Perttunen]

Update pci_pwrctrl_is_required to return true for devices that require a
power domain specified by the power-domains property, such as the
integrated GPU on Tegra264.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/pci/pwrctrl/core.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c
index 0e2387cf4657..437507699beb 100644
--- a/drivers/pci/pwrctrl/core.c
+++ b/drivers/pci/pwrctrl/core.c
@@ -146,8 +146,8 @@ EXPORT_SYMBOL_GPL(devm_pci_pwrctrl_device_set_ready);
  * 1. Presence of compatible property with "pci" prefix to match against the
  *    pwrctrl driver (AND)
  * 2. At least one of the power supplies defined in the devicetree node of the
- *    device (OR) in the remote endpoint parent node to indicate pwrctrl
- *    requirement.
+ *    device (OR) in the remote endpoint parent node (OR) a power-domains
+ *    property in the device node to indicate pwrctrl requirement.
  */
 static bool pci_pwrctrl_is_required(struct device_node *np)
 {
@@ -165,6 +165,9 @@ static bool pci_pwrctrl_is_required(struct device_node *np)
 	if (of_pci_supply_present(np))
 		return true;
 
+	if (of_property_present(np, "power-domains"))
+		return true;
+
 	if (of_graph_is_present(np)) {
 		for_each_endpoint_of_node(np, endpoint) {
 			struct device_node *remote __free(device_node) =

-- 
2.55.0

Re: [PATCH 2/6] PCI/pwrctrl: Enable pwrctrl for devices powered by a power domain

[sashiko-bot]

> Update pci_pwrctrl_is_required to return true for devices that require a
> power domain specified by the power-domains property, such as the
> integrated GPU on Tegra264.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-b4-t264-igpu-pci-v1-0-4d843dda0b02@nvidia.com?part=2

[PATCH 3/6] PCI/pwrctrl: Add the Tegra264 iGPU to the generic match table

[Mikko Perttunen]

Tegra264 exposes its integrated GB10B GPU as PCI device 10de:2b00.
Its power domain must be enabled before enumeration.

Match pci10de,2b00 to let the generic power-control driver bind to the
GPU's platform device and enable its power domain before enumeration.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/pci/pwrctrl/generic.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/pwrctrl/generic.c b/drivers/pci/pwrctrl/generic.c
index 4b6cbbb52248..393ef7dd96af 100644
--- a/drivers/pci/pwrctrl/generic.c
+++ b/drivers/pci/pwrctrl/generic.c
@@ -118,6 +118,10 @@ static const struct of_device_id slot_pwrctrl_of_match[] = {
 	{
 		.compatible = "pciclass,0604",
 	},
+	/* NVIDIA Tegra264 GB10B GPU */
+	{
+		.compatible = "pci10de,2b00",
+	},
 	/* Renesas UPD720201/UPD720202 USB 3.0 xHCI Host Controller */
 	{
 		.compatible = "pci1912,0014",

-- 
2.55.0

Re: [PATCH 3/6] PCI/pwrctrl: Add the Tegra264 iGPU to the generic match table

[sashiko-bot]

> Tegra264 exposes its integrated GB10B GPU as PCI device 10de:2b00.
> Its power domain must be enabled before enumeration.
> 
> Match pci10de,2b00 to let the generic power-control driver bind to the
> GPU's platform device and enable its power domain before enumeration.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-b4-t264-igpu-pci-v1-0-4d843dda0b02@nvidia.com?part=3

[PATCH 4/6] PCI: tegra264: Power endpoint devices before enumeration

[Mikko Perttunen]

Add calls into the PCI pwrctrl framework to do required power sequencing
for endpoint devices before attempting to enumerate them, and select
PCI_PWRCTRL_GENERIC in Kconfig.

This is required for the integrated GB10B GPU on Tegra264 that requires
a power domain to be enabled before it appears on the PCI bus.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/pci/controller/Kconfig         |  1 +
 drivers/pci/controller/pcie-tegra264.c | 22 ++++++++++++++++++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index d246bbe37948..ab8cb1be28ba 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -261,6 +261,7 @@ config PCIE_TEGRA264
 	tristate "NVIDIA Tegra264 PCIe controller"
 	depends on ARCH_TEGRA || COMPILE_TEST
 	select PCI_ECAM
+	select PCI_PWRCTRL_GENERIC
 	help
 	  Say Y here if you want support for the PCIe Host Controller found
 	  on NVIDIA Tegra264 SoCs.
diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controller/pcie-tegra264.c
index c97576ab4a31..1d65ed5d0381 100644
--- a/drivers/pci/controller/pcie-tegra264.c
+++ b/drivers/pci/controller/pcie-tegra264.c
@@ -17,6 +17,7 @@
 #include <linux/of_pci.h>
 #include <linux/of_platform.h>
 #include <linux/pci-ecam.h>
+#include <linux/pci-pwrctrl.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
@@ -391,6 +392,14 @@ static int tegra264_pcie_probe(struct platform_device *pdev)
 	bridge->sysdata = pcie->cfg;
 	pcie->ecam = pcie->cfg->win;
 
+	err = pci_pwrctrl_create_devices(dev);
+	if (err)
+		goto err_free_ecam;
+
+	err = pci_pwrctrl_power_on_devices(dev);
+	if (err)
+		goto err_destroy_pwrctrl;
+
 	tegra264_pcie_init(pcie);
 
 	/*
@@ -402,17 +411,23 @@ static int tegra264_pcie_probe(struct platform_device *pdev)
 				    "PCIe #%u link is down and not hotplug-capable, turning off\n",
 				    pcie->ctl_id);
 		tegra264_pcie_power_off(pcie);
-		goto err_free_ecam;
+		goto err_power_off;
 	}
 
 	err = pci_host_probe(bridge);
 	if (err < 0) {
 		dev_err_probe(dev, err, "failed to register Host Bridge\n");
-		goto err_free_ecam;
+		goto err_power_off;
 	}
 
 	return 0;
 
+err_power_off:
+	pci_pwrctrl_power_off_devices(dev);
+err_destroy_pwrctrl:
+	/* Keep devices registered so their drivers can bind before we retry. */
+	if (err != -EPROBE_DEFER)
+		pci_pwrctrl_destroy_devices(dev);
 err_free_ecam:
 	pci_ecam_free(pcie->cfg);
 err_put_pm:
@@ -437,6 +452,9 @@ static void tegra264_pcie_remove(struct platform_device *pdev)
 	pci_remove_root_bus(pcie->bridge->bus);
 	pci_unlock_rescan_remove();
 
+	pci_pwrctrl_power_off_devices(&pdev->dev);
+	pci_pwrctrl_destroy_devices(&pdev->dev);
+
 	pm_runtime_put_sync(&pdev->dev);
 	tegra_bpmp_put(pcie->bpmp);
 	pci_ecam_free(pcie->cfg);

-- 
2.55.0

Re: [PATCH 4/6] PCI: tegra264: Power endpoint devices before enumeration

[sashiko-bot]

> Add calls into the PCI pwrctrl framework to do required power sequencing
> for endpoint devices before attempting to enumerate them, and select
> PCI_PWRCTRL_GENERIC in Kconfig.
> 
> This is required for the integrated GB10B GPU on Tegra264 that requires
> a power domain to be enabled before it appears on the PCI bus.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-b4-t264-igpu-pci-v1-0-4d843dda0b02@nvidia.com?part=4

[PATCH 5/6] arm64: tegra: Add node for the GB10B GPU on Tegra264

[Mikko Perttunen]

While the integrated GB10B GPU on Tegra264 is on the PCI bus, it
requires a BPMP power domain to be enabled or it won't enumerate on the
bus. Therefore, describe it and the power domain in the device tree to
allow the power domain to be enabled prior to enumeration.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 5ab34cd09a3d..4c8b320ecc40 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3597,6 +3597,12 @@ pcie@0 {
 				#address-cells = <3>;
 				#size-cells = <2>;
 				ranges;
+
+				gpu@0 {
+					compatible = "pci10de,2b00";
+					reg = <0x00010000 0x0 0x0 0x0 0x0>;
+					power-domains = <&bpmp TEGRA264_POWER_DOMAIN_GPU>;
+				};
 			};
 		};
 

-- 
2.55.0

Re: [PATCH 5/6] arm64: tegra: Add node for the GB10B GPU on Tegra264

[sashiko-bot]

> While the integrated GB10B GPU on Tegra264 is on the PCI bus, it
> requires a BPMP power domain to be enabled or it won't enumerate on the
> bus. Therefore, describe it and the power domain in the device tree to
> allow the power domain to be enabled prior to enumeration.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-b4-t264-igpu-pci-v1-0-4d843dda0b02@nvidia.com?part=5

[PATCH 6/6] arm64: tegra: Enable and mark the Tegra264 GPU PCIe controller as ATS supported

[Mikko Perttunen]

PCIe C0 connects to the integrated GPU and is internal to the SoC.
Therefore enable it directly in the SoC device tree file.

At the same time, mark it as ats-supported -- the GPU issues ATS
requests and this is required to enable their handling.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 4c8b320ecc40..9f39b5c52a01 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3580,6 +3580,7 @@ pci@c000000 {
 			iommu-map = <0x0 &smmu2 0x10000 0x10000>;
 			msi-map = <0x0 &its 0x210000 0x10000>;
 			dma-coherent;
+			ats-supported;
 
 			ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */
 				 <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */
@@ -3587,7 +3588,6 @@ pci@c000000 {
 			bus-range = <0x0 0xff>;
 
 			nvidia,bpmp = <&bpmp 0>;
-			status = "disabled";
 
 			pcie@0 {
 				device_type = "pci";

-- 
2.55.0

Re: [PATCH 6/6] arm64: tegra: Enable and mark the Tegra264 GPU PCIe controller as ATS supported

[sashiko-bot]

> PCIe C0 connects to the integrated GPU and is internal to the SoC.
> Therefore enable it directly in the SoC device tree file.
> 
> At the same time, mark it as ats-supported -- the GPU issues ATS
> requests and this is required to enable their handling.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-b4-t264-igpu-pci-v1-0-4d843dda0b02@nvidia.com?part=6