* [PATCH v5 0/2] Add ITE IT6162 MIPI DSI to HDMI bridge driver
@ 2026-10-29 10:12 ` Hermes Wu
0 siblings, 0 replies; 7+ messages in thread
From: Hermes Wu via B4 Relay @ 2026-10-29 10:12 UTC (permalink / raw)
To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Luca Ceresoli
Cc: Pet.Weng, Kenneth.Hung, Hermes Wu, dri-devel, devicetree,
linux-kernel, Dmitry Baryshkov, Hermes Wu
This patch series adds support for the ITE IT6162 MIPI DSI to HDMI
bridge chip. The IT6162 is an I2C-controlled bridge that receives MIPI
DSI input and outputs HDMI signals.
The device supports the following configurations:
- Single MIPI DSI input: up to 4K @ 30Hz
- Dual MIPI DSI input (combined): up to 4K @ 60Hz
This series introduces:
- dt-bindings: Add YAML binding document for ITE IT6162
- drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver
Signed-off-by: Hermes Wu <Hermes.wu@ite.com.tw>
---
Changes in v5:
- Move per-patch changelogs into the cover letter
- Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml:
* Use 1-based data-lanes numbering as lane 0 is the D-PHY clock lane,
revert example to <1 2 3 4>
* Constrain data-lanes to in-order lanes or full reversal <4 3 2 1>
* Document port@1 as the preferred port for a single MIPI DSI input
* Keep port@0 and port@3 optional: a single MIPI DSI input uses port@1,
and the HDMI connector is created for the bridge without a port@3
link
* Keep a single endpoint node per MIPI DSI port, as other bridge
bindings based on port-base do
* Drop Reviewed-by tag due to above changes
- drivers/gpu/drm/bridge/ite-it6162.c:
* Detect lane reversal from 1-based data-lanes (data_lanes[0] == 4)
* Rebase on drm-misc-next: use struct drm_atomic_commit in
atomic_enable/atomic_disable, replace .atomic_reset with
.atomic_create_state, pass DRM_OUTPUT_COLOR_FORMAT_RGB444 to
drm_hdmi_compute_mode_clock()
* Take the colorspace sent to firmware from the AVI infoframe instead of
conn_state->hdmi.output_format, which is no longer enum hdmi_colorspace
* Enable the supplies once, while detecting the chip, and disable them
through devres on removal and on every probe failure; unwind a
partially failed enable in the power-down order; propagate
it6162_poweron() errors and drop the unused it6162_poweroff()
* Power up ivdd, wait at least 1 ms, then ovdd1833 and ovdd, and power
down in the reverse order with the same wait before ivdd
* Rename it6162_poweron() to it6162_hw_start() and the power_on flag to
hw_ready, as the function no longer enables the supplies: it resets
and configures the chip, then enables the interrupt and connector
status reporting
* Order teardown with devres: initialise the (devm managed) mutex, wait
queue and HDCP work first, and register the bridge before the HDCP
work cancel action and the IRQ, so the IRQ is freed and the work
cancelled before the bridge is removed; drop .remove()
* Hold it6162->lock while writing or clearing an infoframe through the
data buffer
* Update the HDCP content protection property from a dedicated work
holding connection_mutex, and drop updates for an HDCP session that
has already ended
* Zero-initialise the video settings and set the HSync/VSync polarity
and scan mode bits as the programming guide defines them, which also
fixes the inverted VSync polarity
* Check regmap read results before using the data read
* Name the chip ID and version register offsets as in the programming
guide (register 0x00 is the most significant ID byte); the ID check
is unchanged
* Document that the firmware is given the HDMI output timing from the
requested mode, not the MIPI input timing in adjusted_mode
* Drop the endpoint node reference on the data-lanes error path
* Get the chip info with i2c_get_match_data(), add it to the I2C ID
table and fail probe if it is missing
* Honour the requested length when reading an EDID block
* Leave the cached HPD state to the IRQ thread instead of updating it
from detect
* Drop Reviewed-by tag due to above changes
- Link to v4: https://lore.kernel.org/r/20260319-upstream-6162-v4-0-7268483ef03d@ite.com.tw
Changes in v4:
- Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml:
* Drop ite,support-hdcp
* Drop endpoint properties already in video-interfaces.yaml
* Fix data-lanes in example with <0 1 2 3>
* Add blanking line in example before endpoint subnode starts
* Add reset-gpio and power controls to required
- drivers/gpu/drm/bridge/ite-it6162.c:
* Drop struc it6162_audio
* Add HDCP_AUTO in enum hdcp_ver{}, FW enable HDCP by sink capability.
* Call drm_atomic_helper_connector_hdmi_clear_audio_infoframe()
in it6162_bridge_hdmi_audio_shutdown()
* Drop it6162_bridge_hdmi_audio_startup()
* Add hdmi_clear_hdmi_infoframe and hdmi_write_hdmi_infoframe
* Drop it6162_parse_dt() due to "ite,support-hdcp" is removed from DT.
* add DRM_BRIDGE_OP_HDMI to it6162->bridge.ops
- Link to v3: https://lore.kernel.org/r/20260313-upstream-6162-v3-0-8497fb7c4406@ite.com.tw
Changes in v3:
- Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml:
* Fix lane-polarities: remove $ref redefinition, allow via video-interfaces.yaml
* Improve ite,support-hdcp description to clarify FW-based HDCP behavior
* Remove descriptions repeating schema constraints
* Remove stray comment in ports required section
* Fix data-lanes spacing in example: <1 2 3 4>
* Add missing newline at end of file
* Add missing change log that Reviewed-by tag was removed when V1->V2
- drivers/gpu/drm/bridge/ite-it6162.c:
* Fix OFFSET_VERSION_H register offset from 0x03 to 0x05
* Add MIPI_PORT_EN_MASK macro combining MIPI_PORT1_EN_MASK and MIPI_PORT0_EN_MASK
* Rename HDCP enums: NO_HDCP -> HDCP_DISABLE, NO_HDCP_STATE -> HDCP_STATE_IDLE,
AUTH_DONE -> HDCP_STATE_AUTH_DONE, AUTH_FAIL -> HDCP_STATE_AUTH_FAIL
* Rename it6162_infoblock_complete() to it6162_wait_command_complete()
* Rename it6162_infoblock_host_set() to it6162_infoblock_trigger()
* Remove it6162_infoblock_mipi_config() and it6162_infoblock_write_msg()
wrappers, inline into it6162_reset_init() and
it6162_mipi_set_video_timing() respectively
* Remove it6162_set_default_config() wrapper, inline into
it6162_reset_init()
* Fix typo: hdcp_encyption -> hdcp_encryption
* Fix typo: it6162_hdcp_read_infomation -> it6162_hdcp_read_information
* Remove dev_err_probe() usage outside of probe path
* Remove verbose success-path dev_info/dev_dbg logging throughout
* Replace __func__ usage in error messages with descriptive strings
* Fix double error printing in probe for it6162_init_pdata failure path
* Fix uninitialized variable warning: initialize cp_status to
DRM_MODE_CONTENT_PROTECTION_DESIRED at declaration; move
drm_hdcp_update_content_protection() inside the state-change block
* Fix audio sample width mapping: case 20 now maps to WORD_LENGTH_20BIT,
case 24 to WORD_LENGTH_24BIT
* Remove stray drm_dbg("it6162_bridge_atomic_disable") call
* Remove drm_dbg() calls from it6162_display_mode_to_settings()
* Drop unused struct it6162 * parameter from it6162_avi_to_video_setting()
and it6162_display_mode_to_settings()
* Fold it6162_set_default_config() body directly into it6162_reset_init(),
removing the wrapper
* it6162_infoblock_request_data(): split command complete polling and
buffer status check into two steps; use wait_event_timeout() for
data_buf_sts since it is updated asynchronously by the interrupt
handler; add wait_queue_head_t data_buf_wait to struct it6162 and
wake_up() in interrupt handler
- Link to v2: https://lore.kernel.org/r/20260309-upstream-6162-v2-0-debdb6c88030@ite.com.tw
Changes in v2:
- dt-bindings:
* Drop Reviewed-by tag due to below changes
* Add property "ite,spport-hdcp" to enable HDCP
* Add property "lane-polarities" and "clock-noncontinuous" for DSI
setting
- drm/bridge:
* Drop unused element in struct it6162
* Remove regmap wrappers
* Use FIELD_PREP for bitfield operations
* Update HDCP status with drm_hdcp_update_content_protection()
* Add AVI, AUDIO, and SPD infoframe control
* Remove conversion from drm_display_mode to videomode
* Fix regulator/gpio error handling in it6162_init_pdata() to return proper error codes
- MAINTAINERS
* squash to driver patch
- Link to v1: https://lore.kernel.org/r/20260223-upstream-6162-v1-0-ebcc66ccb1fe@ite.com.tw
---
Hermes Wu (2):
dt-bindings: display: bridge: Add ITE IT6162 MIPI DSI to HDMI bridge
drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver
.../bindings/display/bridge/ite,it6162.yaml | 205 +++
MAINTAINERS | 7 +
drivers/gpu/drm/bridge/Kconfig | 17 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/ite-it6162.c | 1764 ++++++++++++++++++++
5 files changed, 1994 insertions(+)
---
base-commit: 33ed26235db93162935d1719bc6f538c384a2fd8
change-id: 20260223-upstream-6162-3751e78dfcad
Best regards,
--
Hermes Wu <Hermes.wu@ite.com.tw>
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v5 0/2] Add ITE IT6162 MIPI DSI to HDMI bridge driver @ 2026-10-29 10:12 ` Hermes Wu 0 siblings, 0 replies; 7+ messages in thread From: Hermes Wu @ 2026-10-29 10:12 UTC (permalink / raw) To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Luca Ceresoli Cc: Pet.Weng, Kenneth.Hung, Hermes Wu, dri-devel, devicetree, linux-kernel, Dmitry Baryshkov, Hermes Wu This patch series adds support for the ITE IT6162 MIPI DSI to HDMI bridge chip. The IT6162 is an I2C-controlled bridge that receives MIPI DSI input and outputs HDMI signals. The device supports the following configurations: - Single MIPI DSI input: up to 4K @ 30Hz - Dual MIPI DSI input (combined): up to 4K @ 60Hz This series introduces: - dt-bindings: Add YAML binding document for ITE IT6162 - drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver Signed-off-by: Hermes Wu <Hermes.wu@ite.com.tw> --- Changes in v5: - Move per-patch changelogs into the cover letter - Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml: * Use 1-based data-lanes numbering as lane 0 is the D-PHY clock lane, revert example to <1 2 3 4> * Constrain data-lanes to in-order lanes or full reversal <4 3 2 1> * Document port@1 as the preferred port for a single MIPI DSI input * Keep port@0 and port@3 optional: a single MIPI DSI input uses port@1, and the HDMI connector is created for the bridge without a port@3 link * Keep a single endpoint node per MIPI DSI port, as other bridge bindings based on port-base do * Drop Reviewed-by tag due to above changes - drivers/gpu/drm/bridge/ite-it6162.c: * Detect lane reversal from 1-based data-lanes (data_lanes[0] == 4) * Rebase on drm-misc-next: use struct drm_atomic_commit in atomic_enable/atomic_disable, replace .atomic_reset with .atomic_create_state, pass DRM_OUTPUT_COLOR_FORMAT_RGB444 to drm_hdmi_compute_mode_clock() * Take the colorspace sent to firmware from the AVI infoframe instead of conn_state->hdmi.output_format, which is no longer enum hdmi_colorspace * Enable the supplies once, while detecting the chip, and disable them through devres on removal and on every probe failure; unwind a partially failed enable in the power-down order; propagate it6162_poweron() errors and drop the unused it6162_poweroff() * Power up ivdd, wait at least 1 ms, then ovdd1833 and ovdd, and power down in the reverse order with the same wait before ivdd * Rename it6162_poweron() to it6162_hw_start() and the power_on flag to hw_ready, as the function no longer enables the supplies: it resets and configures the chip, then enables the interrupt and connector status reporting * Order teardown with devres: initialise the (devm managed) mutex, wait queue and HDCP work first, and register the bridge before the HDCP work cancel action and the IRQ, so the IRQ is freed and the work cancelled before the bridge is removed; drop .remove() * Hold it6162->lock while writing or clearing an infoframe through the data buffer * Update the HDCP content protection property from a dedicated work holding connection_mutex, and drop updates for an HDCP session that has already ended * Zero-initialise the video settings and set the HSync/VSync polarity and scan mode bits as the programming guide defines them, which also fixes the inverted VSync polarity * Check regmap read results before using the data read * Name the chip ID and version register offsets as in the programming guide (register 0x00 is the most significant ID byte); the ID check is unchanged * Document that the firmware is given the HDMI output timing from the requested mode, not the MIPI input timing in adjusted_mode * Drop the endpoint node reference on the data-lanes error path * Get the chip info with i2c_get_match_data(), add it to the I2C ID table and fail probe if it is missing * Honour the requested length when reading an EDID block * Leave the cached HPD state to the IRQ thread instead of updating it from detect * Drop Reviewed-by tag due to above changes - Link to v4: https://lore.kernel.org/r/20260319-upstream-6162-v4-0-7268483ef03d@ite.com.tw Changes in v4: - Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml: * Drop ite,support-hdcp * Drop endpoint properties already in video-interfaces.yaml * Fix data-lanes in example with <0 1 2 3> * Add blanking line in example before endpoint subnode starts * Add reset-gpio and power controls to required - drivers/gpu/drm/bridge/ite-it6162.c: * Drop struc it6162_audio * Add HDCP_AUTO in enum hdcp_ver{}, FW enable HDCP by sink capability. * Call drm_atomic_helper_connector_hdmi_clear_audio_infoframe() in it6162_bridge_hdmi_audio_shutdown() * Drop it6162_bridge_hdmi_audio_startup() * Add hdmi_clear_hdmi_infoframe and hdmi_write_hdmi_infoframe * Drop it6162_parse_dt() due to "ite,support-hdcp" is removed from DT. * add DRM_BRIDGE_OP_HDMI to it6162->bridge.ops - Link to v3: https://lore.kernel.org/r/20260313-upstream-6162-v3-0-8497fb7c4406@ite.com.tw Changes in v3: - Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml: * Fix lane-polarities: remove $ref redefinition, allow via video-interfaces.yaml * Improve ite,support-hdcp description to clarify FW-based HDCP behavior * Remove descriptions repeating schema constraints * Remove stray comment in ports required section * Fix data-lanes spacing in example: <1 2 3 4> * Add missing newline at end of file * Add missing change log that Reviewed-by tag was removed when V1->V2 - drivers/gpu/drm/bridge/ite-it6162.c: * Fix OFFSET_VERSION_H register offset from 0x03 to 0x05 * Add MIPI_PORT_EN_MASK macro combining MIPI_PORT1_EN_MASK and MIPI_PORT0_EN_MASK * Rename HDCP enums: NO_HDCP -> HDCP_DISABLE, NO_HDCP_STATE -> HDCP_STATE_IDLE, AUTH_DONE -> HDCP_STATE_AUTH_DONE, AUTH_FAIL -> HDCP_STATE_AUTH_FAIL * Rename it6162_infoblock_complete() to it6162_wait_command_complete() * Rename it6162_infoblock_host_set() to it6162_infoblock_trigger() * Remove it6162_infoblock_mipi_config() and it6162_infoblock_write_msg() wrappers, inline into it6162_reset_init() and it6162_mipi_set_video_timing() respectively * Remove it6162_set_default_config() wrapper, inline into it6162_reset_init() * Fix typo: hdcp_encyption -> hdcp_encryption * Fix typo: it6162_hdcp_read_infomation -> it6162_hdcp_read_information * Remove dev_err_probe() usage outside of probe path * Remove verbose success-path dev_info/dev_dbg logging throughout * Replace __func__ usage in error messages with descriptive strings * Fix double error printing in probe for it6162_init_pdata failure path * Fix uninitialized variable warning: initialize cp_status to DRM_MODE_CONTENT_PROTECTION_DESIRED at declaration; move drm_hdcp_update_content_protection() inside the state-change block * Fix audio sample width mapping: case 20 now maps to WORD_LENGTH_20BIT, case 24 to WORD_LENGTH_24BIT * Remove stray drm_dbg("it6162_bridge_atomic_disable") call * Remove drm_dbg() calls from it6162_display_mode_to_settings() * Drop unused struct it6162 * parameter from it6162_avi_to_video_setting() and it6162_display_mode_to_settings() * Fold it6162_set_default_config() body directly into it6162_reset_init(), removing the wrapper * it6162_infoblock_request_data(): split command complete polling and buffer status check into two steps; use wait_event_timeout() for data_buf_sts since it is updated asynchronously by the interrupt handler; add wait_queue_head_t data_buf_wait to struct it6162 and wake_up() in interrupt handler - Link to v2: https://lore.kernel.org/r/20260309-upstream-6162-v2-0-debdb6c88030@ite.com.tw Changes in v2: - dt-bindings: * Drop Reviewed-by tag due to below changes * Add property "ite,spport-hdcp" to enable HDCP * Add property "lane-polarities" and "clock-noncontinuous" for DSI setting - drm/bridge: * Drop unused element in struct it6162 * Remove regmap wrappers * Use FIELD_PREP for bitfield operations * Update HDCP status with drm_hdcp_update_content_protection() * Add AVI, AUDIO, and SPD infoframe control * Remove conversion from drm_display_mode to videomode * Fix regulator/gpio error handling in it6162_init_pdata() to return proper error codes - MAINTAINERS * squash to driver patch - Link to v1: https://lore.kernel.org/r/20260223-upstream-6162-v1-0-ebcc66ccb1fe@ite.com.tw --- Hermes Wu (2): dt-bindings: display: bridge: Add ITE IT6162 MIPI DSI to HDMI bridge drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver .../bindings/display/bridge/ite,it6162.yaml | 205 +++ MAINTAINERS | 7 + drivers/gpu/drm/bridge/Kconfig | 17 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ite-it6162.c | 1764 ++++++++++++++++++++ 5 files changed, 1994 insertions(+) --- base-commit: 33ed26235db93162935d1719bc6f538c384a2fd8 change-id: 20260223-upstream-6162-3751e78dfcad Best regards, -- Hermes Wu <Hermes.wu@ite.com.tw> ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v5 1/2] dt-bindings: display: bridge: Add ITE IT6162 MIPI DSI to HDMI bridge 2026-10-29 10:12 ` Hermes Wu @ 2026-10-29 10:12 ` Hermes Wu -1 siblings, 0 replies; 7+ messages in thread From: Hermes Wu via B4 Relay @ 2026-10-29 10:12 UTC (permalink / raw) To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Luca Ceresoli Cc: Pet.Weng, Kenneth.Hung, Hermes Wu, dri-devel, devicetree, linux-kernel, Dmitry Baryshkov, Hermes Wu From: Hermes Wu <Hermes.wu@ite.com.tw> Add device tree binding documentation for the ITE IT6162 MIPI DSI to HDMI 2.0 bridge chip. The IT6162 is an I2C-controlled bridge that supports the following configurations: - Single MIPI DSI input: up to 4K @ 30Hz - Dual MIPI DSI input (combined): up to 4K @ 60Hz The chip also supports up to 8-channel audio output via 4 I2S data channels. Assisted-by: Claude Opus 5.5 Signed-off-by: Hermes Wu <Hermes.wu@ite.com.tw> --- .../bindings/display/bridge/ite,it6162.yaml | 205 +++++++++++++++++++++ 1 file changed, 205 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml new file mode 100644 index 0000000000000000000000000000000000000000..50a6e1e8a4c6a6b62f98b7755ca0c103df3a2960 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml @@ -0,0 +1,205 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ite,it6162.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ITE IT6162 MIPI DSI to HDMI 2.0 Bridge + +maintainers: + - Hermes Wu <Hermes.Wu@ite.com.tw> + +description: | + The ITE IT6162 is a high-performance, low-power HDMI bridge that converts + 2 MIPI DSI signals to 1 HDMI 2.0 output. It supports dual MIPI D-PHY 2.0 + links up to 10 Gbps each (20 Gbps total), compatible with DSI-2 v2.0. + + The HDMI transmitter supports resolutions up to 4Kx2K@60Hz and is compliant + with HDMI 2.0 specifications. + + For audio, it supports up to 8-channel LPCM via I2S (multi-line or TDM mode), + with optional S/PDIF or DSD (for SACD). Audio sampling rates up to 192 kHz + are supported. + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + const: ite,it6162 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + ivdd-supply: + description: Core voltage supply + + ovdd-supply: + description: I/O voltage supply + + ovdd1833-supply: + description: Flexible I/O voltage supply (1.8V domain) + + "#sound-dai-cells": + const: 0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input port for MIPI DSI-0 + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + oneOf: + - minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - items: + - const: 4 + - const: 3 + - const: 2 + - const: 1 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for MIPI DSI-1, the preferred port for a single MIPI DSI + input. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + oneOf: + - minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - items: + - const: 4 + - const: 3 + - const: 2 + - const: 1 + + required: + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Audio input port + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + required: + - port@1 + +required: + - compatible + - reg + - interrupts + - reset-gpios + - ivdd-supply + - ovdd-supply + - ovdd1833-supply + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@58 { + compatible = "ite,it6162"; + reg = <0x58>; + + #sound-dai-cells = <0>; + + interrupt-parent = <&pio>; + interrupts = <128 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&it6162_pins>; + + reset-gpios = <&pio 127 GPIO_ACTIVE_LOW>; + + ivdd-supply = <&pp1000_hdmi_x>; + ovdd-supply = <&pp3300_vio28_x>; + ovdd1833-supply = <&pp1800_vcamio_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + it6162_dsi0: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_0_out>; + }; + }; + + port@1 { + reg = <1>; + + it6162_dsi1: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_1_out>; + }; + }; + + port@2 { + reg = <2>; + + it6162_audio_in: endpoint { + remote-endpoint = <&i2s0_out>; + }; + }; + + port@3 { + reg = <3>; + + it6162_hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 1/2] dt-bindings: display: bridge: Add ITE IT6162 MIPI DSI to HDMI bridge @ 2026-10-29 10:12 ` Hermes Wu 0 siblings, 0 replies; 7+ messages in thread From: Hermes Wu @ 2026-10-29 10:12 UTC (permalink / raw) To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Luca Ceresoli Cc: Pet.Weng, Kenneth.Hung, Hermes Wu, dri-devel, devicetree, linux-kernel, Dmitry Baryshkov, Hermes Wu Add device tree binding documentation for the ITE IT6162 MIPI DSI to HDMI 2.0 bridge chip. The IT6162 is an I2C-controlled bridge that supports the following configurations: - Single MIPI DSI input: up to 4K @ 30Hz - Dual MIPI DSI input (combined): up to 4K @ 60Hz The chip also supports up to 8-channel audio output via 4 I2S data channels. Assisted-by: Claude Opus 5.5 Signed-off-by: Hermes Wu <Hermes.wu@ite.com.tw> --- .../bindings/display/bridge/ite,it6162.yaml | 205 +++++++++++++++++++++ 1 file changed, 205 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml new file mode 100644 index 0000000000000000000000000000000000000000..50a6e1e8a4c6a6b62f98b7755ca0c103df3a2960 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml @@ -0,0 +1,205 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ite,it6162.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ITE IT6162 MIPI DSI to HDMI 2.0 Bridge + +maintainers: + - Hermes Wu <Hermes.Wu@ite.com.tw> + +description: | + The ITE IT6162 is a high-performance, low-power HDMI bridge that converts + 2 MIPI DSI signals to 1 HDMI 2.0 output. It supports dual MIPI D-PHY 2.0 + links up to 10 Gbps each (20 Gbps total), compatible with DSI-2 v2.0. + + The HDMI transmitter supports resolutions up to 4Kx2K@60Hz and is compliant + with HDMI 2.0 specifications. + + For audio, it supports up to 8-channel LPCM via I2S (multi-line or TDM mode), + with optional S/PDIF or DSD (for SACD). Audio sampling rates up to 192 kHz + are supported. + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + const: ite,it6162 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + ivdd-supply: + description: Core voltage supply + + ovdd-supply: + description: I/O voltage supply + + ovdd1833-supply: + description: Flexible I/O voltage supply (1.8V domain) + + "#sound-dai-cells": + const: 0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input port for MIPI DSI-0 + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + oneOf: + - minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - items: + - const: 4 + - const: 3 + - const: 2 + - const: 1 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for MIPI DSI-1, the preferred port for a single MIPI DSI + input. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + oneOf: + - minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - items: + - const: 4 + - const: 3 + - const: 2 + - const: 1 + + required: + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Audio input port + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + required: + - port@1 + +required: + - compatible + - reg + - interrupts + - reset-gpios + - ivdd-supply + - ovdd-supply + - ovdd1833-supply + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@58 { + compatible = "ite,it6162"; + reg = <0x58>; + + #sound-dai-cells = <0>; + + interrupt-parent = <&pio>; + interrupts = <128 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&it6162_pins>; + + reset-gpios = <&pio 127 GPIO_ACTIVE_LOW>; + + ivdd-supply = <&pp1000_hdmi_x>; + ovdd-supply = <&pp3300_vio28_x>; + ovdd1833-supply = <&pp1800_vcamio_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + it6162_dsi0: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_0_out>; + }; + }; + + port@1 { + reg = <1>; + + it6162_dsi1: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_1_out>; + }; + }; + + port@2 { + reg = <2>; + + it6162_audio_in: endpoint { + remote-endpoint = <&i2s0_out>; + }; + }; + + port@3 { + reg = <3>; + + it6162_hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 2/2] drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver 2026-10-29 10:12 ` Hermes Wu @ 2026-10-29 10:12 ` Hermes Wu -1 siblings, 0 replies; 7+ messages in thread From: Hermes Wu via B4 Relay @ 2026-10-29 10:12 UTC (permalink / raw) To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Luca Ceresoli Cc: Pet.Weng, Kenneth.Hung, Hermes Wu, dri-devel, devicetree, linux-kernel, Dmitry Baryshkov, Hermes Wu From: Hermes Wu <Hermes.wu@ite.com.tw> Add support for the ITE IT6162 MIPI DSI to HDMI 2.0 bridge chip. The IT6162 is an I2C-controlled bridge that supports the following configurations: - Single MIPI DSI input: up to 4K @ 30Hz - Dual MIPI DSI input (combined): up to 4K @ 60Hz The driver implements the DRM bridge and connector frameworks, including mode setting, EDID retrieval, and HPD support. Also add a MAINTAINERS entry for the newly introduced ITE IT6162 MIPI DSI to HDMI bridge driver, covering the driver source file and the device tree binding document. Assisted-by: Claude Opus 5.5 Signed-off-by: Hermes Wu <Hermes.wu@ite.com.tw> --- MAINTAINERS | 7 + drivers/gpu/drm/bridge/Kconfig | 17 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ite-it6162.c | 1764 +++++++++++++++++++++++++++++++++++ 4 files changed, 1789 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 89ea35a35c6809e5066674cff3d5b7b129db4c49..0ebf58c322e1e2e8916aeba38a3828873374c1d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13977,6 +13977,13 @@ W: https://linuxtv.org Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/tuners/it913x* +ITE IT6162 MIPI DSI TO HDMI BRIDGE DRIVER +M: Hermes Wu <Hermes.wu@ite.com.tw> +L: dri-devel@lists.freedesktop.org +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml +F: drivers/gpu/drm/bridge/ite-it6162.c + ITE IT6263 LVDS TO HDMI BRIDGE DRIVER M: Liu Ying <victor.liu@nxp.com> L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index c7da6b02d7b6b281f328fb3016ea2f167f8da093..59d4911222747a233cfd3fbe8394f0d1652e5c9d 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -106,6 +106,23 @@ config DRM_INNO_HDMI select DRM_DISPLAY_HELPER select DRM_KMS_HELPER +config DRM_ITE_IT6162 + tristate "iTE IT6162 DSI to HDMI bridge" + depends on OF + select REGMAP_I2C + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + select DRM_KMS_HELPER + select DRM_HDMI_HELPER + select DRM_DISPLAY_HDMI_HELPER + select DRM_DISPLAY_HDCP_HELPER + select DRM_DISPLAY_HELPER + help + Driver for iTE IT6162 DSI to HDMI bridge + chip driver that converts DSI to HDMI signals + support up to 4k60 with 2 MIPI DSI + Please say Y if you have such hardware. + config DRM_ITE_IT6263 tristate "ITE IT6263 LVDS/HDMI bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 15cc821d85b7ea6f3cdc313f3e521b028de567d7..2e082ec616d1119788be4deaf7e3436d52404237 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -11,6 +11,7 @@ tda998x-y := tda998x_drv.o obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o obj-$(CONFIG_DRM_INNO_HDMI) += inno-hdmi.o +obj-$(CONFIG_DRM_ITE_IT6162) += ite-it6162.o obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o diff --git a/drivers/gpu/drm/bridge/ite-it6162.c b/drivers/gpu/drm/bridge/ite-it6162.c new file mode 100644 index 0000000000000000000000000000000000000000..5f83722ff4e61e4b6ccb27f53c30ff19328804f3 --- /dev/null +++ b/drivers/gpu/drm/bridge/ite-it6162.c @@ -0,0 +1,1764 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2024 ITE Tech. Inc. + */ +#include <linux/bitfield.h> +#include <linux/gpio/consumer.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/of_irq.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <drm/display/drm_hdcp_helper.h> +#include <drm/display/drm_hdmi_helper.h> +#include <drm/display/drm_hdmi_state_helper.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_bridge_connector.h> +#include <drm/drm_drv.h> +#include <drm/drm_edid.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_of.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_print.h> +#include <video/videomode.h> +#include <sound/hdmi-codec.h> + +#define DATA_BUFFER_DEPTH 32 + +#define OFFSET_CHIP_ID_H 0x00 +#define OFFSET_CHIP_ID_M 0x01 +#define OFFSET_CHIP_ID_L 0x02 +#define OFFSET_VERSION_H 0x03 +#define OFFSET_VERSION_M 0x04 +#define OFFSET_VERSION_L 0x05 + +#define OFFSET_MIPI_CONFIG_L 0x06 +#define MIPI_CLOCK_MODE_MASK BIT(6) +#define MIPI_PORT1_EN_MASK BIT(5) +#define MIPI_PORT0_EN_MASK BIT(4) +#define MIPI_LANE_SWAP_MASK BIT(3) +#define MIPI_PN_SWAP_MASK BIT(2) +#define MIPI_LANE_NUM_MASK 0x3 +#define MIPI_PORT_EN_MASK (MIPI_PORT1_EN_MASK | MIPI_PORT0_EN_MASK) + +#define OFFSET_MIPI_CONFIG_H 0x07 +#define OFFSET_TX_CONFIG 0x08 + +#define OFFSET_TX_SETTING 0x09 +#define TX_HDCP_VER_MASK 0xC0 +#define TX_HDCP_ENCRYP_MASK BIT(5) +#define TX_STREAM_TYPE_MASK BIT(4) + +#define OFFSET_MIPI_STATUS 0x0A +#define OFFSET_TX_STATUS 0x0C +#define B_TX_STATUS_HPD 7 +#define B_TX_STATUS_VIDEO_STB 6 +#define B_TX_STATUS_HDCP 4 +#define M_TX_STATUS_HDCP 0x30 + +#define TX_VIDEO_STB BIT(B_TX_STATUS_VIDEO_STB) +#define TX_STATUS_HPD BIT(B_TX_STATUS_HPD) + +#define GET_TX_HPD_STATUS(x) (((x) & TX_STATUS_HPD) >> B_TX_STATUS_HPD) +#define GET_TX_VIDEO_STATUS(x) (((x) & TX_VIDEO_STB) >> B_TX_STATUS_VIDEO_STB) +#define GET_TX_HDCP_STATUS(x) (((x) & M_TX_STATUS_HDCP) >> B_TX_STATUS_HDCP) + +#define OFFSET_SINK_CAP 0x0D +#define B_SINK_CAP_HDCP_VER 4 +#define M_SINK_CAP_HDCP_VER 0x30 + +#define GET_SINK_CAP_HDCP_VER(x) (((x) & M_SINK_CAP_HDCP_VER) >> B_SINK_CAP_HDCP_VER) + +#define OFFSET_DRIVER_DATA 0x0E + +#define OFFSET_DATA_TYPE_IDX 0x0F +#define OFFSET_DATA_BUFFER 0x20 + +#define OFFSET_AUDIO_CTRL0 0x3C +#define MASK_AUDIO_CHANNEL_NUM 0x0F +#define MASK_AUDIO_SELECT 0x30 +#define MASK_AUDIO_TYPE 0xC0 + +#define OFFSET_AUDIO_CTRL1 0x3D +#define OFFSET_AUDIO_CTRL2 0x3E +#define MASK_I2S_BUS_MODE 0x1F +#define MASK_I2S_WORD_LEN 0x60 +#define MASK_I2S_VALID 0x80 + +#define OFFSET_HOST_SET 0xFE +#define B_CONFIG_CHG BIT(7) +#define B_SET_CHG BIT(6) +#define HOST_SET_VIDEO_INFO (1) +#define HOST_SET_AUDIO_INFO (2) +#define HOST_SET_VIDEO_AUDIO_INFO (3) +#define HOST_SET_EDID_R (0x04) +#define HOST_SET_HDCP_R (0x05) +#define HOST_SET_CEA_INFOFRAME (0x0E) + +#define OFFSET_EVENT_CHG 0xFF +#define B_EVENT_CHG_BUFFER 4 +#define M_EVENT_CHG_BUFFER_STS (0x30) + +#define B_EVENT_CHG 1 +#define B_EVENT_IC_READY 0 + +#define EVENT_CHG BIT(B_EVENT_CHG) +#define EVENT_READY BIT(B_EVENT_IC_READY) + +#define GET_BUFFER_STATUS(x) (((x) & M_EVENT_CHG_BUFFER_STS) >> B_EVENT_CHG_BUFFER) + +#define TIMEOUT_INFOBLOCK_MS 1800 + +enum it6162_audio_select { + I2S = 0, + SPDIF, +}; + +enum it6162_audio_word_length { + WORD_LENGTH_16BIT = 0x0, + WORD_LENGTH_18BIT = 0x1, + WORD_LENGTH_20BIT = 0x2, + WORD_LENGTH_24BIT = 0x3, +}; + +enum it6162_audio_sample_rate { + SAMPLE_RATE_32K = 0x3, + SAMPLE_RATE_48K = 0x2, + SAMPLE_RATE_64K = 0xB, + SAMPLE_RATE_96K = 0xA, + SAMPLE_RATE_192K = 0xE, + SAMPLE_RATE_44_1K = 0x0, + SAMPLE_RATE_88_2K = 0x8, + SAMPLE_RATE_176_4K = 0xC, +}; + +enum it6162_audio_type { + LPCM = 0, + NLPCM, +}; + +enum data_buf_sts { + NO_STS = 0x00, + BUF_READY = 0x01, + BUF_FAIL = 0x02, +}; + +enum hdcp_state { + HDCP_STATE_IDLE = 0x00, + HDCP_STATE_AUTH_DONE = 0x01, + HDCP_STATE_AUTH_FAIL = 0x02, +}; + +enum hdcp_ver { + HDCP_DISABLE = 0x0, + HDCP_14 = 0x1, + HDCP_23 = 0x2, + HDCP_AUTO = 0x3, +}; + +struct it6162_chip_info { + u32 chip_id; + u32 version; +}; + +struct it6162_video_settings { + u8 vic; + u32 clock; + u16 htotal; + u16 hfp; + u16 hsw; + u16 hbp; + u16 hdew; + u16 vtotal; + u16 vfp; + u16 vsw; + u16 vbp; + u16 vdew; + u8 hpol; + u8 vpol; + u8 prog; + u16 v_aspect; + u16 h_aspect; + u8 pix_rep; + u8 colorspace; +}; + +enum sync_mode { + SYNC_EVENT = 0x0, + SYNC_PULSE = 0x1, + SYNC_AUTO = 0x2, +}; + +struct it6162_mipi_cfg { + bool en_port[2]; + u8 lane_num; + bool pn_swap; + bool lane_swap; + bool continuous_clk; + enum sync_mode mode; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; +}; + +struct it6162_hdcp_cfg { + enum hdcp_ver hdcp_version; + bool hdcp_encryption; + u8 stream_ID; +}; + +struct it6162_infoblock_msg { + u8 action; + int len; + u8 msg[32]; +}; + +struct it6162 { + struct drm_bridge bridge; + struct device *dev; + struct drm_connector *connector; + enum drm_connector_status connector_status; + struct drm_device *drm; + + struct i2c_client *it6162_i2c; + struct regmap *regmap; + + struct regulator *pwr1833; + struct regulator *ovdd; + struct regulator *ivdd; + struct gpio_desc *gpiod_reset; + + bool hw_ready; + bool en_hdcp; + + /*lock the infoblock write setting and buffer access*/ + struct mutex lock; + + enum data_buf_sts data_buf_sts; + wait_queue_head_t data_buf_wait; + + /* it6162 DSI RX related params */ + struct mipi_dsi_device *dsi; + struct it6162_mipi_cfg mipi_cfg; + + struct delayed_work hdcp_work; + + /* + * HDCP content protection property update, protected by lock. + * hdcp_gen changes whenever the connector is set or cleared, so that + * updates from an ended session are not published. + * hdcp_prop_connector is non-NULL only while a queued, not yet + * started hdcp_prop_work owns a reference to it. + */ + u32 hdcp_gen; + struct work_struct hdcp_prop_work; + struct drm_connector *hdcp_prop_connector; + u64 hdcp_prop_value; + u32 hdcp_prop_gen; + + enum hdcp_state hdcp_sts; + enum hdcp_ver hdcp_version; + struct it6162_hdcp_cfg hdcp_cfg; + + unsigned int content_protection; +}; + +static struct it6162 *bridge_to_it6162(struct drm_bridge *bridge) +{ + return container_of(bridge, struct it6162, bridge); +} + +static const struct regmap_config it6162_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, + .cache_type = REGCACHE_NONE, +}; + +static inline int it6162_i2c_regmap_init(struct i2c_client *client, + struct it6162 *it6162) +{ + it6162->it6162_i2c = client; + i2c_set_clientdata(client, it6162); + it6162->regmap = devm_regmap_init_i2c(it6162->it6162_i2c, + &it6162_regmap_config); + if (IS_ERR(it6162->regmap)) + return PTR_ERR(it6162->regmap); + + return 0; +} + +static int it6162_wait_command_complete(struct it6162 *it6162) +{ + struct device *dev = it6162->dev; + struct regmap *regmap = it6162->regmap; + unsigned int val; + int ret; + + ret = regmap_read(regmap, OFFSET_HOST_SET, &val); + if (ret < 0) { + dev_err(dev, "read failed rx reg[0x%x]", OFFSET_HOST_SET); + return ret; + } + return val; +} + +static int it6162_infoblock_trigger(struct it6162 *it6162, u8 setting) +{ + struct device *dev = it6162->dev; + int status; + int val; + + regmap_write(it6162->regmap, OFFSET_HOST_SET, setting); + /* OFFSET_HOST_SET is cleared by firmware when the command is processed */ + status = readx_poll_timeout(it6162_wait_command_complete, it6162, val, + val <= 0, 50 * 1000, + TIMEOUT_INFOBLOCK_MS * 1000); + if (status < 0 || val != 0) { + dev_err(dev, "infoblock command timeout: status=%d val=%d", + status, val); + return -ETIMEDOUT; + } + + return 0; +} + +static int it6162_infoblock_request_data(struct it6162 *it6162, + u8 request_type, u8 index, u8 *buf) +{ + struct device *dev = it6162->dev; + int status; + + it6162->data_buf_sts = NO_STS; + regmap_write(it6162->regmap, OFFSET_DATA_TYPE_IDX, index); + status = it6162_infoblock_trigger(it6162, request_type); + if (status < 0) + return status; + /* data_buf_sts is updated asynchronously by the interrupt handler */ + if (wait_event_timeout(it6162->data_buf_wait, + it6162->data_buf_sts != NO_STS, + msecs_to_jiffies(TIMEOUT_INFOBLOCK_MS)) == 0) { + dev_err(dev, "timeout waiting for data buffer"); + return -ETIMEDOUT; + } + + if (it6162->data_buf_sts != BUF_READY) { + dev_err(dev, "data buffer not ready: sts=%d", + it6162->data_buf_sts); + return -EIO; + } + + return regmap_bulk_read(it6162->regmap, OFFSET_DATA_BUFFER, buf, + DATA_BUFFER_DEPTH); +} + +static void it6162_mipi_disable(struct it6162 *it6162) +{ + guard(mutex)(&it6162->lock); + regmap_update_bits(it6162->regmap, OFFSET_MIPI_CONFIG_L, + MIPI_PORT_EN_MASK, 0x00); + it6162_infoblock_trigger(it6162, B_CONFIG_CHG); +} + +static void it6162_mipi_enable(struct it6162 *it6162) +{ + unsigned int cfg_val = 0; + + cfg_val = FIELD_PREP(MIPI_PORT1_EN_MASK, it6162->mipi_cfg.en_port[1]) | + FIELD_PREP(MIPI_PORT0_EN_MASK, it6162->mipi_cfg.en_port[0]); + + guard(mutex)(&it6162->lock); + regmap_update_bits(it6162->regmap, OFFSET_MIPI_CONFIG_L, + MIPI_PORT_EN_MASK, cfg_val); + it6162_infoblock_trigger(it6162, B_CONFIG_CHG); +} + +static void it6162_tx_hdcp_enable(struct it6162 *it6162, + struct it6162_hdcp_cfg *tx_out) +{ + int val; + struct regmap *regmap = it6162->regmap; + + guard(mutex)(&it6162->lock); + it6162->hdcp_sts = HDCP_STATE_IDLE; + + if (regmap_read(regmap, OFFSET_TX_SETTING, &val) < 0) { + dev_err(it6162->dev, "failed to read tx setting"); + return; + } + + val &= 0x0F; + val |= FIELD_PREP(TX_HDCP_VER_MASK, tx_out->hdcp_version) | + FIELD_PREP(TX_HDCP_ENCRYP_MASK, tx_out->hdcp_encryption) | + FIELD_PREP(TX_STREAM_TYPE_MASK, tx_out->stream_ID); + + regmap_write(regmap, OFFSET_TX_SETTING, val); + it6162_infoblock_trigger(it6162, B_SET_CHG); +} + +static void it6162_tx_hdcp_disable(struct it6162 *it6162) +{ + int val; + struct regmap *regmap = it6162->regmap; + + it6162->hdcp_sts = HDCP_STATE_IDLE; + it6162->hdcp_version = HDCP_DISABLE; + + guard(mutex)(&it6162->lock); + if (regmap_read(regmap, OFFSET_TX_SETTING, &val) < 0) { + dev_err(it6162->dev, "failed to read tx setting"); + return; + } + + regmap_write(it6162->regmap, OFFSET_TX_SETTING, val & 0x0F); + it6162_infoblock_trigger(it6162, B_SET_CHG); +} + +static void +it6162_tx_hdcp_setup(struct it6162 *it6162, u8 ver, bool encryption) +{ + struct it6162_hdcp_cfg tx_out; + + if (ver != HDCP_DISABLE) { + tx_out.hdcp_version = ver; + tx_out.hdcp_encryption = encryption; + tx_out.stream_ID = 0; + it6162_tx_hdcp_enable(it6162, &tx_out); + } else { + it6162_tx_hdcp_disable(it6162); + } +} + +static void it6162_tx_enable(struct it6162 *it6162) +{ + if (it6162->en_hdcp) + it6162->hdcp_version = it6162->hdcp_cfg.hdcp_version; + else + it6162->hdcp_version = HDCP_DISABLE; +} + +static void it6162_tx_disable(struct it6162 *it6162) +{ + cancel_delayed_work_sync(&it6162->hdcp_work); + it6162_tx_hdcp_setup(it6162, HDCP_DISABLE, false); +} + +static inline void +it6162_pack_video_setting(struct it6162 *it6162, + struct it6162_video_settings *settings, + struct it6162_infoblock_msg *msg) +{ + msg->msg[0x00] = settings->hdew & 0xFF; + msg->msg[0x01] = (settings->hdew >> 8) & 0x3F; + msg->msg[0x02] = settings->vdew & 0xFF; + msg->msg[0x03] = (settings->vdew >> 8) & 0x3F; + msg->msg[0x04] = settings->clock & 0xFF; + msg->msg[0x05] = (settings->clock >> 8) & 0xFF; + msg->msg[0x06] = (settings->clock >> 16) & 0xFF; + msg->msg[0x07] = (settings->clock >> 24) & 0xFF; + msg->msg[0x08] = settings->hfp & 0xFF; + msg->msg[0x09] = (settings->hfp >> 8) & 0x3F; + msg->msg[0x0A] = settings->hsw & 0xFF; + msg->msg[0x0B] = (settings->hsw >> 8) & 0x3F; + msg->msg[0x0C] = settings->hbp & 0xFF; + msg->msg[0x0D] = (settings->hbp >> 8) & 0x3F; + msg->msg[0x0E] = settings->vfp & 0xFF; + msg->msg[0x0F] = (settings->vfp >> 8) & 0x3F; + msg->msg[0x10] = settings->vsw & 0xFF; + msg->msg[0x11] = (settings->vsw >> 8) & 0x3F; + msg->msg[0x12] = settings->vbp & 0xFF; + msg->msg[0x13] = (settings->vbp >> 8) & 0x3F; + msg->msg[0x14] = (settings->prog << 2) | + (settings->vpol << 1) | + settings->hpol; + + msg->msg[0x15] = settings->v_aspect; + msg->msg[0x16] = settings->h_aspect & 0xFF; + msg->msg[0x17] = settings->h_aspect >> 8; + msg->msg[0x18] = settings->pix_rep; + msg->msg[0x19] = settings->vic; + msg->msg[0x1A] = settings->colorspace; + msg->msg[0x1B] = 1; + + msg->len = 0x1C; + msg->action = HOST_SET_VIDEO_INFO; +} + +static void it6162_mipi_set_video_timing(struct it6162 *it6162, + struct it6162_video_settings *mode) +{ + struct it6162_infoblock_msg msg; + + it6162_pack_video_setting(it6162, mode, &msg); + guard(mutex)(&it6162->lock); + regmap_bulk_write(it6162->regmap, OFFSET_DATA_BUFFER, &msg.msg, + msg.len); + it6162_infoblock_trigger(it6162, msg.action); +} + +static int +it6162_hdcp_read_information(struct it6162 *it6162, u8 *status, u8 *bksv) +{ + u8 buf[DATA_BUFFER_DEPTH]; + int ret; + + guard(mutex)(&it6162->lock); + ret = it6162_infoblock_request_data(it6162, HOST_SET_HDCP_R, 0x00, + buf); + if (ret < 0) + return ret; + + memcpy(status, buf, 2); + memcpy(bksv, buf + 2, 5); + return 0; +} + +static int it6162_hdcp_read_list(struct it6162 *it6162, + u8 *ksv_list, + int dev_count) +{ + u8 buf[DATA_BUFFER_DEPTH]; + int i, j, ret; + + if (!ksv_list || dev_count <= 0) + return -EINVAL; + + guard(mutex)(&it6162->lock); + for (i = 0; i < (dev_count / 6 + 1); i++) { + ret = it6162_infoblock_request_data(it6162, HOST_SET_HDCP_R, + i + 1, buf); + if (ret < 0) + return ret; + + for (j = 0; j < 30; j += 5) { + if ((i * 6 + j / 5) >= dev_count) + break; + + memcpy(&ksv_list[(i * 6 + j / 5) * 5], &buf[j], 5); + } + } + return dev_count; +} + +static void it6162_update_hdcp14(struct it6162 *it6162) +{ + struct drm_device *drm = it6162->drm; + int dev_count; + u8 bksv[5]; + u8 bstatus[2]; + u8 ksvlist[5 * 30]; + int ret; + + ret = it6162_hdcp_read_information(it6162, bstatus, bksv); + if (ret < 0) { + drm_err(drm, "fail to read Bstatus"); + return; + } + + dev_count = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); + if (dev_count == 0) + return; + + if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || + DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { + drm_err(drm, "HDCP1.4 Max Topology Limit Exceeded"); + return; + } + + dev_count = dev_count > 30 ? 30 : dev_count; + ret = it6162_hdcp_read_list(it6162, ksvlist, dev_count); + if (ret < 0) { + drm_err(drm, "fail to read KSV list"); + return; + } +} + +static void it6162_update_hdcp23(struct it6162 *it6162) +{ + struct drm_device *drm = it6162->drm; + int dev_count; + u8 rxid[5]; + u8 rxinfo[2]; + u8 rxid_list[5 * 30]; + int ret; + + ret = it6162_hdcp_read_information(it6162, rxinfo, rxid); + if (ret < 0) { + drm_err(drm, "fail to read Rxinfo"); + return; + } + + dev_count = (HDCP_2_2_DEV_COUNT_HI(rxinfo[0]) << 4 | + HDCP_2_2_DEV_COUNT_LO(rxinfo[1])); + if (dev_count == 0) + return; + + if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rxinfo[1]) || + HDCP_2_2_MAX_DEVS_EXCEEDED(rxinfo[1])) { + drm_err(drm, "HDCP2.3 Topology Max Size Exceeded"); + return; + } + + dev_count = dev_count > 30 ? 30 : dev_count; + ret = it6162_hdcp_read_list(it6162, rxid_list, dev_count); + if (ret < 0) { + drm_err(drm, "fail to read RxID list"); + return; + } +} + +static void it6162_update_hdcp(struct it6162 *it6162, u8 version) +{ + if (version == HDCP_23) + it6162_update_hdcp23(it6162); + else + it6162_update_hdcp14(it6162); +} + +static void it6162_hdcp_queue_prop_update(struct it6162 *it6162, u64 value) +{ + guard(mutex)(&it6162->lock); + + if (!it6162->connector) + return; + + it6162->hdcp_prop_value = value; + it6162->hdcp_prop_gen = it6162->hdcp_gen; + + if (it6162->hdcp_prop_connector) + return; + + it6162->hdcp_prop_connector = it6162->connector; + drm_connector_get(it6162->hdcp_prop_connector); + queue_work(system_wq, &it6162->hdcp_prop_work); +} + +static void it6162_hdcp_prop_work(struct work_struct *work) +{ + struct it6162 *it6162 = container_of(work, struct it6162, + hdcp_prop_work); + struct drm_connector *connector; + struct drm_modeset_lock *connection_mutex; + + scoped_guard(mutex, &it6162->lock) { + connector = it6162->hdcp_prop_connector; + it6162->hdcp_prop_connector = NULL; + } + + if (!connector) + return; + + connection_mutex = &connector->dev->mode_config.connection_mutex; + drm_modeset_lock(connection_mutex, NULL); + + scoped_guard(mutex, &it6162->lock) { + if (it6162->hdcp_prop_gen == it6162->hdcp_gen && + it6162->connector == connector && + connector->state->content_protection != + DRM_MODE_CONTENT_PROTECTION_UNDESIRED) + drm_hdcp_update_content_protection(connector, + it6162->hdcp_prop_value); + } + + drm_modeset_unlock(connection_mutex); + drm_connector_put(connector); +} + +static void it6162_hdcp_handler(struct it6162 *it6162) +{ + struct regmap *regmap = it6162->regmap; + unsigned int tx_status, sink_cap; + enum hdcp_state hdcp_sts; + struct it6162_hdcp_cfg *hdcp_cfg = &it6162->hdcp_cfg; + u8 hdcp_ver; + u64 cp_status = DRM_MODE_CONTENT_PROTECTION_DESIRED; + + if (hdcp_cfg->hdcp_version == HDCP_DISABLE || !it6162->en_hdcp) + return; + + if (it6162->hdcp_version != HDCP_DISABLE) { + if (regmap_read(regmap, OFFSET_TX_STATUS, &tx_status) < 0 || + regmap_read(regmap, OFFSET_SINK_CAP, &sink_cap) < 0) + return; + + if (!GET_TX_VIDEO_STATUS(tx_status)) { + drm_dbg(it6162->drm, "video not stable, skip hdcp check"); + return; + } + + hdcp_sts = GET_TX_HDCP_STATUS(tx_status); + hdcp_ver = GET_SINK_CAP_HDCP_VER(sink_cap); + if (it6162->hdcp_sts != hdcp_sts || + it6162->hdcp_sts == HDCP_STATE_IDLE) { + it6162->hdcp_sts = hdcp_sts; + switch (hdcp_sts) { + case HDCP_STATE_AUTH_DONE: + it6162_update_hdcp(it6162, hdcp_ver); + cp_status = DRM_MODE_CONTENT_PROTECTION_ENABLED; + break; + case HDCP_STATE_AUTH_FAIL: + if (hdcp_ver == HDCP_23) + it6162_tx_hdcp_setup(it6162, HDCP_14, + true); + else + it6162_tx_hdcp_disable(it6162); + + break; + default: + it6162_tx_hdcp_setup(it6162, + it6162->hdcp_version, + true); + break; + } + it6162_hdcp_queue_prop_update(it6162, cp_status); + } + } +} + +static void it6162_interrupt_handler(struct it6162 *it6162) +{ + unsigned int int_status, tx_status; + enum drm_connector_status connector_status; + struct device *dev = it6162->dev; + struct regmap *regmap = it6162->regmap; + int err; + + err = regmap_read(regmap, OFFSET_EVENT_CHG, &int_status); + if (err < 0) { + dev_err(dev, "read failed rx reg[0x%x] err: %d", + OFFSET_EVENT_CHG, err); + return; + } + + regmap_write(it6162->regmap, OFFSET_EVENT_CHG, 0xFF); + + if (!!GET_BUFFER_STATUS(int_status)) { + regmap_write(it6162->regmap, OFFSET_DRIVER_DATA, int_status); + it6162->data_buf_sts = GET_BUFFER_STATUS(int_status); + wake_up(&it6162->data_buf_wait); + } + + if (!(int_status & EVENT_CHG)) + return; + + err = regmap_read(regmap, OFFSET_TX_STATUS, &tx_status); + if (err < 0) { + dev_err(dev, "read failed rx reg[0x%x] err: %d", + OFFSET_TX_STATUS, err); + return; + } + + connector_status = GET_TX_HPD_STATUS(tx_status) ? + connector_status_connected : + connector_status_disconnected; + + if (it6162->connector_status != connector_status) { + it6162->connector_status = connector_status; + drm_bridge_hpd_notify(&it6162->bridge, + it6162->connector_status); + } + + if (it6162->en_hdcp && GET_TX_VIDEO_STATUS(tx_status) && + connector_status == connector_status_connected) + queue_delayed_work(system_wq, &it6162->hdcp_work, + msecs_to_jiffies(2000)); +} + +static int it6162_wait_ready_event(struct it6162 *it6162) +{ + unsigned int val; + int ret; + struct device *dev = it6162->dev; + struct regmap *regmap = it6162->regmap; + + ret = regmap_read(regmap, OFFSET_EVENT_CHG, &val); + if (ret < 0) { + dev_err(dev, "read failed rx reg[0x%x] err: %d", + OFFSET_EVENT_CHG, ret); + return ret; + } + + return val & EVENT_READY; +} + +static bool it6162_wait_mcu_ready(struct it6162 *it6162) +{ + int ret, val; + + ret = readx_poll_timeout(it6162_wait_ready_event, it6162, val, + val == EVENT_READY, 100 * 1000, 1500 * 1000); + if (ret) { + dev_err(it6162->dev, "timeout waiting for MCU ready"); + return false; + } + + return true; +} + +static void it6162_reset_init(struct it6162 *it6162) +{ + struct it6162_mipi_cfg *cfg = &it6162->mipi_cfg; + u8 cfg_val = 0; + + cfg_val = FIELD_PREP(MIPI_CLOCK_MODE_MASK, cfg->continuous_clk) | + FIELD_PREP(MIPI_LANE_SWAP_MASK, cfg->lane_swap) | + FIELD_PREP(MIPI_PN_SWAP_MASK, cfg->pn_swap) | + FIELD_PREP(MIPI_LANE_NUM_MASK, cfg->lane_num - 1); + + guard(mutex)(&it6162->lock); + regmap_write(it6162->regmap, OFFSET_MIPI_CONFIG_L, cfg_val); + regmap_write(it6162->regmap, OFFSET_MIPI_CONFIG_H, cfg->mode); + regmap_write(it6162->regmap, OFFSET_TX_CONFIG, 0x00); + regmap_write(it6162->regmap, OFFSET_TX_SETTING, 0x00); + it6162_infoblock_trigger(it6162, B_CONFIG_CHG | B_SET_CHG); +} + +static void it6162_hw_reset(struct it6162 *it6162) +{ + usleep_range(10000, 20000); + gpiod_set_value_cansleep(it6162->gpiod_reset, 1); + usleep_range(1000, 2000); + gpiod_set_value_cansleep(it6162->gpiod_reset, 0); + usleep_range(10000, 20000); +} + +static int it6162_regulator_disable(struct it6162 *it6162, + struct regulator *supply, const char *name) +{ + int err; + + err = regulator_disable(supply); + if (err) + dev_err(it6162->dev, "failed to disable %s: %d", name, err); + + return err; +} + +static int it6162_platform_set_power(struct it6162 *it6162) +{ + int err; + + err = regulator_enable(it6162->ivdd); + if (err) + return err; + + usleep_range(1000, 2000); + + err = regulator_enable(it6162->pwr1833); + if (err) + goto err_disable_ivdd; + + err = regulator_enable(it6162->ovdd); + if (err) + goto err_disable_pwr1833; + + it6162_hw_reset(it6162); + + return 0; + +err_disable_pwr1833: + it6162_regulator_disable(it6162, it6162->pwr1833, "ovdd1833"); + usleep_range(1000, 2000); +err_disable_ivdd: + it6162_regulator_disable(it6162, it6162->ivdd, "ivdd"); + return err; +} + +static int it6162_platform_clear_power(struct it6162 *it6162) +{ + int err, ret; + + ret = it6162_regulator_disable(it6162, it6162->ovdd, "ovdd"); + + err = it6162_regulator_disable(it6162, it6162->pwr1833, "ovdd1833"); + ret = ret ?: err; + + usleep_range(1000, 2000); + + err = it6162_regulator_disable(it6162, it6162->ivdd, "ivdd"); + + return ret ?: err; +} + +static void it6162_power_off_action(void *data) +{ + it6162_platform_clear_power(data); +} + +static int it6162_detect_devices(struct it6162 *it6162) +{ + struct device *dev = it6162->dev; + const struct it6162_chip_info *chip_info; + u32 chip_id, version; + u8 buf[6]; + int ret = -ENODEV; + + chip_info = i2c_get_match_data(it6162->it6162_i2c); + if (!chip_info) + return -ENODEV; + + if (it6162_platform_set_power(it6162) < 0) + return -ENODEV; + + /* Firmware must finish booting before register access is valid */ + if (!it6162_wait_mcu_ready(it6162)) + goto err_power_off; + + ret = regmap_bulk_read(it6162->regmap, OFFSET_CHIP_ID_H, &buf[0], 6); + if (ret < 0) { + dev_err(dev, "failed to read chip id: %d", ret); + goto err_power_off; + } + + chip_id = (buf[0] << 16) | (buf[1] << 8) | (buf[2]); + version = (buf[3] << 16) | (buf[4] << 8) | (buf[5]); + if (chip_id != chip_info->chip_id || version < chip_info->version) { + dev_err(dev, "chip mismatch: id=0x%06x ver=0x%06x", + chip_id, version); + ret = -ENODEV; + goto err_power_off; + } + + return devm_add_action_or_reset(dev, it6162_power_off_action, it6162); + +err_power_off: + it6162_platform_clear_power(it6162); + return ret; +} + +static int it6162_hw_start(struct it6162 *it6162) +{ + it6162_hw_reset(it6162); + + if (!it6162_wait_mcu_ready(it6162)) + return -ENODEV; + + it6162->connector_status = connector_status_disconnected; + it6162_reset_init(it6162); + enable_irq(it6162->it6162_i2c->irq); + it6162->hw_ready = true; + return 0; +} + +static void it6162_config_default(struct it6162 *it6162) +{ + struct it6162_mipi_cfg *mipi_cfg = &it6162->mipi_cfg; + struct it6162_hdcp_cfg *hdcp_cfg = &it6162->hdcp_cfg; + + mipi_cfg->lane_num = 4; + mipi_cfg->pn_swap = false; + mipi_cfg->lane_swap = false; + mipi_cfg->en_port[0] = false; + mipi_cfg->en_port[1] = false; + mipi_cfg->continuous_clk = true; + mipi_cfg->mode = SYNC_EVENT; + mipi_cfg->format = MIPI_DSI_FMT_RGB888; + mipi_cfg->mode_flags = MIPI_DSI_MODE_VIDEO; + + it6162->en_hdcp = false; + hdcp_cfg->hdcp_version = HDCP_AUTO; + hdcp_cfg->hdcp_encryption = true; + hdcp_cfg->stream_ID = 0; + + it6162->connector_status = connector_status_disconnected; +} + +static enum drm_connector_status it6162_detect(struct it6162 *it6162) +{ + struct regmap *regmap = it6162->regmap; + unsigned int tx_status; + + if (regmap_read(regmap, OFFSET_TX_STATUS, &tx_status) < 0) + return connector_status_unknown; + + return GET_TX_HPD_STATUS(tx_status) ? connector_status_connected : + connector_status_disconnected; +} + +static int it6162_get_edid_block(void *data, u8 *buf, unsigned int block, + size_t len) +{ + struct it6162 *it6162 = data; + u8 chunk[DATA_BUFFER_DEPTH]; + unsigned int i, cnt; + int ret; + u8 config; + + if (len > EDID_LENGTH) + return -EINVAL; + + guard(mutex)(&it6162->lock); + for (i = 0, cnt = 0; i < len; i += DATA_BUFFER_DEPTH, cnt++) { + config = (block << 2) | (cnt); + ret = it6162_infoblock_request_data(it6162, HOST_SET_EDID_R, + config, chunk); + if (ret < 0) + return -EIO; + + memcpy(buf + i, chunk, min_t(size_t, len - i, DATA_BUFFER_DEPTH)); + } + + return 0; +} + +static int it6162_audio_update_hw_params(struct it6162 *it6162, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms) +{ + enum it6162_audio_select select; + enum it6162_audio_sample_rate sample_rate; + unsigned int sample_width; + unsigned int val; + + switch (hparms->sample_rate) { + case 32000: + sample_rate = SAMPLE_RATE_32K; + break; + case 44100: + sample_rate = SAMPLE_RATE_44_1K; + break; + case 48000: + sample_rate = SAMPLE_RATE_48K; + break; + case 88200: + sample_rate = SAMPLE_RATE_88_2K; + break; + case 96000: + sample_rate = SAMPLE_RATE_96K; + break; + case 176400: + sample_rate = SAMPLE_RATE_176_4K; + break; + case 192000: + sample_rate = SAMPLE_RATE_192K; + break; + default: + return -EINVAL; + } + + switch (hparms->sample_width) { + case 16: + sample_width = WORD_LENGTH_16BIT; + break; + case 18: + sample_width = WORD_LENGTH_18BIT; + break; + case 20: + sample_width = WORD_LENGTH_20BIT; + break; + case 24: + sample_width = WORD_LENGTH_24BIT; + break; + default: + return -EINVAL; + } + + switch (fmt->fmt) { + case HDMI_I2S: + select = I2S; + break; + case HDMI_SPDIF: + select = SPDIF; + break; + default: + return -EINVAL; + } + + guard(mutex)(&it6162->lock); + val = FIELD_PREP(MASK_AUDIO_CHANNEL_NUM, hparms->channels) | + FIELD_PREP(MASK_AUDIO_SELECT, select) | + FIELD_PREP(MASK_AUDIO_TYPE, LPCM); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL0, val); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL1, sample_rate); + + val = FIELD_PREP(MASK_I2S_BUS_MODE, 0) | + FIELD_PREP(MASK_I2S_WORD_LEN, sample_width) | + FIELD_PREP(MASK_I2S_VALID, 1); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL2, val); + return it6162_infoblock_trigger(it6162, HOST_SET_AUDIO_INFO); +} + +static void it6162_disable_audio(struct it6162 *it6162) +{ + guard(mutex)(&it6162->lock); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL0, 0x00); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL1, 0x00); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL2, 0x00); + it6162_infoblock_trigger(it6162, HOST_SET_AUDIO_INFO); +} + +static irqreturn_t it6162_int_threaded_handler(int unused, void *data) +{ + struct it6162 *it6162 = data; + + it6162_interrupt_handler(it6162); + return IRQ_HANDLED; +} + +static void it6162_hdcp_work(struct work_struct *work) +{ + struct it6162 *it6162 = container_of(work, struct it6162, + hdcp_work.work); + + it6162_hdcp_handler(it6162); +} + +static void it6162_cancel_work_action(void *data) +{ + struct it6162 *it6162 = data; + struct drm_connector *connector = NULL; + + cancel_delayed_work_sync(&it6162->hdcp_work); + + if (cancel_work_sync(&it6162->hdcp_prop_work)) { + scoped_guard(mutex, &it6162->lock) { + connector = it6162->hdcp_prop_connector; + it6162->hdcp_prop_connector = NULL; + } + } + + if (connector) + drm_connector_put(connector); +} + +static struct mipi_dsi_host * +it6162_of_get_dsi_host_by_port(struct it6162 *it6162, int port) +{ + struct device_node *of = it6162->dev->of_node; + struct device_node *host_node; + struct device_node *endpoint; + struct mipi_dsi_host *dsi_host; + + endpoint = of_graph_get_endpoint_by_regs(of, port, -1); + if (!endpoint) + return ERR_PTR(-ENODEV); + + host_node = of_graph_get_remote_port_parent(endpoint); + of_node_put(endpoint); + if (!host_node) + return ERR_PTR(-ENODEV); + + dsi_host = of_find_mipi_dsi_host_by_node(host_node); + of_node_put(host_node); + if (!dsi_host) + return ERR_PTR(-EPROBE_DEFER); + + return dsi_host; +} + +static int it6162_of_get_dsi_host(struct it6162 *it6162) +{ + struct mipi_dsi_host *dsi_host; + int port, host_count = 0; + + for (port = 0; port < 2; port++) { + dsi_host = it6162_of_get_dsi_host_by_port(it6162, port); + if (IS_ERR(dsi_host)) { + if (PTR_ERR(dsi_host) == -EPROBE_DEFER) + return -EPROBE_DEFER; + continue; + } + + host_count++; + } + + return host_count == 0 ? -ENODEV : 0; +} + +static int it6162_load_mipi_pars_from_port(struct it6162 *it6162, int port) +{ + struct device_node *of = it6162->dev->of_node; + struct device_node *endpoint; + struct it6162_mipi_cfg *mipicfg = &it6162->mipi_cfg; + u32 data_lanes[4] = {1}; + u32 lane_polarities[5] = {0}; + int dsi_lanes; + + endpoint = of_graph_get_endpoint_by_regs(of, port, -1); + if (!endpoint) + return 0; + + dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); + if (dsi_lanes < 0) { + of_node_put(endpoint); + return dsi_lanes; + } + + mipicfg->lane_num = dsi_lanes; + + of_property_read_u32_array(endpoint, "data-lanes", data_lanes, + dsi_lanes); + /* only supports full reversal of all lanes, not arbitrary remapping */ + if (data_lanes[0] == 4) + mipicfg->lane_swap = true; + + of_property_read_u32_array(endpoint, "lane-polarities", + lane_polarities, dsi_lanes + 1); + /* applies Dp/Dn swap globally; mixing polarities across lanes is invalid */ + if (lane_polarities[0] != 0) + mipicfg->pn_swap = true; + + if (of_property_present(endpoint, "clock-noncontinuous")) { + mipicfg->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; + mipicfg->continuous_clk = false; + } + + of_node_put(endpoint); + return dsi_lanes; +} + +static int it6162_attach_dsi(struct it6162 *it6162) +{ + struct device *dev = it6162->dev; + struct device_node *np = dev->of_node; + const struct mipi_dsi_device_info info = {"it6162-mipi", 0, np}; + struct mipi_dsi_device *dsi; + struct mipi_dsi_host *host; + struct it6162_mipi_cfg *mipi_cfg = &it6162->mipi_cfg; + int ret = 0; + + it6162->dsi = NULL; + for (int port = 0; port < 2; port++) { + host = it6162_of_get_dsi_host_by_port(it6162, port); + if (IS_ERR(host)) + continue; + + mipi_cfg->en_port[port] = true; + + dsi = devm_mipi_dsi_device_register_full(dev, host, &info); + if (IS_ERR(dsi)) { + dev_err(dev, "failed to create dsi device"); + return PTR_ERR(dsi); + } + /* uses a single DSI configuration for both ports in dual-link mode */ + if (!it6162->dsi) { + ret = it6162_load_mipi_pars_from_port(it6162, port); + if (ret <= 0) + return ret; + it6162->dsi = dsi; + } + + dsi->lanes = mipi_cfg->lane_num; + dsi->format = mipi_cfg->format; + dsi->mode_flags = mipi_cfg->mode_flags; + ret = devm_mipi_dsi_attach(dev, dsi); + if (ret) { + dev_err(dev, "failed to attach dsi device %d", port); + return ret; + } + } + + return it6162_hw_start(it6162); +} + +static bool it6162_of_get_audio(struct it6162 *it6162) +{ + struct device_node *np = it6162->dev->of_node; + struct device_node *audio_port; + + audio_port = of_graph_get_port_by_id(np, 2); + if (audio_port) { + of_node_put(audio_port); + return true; + } + + return false; +} + +static int it6162_init_pdata(struct it6162 *it6162) +{ + struct device *dev = it6162->dev; + + it6162->ivdd = devm_regulator_get(dev, "ivdd"); + if (IS_ERR(it6162->ivdd)) + return dev_err_probe(dev, PTR_ERR(it6162->ivdd), + "failed to get ivdd regulator"); + + it6162->pwr1833 = devm_regulator_get(dev, "ovdd1833"); + if (IS_ERR(it6162->pwr1833)) + return dev_err_probe(dev, PTR_ERR(it6162->pwr1833), + "failed to get ovdd1833 regulator"); + + it6162->ovdd = devm_regulator_get(dev, "ovdd"); + if (IS_ERR(it6162->ovdd)) + return dev_err_probe(dev, PTR_ERR(it6162->ovdd), + "failed to get ovdd regulator"); + + it6162->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(it6162->gpiod_reset)) + return dev_err_probe(dev, PTR_ERR(it6162->gpiod_reset), + "failed to get reset gpio\n"); + + return 0; +} + +static int it6162_bridge_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + struct drm_device *drm = bridge->dev; + + it6162->drm = drm; + if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { + drm_dbg(drm, "it6162 driver only copes with atomic updates"); + return -EOPNOTSUPP; + } + + return 0; +} + +static enum drm_mode_status +it6162_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + unsigned long long rate; + + rate = drm_hdmi_compute_mode_clock(mode, 8, DRM_OUTPUT_COLOR_FORMAT_RGB444); + if (rate == 0) + return MODE_NOCLOCK; + + return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate); +} + +static enum drm_connector_status +it6162_bridge_detect(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162->hw_ready ? it6162_detect(it6162) : + connector_status_disconnected; +} + +static inline void +it6162_avi_to_video_setting(struct hdmi_avi_infoframe *avi_info, + struct it6162_video_settings *video) +{ + video->vic = avi_info->video_code; + + switch (avi_info->picture_aspect) { + case HDMI_PICTURE_ASPECT_4_3: + video->h_aspect = 4; + video->v_aspect = 3; + break; + case HDMI_PICTURE_ASPECT_16_9: + video->h_aspect = 16; + video->v_aspect = 9; + break; + case HDMI_PICTURE_ASPECT_64_27: + video->h_aspect = 64; + video->v_aspect = 27; + break; + case HDMI_PICTURE_ASPECT_256_135: + video->h_aspect = 256; + video->v_aspect = 135; + break; + default: + video->h_aspect = 4; + video->v_aspect = 3; + break; + } + + video->pix_rep = avi_info->pixel_repeat + 1; +} + +static inline void +it6162_display_mode_to_settings(struct drm_display_mode *mode, + struct it6162_video_settings *settings) +{ + settings->hpol = !!(mode->flags & DRM_MODE_FLAG_PHSYNC); + settings->vpol = !!(mode->flags & DRM_MODE_FLAG_PVSYNC); + settings->prog = !(mode->flags & DRM_MODE_FLAG_INTERLACE); + + settings->clock = mode->clock; + settings->hdew = mode->hdisplay; + settings->hfp = mode->hsync_start - mode->hdisplay; + settings->hsw = mode->hsync_end - mode->hsync_start; + settings->hbp = mode->htotal - mode->hsync_end; + settings->htotal = mode->htotal; + settings->vdew = mode->vdisplay; + settings->vfp = mode->vsync_start - mode->vdisplay; + settings->vsw = mode->vsync_end - mode->vsync_start; + settings->vbp = mode->vtotal - mode->vsync_end; + settings->vtotal = mode->vtotal; +} + +static void it6162_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_commit *state) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + struct drm_crtc_state *crtc_state; + struct drm_connector_state *conn_state; + struct drm_connector *connector; + struct hdmi_avi_infoframe *avi; + struct it6162_video_settings video_setting = {}; + + connector = drm_atomic_get_new_connector_for_encoder(state, + bridge->encoder); + if (!connector) + return; + + conn_state = drm_atomic_get_new_connector_state(state, connector); + if (!conn_state) + return; + + crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); + if (!crtc_state) + return; + + scoped_guard(mutex, &it6162->lock) { + it6162->connector = connector; + it6162->hdcp_gen++; + } + + it6162->content_protection = conn_state->content_protection; + + drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); + avi = &conn_state->hdmi.infoframes.avi.data.avi; + video_setting.colorspace = avi->colorspace; + it6162_avi_to_video_setting(avi, &video_setting); + /* + * The firmware needs the HDMI output timing, i.e. the requested mode. + * The front porch widened by it6162_bridge_atomic_check() only + * applies to the MIPI input and lives in adjusted_mode. + */ + it6162_display_mode_to_settings(&crtc_state->mode, &video_setting); + + it6162_mipi_set_video_timing(it6162, &video_setting); + it6162_tx_enable(it6162); + it6162_mipi_enable(it6162); +} + +static int it6162_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_display_mode *adj = &crtc_state->adjusted_mode; + struct drm_display_mode *mode = &crtc_state->mode; + struct it6162 *it6162 = bridge_to_it6162(bridge); + u32 hfp, hsw, hbp; + u32 clock; + u32 hfp_check; + + clock = mode->clock; + hfp = mode->hsync_start - mode->hdisplay; + hsw = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + hfp_check = DIV_ROUND_UP(65 * clock, 1000000) + 4; + if (hfp >= hfp_check) + return 0; + + if (hbp > hfp_check - hfp) { + adj->hsync_start = adj->hdisplay + hfp_check; + adj->hsync_end = adj->hsync_start + hsw; + drm_dbg(it6162->drm, "adjusted hsync on MIPI bus: %u, %u", + adj->hsync_start, adj->hsync_end); + } + + return 0; +} + +static void it6162_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_commit *state) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + scoped_guard(mutex, &it6162->lock) { + it6162->connector = NULL; + it6162->hdcp_gen++; + } + + it6162_tx_disable(it6162); + it6162_mipi_disable(it6162); +} + +static const struct drm_edid * +it6162_bridge_read_edid(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return drm_edid_read_custom(connector, it6162_get_edid_block, it6162); +} + +static int it6162_bridge_hdmi_audio_prepare(struct drm_bridge *bridge, + struct drm_connector *connector, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *params) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + int ret; + + ret = it6162_audio_update_hw_params(it6162, fmt, params); + if (ret < 0) + return ret; + + return drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, + ¶ms->cea); +} + +static void it6162_bridge_hdmi_audio_shutdown(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector); + it6162_disable_audio(it6162); +} + +static enum drm_mode_status +it6162_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, + const struct drm_display_mode *mode, + unsigned long long tmds_rate) +{ + /*IT6162 hdmi supports HDMI2.0 600Mhz*/ + if (tmds_rate > 600000000) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static inline int +it6162_write_infoframe(struct it6162 *it6162, const u8 *buffer, size_t len) +{ + if (len > DATA_BUFFER_DEPTH) + return -EINVAL; + + guard(mutex)(&it6162->lock); + regmap_bulk_write(it6162->regmap, OFFSET_DATA_BUFFER, buffer, len); + regmap_write(it6162->regmap, OFFSET_DATA_TYPE_IDX, len); + it6162_infoblock_trigger(it6162, HOST_SET_CEA_INFOFRAME); + + return 0; +} + +static inline int it6162_clear_infoframe(struct it6162 *it6162, u8 type) +{ + guard(mutex)(&it6162->lock); + regmap_write(it6162->regmap, OFFSET_DATA_TYPE_IDX, 3); + regmap_write(it6162->regmap, OFFSET_DATA_BUFFER, type); + regmap_write(it6162->regmap, OFFSET_DATA_BUFFER + 1, 0x00); + regmap_write(it6162->regmap, OFFSET_DATA_BUFFER + 2, 0x00); + it6162_infoblock_trigger(it6162, HOST_SET_CEA_INFOFRAME); + + return 0; +} + +static int +it6162_bridge_hdmi_write_avi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_write_infoframe(it6162, buffer, len); +} + +static int +it6162_bridge_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_clear_infoframe(it6162, HDMI_INFOFRAME_TYPE_AVI); +} + +static int +it6162_bridge_hdmi_write_audio_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_write_infoframe(it6162, buffer, len); +} + +static int +it6162_bridge_hdmi_clear_audio_infoframe(struct drm_bridge *bridge) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_clear_infoframe(it6162, HDMI_INFOFRAME_TYPE_AUDIO); +} + +static int +it6162_bridge_hdmi_write_spd_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_write_infoframe(it6162, buffer, len); +} + +static int +it6162_bridge_hdmi_clear_spd_infoframe(struct drm_bridge *bridge) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_clear_infoframe(it6162, HDMI_INFOFRAME_TYPE_SPD); +} + +static int +it6162_bridge_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_write_infoframe(it6162, buffer, len); +} + +static int +it6162_bridge_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_clear_infoframe(it6162, HDMI_INFOFRAME_TYPE_VENDOR); +} + +static const struct drm_bridge_funcs it6162_bridge_funcs = { + .attach = it6162_bridge_attach, + .mode_valid = it6162_bridge_mode_valid, + .detect = it6162_bridge_detect, + + .atomic_enable = it6162_bridge_atomic_enable, + .atomic_disable = it6162_bridge_atomic_disable, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_create_state = drm_atomic_helper_bridge_create_state, + .atomic_check = it6162_bridge_atomic_check, + + .edid_read = it6162_bridge_read_edid, + + .hdmi_clear_hdmi_infoframe = it6162_bridge_hdmi_clear_hdmi_infoframe, + .hdmi_write_hdmi_infoframe = it6162_bridge_hdmi_write_hdmi_infoframe, + .hdmi_clear_avi_infoframe = it6162_bridge_hdmi_clear_avi_infoframe, + .hdmi_write_avi_infoframe = it6162_bridge_hdmi_write_avi_infoframe, + .hdmi_clear_spd_infoframe = it6162_bridge_hdmi_clear_spd_infoframe, + .hdmi_write_spd_infoframe = it6162_bridge_hdmi_write_spd_infoframe, + .hdmi_clear_audio_infoframe = it6162_bridge_hdmi_clear_audio_infoframe, + .hdmi_write_audio_infoframe = it6162_bridge_hdmi_write_audio_infoframe, + + .hdmi_tmds_char_rate_valid = it6162_hdmi_tmds_char_rate_valid, + .hdmi_audio_prepare = it6162_bridge_hdmi_audio_prepare, + .hdmi_audio_shutdown = it6162_bridge_hdmi_audio_shutdown, +}; + +static int it6162_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct device_node *np = dev->of_node; + struct it6162 *it6162; + int ret; + + it6162 = devm_drm_bridge_alloc(dev, struct it6162, bridge, + &it6162_bridge_funcs); + if (IS_ERR(it6162)) + return PTR_ERR(it6162); + + it6162->dev = dev; + + ret = devm_mutex_init(dev, &it6162->lock); + if (ret) + return ret; + + init_waitqueue_head(&it6162->data_buf_wait); + INIT_DELAYED_WORK(&it6162->hdcp_work, it6162_hdcp_work); + INIT_WORK(&it6162->hdcp_prop_work, it6162_hdcp_prop_work); + + ret = it6162_of_get_dsi_host(it6162); + if (ret < 0) + return ret; + + ret = it6162_i2c_regmap_init(client, it6162); + if (ret != 0) + return ret; + + ret = it6162_init_pdata(it6162); + if (ret) + return ret; + + it6162_config_default(it6162); + + if (it6162_detect_devices(it6162) < 0) + return -ENODEV; + + if (!client->irq) { + dev_err(dev, "Failed to get INTP IRQ"); + return -ENODEV; + } + + it6162->bridge.of_node = np; + it6162->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | + DRM_BRIDGE_OP_HDMI | DRM_BRIDGE_OP_MODES; + + it6162->bridge.type = DRM_MODE_CONNECTOR_HDMIA; + + it6162->bridge.vendor = "ITE"; + it6162->bridge.product = "IT6162"; + + if (it6162_of_get_audio(it6162)) { + it6162->bridge.ops |= DRM_BRIDGE_OP_HDMI_AUDIO; + it6162->bridge.hdmi_audio_dev = dev; + it6162->bridge.hdmi_audio_max_i2s_playback_channels = 8; + it6162->bridge.hdmi_audio_dai_port = 2; + } + + /* + * devres releases in reverse order: the IRQ is freed and the HDCP + * works are cancelled before the bridge is removed, which destroys + * the HPD notification mutex, and before the supplies and the driver + * mutex are released. + */ + ret = devm_drm_bridge_add(dev, &it6162->bridge); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, it6162_cancel_work_action, it6162); + if (ret) + return ret; + + ret = devm_request_threaded_irq(&client->dev, client->irq, NULL, + it6162_int_threaded_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT | + IRQF_NO_AUTOEN, + "it6162-intp", it6162); + if (ret) + return ret; + + return it6162_attach_dsi(it6162); +} + +static const struct it6162_chip_info it6162_chip_info = { + .chip_id = 0x616200, + .version = 0x006500, +}; + +static const struct of_device_id it6162_dt_ids[] = { + { .compatible = "ite,it6162", .data = &it6162_chip_info}, + { } +}; +MODULE_DEVICE_TABLE(of, it6162_dt_ids); + +static const struct i2c_device_id it6162_i2c_ids[] = { + { "it6162", (kernel_ulong_t)&it6162_chip_info }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, it6162_i2c_ids); + +static struct i2c_driver it6162_driver = { + .driver = { + .name = "it6162", + .of_match_table = it6162_dt_ids, + }, + .probe = it6162_probe, + .id_table = it6162_i2c_ids, +}; +module_i2c_driver(it6162_driver); + +MODULE_AUTHOR("Pet Weng <pet.weng@ite.com.tw>"); +MODULE_AUTHOR("Hermes Wu <Hermes.Wu@ite.com.tw>"); +MODULE_DESCRIPTION("it6162 MIPI to HDMI driver"); +MODULE_LICENSE("GPL"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 2/2] drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver @ 2026-10-29 10:12 ` Hermes Wu 0 siblings, 0 replies; 7+ messages in thread From: Hermes Wu @ 2026-10-29 10:12 UTC (permalink / raw) To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Luca Ceresoli Cc: Pet.Weng, Kenneth.Hung, Hermes Wu, dri-devel, devicetree, linux-kernel, Dmitry Baryshkov, Hermes Wu Add support for the ITE IT6162 MIPI DSI to HDMI 2.0 bridge chip. The IT6162 is an I2C-controlled bridge that supports the following configurations: - Single MIPI DSI input: up to 4K @ 30Hz - Dual MIPI DSI input (combined): up to 4K @ 60Hz The driver implements the DRM bridge and connector frameworks, including mode setting, EDID retrieval, and HPD support. Also add a MAINTAINERS entry for the newly introduced ITE IT6162 MIPI DSI to HDMI bridge driver, covering the driver source file and the device tree binding document. Assisted-by: Claude Opus 5.5 Signed-off-by: Hermes Wu <Hermes.wu@ite.com.tw> --- MAINTAINERS | 7 + drivers/gpu/drm/bridge/Kconfig | 17 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ite-it6162.c | 1764 +++++++++++++++++++++++++++++++++++ 4 files changed, 1789 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 89ea35a35c6809e5066674cff3d5b7b129db4c49..0ebf58c322e1e2e8916aeba38a3828873374c1d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13977,6 +13977,13 @@ W: https://linuxtv.org Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/tuners/it913x* +ITE IT6162 MIPI DSI TO HDMI BRIDGE DRIVER +M: Hermes Wu <Hermes.wu@ite.com.tw> +L: dri-devel@lists.freedesktop.org +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/ite,it6162.yaml +F: drivers/gpu/drm/bridge/ite-it6162.c + ITE IT6263 LVDS TO HDMI BRIDGE DRIVER M: Liu Ying <victor.liu@nxp.com> L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index c7da6b02d7b6b281f328fb3016ea2f167f8da093..59d4911222747a233cfd3fbe8394f0d1652e5c9d 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -106,6 +106,23 @@ config DRM_INNO_HDMI select DRM_DISPLAY_HELPER select DRM_KMS_HELPER +config DRM_ITE_IT6162 + tristate "iTE IT6162 DSI to HDMI bridge" + depends on OF + select REGMAP_I2C + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + select DRM_KMS_HELPER + select DRM_HDMI_HELPER + select DRM_DISPLAY_HDMI_HELPER + select DRM_DISPLAY_HDCP_HELPER + select DRM_DISPLAY_HELPER + help + Driver for iTE IT6162 DSI to HDMI bridge + chip driver that converts DSI to HDMI signals + support up to 4k60 with 2 MIPI DSI + Please say Y if you have such hardware. + config DRM_ITE_IT6263 tristate "ITE IT6263 LVDS/HDMI bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 15cc821d85b7ea6f3cdc313f3e521b028de567d7..2e082ec616d1119788be4deaf7e3436d52404237 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -11,6 +11,7 @@ tda998x-y := tda998x_drv.o obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o obj-$(CONFIG_DRM_INNO_HDMI) += inno-hdmi.o +obj-$(CONFIG_DRM_ITE_IT6162) += ite-it6162.o obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o diff --git a/drivers/gpu/drm/bridge/ite-it6162.c b/drivers/gpu/drm/bridge/ite-it6162.c new file mode 100644 index 0000000000000000000000000000000000000000..5f83722ff4e61e4b6ccb27f53c30ff19328804f3 --- /dev/null +++ b/drivers/gpu/drm/bridge/ite-it6162.c @@ -0,0 +1,1764 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2024 ITE Tech. Inc. + */ +#include <linux/bitfield.h> +#include <linux/gpio/consumer.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/of_irq.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <drm/display/drm_hdcp_helper.h> +#include <drm/display/drm_hdmi_helper.h> +#include <drm/display/drm_hdmi_state_helper.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_bridge_connector.h> +#include <drm/drm_drv.h> +#include <drm/drm_edid.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_of.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_print.h> +#include <video/videomode.h> +#include <sound/hdmi-codec.h> + +#define DATA_BUFFER_DEPTH 32 + +#define OFFSET_CHIP_ID_H 0x00 +#define OFFSET_CHIP_ID_M 0x01 +#define OFFSET_CHIP_ID_L 0x02 +#define OFFSET_VERSION_H 0x03 +#define OFFSET_VERSION_M 0x04 +#define OFFSET_VERSION_L 0x05 + +#define OFFSET_MIPI_CONFIG_L 0x06 +#define MIPI_CLOCK_MODE_MASK BIT(6) +#define MIPI_PORT1_EN_MASK BIT(5) +#define MIPI_PORT0_EN_MASK BIT(4) +#define MIPI_LANE_SWAP_MASK BIT(3) +#define MIPI_PN_SWAP_MASK BIT(2) +#define MIPI_LANE_NUM_MASK 0x3 +#define MIPI_PORT_EN_MASK (MIPI_PORT1_EN_MASK | MIPI_PORT0_EN_MASK) + +#define OFFSET_MIPI_CONFIG_H 0x07 +#define OFFSET_TX_CONFIG 0x08 + +#define OFFSET_TX_SETTING 0x09 +#define TX_HDCP_VER_MASK 0xC0 +#define TX_HDCP_ENCRYP_MASK BIT(5) +#define TX_STREAM_TYPE_MASK BIT(4) + +#define OFFSET_MIPI_STATUS 0x0A +#define OFFSET_TX_STATUS 0x0C +#define B_TX_STATUS_HPD 7 +#define B_TX_STATUS_VIDEO_STB 6 +#define B_TX_STATUS_HDCP 4 +#define M_TX_STATUS_HDCP 0x30 + +#define TX_VIDEO_STB BIT(B_TX_STATUS_VIDEO_STB) +#define TX_STATUS_HPD BIT(B_TX_STATUS_HPD) + +#define GET_TX_HPD_STATUS(x) (((x) & TX_STATUS_HPD) >> B_TX_STATUS_HPD) +#define GET_TX_VIDEO_STATUS(x) (((x) & TX_VIDEO_STB) >> B_TX_STATUS_VIDEO_STB) +#define GET_TX_HDCP_STATUS(x) (((x) & M_TX_STATUS_HDCP) >> B_TX_STATUS_HDCP) + +#define OFFSET_SINK_CAP 0x0D +#define B_SINK_CAP_HDCP_VER 4 +#define M_SINK_CAP_HDCP_VER 0x30 + +#define GET_SINK_CAP_HDCP_VER(x) (((x) & M_SINK_CAP_HDCP_VER) >> B_SINK_CAP_HDCP_VER) + +#define OFFSET_DRIVER_DATA 0x0E + +#define OFFSET_DATA_TYPE_IDX 0x0F +#define OFFSET_DATA_BUFFER 0x20 + +#define OFFSET_AUDIO_CTRL0 0x3C +#define MASK_AUDIO_CHANNEL_NUM 0x0F +#define MASK_AUDIO_SELECT 0x30 +#define MASK_AUDIO_TYPE 0xC0 + +#define OFFSET_AUDIO_CTRL1 0x3D +#define OFFSET_AUDIO_CTRL2 0x3E +#define MASK_I2S_BUS_MODE 0x1F +#define MASK_I2S_WORD_LEN 0x60 +#define MASK_I2S_VALID 0x80 + +#define OFFSET_HOST_SET 0xFE +#define B_CONFIG_CHG BIT(7) +#define B_SET_CHG BIT(6) +#define HOST_SET_VIDEO_INFO (1) +#define HOST_SET_AUDIO_INFO (2) +#define HOST_SET_VIDEO_AUDIO_INFO (3) +#define HOST_SET_EDID_R (0x04) +#define HOST_SET_HDCP_R (0x05) +#define HOST_SET_CEA_INFOFRAME (0x0E) + +#define OFFSET_EVENT_CHG 0xFF +#define B_EVENT_CHG_BUFFER 4 +#define M_EVENT_CHG_BUFFER_STS (0x30) + +#define B_EVENT_CHG 1 +#define B_EVENT_IC_READY 0 + +#define EVENT_CHG BIT(B_EVENT_CHG) +#define EVENT_READY BIT(B_EVENT_IC_READY) + +#define GET_BUFFER_STATUS(x) (((x) & M_EVENT_CHG_BUFFER_STS) >> B_EVENT_CHG_BUFFER) + +#define TIMEOUT_INFOBLOCK_MS 1800 + +enum it6162_audio_select { + I2S = 0, + SPDIF, +}; + +enum it6162_audio_word_length { + WORD_LENGTH_16BIT = 0x0, + WORD_LENGTH_18BIT = 0x1, + WORD_LENGTH_20BIT = 0x2, + WORD_LENGTH_24BIT = 0x3, +}; + +enum it6162_audio_sample_rate { + SAMPLE_RATE_32K = 0x3, + SAMPLE_RATE_48K = 0x2, + SAMPLE_RATE_64K = 0xB, + SAMPLE_RATE_96K = 0xA, + SAMPLE_RATE_192K = 0xE, + SAMPLE_RATE_44_1K = 0x0, + SAMPLE_RATE_88_2K = 0x8, + SAMPLE_RATE_176_4K = 0xC, +}; + +enum it6162_audio_type { + LPCM = 0, + NLPCM, +}; + +enum data_buf_sts { + NO_STS = 0x00, + BUF_READY = 0x01, + BUF_FAIL = 0x02, +}; + +enum hdcp_state { + HDCP_STATE_IDLE = 0x00, + HDCP_STATE_AUTH_DONE = 0x01, + HDCP_STATE_AUTH_FAIL = 0x02, +}; + +enum hdcp_ver { + HDCP_DISABLE = 0x0, + HDCP_14 = 0x1, + HDCP_23 = 0x2, + HDCP_AUTO = 0x3, +}; + +struct it6162_chip_info { + u32 chip_id; + u32 version; +}; + +struct it6162_video_settings { + u8 vic; + u32 clock; + u16 htotal; + u16 hfp; + u16 hsw; + u16 hbp; + u16 hdew; + u16 vtotal; + u16 vfp; + u16 vsw; + u16 vbp; + u16 vdew; + u8 hpol; + u8 vpol; + u8 prog; + u16 v_aspect; + u16 h_aspect; + u8 pix_rep; + u8 colorspace; +}; + +enum sync_mode { + SYNC_EVENT = 0x0, + SYNC_PULSE = 0x1, + SYNC_AUTO = 0x2, +}; + +struct it6162_mipi_cfg { + bool en_port[2]; + u8 lane_num; + bool pn_swap; + bool lane_swap; + bool continuous_clk; + enum sync_mode mode; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; +}; + +struct it6162_hdcp_cfg { + enum hdcp_ver hdcp_version; + bool hdcp_encryption; + u8 stream_ID; +}; + +struct it6162_infoblock_msg { + u8 action; + int len; + u8 msg[32]; +}; + +struct it6162 { + struct drm_bridge bridge; + struct device *dev; + struct drm_connector *connector; + enum drm_connector_status connector_status; + struct drm_device *drm; + + struct i2c_client *it6162_i2c; + struct regmap *regmap; + + struct regulator *pwr1833; + struct regulator *ovdd; + struct regulator *ivdd; + struct gpio_desc *gpiod_reset; + + bool hw_ready; + bool en_hdcp; + + /*lock the infoblock write setting and buffer access*/ + struct mutex lock; + + enum data_buf_sts data_buf_sts; + wait_queue_head_t data_buf_wait; + + /* it6162 DSI RX related params */ + struct mipi_dsi_device *dsi; + struct it6162_mipi_cfg mipi_cfg; + + struct delayed_work hdcp_work; + + /* + * HDCP content protection property update, protected by lock. + * hdcp_gen changes whenever the connector is set or cleared, so that + * updates from an ended session are not published. + * hdcp_prop_connector is non-NULL only while a queued, not yet + * started hdcp_prop_work owns a reference to it. + */ + u32 hdcp_gen; + struct work_struct hdcp_prop_work; + struct drm_connector *hdcp_prop_connector; + u64 hdcp_prop_value; + u32 hdcp_prop_gen; + + enum hdcp_state hdcp_sts; + enum hdcp_ver hdcp_version; + struct it6162_hdcp_cfg hdcp_cfg; + + unsigned int content_protection; +}; + +static struct it6162 *bridge_to_it6162(struct drm_bridge *bridge) +{ + return container_of(bridge, struct it6162, bridge); +} + +static const struct regmap_config it6162_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, + .cache_type = REGCACHE_NONE, +}; + +static inline int it6162_i2c_regmap_init(struct i2c_client *client, + struct it6162 *it6162) +{ + it6162->it6162_i2c = client; + i2c_set_clientdata(client, it6162); + it6162->regmap = devm_regmap_init_i2c(it6162->it6162_i2c, + &it6162_regmap_config); + if (IS_ERR(it6162->regmap)) + return PTR_ERR(it6162->regmap); + + return 0; +} + +static int it6162_wait_command_complete(struct it6162 *it6162) +{ + struct device *dev = it6162->dev; + struct regmap *regmap = it6162->regmap; + unsigned int val; + int ret; + + ret = regmap_read(regmap, OFFSET_HOST_SET, &val); + if (ret < 0) { + dev_err(dev, "read failed rx reg[0x%x]", OFFSET_HOST_SET); + return ret; + } + return val; +} + +static int it6162_infoblock_trigger(struct it6162 *it6162, u8 setting) +{ + struct device *dev = it6162->dev; + int status; + int val; + + regmap_write(it6162->regmap, OFFSET_HOST_SET, setting); + /* OFFSET_HOST_SET is cleared by firmware when the command is processed */ + status = readx_poll_timeout(it6162_wait_command_complete, it6162, val, + val <= 0, 50 * 1000, + TIMEOUT_INFOBLOCK_MS * 1000); + if (status < 0 || val != 0) { + dev_err(dev, "infoblock command timeout: status=%d val=%d", + status, val); + return -ETIMEDOUT; + } + + return 0; +} + +static int it6162_infoblock_request_data(struct it6162 *it6162, + u8 request_type, u8 index, u8 *buf) +{ + struct device *dev = it6162->dev; + int status; + + it6162->data_buf_sts = NO_STS; + regmap_write(it6162->regmap, OFFSET_DATA_TYPE_IDX, index); + status = it6162_infoblock_trigger(it6162, request_type); + if (status < 0) + return status; + /* data_buf_sts is updated asynchronously by the interrupt handler */ + if (wait_event_timeout(it6162->data_buf_wait, + it6162->data_buf_sts != NO_STS, + msecs_to_jiffies(TIMEOUT_INFOBLOCK_MS)) == 0) { + dev_err(dev, "timeout waiting for data buffer"); + return -ETIMEDOUT; + } + + if (it6162->data_buf_sts != BUF_READY) { + dev_err(dev, "data buffer not ready: sts=%d", + it6162->data_buf_sts); + return -EIO; + } + + return regmap_bulk_read(it6162->regmap, OFFSET_DATA_BUFFER, buf, + DATA_BUFFER_DEPTH); +} + +static void it6162_mipi_disable(struct it6162 *it6162) +{ + guard(mutex)(&it6162->lock); + regmap_update_bits(it6162->regmap, OFFSET_MIPI_CONFIG_L, + MIPI_PORT_EN_MASK, 0x00); + it6162_infoblock_trigger(it6162, B_CONFIG_CHG); +} + +static void it6162_mipi_enable(struct it6162 *it6162) +{ + unsigned int cfg_val = 0; + + cfg_val = FIELD_PREP(MIPI_PORT1_EN_MASK, it6162->mipi_cfg.en_port[1]) | + FIELD_PREP(MIPI_PORT0_EN_MASK, it6162->mipi_cfg.en_port[0]); + + guard(mutex)(&it6162->lock); + regmap_update_bits(it6162->regmap, OFFSET_MIPI_CONFIG_L, + MIPI_PORT_EN_MASK, cfg_val); + it6162_infoblock_trigger(it6162, B_CONFIG_CHG); +} + +static void it6162_tx_hdcp_enable(struct it6162 *it6162, + struct it6162_hdcp_cfg *tx_out) +{ + int val; + struct regmap *regmap = it6162->regmap; + + guard(mutex)(&it6162->lock); + it6162->hdcp_sts = HDCP_STATE_IDLE; + + if (regmap_read(regmap, OFFSET_TX_SETTING, &val) < 0) { + dev_err(it6162->dev, "failed to read tx setting"); + return; + } + + val &= 0x0F; + val |= FIELD_PREP(TX_HDCP_VER_MASK, tx_out->hdcp_version) | + FIELD_PREP(TX_HDCP_ENCRYP_MASK, tx_out->hdcp_encryption) | + FIELD_PREP(TX_STREAM_TYPE_MASK, tx_out->stream_ID); + + regmap_write(regmap, OFFSET_TX_SETTING, val); + it6162_infoblock_trigger(it6162, B_SET_CHG); +} + +static void it6162_tx_hdcp_disable(struct it6162 *it6162) +{ + int val; + struct regmap *regmap = it6162->regmap; + + it6162->hdcp_sts = HDCP_STATE_IDLE; + it6162->hdcp_version = HDCP_DISABLE; + + guard(mutex)(&it6162->lock); + if (regmap_read(regmap, OFFSET_TX_SETTING, &val) < 0) { + dev_err(it6162->dev, "failed to read tx setting"); + return; + } + + regmap_write(it6162->regmap, OFFSET_TX_SETTING, val & 0x0F); + it6162_infoblock_trigger(it6162, B_SET_CHG); +} + +static void +it6162_tx_hdcp_setup(struct it6162 *it6162, u8 ver, bool encryption) +{ + struct it6162_hdcp_cfg tx_out; + + if (ver != HDCP_DISABLE) { + tx_out.hdcp_version = ver; + tx_out.hdcp_encryption = encryption; + tx_out.stream_ID = 0; + it6162_tx_hdcp_enable(it6162, &tx_out); + } else { + it6162_tx_hdcp_disable(it6162); + } +} + +static void it6162_tx_enable(struct it6162 *it6162) +{ + if (it6162->en_hdcp) + it6162->hdcp_version = it6162->hdcp_cfg.hdcp_version; + else + it6162->hdcp_version = HDCP_DISABLE; +} + +static void it6162_tx_disable(struct it6162 *it6162) +{ + cancel_delayed_work_sync(&it6162->hdcp_work); + it6162_tx_hdcp_setup(it6162, HDCP_DISABLE, false); +} + +static inline void +it6162_pack_video_setting(struct it6162 *it6162, + struct it6162_video_settings *settings, + struct it6162_infoblock_msg *msg) +{ + msg->msg[0x00] = settings->hdew & 0xFF; + msg->msg[0x01] = (settings->hdew >> 8) & 0x3F; + msg->msg[0x02] = settings->vdew & 0xFF; + msg->msg[0x03] = (settings->vdew >> 8) & 0x3F; + msg->msg[0x04] = settings->clock & 0xFF; + msg->msg[0x05] = (settings->clock >> 8) & 0xFF; + msg->msg[0x06] = (settings->clock >> 16) & 0xFF; + msg->msg[0x07] = (settings->clock >> 24) & 0xFF; + msg->msg[0x08] = settings->hfp & 0xFF; + msg->msg[0x09] = (settings->hfp >> 8) & 0x3F; + msg->msg[0x0A] = settings->hsw & 0xFF; + msg->msg[0x0B] = (settings->hsw >> 8) & 0x3F; + msg->msg[0x0C] = settings->hbp & 0xFF; + msg->msg[0x0D] = (settings->hbp >> 8) & 0x3F; + msg->msg[0x0E] = settings->vfp & 0xFF; + msg->msg[0x0F] = (settings->vfp >> 8) & 0x3F; + msg->msg[0x10] = settings->vsw & 0xFF; + msg->msg[0x11] = (settings->vsw >> 8) & 0x3F; + msg->msg[0x12] = settings->vbp & 0xFF; + msg->msg[0x13] = (settings->vbp >> 8) & 0x3F; + msg->msg[0x14] = (settings->prog << 2) | + (settings->vpol << 1) | + settings->hpol; + + msg->msg[0x15] = settings->v_aspect; + msg->msg[0x16] = settings->h_aspect & 0xFF; + msg->msg[0x17] = settings->h_aspect >> 8; + msg->msg[0x18] = settings->pix_rep; + msg->msg[0x19] = settings->vic; + msg->msg[0x1A] = settings->colorspace; + msg->msg[0x1B] = 1; + + msg->len = 0x1C; + msg->action = HOST_SET_VIDEO_INFO; +} + +static void it6162_mipi_set_video_timing(struct it6162 *it6162, + struct it6162_video_settings *mode) +{ + struct it6162_infoblock_msg msg; + + it6162_pack_video_setting(it6162, mode, &msg); + guard(mutex)(&it6162->lock); + regmap_bulk_write(it6162->regmap, OFFSET_DATA_BUFFER, &msg.msg, + msg.len); + it6162_infoblock_trigger(it6162, msg.action); +} + +static int +it6162_hdcp_read_information(struct it6162 *it6162, u8 *status, u8 *bksv) +{ + u8 buf[DATA_BUFFER_DEPTH]; + int ret; + + guard(mutex)(&it6162->lock); + ret = it6162_infoblock_request_data(it6162, HOST_SET_HDCP_R, 0x00, + buf); + if (ret < 0) + return ret; + + memcpy(status, buf, 2); + memcpy(bksv, buf + 2, 5); + return 0; +} + +static int it6162_hdcp_read_list(struct it6162 *it6162, + u8 *ksv_list, + int dev_count) +{ + u8 buf[DATA_BUFFER_DEPTH]; + int i, j, ret; + + if (!ksv_list || dev_count <= 0) + return -EINVAL; + + guard(mutex)(&it6162->lock); + for (i = 0; i < (dev_count / 6 + 1); i++) { + ret = it6162_infoblock_request_data(it6162, HOST_SET_HDCP_R, + i + 1, buf); + if (ret < 0) + return ret; + + for (j = 0; j < 30; j += 5) { + if ((i * 6 + j / 5) >= dev_count) + break; + + memcpy(&ksv_list[(i * 6 + j / 5) * 5], &buf[j], 5); + } + } + return dev_count; +} + +static void it6162_update_hdcp14(struct it6162 *it6162) +{ + struct drm_device *drm = it6162->drm; + int dev_count; + u8 bksv[5]; + u8 bstatus[2]; + u8 ksvlist[5 * 30]; + int ret; + + ret = it6162_hdcp_read_information(it6162, bstatus, bksv); + if (ret < 0) { + drm_err(drm, "fail to read Bstatus"); + return; + } + + dev_count = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); + if (dev_count == 0) + return; + + if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || + DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { + drm_err(drm, "HDCP1.4 Max Topology Limit Exceeded"); + return; + } + + dev_count = dev_count > 30 ? 30 : dev_count; + ret = it6162_hdcp_read_list(it6162, ksvlist, dev_count); + if (ret < 0) { + drm_err(drm, "fail to read KSV list"); + return; + } +} + +static void it6162_update_hdcp23(struct it6162 *it6162) +{ + struct drm_device *drm = it6162->drm; + int dev_count; + u8 rxid[5]; + u8 rxinfo[2]; + u8 rxid_list[5 * 30]; + int ret; + + ret = it6162_hdcp_read_information(it6162, rxinfo, rxid); + if (ret < 0) { + drm_err(drm, "fail to read Rxinfo"); + return; + } + + dev_count = (HDCP_2_2_DEV_COUNT_HI(rxinfo[0]) << 4 | + HDCP_2_2_DEV_COUNT_LO(rxinfo[1])); + if (dev_count == 0) + return; + + if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rxinfo[1]) || + HDCP_2_2_MAX_DEVS_EXCEEDED(rxinfo[1])) { + drm_err(drm, "HDCP2.3 Topology Max Size Exceeded"); + return; + } + + dev_count = dev_count > 30 ? 30 : dev_count; + ret = it6162_hdcp_read_list(it6162, rxid_list, dev_count); + if (ret < 0) { + drm_err(drm, "fail to read RxID list"); + return; + } +} + +static void it6162_update_hdcp(struct it6162 *it6162, u8 version) +{ + if (version == HDCP_23) + it6162_update_hdcp23(it6162); + else + it6162_update_hdcp14(it6162); +} + +static void it6162_hdcp_queue_prop_update(struct it6162 *it6162, u64 value) +{ + guard(mutex)(&it6162->lock); + + if (!it6162->connector) + return; + + it6162->hdcp_prop_value = value; + it6162->hdcp_prop_gen = it6162->hdcp_gen; + + if (it6162->hdcp_prop_connector) + return; + + it6162->hdcp_prop_connector = it6162->connector; + drm_connector_get(it6162->hdcp_prop_connector); + queue_work(system_wq, &it6162->hdcp_prop_work); +} + +static void it6162_hdcp_prop_work(struct work_struct *work) +{ + struct it6162 *it6162 = container_of(work, struct it6162, + hdcp_prop_work); + struct drm_connector *connector; + struct drm_modeset_lock *connection_mutex; + + scoped_guard(mutex, &it6162->lock) { + connector = it6162->hdcp_prop_connector; + it6162->hdcp_prop_connector = NULL; + } + + if (!connector) + return; + + connection_mutex = &connector->dev->mode_config.connection_mutex; + drm_modeset_lock(connection_mutex, NULL); + + scoped_guard(mutex, &it6162->lock) { + if (it6162->hdcp_prop_gen == it6162->hdcp_gen && + it6162->connector == connector && + connector->state->content_protection != + DRM_MODE_CONTENT_PROTECTION_UNDESIRED) + drm_hdcp_update_content_protection(connector, + it6162->hdcp_prop_value); + } + + drm_modeset_unlock(connection_mutex); + drm_connector_put(connector); +} + +static void it6162_hdcp_handler(struct it6162 *it6162) +{ + struct regmap *regmap = it6162->regmap; + unsigned int tx_status, sink_cap; + enum hdcp_state hdcp_sts; + struct it6162_hdcp_cfg *hdcp_cfg = &it6162->hdcp_cfg; + u8 hdcp_ver; + u64 cp_status = DRM_MODE_CONTENT_PROTECTION_DESIRED; + + if (hdcp_cfg->hdcp_version == HDCP_DISABLE || !it6162->en_hdcp) + return; + + if (it6162->hdcp_version != HDCP_DISABLE) { + if (regmap_read(regmap, OFFSET_TX_STATUS, &tx_status) < 0 || + regmap_read(regmap, OFFSET_SINK_CAP, &sink_cap) < 0) + return; + + if (!GET_TX_VIDEO_STATUS(tx_status)) { + drm_dbg(it6162->drm, "video not stable, skip hdcp check"); + return; + } + + hdcp_sts = GET_TX_HDCP_STATUS(tx_status); + hdcp_ver = GET_SINK_CAP_HDCP_VER(sink_cap); + if (it6162->hdcp_sts != hdcp_sts || + it6162->hdcp_sts == HDCP_STATE_IDLE) { + it6162->hdcp_sts = hdcp_sts; + switch (hdcp_sts) { + case HDCP_STATE_AUTH_DONE: + it6162_update_hdcp(it6162, hdcp_ver); + cp_status = DRM_MODE_CONTENT_PROTECTION_ENABLED; + break; + case HDCP_STATE_AUTH_FAIL: + if (hdcp_ver == HDCP_23) + it6162_tx_hdcp_setup(it6162, HDCP_14, + true); + else + it6162_tx_hdcp_disable(it6162); + + break; + default: + it6162_tx_hdcp_setup(it6162, + it6162->hdcp_version, + true); + break; + } + it6162_hdcp_queue_prop_update(it6162, cp_status); + } + } +} + +static void it6162_interrupt_handler(struct it6162 *it6162) +{ + unsigned int int_status, tx_status; + enum drm_connector_status connector_status; + struct device *dev = it6162->dev; + struct regmap *regmap = it6162->regmap; + int err; + + err = regmap_read(regmap, OFFSET_EVENT_CHG, &int_status); + if (err < 0) { + dev_err(dev, "read failed rx reg[0x%x] err: %d", + OFFSET_EVENT_CHG, err); + return; + } + + regmap_write(it6162->regmap, OFFSET_EVENT_CHG, 0xFF); + + if (!!GET_BUFFER_STATUS(int_status)) { + regmap_write(it6162->regmap, OFFSET_DRIVER_DATA, int_status); + it6162->data_buf_sts = GET_BUFFER_STATUS(int_status); + wake_up(&it6162->data_buf_wait); + } + + if (!(int_status & EVENT_CHG)) + return; + + err = regmap_read(regmap, OFFSET_TX_STATUS, &tx_status); + if (err < 0) { + dev_err(dev, "read failed rx reg[0x%x] err: %d", + OFFSET_TX_STATUS, err); + return; + } + + connector_status = GET_TX_HPD_STATUS(tx_status) ? + connector_status_connected : + connector_status_disconnected; + + if (it6162->connector_status != connector_status) { + it6162->connector_status = connector_status; + drm_bridge_hpd_notify(&it6162->bridge, + it6162->connector_status); + } + + if (it6162->en_hdcp && GET_TX_VIDEO_STATUS(tx_status) && + connector_status == connector_status_connected) + queue_delayed_work(system_wq, &it6162->hdcp_work, + msecs_to_jiffies(2000)); +} + +static int it6162_wait_ready_event(struct it6162 *it6162) +{ + unsigned int val; + int ret; + struct device *dev = it6162->dev; + struct regmap *regmap = it6162->regmap; + + ret = regmap_read(regmap, OFFSET_EVENT_CHG, &val); + if (ret < 0) { + dev_err(dev, "read failed rx reg[0x%x] err: %d", + OFFSET_EVENT_CHG, ret); + return ret; + } + + return val & EVENT_READY; +} + +static bool it6162_wait_mcu_ready(struct it6162 *it6162) +{ + int ret, val; + + ret = readx_poll_timeout(it6162_wait_ready_event, it6162, val, + val == EVENT_READY, 100 * 1000, 1500 * 1000); + if (ret) { + dev_err(it6162->dev, "timeout waiting for MCU ready"); + return false; + } + + return true; +} + +static void it6162_reset_init(struct it6162 *it6162) +{ + struct it6162_mipi_cfg *cfg = &it6162->mipi_cfg; + u8 cfg_val = 0; + + cfg_val = FIELD_PREP(MIPI_CLOCK_MODE_MASK, cfg->continuous_clk) | + FIELD_PREP(MIPI_LANE_SWAP_MASK, cfg->lane_swap) | + FIELD_PREP(MIPI_PN_SWAP_MASK, cfg->pn_swap) | + FIELD_PREP(MIPI_LANE_NUM_MASK, cfg->lane_num - 1); + + guard(mutex)(&it6162->lock); + regmap_write(it6162->regmap, OFFSET_MIPI_CONFIG_L, cfg_val); + regmap_write(it6162->regmap, OFFSET_MIPI_CONFIG_H, cfg->mode); + regmap_write(it6162->regmap, OFFSET_TX_CONFIG, 0x00); + regmap_write(it6162->regmap, OFFSET_TX_SETTING, 0x00); + it6162_infoblock_trigger(it6162, B_CONFIG_CHG | B_SET_CHG); +} + +static void it6162_hw_reset(struct it6162 *it6162) +{ + usleep_range(10000, 20000); + gpiod_set_value_cansleep(it6162->gpiod_reset, 1); + usleep_range(1000, 2000); + gpiod_set_value_cansleep(it6162->gpiod_reset, 0); + usleep_range(10000, 20000); +} + +static int it6162_regulator_disable(struct it6162 *it6162, + struct regulator *supply, const char *name) +{ + int err; + + err = regulator_disable(supply); + if (err) + dev_err(it6162->dev, "failed to disable %s: %d", name, err); + + return err; +} + +static int it6162_platform_set_power(struct it6162 *it6162) +{ + int err; + + err = regulator_enable(it6162->ivdd); + if (err) + return err; + + usleep_range(1000, 2000); + + err = regulator_enable(it6162->pwr1833); + if (err) + goto err_disable_ivdd; + + err = regulator_enable(it6162->ovdd); + if (err) + goto err_disable_pwr1833; + + it6162_hw_reset(it6162); + + return 0; + +err_disable_pwr1833: + it6162_regulator_disable(it6162, it6162->pwr1833, "ovdd1833"); + usleep_range(1000, 2000); +err_disable_ivdd: + it6162_regulator_disable(it6162, it6162->ivdd, "ivdd"); + return err; +} + +static int it6162_platform_clear_power(struct it6162 *it6162) +{ + int err, ret; + + ret = it6162_regulator_disable(it6162, it6162->ovdd, "ovdd"); + + err = it6162_regulator_disable(it6162, it6162->pwr1833, "ovdd1833"); + ret = ret ?: err; + + usleep_range(1000, 2000); + + err = it6162_regulator_disable(it6162, it6162->ivdd, "ivdd"); + + return ret ?: err; +} + +static void it6162_power_off_action(void *data) +{ + it6162_platform_clear_power(data); +} + +static int it6162_detect_devices(struct it6162 *it6162) +{ + struct device *dev = it6162->dev; + const struct it6162_chip_info *chip_info; + u32 chip_id, version; + u8 buf[6]; + int ret = -ENODEV; + + chip_info = i2c_get_match_data(it6162->it6162_i2c); + if (!chip_info) + return -ENODEV; + + if (it6162_platform_set_power(it6162) < 0) + return -ENODEV; + + /* Firmware must finish booting before register access is valid */ + if (!it6162_wait_mcu_ready(it6162)) + goto err_power_off; + + ret = regmap_bulk_read(it6162->regmap, OFFSET_CHIP_ID_H, &buf[0], 6); + if (ret < 0) { + dev_err(dev, "failed to read chip id: %d", ret); + goto err_power_off; + } + + chip_id = (buf[0] << 16) | (buf[1] << 8) | (buf[2]); + version = (buf[3] << 16) | (buf[4] << 8) | (buf[5]); + if (chip_id != chip_info->chip_id || version < chip_info->version) { + dev_err(dev, "chip mismatch: id=0x%06x ver=0x%06x", + chip_id, version); + ret = -ENODEV; + goto err_power_off; + } + + return devm_add_action_or_reset(dev, it6162_power_off_action, it6162); + +err_power_off: + it6162_platform_clear_power(it6162); + return ret; +} + +static int it6162_hw_start(struct it6162 *it6162) +{ + it6162_hw_reset(it6162); + + if (!it6162_wait_mcu_ready(it6162)) + return -ENODEV; + + it6162->connector_status = connector_status_disconnected; + it6162_reset_init(it6162); + enable_irq(it6162->it6162_i2c->irq); + it6162->hw_ready = true; + return 0; +} + +static void it6162_config_default(struct it6162 *it6162) +{ + struct it6162_mipi_cfg *mipi_cfg = &it6162->mipi_cfg; + struct it6162_hdcp_cfg *hdcp_cfg = &it6162->hdcp_cfg; + + mipi_cfg->lane_num = 4; + mipi_cfg->pn_swap = false; + mipi_cfg->lane_swap = false; + mipi_cfg->en_port[0] = false; + mipi_cfg->en_port[1] = false; + mipi_cfg->continuous_clk = true; + mipi_cfg->mode = SYNC_EVENT; + mipi_cfg->format = MIPI_DSI_FMT_RGB888; + mipi_cfg->mode_flags = MIPI_DSI_MODE_VIDEO; + + it6162->en_hdcp = false; + hdcp_cfg->hdcp_version = HDCP_AUTO; + hdcp_cfg->hdcp_encryption = true; + hdcp_cfg->stream_ID = 0; + + it6162->connector_status = connector_status_disconnected; +} + +static enum drm_connector_status it6162_detect(struct it6162 *it6162) +{ + struct regmap *regmap = it6162->regmap; + unsigned int tx_status; + + if (regmap_read(regmap, OFFSET_TX_STATUS, &tx_status) < 0) + return connector_status_unknown; + + return GET_TX_HPD_STATUS(tx_status) ? connector_status_connected : + connector_status_disconnected; +} + +static int it6162_get_edid_block(void *data, u8 *buf, unsigned int block, + size_t len) +{ + struct it6162 *it6162 = data; + u8 chunk[DATA_BUFFER_DEPTH]; + unsigned int i, cnt; + int ret; + u8 config; + + if (len > EDID_LENGTH) + return -EINVAL; + + guard(mutex)(&it6162->lock); + for (i = 0, cnt = 0; i < len; i += DATA_BUFFER_DEPTH, cnt++) { + config = (block << 2) | (cnt); + ret = it6162_infoblock_request_data(it6162, HOST_SET_EDID_R, + config, chunk); + if (ret < 0) + return -EIO; + + memcpy(buf + i, chunk, min_t(size_t, len - i, DATA_BUFFER_DEPTH)); + } + + return 0; +} + +static int it6162_audio_update_hw_params(struct it6162 *it6162, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms) +{ + enum it6162_audio_select select; + enum it6162_audio_sample_rate sample_rate; + unsigned int sample_width; + unsigned int val; + + switch (hparms->sample_rate) { + case 32000: + sample_rate = SAMPLE_RATE_32K; + break; + case 44100: + sample_rate = SAMPLE_RATE_44_1K; + break; + case 48000: + sample_rate = SAMPLE_RATE_48K; + break; + case 88200: + sample_rate = SAMPLE_RATE_88_2K; + break; + case 96000: + sample_rate = SAMPLE_RATE_96K; + break; + case 176400: + sample_rate = SAMPLE_RATE_176_4K; + break; + case 192000: + sample_rate = SAMPLE_RATE_192K; + break; + default: + return -EINVAL; + } + + switch (hparms->sample_width) { + case 16: + sample_width = WORD_LENGTH_16BIT; + break; + case 18: + sample_width = WORD_LENGTH_18BIT; + break; + case 20: + sample_width = WORD_LENGTH_20BIT; + break; + case 24: + sample_width = WORD_LENGTH_24BIT; + break; + default: + return -EINVAL; + } + + switch (fmt->fmt) { + case HDMI_I2S: + select = I2S; + break; + case HDMI_SPDIF: + select = SPDIF; + break; + default: + return -EINVAL; + } + + guard(mutex)(&it6162->lock); + val = FIELD_PREP(MASK_AUDIO_CHANNEL_NUM, hparms->channels) | + FIELD_PREP(MASK_AUDIO_SELECT, select) | + FIELD_PREP(MASK_AUDIO_TYPE, LPCM); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL0, val); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL1, sample_rate); + + val = FIELD_PREP(MASK_I2S_BUS_MODE, 0) | + FIELD_PREP(MASK_I2S_WORD_LEN, sample_width) | + FIELD_PREP(MASK_I2S_VALID, 1); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL2, val); + return it6162_infoblock_trigger(it6162, HOST_SET_AUDIO_INFO); +} + +static void it6162_disable_audio(struct it6162 *it6162) +{ + guard(mutex)(&it6162->lock); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL0, 0x00); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL1, 0x00); + regmap_write(it6162->regmap, OFFSET_AUDIO_CTRL2, 0x00); + it6162_infoblock_trigger(it6162, HOST_SET_AUDIO_INFO); +} + +static irqreturn_t it6162_int_threaded_handler(int unused, void *data) +{ + struct it6162 *it6162 = data; + + it6162_interrupt_handler(it6162); + return IRQ_HANDLED; +} + +static void it6162_hdcp_work(struct work_struct *work) +{ + struct it6162 *it6162 = container_of(work, struct it6162, + hdcp_work.work); + + it6162_hdcp_handler(it6162); +} + +static void it6162_cancel_work_action(void *data) +{ + struct it6162 *it6162 = data; + struct drm_connector *connector = NULL; + + cancel_delayed_work_sync(&it6162->hdcp_work); + + if (cancel_work_sync(&it6162->hdcp_prop_work)) { + scoped_guard(mutex, &it6162->lock) { + connector = it6162->hdcp_prop_connector; + it6162->hdcp_prop_connector = NULL; + } + } + + if (connector) + drm_connector_put(connector); +} + +static struct mipi_dsi_host * +it6162_of_get_dsi_host_by_port(struct it6162 *it6162, int port) +{ + struct device_node *of = it6162->dev->of_node; + struct device_node *host_node; + struct device_node *endpoint; + struct mipi_dsi_host *dsi_host; + + endpoint = of_graph_get_endpoint_by_regs(of, port, -1); + if (!endpoint) + return ERR_PTR(-ENODEV); + + host_node = of_graph_get_remote_port_parent(endpoint); + of_node_put(endpoint); + if (!host_node) + return ERR_PTR(-ENODEV); + + dsi_host = of_find_mipi_dsi_host_by_node(host_node); + of_node_put(host_node); + if (!dsi_host) + return ERR_PTR(-EPROBE_DEFER); + + return dsi_host; +} + +static int it6162_of_get_dsi_host(struct it6162 *it6162) +{ + struct mipi_dsi_host *dsi_host; + int port, host_count = 0; + + for (port = 0; port < 2; port++) { + dsi_host = it6162_of_get_dsi_host_by_port(it6162, port); + if (IS_ERR(dsi_host)) { + if (PTR_ERR(dsi_host) == -EPROBE_DEFER) + return -EPROBE_DEFER; + continue; + } + + host_count++; + } + + return host_count == 0 ? -ENODEV : 0; +} + +static int it6162_load_mipi_pars_from_port(struct it6162 *it6162, int port) +{ + struct device_node *of = it6162->dev->of_node; + struct device_node *endpoint; + struct it6162_mipi_cfg *mipicfg = &it6162->mipi_cfg; + u32 data_lanes[4] = {1}; + u32 lane_polarities[5] = {0}; + int dsi_lanes; + + endpoint = of_graph_get_endpoint_by_regs(of, port, -1); + if (!endpoint) + return 0; + + dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); + if (dsi_lanes < 0) { + of_node_put(endpoint); + return dsi_lanes; + } + + mipicfg->lane_num = dsi_lanes; + + of_property_read_u32_array(endpoint, "data-lanes", data_lanes, + dsi_lanes); + /* only supports full reversal of all lanes, not arbitrary remapping */ + if (data_lanes[0] == 4) + mipicfg->lane_swap = true; + + of_property_read_u32_array(endpoint, "lane-polarities", + lane_polarities, dsi_lanes + 1); + /* applies Dp/Dn swap globally; mixing polarities across lanes is invalid */ + if (lane_polarities[0] != 0) + mipicfg->pn_swap = true; + + if (of_property_present(endpoint, "clock-noncontinuous")) { + mipicfg->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; + mipicfg->continuous_clk = false; + } + + of_node_put(endpoint); + return dsi_lanes; +} + +static int it6162_attach_dsi(struct it6162 *it6162) +{ + struct device *dev = it6162->dev; + struct device_node *np = dev->of_node; + const struct mipi_dsi_device_info info = {"it6162-mipi", 0, np}; + struct mipi_dsi_device *dsi; + struct mipi_dsi_host *host; + struct it6162_mipi_cfg *mipi_cfg = &it6162->mipi_cfg; + int ret = 0; + + it6162->dsi = NULL; + for (int port = 0; port < 2; port++) { + host = it6162_of_get_dsi_host_by_port(it6162, port); + if (IS_ERR(host)) + continue; + + mipi_cfg->en_port[port] = true; + + dsi = devm_mipi_dsi_device_register_full(dev, host, &info); + if (IS_ERR(dsi)) { + dev_err(dev, "failed to create dsi device"); + return PTR_ERR(dsi); + } + /* uses a single DSI configuration for both ports in dual-link mode */ + if (!it6162->dsi) { + ret = it6162_load_mipi_pars_from_port(it6162, port); + if (ret <= 0) + return ret; + it6162->dsi = dsi; + } + + dsi->lanes = mipi_cfg->lane_num; + dsi->format = mipi_cfg->format; + dsi->mode_flags = mipi_cfg->mode_flags; + ret = devm_mipi_dsi_attach(dev, dsi); + if (ret) { + dev_err(dev, "failed to attach dsi device %d", port); + return ret; + } + } + + return it6162_hw_start(it6162); +} + +static bool it6162_of_get_audio(struct it6162 *it6162) +{ + struct device_node *np = it6162->dev->of_node; + struct device_node *audio_port; + + audio_port = of_graph_get_port_by_id(np, 2); + if (audio_port) { + of_node_put(audio_port); + return true; + } + + return false; +} + +static int it6162_init_pdata(struct it6162 *it6162) +{ + struct device *dev = it6162->dev; + + it6162->ivdd = devm_regulator_get(dev, "ivdd"); + if (IS_ERR(it6162->ivdd)) + return dev_err_probe(dev, PTR_ERR(it6162->ivdd), + "failed to get ivdd regulator"); + + it6162->pwr1833 = devm_regulator_get(dev, "ovdd1833"); + if (IS_ERR(it6162->pwr1833)) + return dev_err_probe(dev, PTR_ERR(it6162->pwr1833), + "failed to get ovdd1833 regulator"); + + it6162->ovdd = devm_regulator_get(dev, "ovdd"); + if (IS_ERR(it6162->ovdd)) + return dev_err_probe(dev, PTR_ERR(it6162->ovdd), + "failed to get ovdd regulator"); + + it6162->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(it6162->gpiod_reset)) + return dev_err_probe(dev, PTR_ERR(it6162->gpiod_reset), + "failed to get reset gpio\n"); + + return 0; +} + +static int it6162_bridge_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + struct drm_device *drm = bridge->dev; + + it6162->drm = drm; + if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { + drm_dbg(drm, "it6162 driver only copes with atomic updates"); + return -EOPNOTSUPP; + } + + return 0; +} + +static enum drm_mode_status +it6162_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + unsigned long long rate; + + rate = drm_hdmi_compute_mode_clock(mode, 8, DRM_OUTPUT_COLOR_FORMAT_RGB444); + if (rate == 0) + return MODE_NOCLOCK; + + return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate); +} + +static enum drm_connector_status +it6162_bridge_detect(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162->hw_ready ? it6162_detect(it6162) : + connector_status_disconnected; +} + +static inline void +it6162_avi_to_video_setting(struct hdmi_avi_infoframe *avi_info, + struct it6162_video_settings *video) +{ + video->vic = avi_info->video_code; + + switch (avi_info->picture_aspect) { + case HDMI_PICTURE_ASPECT_4_3: + video->h_aspect = 4; + video->v_aspect = 3; + break; + case HDMI_PICTURE_ASPECT_16_9: + video->h_aspect = 16; + video->v_aspect = 9; + break; + case HDMI_PICTURE_ASPECT_64_27: + video->h_aspect = 64; + video->v_aspect = 27; + break; + case HDMI_PICTURE_ASPECT_256_135: + video->h_aspect = 256; + video->v_aspect = 135; + break; + default: + video->h_aspect = 4; + video->v_aspect = 3; + break; + } + + video->pix_rep = avi_info->pixel_repeat + 1; +} + +static inline void +it6162_display_mode_to_settings(struct drm_display_mode *mode, + struct it6162_video_settings *settings) +{ + settings->hpol = !!(mode->flags & DRM_MODE_FLAG_PHSYNC); + settings->vpol = !!(mode->flags & DRM_MODE_FLAG_PVSYNC); + settings->prog = !(mode->flags & DRM_MODE_FLAG_INTERLACE); + + settings->clock = mode->clock; + settings->hdew = mode->hdisplay; + settings->hfp = mode->hsync_start - mode->hdisplay; + settings->hsw = mode->hsync_end - mode->hsync_start; + settings->hbp = mode->htotal - mode->hsync_end; + settings->htotal = mode->htotal; + settings->vdew = mode->vdisplay; + settings->vfp = mode->vsync_start - mode->vdisplay; + settings->vsw = mode->vsync_end - mode->vsync_start; + settings->vbp = mode->vtotal - mode->vsync_end; + settings->vtotal = mode->vtotal; +} + +static void it6162_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_commit *state) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + struct drm_crtc_state *crtc_state; + struct drm_connector_state *conn_state; + struct drm_connector *connector; + struct hdmi_avi_infoframe *avi; + struct it6162_video_settings video_setting = {}; + + connector = drm_atomic_get_new_connector_for_encoder(state, + bridge->encoder); + if (!connector) + return; + + conn_state = drm_atomic_get_new_connector_state(state, connector); + if (!conn_state) + return; + + crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); + if (!crtc_state) + return; + + scoped_guard(mutex, &it6162->lock) { + it6162->connector = connector; + it6162->hdcp_gen++; + } + + it6162->content_protection = conn_state->content_protection; + + drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); + avi = &conn_state->hdmi.infoframes.avi.data.avi; + video_setting.colorspace = avi->colorspace; + it6162_avi_to_video_setting(avi, &video_setting); + /* + * The firmware needs the HDMI output timing, i.e. the requested mode. + * The front porch widened by it6162_bridge_atomic_check() only + * applies to the MIPI input and lives in adjusted_mode. + */ + it6162_display_mode_to_settings(&crtc_state->mode, &video_setting); + + it6162_mipi_set_video_timing(it6162, &video_setting); + it6162_tx_enable(it6162); + it6162_mipi_enable(it6162); +} + +static int it6162_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_display_mode *adj = &crtc_state->adjusted_mode; + struct drm_display_mode *mode = &crtc_state->mode; + struct it6162 *it6162 = bridge_to_it6162(bridge); + u32 hfp, hsw, hbp; + u32 clock; + u32 hfp_check; + + clock = mode->clock; + hfp = mode->hsync_start - mode->hdisplay; + hsw = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + hfp_check = DIV_ROUND_UP(65 * clock, 1000000) + 4; + if (hfp >= hfp_check) + return 0; + + if (hbp > hfp_check - hfp) { + adj->hsync_start = adj->hdisplay + hfp_check; + adj->hsync_end = adj->hsync_start + hsw; + drm_dbg(it6162->drm, "adjusted hsync on MIPI bus: %u, %u", + adj->hsync_start, adj->hsync_end); + } + + return 0; +} + +static void it6162_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_commit *state) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + scoped_guard(mutex, &it6162->lock) { + it6162->connector = NULL; + it6162->hdcp_gen++; + } + + it6162_tx_disable(it6162); + it6162_mipi_disable(it6162); +} + +static const struct drm_edid * +it6162_bridge_read_edid(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return drm_edid_read_custom(connector, it6162_get_edid_block, it6162); +} + +static int it6162_bridge_hdmi_audio_prepare(struct drm_bridge *bridge, + struct drm_connector *connector, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *params) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + int ret; + + ret = it6162_audio_update_hw_params(it6162, fmt, params); + if (ret < 0) + return ret; + + return drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, + ¶ms->cea); +} + +static void it6162_bridge_hdmi_audio_shutdown(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector); + it6162_disable_audio(it6162); +} + +static enum drm_mode_status +it6162_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, + const struct drm_display_mode *mode, + unsigned long long tmds_rate) +{ + /*IT6162 hdmi supports HDMI2.0 600Mhz*/ + if (tmds_rate > 600000000) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static inline int +it6162_write_infoframe(struct it6162 *it6162, const u8 *buffer, size_t len) +{ + if (len > DATA_BUFFER_DEPTH) + return -EINVAL; + + guard(mutex)(&it6162->lock); + regmap_bulk_write(it6162->regmap, OFFSET_DATA_BUFFER, buffer, len); + regmap_write(it6162->regmap, OFFSET_DATA_TYPE_IDX, len); + it6162_infoblock_trigger(it6162, HOST_SET_CEA_INFOFRAME); + + return 0; +} + +static inline int it6162_clear_infoframe(struct it6162 *it6162, u8 type) +{ + guard(mutex)(&it6162->lock); + regmap_write(it6162->regmap, OFFSET_DATA_TYPE_IDX, 3); + regmap_write(it6162->regmap, OFFSET_DATA_BUFFER, type); + regmap_write(it6162->regmap, OFFSET_DATA_BUFFER + 1, 0x00); + regmap_write(it6162->regmap, OFFSET_DATA_BUFFER + 2, 0x00); + it6162_infoblock_trigger(it6162, HOST_SET_CEA_INFOFRAME); + + return 0; +} + +static int +it6162_bridge_hdmi_write_avi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_write_infoframe(it6162, buffer, len); +} + +static int +it6162_bridge_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_clear_infoframe(it6162, HDMI_INFOFRAME_TYPE_AVI); +} + +static int +it6162_bridge_hdmi_write_audio_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_write_infoframe(it6162, buffer, len); +} + +static int +it6162_bridge_hdmi_clear_audio_infoframe(struct drm_bridge *bridge) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_clear_infoframe(it6162, HDMI_INFOFRAME_TYPE_AUDIO); +} + +static int +it6162_bridge_hdmi_write_spd_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_write_infoframe(it6162, buffer, len); +} + +static int +it6162_bridge_hdmi_clear_spd_infoframe(struct drm_bridge *bridge) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_clear_infoframe(it6162, HDMI_INFOFRAME_TYPE_SPD); +} + +static int +it6162_bridge_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_write_infoframe(it6162, buffer, len); +} + +static int +it6162_bridge_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) +{ + struct it6162 *it6162 = bridge_to_it6162(bridge); + + return it6162_clear_infoframe(it6162, HDMI_INFOFRAME_TYPE_VENDOR); +} + +static const struct drm_bridge_funcs it6162_bridge_funcs = { + .attach = it6162_bridge_attach, + .mode_valid = it6162_bridge_mode_valid, + .detect = it6162_bridge_detect, + + .atomic_enable = it6162_bridge_atomic_enable, + .atomic_disable = it6162_bridge_atomic_disable, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_create_state = drm_atomic_helper_bridge_create_state, + .atomic_check = it6162_bridge_atomic_check, + + .edid_read = it6162_bridge_read_edid, + + .hdmi_clear_hdmi_infoframe = it6162_bridge_hdmi_clear_hdmi_infoframe, + .hdmi_write_hdmi_infoframe = it6162_bridge_hdmi_write_hdmi_infoframe, + .hdmi_clear_avi_infoframe = it6162_bridge_hdmi_clear_avi_infoframe, + .hdmi_write_avi_infoframe = it6162_bridge_hdmi_write_avi_infoframe, + .hdmi_clear_spd_infoframe = it6162_bridge_hdmi_clear_spd_infoframe, + .hdmi_write_spd_infoframe = it6162_bridge_hdmi_write_spd_infoframe, + .hdmi_clear_audio_infoframe = it6162_bridge_hdmi_clear_audio_infoframe, + .hdmi_write_audio_infoframe = it6162_bridge_hdmi_write_audio_infoframe, + + .hdmi_tmds_char_rate_valid = it6162_hdmi_tmds_char_rate_valid, + .hdmi_audio_prepare = it6162_bridge_hdmi_audio_prepare, + .hdmi_audio_shutdown = it6162_bridge_hdmi_audio_shutdown, +}; + +static int it6162_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct device_node *np = dev->of_node; + struct it6162 *it6162; + int ret; + + it6162 = devm_drm_bridge_alloc(dev, struct it6162, bridge, + &it6162_bridge_funcs); + if (IS_ERR(it6162)) + return PTR_ERR(it6162); + + it6162->dev = dev; + + ret = devm_mutex_init(dev, &it6162->lock); + if (ret) + return ret; + + init_waitqueue_head(&it6162->data_buf_wait); + INIT_DELAYED_WORK(&it6162->hdcp_work, it6162_hdcp_work); + INIT_WORK(&it6162->hdcp_prop_work, it6162_hdcp_prop_work); + + ret = it6162_of_get_dsi_host(it6162); + if (ret < 0) + return ret; + + ret = it6162_i2c_regmap_init(client, it6162); + if (ret != 0) + return ret; + + ret = it6162_init_pdata(it6162); + if (ret) + return ret; + + it6162_config_default(it6162); + + if (it6162_detect_devices(it6162) < 0) + return -ENODEV; + + if (!client->irq) { + dev_err(dev, "Failed to get INTP IRQ"); + return -ENODEV; + } + + it6162->bridge.of_node = np; + it6162->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | + DRM_BRIDGE_OP_HDMI | DRM_BRIDGE_OP_MODES; + + it6162->bridge.type = DRM_MODE_CONNECTOR_HDMIA; + + it6162->bridge.vendor = "ITE"; + it6162->bridge.product = "IT6162"; + + if (it6162_of_get_audio(it6162)) { + it6162->bridge.ops |= DRM_BRIDGE_OP_HDMI_AUDIO; + it6162->bridge.hdmi_audio_dev = dev; + it6162->bridge.hdmi_audio_max_i2s_playback_channels = 8; + it6162->bridge.hdmi_audio_dai_port = 2; + } + + /* + * devres releases in reverse order: the IRQ is freed and the HDCP + * works are cancelled before the bridge is removed, which destroys + * the HPD notification mutex, and before the supplies and the driver + * mutex are released. + */ + ret = devm_drm_bridge_add(dev, &it6162->bridge); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, it6162_cancel_work_action, it6162); + if (ret) + return ret; + + ret = devm_request_threaded_irq(&client->dev, client->irq, NULL, + it6162_int_threaded_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT | + IRQF_NO_AUTOEN, + "it6162-intp", it6162); + if (ret) + return ret; + + return it6162_attach_dsi(it6162); +} + +static const struct it6162_chip_info it6162_chip_info = { + .chip_id = 0x616200, + .version = 0x006500, +}; + +static const struct of_device_id it6162_dt_ids[] = { + { .compatible = "ite,it6162", .data = &it6162_chip_info}, + { } +}; +MODULE_DEVICE_TABLE(of, it6162_dt_ids); + +static const struct i2c_device_id it6162_i2c_ids[] = { + { "it6162", (kernel_ulong_t)&it6162_chip_info }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, it6162_i2c_ids); + +static struct i2c_driver it6162_driver = { + .driver = { + .name = "it6162", + .of_match_table = it6162_dt_ids, + }, + .probe = it6162_probe, + .id_table = it6162_i2c_ids, +}; +module_i2c_driver(it6162_driver); + +MODULE_AUTHOR("Pet Weng <pet.weng@ite.com.tw>"); +MODULE_AUTHOR("Hermes Wu <Hermes.Wu@ite.com.tw>"); +MODULE_DESCRIPTION("it6162 MIPI to HDMI driver"); +MODULE_LICENSE("GPL"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v5 2/2] drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver 2026-10-29 10:12 ` Hermes Wu (?) @ 2026-10-29 10:46 ` sashiko-bot -1 siblings, 0 replies; 7+ messages in thread From: sashiko-bot @ 2026-10-29 10:46 UTC (permalink / raw) To: Hermes Wu; +Cc: dri-devel, devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 8 potential issue(s) to consider: - [High] drm/bridge: it6162: select DRM_DISPLAY_HDMI_STATE_HELPER in Kconfig - [High] drm/bridge: it6162: fix bridge.ops flags and set supported_hdmi_ver - [High] drm/bridge: it6162: avoid HPD notify self-deadlock in IRQ thread - [High] drm/bridge: it6162: initialize hardware before attaching DSI and bridge - [High] drm/bridge: it6162: fix OF node refcount underflow in it6162_attach_dsi() - [High] drm/bridge: it6162: missing port@3 next_bridge and attach flags handling - [Medium] drm/bridge: it6162: unreachable HDCP code and off-by-one KSV list read - [Medium] drm/bridge: it6162: missing single-DSI rate limit in it6162_hdmi_tmds_char_rate_valid() -- commit bb2197e5059c8f22ed7c430b26d564ec316ac54c Author: Hermes Wu <Hermes.wu@ite.com.tw> drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver This commit adds a DRM bridge driver for the ITE IT6162 MIPI DSI to HDMI 2.0 bridge chip, supporting single and dual MIPI DSI inputs, mode setting, EDID retrieval, HDMI audio, and HPD handling. > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > index c7da6b02d7b6b..59d4911222747 100644 > --- a/drivers/gpu/drm/bridge/Kconfig > +++ b/drivers/gpu/drm/bridge/Kconfig > @@ -106,6 +106,23 @@ config DRM_INNO_HDMI > select DRM_DISPLAY_HELPER > select DRM_KMS_HELPER > > +config DRM_ITE_IT6162 > + tristate "iTE IT6162 DSI to HDMI bridge" > + depends on OF > + select REGMAP_I2C > + select DRM_MIPI_DSI > + select DRM_PANEL_BRIDGE > + select DRM_KMS_HELPER > + select DRM_HDMI_HELPER > + select DRM_DISPLAY_HDMI_HELPER > + select DRM_DISPLAY_HDCP_HELPER > + select DRM_DISPLAY_HELPER [Severity: High] Should this select DRM_DISPLAY_HDMI_STATE_HELPER instead of DRM_HDMI_HELPER? There is no DRM_HDMI_HELPER Kconfig symbol in the kernel tree. Meanwhile, it6162_bridge_atomic_enable(), it6162_bridge_hdmi_audio_prepare(), and it6162_bridge_hdmi_audio_shutdown() call: drm_atomic_helper_connector_hdmi_update_infoframes() drm_atomic_helper_connector_hdmi_update_audio_infoframe() drm_atomic_helper_connector_hdmi_clear_audio_infoframe() which are compiled only when CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER is enabled. Without selecting DRM_DISPLAY_HDMI_STATE_HELPER, building the driver when no other enabled driver selects that symbol fails at link time with undefined references. [ ... ] > diff --git a/drivers/gpu/drm/bridge/ite-it6162.c b/drivers/gpu/drm/bridge/ite-it6162.c > new file mode 100644 > index 0000000000000..5f83722ff4e61 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/ite-it6162.c [ ... ] > +static int it6162_hdcp_read_list(struct it6162 *it6162, > + u8 *ksv_list, > + int dev_count) > +{ > + u8 buf[DATA_BUFFER_DEPTH]; > + int i, j, ret; > + > + if (!ksv_list || dev_count <= 0) > + return -EINVAL; > + > + guard(mutex)(&it6162->lock); > + for (i = 0; i < (dev_count / 6 + 1); i++) { > + ret = it6162_infoblock_request_data(it6162, HOST_SET_HDCP_R, > + i + 1, buf); > + if (ret < 0) > + return ret; > + > + for (j = 0; j < 30; j += 5) { > + if ((i * 6 + j / 5) >= dev_count) > + break; > + > + memcpy(&ksv_list[(i * 6 + j / 5) * 5], &buf[j], 5); > + } > + } > + return dev_count; > +} > + > +static void it6162_update_hdcp14(struct it6162 *it6162) > +{ > + struct drm_device *drm = it6162->drm; > + int dev_count; > + u8 bksv[5]; > + u8 bstatus[2]; > + u8 ksvlist[5 * 30]; > + int ret; > + > + ret = it6162_hdcp_read_information(it6162, bstatus, bksv); > + if (ret < 0) { > + drm_err(drm, "fail to read Bstatus"); > + return; > + } > + > + dev_count = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); > + if (dev_count == 0) > + return; > + > + if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || > + DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { > + drm_err(drm, "HDCP1.4 Max Topology Limit Exceeded"); > + return; > + } > + > + dev_count = dev_count > 30 ? 30 : dev_count; > + ret = it6162_hdcp_read_list(it6162, ksvlist, dev_count); > + if (ret < 0) { > + drm_err(drm, "fail to read KSV list"); > + return; > + } > +} [Severity: Medium] Is the HDCP support in this driver incomplete or unreachable? In it6162_config_default(), it6162->en_hdcp is initialized to false and is never set to true anywhere in the driver, while it6162->bridge.support_hdcp is also never set. In addition, it6162_bridge_atomic_enable() stores conn_state->content_protection into it6162->content_protection, which is never read, and it6162_tx_enable() never calls it6162_tx_hdcp_setup(). Also, in it6162_update_hdcp14() and it6162_update_hdcp23(), the read bstatus/bksv/ksvlist and rxinfo/rxid/rxid_list buffers are unused local arrays, and topology or read failures are not propagated back to it6162_hdcp_handler(), which still sets: cp_status = DRM_MODE_CONTENT_PROTECTION_ENABLED; Finally, in it6162_hdcp_read_list(), the loop bound (dev_count / 6 + 1) instead of DIV_ROUND_UP(dev_count, 6) performs an extra iteration when dev_count is an exact multiple of 6 (such as 6 or the clamped maximum of 30), requesting an out-of-range block index via it6162_infoblock_request_data(). Should the unused HDCP code be removed until it is wired up, or completed and fixed to use DIV_ROUND_UP(dev_count, 6)? [ ... ] > +static void it6162_interrupt_handler(struct it6162 *it6162) > +{ > + unsigned int int_status, tx_status; > + enum drm_connector_status connector_status; > + struct device *dev = it6162->dev; > + struct regmap *regmap = it6162->regmap; > + int err; > + > + err = regmap_read(regmap, OFFSET_EVENT_CHG, &int_status); > + if (err < 0) { > + dev_err(dev, "read failed rx reg[0x%x] err: %d", > + OFFSET_EVENT_CHG, err); > + return; > + } > + > + regmap_write(it6162->regmap, OFFSET_EVENT_CHG, 0xFF); > + > + if (!!GET_BUFFER_STATUS(int_status)) { > + regmap_write(it6162->regmap, OFFSET_DRIVER_DATA, int_status); > + it6162->data_buf_sts = GET_BUFFER_STATUS(int_status); > + wake_up(&it6162->data_buf_wait); > + } > + > + if (!(int_status & EVENT_CHG)) > + return; > + > + err = regmap_read(regmap, OFFSET_TX_STATUS, &tx_status); > + if (err < 0) { > + dev_err(dev, "read failed rx reg[0x%x] err: %d", > + OFFSET_TX_STATUS, err); > + return; > + } > + > + connector_status = GET_TX_HPD_STATUS(tx_status) ? > + connector_status_connected : > + connector_status_disconnected; > + > + if (it6162->connector_status != connector_status) { > + it6162->connector_status = connector_status; > + drm_bridge_hpd_notify(&it6162->bridge, > + it6162->connector_status); > + } [Severity: High] Won't calling drm_bridge_hpd_notify() synchronously inside it6162_interrupt_handler() deadlock when HPD processing reads the EDID? it6162_probe() registers it6162_int_threaded_handler() with IRQF_ONESHOT, so the IRQ line stays masked and the handler cannot re-enter until it6162_int_threaded_handler() returns. However, reading the EDID in it6162_get_edid_block() calls it6162_infoblock_request_data(), which blocks in wait_event_timeout() on it6162->data_buf_wait waiting for it6162_int_threaded_handler() to service the buffer status interrupt and call wake_up(&it6162->data_buf_wait): it6162_int_threaded_handler() it6162_interrupt_handler() drm_bridge_hpd_notify() drm_bridge_connector_hpd_cb() drm_kms_helper_connector_hotplug_event() drm_client_dev_hotplug() drm_helper_probe_single_connector_modes() it6162_bridge_read_edid() it6162_get_edid_block() it6162_infoblock_request_data() wait_event_timeout(it6162->data_buf_wait, ...) Because this runs on the same IRQF_ONESHOT thread that is supposed to wake data_buf_wait, wait_event_timeout() will always stall for TIMEOUT_INFOBLOCK_MS (1800 ms) and fail with -ETIMEDOUT. Similarly, if another thread holds dev->mode_config.mutex and calls it6162_bridge_read_edid() -> it6162_infoblock_request_data() while it6162_interrupt_handler() processes EVENT_CHG and calls drm_bridge_hpd_notify(), the IRQ thread will block waiting for dev->mode_config.mutex and never process the buffer-ready interrupt to wake data_buf_wait. [ ... ] > +static int it6162_attach_dsi(struct it6162 *it6162) > +{ > + struct device *dev = it6162->dev; > + struct device_node *np = dev->of_node; > + const struct mipi_dsi_device_info info = {"it6162-mipi", 0, np}; > + struct mipi_dsi_device *dsi; > + struct mipi_dsi_host *host; > + struct it6162_mipi_cfg *mipi_cfg = &it6162->mipi_cfg; > + int ret = 0; > + > + it6162->dsi = NULL; > + for (int port = 0; port < 2; port++) { > + host = it6162_of_get_dsi_host_by_port(it6162, port); > + if (IS_ERR(host)) > + continue; > + > + mipi_cfg->en_port[port] = true; > + > + dsi = devm_mipi_dsi_device_register_full(dev, host, &info); [Severity: High] Does passing np in mipi_dsi_device_info without taking a reference underflow the OF node refcount of dev->of_node on teardown? devm_mipi_dsi_device_register_full() calls mipi_dsi_device_register_full(), which assigns dsi->dev.of_node = info->node via device_set_node() without calling of_node_get(). When the DSI device is released on probe failure or driver unbind, mipi_dsi_dev_release() unconditionally calls: of_node_put(dev->of_node); Because no matching reference was acquired for each registered DSI device (one in single-DSI mode, two in dual-DSI mode), this drops references owned by the I2C client's device_node. [ ... ] > +static int it6162_bridge_attach(struct drm_bridge *bridge, > + struct drm_encoder *encoder, > + enum drm_bridge_attach_flags flags) > +{ > + struct it6162 *it6162 = bridge_to_it6162(bridge); > + struct drm_device *drm = bridge->dev; > + > + it6162->drm = drm; > + if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { > + drm_dbg(drm, "it6162 driver only copes with atomic updates"); > + return -EOPNOTSUPP; > + } > + > + return 0; > +} [Severity: High] Should it6162_bridge_attach() check DRM_BRIDGE_ATTACH_NO_CONNECTOR and attach the downstream HDMI output bridge from port@3? In it6162_bridge_attach(), the flags parameter is ignored: the function neither requires DRM_BRIDGE_ATTACH_NO_CONNECTOR nor creates a connector. In addition, the device tree binding defines port@3 as the HDMI output port (typically connected to an hdmi-connector node), but it6162_probe() only checks ports 0, 1, and 2, and never acquires or attaches the next bridge on port@3. > + > +static enum drm_mode_status > +it6162_bridge_mode_valid(struct drm_bridge *bridge, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + unsigned long long rate; > + > + rate = drm_hdmi_compute_mode_clock(mode, 8, DRM_OUTPUT_COLOR_FORMAT_RGB444); > + if (rate == 0) > + return MODE_NOCLOCK; > + > + return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate); > +} [ ... ] > +static enum drm_mode_status > +it6162_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, > + const struct drm_display_mode *mode, > + unsigned long long tmds_rate) > +{ > + /*IT6162 hdmi supports HDMI2.0 600Mhz*/ > + if (tmds_rate > 600000000) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} [Severity: Medium] Should it6162_hdmi_tmds_char_rate_valid() or it6162_bridge_mode_valid() also limit the maximum rate when only a single MIPI DSI port is enabled? The commit description notes that single MIPI DSI input supports up to 4K @ 30Hz (~300 MHz) while dual MIPI DSI input is required for 4K @ 60Hz (600 MHz), but it6162_hdmi_tmds_char_rate_valid() allows up to 600 MHz without checking whether both ports in mipi_cfg.en_port[] are enabled. [ ... ] > +static int it6162_probe(struct i2c_client *client) > +{ [ ... ] > + it6162->bridge.of_node = np; > + it6162->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | > + DRM_BRIDGE_OP_HDMI | DRM_BRIDGE_OP_MODES; > + > + it6162->bridge.type = DRM_MODE_CONNECTOR_HDMIA; > + > + it6162->bridge.vendor = "ITE"; > + it6162->bridge.product = "IT6162"; [Severity: High] Are the bridge.ops flags and HDMI version fields configured as intended here? 1. DRM_BRIDGE_OP_MODES is set in it6162->bridge.ops, which tells drm_bridge_connector to call bridge->funcs->get_modes(). Because it6162_bridge_funcs does not implement .get_modes (it only implements .edid_read), drm_bridge_get_modes() will dereference a NULL function pointer: if (!(bridge->ops & DRM_BRIDGE_OP_MODES)) return 0; return bridge->funcs->get_modes(bridge, connector); 2. it6162_interrupt_handler() calls drm_bridge_hpd_notify(), but DRM_BRIDGE_OP_HPD is not set in it6162->bridge.ops, so drm_bridge_connector never registers an HPD callback on this bridge and drm_bridge_hpd_notify() is a no-op. 3. it6162_bridge_funcs implements .hdmi_write_spd_infoframe and .hdmi_clear_spd_infoframe, and bridge.vendor and bridge.product are set, but DRM_BRIDGE_OP_HDMI_SPD_INFOFRAME is omitted from it6162->bridge.ops. 4. DRM_BRIDGE_OP_HDMI is set without setting it6162->bridge.supported_hdmi_ver (for example to HDMI_VERSION_2_0), which triggers a DRM_WARN("HDMI bridge misses supported HDMI version\n") in drm_bridge_add(). > + > + if (it6162_of_get_audio(it6162)) { > + it6162->bridge.ops |= DRM_BRIDGE_OP_HDMI_AUDIO; > + it6162->bridge.hdmi_audio_dev = dev; > + it6162->bridge.hdmi_audio_max_i2s_playback_channels = 8; > + it6162->bridge.hdmi_audio_dai_port = 2; > + } > + > + /* > + * devres releases in reverse order: the IRQ is freed and the HDCP > + * works are cancelled before the bridge is removed, which destroys > + * the HPD notification mutex, and before the supplies and the driver > + * mutex are released. > + */ > + ret = devm_drm_bridge_add(dev, &it6162->bridge); > + if (ret) > + return ret; > + > + ret = devm_add_action_or_reset(dev, it6162_cancel_work_action, it6162); > + if (ret) > + return ret; > + > + ret = devm_request_threaded_irq(&client->dev, client->irq, NULL, > + it6162_int_threaded_handler, > + IRQF_TRIGGER_LOW | IRQF_ONESHOT | > + IRQF_NO_AUTOEN, > + "it6162-intp", it6162); > + if (ret) > + return ret; > + > + return it6162_attach_dsi(it6162); > +} [Severity: High] Does registering the bridge and attaching the DSI devices before it6162_hw_start() expose the bridge before the hardware and IRQ are ready? In it6162_probe(), devm_drm_bridge_add() is called before devm_request_threaded_irq() and it6162_attach_dsi(). Then, inside it6162_attach_dsi(), devm_mipi_dsi_attach() is called inside the port loop before it6162_hw_start() runs: it6162_attach_dsi() for (int port = 0; port < 2; port++) { ... devm_mipi_dsi_attach(dev, dsi); } return it6162_hw_start(it6162); When a DSI host's .attach callback binds the DRM pipeline synchronously during devm_mipi_dsi_attach(), the bridge is already active while it6162->hw_ready is still false (causing it6162_bridge_detect() to return connector_status_disconnected) and client->irq is still disabled with IRQF_NO_AUTOEN (causing any EDID read via it6162_infoblock_request_data() to time out). Once it6162_hw_start() subsequently runs, it calls it6162_hw_reset() and resets the chip after the DSI host has attached. Also, in it6162_attach_dsi(), if it6162_load_mipi_pars_from_port() were to return 0, the check: if (ret <= 0) return ret; would return 0 from it6162_probe() without attaching DSI or starting the hardware. Should the MIPI DT parameters be parsed and it6162_hw_start() be completed before publishing the bridge and attaching the DSI host(s)? -- Sashiko AI review · https://sashiko.dev/#/patchset/20261029-upstream-6162-v5-0-8369f9e5afe6@ite.com.tw?part=2 ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-10-29 10:46 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-10-29 10:12 [PATCH v5 0/2] Add ITE IT6162 MIPI DSI to HDMI bridge driver Hermes Wu via B4 Relay 2026-10-29 10:12 ` Hermes Wu 2026-10-29 10:12 ` [PATCH v5 1/2] dt-bindings: display: bridge: Add ITE IT6162 MIPI DSI to HDMI bridge Hermes Wu via B4 Relay 2026-10-29 10:12 ` Hermes Wu 2026-10-29 10:12 ` [PATCH v5 2/2] drm/bridge: Add ITE IT6162 MIPI DSI to HDMI bridge driver Hermes Wu via B4 Relay 2026-10-29 10:12 ` Hermes Wu 2026-10-29 10:46 ` sashiko-bot
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